├── CA1-Rat In Maze ├── adder.v ├── controller.v ├── datapath.v ├── description │ └── CA#01.pdf ├── map │ └── map.txt ├── mazeMemory.v ├── mux2To1.v ├── ratInMaze.v ├── ratInMazeTB.v ├── reg4B.v ├── report │ └── ComputerArchitecture-CA1Report.pdf ├── stckQue.v └── twosComplement.v ├── CA2-RISC-V Single-Cycle ├── ALU.v ├── RISCV.v ├── RISCV_TB.v ├── adder32B.v ├── array │ └── array.txt ├── assembly │ └── a_riscv.s ├── controller.v ├── dataMemory.v ├── datapath.v ├── datapath │ └── Datapath.JPG ├── description │ └── CA#02.pdf ├── extend.v ├── instructionMemory.v ├── instructions │ └── instructions.txt ├── mux2To1.v ├── mux4To1.v ├── reg32B.v └── registerFile.v ├── CA3-RISC-V Multi-Cycle ├── ALU.v ├── RISCV.v ├── RISCV_TB.v ├── assembly │ └── a_riscv.s ├── controller.v ├── controller │ ├── controller1.JPG │ ├── controller2.JPG │ └── controller3.JPG ├── data │ └── data.txt ├── datapath.v ├── datapath │ └── Datapath.JPG ├── description │ └── CA#03.pdf ├── extend.v ├── memory.v ├── mux2To1.v ├── mux4To1.v ├── reg32B.v └── registerFile.v ├── CA4-RISC-V Pipeline ├── ALU.v ├── RISCV.v ├── RISCV_TB.v ├── adder32B.v ├── array │ └── array.txt ├── assembly │ └── a_riscv.s ├── controller.v ├── dataMemory.v ├── datapath.v ├── datapath │ └── Datapath.JPG ├── description │ └── CA#04.pdf ├── extend.v ├── hazardUnit.v ├── instructionMemory.v ├── instructions │ └── instructions.txt ├── mux2To1.v ├── mux4To1.v ├── pipeDE.v ├── pipeEM.v ├── pipeFD.v ├── pipeMW.v ├── reg32B.v ├── regPipe.v └── registerFile.v ├── LICENSE └── README.md /CA1-Rat In Maze/adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/HEAD/CA1-Rat In Maze/adder.v -------------------------------------------------------------------------------- /CA1-Rat In Maze/controller.v: -------------------------------------------------------------------------------- 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