├── CA1-Rat In Maze ├── adder.v ├── controller.v ├── datapath.v ├── description │ └── CA#01.pdf ├── map │ └── map.txt ├── mazeMemory.v ├── mux2To1.v ├── ratInMaze.v ├── ratInMazeTB.v ├── reg4B.v ├── report │ └── ComputerArchitecture-CA1Report.pdf ├── stckQue.v └── twosComplement.v ├── CA2-RISC-V Single-Cycle ├── ALU.v ├── RISCV.v ├── RISCV_TB.v ├── adder32B.v ├── array │ └── array.txt ├── assembly │ └── a_riscv.s ├── controller.v ├── dataMemory.v ├── datapath.v ├── datapath │ └── Datapath.JPG ├── description │ └── CA#02.pdf ├── extend.v ├── instructionMemory.v ├── instructions │ └── instructions.txt ├── mux2To1.v ├── mux4To1.v ├── reg32B.v └── registerFile.v ├── CA3-RISC-V Multi-Cycle ├── ALU.v ├── RISCV.v ├── RISCV_TB.v ├── assembly │ └── a_riscv.s ├── controller.v ├── controller │ ├── controller1.JPG │ ├── controller2.JPG │ └── controller3.JPG ├── data │ └── data.txt ├── datapath.v ├── datapath │ └── Datapath.JPG ├── description │ └── CA#03.pdf ├── extend.v ├── memory.v ├── mux2To1.v ├── mux4To1.v ├── reg32B.v └── registerFile.v ├── CA4-RISC-V Pipeline ├── ALU.v ├── RISCV.v ├── RISCV_TB.v ├── adder32B.v ├── array │ └── array.txt ├── assembly │ └── a_riscv.s ├── controller.v ├── dataMemory.v ├── datapath.v ├── datapath │ └── Datapath.JPG ├── description │ └── CA#04.pdf ├── extend.v ├── hazardUnit.v ├── instructionMemory.v ├── instructions │ └── instructions.txt ├── mux2To1.v ├── mux4To1.v ├── pipeDE.v ├── pipeEM.v ├── pipeFD.v ├── pipeMW.v ├── reg32B.v ├── regPipe.v └── registerFile.v ├── LICENSE └── README.md /CA1-Rat In Maze/adder.v: -------------------------------------------------------------------------------- 1 | module adder(a, b, ci, en, co, sum); 2 | #parameter N = 4; 3 | input [N - 1:0] a, b; 4 | input ci, en; 5 | output co; 6 | output [N - 1:0] sum; 7 | assign {co, sum} = en ? a + b + ci: {co, sum}; 8 | endmodule -------------------------------------------------------------------------------- /CA1-Rat In Maze/controller.v: -------------------------------------------------------------------------------- 1 | `define S0 6'd0 2 | `define S1 6'd1 3 | `define S2 6'd2 4 | `define S3 6'd3 5 | `define S4 6'd4 6 | `define S5 6'd5 7 | `define S6 6'd6 8 | `define S7 6'd7 9 | `define S8 6'd8 10 | `define S9 6'd9 11 | `define S10 6'd10 12 | `define S11 6'd11 13 | `define S12 6'd12 14 | `define S13 6'd13 15 | `define S14 6'd14 16 | `define S15 6'd15 17 | 18 | module controller(clk, rst, start, cntReach, empStck, dIn, nxtLoc, curLoc, 19 | wr, rd, fail, done, dir, rgLd, pop, push, dOut, adderEn, giveTMem); 20 | 21 | input clk, rst, start, cntReach, empStck , dIn; 22 | input [7:0] nxtLoc, curLoc; 23 | 24 | output wr, rd, fail, done, dir, rgLd, pop, push, dOut, adderEn; 25 | output reg [7:0] giveTMem; 26 | 27 | wire isDestination = &nxtLoc; 28 | 29 | reg [3:0] ns, ps; 30 | reg [1:0] dir = 2'b0; 31 | reg rgLd, wr, dOut, noDir, rd, push, pop, fail, done, adderEn; 32 | 33 | always @(posedge clk, posedge rst) begin 34 | if (rst) 35 | ps <= `S0; 36 | else 37 | ps <= ns; 38 | end 39 | 40 | always @(ps, start, isDestination, cntReach, noDir, dIn, empStck) begin 41 | case (ps) 42 | `S0 : ns = start? `S1: `S0; 43 | `S1 : ns = `S2; 44 | `S2 : ns = `S3; 45 | `S3 : ns = isDestination? `S12: `S6; 46 | `S4 : ns = noDir? `S8: `S13; 47 | `S5 : ns = dIn? `S4: `S7; 48 | `S6 : ns = cntReach? `S4: `S5; 49 | `S7 : ns = `S1; 50 | `S8 : ns = empStck? `S10: `S9; 51 | `S9 : ns = `S1; 52 | `S10: ns = `S11; 53 | `S11: ns = `S0; 54 | `S12: ns = `S15; 55 | `S13: ns = cntReach? `S4: `S5; 56 | `S14: ns = empStck? `S0: `S14; 57 | `S15: ns = `S14; 58 | default: ns = `S0; 59 | endcase 60 | end 61 | 62 | always @(ps) begin 63 | {rgLd, wr, dOut, rd, push, pop, fail, done, adderEn} = 10'b0; 64 | case(ps) 65 | `S1: rgLd = 1'b1; 66 | `S3: begin 67 | giveTMem = curLoc; 68 | wr = 1'b1; 69 | dOut = 1'b0; 70 | end 71 | `S4: begin 72 | {noDir, dir} = dir + 1; 73 | adderEn = 1'b1; 74 | giveTMem = nxtLoc; 75 | end 76 | `S5: begin 77 | rd = 1'b1; 78 | giveTMem = nxtLoc; 79 | end 80 | `S6: begin 81 | noDir = 1'b0; 82 | dir = 2'b00; 83 | adderEn = 1'b1; 84 | end 85 | `S7: begin 86 | giveTMem = curLoc; 87 | wr = 1'b1; 88 | dOut = 1'b1; 89 | push = 1'b1; 90 | end 91 | `S8: begin 92 | giveTMem = curLoc; 93 | wr = 1'b1; 94 | dOut = 1'b1; 95 | end 96 | `S9: pop = 1'b1; 97 | `S10: fail = 1'b1; 98 | `S12: push = 1'b1; 99 | `S14: pop = 1'b1; 100 | `S15: done = 1'b1; 101 | endcase 102 | end 103 | endmodule -------------------------------------------------------------------------------- /CA1-Rat In Maze/datapath.v: -------------------------------------------------------------------------------- 1 | module datapath(clk, rst, rgLd, dir, push, pop, done, run, adderEn, 2 | cntReach, empStck, nxtLoc, curLoc, move); 3 | input clk, rst, rgLd, push, pop, done, run, adderEn; 4 | input [1:0] dir; 5 | output [7:0] nxtLoc, curLoc, move; 6 | output cntReach, empStck; 7 | 8 | wire sl, co, muxSl1, muxSl2; 9 | wire [3:0] res, toAdd, addTo, tmp, negOne; 10 | wire [7:0] popedLoc, mux1Out, mux2Out, mux3Out, inMux1, inMux2; 11 | 12 | 13 | assign tmp = addTo + dir[0]; 14 | assign sl = ^dir; 15 | assign toAdd = dir[0]? 4'b1: negOne; 16 | assign cntReach = (tmp == 4'b0); 17 | assign addTo = sl? curLoc[7:4]: curLoc[3:0]; 18 | assign muxSl1 = adderEn && ~sl; 19 | assign muxSl2 = adderEn && sl; 20 | assign inMux1 = {curLoc[7:4], res}; 21 | assign inMux2 = {res, curLoc[3:0]}; 22 | 23 | twosComplement neg1(.in(4'b1), .out(negOne)); 24 | 25 | mux2To1 mux1(.in0(nxtLoc), .in1(inMux1), .sl(muxSl1), .out(mux1Out)); 26 | mux2To1 mux2(.in0(mux1Out), .in1(inMux2), .sl(muxSl2), .out(mux2Out)); 27 | mux2To1 mux3(.in0(mux2Out), .in1(popedLoc), .sl(pop), .out(mux3Out)); 28 | mux2To1 mux4(.in0(mux3Out), .in1(8'h00), .sl(rst), .out(nxtLoc)); 29 | 30 | reg4B xLoc(.clk(clk), .rst(rst), .ld(rgLd), .dataIn(nxtLoc[7:4]), .dataOut(curLoc[7:4])); 31 | reg4B yLoc(.clk(clk), .rst(rst), .ld(rgLd), .dataIn(nxtLoc[3:0]), .dataOut(curLoc[3:0])); 32 | 33 | adder add(.a(addTo), .b(toAdd), .ci(1'b0), .en(adderEn), .co(co), .sum(res)); 34 | stckQue stkQ(.clk(clk), .rst(rst), .locIn(curLoc), .push(push), .pop(pop), 35 | .done(done), .run(run), .locOut(popedLoc), .move(move), .empStck(empStck)); 36 | 37 | always @(curLoc) begin 38 | $display("Mouse Location --> X:%d Y:%d", curLoc[7:4], curLoc[3:0]); 39 | end 40 | endmodule -------------------------------------------------------------------------------- /CA1-Rat In Maze/description/CA#01.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA1-Rat In Maze/description/CA#01.pdf -------------------------------------------------------------------------------- /CA1-Rat In Maze/map/map.txt: -------------------------------------------------------------------------------- 1 | 00C7 2 | 6EDF 3 | 6E1C 4 | 7FFD 5 | 01FD 6 | B500 7 | B17D 8 | BF7D 9 | BC71 10 | 8747 11 | B777 12 | 307F 13 | BF77 14 | 8330 15 | B7F6 16 | B006 -------------------------------------------------------------------------------- /CA1-Rat In Maze/mazeMemory.v: -------------------------------------------------------------------------------- 1 | module mazeMemory(clk, loc, dIn, rd, wr, dOut); 2 | input clk, dIn, rd, wr; 3 | input [7:0] loc; 4 | output dOut; 5 | 6 | reg [3:0] x, y; 7 | reg [0:15] map [0:15]; 8 | reg dOut; 9 | 10 | initial begin 11 | $readmemh("map.txt", map); 12 | end 13 | 14 | always @(posedge clk, posedge rd) begin 15 | dOut <= 1'b0; 16 | {y, x} = loc; 17 | 18 | if (rd) begin 19 | dOut <= map[x][y]; 20 | end 21 | 22 | else if (wr) begin 23 | map[x][y] <= dIn; 24 | end 25 | end 26 | endmodule -------------------------------------------------------------------------------- /CA1-Rat In Maze/mux2To1.v: -------------------------------------------------------------------------------- 1 | module mux2To1(in0, in1, sl, out); 2 | input [7:0] in0, in1; 3 | input sl; 4 | output [7:0] out; 5 | 6 | assign out = (sl == 1'b0) ? in0 : in1; 7 | endmodule -------------------------------------------------------------------------------- /CA1-Rat In Maze/ratInMaze.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module ratInMaze(clk, rst, start, run, fail, done, move); 4 | input clk, rst, start, run; 5 | output fail, done; 6 | output [7:0] move; 7 | 8 | wire [7:0] cLoc, nLoc, gTMem; 9 | wire [1:0] dir; 10 | wire pop, push, empStck, rgLd, cntRch, rd, wr, wriM, rdfM, addEn; 11 | 12 | controller cntrllr(.clk(clk), .rst(rst), .start(start), .cntReach(cntRch), .empStck(empStck), 13 | .dIn(rdfM), .nxtLoc(nLoc), .curLoc(cLoc), .wr(wr), .rd(rd), .fail(fail), 14 | .done(done), .dir(dir), .rgLd(rgLd), .pop(pop), .push(push), .dOut(wriM), 15 | .adderEn(addEn), .giveTMem(gTMem)); 16 | 17 | datapath dtpth(.clk(clk), .rst(rst), .rgLd(rgLd), .dir(dir), .push(push), .pop(pop), 18 | .done(done), .run(run), .adderEn(addEn), .cntReach(cntRch), 19 | .empStck(empStck), .nxtLoc(nLoc), .curLoc(cLoc), .move(move)); 20 | 21 | mazeMemory mzmmr(.clk(clk), .loc(gTMem), .dIn(wriM), .rd(rd), .wr(wr),.dOut(rdfM)); 22 | endmodule -------------------------------------------------------------------------------- /CA1-Rat In Maze/ratInMazeTB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module ratInMazeTB(); 4 | reg _clk = 1'b0; 5 | reg _rst = 1'b0; 6 | reg _start = 1'b0; 7 | reg _run = 1'b0; 8 | wire _fail, _done; 9 | wire [7:0] _move; 10 | 11 | ratInMaze rtInMz (.clk(_clk), .rst(_rst), .start(_start), .run(_run), .fail(_fail), .done(_done), .move(_move)); 12 | 13 | always #5 _clk <= ~_clk; 14 | initial begin 15 | #2; 16 | _rst = 1'b1; 17 | #4; 18 | _rst = 1'b0; 19 | _start = 1'b1; 20 | #12; 21 | _start = 1'b0; 22 | #35000; 23 | _run = 1'b1; 24 | #800 $stop; 25 | end 26 | endmodule -------------------------------------------------------------------------------- /CA1-Rat In Maze/reg4B.v: -------------------------------------------------------------------------------- 1 | module reg4B(clk, rst, ld, dataIn, dataOut); 2 | input clk, rst, ld; 3 | input [3:0] dataIn; 4 | output [3:0] dataOut; 5 | reg [3:0] savedData; 6 | 7 | always @(posedge clk, posedge rst) begin 8 | if (rst) begin 9 | savedData <= 4'h0; 10 | end 11 | 12 | else if (ld) begin 13 | savedData <= dataIn; 14 | end 15 | 16 | else 17 | savedData <= dataOut; 18 | end 19 | 20 | assign dataOut = savedData; 21 | endmodule -------------------------------------------------------------------------------- /CA1-Rat In Maze/report/ComputerArchitecture-CA1Report.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA1-Rat In Maze/report/ComputerArchitecture-CA1Report.pdf -------------------------------------------------------------------------------- /CA1-Rat In Maze/stckQue.v: -------------------------------------------------------------------------------- 1 | `define STACK 1'b0 2 | `define QUEUE 1'b1 3 | 4 | module stckQue(clk, rst, locIn, push, pop, done, run, locOut, move, empStck); 5 | input clk, rst, push, pop, done, run; 6 | input [7:0] locIn; 7 | output [7:0] locOut; 8 | output reg [7:0] move; 9 | output empStck; 10 | 11 | reg [7:0] headPointer = 8'b0; 12 | reg [7:0] mainPointer = 8'b0; 13 | reg pPopType = `STACK; 14 | 15 | assign empStck = (pPopType == `STACK)? (headPointer == 8'b0): (mainPointer == headPointer); 16 | 17 | reg [7:0] stackMem [0:255]; 18 | reg [7:0] locOut; 19 | integer i; 20 | 21 | always @(posedge clk, posedge rst) begin 22 | if (done) begin 23 | pPopType = `QUEUE; 24 | mainPointer = 8'b1; 25 | $display("--Done signal activated--"); 26 | end 27 | 28 | else begin 29 | if (rst) begin 30 | headPointer = 8'b0; 31 | mainPointer = 8'b0; 32 | pPopType = `STACK; 33 | for (i = 0; i < 256; i = i + 1) 34 | stackMem[i] <= 8'h00; 35 | end 36 | 37 | else if (push) begin 38 | headPointer = headPointer + 1; 39 | mainPointer = headPointer; 40 | stackMem[mainPointer] = locIn; 41 | end 42 | 43 | else if (pop && headPointer > 0 && pPopType == `QUEUE && run) begin 44 | locOut = stackMem[mainPointer]; 45 | mainPointer = mainPointer + 1; 46 | move = locOut; 47 | $display("Path --> X:%d Y:%d", locOut[7:4], locOut[3:0]); 48 | end 49 | 50 | else if (pop && headPointer > 0 && pPopType == `STACK) begin 51 | locOut = stackMem[mainPointer]; 52 | headPointer = headPointer - 1; 53 | mainPointer = headPointer; 54 | end 55 | end 56 | end 57 | endmodule -------------------------------------------------------------------------------- /CA1-Rat In Maze/twosComplement.v: -------------------------------------------------------------------------------- 1 | module twosComplement(in, out); 2 | input [3:0] in; 3 | output [3:0] out; 4 | 5 | assign out = ~in + 4'b1; 6 | endmodule -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/ALU.v: -------------------------------------------------------------------------------- 1 | `define ALU_SUB 3'b001 2 | `define ALU_ADD 3'b000 3 | `define ALU_XOR 3'b100 4 | `define ALU_AND 3'b010 5 | `define ALU_OR 3'b011 6 | `define ALU_SLT 3'b101 7 | 8 | module ALU(in1, in2, sl, out, zero, sign); 9 | input [31:0] in1, in2; 10 | input [2:0] sl; 11 | output zero, sign; 12 | output reg [31:0] out; 13 | 14 | always @(in1, in2, sl) begin 15 | out = 32'b0; 16 | case (sl) 17 | `ALU_ADD: 18 | out = in1 + in2; 19 | `ALU_SUB: 20 | out = in1 - in2; 21 | `ALU_AND: 22 | out = in1 & in2; 23 | `ALU_OR: 24 | out = in1 | in2; 25 | `ALU_XOR: 26 | out = in1 ^ in2; 27 | `ALU_SLT: 28 | out = (in1 < in2 ? 32'd1 : 32'd0); 29 | default: 30 | out = 32'b0; 31 | endcase 32 | end 33 | 34 | assign zero = (out == 32'b0); 35 | assign sign = (out[31]); 36 | endmodule -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/RISCV.v: -------------------------------------------------------------------------------- 1 | module RISCV(clk, rst); 2 | input clk, rst; 3 | wire zero; 4 | wire [6:0] op, funct7; 5 | wire [2:0] funct3; 6 | wire RegWrite, ALUSrc, MemWrite, ALUResSign; 7 | wire [1:0] ResultSrc, PCSrc; 8 | wire [2:0] ALUControl, ImmSrc; 9 | 10 | datapath dPath(.clk(clk), .rst(rst), .MemWrite(MemWrite), .ALUSrc(ALUSrc), 11 | .RegWrite(RegWrite), .PCSrc(PCSrc), .ResultSrc(ResultSrc), 12 | .ImmSrc(ImmSrc), .ALUControl(ALUControl), .Zero(zero), .ALUResSign(ALUResSign), 13 | .funct3(funct3), .funct7(funct7), .op(op)); 14 | 15 | controller cntrller(.Zero(zero), .ALUResSign(ALUResSign), .funct3(funct3), .funct7(funct7), 16 | .op(op), .MemWrite(MemWrite), .ALUSrc(ALUSrc), .RegWrite(RegWrite), 17 | .PCSrc(PCSrc), .ResultSrc(ResultSrc), .ImmSrc(ImmSrc), .ALUControl(ALUControl)); 18 | endmodule 19 | -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/RISCV_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module RISCV_TB(); 4 | reg clk, rst; 5 | 6 | RISCV cpu(clk, rst); 7 | 8 | always #5 clk <= ~clk; 9 | 10 | initial begin 11 | clk = 1'b0; 12 | rst = 1'b1; 13 | #10 rst = 1'b0; 14 | 15 | #1100 $stop; 16 | end 17 | endmodule -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/adder32B.v: -------------------------------------------------------------------------------- 1 | module adder32B(in1, in2, sum, c); 2 | input [31:0] in1, in2; 3 | output [31:0] sum; 4 | output c; 5 | assign {c, sum} = in1 + in2; 6 | endmodule -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/array/array.txt: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000101 2 | 00000000000000000000000000011110 3 | 00000000000000000000000000011100 4 | 00000000000000000000000000001000 5 | 00000000000000000000000000010001 6 | 00000000000000000000000001100011 7 | 00000000000000000000000010111101 8 | 00000000000000000000000000000011 9 | 00000000000000000000000001010111 10 | 00000000000000000000000000001111 -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/assembly/a_riscv.s: -------------------------------------------------------------------------------- 1 | # int i = 0; 2 | # int max = 0l 3 | # for (i = 0; i < 10; i++) 4 | // if (max < A[i]) 5 | # max = A[i] 6 | 7 | # i <- x6 8 | # A[i] <- x9 9 | # max <- x8 10 | 11 | add x6,x0,x0 12 | addi x8,x0,0 13 | 14 | LOOP: slti x7,x6,40 15 | beq x7,x0,END_LOOP 16 | lw x9,0(x6) 17 | 18 | IF: slt x1,x8,x9 19 | beq x1,x0, END_IF 20 | add x8,x0,x9 21 | 22 | END_IF: addi x6,x6,4 23 | j LOOP 24 | 25 | END_LOOP: 26 | -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/controller.v: -------------------------------------------------------------------------------- 1 | `define LW 7'b0000011 2 | `define SW 7'b0100011 3 | `define BRANCH 7'b1100011 4 | `define LUI 7'b0110111 5 | `define JALR 7'b1100111 6 | `define JAL 7'b1101111 7 | `define ADDI 7'b0010011 8 | `define ADD 7'b0110011 9 | `define BEQ 3'b000 10 | `define BNE 3'b001 11 | `define BLT 3'b100 12 | `define BGE 3'b101 13 | `define I_TYPE 3'b000 14 | `define S_TYPE 3'b001 15 | `define B_TYPE 3'b010 16 | `define U_TYPE 3'b100 17 | `define J_TYPE 3'b011 18 | `define ADD_FUN3 3'b000 19 | `define ADD_FUN7 7'b0000000 20 | `define ADDI_FUN3 3'b000 21 | `define SUB_FUN3 3'b000 22 | `define SUB_FUN7 7'b0100000 23 | `define XOR_FUN3 3'b100 24 | `define AND_FUN3 3'b111 25 | `define OR_FUN3 3'b110 // or ORI_FUN3 26 | `define SLT_FUN3 3'b010 // or SLTI_FUN3 27 | `define ALU_SUB 3'b001 28 | `define ALU_ADD 3'b000 29 | `define ALU_XOR 3'b100 30 | `define ALU_AND 3'b010 31 | `define ALU_OR 3'b011 32 | `define ALU_SLT 3'b101 33 | `define PC_PLUS_4 2'b00 34 | `define PC_PLUS_IMM 2'b01 35 | `define PC_PLUS_JADR 2'b10 36 | 37 | module controller(Zero, ALUResSign, funct3, funct7, op, 38 | MemWrite, ALUSrc, RegWrite, PCSrc, ResultSrc, ImmSrc, ALUControl); 39 | input Zero, ALUResSign; 40 | input [2:0] funct3; 41 | input [6:0] funct7, op; 42 | 43 | output reg MemWrite, ALUSrc, RegWrite; 44 | output reg [1:0] PCSrc, ResultSrc; 45 | output reg [2:0] ALUControl, ImmSrc; 46 | reg [1:0] ALUOp; 47 | 48 | always @(op, funct3, funct7) begin 49 | {PCSrc, ResultSrc, MemWrite, ALUControl, ALUSrc, ImmSrc, RegWrite, ALUOp} = 15'b0; 50 | case (op) 51 | `LW: begin 52 | ALUSrc = 1'b1; 53 | ImmSrc = `I_TYPE; 54 | ALUOp = 2'b00; 55 | ResultSrc = 2'b01; 56 | RegWrite = 1'b1; 57 | end 58 | 59 | `ADDI: begin 60 | ALUSrc = 1'b1; 61 | ImmSrc = `I_TYPE; 62 | ALUOp = 2'b10; 63 | ResultSrc = 2'b00; 64 | RegWrite = 1'b1; 65 | end 66 | 67 | `SW: begin 68 | ALUSrc = 1'b1; 69 | ImmSrc = `S_TYPE; 70 | ALUOp = 2'b00; 71 | MemWrite = 1'b1; 72 | end 73 | 74 | `BRANCH: begin 75 | ALUSrc = 1'b1; 76 | ImmSrc = `B_TYPE; 77 | ALUOp = 2'b01; 78 | if (funct3 == `BEQ) 79 | PCSrc = Zero ? `PC_PLUS_IMM : `PC_PLUS_4; 80 | 81 | else if (funct3 == `BNE) 82 | PCSrc = ~Zero ? `PC_PLUS_IMM : `PC_PLUS_4; 83 | 84 | else if (funct3 == `BLT) 85 | PCSrc = ALUResSign ? `PC_PLUS_IMM : `PC_PLUS_4; 86 | 87 | else if (funct3 == `BGE) 88 | PCSrc = ~ALUResSign ? `PC_PLUS_IMM : `PC_PLUS_4; 89 | end 90 | 91 | `ADD: begin 92 | RegWrite = 1'b1; 93 | ALUOp = 2'b10; 94 | end 95 | 96 | `LUI: begin 97 | RegWrite = 1'b1; 98 | ResultSrc = 2'b11; 99 | ImmSrc = `U_TYPE; 100 | end 101 | 102 | `JALR: begin 103 | ALUSrc = 1'b1; 104 | RegWrite = 1'b1; 105 | PCSrc = 2'b10; 106 | ResultSrc = 2'b10; 107 | ImmSrc = `I_TYPE; 108 | ALUOp = 2'b00; 109 | end 110 | 111 | `JAL: begin 112 | ALUSrc = 1'b1; 113 | RegWrite = 1'b1; 114 | PCSrc = 2'b01; 115 | ResultSrc = 2'b10; 116 | ImmSrc = `J_TYPE; 117 | ALUOp = 2'b00; 118 | end 119 | 120 | default: begin 121 | {PCSrc, ResultSrc, MemWrite, ALUControl, ALUSrc, ImmSrc, RegWrite, ALUOp} = 15'b0; 122 | end 123 | endcase 124 | end 125 | 126 | always @(ALUOp) begin 127 | case (ALUOp) 128 | 2'b00: 129 | ALUControl = `ALU_ADD; 130 | 2'b01: 131 | ALUControl = `ALU_SUB; 132 | 2'b10: begin 133 | if (funct3 == `ADDI_FUN3 && op == `ADDI) 134 | ALUControl = `ALU_ADD; 135 | 136 | if (funct3 == `ADD_FUN3 && funct7 == `ADD_FUN7) 137 | ALUControl = `ALU_ADD; 138 | 139 | if (funct3 == `SUB_FUN3 && funct7 == `SUB_FUN7) 140 | ALUControl = `ALU_SUB; 141 | 142 | if (funct3 == `XOR_FUN3) 143 | ALUControl = `ALU_XOR; 144 | 145 | if (funct3 == `AND_FUN3) 146 | ALUControl = `ALU_AND; 147 | 148 | if (funct3 == `OR_FUN3) 149 | ALUControl = `ALU_OR; 150 | 151 | if (funct3 == `SLT_FUN3) 152 | ALUControl = `ALU_SLT; 153 | end 154 | endcase 155 | end 156 | endmodule 157 | -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/dataMemory.v: -------------------------------------------------------------------------------- 1 | module dataMemory(clk, rst, A, WE, WD, RD); 2 | input clk, rst; 3 | input [31:0] A; 4 | input WE; 5 | input [31:0] WD; 6 | output [31:0] RD; 7 | wire [31:0] address; 8 | integer i; 9 | 10 | reg [31:0] memory [0:16384]; 11 | 12 | initial begin 13 | $readmemb("array.txt", memory); 14 | end 15 | 16 | assign address = {2'b0, A[31:2]}; 17 | 18 | always @(posedge clk, posedge rst) begin 19 | if (WE) begin 20 | memory[address] <= WD; 21 | end 22 | end 23 | 24 | assign RD = memory[address]; 25 | endmodule -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/datapath.v: -------------------------------------------------------------------------------- 1 | module datapath(clk, rst, MemWrite, ALUSrc, RegWrite, PCSrc, ResultSrc, ImmSrc, ALUControl, 2 | Zero, ALUResSign, funct3, funct7, op); 3 | input clk, rst; 4 | input MemWrite, ALUSrc, RegWrite; 5 | input [1:0] PCSrc, ResultSrc; 6 | input [2:0] ALUControl, ImmSrc; 7 | 8 | output Zero, ALUResSign; 9 | output [2:0] funct3; 10 | output [6:0] funct7, op; 11 | 12 | wire [31:0] PCOut, PCNext, PCPlus4, Instr, SrcA, preSrcB, SrcB, ImmExt, 13 | ALUResult, PCTarget, MemReadData, RFWriteData; 14 | wire co1, co2; 15 | 16 | mux4To1 PCInMux(.in0(PCPlus4), .in1(PCTarget), .in2(ALUResult), .in3(32'bx), .sl(PCSrc), .out(PCNext)); 17 | reg32B PC(.clk(clk), .rst(rst), .dataIn(PCNext), .dataOut(PCOut)); 18 | instructionMemory InstructionMem(.A(PCOut), .RD(Instr)); 19 | adder32B PCIncrementBy4(.in1(PCOut), .in2(32'd4), .sum(PCPlus4), .c(co1)); 20 | registerFile RegFile(.clk(clk), .rst(rst), .A1(Instr[19:15]), .A2(Instr[24:20]), .A3(Instr[11:7]), 21 | .WE(RegWrite), .WD(RFWriteData), .RD1(SrcA), .RD2(preSrcB)); 22 | extend immExtend(.inst(Instr[31:7]), .sl(ImmSrc), .out(ImmExt)); 23 | mux2To1 ALUSrc2Mux(.in0(preSrcB), .in1(ImmExt), .sl(ALUSrc), .out(SrcB)); 24 | ALU mainALU(.in1(SrcA), .in2(SrcB), .sl(ALUControl), .out(ALUResult), .zero(Zero), .sign(ALUResSign)); 25 | adder32B PCAdd(.in1(PCOut), .in2(ImmExt), .sum(PCTarget), .c(co2)); 26 | dataMemory DataMem(.clk(clk), .rst(rst), .A(ALUResult), .WE(MemWrite), .WD(preSrcB), .RD(MemReadData)); 27 | mux4To1 RegFileWDMux(.in0(ALUResult), .in1(MemReadData), .in2(PCPlus4), .in3(ImmExt), .sl(ResultSrc), .out(RFWriteData)); 28 | 29 | assign op = Instr[6:0]; 30 | assign funct3 = Instr[14:12]; 31 | assign funct7 = Instr[31:25]; 32 | 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/datapath/Datapath.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA2-RISC-V Single-Cycle/datapath/Datapath.JPG -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/description/CA#02.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA2-RISC-V Single-Cycle/description/CA#02.pdf -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/extend.v: -------------------------------------------------------------------------------- 1 | module extend(inst, sl, out); 2 | input [31:7] inst; 3 | input [2:0] sl; 4 | output [31:0] out; 5 | 6 | assign out = 7 | sl == 3'b000 ? {{21{inst[31]}}, inst[30:20]} : // I-Type 8 | sl == 3'b001 ? {{21{inst[31]}}, inst[30:25], inst[11:7]} : // S-Type 9 | sl == 3'b010 ? {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0} : // B-Type 10 | sl == 3'b100 ? {inst[31], inst[30:20], inst[19:12], 12'b0} : // U-Type 11 | sl == 3'b011 ? {{12{inst[31]}}, inst[19:12], inst[20], inst[30:25], inst[24:21], 1'b0} : // J-Type 12 | 32'bx; 13 | endmodule -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/instructionMemory.v: -------------------------------------------------------------------------------- 1 | module instructionMemory(A, RD); 2 | input [31:0] A; 3 | output [31:0] RD; 4 | wire [31:0] address; 5 | 6 | reg [31:0] memory [0:16384]; // 2^14 7 | 8 | initial begin 9 | $readmemb("instructions.txt", memory); 10 | end 11 | 12 | assign address = {2'b0, A[31:2]}; 13 | assign RD = memory[address]; 14 | endmodule -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/instructions/instructions.txt: -------------------------------------------------------------------------------- 1 | 00000000000000000000001100110011 2 | 00000000000000000000010000010011 3 | 00000010100000110010001110010011 4 | 00000000000000111000111001100011 5 | 00000000000000110010010010000011 6 | 00000000100101000010000010110011 7 | 00000000000000001000010001100011 8 | 00000000100100000000010000110011 9 | 00000000010000110000001100010011 10 | 11111110010111111111000001101111 -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/mux2To1.v: -------------------------------------------------------------------------------- 1 | module mux2To1(in0, in1, sl, out); 2 | input [31:0] in0, in1; 3 | input sl; 4 | output [31:0] out; 5 | 6 | assign out = sl ? in1 : in0; 7 | endmodule -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/mux4To1.v: -------------------------------------------------------------------------------- 1 | module mux4To1(in0, in1, in2, in3, sl, out); 2 | input [31:0] in0, in1, in2, in3; 3 | input [1:0] sl; 4 | output [31:0] out; 5 | 6 | assign out = 7 | sl == 2'b00 ? in0 : 8 | sl == 2'b01 ? in1 : 9 | sl == 2'b10 ? in2 : 10 | sl == 2'b11 ? in3 : 11 | 32'bx; 12 | endmodule 13 | -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/reg32B.v: -------------------------------------------------------------------------------- 1 | module reg32B(clk, rst, dataIn, dataOut); 2 | input clk, rst; 3 | input [31:0] dataIn; 4 | output [31:0] dataOut; 5 | reg [31:0] savedData; 6 | 7 | always @(posedge clk, posedge rst) begin 8 | if (rst) begin 9 | savedData = 32'b0; 10 | end 11 | else begin 12 | savedData = dataIn; 13 | end 14 | end 15 | 16 | assign dataOut = savedData; 17 | endmodule -------------------------------------------------------------------------------- /CA2-RISC-V Single-Cycle/registerFile.v: -------------------------------------------------------------------------------- 1 | module registerFile(clk, rst, A1, A2, A3, WE, WD, RD1, RD2); 2 | input clk, rst; 3 | input [19:15] A1; 4 | input [24:20] A2; 5 | input [11:7] A3; 6 | input WE; 7 | input [31:0] WD; 8 | output [31:0] RD1, RD2; 9 | integer i; 10 | 11 | reg [31:0] registers [0:31]; 12 | initial begin 13 | registers[0] <= 32'b0; // ZERO register 14 | end 15 | 16 | always @(posedge clk, posedge rst) begin 17 | if (rst) begin 18 | for (i = 0; i < 32; i = i + 1) 19 | registers[i] <= 32'b0; 20 | end 21 | else if (WE && A3 != 5'b0) begin 22 | registers[A3] <= WD; 23 | end 24 | end 25 | 26 | assign RD1 = registers[A1]; 27 | assign RD2 = registers[A2]; 28 | endmodule -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/ALU.v: -------------------------------------------------------------------------------- 1 | `define ALU_SUB 3'b001 2 | `define ALU_ADD 3'b000 3 | `define ALU_XOR 3'b100 4 | `define ALU_AND 3'b010 5 | `define ALU_OR 3'b011 6 | `define ALU_SLT 3'b101 7 | 8 | module ALU(in1, in2, sl, out, zero, sign); 9 | input [31:0] in1, in2; 10 | input [2:0] sl; 11 | output zero, sign; 12 | output reg [31:0] out; 13 | 14 | always @(in1, in2, sl) begin 15 | out = 32'b0; 16 | case (sl) 17 | `ALU_ADD: 18 | out = in1 + in2; 19 | `ALU_SUB: 20 | out = in1 - in2; 21 | `ALU_AND: 22 | out = in1 & in2; 23 | `ALU_OR: 24 | out = in1 | in2; 25 | `ALU_XOR: 26 | out = in1 ^ in2; 27 | `ALU_SLT: 28 | out = (in1 < in2 ? 32'd1 : 32'd0); 29 | default: 30 | out = 32'b0; 31 | endcase 32 | end 33 | 34 | assign zero = (out == 32'b0); 35 | assign sign = (out[31]); 36 | endmodule -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/RISCV.v: -------------------------------------------------------------------------------- 1 | module RISCV(clk, rst); 2 | input clk, rst; 3 | wire PCWrite, AdrSrc, MemWrite, IRWrite, RegWrite; 4 | wire [1:0] ResultSrc, ALUSrcA, ALUSrcB; 5 | wire [2:0] ALUControl, ImmSrc; 6 | 7 | wire Zero, ALUResSign; 8 | wire [2:0] funct3; 9 | wire [6:0] funct7, op; 10 | 11 | datapath dPath(clk, rst, PCWrite, AdrSrc, MemWrite, IRWrite, ResultSrc, ALUControl, 12 | ALUSrcA, ALUSrcB, ImmSrc, RegWrite, Zero, ALUResSign, funct3, funct7, op); 13 | 14 | controller cntrller(clk, rst, Zero, ALUResSign, op, funct7, funct3, PCWrite, AdrSrc, MemWrite, 15 | IRWrite, ImmSrc, RegWrite, ALUControl, ALUSrcA, ALUSrcB, ResultSrc); 16 | endmodule 17 | -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/RISCV_TB.v: -------------------------------------------------------------------------------- 1 | module RISCV_TB(); 2 | reg clk, rst; 3 | 4 | RISCV cpu(clk, rst); 5 | 6 | always #5 clk <= ~clk; 7 | 8 | initial begin 9 | clk = 1'b0; 10 | rst = 1'b1; 11 | #10 rst = 1'b0; 12 | 13 | #3000 $stop; 14 | end 15 | endmodule -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/assembly/a_riscv.s: -------------------------------------------------------------------------------- 1 | add x6,x0,x0 2 | addi x8,x0,0 3 | 4 | LOOP: slti x7,x6,40 5 | beq x7,x0,END_LOOP 6 | lw x9,40(x6) 7 | 8 | IF: slt x1,x8,x9 9 | beq x1,x0, END_IF 10 | add x8,x0,x9 11 | 12 | END_IF: addi x6,x6,4 13 | j LOOP 14 | 15 | END_LOOP: 16 | -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/controller.v: -------------------------------------------------------------------------------- 1 | `define SW 7'b0100011 2 | 3 | `define JAL 7'b1101111 4 | 5 | `define LUI 7'b0110111 6 | 7 | `define LW 7'b0000011 8 | `define ADDI 7'b0010011 9 | `define SLTI 7'b0010011 10 | `define XORI 7'b0010011 11 | `define ORI 7'b0010011 12 | `define JALR 7'b1100111 13 | 14 | `define BRANCH 7'b1100011 15 | `define BEQ 7'b1100011 16 | `define BNW 7'b1100011 17 | `define BLT 7'b1100011 18 | `define BGE 7'b1100011 19 | 20 | `define ADD 7'b0110011 21 | `define SUB 7'b0110011 22 | `define SLT 7'b0110011 23 | `define OR 7'b0110011 24 | `define AND 7'b0110011 25 | 26 | 27 | module controller(clk, rst, Zero, ALUResSign, op, funct7, funct3, 28 | PCWrite, AdrSrc, MemWrite, IRWrite, ImmSrc, 29 | RegWrite, ALUControl, ALUSrcA, ALUSrcB, ResultSrc); 30 | input clk, rst, Zero, ALUResSign; 31 | input [6:0] op, funct7; 32 | input [2:0] funct3; 33 | output reg PCWrite, AdrSrc, MemWrite, IRWrite, RegWrite; 34 | output reg [2:0] ALUControl, ImmSrc; 35 | output reg [1:0] ALUSrcA, ALUSrcB, ResultSrc; 36 | 37 | parameter [4:0] IF=5'd0, ID=5'd1; 38 | parameter [4:0] EX_B=5'd2, EX_R=5'd3, EX_S=5'd4, EX_I=5'd5, EX_J=5'd6, EX_J2=5'd7, EX_U=5'd8; 39 | parameter [4:0] MEM_S=5'd9, MEM_I=5'd10; 40 | parameter [4:0] REG_R=5'd11, REG_I_LW=5'd12, REG_I_LOGIC=5'd13, REG_I_JALR=5'd14, REG_J=5'd15; 41 | 42 | reg [4:0] ns, ps; 43 | 44 | always @(ps, op) begin 45 | ns = IF; 46 | case (ps) 47 | IF : ns = ID; 48 | 49 | ID : ns = (op == `LW) ? EX_I : 50 | (op == `ADDI) ? EX_I : 51 | (op == `JALR) ? EX_I : 52 | (op == `SW) ? EX_S : 53 | (op == `BRANCH) ? EX_B : 54 | (op == `ADD) ? EX_R : 55 | (op == `LUI) ? EX_U : 56 | (op == `JAL) ? EX_J : 57 | 7'bx; 58 | 59 | EX_B : ns = IF; 60 | EX_R : ns = REG_R; 61 | EX_S : ns = MEM_S; 62 | EX_I : ns = (op == `LW) ? MEM_I : 63 | (op == `ADDI) ? REG_I_LOGIC : 64 | (op == `JALR) ? REG_I_JALR : 5'bx; 65 | EX_J : ns = REG_J; 66 | EX_J2 : ns = IF; 67 | EX_U : ns = IF; 68 | 69 | MEM_S : ns = IF; 70 | MEM_I : ns = REG_I_LW; 71 | 72 | REG_R : ns = IF; 73 | REG_I_LW : ns = IF; 74 | REG_I_LOGIC : ns = IF; 75 | REG_I_JALR : ns = IF; 76 | REG_J : ns = EX_J2; 77 | 78 | default: ns = IF; 79 | endcase 80 | end 81 | 82 | always @(ps, op, funct3, funct7, Zero, ALUResSign) begin 83 | {AdrSrc, PCWrite, MemWrite, IRWrite, ALUSrcA, ALUSrcB, ALUControl, ResultSrc, RegWrite, ImmSrc} = 16'b0; 84 | case(ps) 85 | IF : begin 86 | AdrSrc = 1'b0; 87 | IRWrite = 1'b1; 88 | ALUSrcA = 2'b00; 89 | ALUSrcB = 2'b10; 90 | ALUControl = 3'b000; 91 | ResultSrc = 2'b10; 92 | PCWrite = 1'b1; 93 | end 94 | 95 | ID : begin 96 | ALUSrcA = 2'b01; 97 | ALUSrcB = 2'b01; 98 | ALUControl = 3'b000; 99 | ImmSrc = 3'b010; 100 | end 101 | 102 | EX_B : begin 103 | ALUSrcA = 2'b10; 104 | ALUSrcB = 2'b00; 105 | ALUControl = 3'b001; 106 | ResultSrc = 2'b00; 107 | PCWrite = (funct3 == 3'b000 && Zero == 1'b1) ? 1'b1 ://beq branches 108 | (funct3 == 3'b001 && Zero == 1'b0) ? 1'b1 : //bne branches 109 | (funct3 == 3'b100 && ALUResSign == 1'b1) ? 1'b1 : //blt branches 110 | (funct3 == 3'b101 && ALUResSign == 1'b0) ? 1'b1 : 1'b0; //bge branches 111 | end 112 | 113 | EX_R : begin 114 | ALUSrcA = 2'b10; 115 | ALUSrcB = 2'b00; 116 | ALUControl = (funct3 == 3'b000 && funct7 == 7'b0000000) ? 3'b000 : //ADD 117 | (funct3 == 3'b000 && funct7 == 7'b0100000) ? 3'b001 ://SUB 118 | (funct3 == 3'b010 && funct7 == 7'b0000000) ? 3'b101 : //SLT 119 | (funct3 == 3'b110 && funct7 == 7'b0000000) ? 3'b011 : //OR 120 | (funct3 == 3'b111 && funct7 == 7'b0000000) ? 3'b010 : 3'bx; //AND 121 | end 122 | 123 | EX_S : begin 124 | ImmSrc = 3'b001; 125 | ALUSrcA = 2'b10; 126 | ALUSrcB = 2'b01; 127 | ALUControl = 3'b000; 128 | end 129 | 130 | EX_I : begin 131 | ImmSrc = 3'b000; 132 | ALUSrcA = 2'b10; 133 | ALUSrcB = (op == `JALR && funct3 == 3'b000) ? 2'b10 : // JALR 134 | (op == `LW && funct3 == 3'b010) ? 2'b01 : // LW 135 | (op == `ADDI) ? 2'b01 : 2'bxx; // ADDI - ORI - SLTI - XORI - 136 | 137 | ALUControl = (op == `ADDI && funct3 == 3'b000) ? 3'b000 : //ADDI 138 | (op == `JALR && funct3 == 3'b000) ? 3'b000 ://JALR 139 | (op == `LW && funct3 == 3'b010) ? 3'b000 : //LW 140 | (op == `ORI && funct3 == 3'b110) ? 3'b011 : //ORI 141 | (op == `XORI && funct3 == 3'b100) ? 3'b100 : //XORI 142 | (op == `SLTI && funct3 == 3'b010) ? 3'b101 : 3'bx; //SLTI 143 | end 144 | 145 | EX_J : begin 146 | ALUSrcA = 2'b01; 147 | ALUSrcB = 2'b10; 148 | ALUControl = 3'b000; 149 | end 150 | 151 | EX_J2 : begin 152 | ImmSrc = 3'b011; 153 | ALUSrcA = 2'b01; 154 | ALUSrcB = 2'b01; 155 | ALUControl = 3'b000; 156 | ResultSrc = 2'b10; 157 | PCWrite = 1'b1; 158 | end 159 | 160 | EX_U : begin 161 | ImmSrc = 3'b100; 162 | ResultSrc = 3'b011; 163 | RegWrite = 1'b1; 164 | end 165 | 166 | MEM_S : begin 167 | ResultSrc = 2'b00; 168 | AdrSrc = 1'b1; 169 | MemWrite = 1'b1; 170 | end 171 | 172 | MEM_I : begin 173 | ResultSrc = 2'b00; 174 | AdrSrc = 1'b1; 175 | end 176 | 177 | REG_R : begin 178 | ResultSrc = 2'b00; 179 | RegWrite = 1'b1; 180 | end 181 | 182 | REG_I_LW : begin 183 | ResultSrc = 2'b01; 184 | RegWrite = 1'b1; 185 | end 186 | 187 | REG_I_LOGIC : begin 188 | ResultSrc = 2'b00; 189 | RegWrite = 1'b1; 190 | end 191 | 192 | REG_I_JALR : begin 193 | ResultSrc = 2'b00; 194 | RegWrite = 1'b1; 195 | end 196 | 197 | REG_J : begin 198 | ResultSrc = 2'b00; 199 | RegWrite = 1'b1; 200 | end 201 | 202 | default: {AdrSrc, PCWrite, MemWrite, IRWrite, ALUSrcA, 203 | ALUSrcB, ALUControl, ResultSrc, RegWrite, ImmSrc} = 16'b0; 204 | endcase 205 | end 206 | 207 | always @(posedge clk, posedge rst) begin 208 | if (rst) begin 209 | ps <= IF; 210 | end 211 | else begin 212 | ps <= ns; 213 | end 214 | end 215 | endmodule 216 | -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/controller/controller1.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA3-RISC-V Multi-Cycle/controller/controller1.JPG -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/controller/controller2.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA3-RISC-V Multi-Cycle/controller/controller2.JPG -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/controller/controller3.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA3-RISC-V Multi-Cycle/controller/controller3.JPG -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/data/data.txt: -------------------------------------------------------------------------------- 1 | 00000333 2 | 00000413 3 | 02832393 4 | 00038e63 5 | 02832483 6 | 009420b3 7 | 00008463 8 | 00900433 9 | 00430313 10 | fe5ff06f 11 | 0000000a 12 | 0000000c 13 | 00000008 14 | 00000009 15 | 00000004 16 | 0000000b 17 | 00000001 18 | 000000a2 19 | 0000000d 20 | 00000006 -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/datapath.v: -------------------------------------------------------------------------------- 1 | module datapath(clk, rst, PCWrite, AdrSrc, MemWrite, IRWrite, ResultSrc, ALUControl, ALUSrcA, 2 | ALUSrcB, ImmSrc, RegWrite, Zero, ALUResSign, funct3, funct7, op); 3 | input clk, rst; 4 | input PCWrite, AdrSrc, MemWrite, IRWrite, RegWrite; 5 | input [1:0] ResultSrc, ALUSrcA, ALUSrcB; 6 | input [2:0] ALUControl, ImmSrc; 7 | 8 | output Zero, ALUResSign; 9 | output [2:0] funct3; 10 | output [6:0] funct7, op; 11 | 12 | wire [31:0] PCOut, PCNext, Instr, SrcA, SrcB, ImmExt, ALUResult, MemReadData, Result; 13 | wire [31:0] memAdr, OldPC, MDROut, SrcRegA, SrcRegB, preSrcA, preSrcB, ALUOut; 14 | 15 | reg32B PC(.clk(clk), .rst(rst), .en(PCWrite), .dataIn(PCNext), .dataOut(PCOut)); 16 | mux2To1 memAdrMux(.in0(PCOut), .in1(Result), .sl(AdrSrc), .out(memAdr)); 17 | memory DataInstrMem(.clk(clk), .rst(rst), .A(memAdr), .WE(MemWrite), .WD(preSrcB), .RD(MemReadData)); 18 | reg32B oldPCReg(.clk(clk), .rst(rst), .en(IRWrite), .dataIn(PCOut), .dataOut(OldPC)); 19 | reg32B instrReg(.clk(clk), .rst(rst), .en(IRWrite), .dataIn(MemReadData), .dataOut(Instr)); 20 | reg32B MDR(.clk(clk), .rst(rst), .en(1'b1), .dataIn(MemReadData), .dataOut(MDROut)); 21 | registerFile RegFile(.clk(clk), .rst(rst), .A1(Instr[19:15]), .A2(Instr[24:20]), .A3(Instr[11:7]), 22 | .WE(RegWrite), .WD(Result), .RD1(SrcRegA), .RD2(SrcRegB)); 23 | reg32B regA(.clk(clk), .rst(rst), .en(1'b1), .dataIn(SrcRegA), .dataOut(preSrcA)); 24 | reg32B regB(.clk(clk), .rst(rst), .en(1'b1), .dataIn(SrcRegB), .dataOut(preSrcB)); 25 | extend immExtend(.inst(Instr[31:7]), .sl(ImmSrc), .out(ImmExt)); 26 | mux4To1 ALUSrc1Mux(.in0(PCOut), .in1(OldPC), .in2(preSrcA), .in3(32'bx), .sl(ALUSrcA), .out(SrcA)); 27 | mux4To1 ALUSrc2Mux(.in0(preSrcB), .in1(ImmExt), .in2(32'd4), .in3(32'bx), .sl(ALUSrcB), .out(SrcB)); 28 | ALU mainALU(.in1(SrcA), .in2(SrcB), .sl(ALUControl), .out(ALUResult), .zero(Zero), .sign(ALUResSign)); 29 | reg32B ALUResReg(.clk(clk), .rst(rst), .en(1'b1), .dataIn(ALUResult), .dataOut(ALUOut)); 30 | mux4To1 resultMux(.in0(ALUOut), .in1(MDROut), .in2(ALUResult), .in3(ImmExt), .sl(ResultSrc), .out(Result)); 31 | 32 | assign op = Instr[6:0]; 33 | assign funct3 = Instr[14:12]; 34 | assign funct7 = Instr[31:25]; 35 | assign PCNext = Result; 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/datapath/Datapath.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA3-RISC-V Multi-Cycle/datapath/Datapath.JPG -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/description/CA#03.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA3-RISC-V Multi-Cycle/description/CA#03.pdf -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/extend.v: -------------------------------------------------------------------------------- 1 | module extend(inst, sl, out); 2 | input [31:7] inst; 3 | input [2:0] sl; 4 | output [31:0] out; 5 | 6 | assign out = 7 | sl == 3'b000 ? {{21{inst[31]}}, inst[30:20]} : // I-Type 8 | sl == 3'b001 ? {{21{inst[31]}}, inst[30:25], inst[11:7]} : // S-Type 9 | sl == 3'b010 ? {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0} : // B-Type 10 | sl == 3'b100 ? {inst[31], inst[30:20], inst[19:12], 12'b0} : // U-Type 11 | sl == 3'b011 ? {{12{inst[31]}}, inst[19:12], inst[20], inst[30:25], inst[24:21], 1'b0} : // J-Type 12 | 32'bx; 13 | endmodule -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/memory.v: -------------------------------------------------------------------------------- 1 | module memory(clk, rst, A, WE, WD, RD); 2 | input clk, rst; 3 | input [31:0] A; 4 | input WE; 5 | input [31:0] WD; 6 | output [31:0] RD; 7 | wire [31:0] address; 8 | integer i; 9 | 10 | reg [31:0] memory [0:16384]; // 2^14 11 | 12 | initial begin 13 | $readmemh("data.txt", memory); 14 | end 15 | 16 | assign address = {2'b0, A[31:2]}; 17 | 18 | always @(posedge clk, posedge rst) begin 19 | if (WE) begin 20 | memory[address] <= WD; 21 | end 22 | end 23 | 24 | assign RD = memory[address]; 25 | endmodule -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/mux2To1.v: -------------------------------------------------------------------------------- 1 | module mux2To1(in0, in1, sl, out); 2 | input [31:0] in0, in1; 3 | input sl; 4 | output [31:0] out; 5 | 6 | assign out = sl ? in1 : in0; 7 | endmodule -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/mux4To1.v: -------------------------------------------------------------------------------- 1 | module mux4To1(in0, in1, in2, in3, sl, out); 2 | input [31:0] in0, in1, in2, in3; 3 | input [1:0] sl; 4 | output [31:0] out; 5 | 6 | assign out = 7 | sl == 2'b00 ? in0 : 8 | sl == 2'b01 ? in1 : 9 | sl == 2'b10 ? in2 : 10 | sl == 2'b11 ? in3 : 11 | 32'bx; 12 | endmodule 13 | -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/reg32B.v: -------------------------------------------------------------------------------- 1 | module reg32B(clk, rst, en, dataIn, dataOut); 2 | input clk, rst, en; 3 | input [31:0] dataIn; 4 | output [31:0] dataOut; 5 | reg [31:0] savedData; 6 | 7 | always @(posedge clk, posedge rst) begin 8 | if (rst) 9 | savedData = 32'b0; 10 | 11 | else if (en) 12 | savedData = dataIn; 13 | end 14 | 15 | assign dataOut = savedData; 16 | endmodule -------------------------------------------------------------------------------- /CA3-RISC-V Multi-Cycle/registerFile.v: -------------------------------------------------------------------------------- 1 | module registerFile(clk, rst, A1, A2, A3, WE, WD, RD1, RD2); 2 | input clk, rst; 3 | input [19:15] A1; 4 | input [24:20] A2; 5 | input [11:7] A3; 6 | input WE; 7 | input [31:0] WD; 8 | output [31:0] RD1, RD2; 9 | integer i; 10 | 11 | reg [31:0] registers [0:31]; 12 | initial begin 13 | registers[0] <= 32'b0; // ZERO register 14 | end 15 | 16 | always @(posedge clk, posedge rst) begin 17 | if (rst) begin 18 | for (i = 0; i < 32; i = i + 1) 19 | registers[i] <= 32'b0; 20 | end 21 | else if (WE && A3 != 5'b0) begin 22 | registers[A3] <= WD; 23 | end 24 | end 25 | 26 | assign RD1 = registers[A1]; 27 | assign RD2 = registers[A2]; 28 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/ALU.v: -------------------------------------------------------------------------------- 1 | `define ALU_SUB 3'b001 2 | `define ALU_ADD 3'b000 3 | `define ALU_XOR 3'b100 4 | `define ALU_AND 3'b010 5 | `define ALU_OR 3'b011 6 | `define ALU_SLT 3'b101 7 | 8 | module ALU(in1, in2, sl, out, zero, sign); 9 | input [31:0] in1, in2; 10 | input [2:0] sl; 11 | output zero, sign; 12 | output reg [31:0] out; 13 | 14 | always @(in1, in2, sl) begin 15 | out = 32'b0; 16 | case (sl) 17 | `ALU_ADD: 18 | out = in1 + in2; 19 | `ALU_SUB: 20 | out = in1 - in2; 21 | `ALU_AND: 22 | out = in1 & in2; 23 | `ALU_OR: 24 | out = in1 | in2; 25 | `ALU_XOR: 26 | out = in1 ^ in2; 27 | `ALU_SLT: 28 | out = (in1 < in2 ? 32'd1 : 32'd0); 29 | default: 30 | out = 32'b0; 31 | endcase 32 | end 33 | 34 | assign zero = (out == 32'b0); 35 | assign sign = (out[31]); 36 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/RISCV.v: -------------------------------------------------------------------------------- 1 | module RISCV(clk, rst); 2 | input clk, rst; 3 | wire RegWriteMHazard, RegWriteWHazard; 4 | 5 | wire [6:0] op, funct7; 6 | wire [2:0] funct3; 7 | wire ZeroE, ResSignE; 8 | wire [2:0] BranchE; 9 | wire [1:0] JumpE; 10 | 11 | wire [1:0] ResultSrcD, JumpD, PCSrcE; 12 | wire [2:0] ALUControlD, ImmSrcD, BranchD; 13 | wire RegWriteD, MemWriteD, ALUSrcD, LUIInstr; 14 | 15 | wire StallF, StallD, FlushD, FlushE; 16 | wire [1:0] ForwardAE, ForwardBE; 17 | 18 | wire ResultSrcEHazard; 19 | wire [1:0] PCSrcEHazard; 20 | wire [4:0] RdWHazard, RdMHazard, Rs1EHazard, Rs2EHazard, RdEHazard, Rs2DHazard, Rs1DHazard; 21 | 22 | datapath dPth(.clk(clk), .rst(rst), .RegWriteD(RegWriteD), .ResultSrcD(ResultSrcD), 23 | .MemWriteD(MemWriteD), .JumpD(JumpD), .BranchD(BranchD), .ALUControlD(ALUControlD), 24 | .ALUSrcD(ALUSrcD), .ImmSrcD(ImmSrcD), .PCSrcE(PCSrcE), .LUIInstr(LUIInstr), 25 | .StallF(StallF), .StallD(StallD), .FlushD(FlushD), .FlushE(FlushE), 26 | .ForwardAE(ForwardAE), .ForwardBE(ForwardBE), .ZeroE(ZeroE), .ALUResSignE(ResSignE), 27 | .JumpEOut(JumpE), .BranchEOut(BranchE), .funct3(funct3), .funct7(funct7), .op(op), 28 | .Rs1DHazard(Rs1DHazard), .Rs2DHazard(Rs2DHazard), .RdEHazard(RdEHazard), 29 | .Rs1EHazard(Rs1EHazard), .Rs2EHazard(Rs2EHazard), .PCSrcEHazard(PCSrcEHazard), 30 | .ResultSrcEHazard(ResultSrcEHazard), .RdMHazard(RdMHazard), .RdWHazard(RdWHazard), 31 | .RegWriteMHazard(RegWriteMHazard), .RegWriteWHazard(RegWriteWHazard)); 32 | 33 | controller cntrllr(.funct3(funct3), .funct7(funct7), .op(op), .JumpE(JumpE), .BranchE(BranchE), 34 | .ZeroE(ZeroE), .ResSignE(ResSignE), .RegWriteD(RegWriteD), .ResultSrcD(ResultSrcD), 35 | .MemWriteD(MemWriteD), .JumpD(JumpD), .BranchD(BranchD), .ALUControlD(ALUControlD), 36 | .ALUSrcD(ALUSrcD), .PCSrcE(PCSrcE), .ImmSrcD(ImmSrcD), .LUIInstr(LUIInstr)); 37 | 38 | hazardUnit hzrdUnt(.rst(rst), .RegWriteWHazard(RegWriteWHazard), .RdWHazard(RdWHazard), 39 | .RegWriteMHazard(RegWriteMHazard), .RdMHazard(RdMHazard), 40 | .ResultSrcEHazard(ResultSrcEHazard), .PCSrcEHazard(PCSrcEHazard), 41 | .Rs1EHazard(Rs1EHazard), .Rs2EHazard(Rs2EHazard), .RdEHazard(RdEHazard), 42 | .Rs2DHazard(Rs2DHazard), .Rs1DHazard(Rs1DHazard), .FlushE(FlushE), .FlushD(FlushD), 43 | .StallD(StallD), .StallF(StallF), .ForwardBE(ForwardBE), .ForwardAE(ForwardAE)); 44 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/RISCV_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module RISCV_TB(); 4 | reg clk, rst; 5 | 6 | RISCV cpu(clk, rst); 7 | 8 | always #5 clk <= ~clk; 9 | 10 | initial begin 11 | clk = 1'b0; 12 | rst = 1'b1; 13 | #10 rst = 1'b0; 14 | 15 | #1300 $stop; 16 | end 17 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/adder32B.v: -------------------------------------------------------------------------------- 1 | module adder32B(in1, in2, sum, c); 2 | input [31:0] in1, in2; 3 | output [31:0] sum; 4 | output c; 5 | assign {c, sum} = in1 + in2; 6 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/array/array.txt: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000101 2 | 00000000000000000000000000011110 3 | 00000000000000000000000000011100 4 | 00000000000000000000000000001000 5 | 00000000000000000000000000010001 6 | 00000000000000000000000001100011 7 | 00000000000000000000001110111101 8 | 00000000000000000000000000000011 9 | 00000000000000000000000001010111 10 | 00000000000000000000000000001111 -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/assembly/a_riscv.s: -------------------------------------------------------------------------------- 1 | # int i = 0; 2 | # int max = 0l 3 | # for (i = 0; i < 10; i++) 4 | // if (max < A[i]) 5 | # max = A[i] 6 | 7 | # i <- x6 8 | # A[i] <- x9 9 | # max <- x8 10 | 11 | add x6,x0,x0 12 | addi x8,x0,0 13 | 14 | LOOP: slti x7,x6,40 15 | beq x7,x0,END_LOOP 16 | lw x9,0(x6) 17 | 18 | IF: slt x1,x8,x9 19 | beq x1,x0, END_IF 20 | add x8,x0,x9 21 | 22 | END_IF: addi x6,x6,4 23 | j LOOP 24 | 25 | END_LOOP: 26 | -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/controller.v: -------------------------------------------------------------------------------- 1 | `define LW_OP 7'b0000011 2 | `define SW_OP 7'b0100011 3 | `define BRANCH_OP 7'b1100011 4 | `define LUI_OP 7'b0110111 5 | `define JALR_OP 7'b1100111 6 | `define JAL_OP 7'b1101111 7 | `define ADDI_OP 7'b0010011 8 | `define ADD_OP 7'b0110011 9 | 10 | `define I_TYPE_ImmSrc 3'b000 11 | `define S_TYPE_ImmSrc 3'b001 12 | `define B_TYPE_ImmSrc 3'b010 13 | `define U_TYPE_ImmSrc 3'b100 14 | `define J_TYPE_ImmSrc 3'b011 15 | `define ADDI 7'b0010011 16 | `define ADD_FUN3 3'b000 17 | `define SUB_FUN3 3'b000 18 | `define AND_FUN3 3'b111 19 | `define OR_FUN3 3'b110 20 | `define SLT_FUN3 3'b010 21 | `define XOR_FUN3 3'b100 22 | `define ADDI_FUN3 3'b000 23 | `define XORI_FUN3 3'b100 24 | `define ORI_FUN3 3'b110 25 | `define SLTI_FUN3 3'b010 26 | `define JALR_FUN3 3'b000 27 | `define LW_FUN3 3'b010 28 | 29 | 30 | `define ADD_FUN7 7'b0000000 31 | `define SUB_FUN7 7'b01000000 32 | `define AND_FUN7 7'b0000000 33 | `define OR_FUN7 7'b0000000 34 | `define SLT_FUN7 7'b0000000 35 | 36 | `define ALU_SUB 3'b001 37 | `define ALU_ADD 3'b000 38 | `define ALU_XOR 3'b100 39 | `define ALU_AND 3'b010 40 | `define ALU_OR 3'b011 41 | `define ALU_SLT 3'b101 42 | 43 | `define branchEq 3'b001 44 | `define branchNEq 3'b010 45 | `define branchLEq 3'b011 46 | `define branchGEq 3'b100 47 | `define notBranch 3'b000 48 | `define jumpRegister 2'b10 49 | `define jump 2'b11 50 | 51 | `define BEQ 3'b000 52 | `define BNE 3'b001 53 | `define BLT 3'b100 54 | `define BGE 3'b101 55 | 56 | `define PC_PLUS_4 2'b00 57 | `define PC_PLUS_IMM 2'b01 58 | `define PC_PLUS_JADR 2'b10 59 | 60 | module controller(funct3, funct7, op, JumpE, BranchE, ZeroE, ResSignE, RegWriteD, ResultSrcD, 61 | MemWriteD, JumpD, BranchD, ALUControlD, ALUSrcD, PCSrcE, ImmSrcD, LUIInstr); 62 | input [2:0] funct3; 63 | input [6:0] funct7, op; 64 | input ZeroE, ResSignE; 65 | input [1:0] JumpE; 66 | input [2:0] BranchE; 67 | output reg [1:0] ResultSrcD, PCSrcE, JumpD; 68 | output reg [2:0] ALUControlD, ImmSrcD, BranchD; 69 | output reg RegWriteD, MemWriteD, ALUSrcD, LUIInstr; 70 | reg [1:0] ALUOp; 71 | 72 | always @(op, funct3, funct7) begin 73 | {ResultSrcD, MemWriteD, ALUControlD, ALUSrcD, ImmSrcD, RegWriteD, ALUOp, 74 | LUIInstr, JumpD, BranchD} = 21'b0; 75 | case (op) 76 | `LW_OP: begin 77 | ALUSrcD = 1'b1; 78 | ImmSrcD = `I_TYPE_ImmSrc; 79 | ALUOp = 2'b00; 80 | ResultSrcD = 2'b01; 81 | RegWriteD = 1'b1; 82 | LUIInstr = 1'b1; 83 | 84 | end 85 | 86 | `ADDI_OP: begin 87 | ALUSrcD = 1'b1; 88 | ImmSrcD = `I_TYPE_ImmSrc; 89 | ALUOp = 2'b10; 90 | ResultSrcD = 2'b00; 91 | RegWriteD = 1'b1; 92 | ALUOp = 2'b10; 93 | end 94 | 95 | `SW_OP: begin 96 | ALUSrcD = 1'b1; 97 | ImmSrcD = `S_TYPE_ImmSrc; 98 | ALUOp = 2'b00; 99 | MemWriteD = 1'b1; 100 | end 101 | 102 | `BRANCH_OP: begin 103 | BranchD = (funct3 == `BEQ) ? `branchEq : 104 | (funct3 == `BNE) ? `branchNEq : 105 | (funct3 == `BLT) ? `branchLEq : 106 | (funct3 == `BGE) ? `branchGEq : 107 | 3'b101; //this one will never happen 108 | ALUSrcD = 1'b0; 109 | ImmSrcD = `B_TYPE_ImmSrc; 110 | ALUOp = 2'b01; 111 | end 112 | 113 | `ADD_OP: begin 114 | RegWriteD = 1'b1; 115 | ALUOp = 2'b10; 116 | end 117 | 118 | `LUI_OP: begin 119 | RegWriteD = 1'b1; 120 | ResultSrcD = 2'b11; 121 | ImmSrcD = `U_TYPE_ImmSrc; 122 | LUIInstr = 1'b1; 123 | end 124 | 125 | `JALR_OP: begin 126 | BranchD = `notBranch; 127 | JumpD = `jumpRegister; 128 | ALUSrcD = 1'b1; 129 | RegWriteD = 1'b1; 130 | ResultSrcD = 2'b10; 131 | ImmSrcD = `I_TYPE_ImmSrc; 132 | ALUOp = 2'b00; 133 | end 134 | 135 | `JAL_OP: begin 136 | BranchD = `notBranch; 137 | JumpD = `jump; 138 | ALUSrcD = 1'b1; 139 | RegWriteD = 1'b1; 140 | ResultSrcD = 2'b10; 141 | ImmSrcD = `J_TYPE_ImmSrc; 142 | ALUOp = 2'b00; 143 | end 144 | default: begin 145 | {ResultSrcD, MemWriteD, ALUControlD, ALUSrcD, ImmSrcD, 146 | RegWriteD, ALUOp, LUIInstr, JumpD, BranchD} = 21'b0; 147 | end 148 | endcase 149 | end 150 | 151 | always @(ALUOp) begin 152 | case (ALUOp) 153 | 2'b00: 154 | ALUControlD = `ALU_ADD; 155 | 2'b01: 156 | ALUControlD = `ALU_SUB; 157 | 2'b10: begin 158 | if (funct3 == `ADDI_FUN3 && op == `ADDI) 159 | ALUControlD = `ALU_ADD; 160 | 161 | if (funct3 == `ADD_FUN3 && funct7 == `ADD_FUN7) 162 | ALUControlD = `ALU_ADD; 163 | 164 | if (funct3 == `SUB_FUN3 && funct7 == `SUB_FUN7) 165 | ALUControlD = `ALU_SUB; 166 | 167 | if (funct3 == `XOR_FUN3) 168 | ALUControlD = `ALU_XOR; 169 | 170 | if (funct3 == `AND_FUN3) 171 | ALUControlD = `ALU_AND; 172 | 173 | if (funct3 == `OR_FUN3) 174 | ALUControlD = `ALU_OR; 175 | 176 | if (funct3 == `SLT_FUN3) 177 | ALUControlD = `ALU_SLT; 178 | end 179 | endcase 180 | end 181 | 182 | assign PCSrcE = ((BranchE == `branchEq && ZeroE == 1'b1) || 183 | (BranchE == `branchNEq && ZeroE == 1'b0) || 184 | (BranchE == `branchLEq && ResSignE == 1'b1) || 185 | (BranchE == `branchGEq && ResSignE == 1'b0) || 186 | (BranchE == `notBranch && JumpE == `jump)) ? 2'b01 : 187 | (BranchE == `notBranch && JumpE == `jumpRegister) ? 2'b10 : 2'b00; 188 | 189 | endmodule 190 | 191 | 192 | 193 | -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/dataMemory.v: -------------------------------------------------------------------------------- 1 | 2 | module dataMemory(clk, rst, A, WE, WD, RD); 3 | input clk, rst; 4 | input [31:0] A; 5 | input WE; 6 | input [31:0] WD; 7 | output [31:0] RD; 8 | wire [31:0] address; 9 | integer i; 10 | 11 | reg [31:0] memory [0:16384]; 12 | 13 | initial begin 14 | $readmemb("array.txt", memory); 15 | end 16 | 17 | assign address = {2'b0, A[31:2]}; 18 | 19 | always @(posedge clk, posedge rst) begin 20 | if (WE) begin 21 | memory[address] <= WD; 22 | end 23 | end 24 | 25 | assign RD = memory[address]; 26 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/datapath.v: -------------------------------------------------------------------------------- 1 | module datapath(clk, rst, 2 | RegWriteD, ResultSrcD, MemWriteD, JumpD, BranchD, 3 | ALUControlD, ALUSrcD, ImmSrcD, PCSrcE, LUIInstr, // inputs from controller 4 | StallF, StallD, FlushD, FlushE, ForwardAE, ForwardBE, // inputs from hazard unit 5 | ZeroE, ALUResSignE, JumpEOut, BranchEOut, funct3, funct7, op, // outputs to controller 6 | Rs1DHazard, Rs2DHazard, RdEHazard, Rs1EHazard, Rs2EHazard, PCSrcEHazard, ResultSrcEHazard, RdMHazard, 7 | RegWriteMHazard, RdWHazard, RegWriteWHazard); // outputs to hazard unit 8 | 9 | input clk, rst; 10 | input RegWriteD, MemWriteD, ALUSrcD, LUIInstr, StallF, StallD, FlushD, FlushE; 11 | input [1:0] ResultSrcD, JumpD, PCSrcE, ForwardAE, ForwardBE; 12 | input [2:0] ALUControlD, ImmSrcD, BranchD; 13 | output ResultSrcEHazard, 14 | RegWriteMHazard, RegWriteWHazard; 15 | output [4:0] RdWHazard, RdMHazard, Rs1EHazard, Rs2EHazard, RdEHazard, Rs2DHazard, Rs1DHazard; 16 | output ZeroE, ALUResSignE; 17 | output [1:0] PCSrcEHazard, JumpEOut; 18 | output [2:0] funct3, BranchEOut; 19 | output [6:0] funct7, op; 20 | 21 | wire [31:0] PCPlus4F, PCF, secPCF, InstrF; 22 | wire [31:0] InstrD, RD1D, RD2D, PCD, ExtImmD, PCPlus4D; 23 | 24 | wire RegWriteE, MemWriteE, ALUSrcE; 25 | wire [1:0] ResultSrcE, JumpE; 26 | wire [2:0] ALUControlE, BranchE; 27 | wire [4:0] Rs1E, Rs2E, RdE; 28 | wire [31:0] RD1E, RD2E, PCE, ExtImmE, PCPlus4E, SrcAE, SrcBE, ALUResultE, WriteDataE, PCTargetE; 29 | 30 | wire RegWriteM, MemWriteM; 31 | wire [1:0] ResultSrcM; 32 | wire [4:0] RdM; 33 | wire [31:0] ALUResultM, WriteDataM, ExtImmM, PCPlus4M, ReadDataM, memToExBackward; 34 | 35 | wire RegWriteW; 36 | wire [1:0] ResultSrcW; 37 | wire [4:0] RdW; 38 | wire [31:0] PCPlus4W, ReadDataW, ExtImmW, ResultW, ALUResultW; 39 | wire LUIInstrE, LUIInstrM; 40 | wire co1, co2; 41 | 42 | mux4To1 PCFMux(.in0(PCPlus4F), .in1(PCTargetE), .in2(ALUResultE), .in3(32'bx), .sl(PCSrcE), .out(secPCF)); 43 | reg32B PC(.clk(clk), .rst(rst), .en(~StallF), .dataIn(secPCF), .dataOut(PCF)); 44 | instructionMemory InstructionMem(.A(PCF), .RD(InstrF)); 45 | adder32B PCIncrementBy4(.in1(PCF), .in2(32'd4), .sum(PCPlus4F), .c(co1)); 46 | pipeFD pipe1(clk, rst, ~StallD, FlushD, InstrF, PCF, PCPlus4F, InstrD, PCD, PCPlus4D); 47 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 48 | registerFile RegFile(.clk(clk), .rst(rst), .A1(InstrD[19:15]), .A2(InstrD[24:20]), .A3(RdW), 49 | .WE(RegWriteW), .WD(ResultW), .RD1(RD1D), .RD2(RD2D)); 50 | extend immExtend(.inst(InstrD[31:7]), .sl(ImmSrcD), .out(ExtImmD)); 51 | pipeDE pipe2(clk, rst, FlushE, 52 | RegWriteD, ResultSrcD, MemWriteD, JumpD, BranchD, ALUControlD, ALUSrcD, LUIInstr, 53 | RD1D, RD2D, PCD, InstrD[19:15], InstrD[24:20], InstrD[11:7], ExtImmD, PCPlus4D, 54 | RegWriteE, ResultSrcE, MemWriteE, JumpE, BranchE, ALUControlE, ALUSrcE, LUIInstrE, 55 | RD1E, RD2E, PCE, Rs1E, Rs2E, RdE, ExtImmE, PCPlus4E); 56 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 57 | mux4To1 srcAMux(.in0(RD1E), .in1(ResultW), .in2(memToExBackward), .in3(32'bx), .sl(ForwardAE), .out(SrcAE)); 58 | mux4To1 srcBMux(.in0(RD2E), .in1(ResultW), .in2(memToExBackward), .in3(32'bx), .sl(ForwardBE), .out(WriteDataE)); 59 | mux2To1 srcBMux2(.in0(WriteDataE), .in1(ExtImmE), .sl(ALUSrcE), .out(SrcBE)); 60 | adder32B addderE(.in1(PCE), .in2(ExtImmE), .sum(PCTargetE), .c(co2)); 61 | ALU mainALU(.in1(SrcAE), .in2(SrcBE), .sl(ALUControlE), .out(ALUResultE), .zero(ZeroE), .sign(ALUResSignE)); 62 | pipeEM pipe3(clk, rst, 63 | RegWriteE, ResultSrcE, MemWriteE, LUIInstrE, 64 | ALUResultE, WriteDataE, RdE, ExtImmE, PCPlus4E, 65 | RegWriteM, ResultSrcM, MemWriteM, LUIInstrM, 66 | ALUResultM, WriteDataM, RdM, ExtImmM, PCPlus4M); 67 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 68 | dataMemory DataMem(.clk(clk), .rst(rst), .A(ALUResultM), .WE(MemWriteM), .WD(WriteDataM), .RD(ReadDataM)); 69 | mux2To1 memToExMux(.in0(ALUResultM), .in1(ExtImmM), .sl(LUIInstrM), .out(memToExBackward)); 70 | pipeMW pipe4(clk, rst, 71 | RegWriteM, ResultSrcM, 72 | ReadDataM, RdM, ExtImmM, PCPlus4M, ALUResultM, 73 | RegWriteW, ResultSrcW, 74 | ReadDataW, RdW, ExtImmW, PCPlus4W, ALUResultW); 75 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 76 | mux4To1 resMux(.in0(ALUResultW), .in1(ReadDataW), .in2(PCPlus4W), .in3(ExtImmW), .sl(ResultSrcW), .out(ResultW)); 77 | 78 | assign op = InstrD[6:0]; 79 | assign funct3 = InstrD[14:12]; 80 | assign funct7 = InstrD[31:25]; 81 | assign JumpEOut = JumpE; 82 | assign BranchEOut = BranchE; 83 | 84 | assign Rs1DHazard = InstrD[19:15]; 85 | assign Rs2DHazard = InstrD[24:20]; 86 | assign Rs1EHazard = Rs1E; 87 | assign Rs2EHazard = Rs2E; 88 | assign RdEHazard = RdE; 89 | assign PCSrcEHazard = PCSrcE; 90 | assign ResultSrcEHazard = ResultSrcE[0]; 91 | assign RdMHazard = RdM; 92 | assign RegWriteMHazard = RegWriteM; 93 | assign RdWHazard = RdW; 94 | assign RegWriteWHazard = RegWriteW; 95 | 96 | 97 | 98 | endmodule 99 | 100 | -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/datapath/Datapath.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA4-RISC-V Pipeline/datapath/Datapath.JPG -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/description/CA#04.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MobinaMhr/Computer-Architecture-Course-Projects-S2023/ed350700367bff97715af963820b903cdccf8dda/CA4-RISC-V Pipeline/description/CA#04.pdf -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/extend.v: -------------------------------------------------------------------------------- 1 | module extend(inst, sl, out); 2 | input [31:7] inst; 3 | input [2:0] sl; 4 | output [31:0] out; 5 | 6 | assign out = 7 | sl == 3'b000 ? {{21{inst[31]}}, inst[30:20]} : // I-Type 8 | sl == 3'b001 ? {{21{inst[31]}}, inst[30:25], inst[11:7]} : // S-Type 9 | sl == 3'b010 ? {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0} : // B-Type 10 | sl == 3'b100 ? {inst[31], inst[30:20], inst[19:12], 12'b0} : // U-Type 11 | sl == 3'b011 ? {{12{inst[31]}}, inst[19:12], inst[20], inst[30:25], inst[24:21], 1'b0} : // J-Type 12 | 32'bx; 13 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/hazardUnit.v: -------------------------------------------------------------------------------- 1 | module hazardUnit(rst, RegWriteWHazard, RdWHazard, RegWriteMHazard, RdMHazard, ResultSrcEHazard, 2 | PCSrcEHazard, Rs1EHazard, Rs2EHazard, RdEHazard, Rs2DHazard, Rs1DHazard, FlushE, 3 | FlushD, StallD, StallF, ForwardBE, ForwardAE); 4 | input RegWriteWHazard, RegWriteMHazard; 5 | input ResultSrcEHazard; 6 | input [1:0] PCSrcEHazard; 7 | output reg FlushE, FlushD, StallD, StallF; 8 | output reg [1:0] ForwardBE, ForwardAE; 9 | input [4:0] RdWHazard, RdMHazard, Rs1EHazard, Rs2EHazard, RdEHazard, Rs2DHazard, Rs1DHazard; 10 | input rst; 11 | reg lwStall; 12 | 13 | always @(posedge rst) {lwStall, StallF, StallD, ForwardAE, ForwardBE} = 7'b0000_000; 14 | 15 | always @(Rs1DHazard, Rs2DHazard, Rs1EHazard, Rs2EHazard, RdEHazard, 16 | ResultSrcEHazard, RdMHazard, RegWriteMHazard, RdWHazard, RegWriteWHazard) begin 17 | 18 | {lwStall, StallF, StallD, ForwardAE, ForwardBE} = 7'b0000_000; 19 | 20 | if (((Rs1EHazard == RdMHazard) && RegWriteMHazard) && (Rs1EHazard != 5'b00000)) 21 | ForwardAE = 2'b10; 22 | else if (((Rs1EHazard == RdWHazard) && RegWriteWHazard) && (Rs1EHazard != 5'b00000)) 23 | ForwardAE = 2'b01; 24 | else 25 | ForwardAE = 2'b00; 26 | 27 | if (((Rs2EHazard == RdMHazard) && RegWriteMHazard) && (Rs2EHazard != 5'b00000)) 28 | ForwardBE = 2'b10; 29 | else if (((Rs2EHazard == RdWHazard) && RegWriteWHazard) && (Rs2EHazard != 5'b00000)) 30 | ForwardBE = 2'b01; 31 | else 32 | ForwardBE = 2'b00; 33 | 34 | if (((Rs1DHazard == RdEHazard) || (Rs2DHazard == RdEHazard)) && (ResultSrcEHazard == 2'b01)) 35 | {lwStall, StallD, StallF} = 3'b111; 36 | 37 | end 38 | 39 | assign FlushD = |PCSrcEHazard; 40 | assign FlushE = (lwStall || |PCSrcEHazard); 41 | 42 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/instructionMemory.v: -------------------------------------------------------------------------------- 1 | module instructionMemory(A, RD); 2 | input [31:0] A; 3 | output [31:0] RD; 4 | wire [31:0] khoone; 5 | 6 | reg [31:0] memory [0:16384]; // 2^14 7 | initial begin 8 | $readmemh("instructions.txt", memory); 9 | end 10 | 11 | assign khoone = {2'b0, A[31:2]}; 12 | assign RD = memory[khoone]; 13 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/instructions/instructions.txt: -------------------------------------------------------------------------------- 1 | 00000333 2 | 00000413 3 | 02832393 4 | 00038e63 5 | 00032483 6 | 009420b3 7 | 00008463 8 | 00900433 9 | 00430313 10 | fe5ff06f -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/mux2To1.v: -------------------------------------------------------------------------------- 1 | module mux2To1(in0, in1, sl, out); 2 | input [31:0] in0, in1; 3 | input sl; 4 | output [31:0] out; 5 | 6 | assign out = sl ? in1 : in0; 7 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/mux4To1.v: -------------------------------------------------------------------------------- 1 | module mux4To1(in0, in1, in2, in3, sl, out); 2 | input [31:0] in0, in1, in2, in3; 3 | input [1:0] sl; 4 | output [31:0] out; 5 | 6 | assign out = 7 | sl == 2'b00 ? in0 : 8 | sl == 2'b01 ? in1 : 9 | sl == 2'b10 ? in2 : 10 | sl == 2'b11 ? in3 : 11 | 32'bx; 12 | endmodule 13 | -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/pipeDE.v: -------------------------------------------------------------------------------- 1 | module pipeDE(clk, rst, clr, 2 | RegWriteD, ResultSrcD, MemWriteD, JumpD, BranchD, ALUControlD, 3 | ALUSrcD, LUIInstrD, RD1D, RD2D, PCD, Rs1D, Rs2D, RdD, ExtImmD, PCPlus4D, 4 | RegWriteE, ResultSrcE, MemWriteE, JumpE, BranchE, ALUControlE, 5 | ALUSrcE, LUIInstrE, RD1E, RD2E, PCE, Rs1E, Rs2E, RdE, ExtImmE, PCPlus4E); 6 | 7 | input clk, rst, clr; 8 | input RegWriteD, MemWriteD, ALUSrcD, LUIInstrD; 9 | input [1:0] ResultSrcD, JumpD; 10 | input [2:0] ALUControlD, BranchD; 11 | input [4:0] Rs1D, Rs2D, RdD; 12 | input [31:0] RD1D, RD2D, PCD, ExtImmD, PCPlus4D; 13 | 14 | output RegWriteE, MemWriteE, ALUSrcE, LUIInstrE; 15 | output [1:0] ResultSrcE, JumpE; 16 | output [2:0] ALUControlE, BranchE; 17 | output [4:0] Rs1E, Rs2E, RdE; 18 | output [31:0] RD1E, RD2E, PCE, ExtImmE, PCPlus4E; 19 | 20 | regPipe #(1) regWriteReg(clk, rst, clr, 1'b1, RegWriteD, RegWriteE); 21 | regPipe #(1) memWriteReg(clk, rst, clr, 1'b1, memWriteD, memWriteE); 22 | regPipe #(1) ALUSrcReg(clk, rst, clr, 1'b1, ALUSrcD, ALUSrcE); 23 | regPipe #(1) luiReg(clk, rst, clr, 1'b1, LUIInstrD, LUIInstrE); 24 | regPipe #(2) jumpReg(clk, rst, clr, 1'b1, JumpD, JumpE); 25 | regPipe #(2) resultSrcReg(clk, rst, clr, 1'b1, ResultSrcD, ResultSrcE); 26 | regPipe #(3) branchReg(clk, rst, clr, 1'b1, BranchD, BranchE); 27 | regPipe #(3) ALUControlReg(clk, rst, clr, 1'b1, ALUControlD, ALUControlE); 28 | 29 | regPipe #(5) Rs1Reg(clk, rst, clr, 1'b1, Rs1D, Rs1E); 30 | regPipe #(5) Rs2Reg(clk, rst, clr, 1'b1, Rs2D, Rs2E); 31 | regPipe #(5) Rd3Reg(clk, rst, clr, 1'b1, RdD, RdE); 32 | regPipe #(32) RD1Reg(clk, rst, clr, 1'b1, RD1D, RD1E); 33 | regPipe #(32) RD2Reg(clk, rst, clr, 1'b1, RD2D, RD2E); 34 | regPipe #(32) PCReg(clk, rst, clr, 1'b1, PCD, PCE); 35 | regPipe #(32) extImmReg(clk, rst, clr, 1'b1, ExtImmD, ExtImmE); 36 | regPipe #(32) pcPlus4Reg(clk, rst, clr, 1'b1, PCPlus4D, PCPlus4E); 37 | endmodule 38 | -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/pipeEM.v: -------------------------------------------------------------------------------- 1 | module pipeEM(clk, rst, 2 | RegWriteE, ResultSrcE, MemWriteE, LUIInstrE, 3 | ALUResultE, WriteDataE, RdE, ExtImmE, PCPlus4E, 4 | RegWriteM, ResultSrcM, MemWriteM, LUIInstrM, 5 | ALUResultM, WriteDataM, RdM, ExtImmM, PCPlus4M); 6 | 7 | input clk, rst; 8 | input RegWriteE, MemWriteE, LUIInstrE; 9 | input [1:0] ResultSrcE; 10 | input [4:0] RdE; 11 | input [31:0] ALUResultE, WriteDataE, ExtImmE, PCPlus4E; 12 | 13 | output RegWriteM, MemWriteM, LUIInstrM; 14 | output [1:0] ResultSrcM; 15 | output [4:0] RdM; 16 | output [31:0] ALUResultM, WriteDataM, ExtImmM, PCPlus4M; 17 | 18 | regPipe #(1) regWriteReg(clk, rst, 1'b0, 1'b1, RegWriteE, RegWriteM); 19 | regPipe #(1) memWriteReg(clk, rst, 1'b0, 1'b1, memWriteE, memWriteM); 20 | regPipe #(1) luiReg(clk, rst, 1'b0, 1'b1, LUIInstrE, LUIInstrM); 21 | regPipe #(2) resultSrcReg(clk, rst, 1'b0, 1'b1, ResultSrcE, ResultSrcM); 22 | 23 | regPipe #(5) RdReg(clk, rst, 1'b0, 1'b1, RdE, RdM); 24 | regPipe #(32) ALUResultReg(clk, rst, 1'b0, 1'b1, ALUResultE, ALUResultM); 25 | regPipe #(32) writeDataReg(clk, rst, 1'b0, 1'b1, WriteDataE, WriteDataM); 26 | regPipe #(32) extImmReg(clk, rst, 1'b0, 1'b1, ExtImmE, ExtImmM); 27 | regPipe #(32) pcPlus4Reg(clk, rst, 1'b0, 1'b1, PCPlus4E, PCPlus4M); 28 | endmodule 29 | -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/pipeFD.v: -------------------------------------------------------------------------------- 1 | module pipeFD(clk, rst, en, clr, 2 | InstrF, PCF, PCPlus4F, 3 | InstrD, PCD, PCPlus4D); 4 | 5 | input clk, rst, en, clr; 6 | input [31:0] InstrF, PCF, PCPlus4F; 7 | output [31:0] InstrD, PCD, PCPlus4D; 8 | 9 | regPipe #(32) instrReg(clk, rst, clr, en, InstrF, InstrD); 10 | regPipe #(32) pcReg(clk, rst, clr, en, PCF, PCD); 11 | regPipe #(32) pcPlus4Reg(clk, rst, clr, en, PCPlus4F, PCPlus4D); 12 | endmodule 13 | -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/pipeMW.v: -------------------------------------------------------------------------------- 1 | module pipeMW(clk, rst, 2 | RegWriteM, ResultSrcM, 3 | ReadDataM, RdM, ExtImmM, PCPlus4M, ALUResultM, 4 | RegWriteW, ResultSrcW, 5 | ReadDataW, RdW, ExtImmW, PCPlus4W, ALUResultW); 6 | 7 | input clk, rst; 8 | input RegWriteM; 9 | input [1:0] ResultSrcM; 10 | input [4:0] RdM; 11 | input [31:0] ReadDataM, ExtImmM, PCPlus4M, ALUResultM; 12 | output RegWriteW; 13 | output [1:0] ResultSrcW; 14 | output [4:0] RdW; 15 | output [31:0] ReadDataW, ExtImmW, PCPlus4W, ALUResultW; 16 | 17 | regPipe #(1) regWriteReg(clk, rst, 1'b0, 1'b1, RegWriteM, RegWriteW); 18 | regPipe #(2) resultSrcReg(clk, rst, 1'b0, 1'b1, ResultSrcM, ResultSrcW); 19 | 20 | regPipe #(5) RdReg(clk, rst, 1'b0, 1'b1, RdM, RdW); 21 | regPipe #(32) readDataReg(clk, rst, 1'b0, 1'b1, ReadDataM, ReadDataW); 22 | regPipe #(32) extImmReg(clk, rst, 1'b0, 1'b1, ExtImmM, ExtImmW); 23 | regPipe #(32) ALUResReg(clk, rst, 1'b0, 1'b1, ALUResultM, ALUResultW); 24 | regPipe #(32) pcPlus4Reg(clk, rst, 1'b0, 1'b1, PCPlus4M, PCPlus4W); 25 | endmodule 26 | -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/reg32B.v: -------------------------------------------------------------------------------- 1 | module reg32B(clk, rst, en, dataIn, dataOut); 2 | input clk, rst, en; 3 | input [31:0] dataIn; 4 | output [31:0] dataOut; 5 | reg [31:0] savedData; 6 | 7 | always @(posedge clk, posedge rst) begin 8 | if (rst) 9 | savedData = 32'b0; 10 | 11 | else if (en) 12 | savedData = dataIn; 13 | end 14 | 15 | assign dataOut = savedData; 16 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/regPipe.v: -------------------------------------------------------------------------------- 1 | module regPipe(clk, rst, clr, en, dataIn, dataOut); 2 | parameter SIZE; 3 | input clk, rst, clr, en; 4 | input [SIZE-1:0] dataIn; 5 | output [SIZE-1:0] dataOut; 6 | reg [SIZE-1:0] savedData; 7 | 8 | always @(posedge clk, posedge rst) begin 9 | if (rst || clr) 10 | savedData = 0; 11 | else if (en) 12 | savedData = dataIn; 13 | end 14 | 15 | assign dataOut = savedData; 16 | endmodule -------------------------------------------------------------------------------- /CA4-RISC-V Pipeline/registerFile.v: -------------------------------------------------------------------------------- 1 | module registerFile(clk, rst, A1, A2, A3, WE, WD, RD1, RD2); 2 | input clk, rst; 3 | input [19:15] A1; 4 | input [24:20] A2; 5 | input [4:0] A3; 6 | input WE; 7 | input [31:0] WD; 8 | output [31:0] RD1, RD2; 9 | integer i; 10 | 11 | reg [31:0] registers [0:31]; 12 | initial begin 13 | registers[0] <= 32'b0; // ZERO register 14 | end 15 | 16 | always @(negedge clk, posedge rst) begin 17 | if (rst) begin 18 | for (i = 0; i < 32; i = i + 1) 19 | registers[i] = 32'b0; 20 | end 21 | else if (WE && A3 != 5'b0) begin 22 | registers[A3] = WD; 23 | end 24 | end 25 | assign RD1 = registers[A1]; 26 | assign RD2 = registers[A2]; 27 | endmodule 28 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 Mobina Mehrazar 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Computer-Architecture-Course-Projects-S2023 2 | 3 | **Contributors:** 4 | 5 | [Mobina Mehrazar](https://github.com/MobinaMhr) 6 | 7 | [Mohammad Nemati](https://github.com/mmd-nemati) 8 | --------------------------------------------------------------------------------