├── .gitignore ├── Document ├── algorithm_specific.md ├── command.md └── pic │ ├── 屏幕截图 2023-11-13 143918.png │ ├── 屏幕截图 2023-11-13 150736.png │ ├── 屏幕截图 2023-11-17 124110.png │ ├── 屏幕截图 2023-11-19 150138.png │ ├── 屏幕截图 2023-11-19 150756.png │ ├── 屏幕截图 2023-11-19 150900.png │ ├── 屏幕截图 2023-11-19 151022.png │ ├── 屏幕截图 2023-11-19 151138.png │ ├── 屏幕截图 2023-11-19 151338.png │ ├── 屏幕截图 2023-11-19 151432.png │ ├── 屏幕截图 2023-11-19 151544.png │ ├── 屏幕截图 2023-11-19 151719.png │ └── 绘图1.vsdx ├── FPGA ├── bitstream_backup │ ├── fpga_top.sbit │ ├── hdmi_ov5640_single.sbit │ └── video_splicing.sbit ├── constraint_backup.fdc ├── ethernet_character_1.txt └── rom_init_file │ ├── display_angle.dat │ ├── display_now_input.dat │ ├── display_scale.dat │ ├── display_total_input.dat │ └── rom_for_number.dat ├── LICENSE ├── RTL ├── aq_axi_master.v ├── axi_interconnect_rd.v ├── axi_interconnect_rd_backup.v ├── axi_interconnect_wr.v ├── axi_interconnect_wr_backup.v ├── cmos_add.v ├── ddr_rd_buf.v ├── ddr_rd_buf_backup.v ├── fpga_top.v ├── hdmi_data_in.v ├── hdmi_data_in_backup.v ├── image_adjust.v ├── image_brief.v ├── image_global.v ├── image_process.v ├── image_rotation_backup.v ├── image_scale_backup.v ├── main.filelist ├── rtl_1 │ ├── cmos_8_16bit.v │ ├── fram_buf.v │ ├── hdmi_ddr_ov5640_top.v │ ├── i2c_com.v │ ├── iic_dri.v │ ├── ms7200_ctl.v │ ├── ms7210_ctl.v │ ├── ms72xx_ctl.v │ ├── power_on_delay.v │ ├── rd_buf.v │ ├── rd_ctrl.v │ ├── reg_config.v │ ├── reg_config_1.v │ ├── sync_vg.v │ ├── wr_buf.v │ ├── wr_cmd_trans.v │ ├── wr_ctrl.v │ └── wr_rd_ctrl_top.v ├── rtl_2 │ ├── arp_cache.v │ ├── arp_rx.v │ ├── arp_tx.v │ ├── color_bar.v │ ├── crc.v │ ├── ethernet_character.v │ ├── ethernet_test.v │ ├── icmp_reply.v │ ├── ip_rx.v │ ├── ip_tx.v │ ├── ip_tx_mode.v │ ├── mac_rx.v │ ├── mac_rx_top.v │ ├── mac_test.v │ ├── mac_top.v │ ├── mac_tx.v │ ├── mac_tx_mode.v │ ├── mac_tx_top.v │ ├── osd_display.v │ ├── timing_gen_xy.v │ ├── udp_rx.v │ ├── udp_tx.v │ └── util_gmii_to_rgmii.v ├── rtl_3 │ ├── coor_trans.v │ ├── coor_trans_forward.v │ ├── coor_trans_reverse.v │ ├── cos_table.v │ └── sin_table.v ├── testbench │ ├── axi_interconnect_rd_tb.v │ ├── axi_interconnect_wr_tb.v │ ├── test_hdmi_data_in.v │ └── video_sampling_tb.v ├── uart_rx.v ├── uart_trans.v ├── uart_tx.v ├── video_fusion.v ├── video_sampling.v ├── video_sampling_1.v ├── video_sampling_1_backup.v ├── video_sampling_2.v ├── video_sampling_2_backup.v └── video_sampling_backup.v ├── Software └── auto_test.py └── readme.md /.gitignore: -------------------------------------------------------------------------------- 1 | /project.old 2 | /Document/datasheet 3 | /Document/ip_settings.md 4 | Software/character_pixel_software/ -------------------------------------------------------------------------------- /Document/algorithm_specific.md: -------------------------------------------------------------------------------- 1 | 26 | # 算法细节 27 | 28 | ## 任意角度旋转 29 | 30 | 旋转后的坐标通常不是按照显示顺序排列的，而 HDMI 输出需要按照 VESA 时序要求将图像数据按行列顺序进行输出。因此，我们需要解决如何将旋转后的图像数据重新排序以满足 HDMI 输出的顺序要求。 31 | 32 | 要实现这一点，可以考虑使用反向映射（Backward Mapping）和帧缓存的方法。我们从输出图像的每个像素点反向计算出对应的原始图像中的坐标，从而直接生成按顺序排列的图像数据。 33 | 34 | 为了避免使用浮点运算，可以将三角函数的值预先计算并放大一定倍数（比如 256 倍），然后存储在 ROM 中。每当需要进行坐标变换时，可以直接使用这些放大的系数进行乘法运算，并在计算结束后通过移位操作将结果还原到原始坐标系统。 35 | 36 | 在每一个像素 `(x', y')`的位置，需要计算其对应的原始图像中的坐标 `(x, y)`。公式如下： 37 | 38 | $$\begin{bmatrix} 39 | x \\ 40 | y 41 | \end{bmatrix} = 42 | \frac{1}{256} 43 | \begin{bmatrix} 44 | \cos(\theta) \times 256 & \sin(\theta) \times 256 \\ 45 | -\sin(\theta) \times 256 & \cos(\theta) \times 256 46 | \end{bmatrix} 47 | \begin{bmatrix} 48 | x' \\ 49 | y' 50 | \end{bmatrix}$$ 51 | 52 | 由于 $\cos(θ) \times 256$ 和 $\sin(θ) \times 256$ 都是整数，我们可以直接进行乘法运算，并在结果得到后右移 8 位来实现除以 256 的操作。 53 | 54 | ## FPGA 固定角度旋转实现 55 | 56 | 1. AXI 突发读取操作 57 | 58 | 每一行有 960 个像素，按照代码设定，`burst_len=10`。每次 AXI 读事务读取 160 个像素（256 位数据对应 16 个像素，`burst_len=10` 则读取 160 个像素）。 59 | 60 | 因此，读取完整一行 960 个像素需要 6 次 AXI 突发读取操作。 61 | 62 | 2. `addr_cnt` 的作用 63 | `addr_cnt` 用来计数每行的读事务数。当 `addr_cnt` 达到 6 时（即读完 960 个像素），`addr_cnt` 复位为 0，开始下一行的读取。 64 | 65 | 每次 `addr_cnt` 增加时，`reg_axi_araddr` 用于更新 AXI 读地址。尽管 `rotate_mode=1` 时 `reg_axi_araddr_5` 是倒序更新的，但由于一次突发读取会返回多个顺序排列的像素，这些像素还是按顺序排列的。 66 | 67 | 3. RAM 写入操作 68 | 69 | AXI 从 DDR 中顺序读取出一行的 160 个像素，按正序写入 RAM。这个过程是连续进行的，直到完成一整行（960 个像素）的读取。 70 | 71 | 写入 RAM 的地址 `wr_addr` 逐次增加，因此一行数据在 RAM 中是顺序存储的。 72 | 73 | 4. RAM 读取操作 74 | 75 | 在 `rotate_mode=1` 的情况下，读取操作是按行完全逆序进行的。也就是说，`rd_addr` 从高地址开始（例如 959），逐渐减少直到 0。 76 | 77 | 这样，通过逆序读取，输出的数据是按原行像素的倒序排列，达到了 180 度旋转的效果。 -------------------------------------------------------------------------------- /Document/command.md: -------------------------------------------------------------------------------- 1 | # UART 输入指令密码表 2 | 3 | UART 输入 8 位数据用于指令控制，其中高 4 位作为控制信道，低 4 位作为数据信道。控制信道对应如下表格工作： 4 | 5 | | `command_in[7:4]` | 控制内容 | 6 | | :---: | :--- | 7 | | 4'b0000 | default | 8 | | 4'b0010 | 图像缩放模式（zoom_in） | 9 | | 4'b0011 | 图像旋转模式（rotate） | 10 | | 4'b0100 | 图像翻转模式（mirror） | 11 | | 4'b0101 | 图像纵向平移模式（y_shift）| 12 | | 4'b0110 | 图像灰阶处理 | 13 | | 4'b0111 | 图像亮度更改 | 14 | | 4'b1000 | 图像色度更改 | 15 | | 4'b1111 | 切换显示源 | 16 | 17 | 数据信道对应如下表格工作： 18 | 19 | | `command_in[3:0]` | 数值内容 | 20 | | :---: | :--- | 21 | | 4'b0000 | 不作任何更改 | 22 | | 4'b1xxx | 负数位（如果需要） | 23 | | 4'b0xxx | 正数位 | 24 | | 4'bx001 | 数值在原来的基础上更改 1（对于当前模式的更改）| 25 | | 4'bx010 | 数值在原来的基础上更改 2 | 26 | | $\cdots$ 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0000007800000078000C000000000E00C0E1FFFFC0E1FFFF001E0000001E0F00C0E3FFFFC0E3FFFF000EFCFF000F0F00C0E37F00C0E37F00001FFCFF000F0F008007303080073030003F8007800F0F0000C7713800C77138807F800380FFFF1F00CF713C00CF713CC073C003C0FFFF1F0080731C0080731CC0F3FC1FC0FFFF1F0080110E0080110EE0E1FC3FE08107000000000600000006F0CEFD3FF0810700F0800300F0800300784E1C38F8800700F0C3FF3FF0C3FF3F380ECE3978800700F0E3FF1FF0E3FF1F001CCE392080070080F3FF1F80F3FF1F001CCE190080070080737800807378000000CE1D008003008003780080037800F03FEE1DF0FFFF3FC0F3FF3FC0F3FF3FF87FEE1DF0FFFF3FC0FBFF3FC0FBFF3FF87FEE1CF8FFFF3FC0FBFF3FC0FBFF3F0078E71C003C1C00C0013800C00138000038E71C001C1E00C071381EC071381E003CE71C001E1E00C071380EC071380E203CF70E001E1E00E0713C0EE0713C0E701E770E001E1E00E0713C0EE0713C0EF80E770E000F1E00E0F9FF0FE0F9FF0FF00FF801800F1E00E0F9FF0FE0F9FF0FE007FC0380070E3CF0070000F0070000C0039C07E0030F3CF81F0010F81F001080071F0FF0030F3C3EFF003F3EFF003F00870F1EFC001E1E1EFCFF3F1EFCFF3F00CF073E7F00FE1F0CF0FF0F0CF0FF0F00C6011C1E00FC0F00003E0000003E00008000000600F803 -------------------------------------------------------------------------------- /FPGA/rom_init_file/display_angle.dat: -------------------------------------------------------------------------------- 1 | 00 2 | 00 3 | 00 4 | 00 5 | 00 6 | 00 7 | 00 8 | 00 9 | 00 10 | 00 11 | 00 12 | 00 13 | 00 14 | 00 15 | 00 16 | 00 17 | 00 18 | 00 19 | 00 20 | 00 21 | 00 22 | 00 23 | 00 24 | 00 25 | 00 26 | 00 27 | 00 28 | 00 29 | 00 30 | 00 31 | 00 32 | 00 33 | 00 34 | 00 35 | 00 36 | 00 37 | 00 38 | 00 39 | 00 40 | 00 41 | 00 42 | 00 43 | 00 44 | 00 45 | 00 46 | 00 47 | 00 48 | 00 49 | 00 50 | 00 51 | 00 52 | 00 53 | 00 54 | 00 55 | 00 56 | 00 57 | 00 58 | 00 59 | 0F 60 | 3C 61 | 00 62 | C0 63 | 03 64 | 78 65 | 00 66 | 00 67 | 07 68 | 00 69 | 00 70 | 00 71 | 3C 72 | 00 73 | 00 74 | 00 75 | 00 76 | 00 77 | 00 78 | 0F 79 | 3C 80 | 00 81 | C0 82 | 03 83 | 3C 84 | 00 85 | 80 86 | 07 87 | 00 88 | 00 89 | 00 90 | 3C 91 | 00 92 | 00 93 | 00 94 | 00 95 | 00 96 | 00 97 | 07 98 | 3C 99 | 00 100 | C0 101 | 03 102 | 3C 103 | 00 104 | 80 105 | FF 106 | 07 107 | 00 108 | FE 109 | FF 110 | 7F 111 | 00 112 | 00 113 | 00 114 | 00 115 | 00 116 | 07 117 | FE 118 | 1F 119 | C0 120 | 03 121 | 3C 122 | 00 123 | C0 124 | FF 125 | 0F 126 | 00 127 | FF 128 | FF 129 | 7F 130 | 00 131 | 00 132 | 00 133 | 00 134 | F0 135 | 7F 136 | FE 137 | 1F 138 | E0 139 | C1 140 | FF 141 | 07 142 | E0 143 | FF 144 | 0F 145 | 00 146 | FF 147 | FF 148 | 7F 149 | 00 150 | 00 151 | 00 152 | 00 153 | F8 154 | 7F 155 | FF 156 | 1F 157 | F8 158 | FF 159 | FF 160 | 07 161 | F0 162 | FF 163 | 0F 164 | 00 165 | FF 166 | FF 167 | 7F 168 | 00 169 | 00 170 | 00 171 | 00 172 | F8 173 | 7F 174 | FF 175 | 1F 176 | FC 177 | FF 178 | FF 179 | 07 180 | F0 181 | 80 182 | 0F 183 | 00 184 | 0F 185 | 00 186 | 00 187 | 00 188 | 00 189 | 00 190 | 00 191 | F8 192 | FF 193 | 07 194 | 00 195 | FC 196 | DF 197 | FF 198 | 07 199 | F8 200 | C0 201 | 07 202 | 00 203 | 8F 204 | 87 205 | 07 206 | 00 207 | 00 208 | 00 209 | 00 210 | E0 211 | C1 212 | 07 213 | 00 214 | FC 215 | 1F 216 | 1E 217 | 00 218 | FC 219 | FF 220 | 3F 221 | 00 222 | 8F 223 | 87 224 | 07 225 | 00 226 | 00 227 | 00 228 | 00 229 | E0 230 | C1 231 | 03 232 | 00 233 | F0 234 | 00 235 | 1E 236 | 00 237 | FE 238 | FF 239 | FF 240 | 00 241 | FF 242 | FF 243 | 3F 244 | 00 245 | 00 246 | 00 247 | 00 248 | E0 249 | E1 250 | FF 251 | 03 252 | F0 253 | 00 254 | 1F 255 | 00 256 | FF 257 | FF 258 | FF 259 | 80 260 | FF 261 | FF 262 | 7F 263 | 00 264 | 00 265 | 00 266 | 00 267 | E0 268 | C1 269 | FF 270 | 0F 271 | F8 272 | 03 273 | 0F 274 | 80 275 | FF 276 | FF 277 | FF 278 | 80 279 | FF 280 | FF 281 | 3F 282 | 00 283 | 00 284 | 00 285 | 00 286 | E0 287 | 81 288 | FF 289 | 0F 290 | F8 291 | F3 292 | FF 293 | 87 294 | F7 295 | F0 296 | E0 297 | 80 298 | FF 299 | FF 300 | 3F 301 | 00 302 | 00 303 | 00 304 | 00 305 | E0 306 | 9F 307 | FF 308 | 0F 309 | F8 310 | F3 311 | FF 312 | 07 313 | F3 314 | F0 315 | F0 316 | 80 317 | C7 318 | 83 319 | 07 320 | C0 321 | 03 322 | 00 323 | 00 324 | E0 325 | 1F 326 | 70 327 | 0E 328 | FC 329 | F3 330 | FF 331 | 07 332 | F0 333 | F0 334 | F0 335 | 80 336 | C7 337 | 83 338 | 03 339 | C0 340 | 07 341 | 00 342 | 00 343 | F0 344 | 1F 345 | 70 346 | 0F 347 | FC 348 | F3 349 | FF 350 | 07 351 | F0 352 | F0 353 | F0 354 | 80 355 | C7 356 | C3 357 | 03 358 | E0 359 | 07 360 | 00 361 | 00 362 | F0 363 | 1E 364 | 78 365 | 0F 366 | FC 367 | 83 368 | 07 369 | 00 370 | F0 371 | FF 372 | FF 373 | 80 374 | C7 375 | FF 376 | 03 377 | E0 378 | 07 379 | 00 380 | 00 381 | F0 382 | 9E 383 | 7B 384 | 0F 385 | FE 386 | CF 387 | 07 388 | 00 389 | F8 390 | FF 391 | FF 392 | 80 393 | C7 394 | FF 395 | 03 396 | E0 397 | 03 398 | 00 399 | 00 400 | F0 401 | 9E 402 | 7B 403 | 07 404 | FE 405 | CF 406 | 03 407 | 00 408 | F8 409 | FF 410 | FF 411 | 80 412 | C7 413 | FF 414 | 03 415 | C0 416 | 01 417 | 00 418 | 00 419 | F0 420 | DE 421 | 7B 422 | 07 423 | FE 424 | CF 425 | FF 426 | 01 427 | 78 428 | 78 429 | F0 430 | C0 431 | 03 432 | 00 433 | 00 434 | 00 435 | 00 436 | 00 437 | 00 438 | F0 439 | DE 440 | 7B 441 | 00 442 | CC 443 | E1 444 | FF 445 | 01 446 | 78 447 | 78 448 | 70 449 | C0 450 | 03 451 | 00 452 | 00 453 | 00 454 | 00 455 | 00 456 | 00 457 | F0 458 | DE 459 | 7B 460 | 00 461 | E0 462 | E1 463 | FF 464 | 01 465 | 78 466 | 78 467 | 70 468 | C0 469 | FB 470 | FF 471 | 07 472 | 00 473 | 00 474 | 00 475 | 00 476 | 70 477 | DE 478 | FB 479 | 03 480 | E0 481 | F1 482 | FF 483 | 01 484 | 78 485 | 78 486 | 78 487 | C0 488 | FB 489 | FF 490 | 07 491 | 00 492 | 00 493 | 00 494 | 00 495 | 78 496 | CE 497 | F9 498 | 03 499 | E0 500 | F1 501 | F0 502 | 01 503 | FC 504 | FF 505 | 7F 506 | C0 507 | FF 508 | FF 509 | 07 510 | 00 511 | 00 512 | 00 513 | 00 514 | 78 515 | CE 516 | F9 517 | 03 518 | E0 519 | 8F 520 | F0 521 | 00 522 | FC 523 | FF 524 | 7F 525 | C0 526 | FF 527 | FF 528 | 07 529 | 00 530 | 00 531 | 00 532 | 00 533 | 78 534 | CE 535 | 3D 536 | 00 537 | FC 538 | CF 539 | F8 540 | 00 541 | FC 542 | FF 543 | 7F 544 | E0 545 | E1 546 | C1 547 | 07 548 | 00 549 | 00 550 | 00 551 | 00 552 | 78 553 | CF 554 | 3D 555 | 00 556 | FF 557 | EF 558 | 79 559 | 00 560 | 3C 561 | 38 562 | 78 563 | E0 564 | E1 565 | E3 566 | 03 567 | 00 568 | 00 569 | 00 570 | 00 571 | 78 572 | EF 573 | 3D 574 | 00 575 | FF 576 | F7 577 | 7F 578 | 00 579 | 1E 580 | 3C 581 | 78 582 | E0 583 | C1 584 | F7 585 | 01 586 | 00 587 | 00 588 | 00 589 | 00 590 | 38 591 | EF 592 | 3F 593 | 00 594 | FF 595 | E1 596 | 3F 597 | 00 598 | 1E 599 | 3C 600 | 78 601 | E0 602 | 81 603 | FF 604 | 00 605 | 00 606 | 00 607 | 00 608 | 00 609 | 3C 610 | EF 611 | 3F 612 | 00 613 | E3 614 | C0 615 | 1F 616 | 00 617 | 1F 618 | 3C 619 | 78 620 | F0 621 | 01 622 | 7F 623 | 00 624 | F0 625 | 00 626 | 00 627 | 00 628 | 3C 629 | EF 630 | 3F 631 | 00 632 | E0 633 | 80 634 | 1F 635 | 00 636 | 0F 637 | 3C 638 | 38 639 | F0 640 | 80 641 | 7F 642 | 00 643 | F0 644 | 01 645 | 00 646 | 00 647 | 7C 648 | FF 649 | 3F 650 | 00 651 | F0 652 | 00 653 | 1F 654 | 80 655 | 0F 656 | BC 657 | 3D 658 | F0 659 | E0 660 | FF 661 | 01 662 | F8 663 | 01 664 | 00 665 | 00 666 | 7E 667 | F7 668 | FF 669 | 07 670 | F0 671 | 00 672 | 3E 673 | 80 674 | 0F 675 | FC 676 | 3F 677 | F8 678 | FE 679 | FF 680 | 0F 681 | F8 682 | 01 683 | 00 684 | 00 685 | FE 686 | 77 687 | FE 688 | 07 689 | F0 690 | 00 691 | 3C 692 | C0 693 | 07 694 | FC 695 | 3F 696 | 78 697 | FF 698 | E1 699 | 1F 700 | F8 701 | 00 702 | 00 703 | 00 704 | FE 705 | 7F 706 | FC 707 | 07 708 | F0 709 | 00 710 | 7C 711 | C0 712 | 03 713 | FC 714 | 1F 715 | 78 716 | 7F 717 | C0 718 | 0F 719 | 00 720 | 00 721 | 00 722 | 00 723 | CC 724 | 73 725 | F8 726 | 03 727 | F0 728 | 00 729 | 38 730 | 80 731 | 03 732 | 9C 733 | 1F 734 | 70 735 | 0E 736 | 00 737 | 0E 738 | 00 739 | 00 740 | 00 741 | 00 742 | 00 743 | 00 744 | 00 745 | 00 746 | 00 747 | 00 748 | 00 749 | 00 750 | 00 751 | 00 752 | 00 753 | 00 754 | 00 755 | 00 756 | 00 757 | 00 758 | 00 759 | 00 760 | 00 761 | 00 762 | 00 763 | 00 764 | 00 765 | 00 766 | 00 767 | 00 768 | 00 769 | 00 770 | 00 771 | 00 772 | 00 773 | 00 774 | 00 775 | 00 776 | 00 777 | 00 778 | 00 779 | 00 780 | 00 781 | 00 782 | 00 783 | 00 784 | 00 785 | 00 786 | 00 787 | 00 788 | 00 789 | 00 790 | 00 791 | 00 792 | 00 793 | 00 794 | 00 795 | 00 796 | 00 797 | 00 798 | 00 799 | 00 800 | 00 801 | 00 802 | 00 803 | 00 804 | 00 805 | 00 806 | 00 807 | 00 808 | 00 809 | 00 810 | 00 811 | 00 812 | 00 813 | 00 814 | 00 815 | 00 816 | 00 817 | 00 818 | 00 819 | 00 820 | 00 821 | 00 822 | 00 823 | 00 824 | 00 825 | 00 826 | 00 827 | 00 828 | 00 829 | 00 830 | 00 831 | 00 832 | 00 833 | 00 834 | 00 835 | 00 836 | 00 837 | 00 838 | 00 839 | 00 840 | 00 841 | 00 842 | 00 843 | 00 844 | 00 845 | 00 846 | 00 847 | 00 848 | 00 849 | 00 850 | 00 851 | 00 852 | 00 853 | 00 854 | 00 855 | 00 856 | -------------------------------------------------------------------------------- /FPGA/rom_init_file/display_now_input.dat: -------------------------------------------------------------------------------- 1 | 00 2 | 00 3 | 00 4 | 00 5 | 00 6 | 00 7 | 00 8 | 00 9 | 00 10 | 00 11 | 00 12 | 00 13 | 00 14 | 00 15 | 00 16 | 00 17 | 00 18 | 00 19 | 00 20 | 00 21 | 00 22 | 00 23 | 00 24 | 00 25 | 00 26 | 00 27 | 00 28 | 00 29 | 00 30 | 00 31 | 00 32 | 00 33 | 00 34 | 00 35 | 00 36 | 00 37 | 00 38 | 00 39 | 00 40 | 00 41 | 00 42 | 00 43 | 00 44 | 00 45 | 00 46 | 00 47 | 00 48 | 00 49 | 00 50 | 00 51 | 00 52 | 00 53 | 00 54 | 00 55 | 00 56 | 00 57 | 00 58 | 00 59 | 80 60 | 0F 61 | 00 62 | 00 63 | 07 64 | 38 65 | 00 66 | 00 67 | 00 68 | 00 69 | 00 70 | 00 71 | 0E 72 | 0E 73 | 00 74 | 00 75 | 00 76 | 00 77 | 00 78 | 81 79 | 07 80 | 02 81 | 80 82 | 07 83 | 78 84 | 00 85 | 1E 86 | FE 87 | 7F 88 | 80 89 | 07 90 | 1E 91 | 1E 92 | 00 93 | 00 94 | 00 95 | 00 96 | C0 97 | 83 98 | 07 99 | 0E 100 | 80 101 | 07 102 | 7C 103 | 00 104 | 1E 105 | FE 106 | FF 107 | 80 108 | 07 109 | 1E 110 | 1E 111 | 00 112 | 00 113 | 00 114 | 00 115 | C0 116 | 83 117 | 07 118 | 0F 119 | 00 120 | 0F 121 | 3C 122 | 00 123 | 3E 124 | FE 125 | FF 126 | 80 127 | 0F 128 | 1C 129 | 0F 130 | 00 131 | 00 132 | 00 133 | 00 134 | C0 135 | 83 136 | 07 137 | 0F 138 | 00 139 | 0F 140 | 3E 141 | 00 142 | 3C 143 | FE 144 | FF 145 | 00 146 | 0F 147 | 1C 148 | 0F 149 | 00 150 | 00 151 | 00 152 | 00 153 | C0 154 | 83 155 | 87 156 | 0F 157 | FC 158 | FF 159 | FF 160 | 07 161 | 7C 162 | 30 163 | 78 164 | 00 165 | DF 166 | FF 167 | 3F 168 | 00 169 | 00 170 | 00 171 | 00 172 | C0 173 | 87 174 | 87 175 | 07 176 | FC 177 | FF 178 | FF 179 | 07 180 | 78 181 | 78 182 | 3C 183 | 00 184 | DE 185 | FF 186 | 3F 187 | 00 188 | 00 189 | 00 190 | 00 191 | 80 192 | 87 193 | C7 194 | 07 195 | FC 196 | FF 197 | FF 198 | 07 199 | 78 200 | F8 201 | 3E 202 | 00 203 | DE 204 | FF 205 | 3F 206 | 00 207 | 00 208 | 00 209 | 00 210 | 80 211 | 87 212 | E7 213 | 03 214 | FC 215 | FF 216 | FF 217 | 07 218 | 10 219 | F0 220 | 1F 221 | 00 222 | 0E 223 | F0 224 | 00 225 | 00 226 | 00 227 | 00 228 | 00 229 | 80 230 | C7 231 | E7 232 | 03 233 | 00 234 | 00 235 | 00 236 | 00 237 | 00 238 | FF 239 | 7F 240 | 00 241 | 00 242 | F8 243 | 00 244 | 00 245 | 00 246 | 00 247 | 00 248 | 00 249 | C3 250 | C7 251 | 01 252 | F0 253 | 1F 254 | E0 255 | 01 256 | 00 257 | FF 258 | FF 259 | 00 260 | 80 261 | FF 262 | 0F 263 | 00 264 | 00 265 | 00 266 | 00 267 | 00 268 | C0 269 | 03 270 | 00 271 | F8 272 | 3F 273 | EF 274 | 01 275 | 00 276 | FF 277 | FF 278 | 00 279 | 80 280 | FF 281 | 1F 282 | 00 283 | 00 284 | 00 285 | 00 286 | 00 287 | C0 288 | 03 289 | 00 290 | F8 291 | 7F 292 | EF 293 | 81 294 | 9F 295 | C7 296 | F1 297 | E0 298 | 8F 299 | FF 300 | 1F 301 | 00 302 | 00 303 | 00 304 | 00 305 | E0 306 | FF 307 | FF 308 | 01 309 | F8 310 | 3F 311 | E7 312 | 81 313 | BF 314 | C7 315 | F1 316 | E0 317 | DF 318 | FF 319 | 1F 320 | C0 321 | 03 322 | 00 323 | 00 324 | E0 325 | FF 326 | FF 327 | 07 328 | 78 329 | 38 330 | E7 331 | 81 332 | BF 333 | E7 334 | F1 335 | E0 336 | DF 337 | 03 338 | 1E 339 | C0 340 | 07 341 | 00 342 | 00 343 | E0 344 | FF 345 | FF 346 | 07 347 | 38 348 | 3C 349 | E7 350 | 81 351 | BF 352 | FF 353 | FF 354 | E0 355 | DF 356 | 03 357 | 1E 358 | E0 359 | 07 360 | 00 361 | 00 362 | E0 363 | FF 364 | FF 365 | 07 366 | 38 367 | BC 368 | E7 369 | 01 370 | BC 371 | FF 372 | 7F 373 | 00 374 | DF 375 | FF 376 | 1F 377 | E0 378 | 07 379 | 00 380 | 00 381 | 00 382 | 00 383 | 80 384 | 07 385 | F8 386 | BF 387 | E7 388 | 00 389 | BC 390 | FF 391 | 7F 392 | 00 393 | CF 394 | FF 395 | 0F 396 | E0 397 | 03 398 | 00 399 | 00 400 | 00 401 | 00 402 | 80 403 | 07 404 | F8 405 | BF 406 | E7 407 | 00 408 | BC 409 | E3 410 | 79 411 | 00 412 | CF 413 | FF 414 | 0F 415 | C0 416 | 01 417 | 00 418 | 00 419 | 00 420 | 00 421 | 80 422 | 07 423 | FC 424 | BF 425 | F7 426 | 00 427 | 9C 428 | E3 429 | 78 430 | 00 431 | CF 432 | 03 433 | 0F 434 | 00 435 | 00 436 | 00 437 | 00 438 | 00 439 | 00 440 | C0 441 | 07 442 | 3C 443 | BC 444 | F7 445 | 00 446 | 9E 447 | E3 448 | 78 449 | 00 450 | CF 451 | 03 452 | 0F 453 | 00 454 | 00 455 | 00 456 | 00 457 | 00 458 | 00 459 | C0 460 | 07 461 | 3C 462 | BC 463 | F7 464 | 00 465 | DE 466 | FF 467 | 7F 468 | 00 469 | CF 470 | FF 471 | 0F 472 | 00 473 | 00 474 | 00 475 | 00 476 | E0 477 | FF 478 | FF 479 | 03 480 | 3C 481 | BC 482 | F7 483 | 00 484 | DE 485 | FF 486 | 7F 487 | 00 488 | CF 489 | FF 490 | 0F 491 | 00 492 | 00 493 | 00 494 | 00 495 | E0 496 | FF 497 | FF 498 | 03 499 | FC 500 | BF 501 | F3 502 | 00 503 | DE 504 | FF 505 | 7F 506 | 00 507 | EF 508 | FF 509 | 0F 510 | 00 511 | 00 512 | 00 513 | 00 514 | E0 515 | FF 516 | FF 517 | 03 518 | FC 519 | 9F 520 | F3 521 | 00 522 | DE 523 | F3 524 | 78 525 | 00 526 | EF 527 | FF 528 | 0F 529 | 00 530 | 00 531 | 00 532 | 00 533 | E0 534 | FF 535 | FF 536 | 03 537 | FC 538 | 9F 539 | F3 540 | 00 541 | DE 542 | F3 543 | 38 544 | 80 545 | E7 546 | 01 547 | 0F 548 | 00 549 | 00 550 | 00 551 | 00 552 | 00 553 | 00 554 | C0 555 | 03 556 | FC 557 | DF 558 | F3 559 | 00 560 | DE 561 | F1 562 | 3C 563 | 80 564 | E7 565 | 01 566 | 07 567 | 00 568 | 00 569 | 00 570 | 00 571 | 00 572 | 00 573 | C0 574 | 03 575 | 1C 576 | DE 577 | 73 578 | 00 579 | DE 580 | F1 581 | 3E 582 | 80 583 | E7 584 | FF 585 | 07 586 | 00 587 | 00 588 | 00 589 | 00 590 | 00 591 | 00 592 | C0 593 | 03 594 | 1E 595 | DE 596 | 7B 597 | 00 598 | CF 599 | F1 600 | 3E 601 | 80 602 | E7 603 | FF 604 | 07 605 | 00 606 | 00 607 | 00 608 | 00 609 | 00 610 | 00 611 | E0 612 | 03 613 | 1E 614 | 1E 615 | 78 616 | 00 617 | DF 618 | 01 619 | 1E 620 | C0 621 | EF 622 | FF 623 | 07 624 | F0 625 | 00 626 | 00 627 | 00 628 | 00 629 | 00 630 | E0 631 | 03 632 | 1E 633 | 1E 634 | 78 635 | 80 636 | 3F 637 | 00 638 | 0E 639 | E0 640 | 1F 641 | 00 642 | 00 643 | F0 644 | 01 645 | 00 646 | 00 647 | F8 648 | FF 649 | FF 650 | 01 651 | DE 652 | DE 653 | 79 654 | C0 655 | FF 656 | 01 657 | 38 658 | F0 659 | 7F 660 | 00 661 | 0E 662 | F8 663 | 01 664 | 00 665 | 00 666 | F8 667 | FF 668 | FF 669 | 01 670 | FE 671 | DE 672 | 7B 673 | E0 674 | FB 675 | FF 676 | 7F 677 | F8 678 | FE 679 | FF 680 | 1F 681 | F8 682 | 01 683 | 00 684 | 00 685 | F8 686 | FF 687 | FF 688 | 01 689 | FE 690 | CF 691 | 3F 692 | E0 693 | F1 694 | FF 695 | 7F 696 | 78 697 | FC 698 | FF 699 | 1F 700 | F8 701 | 00 702 | 00 703 | 00 704 | F8 705 | FF 706 | FF 707 | 01 708 | EE 709 | 8F 710 | 3F 711 | E0 712 | E0 713 | FF 714 | 3F 715 | 38 716 | F0 717 | FF 718 | 0F 719 | 00 720 | 00 721 | 00 722 | 00 723 | 00 724 | 00 725 | 00 726 | 00 727 | CE 728 | 07 729 | 1F 730 | 40 731 | 00 732 | FF 733 | 0F 734 | 10 735 | C0 736 | FF 737 | 03 738 | 00 739 | 00 740 | 00 741 | 00 742 | 00 743 | 00 744 | 00 745 | 00 746 | 00 747 | 00 748 | 00 749 | 00 750 | 00 751 | 00 752 | 00 753 | 00 754 | 00 755 | 00 756 | 00 757 | 00 758 | 00 759 | 00 760 | 00 761 | 00 762 | 00 763 | 00 764 | 00 765 | 00 766 | 00 767 | 00 768 | 00 769 | 00 770 | 00 771 | 00 772 | 00 773 | 00 774 | 00 775 | 00 776 | 00 777 | 00 778 | 00 779 | 00 780 | 00 781 | 00 782 | 00 783 | 00 784 | 00 785 | 00 786 | 00 787 | 00 788 | 00 789 | 00 790 | 00 791 | 00 792 | 00 793 | 00 794 | 00 795 | 00 796 | 00 797 | 00 798 | 00 799 | 00 800 | 00 801 | 00 802 | 00 803 | 00 804 | 00 805 | 00 806 | 00 807 | 00 808 | 00 809 | 00 810 | 00 811 | 00 812 | 00 813 | 00 814 | 00 815 | 00 816 | 00 817 | 00 818 | 00 819 | 00 820 | 00 821 | 00 822 | 00 823 | 00 824 | 00 825 | 00 826 | 00 827 | 00 828 | 00 829 | 00 830 | 00 831 | 00 832 | 00 833 | 00 834 | 00 835 | 00 836 | 00 837 | 00 838 | 00 839 | 00 840 | 00 841 | 00 842 | 00 843 | 00 844 | 00 845 | 00 846 | 00 847 | 00 848 | 00 849 | 00 850 | 00 851 | 00 852 | 00 853 | 00 854 | 00 855 | 00 856 | 00 857 | 00 858 | 00 859 | 00 860 | 00 861 | 00 862 | 00 863 | 00 864 | 00 865 | 00 866 | 00 867 | 00 868 | 00 869 | 80 870 | 07 871 | 00 872 | 00 873 | 80 874 | 07 875 | 00 876 | C0 877 | FF 878 | FF 879 | 0F 880 | C0 881 | FF 882 | FF 883 | 0F 884 | C0 885 | FF 886 | FF 887 | 0F 888 | C0 889 | 01 890 | 00 891 | 00 892 | E0 893 | F1 894 | F0 895 | 00 896 | E0 897 | F1 898 | F0 899 | 00 900 | E0 901 | F1 902 | F0 903 | 00 904 | E0 905 | FF 906 | FF 907 | 07 908 | E0 909 | FF 910 | FF 911 | 07 912 | E0 913 | FF 914 | FF 915 | 07 916 | E0 917 | 79 918 | 70 919 | 00 920 | E0 921 | 79 922 | 78 923 | 00 924 | E0 925 | 78 926 | 78 927 | 00 928 | E0 929 | F8 930 | 7F 931 | 00 932 | F0 933 | F8 934 | 7F 935 | 00 936 | F0 937 | F8 938 | 7F 939 | 00 940 | F0 941 | 00 942 | 00 943 | 00 944 | F0 945 | 00 946 | 00 947 | 00 948 | F0 949 | FF 950 | FF 951 | 00 952 | 70 953 | FF 954 | FF 955 | 00 956 | 78 957 | FF 958 | FF 959 | 00 960 | 78 961 | 3C 962 | F8 963 | 00 964 | 78 965 | 7C 966 | 7C 967 | 00 968 | 78 969 | 78 970 | 3E 971 | 00 972 | 38 973 | F0 974 | 1F 975 | 00 976 | 3C 977 | E0 978 | 0F 979 | 00 980 | 3C 981 | E0 982 | 07 983 | 00 984 | 3C 985 | FC 986 | 1F 987 | 00 988 | 9E 989 | FF 990 | FF 991 | 00 992 | DE 993 | 7F 994 | FC 995 | 01 996 | DE 997 | 0F 998 | F8 999 | 01 1000 | CC 1001 | 01 1002 | C0 1003 | 01 1004 | 00 1005 | 00 1006 | 00 1007 | 00 1008 | 00 1009 | 00 1010 | 00 1011 | 00 1012 | 00 1013 | 00 1014 | 00 1015 | 00 1016 | 00 1017 | 00 1018 | 00 1019 | 00 1020 | 00 1021 | 00 1022 | 00 1023 | 00 1024 | -------------------------------------------------------------------------------- /FPGA/rom_init_file/display_scale.dat: -------------------------------------------------------------------------------- 1 | 00 2 | 00 3 | 00 4 | 00 5 | 00 6 | 00 7 | 00 8 | 00 9 | 00 10 | 00 11 | 00 12 | 00 13 | 00 14 | 00 15 | 00 16 | 00 17 | 00 18 | 00 19 | 00 20 | 00 21 | 00 22 | 00 23 | 00 24 | 00 25 | 00 26 | 00 27 | 00 28 | 00 29 | 00 30 | 00 31 | 00 32 | 00 33 | 00 34 | 00 35 | 00 36 | 00 37 | 00 38 | 00 39 | 00 40 | 00 41 | 00 42 | 00 43 | 00 44 | 00 45 | 00 46 | 00 47 | 00 48 | 00 49 | 00 50 | 00 51 | 00 52 | 00 53 | 00 54 | 00 55 | 00 56 | 00 57 | 00 58 | 00 59 | 0F 60 | 78 61 | 00 62 | 80 63 | 07 64 | 1C 65 | 00 66 | 7C 67 | C0 68 | 03 69 | 00 70 | 1C 71 | 00 72 | 70 73 | 00 74 | 00 75 | 00 76 | 00 77 | 00 78 | 0F 79 | 78 80 | 00 81 | 80 82 | 07 83 | 3C 84 | 00 85 | 3C 86 | E0 87 | 03 88 | 00 89 | FC 90 | 7F 91 | 70 92 | 00 93 | 00 94 | 00 95 | 00 96 | 00 97 | E7 98 | FF 99 | 07 100 | 80 101 | 07 102 | 3C 103 | 00 104 | 3C 105 | E0 106 | 01 107 | 00 108 | FC 109 | 7F 110 | 70 111 | 00 112 | 00 113 | 00 114 | 00 115 | 80 116 | E7 117 | FF 118 | 1F 119 | 80 120 | 07 121 | 3C 122 | 00 123 | 3C 124 | E0 125 | 01 126 | 00 127 | FE 128 | FF 129 | 7F 130 | 00 131 | 00 132 | 00 133 | 00 134 | 80 135 | E7 136 | FF 137 | 1F 138 | FC 139 | 7F 140 | 1E 141 | 00 142 | 3C 143 | E0 144 | 01 145 | 00 146 | FE 147 | FF 148 | 7F 149 | 00 150 | 00 151 | 00 152 | 00 153 | 80 154 | E3 155 | FF 156 | 1F 157 | FC 158 | FF 159 | FE 160 | 07 161 | 3C 162 | E0 163 | 01 164 | 00 165 | 9E 166 | 87 167 | 7F 168 | 00 169 | 00 170 | 00 171 | 00 172 | C0 173 | E3 174 | 01 175 | 1E 176 | FC 177 | 7F 178 | FE 179 | 07 180 | 3C 181 | E0 182 | C1 183 | 00 184 | 8F 185 | 83 186 | 7F 187 | 00 188 | 00 189 | 00 190 | 00 191 | C0 192 | E3 193 | 01 194 | 1E 195 | FC 196 | 7F 197 | FF 198 | 07 199 | 3C 200 | E0 201 | E1 202 | 00 203 | 8F 204 | 83 205 | 7F 206 | 00 207 | 00 208 | 00 209 | 00 210 | E0 211 | ED 212 | 03 213 | 1E 214 | F0 215 | 00 216 | FF 217 | 07 218 | 3C 219 | E0 220 | F1 221 | 01 222 | CF 223 | 9F 224 | 7B 225 | 00 226 | 00 227 | 00 228 | 00 229 | E0 230 | DF 231 | FF 232 | 0F 233 | F0 234 | 00 235 | CF 236 | 03 237 | 3C 238 | E0 239 | FD 240 | 80 241 | CF 242 | BF 243 | 7B 244 | 00 245 | 00 246 | 00 247 | 00 248 | E0 249 | DE 250 | FF 251 | 1F 252 | F0 253 | 80 254 | CF 255 | 03 256 | 3E 257 | F0 258 | 7F 259 | 80 260 | CF 261 | BF 262 | 7B 263 | 00 264 | 00 265 | 00 266 | 00 267 | F0 268 | EF 269 | FD 270 | 1F 271 | F0 272 | 80 273 | C7 274 | 03 275 | FE 276 | F7 277 | 3F 278 | C0 279 | CF 280 | FF 281 | 3B 282 | 00 283 | 00 284 | 00 285 | 00 286 | F8 287 | EF 288 | FD 289 | 0F 290 | F0 291 | 8F 292 | C7 293 | 01 294 | FE 295 | F7 296 | 1F 297 | C0 298 | EF 299 | FD 300 | 3B 301 | 00 302 | 00 303 | 00 304 | 00 305 | F8 306 | E7 307 | E1 308 | 01 309 | F0 310 | DF 311 | E7 312 | 01 313 | FE 314 | F7 315 | 07 316 | E0 317 | EF 318 | FD 319 | 3F 320 | C0 321 | 03 322 | 00 323 | 00 324 | F0 325 | F7 326 | E1 327 | 01 328 | F0 329 | DF 330 | E7 331 | 01 332 | FE 333 | F7 334 | 03 335 | E0 336 | E7 337 | FD 338 | 3F 339 | C0 340 | 07 341 | 00 342 | 00 343 | 80 344 | F7 345 | E1 346 | 00 347 | F8 348 | FF 349 | E7 350 | 01 351 | 1E 352 | F0 353 | 00 354 | F0 355 | E7 356 | DC 357 | 3F 358 | E0 359 | 07 360 | 00 361 | 00 362 | C0 363 | FB 364 | FD 365 | 03 366 | 78 367 | FE 368 | E7 369 | 01 370 | 1E 371 | F0 372 | 00 373 | F0 374 | F7 375 | DD 376 | 3F 377 | E0 378 | 07 379 | 00 380 | 00 381 | C0 382 | FF 383 | FD 384 | 07 385 | 78 386 | FE 387 | E7 388 | 00 389 | 1E 390 | F0 391 | 00 392 | F0 393 | F7 394 | DF 395 | 3F 396 | E0 397 | 03 398 | 00 399 | 00 400 | E0 401 | FD 402 | FC 403 | 07 404 | 78 405 | DE 406 | FF 407 | 00 408 | 1E 409 | F0 410 | 00 411 | E0 412 | F7 413 | DF 414 | 3D 415 | C0 416 | 01 417 | 00 418 | 00 419 | E0 420 | FD 421 | FE 422 | 07 423 | 78 424 | 1E 425 | FF 426 | 00 427 | 1F 428 | F0 429 | 00 430 | 80 431 | FF 432 | CF 433 | 3D 434 | 00 435 | 00 436 | 00 437 | 00 438 | F0 439 | E7 440 | 9E 441 | 07 442 | 78 443 | 1E 444 | FF 445 | 00 446 | 0F 447 | F8 448 | 00 449 | 80 450 | 7F 451 | CF 452 | 1D 453 | 00 454 | 00 455 | 00 456 | 00 457 | F8 458 | E7 459 | 9E 460 | 07 461 | 38 462 | 1E 463 | 7F 464 | 00 465 | 0F 466 | 78 467 | 00 468 | 80 469 | 3F 470 | EF 471 | 1D 472 | 00 473 | 00 474 | 00 475 | 00 476 | F8 477 | F7 478 | 9E 479 | 07 480 | 3C 481 | 1E 482 | 7F 483 | 00 484 | 0F 485 | 78 486 | 00 487 | 80 488 | 27 489 | EF 490 | 1F 491 | 00 492 | 00 493 | 00 494 | 00 495 | F8 496 | F7 497 | 9E 498 | 07 499 | 3C 500 | 1E 501 | 7E 502 | 00 503 | 0F 504 | 78 505 | 00 506 | 80 507 | 87 508 | E7 509 | 1F 510 | 00 511 | 00 512 | 00 513 | 00 514 | F8 515 | F0 516 | FE 517 | 07 518 | 3C 519 | 0E 520 | 3E 521 | 00 522 | 0F 523 | 78 524 | 00 525 | 80 526 | 83 527 | E7 528 | 1F 529 | 00 530 | 00 531 | 00 532 | 00 533 | 00 534 | F0 535 | FE 536 | 03 537 | 3C 538 | 0F 539 | 3E 540 | 00 541 | 0F 542 | 78 543 | 00 544 | C0 545 | C3 546 | E7 547 | 1F 548 | 00 549 | 00 550 | 00 551 | 00 552 | 00 553 | F0 554 | FE 555 | 03 556 | 1E 557 | 0F 558 | 3E 559 | 00 560 | 0F 561 | 78 562 | 00 563 | C0 564 | C3 565 | E3 566 | 1F 567 | 00 568 | 00 569 | 00 570 | 00 571 | 00 572 | 72 573 | 8E 574 | 03 575 | 1E 576 | 0F 577 | 3F 578 | 00 579 | 0F 580 | 79 581 | F8 582 | C0 583 | C3 584 | E3 585 | 1E 586 | 00 587 | 00 588 | 00 589 | 00 590 | 80 591 | 77 592 | 8F 593 | 03 594 | 1E 595 | 0F 596 | 7F 597 | 00 598 | CF 599 | 79 600 | F8 601 | C0 602 | E3 603 | 01 604 | 1E 605 | 00 606 | 00 607 | 00 608 | 00 609 | F8 610 | 77 611 | CF 612 | 03 613 | 1E 614 | 8F 615 | 7F 616 | 80 617 | FF 618 | 7B 619 | 78 620 | C0 621 | F3 622 | 01 623 | 1E 624 | F0 625 | 00 626 | 00 627 | 00 628 | FC 629 | 77 630 | CF 631 | 03 632 | 0F 633 | CF 634 | FF 635 | 80 636 | FF 637 | 7B 638 | 78 639 | C0 640 | F3 641 | 38 642 | 0E 643 | F0 644 | 01 645 | 00 646 | 00 647 | FC 648 | 7B 649 | CF 650 | 03 651 | 7F 652 | EF 653 | F3 654 | 81 655 | FF 656 | 79 657 | 7C 658 | C0 659 | FB 660 | 38 661 | 0F 662 | F8 663 | 01 664 | 00 665 | 00 666 | 7C 667 | 78 668 | FF 669 | 83 670 | 7F 671 | F7 672 | E3 673 | E1 674 | 7F 675 | F8 676 | 3F 677 | C0 678 | 7B 679 | 78 680 | 0F 681 | F8 682 | 01 683 | 00 684 | 00 685 | 0C 686 | 78 687 | FF 688 | 83 689 | F7 690 | FF 691 | E1 692 | E3 693 | 1F 694 | F8 695 | 3F 696 | C0 697 | 7F 698 | F8 699 | 0F 700 | F8 701 | 00 702 | 00 703 | 00 704 | 00 705 | 78 706 | FF 707 | 83 708 | F7 709 | FF 710 | C0 711 | C3 712 | 07 713 | F0 714 | 1F 715 | E0 716 | 3D 717 | F0 718 | 07 719 | 00 720 | 00 721 | 00 722 | 00 723 | 00 724 | 78 725 | FF 726 | 01 727 | E3 728 | 73 729 | 80 730 | C1 731 | 00 732 | E0 733 | 0F 734 | E0 735 | 19 736 | E0 737 | 03 738 | 00 739 | 00 740 | 00 741 | 00 742 | 00 743 | 00 744 | 00 745 | 00 746 | 00 747 | 00 748 | 00 749 | 00 750 | 00 751 | 00 752 | 00 753 | 00 754 | 00 755 | 00 756 | 00 757 | 00 758 | 00 759 | 00 760 | 00 761 | 00 762 | 00 763 | 00 764 | 00 765 | 00 766 | 00 767 | 00 768 | 00 769 | 00 770 | 00 771 | 00 772 | 00 773 | 00 774 | 00 775 | 00 776 | 00 777 | 00 778 | 00 779 | 00 780 | 00 781 | 00 782 | 00 783 | 00 784 | 00 785 | 00 786 | 00 787 | 00 788 | 00 789 | 00 790 | 00 791 | 00 792 | 00 793 | 00 794 | 00 795 | 00 796 | 00 797 | 00 798 | 00 799 | 00 800 | 00 801 | 00 802 | 00 803 | 00 804 | 00 805 | 00 806 | 00 807 | 00 808 | 00 809 | 00 810 | 00 811 | 00 812 | 00 813 | 00 814 | 00 815 | 00 816 | 00 817 | 00 818 | 00 819 | 00 820 | 00 821 | 00 822 | 00 823 | 00 824 | 00 825 | 00 826 | 00 827 | 00 828 | 00 829 | 00 830 | 00 831 | 00 832 | 00 833 | 00 834 | 00 835 | 00 836 | 00 837 | 00 838 | 00 839 | 00 840 | 00 841 | 00 842 | 00 843 | 00 844 | 00 845 | 00 846 | 00 847 | 00 848 | 00 849 | 00 850 | 00 851 | 00 852 | 00 853 | 00 854 | 00 855 | 00 856 | -------------------------------------------------------------------------------- /FPGA/rom_init_file/display_total_input.dat: -------------------------------------------------------------------------------- 1 | 00 2 | 00 3 | 00 4 | 00 5 | 00 6 | 00 7 | 00 8 | 00 9 | 00 10 | 00 11 | 00 12 | 00 13 | 00 14 | 00 15 | 00 16 | 00 17 | 00 18 | 00 19 | 00 20 | 00 21 | 00 22 | 00 23 | 00 24 | 00 25 | 00 26 | 00 27 | 00 28 | 00 29 | 00 30 | 00 31 | 00 32 | 00 33 | 00 34 | 00 35 | 00 36 | 00 37 | 00 38 | 00 39 | 00 40 | 00 41 | 00 42 | 00 43 | 00 44 | 00 45 | 00 46 | 00 47 | 00 48 | 00 49 | 00 50 | 00 51 | 00 52 | 00 53 | 00 54 | 00 55 | 00 56 | 00 57 | 00 58 | 00 59 | 0C 60 | 60 61 | 00 62 | C0 63 | 03 64 | 1C 65 | 00 66 | 00 67 | 00 68 | 00 69 | 00 70 | 00 71 | 00 72 | 00 73 | 00 74 | 00 75 | 00 76 | 00 77 | 00 78 | 1E 79 | E0 80 | 01 81 | C0 82 | 01 83 | 1E 84 | 00 85 | C0 86 | 1F 87 | 00 88 | 80 89 | C7 90 | FF 91 | 7F 92 | 00 93 | 00 94 | 00 95 | 00 96 | 00 97 | 1E 98 | F0 99 | 01 100 | C0 101 | 01 102 | 1E 103 | 00 104 | C0 105 | 3F 106 | 00 107 | 80 108 | E7 109 | FF 110 | 7F 111 | 00 112 | 00 113 | 00 114 | 00 115 | 00 116 | 3E 117 | F0 118 | 00 119 | C0 120 | 01 121 | 1F 122 | 00 123 | C0 124 | 7F 125 | 00 126 | 00 127 | EF 128 | FF 129 | 7F 130 | 00 131 | 00 132 | 00 133 | 00 134 | 00 135 | 3C 136 | F8 137 | 00 138 | F8 139 | 8F 140 | 3F 141 | 00 142 | C0 143 | 7F 144 | 00 145 | 00 146 | EF 147 | FF 148 | 7F 149 | 00 150 | 00 151 | 00 152 | 00 153 | 00 154 | 3C 155 | 7C 156 | 00 157 | FC 158 | C7 159 | 7F 160 | 00 161 | 00 162 | 78 163 | 00 164 | 00 165 | FE 166 | C1 167 | 03 168 | 00 169 | 00 170 | 00 171 | 00 172 | 00 173 | 18 174 | 3C 175 | 00 176 | FC 177 | E7 178 | FB 179 | 00 180 | 00 181 | 78 182 | 00 183 | 00 184 | FE 185 | FD 186 | 1F 187 | 00 188 | 00 189 | 00 190 | 00 191 | 80 192 | FF 193 | FF 194 | 01 195 | FC 196 | F7 197 | F1 198 | 00 199 | 00 200 | 78 201 | 00 202 | 00 203 | FE 204 | FD 205 | 3F 206 | 00 207 | 00 208 | 00 209 | 00 210 | 80 211 | FF 212 | FF 213 | 03 214 | F0 215 | F8 216 | E0 217 | 03 218 | 00 219 | 78 220 | 00 221 | 00 222 | EC 223 | FD 224 | 3F 225 | 00 226 | 00 227 | 00 228 | 00 229 | 80 230 | FF 231 | FF 232 | 03 233 | F0 234 | FC 235 | FF 236 | 07 237 | 00 238 | 78 239 | 00 240 | 00 241 | E0 242 | FD 243 | 3F 244 | 00 245 | 00 246 | 00 247 | 00 248 | C0 249 | FF 250 | FF 251 | 03 252 | 70 253 | FE 254 | FF 255 | 07 256 | 00 257 | 78 258 | 00 259 | 80 260 | E1 261 | 1F 262 | 3C 263 | 00 264 | 00 265 | 00 266 | 00 267 | C0 268 | 03 269 | C0 270 | 03 271 | F8 272 | DF 273 | 7F 274 | 07 275 | 00 276 | 7C 277 | 00 278 | C0 279 | E3 280 | 1E 281 | 3C 282 | 00 283 | 00 284 | 00 285 | 00 286 | C0 287 | 03 288 | E0 289 | 03 290 | F8 291 | 01 292 | 00 293 | 02 294 | 00 295 | 7C 296 | 00 297 | C0 298 | F3 299 | FE 300 | 3F 301 | 00 302 | 00 303 | 00 304 | 00 305 | C0 306 | 03 307 | E0 308 | 01 309 | F8 310 | F9 311 | C3 312 | 03 313 | 00 314 | FC 315 | 00 316 | C0 317 | F3 318 | FE 319 | 3F 320 | C0 321 | 03 322 | 00 323 | 00 324 | C0 325 | 03 326 | E0 327 | 01 328 | FC 329 | F9 330 | C3 331 | 03 332 | 00 333 | FE 334 | 00 335 | 80 336 | F7 337 | FE 338 | 3F 339 | C0 340 | 07 341 | 00 342 | 00 343 | C0 344 | 03 345 | E0 346 | 01 347 | FC 348 | F9 349 | FF 350 | 01 351 | 00 352 | FE 353 | 00 354 | 80 355 | F7 356 | FE 357 | 3F 358 | E0 359 | 07 360 | 00 361 | 00 362 | C0 363 | 03 364 | E0 365 | 01 366 | FC 367 | FB 368 | FF 369 | 01 370 | 00 371 | FE 372 | 00 373 | 00 374 | FF 375 | 0E 376 | 1C 377 | E0 378 | 07 379 | 00 380 | 00 381 | C0 382 | FF 383 | FF 384 | 01 385 | FE 386 | BB 387 | FB 388 | 01 389 | 00 390 | FF 391 | 00 392 | 00 393 | FF 394 | 0E 395 | 1C 396 | E0 397 | 03 398 | 00 399 | 00 400 | C0 401 | FF 402 | FF 403 | 01 404 | FE 405 | BF 406 | FB 407 | 01 408 | 00 409 | FF 410 | 00 411 | 00 412 | F3 413 | FE 414 | 1F 415 | C0 416 | 01 417 | 00 418 | 00 419 | E0 420 | FF 421 | FF 422 | 01 423 | FE 424 | FF 425 | FF 426 | 01 427 | 00 428 | FF 429 | 01 430 | 00 431 | F0 432 | FE 433 | 1F 434 | 00 435 | 00 436 | 00 437 | 00 438 | E0 439 | FF 440 | FF 441 | 01 442 | EC 443 | FD 444 | FF 445 | 01 446 | 80 447 | E7 448 | 01 449 | 00 450 | 70 451 | FF 452 | 1F 453 | 00 454 | 00 455 | 00 456 | 00 457 | 00 458 | 40 459 | 00 460 | 00 461 | E0 462 | FC 463 | DF 464 | 01 465 | 80 466 | E7 467 | 01 468 | 00 469 | 7F 470 | E0 471 | 01 472 | 00 473 | 00 474 | 00 475 | 00 476 | 00 477 | F0 478 | 00 479 | 00 480 | E0 481 | 9C 482 | FF 483 | 01 484 | C0 485 | E7 486 | 03 487 | 80 488 | 7F 489 | E6 490 | 09 491 | 00 492 | 00 493 | 00 494 | 00 495 | 70 496 | F0 497 | 81 498 | 01 499 | E0 500 | 9C 501 | FF 502 | 01 503 | E0 504 | C3 505 | 03 506 | 80 507 | 7F 508 | EF 509 | 0E 510 | 00 511 | 00 512 | 00 513 | 00 514 | F0 515 | EF 516 | E3 517 | 01 518 | E0 519 | 9F 520 | FF 521 | 00 522 | E0 523 | C3 524 | 03 525 | 80 526 | 7F 527 | EF 528 | 0E 529 | 00 530 | 00 531 | 00 532 | 00 533 | 78 534 | CF 535 | C3 536 | 03 537 | FC 538 | FF 539 | FF 540 | 00 541 | F0 542 | C1 543 | 07 544 | C0 545 | 7B 546 | F7 547 | 0E 548 | 00 549 | 00 550 | 00 551 | 00 552 | 78 553 | CF 554 | C3 555 | 03 556 | FF 557 | FF 558 | FD 559 | 00 560 | F8 561 | 80 562 | 07 563 | C0 564 | BF 565 | F7 566 | 1E 567 | 00 568 | 00 569 | 00 570 | 00 571 | 78 572 | 8F 573 | C3 574 | 03 575 | FF 576 | FF 577 | FD 578 | 00 579 | FC 580 | 80 581 | 0F 582 | C0 583 | BF 584 | F7 585 | 1E 586 | 00 587 | 00 588 | 00 589 | 00 590 | 78 591 | 0F 592 | FC 593 | 03 594 | FF 595 | DE 596 | FD 597 | 00 598 | 7C 599 | 00 600 | 1F 601 | E0 602 | BD 603 | F3 604 | 1E 605 | 00 606 | 00 607 | 00 608 | 00 609 | 3C 610 | 0F 611 | BC 612 | 07 613 | F1 614 | CE 615 | E1 616 | 00 617 | 3E 618 | 00 619 | 1F 620 | E0 621 | FD 622 | F3 623 | 1E 624 | F0 625 | 00 626 | 00 627 | 00 628 | 3C 629 | 0F 630 | BC 631 | 07 632 | 70 633 | CE 634 | E1 635 | 00 636 | 1F 637 | 00 638 | 3E 639 | E0 640 | DF 641 | F3 642 | 1E 643 | F0 644 | 01 645 | 00 646 | 00 647 | 3E 648 | 1F 649 | BE 650 | 07 651 | 70 652 | CE 653 | F7 654 | C0 655 | 1F 656 | 00 657 | 3E 658 | F0 659 | FE 660 | F1 661 | 1E 662 | F8 663 | 01 664 | 00 665 | 00 666 | 1E 667 | 3E 668 | 9F 669 | 07 670 | 70 671 | CE 672 | FF 673 | E0 674 | 0F 675 | 00 676 | 7C 677 | F0 678 | FE 679 | 7F 680 | 1C 681 | F8 682 | 01 683 | 00 684 | 00 685 | 1E 686 | FE 687 | 1F 688 | 07 689 | 70 690 | FE 691 | 7F 692 | E0 693 | 07 694 | 00 695 | FC 696 | F8 697 | CF 698 | 7F 699 | 1C 700 | F8 701 | 00 702 | 00 703 | 00 704 | 08 705 | FC 706 | 0F 707 | 03 708 | 70 709 | FE 710 | 7E 711 | C0 712 | 03 713 | 00 714 | 78 715 | 78 716 | 0F 717 | 7F 718 | 04 719 | 00 720 | 00 721 | 00 722 | 00 723 | 00 724 | F8 725 | 07 726 | 00 727 | 78 728 | FE 729 | 3C 730 | C0 731 | 00 732 | 00 733 | 30 734 | 70 735 | 0F 736 | 3E 737 | 00 738 | 00 739 | 00 740 | 00 741 | 00 742 | 00 743 | 00 744 | 00 745 | 00 746 | 00 747 | 00 748 | 00 749 | 00 750 | 00 751 | 00 752 | 00 753 | 00 754 | 00 755 | 00 756 | 00 757 | 00 758 | 00 759 | 00 760 | 00 761 | 00 762 | 00 763 | 00 764 | 00 765 | 00 766 | 00 767 | 00 768 | 00 769 | 00 770 | 00 771 | 00 772 | 00 773 | 00 774 | 00 775 | 00 776 | 00 777 | 00 778 | 00 779 | 00 780 | 00 781 | 00 782 | 00 783 | 00 784 | 00 785 | 00 786 | 00 787 | 00 788 | 00 789 | 00 790 | 00 791 | 00 792 | 00 793 | 00 794 | 00 795 | 00 796 | 00 797 | 00 798 | 00 799 | 00 800 | 00 801 | 00 802 | 00 803 | 00 804 | 00 805 | 00 806 | 00 807 | 00 808 | 00 809 | 00 810 | 00 811 | 00 812 | 00 813 | 00 814 | 00 815 | 00 816 | 00 817 | 00 818 | 00 819 | 00 820 | 00 821 | 00 822 | 00 823 | 00 824 | 00 825 | 00 826 | 00 827 | 00 828 | 00 829 | 00 830 | 00 831 | 00 832 | 00 833 | 00 834 | 00 835 | 00 836 | 00 837 | 00 838 | 00 839 | 00 840 | 00 841 | 00 842 | 00 843 | 00 844 | 00 845 | 00 846 | 00 847 | 00 848 | 00 849 | 00 850 | 00 851 | 00 852 | 00 853 | 00 854 | 00 855 | 00 856 | -------------------------------------------------------------------------------- /FPGA/rom_init_file/rom_for_number.dat: -------------------------------------------------------------------------------- 1 | 00 2 | 00 3 | 80 4 | 0F 5 | C0 6 | 1F 7 | E0 8 | 3F 9 | E0 10 | 3D 11 | F0 12 | 38 13 | 70 14 | 38 15 | 70 16 | 38 17 | 38 18 | 70 19 | 38 20 | 70 21 | 38 22 | 70 23 | 38 24 | 38 25 | 38 26 | 38 27 | 3C 28 | 38 29 | 1C 30 | 38 31 | 1C 32 | 38 33 | 1C 34 | 38 35 | 1C 36 | 38 37 | 1C 38 | 38 39 | 1C 40 | 38 41 | 1C 42 | 38 43 | 1C 44 | 3C 45 | 1E 46 | 1C 47 | 1E 48 | 1C 49 | 0E 50 | 1C 51 | 0E 52 | 1C 53 | 1E 54 | 1E 55 | 1C 56 | 0E 57 | 1C 58 | 0E 59 | 1C 60 | 07 61 | FC 62 | 07 63 | F8 64 | 03 65 | F8 66 | 01 67 | 00 68 | 00 69 | 80 70 | 01 71 | C0 72 | 01 73 | F0 74 | 01 75 | F0 76 | 01 77 | F0 78 | 01 79 | C0 80 | 01 81 | C0 82 | 01 83 | C0 84 | 01 85 | C0 86 | 01 87 | E0 88 | 00 89 | E0 90 | 00 91 | E0 92 | 00 93 | E0 94 | 00 95 | E0 96 | 00 97 | E0 98 | 00 99 | E0 100 | 00 101 | E0 102 | 00 103 | E0 104 | 00 105 | F0 106 | 00 107 | 70 108 | 00 109 | 70 110 | 00 111 | 70 112 | 00 113 | 70 114 | 00 115 | 70 116 | 00 117 | 70 118 | 00 119 | 70 120 | 00 121 | 70 122 | 00 123 | 78 124 | 00 125 | 38 126 | 00 127 | 38 128 | 00 129 | 38 130 | 00 131 | 38 132 | 00 133 | 00 134 | 00 135 | 80 136 | 0F 137 | C0 138 | 1F 139 | E0 140 | 1F 141 | F0 142 | 3C 143 | 70 144 | 38 145 | 70 146 | 38 147 | 38 148 | 38 149 | 00 150 | 38 151 | 00 152 | 38 153 | 00 154 | 38 155 | 00 156 | 1C 157 | 00 158 | 1C 159 | 00 160 | 1E 161 | 00 162 | 0E 163 | 00 164 | 0F 165 | 00 166 | 07 167 | 80 168 | 07 169 | C0 170 | 03 171 | C0 172 | 01 173 | E0 174 | 01 175 | F0 176 | 00 177 | 70 178 | 00 179 | 78 180 | 00 181 | 38 182 | 00 183 | 38 184 | 00 185 | 1C 186 | 00 187 | 1C 188 | 00 189 | 1C 190 | 00 191 | FE 192 | 0F 193 | FE 194 | 0F 195 | FE 196 | 07 197 | FE 198 | 07 199 | 00 200 | 00 201 | 80 202 | 07 203 | E0 204 | 0F 205 | E0 206 | 1F 207 | F0 208 | 1E 209 | 70 210 | 3C 211 | 38 212 | 38 213 | 00 214 | 38 215 | 00 216 | 38 217 | 00 218 | 3C 219 | 00 220 | 1C 221 | 00 222 | 1C 223 | 00 224 | 0E 225 | 80 226 | 0F 227 | C0 228 | 07 229 | E0 230 | 07 231 | E0 232 | 0F 233 | 00 234 | 0F 235 | 00 236 | 1E 237 | 00 238 | 1C 239 | 00 240 | 1C 241 | 00 242 | 1C 243 | 00 244 | 1C 245 | 00 246 | 1C 247 | 00 248 | 1C 249 | 0C 250 | 1E 251 | 0E 252 | 0E 253 | 0E 254 | 0E 255 | 0E 256 | 0F 257 | 1C 258 | 07 259 | FC 260 | 07 261 | FC 262 | 03 263 | F8 264 | 01 265 | 00 266 | 00 267 | 00 268 | 38 269 | 00 270 | 38 271 | 00 272 | 3C 273 | 00 274 | 3C 275 | 00 276 | 3E 277 | 00 278 | 3E 279 | 00 280 | 1F 281 | 00 282 | 1B 283 | 80 284 | 1F 285 | 80 286 | 1F 287 | C0 288 | 1D 289 | C0 290 | 1D 291 | E0 292 | 1C 293 | E0 294 | 1C 295 | 70 296 | 1C 297 | 70 298 | 0E 299 | 38 300 | 0E 301 | 38 302 | 0E 303 | 1C 304 | 0E 305 | 1C 306 | 0E 307 | FE 308 | 3F 309 | FE 310 | 3F 311 | FE 312 | 3F 313 | FE 314 | 3F 315 | 00 316 | 07 317 | 00 318 | 07 319 | 00 320 | 07 321 | 00 322 | 07 323 | 00 324 | 07 325 | 00 326 | 07 327 | 00 328 | 07 329 | 00 330 | 07 331 | 00 332 | 00 333 | C0 334 | 3F 335 | E0 336 | 3F 337 | E0 338 | 3F 339 | E0 340 | 3F 341 | E0 342 | 00 343 | E0 344 | 00 345 | 60 346 | 00 347 | 60 348 | 00 349 | 70 350 | 00 351 | 70 352 | 00 353 | 70 354 | 00 355 | 70 356 | 03 357 | F0 358 | 0F 359 | F0 360 | 0F 361 | F0 362 | 1F 363 | 38 364 | 1C 365 | 38 366 | 1C 367 | 10 368 | 1C 369 | 00 370 | 1C 371 | 00 372 | 1C 373 | 00 374 | 1C 375 | 00 376 | 1C 377 | 00 378 | 1C 379 | 00 380 | 1C 381 | 0C 382 | 1C 383 | 0E 384 | 1E 385 | 0E 386 | 0E 387 | 1E 388 | 0E 389 | 1C 390 | 0F 391 | FC 392 | 07 393 | FC 394 | 03 395 | F8 396 | 01 397 | 00 398 | 00 399 | 00 400 | 1E 401 | 80 402 | 3F 403 | 80 404 | 7F 405 | C0 406 | 7B 407 | C0 408 | 71 409 | E0 410 | E0 411 | E0 412 | 60 413 | F0 414 | 00 415 | 70 416 | 00 417 | 70 418 | 00 419 | 70 420 | 00 421 | 70 422 | 00 423 | 38 424 | 0F 425 | B8 426 | 1F 427 | F8 428 | 1F 429 | F8 430 | 3C 431 | 78 432 | 38 433 | 38 434 | 38 435 | 38 436 | 38 437 | 38 438 | 38 439 | 38 440 | 38 441 | 1C 442 | 38 443 | 1C 444 | 38 445 | 1C 446 | 38 447 | 1C 448 | 38 449 | 1C 450 | 38 451 | 18 452 | 1C 453 | 38 454 | 1C 455 | 38 456 | 1E 457 | F8 458 | 0F 459 | F0 460 | 07 461 | F0 462 | 03 463 | 00 464 | 00 465 | F0 466 | 7F 467 | F0 468 | 3F 469 | F0 470 | 3F 471 | F8 472 | 3F 473 | 00 474 | 18 475 | 00 476 | 1C 477 | 00 478 | 1C 479 | 00 480 | 0E 481 | 00 482 | 0E 483 | 00 484 | 07 485 | 00 486 | 07 487 | 00 488 | 07 489 | 80 490 | 03 491 | 80 492 | 03 493 | 80 494 | 03 495 | C0 496 | 01 497 | C0 498 | 01 499 | C0 500 | 01 501 | E0 502 | 01 503 | E0 504 | 00 505 | E0 506 | 00 507 | E0 508 | 00 509 | F0 510 | 00 511 | 70 512 | 00 513 | 70 514 | 00 515 | 70 516 | 00 517 | 70 518 | 00 519 | 38 520 | 00 521 | 38 522 | 00 523 | 38 524 | 00 525 | 38 526 | 00 527 | 38 528 | 00 529 | 00 530 | 00 531 | 00 532 | 0F 533 | C0 534 | 3F 535 | E0 536 | 3F 537 | E0 538 | 79 539 | E0 540 | 70 541 | 70 542 | 70 543 | 70 544 | 70 545 | 70 546 | 70 547 | 70 548 | 70 549 | 70 550 | 70 551 | 70 552 | 78 553 | 70 554 | 38 555 | E0 556 | 3C 557 | E0 558 | 1F 559 | C0 560 | 0F 561 | E0 562 | 0F 563 | F0 564 | 1F 565 | 78 566 | 1C 567 | 38 568 | 38 569 | 38 570 | 38 571 | 1C 572 | 38 573 | 1C 574 | 38 575 | 1C 576 | 38 577 | 1C 578 | 38 579 | 1C 580 | 38 581 | 1C 582 | 38 583 | 1C 584 | 1C 585 | 1C 586 | 1C 587 | 3C 588 | 1E 589 | F8 590 | 0F 591 | F8 592 | 0F 593 | F0 594 | 07 595 | 00 596 | 0C 597 | 00 598 | 3F 599 | 80 600 | 3F 601 | C0 602 | 7F 603 | E0 604 | 71 605 | E0 606 | 70 607 | E0 608 | 60 609 | 70 610 | E0 611 | 70 612 | E0 613 | 70 614 | E0 615 | 70 616 | E0 617 | 70 618 | E0 619 | 70 620 | 70 621 | 70 622 | 70 623 | 70 624 | 70 625 | 70 626 | 70 627 | 70 628 | 78 629 | F0 630 | 7C 631 | E0 632 | 7F 633 | E0 634 | 77 635 | C0 636 | 73 637 | 00 638 | 38 639 | 00 640 | 38 641 | 00 642 | 38 643 | 00 644 | 38 645 | 00 646 | 3C 647 | 18 648 | 1C 649 | 1C 650 | 1C 651 | 38 652 | 0E 653 | 78 654 | 0F 655 | F8 656 | 07 657 | F0 658 | 07 659 | E0 660 | 01 661 | 662 | 00 663 | 00 664 | 00 665 | 00 666 | 00 667 | 00 668 | 00 669 | 00 670 | 00 671 | 00 672 | 00 673 | 00 674 | 00 675 | 00 676 | 00 677 | 00 678 | 00 679 | 00 680 | 00 681 | 00 682 | 00 683 | 00 684 | 00 685 | 00 686 | 00 687 | 00 688 | 00 689 | 00 690 | 00 691 | 1E 692 | 1E 693 | 1E 694 | 1E -------------------------------------------------------------------------------- /RTL/axi_interconnect_rd.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/axi_interconnect_rd.v -------------------------------------------------------------------------------- /RTL/axi_interconnect_rd_backup.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/axi_interconnect_rd_backup.v -------------------------------------------------------------------------------- /RTL/axi_interconnect_wr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/axi_interconnect_wr.v -------------------------------------------------------------------------------- /RTL/axi_interconnect_wr_backup.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/axi_interconnect_wr_backup.v -------------------------------------------------------------------------------- /RTL/cmos_add.v: -------------------------------------------------------------------------------- 1 | /* 2 | 20211025 3 | 2021.10.27 4 | */ 5 | 6 | module cmos_add( 7 | input sys_rst_n, 8 | input cmos0_pclk, 9 | input cmos0_href, 10 | input[15:0] cmos0_data, 11 | input cmos0_vsync, 12 | 13 | input cmos1_pclk, 14 | input cmos1_href, 15 | input[15:0] cmos1_data, 16 | input cmos1_vsync, 17 | /* 18 | input cmos0_en, 19 | input cmos1_en, 20 | input splicing_en, 21 | */ 22 | output pixel_vsync, 23 | output pixel_href, 24 | output reg [15:0] pixel_data 25 | ); 26 | 27 | // 使能信号 28 | reg cmos0_en; 29 | reg cmos1_en; 30 | reg splicing_en; 31 | 32 | always @(posedge cmos0_pclk or negedge sys_rst_n) begin 33 | if(!sys_rst_n) begin 34 | cmos0_en <= 'b0; 35 | cmos1_en <= 'b0; 36 | splicing_en <= 'b0; 37 | end 38 | else begin 39 | cmos0_en <= 1'b1; 40 | cmos1_en <= 1'b1; 41 | splicing_en <= 1'b1; 42 | end 43 | end 44 | 45 | 46 | //计数器对系统时钟计数，计时0.2秒，场信号采样时钟 47 | reg [23:0] counter; 48 | reg counter_clk; 49 | always @(posedge cmos0_pclk or negedge sys_rst_n) begin 50 | if (!sys_rst_n) begin 51 | counter <= 24'd0; 52 | counter_clk <= 1'b0; 53 | end 54 | else if (counter < 24'd10_0000) 55 | counter <= counter + 1'b1; 56 | else begin 57 | counter <= 24'd0; 58 | counter_clk <= ~counter_clk; 59 | end 60 | end 61 | 62 | 63 | wire [15:0] cmos0_data_rd; 64 | wire cmos1_write_full; 65 | fifo_pong u_fifo_pong( 66 | .Data (cmos0_data ), //input [15:0] Data 67 | .Reset (~sys_rst_n ), //input Reset 68 | .WrClk (cmos0_pclk ), //input WrClk 69 | .RdClk (cmos0_pclk ), //input RdClk 70 | .WrEn (cmos0_href ), //input WrEn 71 | .RdEn (~cmos1_href ), //input RdEn 72 | // .RdEn (~empty ), //input RdEn 73 | .Q (cmos0_data_rd ), //output [15:0] Q 74 | .Empty (empty ), //output Empty 75 | .Full (cmos1_write_full ) //output Full 76 | ); 77 | 78 | //将empty信号打到cmos0_pclk里 79 | reg empty_vsync; 80 | reg fifo_empty; 81 | always @(posedge cmos1_pclk or negedge sys_rst_n) begin 82 | if(!sys_rst_n) begin 83 | empty_vsync <= 1'b0; 84 | fifo_empty <= 1'b0; 85 | end 86 | else if(~empty) begin 87 | fifo_empty <= ~empty; 88 | empty_vsync <= fifo_empty; 89 | end 90 | else begin 91 | fifo_empty <= 1'b0; 92 | empty_vsync <= 1'b0; 93 | end 94 | end 95 | 96 | //对cmos0_href进行计数 97 | reg [10:0] cmos0_href_cnt; 98 | always @(posedge cmos0_pclk or negedge sys_rst_n) begin 99 | if(!sys_rst_n) 100 | cmos0_href_cnt <= 11'd0; 101 | else if(cmos0_href) 102 | cmos0_href_cnt <= cmos0_href_cnt + 11'd1; 103 | else if(empty) 104 | cmos0_href_cnt <= 11'd0; 105 | end 106 | 107 | //在cmos1_href后继续延时cmos0_href长度，以达到两个摄像头数据拼接成一行的效果 108 | reg cmos0_href_reg; 109 | reg [10:0] cmos0_delay; 110 | always @(posedge cmos0_pclk or negedge sys_rst_n) begin 111 | if(!sys_rst_n) begin 112 | cmos0_href_reg <= 1'b0; 113 | cmos0_delay <= 11'd0; 114 | end 115 | else if(~cmos1_href && cmos0_delay < 10'd640) begin 116 | cmos0_delay <= cmos0_delay + 11'd1; 117 | cmos0_href_reg <= 1'b1; 118 | end 119 | else if(~cmos1_href && cmos0_delay >= 10'd640) begin 120 | cmos0_href_reg <= 1'b0; 121 | end 122 | else if(cmos1_href) cmos0_delay <= 10'd0; 123 | end 124 | 125 | 126 | ///cmos_vsync信号2分频作pixel_vsync信号 127 | reg [1:0] vsync_add_clk_cnt; 128 | always @(posedge cmos0_vsync or negedge sys_rst_n) begin 129 | if (!sys_rst_n) begin 130 | vsync_add_clk_cnt <= 2'b0; 131 | end 132 | else if (vsync_add_clk_cnt >= 2'd2) begin 133 | vsync_add_clk_cnt <= 2'b0; 134 | end 135 | else begin 136 | vsync_add_clk_cnt <= vsync_add_clk_cnt + 2'b1; 137 | end 138 | end 139 | 140 | assign pixel_vsync = (vsync_add_clk_cnt ^ 2'd1) ? 1'b0 : cmos0_vsync ; 141 | 142 | 143 | 144 | //cam1行像素点计数 145 | reg [11:0] cam1_pixel_cnt;//行像素计数器 146 | always @(posedge cmos1_pclk or negedge sys_rst_n) begin 147 | if (!sys_rst_n) 148 | cam1_pixel_cnt <= 12'd0; 149 | else if (!pixel_href) begin 150 | cam1_pixel_cnt <= 12'd0; 151 | end 152 | else begin 153 | cam1_pixel_cnt <= cam1_pixel_cnt + 12'd1; 154 | end 155 | end 156 | 157 | //像素偏差位置设置 158 | localparam PIXEL_OFFSET = 12'd80; 159 | wire pixel_offset_flag = (cam1_pixel_cnt < PIXEL_OFFSET && cam1_pixel_cnt > 16'b0) ? 1'b1 : 1'b0; 160 | wire pixel_increase_flag = (cam1_pixel_cnt > (PIXEL_OFFSET-1) && cam1_pixel_cnt <= (641 + PIXEL_OFFSET)) ? 1'b1 : 1'b0; 161 | 162 | wire [15:0] cmos0_data_splicing; 163 | wire fifo_splicing_full; 164 | wire fifo_splicing_empty; 165 | fifo_pong u_fifo_splicing( 166 | .Data (cmos0_data ), //input [15:0] Data 167 | .Reset (~sys_rst_n ), //input Reset 168 | .WrClk (cmos0_pclk ), //input WrClk 169 | .RdClk (cmos1_pclk ), //input RdClk 170 | .WrEn (cmos0_href ), //input WrEn 171 | .RdEn (pixel_increase_flag), //input RdEn 172 | // .RdEn (1'b1), //input RdEn 173 | .Q (cmos0_data_splicing), //output [15:0] Q 174 | .Empty (fifo_splicing_empty), //output Empty 175 | .Full (fifo_splicing_full ) //output Full 176 | ); 177 | 178 | 179 | reg [4:0] R; 180 | reg [5:0] G; 181 | reg [4:0] B; 182 | /* 183 | always @(*) begin 184 | if (!pixel_flip_flag) begin //上半屏 185 | pixel_data <= cmos1_href ? cmos1_data : cmos0_data_rd; 186 | // pixel_data <= cmos1_href ? 16'd0 : 16'd0; 187 | end 188 | else if(pixel_flip_flag) begin 189 | // R <= cmos1_data[14:11] + cmos0_data_rd[14:11]; 190 | // G <= cmos1_data[9:5] + cmos0_data_rd[9:5]; 191 | // B <= cmos1_data[3:0] + cmos0_data_rd[3:0]; 192 | // pixel_data <= {R,G,B}; 193 | pixel_data <= cmos1_href ? 16'd0 : 16'd0; 194 | end 195 | end 196 | */ 197 | 198 | reg [15:0] fusion_data; 199 | //RBG加权平均 200 | always @(*) begin 201 | if(cam1_pixel_cnt < PIXEL_OFFSET) begin 202 | // fusion_data[4:0] = (cmos1_data[4:0] >> 2) + (cmos0_data[4:0] >> 1); 203 | // fusion_data[10:5] = (cmos1_data[10:5] >> 2) + (cmos0_data[10:5] >> 1); 204 | // fusion_data[15:11] = (cmos1_data[15:11] >> 2) + (cmos0_data[15:11] >> 1); 205 | fusion_data = cmos1_data; 206 | end 207 | else if((cam1_pixel_cnt >= PIXEL_OFFSET) && (cam1_pixel_cnt <= PIXEL_OFFSET + 12'd10)) begin 208 | fusion_data[4:0] = (cmos1_data[4:0] >> 1) + (cmos0_data_splicing[4:0] >> 1); 209 | fusion_data[10:5] = (cmos1_data[10:5] >> 1) + (cmos0_data_splicing[10:5] >> 1); 210 | fusion_data[15:11] = (cmos1_data[15:11] >> 1) + (cmos0_data_splicing[15:11] >> 1); 211 | end 212 | else begin 213 | fusion_data = cmos0_data_splicing; 214 | end 215 | end 216 | 217 | //移位拼接 218 | always @(*) begin 219 | //pixel_data = (vsync_add_clk_cnt ^ 2'd1) ? (cmos1_href ? cmos1_data : cmos0_data_rd) : 16'd0; 220 | case (vsync_add_clk_cnt)//上下分屏显示，用vsync分屏信号做标志 221 | 2'd0 : begin //下360行 222 | if (splicing_en) begin 223 | pixel_data = pixel_offset_flag ? cmos1_data : ~fifo_splicing_empty ? fusion_data : 1'b0; 224 | end 225 | else begin 226 | pixel_data = 16'd0; 227 | end 228 | end 229 | 2'd1 : begin//上360行 230 | // pixel_data = cmos1_href ? cmos1_data : cmos0_data_rd; 231 | if (cmos1_href) begin 232 | pixel_data = cmos1_en ? cmos1_data : 16'd0; 233 | end 234 | else begin 235 | pixel_data = cmos0_en ? cmos0_data_rd : 16'd0; 236 | end 237 | end 238 | default : begin 239 | if (splicing_en) begin 240 | pixel_data = pixel_offset_flag ? cmos1_data : ~fifo_splicing_empty ? fusion_data : 1'b0; 241 | end 242 | else begin 243 | pixel_data = 16'd0; 244 | end 245 | end 246 | endcase 247 | end 248 | 249 | assign pixel_href = cmos1_href | (~ empty); 250 | 251 | endmodule 252 | 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image_global.v 9 | uart_rx.v 10 | uart_trans.v 11 | uart_tx.v 12 | video_fusion.v 13 | video_sampling_1.v 14 | video_sampling_2.v 15 | cmos_8_16bit.v 16 | fram_buf.v 17 | i2c_com.v 18 | iic_dri.v 19 | ms7200_ctl.v 20 | ms7210_ctl.v 21 | ms72xx_ctl.v 22 | power_on_delay.v 23 | rd_buf.v 24 | rd_ctrl.v 25 | reg_config.v 26 | sync_vg.v 27 | wr_buf.v 28 | wr_cmd_trans.v 29 | wr_ctrl.v 30 | wr_rd_ctrl_top.v 31 | arp_cache.v 32 | arp_rx.v 33 | arp_tx.v 34 | color_bar.v 35 | crc.v 36 | ethernet_character.v 37 | ethernet_test.v 38 | icmp_reply.v 39 | ip_rx.v 40 | ip_tx.v 41 | ip_tx_mode.v 42 | mac_rx.v 43 | mac_rx_top.v 44 | mac_test.v 45 | mac_top.v 46 | mac_tx.v 47 | mac_tx_mode.v 48 | mac_tx_top.v 49 | osd_display.v 50 | timing_gen_xy.v 51 | udp_rx.v 52 | udp_tx.v 53 | util_gmii_to_rgmii.v 54 | -------------------------------------------------------------------------------- /RTL/rtl_1/cmos_8_16bit.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_1/cmos_8_16bit.v -------------------------------------------------------------------------------- /RTL/rtl_1/fram_buf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_1/fram_buf.v -------------------------------------------------------------------------------- /RTL/rtl_1/i2c_com.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////// 2 | // Company:Meyesemi 3 | // Engineer: Will 4 | // 5 | // Create Date: 2023-03-17 6 | // Design Name: 7 | // Module Name: 8 | // Project Name: 9 | // Target Devices: Pango 10 | // Tool Versions: 11 | // Description: 12 | // 13 | // Dependencies: 14 | // 15 | // Revision: 16 | // Revision 1.0 - File Created 17 | // Additional Comments: 18 | // 19 | ////////////////////////////////////////////////////////////////////////////////// 20 | //sclk，sdin数据传输时序代码（i2c写控制代码） 21 | module i2c_com(clock_i2c , //i2c控制接口传输所需时钟，0-400khz，此处为20khz 22 | camera_rstn , 23 | ack , //应答信号 24 | i2c_data , //sdin接口传输的32位数据 25 | start , //开始传输标志 26 | tr_end , //传输结束标志 27 | i2c_sclk , //FPGA与camera iic时钟接口 28 | i2c_sdat //FPGA与camera iic数据接口 29 | ); 30 | input [31:0]i2c_data; 31 | input camera_rstn; 32 | input clock_i2c; 33 | output ack; 34 | input start; 35 | output tr_end; 36 | output i2c_sclk; 37 | inout i2c_sdat; 38 | reg [5:0] cyc_count; 39 | reg reg_sdat; 40 | reg sclk; 41 | reg ack1,ack2,ack3; 42 | reg tr_end; 43 | 44 | 45 | wire i2c_sclk; 46 | wire i2c_sdat; 47 | wire ack; 48 | 49 | assign ack=ack1|ack2|ack3; 50 | assign i2c_sclk=sclk|(((cyc_count>=4)&(cyc_count<=39))?~clock_i2c:0); 51 | assign i2c_sdat=reg_sdat?1'bz:0; 52 | 53 | always@(posedge clock_i2c) 54 | begin 55 | if(!camera_rstn) 56 | cyc_count<=6'b111111; 57 | else 58 | begin 59 | if(start==0) 60 | cyc_count<=0; 61 | else if(cyc_count<6'b111111) 62 | cyc_count<=cyc_count+1; 63 | end 64 | end 65 | 66 | 67 | always@(posedge clock_i2c) 68 | begin 69 | if(!camera_rstn) 70 | begin 71 | tr_end<=0; 72 | ack1<=1; 73 | ack2<=1; 74 | ack3<=1; 75 | sclk<=1; 76 | reg_sdat<=1; 77 | end 78 | else 79 | case(cyc_count) 80 | 0:begin ack1<=1;ack2<=1;ack3<=1;tr_end<=0;sclk<=1;reg_sdat<=1;end 81 | 1:reg_sdat<=0; //开始传输 82 | 2:sclk<=0; 83 | 3:reg_sdat<=i2c_data[31]; 84 | 4:reg_sdat<=i2c_data[30]; 85 | 5:reg_sdat<=i2c_data[29]; 86 | 6:reg_sdat<=i2c_data[28]; 87 | 7:reg_sdat<=i2c_data[27]; 88 | 8:reg_sdat<=i2c_data[26]; 89 | 9:reg_sdat<=i2c_data[25]; 90 | 10:reg_sdat<=i2c_data[24]; 91 | 11:reg_sdat<=1; //应答信号 92 | 12:begin reg_sdat<=i2c_data[23];ack1<=i2c_sdat;end 93 | 13:reg_sdat<=i2c_data[22]; 94 | 14:reg_sdat<=i2c_data[21]; 95 | 15:reg_sdat<=i2c_data[20]; 96 | 16:reg_sdat<=i2c_data[19]; 97 | 17:reg_sdat<=i2c_data[18]; 98 | 18:reg_sdat<=i2c_data[17]; 99 | 19:reg_sdat<=i2c_data[16]; 100 | 20:reg_sdat<=1; //应答信号 101 | 21:begin reg_sdat<=i2c_data[15];ack1<=i2c_sdat;end 102 | 22:reg_sdat<=i2c_data[14]; 103 | 23:reg_sdat<=i2c_data[13]; 104 | 24:reg_sdat<=i2c_data[12]; 105 | 25:reg_sdat<=i2c_data[11]; 106 | 26:reg_sdat<=i2c_data[10]; 107 | 27:reg_sdat<=i2c_data[9]; 108 | 28:reg_sdat<=i2c_data[8]; 109 | 29:reg_sdat<=1; //应答信号 110 | 30:begin reg_sdat<=i2c_data[7];ack2<=i2c_sdat;end 111 | 31:reg_sdat<=i2c_data[6]; 112 | 32:reg_sdat<=i2c_data[5]; 113 | 33:reg_sdat<=i2c_data[4]; 114 | 34:reg_sdat<=i2c_data[3]; 115 | 35:reg_sdat<=i2c_data[2]; 116 | 36:reg_sdat<=i2c_data[1]; 117 | 37:reg_sdat<=i2c_data[0]; 118 | 38:reg_sdat<=1; //应答信号 119 | 39:begin ack3<=i2c_sdat;sclk<=0;reg_sdat<=0;end 120 | 40:sclk<=1; 121 | 41:begin reg_sdat<=1;tr_end<=1;end 122 | endcase 123 | 124 | end 125 | endmodule 126 | 127 | -------------------------------------------------------------------------------- /RTL/rtl_1/iic_dri.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_1/iic_dri.v -------------------------------------------------------------------------------- /RTL/rtl_1/ms72xx_ctl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_1/ms72xx_ctl.v -------------------------------------------------------------------------------- /RTL/rtl_1/power_on_delay.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company:Meyesemi 4 | // Engineer: Will 5 | // 6 | // Create Date: 2023-03-17 7 | // Design Name: 8 | // Module Name: 9 | // Project Name: 10 | // Target Devices: Pango 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 1.0 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | //camera power on timing requirement 22 | module power_on_delay( 23 | input clk_50M , 24 | input reset_n , 25 | output camera1_rstn , 26 | output camera2_rstn , 27 | output camera_pwnd , 28 | output initial_en 29 | ); 30 | reg [18:0]cnt1; 31 | reg [15:0]cnt2; 32 | reg [19:0]cnt3; 33 | reg initial_en; 34 | reg camera_rstn_reg; 35 | reg camera_pwnd_reg; 36 | 37 | assign camera1_rstn=camera_rstn_reg; 38 | assign camera2_rstn=camera_rstn_reg; 39 | assign camera_pwnd=camera_pwnd_reg; 40 | 41 | //5ms, delay from sensor power up stable to Pwdn pull down 42 | always@(posedge clk_50M)begin 43 | if(reset_n==1'b0) begin 44 | cnt1<=0; 45 | camera_pwnd_reg<=1'b1;// 1'b1 46 | end 47 | else if(cnt1<19'h40000) begin 48 | cnt1<=cnt1+1'b1; 49 | camera_pwnd_reg<=1'b1; 50 | end 51 | else 52 | camera_pwnd_reg<=1'b0; 53 | end 54 | 55 | //1.3ms, delay from pwdn low to resetb pull up 56 | always@(posedge clk_50M)begin 57 | if(camera_pwnd_reg==1) begin 58 | cnt2<=0; 59 | camera_rstn_reg<=1'b0; 60 | end 61 | else if(cnt2<16'hffff) begin 62 | cnt2<=cnt2+1'b1; 63 | camera_rstn_reg<=1'b0; 64 | end 65 | else 66 | camera_rstn_reg<=1'b1; 67 | end 68 | 69 | //21ms, delay from resetb pul high to SCCB initialization 70 | always@(posedge clk_50M)begin 71 | if(camera_rstn_reg==0) begin 72 | cnt3<=0; 73 | initial_en<=1'b0; 74 | end 75 | else if(cnt3<20'hfffff) begin 76 | cnt3<=cnt3+1'b1; 77 | initial_en<=1'b0; 78 | end 79 | else 80 | initial_en<=1'b1; 81 | end 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /RTL/rtl_1/rd_buf.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Meyesemi 4 | // Engineer: Nill 5 | // 6 | // Create Date: 15/03/23 15:02:21 7 | // Design Name: 8 | // Module Name: rd_buf 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `define UD #1 22 | module rd_buf #( 23 | parameter ADDR_WIDTH = 6'd27, 24 | parameter ADDR_OFFSET = 32'h0000_0000, 25 | parameter H_NUM = 12'd1920, 26 | parameter V_NUM = 12'd1080, 27 | parameter DQ_WIDTH = 12'd32, 28 | parameter LEN_WIDTH = 12'd16, 29 | parameter PIX_WIDTH = 12'd24, 30 | parameter LINE_ADDR_WIDTH = 16'd19, 31 | parameter FRAME_CNT_WIDTH = 16'd8 32 | ) ( 33 | input ddr_clk, 34 | input ddr_rstn, 35 | 36 | input vout_clk, 37 | input rd_fsync, 38 | input rd_en, 39 | output vout_de, 40 | output [PIX_WIDTH- 1'b1 : 0] vout_data, 41 | 42 | input init_done, 43 | 44 | output ddr_rreq, 45 | output [ADDR_WIDTH- 1'b1 : 0] ddr_raddr, 46 | output [LEN_WIDTH- 1'b1 : 0] ddr_rd_len, 47 | input ddr_rrdy, 48 | input ddr_rdone, 49 | 50 | input [8*DQ_WIDTH- 1'b1 : 0] ddr_rdata, 51 | input ddr_rdata_en 52 | ); 53 | localparam SIM = 1'b0; 54 | localparam RAM_WIDTH = 16'd32; 55 | localparam DDR_DATA_WIDTH = DQ_WIDTH * 8; 56 | localparam WR_LINE_NUM = H_NUM * PIX_WIDTH/RAM_WIDTH; 57 | localparam RD_LINE_NUM = WR_LINE_NUM * RAM_WIDTH/DDR_DATA_WIDTH; 58 | localparam DDR_ADDR_OFFSET= RD_LINE_NUM*DDR_DATA_WIDTH/DQ_WIDTH; 59 | 60 | //=========================================================================== 61 | reg rd_fsync_1d; 62 | reg rd_en_1d,rd_en_2d; 63 | wire rd_rst; 64 | reg ddr_rstn_1d,ddr_rstn_2d; 65 | always @(posedge vout_clk) 66 | begin 67 | rd_fsync_1d <= rd_fsync; 68 | rd_en_1d <= rd_en; 69 | rd_en_2d <= rd_en_1d; 70 | ddr_rstn_1d <= ddr_rstn; 71 | ddr_rstn_2d <= ddr_rstn_1d; 72 | end 73 | assign rd_rst = ~rd_fsync_1d &rd_fsync; 74 | 75 | //=========================================================================== 76 | reg wr_fsync_1d,wr_fsync_2d,wr_fsync_3d; 77 | wire wr_rst; 78 | 79 | reg wr_en_1d,wr_en_2d,wr_en_3d; 80 | reg wr_trig; 81 | reg [11:0] wr_line; 82 | always @(posedge ddr_clk) 83 | begin 84 | wr_fsync_1d <= rd_fsync; 85 | wr_fsync_2d <= wr_fsync_1d; 86 | wr_fsync_3d <= wr_fsync_2d; 87 | 88 | wr_en_1d <= rd_en; 89 | wr_en_2d <= wr_en_1d; 90 | wr_en_3d <= wr_en_2d; 91 | 92 | wr_trig <= wr_rst || (~wr_en_3d && wr_en_2d && wr_line != V_NUM); 93 | end 94 | always @(posedge ddr_clk) 95 | begin 96 | if(wr_rst || (~ddr_rstn)) 97 | wr_line <= 12'd1; 98 | else if(wr_trig) 99 | wr_line <= wr_line + 12'd1; 100 | end 101 | 102 | assign wr_rst = ~wr_fsync_3d && wr_fsync_2d; 103 | 104 | //========================================================================== 105 | reg [FRAME_CNT_WIDTH - 1'b1 :0] wr_frame_cnt=0; 106 | always @(posedge ddr_clk) 107 | begin 108 | if(wr_rst) 109 | wr_frame_cnt <= wr_frame_cnt + 1'b1; 110 | else 111 | wr_frame_cnt <= wr_frame_cnt; 112 | end 113 | 114 | reg [LINE_ADDR_WIDTH - 1'b1 :0] wr_cnt; 115 | always @(posedge ddr_clk) 116 | begin 117 | if(wr_rst) 118 | wr_cnt <= 9'd0; 119 | else if(ddr_rdone) 120 | wr_cnt <= wr_cnt + DDR_ADDR_OFFSET; 121 | else 122 | wr_cnt <= wr_cnt; 123 | end 124 | 125 | assign ddr_rreq = wr_trig; 126 | assign ddr_raddr = {wr_frame_cnt[0],wr_cnt} + ADDR_OFFSET; 127 | assign ddr_rd_len = RD_LINE_NUM; 128 | 129 | reg [ 8:0] wr_addr; 130 | reg [11:0] rd_addr; 131 | wire [RAM_WIDTH-1:0] rd_data; 132 | 133 | //=========================================================================== 134 | always @(posedge ddr_clk) 135 | begin 136 | if(wr_rst) 137 | wr_addr <= (SIM == 1'b1) ? 9'd180 : 9'd0; 138 | else if(ddr_rdata_en) 139 | wr_addr <= wr_addr + 9'd1; 140 | else 141 | wr_addr <= wr_addr; 142 | end 143 | 144 | rd_fram_buf rd_fram_buf ( 145 | .wr_data ( ddr_rdata ),// input [255:0] 146 | .wr_addr ( wr_addr ),// input [8:0] 147 | .wr_en ( ddr_rdata_en ),// input 148 | .wr_clk ( ddr_clk ),// input 149 | .wr_rst ( ~ddr_rstn ),// input 150 | .rd_addr ( rd_addr ),// input [11:0] 151 | .rd_data ( rd_data ),// output [31:0] 152 | .rd_clk ( vout_clk ),// input 153 | .rd_rst ( ~ddr_rstn_2d ) // input 154 | ); 155 | 156 | reg [1:0] rd_cnt; 157 | wire read_en; 158 | always @(posedge vout_clk) 159 | begin 160 | if(rd_en) 161 | rd_cnt <= rd_cnt + 1'b1; 162 | else 163 | rd_cnt <= 2'd0; 164 | end 165 | 166 | always @(posedge vout_clk) 167 | begin 168 | if(rd_rst) 169 | rd_addr <= 'd0; 170 | else if(read_en) 171 | rd_addr <= rd_addr + 1'b1; 172 | else 173 | rd_addr <= rd_addr; 174 | end 175 | 176 | reg [PIX_WIDTH- 1'b1 : 0] read_data; 177 | reg [RAM_WIDTH-1:0] rd_data_1d; 178 | always @(posedge vout_clk) 179 | begin 180 | rd_data_1d <= rd_data; 181 | end 182 | 183 | generate 184 | if(PIX_WIDTH == 6'd24) 185 | begin 186 | assign read_en = rd_en && (rd_cnt != 2'd3); 187 | 188 | always @(posedge vout_clk) 189 | begin 190 | if(rd_en_1d) 191 | begin 192 | if(rd_cnt[1:0] == 2'd1) 193 | read_data <= rd_data[PIX_WIDTH-1:0]; 194 | else if(rd_cnt[1:0] == 2'd2) 195 | read_data <= {rd_data[15:0],rd_data_1d[31:PIX_WIDTH]}; 196 | else if(rd_cnt[1:0] == 2'd3) 197 | read_data <= {rd_data[7:0],rd_data_1d[31:16]}; 198 | else 199 | read_data <= rd_data_1d[31:8]; 200 | end 201 | else 202 | read_data <= 'd0; 203 | end 204 | end 205 | else if(PIX_WIDTH == 6'd16) 206 | begin 207 | assign read_en = rd_en && (rd_cnt[0] != 1'b1); 208 | 209 | always @(posedge vout_clk) 210 | begin 211 | if(rd_en_1d) 212 | begin 213 | if(rd_cnt[0]) 214 | read_data <= rd_data[15:0]; 215 | else 216 | read_data <= rd_data_1d[31:16]; 217 | end 218 | else 219 | read_data <= 'd0; 220 | end 221 | end 222 | else 223 | begin 224 | assign read_en = rd_en; 225 | 226 | always @(posedge vout_clk) 227 | begin 228 | read_data <= rd_data; 229 | end 230 | end 231 | endgenerate 232 | 233 | assign vout_de = rd_en_2d; 234 | assign vout_data = read_data; 235 | 236 | endmodule 237 | -------------------------------------------------------------------------------- /RTL/rtl_1/rd_ctrl.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Meyesemi 4 | // Engineer: Nill 5 | // 6 | // Create Date: 07/01/23 17:29:29 7 | // Design Name: 8 | // Module Name: rd_ctrl 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `define UD #1 22 | 23 | module rd_ctrl #( 24 | parameter CTRL_ADDR_WIDTH = 28, 25 | parameter MEM_DQ_WIDTH = 16 26 | )( 27 | input clk , 28 | input rst_n , 29 | 30 | input [CTRL_ADDR_WIDTH-1:0] read_addr , 31 | input [3:0] read_id , 32 | input [3:0] read_len , 33 | input read_en , 34 | output reg read_done_p =0, 35 | 36 | input read_ready , 37 | output [MEM_DQ_WIDTH*8-1:0] read_rdata , 38 | output read_rdata_en , 39 | 40 | output reg [CTRL_ADDR_WIDTH-1:0] axi_araddr =0, 41 | output reg [3:0] axi_arid =0, 42 | output reg [3:0] axi_arlen =0, 43 | output [2:0] axi_arsize , 44 | output [1:0] axi_arburst , 45 | output reg axi_arvalid =0, 46 | input axi_arready , //only support 2'b01: INCR 47 | 48 | output axi_rready , 49 | input [MEM_DQ_WIDTH*8-1:0] axi_rdata , 50 | input axi_rvalid , 51 | input axi_rlast , 52 | input [3:0] axi_rid , 53 | input [1:0] axi_rresp 54 | ); 55 | 56 | localparam E_IDLE = 3'd0; 57 | localparam E_RD = 3'd1; 58 | localparam E_END = 3'd2; 59 | localparam DQ_NUM = MEM_DQ_WIDTH/8; 60 | 61 | assign axi_arburst = 2'b01; 62 | assign axi_arsize = 3'b110; 63 | 64 | reg [2:0] test_rd_state; 65 | reg [3:0] rd_delay_cnt; 66 | 67 | always @(posedge clk or negedge rst_n) 68 | begin 69 | if (!rst_n) 70 | test_rd_state <= E_IDLE; 71 | else begin 72 | case (test_rd_state) 73 | E_IDLE: begin 74 | if (read_en) 75 | test_rd_state <= E_RD; 76 | end 77 | E_RD: begin 78 | if (axi_arvalid&axi_arready)//(rd_delay_cnt == 4'd7)// 79 | test_rd_state <= E_END; 80 | end 81 | E_END: begin 82 | if (rd_delay_cnt == 4'd15) 83 | test_rd_state <= E_IDLE; 84 | end 85 | default: test_rd_state <= E_IDLE; 86 | endcase 87 | end 88 | end 89 | 90 | 91 | always @(posedge clk or negedge rst_n) 92 | begin 93 | if (!rst_n) 94 | rd_delay_cnt <= 4'b0; 95 | else if((test_rd_state == E_END)) 96 | rd_delay_cnt <= rd_delay_cnt + 1'b1; 97 | else 98 | rd_delay_cnt <= 4'b0; 99 | end 100 | 101 | always @(posedge clk or negedge rst_n) 102 | begin 103 | if (!rst_n) begin 104 | axi_araddr <= {CTRL_ADDR_WIDTH{1'b0}}; 105 | axi_arid <= 4'b0; 106 | axi_arlen <= 4'b0; 107 | end 108 | else if((test_rd_state == E_IDLE) & read_en) 109 | begin 110 | axi_arid <= read_id; 111 | axi_araddr <= read_addr; 112 | axi_arlen <= read_len; 113 | end 114 | end 115 | 116 | always @(posedge clk or negedge rst_n) 117 | begin 118 | if (!rst_n) begin 119 | axi_arvalid <= 1'b0; 120 | read_done_p <= 1'b0; 121 | end 122 | else begin 123 | case (test_rd_state) 124 | E_IDLE: begin 125 | read_done_p <= 1'b0 ; 126 | axi_arvalid <= 1'b0; 127 | end 128 | E_RD: begin 129 | axi_arvalid <= 1'b1; 130 | 131 | if (axi_arvalid&axi_arready) 132 | axi_arvalid <= 1'b0; 133 | end 134 | E_END: begin 135 | axi_arvalid <= 1'b0; 136 | if(rd_delay_cnt == 4'd15) 137 | read_done_p <= 1'b1; 138 | end 139 | default: begin 140 | axi_arvalid <= 1'b0; 141 | read_done_p <= 1'b0; 142 | end 143 | endcase 144 | end 145 | end 146 | 147 | assign axi_ready = read_ready; 148 | assign read_rdata = axi_rdata; 149 | assign read_rdata_en = axi_rvalid; 150 | assign axi_rready = 1'b1; 151 | 152 | endmodule 153 | 154 | -------------------------------------------------------------------------------- /RTL/rtl_1/reg_config.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_1/reg_config.v -------------------------------------------------------------------------------- /RTL/rtl_1/reg_config_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_1/reg_config_1.v -------------------------------------------------------------------------------- /RTL/rtl_1/sync_vg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_1/sync_vg.v -------------------------------------------------------------------------------- /RTL/rtl_1/wr_buf.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Meyesemi 4 | // Engineer: Nill 5 | // 6 | // Create Date: 07/03/23 19:13:35 7 | // Design Name: 8 | // Module Name: wr_buf 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `define UD #1 22 | module wr_buf #( 23 | parameter ADDR_WIDTH = 6'd27, 24 | parameter ADDR_OFFSET = 32'h0000_0000, 25 | parameter H_NUM = 12'd1920, 26 | parameter V_NUM = 12'd1080, 27 | parameter DQ_WIDTH = 12'd32, 28 | parameter LEN_WIDTH = 12'd16, 29 | parameter PIX_WIDTH = 12'd24, 30 | parameter LINE_ADDR_WIDTH = 16'd19, 31 | parameter FRAME_CNT_WIDTH = 16'd8 32 | ) ( 33 | input ddr_clk, 34 | input ddr_rstn, 35 | 36 | input wr_clk, 37 | input wr_fsync, 38 | input wr_en, 39 | input [PIX_WIDTH- 1'b1 : 0] wr_data, 40 | 41 | input rd_bac, 42 | output ddr_wreq, 43 | output [ADDR_WIDTH- 1'b1 : 0] ddr_waddr, 44 | output [LEN_WIDTH- 1'b1 : 0] ddr_wr_len, 45 | input ddr_wrdy, 46 | input ddr_wdone, 47 | output [8*DQ_WIDTH- 1'b1 : 0] ddr_wdata, 48 | input ddr_wdata_req, 49 | 50 | output [FRAME_CNT_WIDTH-1 :0] frame_wcnt, 51 | output frame_wirq 52 | ); 53 | localparam RAM_WIDTH = 16'd32; 54 | localparam DDR_DATA_WIDTH = DQ_WIDTH * 8; 55 | localparam WR_LINE_NUM = H_NUM*PIX_WIDTH/RAM_WIDTH; 56 | localparam RD_LINE_NUM = WR_LINE_NUM*RAM_WIDTH/DDR_DATA_WIDTH; 57 | localparam DDR_ADDR_OFFSET= RD_LINE_NUM*DDR_DATA_WIDTH/DQ_WIDTH; 58 | 59 | //=========================================================================== 60 | reg wr_fsync_1d; 61 | reg wr_en_1d; 62 | wire wr_rst; 63 | reg wr_enable=0; 64 | 65 | reg ddr_rstn_1d,ddr_rstn_2d; 66 | 67 | always @(posedge wr_clk) 68 | begin 69 | wr_fsync_1d <= wr_fsync; 70 | wr_en_1d <= wr_en; 71 | ddr_rstn_1d <= ddr_rstn; 72 | ddr_rstn_2d <= ddr_rstn_1d; 73 | 74 | if(~wr_fsync_1d & wr_fsync && ddr_rstn_2d) 75 | wr_enable <= 1'b1; 76 | else 77 | wr_enable <= wr_enable; 78 | end 79 | 80 | assign wr_rst = (~wr_fsync_1d & wr_fsync) | (~ddr_rstn_2d); 81 | 82 | //=========================================================================== 83 | reg rd_fsync_1d,rd_fsync_2d,rd_fsync_3d; 84 | wire rd_rst; 85 | always @(posedge ddr_clk) 86 | begin 87 | rd_fsync_1d <= wr_fsync; 88 | rd_fsync_2d <= rd_fsync_1d; 89 | rd_fsync_3d <= rd_fsync_2d; 90 | end 91 | 92 | assign rd_rst = (~rd_fsync_3d && rd_fsync_2d) | (~ddr_rstn); 93 | 94 | //=========================================================================== 95 | // wr_addr control 96 | reg [11:0] x_cnt; 97 | reg [11:0] y_cnt; 98 | reg [31 : 0] write_data; 99 | reg [PIX_WIDTH- 1'b1 : 0] wr_data_1d; 100 | reg write_en; 101 | reg [11:0] wr_addr=0; 102 | 103 | generate 104 | if(PIX_WIDTH == 6'd24) 105 | begin 106 | always @(posedge wr_clk) 107 | begin 108 | wr_data_1d <= wr_data; 109 | 110 | write_en <= (x_cnt[1:0] != 0); 111 | 112 | if(x_cnt[1:0] == 2'd1) 113 | write_data <= {wr_data[7:0],wr_data_1d}; 114 | else if(x_cnt[1:0] == 2'd2) 115 | write_data <= {wr_data[15:0],wr_data_1d[PIX_WIDTH-1'b1:8]}; 116 | else if(x_cnt[1:0] == 2'd3) 117 | write_data <= {wr_data,wr_data_1d[PIX_WIDTH-1'b1:16]}; 118 | else 119 | write_data <= write_data; 120 | end 121 | end 122 | else if(PIX_WIDTH == 6'd16) 123 | begin 124 | always @(posedge wr_clk) 125 | begin 126 | wr_data_1d <= wr_data; 127 | 128 | write_en <= x_cnt[0]; 129 | if(x_cnt[0]) 130 | write_data <= {wr_data,wr_data_1d}; 131 | else 132 | write_data <= write_data; 133 | end 134 | end 135 | else 136 | begin 137 | always @(posedge wr_clk) 138 | begin 139 | write_data <= wr_data; 140 | write_en <= wr_en; 141 | end 142 | end 143 | endgenerate 144 | 145 | always @(posedge wr_clk) 146 | begin 147 | if(wr_rst) 148 | wr_addr <= 12'd0; 149 | else 150 | begin 151 | if(write_en & wr_enable) 152 | wr_addr <= wr_addr + 12'd1; 153 | else 154 | wr_addr <= wr_addr; 155 | end 156 | end 157 | 158 | always @(posedge wr_clk) 159 | begin 160 | if(wr_rst) 161 | x_cnt <= 12'd0; 162 | else if(wr_en & wr_enable) 163 | x_cnt <= x_cnt + 1'b1; 164 | else 165 | x_cnt <= 12'd0; 166 | end 167 | 168 | always @(posedge wr_clk) 169 | begin 170 | if(wr_rst) 171 | y_cnt <= 12'd0; 172 | else if(~wr_en_1d & wr_en & wr_enable) 173 | y_cnt <= y_cnt + 1'b1; 174 | else 175 | y_cnt <= y_cnt; 176 | end 177 | 178 | reg rd_pulse; 179 | always @(posedge wr_clk) 180 | begin 181 | if(x_cnt > H_NUM - 5'd20 & wr_enable) 182 | rd_pulse <= 1'b1; 183 | else 184 | rd_pulse <= 1'b0; 185 | end 186 | 187 | reg [8:0] rd_addr=0; 188 | wire [255:0] rd_wdata; 189 | reg [255:0] rd_wdata_1d=0; 190 | wr_fram_buf wr_fram_buf ( 191 | .wr_data ( write_data ),// input [31:0] 192 | .wr_addr ( wr_addr ),// input [11:0] 193 | .wr_en ( write_en ),// input 194 | .wr_clk ( wr_clk ),// input 195 | .wr_rst ( ~ddr_rstn_2d ),// input 196 | 197 | .rd_addr ( rd_addr ),// input [8:0] 198 | .rd_data ( rd_wdata ),// output [255:0] 199 | .rd_clk ( ddr_clk ),// input 200 | .rd_rst ( ~ddr_rstn ) // input 201 | ); 202 | 203 | reg rd_pulse_1d,rd_pulse_2d,rd_pulse_3d; 204 | always @(posedge ddr_clk) 205 | begin 206 | rd_pulse_1d <= rd_pulse; 207 | rd_pulse_2d <= rd_pulse_1d; 208 | rd_pulse_3d <= rd_pulse_2d; 209 | end 210 | 211 | wire rd_trig; 212 | assign rd_trig = ~rd_pulse_3d && rd_pulse_2d; 213 | 214 | reg ddr_wr_req=0; 215 | reg ddr_wr_req_1d; 216 | assign ddr_wreq =ddr_wr_req; 217 | 218 | always @(posedge ddr_clk) 219 | begin 220 | ddr_wr_req_1d <= ddr_wr_req; 221 | 222 | if(rd_trig) 223 | ddr_wr_req <= 1'b1; 224 | else if(ddr_wdata_req) 225 | ddr_wr_req <= 1'b0; 226 | else 227 | ddr_wr_req <= ddr_wr_req; 228 | end 229 | 230 | reg rd_en_1d; 231 | reg ddr_wdata_req_1d; 232 | always @(posedge ddr_clk) 233 | begin 234 | ddr_wdata_req_1d <= ddr_wdata_req; 235 | rd_en_1d <= ~ddr_wr_req_1d & ddr_wr_req; 236 | end 237 | 238 | always @(posedge ddr_clk) 239 | begin 240 | if(ddr_wdata_req_1d | rd_en_1d) 241 | rd_wdata_1d <= rd_wdata; 242 | else 243 | rd_wdata_1d <= rd_wdata_1d; 244 | end 245 | 246 | reg line_flag=0; 247 | always@(posedge ddr_clk) 248 | begin 249 | if(rd_rst) 250 | line_flag <= 1'b0; 251 | else if(rd_trig) 252 | line_flag <= 1'b1; 253 | else 254 | line_flag <= line_flag; 255 | end 256 | 257 | always @(posedge ddr_clk) 258 | begin 259 | if(rd_rst) 260 | rd_addr <= 1'b0; 261 | else if(~ddr_wr_req_1d & ddr_wr_req) 262 | rd_addr <= rd_addr + 1'b1; 263 | else if(ddr_wdata_req) 264 | rd_addr <= rd_addr + 1'b1; 265 | else if(rd_trig & line_flag) 266 | rd_addr <= rd_addr - 1'b1; 267 | else 268 | rd_addr <= rd_addr; 269 | end 270 | 271 | reg [FRAME_CNT_WIDTH - 1'b1 :0] rd_frame_cnt=1; 272 | always @(posedge ddr_clk) 273 | begin 274 | if(~ddr_rstn) 275 | rd_frame_cnt <= 'd0; 276 | else if(~rd_fsync_3d && rd_fsync_2d) 277 | rd_frame_cnt <= rd_frame_cnt + 1'b1; 278 | else 279 | rd_frame_cnt <= rd_frame_cnt; 280 | end 281 | 282 | reg [LINE_ADDR_WIDTH - 1'b1 :0] rd_cnt; 283 | always @(posedge ddr_clk) 284 | begin 285 | if(rd_rst) 286 | rd_cnt <= 9'd0; 287 | else if(ddr_wdone) 288 | rd_cnt <= rd_cnt + DDR_ADDR_OFFSET; 289 | else 290 | rd_cnt <= rd_cnt; 291 | end 292 | 293 | reg wirq_en=0; 294 | always @(posedge ddr_clk) 295 | begin 296 | if (~rd_fsync_2d && rd_fsync_3d) 297 | wirq_en <= 1'b1; 298 | else 299 | wirq_en <= wirq_en; 300 | end 301 | 302 | assign ddr_wdata = (~ddr_wdata_req_1d & ddr_wdata_req) ? rd_wdata_1d : rd_wdata; 303 | assign ddr_waddr = {rd_frame_cnt[0],rd_cnt} + ADDR_OFFSET; 304 | assign ddr_wr_len = RD_LINE_NUM; 305 | assign frame_wcnt = rd_frame_cnt; 306 | assign frame_wirq = wirq_en && rd_fsync_3d; 307 | 308 | endmodule 309 | -------------------------------------------------------------------------------- /RTL/rtl_1/wr_cmd_trans.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Meyesemi 4 | // Engineer: Nill 5 | // 6 | // Create Date: 29/01/23 14:24:22 7 | // Design Name: 8 | // Module Name: wr_cmd_trans 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `define UD #1 22 | module wr_cmd_trans #( 23 | parameter CTRL_ADDR_WIDTH = 28, 24 | parameter MEM_DQ_WIDTH = 16 25 | ) ( 26 | input clk, 27 | input rstn, 28 | 29 | input wr_cmd_en, 30 | input [CTRL_ADDR_WIDTH-1:0] wr_cmd_addr, 31 | input [31: 0] wr_cmd_len, 32 | output reg wr_cmd_ready, 33 | output reg wr_cmd_done, 34 | input wr_bac, 35 | input [MEM_DQ_WIDTH*8-1:0] wr_ctrl_data, 36 | output wr_data_re, 37 | 38 | output reg wr_en=0, 39 | output reg [CTRL_ADDR_WIDTH-1:0] wr_addr=0, 40 | output reg [ 3: 0] wr_id=0, 41 | output reg [ 3: 0] wr_len=0, 42 | output reg wr_data_en=0, 43 | output [MEM_DQ_WIDTH*8-1:0] wr_data, 44 | input wr_ready, 45 | input wr_done, 46 | 47 | input rd_cmd_en, 48 | input [CTRL_ADDR_WIDTH-1:0] rd_cmd_addr, 49 | input [31: 0] rd_cmd_len, 50 | output reg rd_cmd_ready=1, 51 | output reg rd_cmd_done=0, 52 | input read_en, 53 | 54 | output reg rd_en =0, 55 | output reg [CTRL_ADDR_WIDTH-1:0] rd_addr =0, 56 | output reg [3:0] rd_id =0, 57 | output reg [3:0] rd_len =0, 58 | input rd_done_p 59 | ); 60 | 61 | reg wr_done_1d; 62 | reg wr_cmd_en_1d; 63 | reg [15:0] wr_cnt; 64 | reg write_enable; 65 | reg [31:0] wr_trans_len; 66 | wire wr_cmd_trig; 67 | always @(posedge clk) 68 | begin 69 | wr_done_1d <= wr_done; 70 | wr_cmd_en_1d <= wr_cmd_en; 71 | 72 | if(wr_cmd_trig) 73 | wr_trans_len <= wr_cmd_len; 74 | else 75 | wr_trans_len <= wr_trans_len; 76 | end 77 | assign wr_cmd_trig = ~wr_cmd_en_1d & wr_cmd_en; 78 | 79 | always @(posedge clk) 80 | begin 81 | if(~rstn) 82 | wr_en <= 1'd0; 83 | else if(wr_cmd_trig) 84 | wr_en <= 1'd1; 85 | else if(wr_cnt < wr_trans_len && (~wr_done_1d && wr_done)) 86 | wr_en <= 1'd1; 87 | else 88 | wr_en <= 1'd0; 89 | end 90 | 91 | always @(posedge clk) 92 | begin 93 | if(~rstn) 94 | write_enable <= 1'd0; 95 | else if(wr_cmd_trig) 96 | write_enable <= 1'd1; 97 | else if(wr_cnt >= wr_trans_len - 16 && (~wr_done_1d && wr_done)) 98 | write_enable <= 1'd0; 99 | else 100 | write_enable <= write_enable; 101 | end 102 | 103 | always @(posedge clk) 104 | begin 105 | if(~rstn) 106 | wr_cnt <= 16'd0; 107 | else if(wr_cmd_trig) 108 | wr_cnt <= 16'd16; 109 | else if(write_enable && (~wr_done_1d && wr_done)) 110 | begin 111 | if(wr_cnt >= wr_trans_len - 16) 112 | wr_cnt <= wr_cmd_len; 113 | else 114 | wr_cnt <= wr_cnt + 16'd16; 115 | end 116 | else 117 | wr_cnt <= wr_cnt; 118 | end 119 | 120 | always @(posedge clk) 121 | begin 122 | if(~rstn) 123 | wr_cmd_done <= 1'd0; 124 | else 125 | begin 126 | if(wr_cnt == wr_trans_len && (~wr_done_1d && wr_done)) 127 | wr_cmd_done <= 1'd1; 128 | else 129 | wr_cmd_done <= 1'd0; 130 | end 131 | end 132 | 133 | always @(posedge clk) 134 | begin 135 | if(~rstn) 136 | wr_cmd_ready <= 1'd1; 137 | else 138 | begin 139 | if(wr_cmd_trig) 140 | wr_cmd_ready <= 1'd0; 141 | else if(wr_cmd_done) 142 | wr_cmd_ready <= 1'd1; 143 | else 144 | wr_cmd_ready <= wr_cmd_ready; 145 | end 146 | end 147 | 148 | always @(posedge clk) 149 | begin 150 | if(~rstn) 151 | begin 152 | wr_addr <= {CTRL_ADDR_WIDTH{1'b0}}; 153 | wr_id <= 'd0; 154 | wr_len <= 4'd15; 155 | end 156 | else if(wr_cmd_trig) 157 | begin 158 | wr_addr <= wr_cmd_addr; 159 | wr_id <= 'd0; 160 | wr_len <= 4'd15; 161 | end 162 | else 163 | begin 164 | if(~wr_done_1d && wr_done) 165 | begin 166 | if(wr_cnt >= wr_trans_len - 16) 167 | wr_len <= wr_trans_len - wr_cnt - 1'b1; 168 | else 169 | wr_len <= 4'd15; 170 | 171 | wr_addr <= wr_addr + {wr_len,3'd0} + 4'b1000;//12'd1024; 172 | end 173 | else 174 | begin 175 | // wr_id <= wr_id; 176 | wr_addr <= wr_addr; 177 | end 178 | end 179 | end 180 | 181 | reg [3:0] burst_cnt ; 182 | reg wr_data_re_reg; 183 | always @(posedge clk) 184 | begin 185 | if(~rstn) 186 | wr_data_re_reg <= 1'b0; 187 | else if(wr_ready) 188 | begin 189 | if(burst_cnt == wr_len && wr_data_re_reg) 190 | wr_data_re_reg <= 1'b0; 191 | else 192 | wr_data_re_reg <= 1'b1; 193 | end 194 | else 195 | wr_data_re_reg <= 1'b0; 196 | end 197 | assign wr_data_re = wr_ready;// & wr_data_re_reg; 198 | 199 | always @(posedge clk) 200 | begin 201 | if(wr_data_re) 202 | wr_data_en <= 1'b1; 203 | else 204 | wr_data_en <= 1'b0; 205 | end 206 | 207 | always @(posedge clk) 208 | begin 209 | if(~rstn) 210 | burst_cnt <= 1'b0; 211 | else if(wr_data_re && wr_ready) 212 | begin 213 | if(burst_cnt == wr_len) 214 | burst_cnt <= 1'b0; 215 | else 216 | burst_cnt <= burst_cnt + 1'b1; 217 | end 218 | else if(wr_bac) 219 | burst_cnt <= burst_cnt - 1'b1; 220 | else 221 | burst_cnt <= burst_cnt; 222 | end 223 | 224 | assign wr_data = wr_ctrl_data; 225 | 226 | //============================================================================ 227 | // read chanel 228 | //============================================================================ 229 | reg read_enable; 230 | reg [15:0] rd_cnt; 231 | reg rd_done_1d; 232 | reg rd_cmd_en_1d; 233 | reg [31:0] rd_trans_len; 234 | wire rd_cmd_trig; 235 | assign rd_cmd_trig = ~rd_cmd_en_1d & rd_cmd_en; 236 | always @(posedge clk) 237 | begin 238 | rd_done_1d <= rd_done_p; 239 | rd_cmd_en_1d <= rd_cmd_en; 240 | if(rd_cmd_trig) 241 | rd_trans_len <= rd_cmd_len; 242 | else 243 | rd_trans_len <= rd_trans_len; 244 | 245 | 246 | if(~rstn) 247 | read_enable <= 1'b0; 248 | else if(rd_cmd_trig) 249 | read_enable <= 1'b1; 250 | else if(rd_cnt >= rd_trans_len - 16 && (~rd_done_1d && rd_done_p)) 251 | read_enable <= 1'b0; 252 | else 253 | read_enable <= read_enable; 254 | end 255 | 256 | reg read_enable_1d; 257 | 258 | always @(posedge clk) 259 | begin 260 | read_enable_1d <= read_enable; 261 | 262 | if(~rstn) 263 | rd_en <= 1'd0; 264 | else if(~read_enable_1d && read_enable) 265 | rd_en <= 1'd1; 266 | else if(rd_cnt < rd_trans_len && (~rd_done_1d && rd_done_p)) 267 | rd_en <= 1'd1; 268 | else 269 | rd_en <= 1'd0; 270 | end 271 | 272 | reg [15:0] rd_data_cnt; 273 | always @(posedge clk) 274 | begin 275 | if(~rstn) 276 | rd_data_cnt <= 1'd0; 277 | else if(rd_cmd_trig) 278 | rd_data_cnt <= 1'd0; 279 | else if(read_en) 280 | begin 281 | if(rd_data_cnt == rd_trans_len - 1'b1) 282 | rd_data_cnt <= 1'd0; 283 | else 284 | rd_data_cnt <= rd_data_cnt + 1'd1; 285 | end 286 | else 287 | rd_data_cnt <= rd_data_cnt; 288 | end 289 | 290 | always @(posedge clk) 291 | begin 292 | if(~rstn) 293 | rd_cmd_done <= 1'd0; 294 | else 295 | begin 296 | if(rd_data_cnt == rd_trans_len - 1'b1) 297 | rd_cmd_done <= 1'd1; 298 | else 299 | rd_cmd_done <= 1'd0; 300 | end 301 | end 302 | 303 | always @(posedge clk) 304 | begin 305 | if(~rstn) 306 | rd_cmd_ready <= 1'd1; 307 | else 308 | begin 309 | if(rd_cmd_trig) 310 | rd_cmd_ready <= 1'd0; 311 | else if(rd_cnt == rd_trans_len && (~rd_done_1d && rd_done_p)) 312 | rd_cmd_ready <= 1'd1; 313 | else 314 | rd_cmd_ready <= rd_cmd_ready; 315 | end 316 | end 317 | 318 | always @(posedge clk) 319 | begin 320 | if(~rstn) 321 | rd_cnt <= 16'd0; 322 | else if(~read_enable_1d && read_enable) 323 | rd_cnt <= 16'd16; 324 | else if(read_enable && (~rd_done_1d && rd_done_p)) 325 | begin 326 | if(rd_cnt >= rd_cmd_len - 16) 327 | rd_cnt <= rd_cmd_len; 328 | else 329 | rd_cnt <= rd_cnt + 16'd16; 330 | end 331 | else 332 | rd_cnt <= rd_cnt; 333 | end 334 | 335 | always @(posedge clk) 336 | begin 337 | if(~rstn) 338 | begin 339 | rd_addr <= {CTRL_ADDR_WIDTH{1'b0}}; 340 | rd_id <= 'd0; 341 | rd_len <= 4'd15; 342 | end 343 | else if(~read_enable_1d && read_enable) 344 | begin 345 | rd_addr <= rd_cmd_addr; 346 | rd_id <= 'd0; 347 | rd_len <= 4'd15; 348 | end 349 | else 350 | begin 351 | if(~rd_done_1d && rd_done_p) 352 | begin 353 | if(rd_cnt >= rd_cmd_len - 16) 354 | rd_len <= rd_cmd_len - rd_cnt - 1'b1; 355 | else 356 | rd_len <= 4'd15; 357 | 358 | rd_addr <= rd_addr + {rd_len,3'd0} + 4'b1000;//12'd1024; 359 | end 360 | else 361 | begin 362 | rd_addr <= rd_addr; 363 | end 364 | end 365 | end 366 | 367 | endmodule 368 | -------------------------------------------------------------------------------- /RTL/rtl_1/wr_ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_1/wr_ctrl.v -------------------------------------------------------------------------------- /RTL/rtl_1/wr_rd_ctrl_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_1/wr_rd_ctrl_top.v -------------------------------------------------------------------------------- /RTL/rtl_2/arp_cache.v: -------------------------------------------------------------------------------- 1 | module arp_cache 2 | ( 3 | input clk , 4 | input rst_n , 5 | 6 | input arp_found, 7 | input [31:0] arp_rec_source_ip_addr, 8 | input [47:0] arp_rec_source_mac_addr, 9 | 10 | input [31:0] destination_ip_addr, 11 | output reg [47:0] destination_mac_addr, 12 | 13 | output reg mac_not_exist 14 | ) ; 15 | 16 | reg [79:0] arp_cache ; 17 | 18 | //init arp cache 19 | always @(posedge clk or negedge rst_n) 20 | begin 21 | if (~rst_n) 22 | arp_cache <= 80'h00_00_00_00_ff_ff_ff_ff_ff_ff ; 23 | else if (arp_found) 24 | arp_cache <= {arp_rec_source_ip_addr, arp_rec_source_mac_addr} ; 25 | else 26 | arp_cache <= arp_cache ; 27 | end 28 | 29 | always @(posedge clk or negedge rst_n) 30 | begin 31 | if (~rst_n) 32 | destination_mac_addr <= 48'hff_ff_ff_ff_ff_ff ; 33 | else if (destination_ip_addr == arp_cache[79:48]) 34 | destination_mac_addr <= arp_cache[47:0] ; 35 | else 36 | destination_mac_addr <= 48'hff_ff_ff_ff_ff_ff ; 37 | end 38 | 39 | always @(posedge clk or negedge rst_n) 40 | begin 41 | if (~rst_n) 42 | mac_not_exist <= 1'b0 ; 43 | else if (destination_ip_addr != arp_cache[79:48]) 44 | mac_not_exist <= 1'b1 ; 45 | else if (destination_ip_addr == arp_cache[79:48] && arp_cache[47:0] == 48'hff_ff_ff_ff_ff_ff) 46 | mac_not_exist <= 1'b1 ; 47 | else 48 | mac_not_exist <= 1'b0 ; 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /RTL/rtl_2/arp_rx.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////////// 2 | //Module Name : arp_rx 3 | //Description : This module is used to receive ARP data and send ARP reply request 4 | // 5 | ////////////////////////////////////////////////////////////////////////////////////// 6 | `timescale 1 ns/1 ns 7 | module arp_rx 8 | //# 9 | //( 10 | // parameter local_ip_addr = 32'hc0a80002, 11 | // parameter local_mac_addr = 48'h00_0a_35_01_fe_c0 12 | //) 13 | ( 14 | input clk, 15 | input rst_n, 16 | 17 | input [31:0] local_ip_addr, 18 | input [47:0] local_mac_addr, 19 | input [7:0] arp_rx_data, //arp received data 20 | input arp_rx_req, //arp rx request from mac 21 | output reg arp_rx_end, //arp rx end 22 | 23 | input arp_reply_ack, //arp reply ack from arp reply module 24 | output reg arp_reply_req, //arp reply request to arp reply module 25 | 26 | output reg [31:0] arp_rec_source_ip_addr, //arp received source ip address 27 | output reg [47:0] arp_rec_source_mac_addr, //arp received mac address 28 | output reg arp_found //found destination mac address 29 | ) ; 30 | 31 | localparam ARP_REQUEST_CODE = 16'h0001 ; 32 | localparam ARP_REPLY_CODE = 16'h0002 ; 33 | 34 | reg [31:0] arp_rec_destination_ip_addr ; 35 | reg [47:0] arp_rec_destination_mac_addr ; 36 | reg [15:0] arp_rec_op ; 37 | reg [7:0] arp_rx_cnt ; 38 | 39 | parameter IDLE = 4'b0001 ; 40 | parameter ARP_REC_DATA = 4'b0010 ; 41 | parameter ARP_WAIT = 4'b0100 ; 42 | parameter ARP_END = 4'b1000 ; 43 | 44 | reg [3:0] state ; 45 | reg [3:0] next_state ; 46 | 47 | always @(posedge clk or negedge rst_n) 48 | begin 49 | if (~rst_n) 50 | state <= IDLE ; 51 | else 52 | state <= next_state ; 53 | end 54 | 55 | always @(*) 56 | begin 57 | case(state) 58 | IDLE : begin 59 | if (arp_rx_req) 60 | next_state <= ARP_REC_DATA ; 61 | else 62 | next_state <= IDLE ; 63 | end 64 | ARP_REC_DATA : begin 65 | if (arp_rx_cnt == 45) 66 | next_state <= ARP_WAIT ; 67 | else 68 | next_state <= ARP_REC_DATA ; 69 | end 70 | ARP_WAIT : begin 71 | if (arp_rx_cnt == 99) 72 | next_state <= ARP_END ; 73 | else 74 | next_state <= ARP_WAIT ; 75 | end 76 | 77 | ARP_END : next_state <= IDLE ; 78 | 79 | default : next_state <= IDLE ; 80 | endcase 81 | end 82 | 83 | 84 | always @(posedge clk or negedge rst_n) 85 | begin 86 | if (~rst_n) 87 | arp_rx_end <= 1'b0 ; 88 | else if (state == ARP_REC_DATA || arp_rx_cnt == 44) 89 | arp_rx_end <= 1'b1 ; 90 | else 91 | arp_rx_end <= 1'b0 ; 92 | end 93 | 94 | //received arp request 95 | always @(posedge clk or negedge rst_n) 96 | begin 97 | if (~rst_n) 98 | arp_reply_req <= 1'b0 ; 99 | else if (arp_rx_req) 100 | arp_reply_req <= 1'b0 ; 101 | else if (arp_reply_ack) 102 | arp_reply_req <= 1'b0 ; 103 | else if (state == ARP_END) 104 | begin 105 | if (arp_rec_op == ARP_REQUEST_CODE && arp_rec_destination_ip_addr == local_ip_addr) 106 | arp_reply_req <= 1'b1 ; 107 | end 108 | end 109 | //received arp reply 110 | always @(posedge clk or negedge rst_n) 111 | begin 112 | if (~rst_n) 113 | arp_found <= 1'b0 ; 114 | else if (state == ARP_END) 115 | begin 116 | if (arp_rec_op == ARP_REPLY_CODE && arp_rec_destination_ip_addr == local_ip_addr && arp_rec_destination_mac_addr == local_mac_addr) 117 | arp_found <= 1'b1 ; 118 | end 119 | else 120 | arp_found <= 1'b0 ; 121 | end 122 | 123 | always @(posedge clk or negedge rst_n) 124 | begin 125 | if (~rst_n) 126 | arp_rx_cnt <= 8'd0 ; 127 | else if (state == ARP_REC_DATA || state == ARP_WAIT) 128 | arp_rx_cnt <= arp_rx_cnt + 1'b1 ; 129 | else 130 | arp_rx_cnt <= 8'd0 ; 131 | end 132 | 133 | always @(posedge clk or negedge rst_n) 134 | begin 135 | if (~rst_n) 136 | arp_rec_op <= 16'd0 ; 137 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd6) 138 | arp_rec_op[15:8] <= arp_rx_data ; 139 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd7) 140 | arp_rec_op[7:0] <= arp_rx_data ; 141 | end 142 | 143 | always @(posedge clk or negedge rst_n) 144 | begin 145 | if (~rst_n) 146 | arp_rec_source_mac_addr <= 48'd0 ; 147 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd8) 148 | arp_rec_source_mac_addr[47:40] <= arp_rx_data ; 149 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd9) 150 | arp_rec_source_mac_addr[39:32] <= arp_rx_data ; 151 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd10) 152 | arp_rec_source_mac_addr[31:24] <= arp_rx_data ; 153 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd11) 154 | arp_rec_source_mac_addr[23:16] <= arp_rx_data ; 155 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd12) 156 | arp_rec_source_mac_addr[15:8] <= arp_rx_data ; 157 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd13) 158 | arp_rec_source_mac_addr[7:0] <= arp_rx_data ; 159 | end 160 | 161 | always @(posedge clk or negedge rst_n) 162 | begin 163 | if (~rst_n) 164 | arp_rec_source_ip_addr <= 32'd0 ; 165 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd14) 166 | arp_rec_source_ip_addr[31:24] <= arp_rx_data ; 167 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd15) 168 | arp_rec_source_ip_addr[23:16] <= arp_rx_data ; 169 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd16) 170 | arp_rec_source_ip_addr[15:8] <= arp_rx_data ; 171 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd17) 172 | arp_rec_source_ip_addr[7:0] <= arp_rx_data ; 173 | end 174 | 175 | always @(posedge clk or negedge rst_n) 176 | begin 177 | if (~rst_n) 178 | arp_rec_destination_mac_addr <= 48'd0 ; 179 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd18) 180 | arp_rec_destination_mac_addr[47:40] <= arp_rx_data ; 181 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd19) 182 | arp_rec_destination_mac_addr[39:32] <= arp_rx_data ; 183 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd20) 184 | arp_rec_destination_mac_addr[31:24] <= arp_rx_data ; 185 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd21) 186 | arp_rec_destination_mac_addr[23:16] <= arp_rx_data ; 187 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd22) 188 | arp_rec_destination_mac_addr[15:8] <= arp_rx_data ; 189 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd23) 190 | arp_rec_destination_mac_addr[7:0] <= arp_rx_data ; 191 | end 192 | 193 | always @(posedge clk or negedge rst_n) 194 | begin 195 | if (~rst_n) 196 | arp_rec_destination_ip_addr <= 32'd0 ; 197 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd24) 198 | arp_rec_destination_ip_addr[31:24] <= arp_rx_data ; 199 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd25) 200 | arp_rec_destination_ip_addr[23:16] <= arp_rx_data ; 201 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd26) 202 | arp_rec_destination_ip_addr[15:8] <= arp_rx_data ; 203 | else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd27) 204 | arp_rec_destination_ip_addr[7:0] <= arp_rx_data ; 205 | end 206 | 207 | 208 | endmodule 209 | -------------------------------------------------------------------------------- /RTL/rtl_2/arp_tx.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////////// 2 | //Module Name : arp_tx 3 | //Description : This module is used to send arp data when request arp or reply arp 4 | // 5 | ////////////////////////////////////////////////////////////////////////////////////// 6 | `timescale 1 ns/1 ns 7 | module arp_tx 8 | ( 9 | input clk , 10 | input rst_n , 11 | 12 | input [47:0] destination_mac_addr , //destination mac address 13 | input [47:0] source_mac_addr , //source mac address 14 | input [31:0] source_ip_addr , //source ip address 15 | input [31:0] destination_ip_addr , //destination ip address 16 | 17 | input mac_data_req, //mac layer request data 18 | input arp_request_req, //arp request 19 | output reg arp_reply_ack, //arp reply ack to arp rx module 20 | input arp_reply_req, //arp reply request from arp rx module 21 | output reg arp_tx_req, 22 | input [31:0] arp_rec_source_ip_addr, 23 | input [47:0] arp_rec_source_mac_addr , 24 | input mac_send_end, 25 | input mac_tx_ack, 26 | 27 | output reg arp_tx_ready, 28 | output reg [7:0] arp_tx_data, 29 | output reg arp_tx_end 30 | ) ; 31 | 32 | localparam mac_type = 16'h0806 ; 33 | localparam hardware_type = 16'h0001 ; 34 | localparam protocol_type = 16'h0800 ; 35 | localparam mac_length = 8'h06 ; 36 | localparam ip_length = 8'h04 ; 37 | 38 | localparam ARP_REQUEST_CODE = 16'h0001 ; 39 | localparam ARP_REPLY_CODE = 16'h0002 ; 40 | 41 | 42 | reg [15:0] op ; 43 | 44 | reg [31:0] arp_destination_ip_addr ; 45 | reg [47:0] arp_destination_mac_addr ; 46 | reg [15:0] arp_send_cnt ; 47 | reg [15:0] timeout ; 48 | reg mac_send_end_d0 ; 49 | 50 | parameter IDLE = 8'b00000001 ; 51 | parameter ARP_REQUEST_WAIT_0 = 8'b00000010 ; 52 | parameter ARP_REQUEST_WAIT_1 = 8'b00000100 ; 53 | parameter ARP_REQUEST = 8'b00001000 ; 54 | parameter ARP_REPLY_WAIT_0 = 8'b00010000 ; 55 | parameter ARP_REPLY_WAIT_1 = 8'b00100000 ; 56 | parameter ARP_REPLY = 8'b01000000 ; 57 | parameter ARP_END = 8'b10000000 ; 58 | 59 | reg [7:0] state ; 60 | reg [7:0] next_state ; 61 | 62 | always @(posedge clk or negedge rst_n) 63 | begin 64 | if (~rst_n) 65 | state <= IDLE ; 66 | else 67 | state <= next_state ; 68 | end 69 | 70 | always @(*) 71 | begin 72 | case(state) 73 | IDLE : 74 | begin 75 | if (arp_request_req) 76 | next_state <= ARP_REQUEST_WAIT_0 ; 77 | else if (arp_reply_req) 78 | next_state <= ARP_REPLY_WAIT_0 ; 79 | else 80 | next_state <= IDLE ; 81 | end 82 | ARP_REQUEST_WAIT_0 : 83 | begin 84 | if (mac_tx_ack) 85 | next_state <= ARP_REQUEST_WAIT_1 ; 86 | else 87 | next_state <= ARP_REQUEST_WAIT_0 ; 88 | end 89 | ARP_REQUEST_WAIT_1 : 90 | begin 91 | if (mac_data_req) 92 | next_state <= ARP_REQUEST ; 93 | else if (timeout == 16'hffff) 94 | next_state <= IDLE ; 95 | else 96 | next_state <= ARP_REQUEST_WAIT_1 ; 97 | end 98 | ARP_REQUEST : 99 | begin 100 | if (arp_tx_end) 101 | next_state <= ARP_END ; 102 | else 103 | next_state <= ARP_REQUEST ; 104 | end 105 | ARP_REPLY_WAIT_0 : 106 | begin 107 | if (mac_tx_ack) 108 | next_state <= ARP_REPLY_WAIT_1 ; 109 | else 110 | next_state <= ARP_REPLY_WAIT_0 ; 111 | end 112 | ARP_REPLY_WAIT_1 : 113 | begin 114 | if (mac_data_req) 115 | next_state <= ARP_REPLY ; 116 | else if (timeout == 16'hffff) 117 | next_state <= IDLE ; 118 | else 119 | next_state <= ARP_REPLY_WAIT_1 ; 120 | end 121 | ARP_REPLY : 122 | begin 123 | if (arp_tx_end) 124 | next_state <= ARP_END ; 125 | else 126 | next_state <= ARP_REPLY ; 127 | end 128 | ARP_END : 129 | begin 130 | if (mac_send_end_d0) 131 | next_state <= IDLE ; 132 | else 133 | next_state <= ARP_END ; 134 | end 135 | default : 136 | next_state <= IDLE ; 137 | endcase 138 | end 139 | 140 | always @(posedge clk or negedge rst_n) 141 | begin 142 | if (~rst_n) 143 | mac_send_end_d0 <= 1'b0 ; 144 | else 145 | mac_send_end_d0 <= mac_send_end ; 146 | end 147 | 148 | always @(posedge clk or negedge rst_n) 149 | begin 150 | if (~rst_n) 151 | arp_tx_req <= 1'b0 ; 152 | else if (state == ARP_REQUEST_WAIT_0 || state == ARP_REPLY_WAIT_0) 153 | arp_tx_req <= 1'b1 ; 154 | else 155 | arp_tx_req <= 1'b0 ; 156 | end 157 | 158 | always @(posedge clk or negedge rst_n) 159 | begin 160 | if (~rst_n) 161 | op <= 16'd0 ; 162 | else if (state == ARP_REPLY) 163 | op <= ARP_REPLY_CODE ; 164 | else 165 | op <= ARP_REQUEST_CODE ; 166 | end 167 | 168 | always @(posedge clk or negedge rst_n) 169 | begin 170 | if (~rst_n) 171 | arp_tx_ready <= 1'b0 ; 172 | else if (state == ARP_REQUEST_WAIT_1 || state == ARP_REPLY_WAIT_1) 173 | arp_tx_ready <= 1'b1 ; 174 | else 175 | arp_tx_ready <= 1'b0 ; 176 | end 177 | 178 | always @(posedge clk or negedge rst_n) 179 | begin 180 | if (~rst_n) 181 | arp_tx_end <= 1'b0 ; 182 | else if ((state == ARP_REQUEST && arp_send_cnt == 13 + 46 ) || (state == ARP_REPLY && arp_send_cnt == 13 + 46 )) 183 | arp_tx_end <= 1'b1 ; 184 | else 185 | arp_tx_end <= 1'b0 ; 186 | end 187 | 188 | 189 | //timeout counter 190 | always @(posedge clk or negedge rst_n) 191 | begin 192 | if (~rst_n) 193 | timeout <= 16'd0 ; 194 | else if (state == ARP_REQUEST_WAIT_1 || state == ARP_REPLY_WAIT_1) 195 | timeout <= timeout + 1'b1 ; 196 | else 197 | timeout <= 16'd0 ; 198 | end 199 | 200 | 201 | always @(posedge clk or negedge rst_n) 202 | begin 203 | if (~rst_n) 204 | arp_destination_ip_addr <= 32'd0 ; 205 | else if (state == ARP_REQUEST_WAIT_1) 206 | arp_destination_ip_addr <= destination_ip_addr ; 207 | else if (state == ARP_REPLY_WAIT_1) 208 | arp_destination_ip_addr <= arp_rec_source_ip_addr ; 209 | end 210 | 211 | always @(posedge clk or negedge rst_n) 212 | begin 213 | if (~rst_n) 214 | arp_destination_mac_addr <= 48'd0 ; 215 | else if (state == ARP_REQUEST_WAIT_1) 216 | arp_destination_mac_addr <= destination_mac_addr ; 217 | else if (state == ARP_REPLY_WAIT_1) 218 | arp_destination_mac_addr <= arp_rec_source_mac_addr ; 219 | end 220 | 221 | 222 | always @(posedge clk or negedge rst_n) 223 | begin 224 | if (~rst_n) 225 | arp_reply_ack <= 1'b0 ; 226 | else if (state == ARP_REPLY_WAIT_1) 227 | arp_reply_ack <= 1'b1 ; 228 | else 229 | arp_reply_ack <= 1'b0 ; 230 | end 231 | 232 | 233 | 234 | 235 | always @(posedge clk or negedge rst_n) 236 | begin 237 | if (~rst_n) 238 | arp_send_cnt <= 16'd0 ; 239 | else if (state == ARP_REQUEST || state == ARP_REPLY) 240 | arp_send_cnt <= arp_send_cnt + 1'b1 ; 241 | else 242 | arp_send_cnt <= 16'd0 ; 243 | end 244 | 245 | 246 | 247 | 248 | always @(posedge clk or negedge rst_n) 249 | begin 250 | if (~rst_n) 251 | arp_tx_data <= 8'd0 ; 252 | else if(state == ARP_REQUEST || state == ARP_REPLY) 253 | begin 254 | case(arp_send_cnt) 255 | 16'd0 : arp_tx_data <= arp_destination_mac_addr[47:40] ; 256 | 16'd1 : arp_tx_data <= arp_destination_mac_addr[39:32] ; 257 | 16'd2 : arp_tx_data <= arp_destination_mac_addr[31:24] ; 258 | 16'd3 : arp_tx_data <= arp_destination_mac_addr[23:16] ; 259 | 16'd4 : arp_tx_data <= arp_destination_mac_addr[15:8] ; 260 | 16'd5 : arp_tx_data <= arp_destination_mac_addr[7:0] ; 261 | 16'd6 : arp_tx_data <= source_mac_addr[47:40] ; 262 | 16'd7 : arp_tx_data <= source_mac_addr[39:32] ; 263 | 16'd8 : arp_tx_data <= source_mac_addr[31:24] ; 264 | 16'd9 : arp_tx_data <= source_mac_addr[23:16] ; 265 | 16'd10 : arp_tx_data <= source_mac_addr[15:8] ; 266 | 16'd11 : arp_tx_data <= source_mac_addr[7:0] ; 267 | 16'd12 : arp_tx_data <= mac_type[15:8] ; //frame type 268 | 16'd13 : arp_tx_data <= mac_type[7:0] ; 269 | 16'd14 : arp_tx_data <= hardware_type[15:8] ; //hardware type 270 | 16'd15 : arp_tx_data <= hardware_type[7:0] ; 271 | 16'd16 : arp_tx_data <= protocol_type[15:8] ; //protocol type using IP 0800 272 | 16'd17 : arp_tx_data <= protocol_type[7:0] ; 273 | 16'd18 : arp_tx_data <= mac_length ; //MAC address length 274 | 16'd19 : arp_tx_data <= ip_length ; //IP address length 275 | 16'd20 : arp_tx_data <= op[15:8] ; 276 | 16'd21 : arp_tx_data <= op[7:0] ; 277 | 16'd22 : arp_tx_data <= source_mac_addr[47:40] ; 278 | 16'd23 : arp_tx_data <= source_mac_addr[39:32] ; 279 | 16'd24 : arp_tx_data <= source_mac_addr[31:24] ; 280 | 16'd25 : arp_tx_data <= source_mac_addr[23:16] ; 281 | 16'd26 : arp_tx_data <= source_mac_addr[15:8] ; 282 | 16'd27 : arp_tx_data <= source_mac_addr[7:0] ; 283 | 16'd28 : arp_tx_data <= source_ip_addr[31:24] ; 284 | 16'd29 : arp_tx_data <= source_ip_addr[23:16] ; 285 | 16'd30 : arp_tx_data <= source_ip_addr[15:8] ; 286 | 16'd31 : arp_tx_data <= source_ip_addr[7:0] ; 287 | 16'd32 : arp_tx_data <= arp_destination_mac_addr[47:40] ; 288 | 16'd33 : arp_tx_data <= arp_destination_mac_addr[39:32] ; 289 | 16'd34 : arp_tx_data <= arp_destination_mac_addr[31:24] ; 290 | 16'd35 : arp_tx_data <= arp_destination_mac_addr[23:16] ; 291 | 16'd36 : arp_tx_data <= arp_destination_mac_addr[15:8] ; 292 | 16'd37 : arp_tx_data <= arp_destination_mac_addr[7:0] ; 293 | 16'd38 : arp_tx_data <= arp_destination_ip_addr[31:24] ; 294 | 16'd39 : arp_tx_data <= arp_destination_ip_addr[23:16] ; 295 | 16'd40 : arp_tx_data <= arp_destination_ip_addr[15:8] ; 296 | 16'd41 : arp_tx_data <= arp_destination_ip_addr[7:0] ; 297 | default : arp_tx_data <= 8'd0 ; 298 | endcase 299 | end 300 | else 301 | arp_tx_data <= 8'd0 ; 302 | end 303 | 304 | 305 | 306 | endmodule 307 | -------------------------------------------------------------------------------- /RTL/rtl_2/crc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module crc (Clk, Reset, Data_in, Enable, Crc,CrcNext); 3 | parameter Tp = 1; 4 | 5 | input Clk; 6 | input Reset; 7 | input [7:0] Data_in; 8 | input Enable; 9 | 10 | output [31:0] Crc; 11 | reg [31:0] Crc; 12 | 13 | output [31:0] CrcNext; 14 | 15 | wire [7:0] Data; 16 | 17 | assign Data={Data_in[0],Data_in[1],Data_in[2],Data_in[3],Data_in[4],Data_in[5],Data_in[6],Data_in[7]}; 18 | 19 | 20 | assign CrcNext[0] = Crc[24] ^ Crc[30] ^ Data[0] ^ Data[6]; 21 | assign CrcNext[1] = Crc[24] ^ Crc[25] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[6] ^ Data[7]; 22 | assign CrcNext[2] = Crc[24] ^ Crc[25] ^ Crc[26] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[2] ^ Data[6] ^ Data[7]; 23 | assign CrcNext[3] = Crc[25] ^ Crc[26] ^ Crc[27] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[3] ^ Data[7]; 24 | assign CrcNext[4] = Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[4] ^ Data[6]; 25 | assign CrcNext[5] = Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4] ^ Data[5] ^ Data[6] ^ Data[7]; 26 | assign CrcNext[6] = Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5] ^ Data[6] ^ Data[7]; 27 | assign CrcNext[7] = Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Crc[31] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[5] ^ Data[7]; 28 | assign CrcNext[8] = Crc[0] ^ Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4]; 29 | assign CrcNext[9] = Crc[1] ^ Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5]; 30 | assign CrcNext[10] = Crc[2] ^ Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[5]; 31 | assign CrcNext[11] = Crc[3] ^ Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4]; 32 | assign CrcNext[12] = Crc[4] ^ Crc[24] ^ Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Data[0] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5] ^ Data[6]; 33 | assign CrcNext[13] = Crc[5] ^ Crc[25] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[3] ^ Data[5] ^ Data[6] ^ Data[7]; 34 | assign CrcNext[14] = Crc[6] ^ Crc[26] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Crc[31] ^ Data[2] ^ Data[3] ^ Data[4] ^ Data[6] ^ Data[7]; 35 | assign CrcNext[15] = Crc[7] ^ Crc[27] ^ Crc[28] ^ Crc[29] ^ Crc[31] ^ Data[3] ^ Data[4] ^ Data[5] ^ Data[7]; 36 | assign CrcNext[16] = Crc[8] ^ Crc[24] ^ Crc[28] ^ Crc[29] ^ Data[0] ^ Data[4] ^ Data[5]; 37 | assign CrcNext[17] = Crc[9] ^ Crc[25] ^ Crc[29] ^ Crc[30] ^ Data[1] ^ Data[5] ^ Data[6]; 38 | assign CrcNext[18] = Crc[10] ^ Crc[26] ^ Crc[30] ^ Crc[31] ^ Data[2] ^ Data[6] ^ Data[7]; 39 | assign CrcNext[19] = Crc[11] ^ Crc[27] ^ Crc[31] ^ Data[3] ^ Data[7]; 40 | assign CrcNext[20] = Crc[12] ^ Crc[28] ^ Data[4]; 41 | assign CrcNext[21] = Crc[13] ^ Crc[29] ^ Data[5]; 42 | assign CrcNext[22] = Crc[14] ^ Crc[24] ^ Data[0]; 43 | assign CrcNext[23] = Crc[15] ^ Crc[24] ^ Crc[25] ^ Crc[30] ^ Data[0] ^ Data[1] ^ Data[6]; 44 | assign CrcNext[24] = Crc[16] ^ Crc[25] ^ Crc[26] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[7]; 45 | assign CrcNext[25] = Crc[17] ^ Crc[26] ^ Crc[27] ^ Data[2] ^ Data[3]; 46 | assign CrcNext[26] = Crc[18] ^ Crc[24] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Data[0] ^ Data[3] ^ Data[4] ^ Data[6]; 47 | assign CrcNext[27] = Crc[19] ^ Crc[25] ^ Crc[28] ^ Crc[29] ^ Crc[31] ^ Data[1] ^ Data[4] ^ Data[5] ^ Data[7]; 48 | assign CrcNext[28] = Crc[20] ^ Crc[26] ^ Crc[29] ^ Crc[30] ^ Data[2] ^ Data[5] ^ Data[6]; 49 | assign CrcNext[29] = Crc[21] ^ Crc[27] ^ Crc[30] ^ Crc[31] ^ Data[3] ^ Data[6] ^ Data[7]; 50 | assign CrcNext[30] = Crc[22] ^ Crc[28] ^ Crc[31] ^ Data[4] ^ Data[7]; 51 | assign CrcNext[31] = Crc[23] ^ Crc[29] ^ Data[5]; 52 | 53 | always @ (posedge Clk, posedge Reset) 54 | begin 55 | if (Reset) begin 56 | Crc <={32{1'b1}}; 57 | end 58 | else if (Enable) 59 | Crc <=CrcNext; 60 | end 61 | endmodule 62 | -------------------------------------------------------------------------------- /RTL/rtl_2/ethernet_character.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_2/ethernet_character.v -------------------------------------------------------------------------------- /RTL/rtl_2/ethernet_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_2/ethernet_test.v -------------------------------------------------------------------------------- /RTL/rtl_2/ip_rx.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////////// 2 | //Module Name : ip_rx 3 | //Description : This module is used to receive IP data and verify IP header checksum 4 | // 5 | ////////////////////////////////////////////////////////////////////////////////////// 6 | `timescale 1 ns/1 ns 7 | module ip_rx 8 | //# 9 | //( 10 | // parameter local_mac_addr = 48'h00_0a_35_01_fe_c0, 11 | // parameter local_ip_addr = 32'hc0a80002 12 | //) 13 | ( 14 | input clk, 15 | input rst_n, 16 | 17 | input [31:0] local_ip_addr, 18 | input [47:0] local_mac_addr, 19 | 20 | input [7:0] ip_rx_data, 21 | input ip_rx_req, 22 | input [47:0] mac_rx_destination_mac_addr, 23 | 24 | output reg udp_rx_req, //udp rx request 25 | output reg icmp_rx_req, //icmp rx request 26 | output reg ip_addr_check_error, //ip address is not equal to local address 27 | 28 | output reg [15:0] upper_layer_data_length, //udp or icmp data length = ip data length - ip header length 29 | output reg [15:0] ip_total_data_length, //send data length 30 | 31 | output reg [7:0] net_protocol, //network layer protocol: 8'h11 udp 8'h01 icmp 32 | output reg [31:0] ip_rec_source_addr, //received source ip address 33 | output reg [31:0] ip_rec_destination_addr, //received destination ip address 34 | 35 | output reg ip_rx_end, 36 | output reg ip_checksum_error 37 | 38 | ) ; 39 | 40 | reg [15:0] ip_rx_cnt ; 41 | reg [15:0] ip_rec_data_length ; 42 | 43 | reg [7:0] ip_rx_data_d0 ; 44 | reg [7:0] ip_rx_data_d1 ; 45 | 46 | reg [15:0] ip_rec_checksum ; 47 | 48 | reg [3:0] header_length_buf ; 49 | wire [5:0] header_length ; 50 | 51 | parameter IDLE = 5'b00001 ; 52 | parameter REC_HEADER0 = 5'b00010 ; 53 | parameter REC_HEADER1 = 5'b00100 ; 54 | parameter REC_DATA = 5'b01000 ; 55 | parameter REC_END = 5'b10000 ; 56 | 57 | reg [4:0] state ; 58 | reg [4:0] next_state ; 59 | 60 | always @(posedge clk or negedge rst_n) 61 | begin 62 | if (~rst_n) 63 | state <= IDLE ; 64 | else 65 | state <= next_state ; 66 | end 67 | 68 | always @(*) 69 | begin 70 | case(state) 71 | IDLE : begin 72 | if (ip_rx_req == 1'b1) 73 | next_state <= REC_HEADER0 ; 74 | else 75 | next_state <= IDLE ; 76 | end 77 | REC_HEADER0 : begin 78 | if (ip_rx_cnt == 16'd3) 79 | next_state <= REC_HEADER1 ; 80 | else 81 | next_state <= REC_HEADER0 ; 82 | end 83 | REC_HEADER1 : begin 84 | if (ip_rx_cnt == header_length - 1) 85 | next_state <= REC_DATA ; 86 | else 87 | next_state <= REC_HEADER1 ; 88 | end 89 | REC_DATA : begin 90 | if (ip_checksum_error || ip_rx_end) 91 | next_state <= REC_END ; 92 | else if (ip_rx_cnt == 16'hffff) 93 | next_state <= REC_END ; 94 | else 95 | next_state <= REC_DATA ; 96 | end 97 | REC_END : next_state <= IDLE ; 98 | default : next_state <= IDLE ; 99 | endcase 100 | end 101 | 102 | assign header_length = 4*header_length_buf ; 103 | 104 | always @(posedge clk or negedge rst_n) 105 | begin 106 | if (~rst_n) 107 | ip_rx_end <= 1'b0 ; 108 | else if (state == REC_DATA && ip_rx_cnt == ip_total_data_length - 2) 109 | ip_rx_end <= 1'b1 ; 110 | else 111 | ip_rx_end <= 1'b0 ; 112 | end 113 | //mac addr and ip addr is not equal to local addr, assert error 114 | always @(posedge clk or negedge rst_n) 115 | begin 116 | if (~rst_n) 117 | ip_addr_check_error <= 1'b0 ; 118 | else if (state == REC_DATA) 119 | begin 120 | if (mac_rx_destination_mac_addr == local_mac_addr && ip_rec_destination_addr == local_ip_addr) 121 | ip_addr_check_error <= 1'b0 ; 122 | else 123 | ip_addr_check_error <= 1'b1 ; 124 | end 125 | else 126 | ip_addr_check_error <= 1'b0 ; 127 | end 128 | //generate udp rx request signal 129 | always @(posedge clk or negedge rst_n) 130 | begin 131 | if (~rst_n) 132 | udp_rx_req <= 1'b0 ; 133 | else if (state == REC_HEADER1 && net_protocol == 8'h11 && ip_rx_cnt == header_length - 2) 134 | udp_rx_req <= 1'b1 ; 135 | else 136 | udp_rx_req <= 1'b0 ; 137 | end 138 | //generate icmp rx request signal 139 | always @(posedge clk or negedge rst_n) 140 | begin 141 | if (~rst_n) 142 | icmp_rx_req <= 1'b0 ; 143 | else if (state == REC_HEADER1 && net_protocol == 8'h01 && ip_rx_cnt == header_length - 2) 144 | icmp_rx_req <= 1'b1 ; 145 | else 146 | icmp_rx_req <= 1'b0 ; 147 | end 148 | 149 | 150 | //icmp or udp data length 151 | always @(posedge clk or negedge rst_n) 152 | begin 153 | if (~rst_n) 154 | begin 155 | upper_layer_data_length <= 16'd0 ; 156 | end 157 | else 158 | begin 159 | upper_layer_data_length <= ip_rec_data_length - header_length ; 160 | end 161 | end 162 | 163 | always @(posedge clk or negedge rst_n) 164 | begin 165 | if (~rst_n) 166 | begin 167 | ip_rx_data_d0 <= 8'd0 ; 168 | ip_rx_data_d1 <= 8'd0 ; 169 | end 170 | else 171 | begin 172 | ip_rx_data_d0 <= ip_rx_data ; 173 | ip_rx_data_d1 <= ip_rx_data_d0 ; 174 | end 175 | end 176 | 177 | always @(posedge clk or negedge rst_n) 178 | begin 179 | if (~rst_n) 180 | ip_rx_cnt <= 16'd0 ; 181 | else if (state == REC_HEADER0 || state == REC_HEADER1 || state == REC_DATA) 182 | ip_rx_cnt <= ip_rx_cnt + 1'b1 ; 183 | else 184 | ip_rx_cnt <= 16'd0 ; 185 | end 186 | //total length 187 | always @(posedge clk or negedge rst_n) 188 | begin 189 | if (~rst_n) 190 | ip_total_data_length <= 16'd0 ; 191 | else if (state == REC_HEADER1) 192 | begin 193 | if (ip_rec_data_length < 16'd46) 194 | ip_total_data_length <= 16'd46 ; 195 | else 196 | ip_total_data_length <= ip_rec_data_length ; 197 | end 198 | end 199 | 200 | 201 | //ip header length 202 | always @(posedge clk or negedge rst_n) 203 | begin 204 | if (~rst_n) 205 | header_length_buf <= 4'd0 ; 206 | else if (state == REC_HEADER0 && ip_rx_cnt == 16'd0) 207 | header_length_buf <= ip_rx_data[3:0] ; 208 | end 209 | //ip data total length 210 | always @(posedge clk or negedge rst_n) 211 | begin 212 | if (~rst_n) 213 | ip_rec_data_length <= 16'd0 ; 214 | else if (state == REC_HEADER0 && ip_rx_cnt == 16'd2) 215 | ip_rec_data_length[15:8] <= ip_rx_data ; 216 | else if (state == REC_HEADER0 && ip_rx_cnt == 16'd3) 217 | ip_rec_data_length[7:0] <= ip_rx_data ; 218 | end 219 | //network layer protocol 220 | always @(posedge clk or negedge rst_n) 221 | begin 222 | if (~rst_n) 223 | net_protocol <= 8'd0 ; 224 | else if (state == REC_HEADER1 && ip_rx_cnt == 16'd9) 225 | net_protocol <= ip_rx_data ; 226 | end 227 | 228 | //ip source address 229 | always @(posedge clk or negedge rst_n) 230 | begin 231 | if (~rst_n) 232 | ip_rec_source_addr <= 32'd0 ; 233 | else if (state == REC_HEADER1 && ip_rx_cnt == 16'd12) 234 | ip_rec_source_addr[31:24] <= ip_rx_data ; 235 | else if (state == REC_HEADER1 && ip_rx_cnt == 16'd13) 236 | ip_rec_source_addr[23:16] <= ip_rx_data ; 237 | else if (state == REC_HEADER1 && ip_rx_cnt == 16'd14) 238 | ip_rec_source_addr[15:8] <= ip_rx_data ; 239 | else if (state == REC_HEADER1 && ip_rx_cnt == 16'd15) 240 | ip_rec_source_addr[7:0] <= ip_rx_data ; 241 | end 242 | //ip source address 243 | always @(posedge clk or negedge rst_n) 244 | begin 245 | if (~rst_n) 246 | ip_rec_destination_addr <= 32'd0 ; 247 | else if (state == REC_HEADER1 && ip_rx_cnt == 16'd16) 248 | ip_rec_destination_addr[31:24] <= ip_rx_data ; 249 | else if (state == REC_HEADER1 && ip_rx_cnt == 16'd17) 250 | ip_rec_destination_addr[23:16] <= ip_rx_data ; 251 | else if (state == REC_HEADER1 && ip_rx_cnt == 16'd18) 252 | ip_rec_destination_addr[15:8] <= ip_rx_data ; 253 | else if (state == REC_HEADER1 && ip_rx_cnt == 16'd19) 254 | ip_rec_destination_addr[7:0] <= ip_rx_data ; 255 | end 256 | 257 | 258 | //****************************************************************// 259 | //verify checksum 260 | //****************************************************************// 261 | reg [31:0] checksum_tmp ; 262 | reg [31:0] checksum_buf ; 263 | reg [31:0] check_out ; 264 | reg [31:0] checkout_buf ; 265 | wire [15:0] checksum ; 266 | reg [2:0] checksum_cnt ; 267 | 268 | //checksum function 269 | function [31:0] checksum_adder 270 | ( 271 | input [31:0] dataina, 272 | input [31:0] datainb 273 | ); 274 | 275 | begin 276 | checksum_adder = dataina + datainb; 277 | end 278 | endfunction 279 | 280 | function [31:0] checksum_out 281 | ( 282 | input [31:0] dataina 283 | ); 284 | 285 | begin 286 | checksum_out = dataina[15:0]+dataina[31:16]; 287 | end 288 | 289 | endfunction 290 | 291 | always @(posedge clk or negedge rst_n) 292 | begin 293 | if (~rst_n) 294 | checksum_tmp <= 32'd0; 295 | else if (state == REC_HEADER0 || state == REC_HEADER1) 296 | begin 297 | if (ip_rx_cnt[0] == 1'b1) 298 | checksum_tmp <= checksum_adder({ip_rx_data_d0, ip_rx_data},checksum_buf); 299 | end 300 | else if (state == IDLE) 301 | checksum_tmp <= 32'd0; 302 | end 303 | 304 | always @(posedge clk or negedge rst_n) 305 | begin 306 | if (~rst_n) 307 | check_out <= 32'd0; 308 | else if (state == REC_DATA) 309 | check_out <= checksum_out(checksum_tmp) ; 310 | end 311 | 312 | always @(posedge clk or negedge rst_n) 313 | begin 314 | if(rst_n == 1'b0) 315 | checksum_cnt <= 3'd0 ; 316 | else if (state == REC_DATA) 317 | begin 318 | if (checksum_cnt == 3'd7) 319 | checksum_cnt <= checksum_cnt ; 320 | else 321 | checksum_cnt <= checksum_cnt + 1'b1 ; 322 | end 323 | else 324 | checksum_cnt <= 3'd0 ; 325 | end 326 | 327 | always @(posedge clk or negedge rst_n) 328 | begin 329 | if (~rst_n) 330 | checksum_buf <= 32'd0 ; 331 | else 332 | checksum_buf <= checksum_tmp ; 333 | end 334 | 335 | always @(posedge clk or negedge rst_n) 336 | begin 337 | if (~rst_n) 338 | checkout_buf <= 32'd0 ; 339 | else 340 | checkout_buf <= check_out ; 341 | end 342 | 343 | assign checksum = ~checkout_buf[15:0] ; 344 | 345 | always @(posedge clk or negedge rst_n) 346 | begin 347 | if (~rst_n) 348 | ip_checksum_error <= 1'b0 ; 349 | else if (state == REC_DATA && checksum_cnt == 3'd2) 350 | begin 351 | if (checksum == 16'd0) 352 | ip_checksum_error <= 1'b0 ; 353 | else 354 | ip_checksum_error <= 1'b1 ; 355 | end 356 | else 357 | ip_checksum_error <= 1'b0 ; 358 | end 359 | 360 | endmodule 361 | -------------------------------------------------------------------------------- /RTL/rtl_2/ip_tx_mode.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////////// 2 | //Module Name : ip_tx_mode 3 | //Description : This module is arbitration for ip layer signal, which from udp and icmp 4 | // 5 | ////////////////////////////////////////////////////////////////////////////////////// 6 | `timescale 1 ns/1 ns 7 | module ip_tx_mode 8 | ( 9 | input clk , 10 | input rst_n, 11 | input mac_send_end, 12 | 13 | 14 | input udp_tx_req, 15 | input udp_tx_ready , 16 | input [7:0] udp_tx_data, 17 | input [15:0] udp_send_data_length, 18 | output reg udp_tx_ack, 19 | 20 | input icmp_tx_req, 21 | input icmp_tx_ready, 22 | input [7:0] icmp_tx_data, 23 | input [15:0] icmp_send_data_length, 24 | output reg icmp_tx_ack, 25 | 26 | input ip_tx_ack, 27 | output reg ip_tx_req, 28 | output reg ip_tx_ready, 29 | output reg [7:0] ip_tx_data, 30 | output reg [7:0] ip_send_type, 31 | output reg [15:0] ip_send_data_length 32 | 33 | 34 | ); 35 | 36 | localparam ip_udp_type = 8'h11 ; 37 | localparam ip_icmp_type = 8'h01 ; 38 | 39 | reg [15:0] timeout ; 40 | 41 | parameter IDLE = 5'b00001 ; 42 | parameter UDP_WAIT = 5'b00010 ; 43 | parameter UDP = 5'b00100 ; 44 | parameter ICMP_WAIT = 5'b01000 ; 45 | parameter ICMP = 5'b10000 ; 46 | 47 | 48 | reg [4:0] state ; 49 | reg [4:0] next_state ; 50 | 51 | always @(posedge clk or negedge rst_n) 52 | begin 53 | if (~rst_n) 54 | state <= IDLE ; 55 | else 56 | state <= next_state ; 57 | end 58 | 59 | always @(*) 60 | begin 61 | case(state) 62 | IDLE : 63 | begin 64 | if (udp_tx_req) 65 | next_state <= UDP_WAIT ; 66 | else if (icmp_tx_req) 67 | next_state <= ICMP_WAIT ; 68 | else 69 | next_state <= IDLE ; 70 | end 71 | UDP_WAIT : 72 | begin 73 | if (ip_tx_ack) 74 | next_state <= UDP ; 75 | else 76 | next_state <= UDP_WAIT ; 77 | end 78 | UDP : 79 | begin 80 | if (mac_send_end) 81 | next_state <= IDLE ; 82 | else if (timeout == 16'hffff) 83 | next_state <= IDLE ; 84 | else 85 | next_state <= UDP ; 86 | end 87 | ICMP_WAIT : 88 | begin 89 | if (ip_tx_ack) 90 | next_state <= ICMP ; 91 | else 92 | next_state <= ICMP_WAIT ; 93 | end 94 | ICMP : 95 | begin 96 | if (mac_send_end) 97 | next_state <= IDLE ; 98 | else if (timeout == 16'hffff) 99 | next_state <= IDLE ; 100 | else 101 | next_state <= ICMP ; 102 | end 103 | default : 104 | next_state <= IDLE ; 105 | endcase 106 | end 107 | 108 | 109 | always @(posedge clk or negedge rst_n) 110 | begin 111 | if (~rst_n) 112 | timeout <= 16'd0 ; 113 | else if (state == UDP || state == ICMP) 114 | timeout <= timeout + 1'b1 ; 115 | else 116 | timeout <= 16'd0 ; 117 | end 118 | 119 | always @(posedge clk or negedge rst_n) 120 | begin 121 | if (~rst_n) 122 | ip_send_data_length <= 16'd0 ; 123 | else if (state == ICMP_WAIT || state == ICMP) 124 | ip_send_data_length <= icmp_send_data_length ; 125 | else 126 | ip_send_data_length <= udp_send_data_length + 28 ; 127 | end 128 | 129 | always @(posedge clk or negedge rst_n) 130 | begin 131 | if (~rst_n) 132 | ip_tx_req <= 1'b0 ; 133 | else if (state == UDP_WAIT || state == ICMP_WAIT) 134 | ip_tx_req <= 1'b1 ; 135 | else 136 | ip_tx_req <= 1'b0 ; 137 | end 138 | 139 | always @(posedge clk or negedge rst_n) 140 | begin 141 | if (~rst_n) 142 | udp_tx_ack <= 1'b0 ; 143 | else if (state == UDP) 144 | udp_tx_ack <= 1'b1 ; 145 | else 146 | udp_tx_ack <= 1'b0 ; 147 | end 148 | 149 | 150 | always @(posedge clk or negedge rst_n) 151 | begin 152 | if (~rst_n) 153 | icmp_tx_ack <= 1'b0 ; 154 | else if (state == ICMP) 155 | icmp_tx_ack <= 1'b1 ; 156 | else 157 | icmp_tx_ack <= 1'b0 ; 158 | end 159 | 160 | always @(posedge clk or negedge rst_n) 161 | begin 162 | if (~rst_n) 163 | begin 164 | ip_tx_ready <= 1'b0 ; 165 | ip_tx_data <= 8'h00 ; 166 | ip_send_type <= ip_udp_type ; 167 | end 168 | else if (state == UDP) 169 | begin 170 | ip_tx_ready <= udp_tx_ready ; 171 | ip_tx_data <= udp_tx_data ; 172 | ip_send_type <= ip_udp_type ; 173 | 174 | end 175 | else if (state == ICMP) 176 | begin 177 | ip_tx_ready <= icmp_tx_ready ; 178 | ip_tx_data <= icmp_tx_data ; 179 | ip_send_type <= ip_icmp_type ; 180 | 181 | end 182 | else 183 | begin 184 | ip_tx_ready <= 1'b0 ; 185 | ip_tx_data <= 8'h00 ; 186 | ip_send_type <= ip_udp_type ; 187 | end 188 | end 189 | 190 | 191 | 192 | endmodule 193 | 194 | 195 | -------------------------------------------------------------------------------- /RTL/rtl_2/mac_rx_top.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////////// 2 | //Module Name : mac_rx_top 3 | //Description : MAC RX Top 4 | // 5 | ////////////////////////////////////////////////////////////////////////////////////// 6 | `timescale 1 ns/1 ns 7 | module mac_rx_top 8 | ( 9 | input clk, 10 | input rst_n, 11 | input video_clk, 12 | input rx_dv, 13 | input [7:0] mac_rx_datain, 14 | 15 | input [31:0] local_ip_addr, 16 | input [47:0] local_mac_addr, 17 | 18 | input arp_reply_ack, 19 | output arp_reply_req, 20 | output [31:0] arp_rec_source_ip_addr, 21 | output [47:0] arp_rec_source_mac_addr, 22 | 23 | 24 | output [7:0] udp_rec_ram_rdata , 25 | input [10:0] udp_rec_ram_read_addr, 26 | output [15:0] udp_rec_data_length, 27 | output udp_rec_data_valid, 28 | 29 | output [7:0] mac_rx_dataout, 30 | output [15:0] upper_layer_data_length , 31 | output [15:0] ip_total_data_length, 32 | output icmp_rx_req, 33 | output icmp_rev_error, 34 | output wire [10:0] rec_length, 35 | output arp_found 36 | ) ; 37 | 38 | 39 | 40 | wire ip_rx_req ; 41 | wire udp_rx_req ; 42 | wire ip_rx_end ; 43 | 44 | wire arp_rx_req ; 45 | wire arp_rx_end ; 46 | 47 | wire [7:0] net_protocol ; 48 | wire [31:0] ip_rec_destination_addr ; 49 | wire [31:0] ip_rec_source_ip_addr ; 50 | 51 | wire ip_addr_check_error ; 52 | wire ip_checksum_error ; 53 | wire mac_rec_error ; 54 | 55 | wire [47:0] mac_rx_destination_mac_addr ; 56 | wire [47:0] mac_rx_source_mac_addr ; 57 | 58 | wire crcen ; 59 | wire crcre ; 60 | wire [7:0] crc_din ; 61 | wire [31:0] crc_result ; 62 | 63 | 64 | 65 | assign icmp_rev_error = (mac_rec_error | ip_checksum_error | ip_addr_check_error) ; 66 | 67 | 68 | crc c0 69 | ( 70 | .Clk (clk), 71 | .Reset (crcre), 72 | .Data_in (crc_din), 73 | .Enable (crcen), 74 | .Crc (crc_result), 75 | .CrcNext () 76 | ) ; 77 | 78 | mac_rx mac0 79 | ( 80 | .clk (clk) , 81 | .rst_n (rst_n) , 82 | 83 | .rx_dv (rx_dv ), 84 | .mac_rx_datain (mac_rx_datain ), 85 | 86 | .crc_result (crc_result ) , 87 | .crcen (crcen ), 88 | .crcre (crcre ), 89 | .crc_din (crc_din ), 90 | 91 | .checksum_err (ip_checksum_error ), 92 | 93 | .ip_rx_end (ip_rx_end ), 94 | .arp_rx_end (arp_rx_end), 95 | 96 | .ip_rx_req (ip_rx_req ), 97 | .arp_rx_req (arp_rx_req), 98 | 99 | .mac_rx_dataout (mac_rx_dataout ), 100 | .mac_rec_error (mac_rec_error), 101 | 102 | .mac_rx_destination_mac_addr (mac_rx_destination_mac_addr ), 103 | .mac_rx_source_mac_addr (mac_rx_source_mac_addr) 104 | ); 105 | 106 | 107 | ip_rx ip0 108 | ( 109 | .clk (clk), 110 | .rst_n (rst_n) , 111 | 112 | .local_ip_addr (local_ip_addr ), 113 | .local_mac_addr (local_mac_addr), 114 | 115 | .ip_rx_data (mac_rx_dataout) , 116 | .ip_rx_req (ip_rx_req) , 117 | .ip_rx_end (ip_rx_end) , 118 | .icmp_rx_req (icmp_rx_req ), 119 | 120 | .ip_addr_check_error (ip_addr_check_error), 121 | .mac_rx_destination_mac_addr (mac_rx_destination_mac_addr), 122 | 123 | .upper_layer_data_length (upper_layer_data_length ), 124 | .ip_total_data_length (ip_total_data_length ), 125 | 126 | .net_protocol (net_protocol), 127 | .ip_rec_source_addr (ip_rec_source_ip_addr), 128 | .ip_rec_destination_addr (ip_rec_destination_addr), 129 | .udp_rx_req (udp_rx_req), 130 | .ip_checksum_error (ip_checksum_error) 131 | 132 | ) ; 133 | 134 | 135 | udp_rx udp0 136 | ( 137 | .clk (clk) , 138 | .rst_n (rst_n) , 139 | .video_clk (video_clk), 140 | .udp_rx_data (mac_rx_dataout), 141 | .udp_rx_req (udp_rx_req), 142 | 143 | .mac_rec_error (mac_rec_error), 144 | 145 | .ip_addr_check_error (ip_addr_check_error), 146 | 147 | .net_protocol (net_protocol), 148 | .ip_rec_source_addr (ip_rec_source_ip_addr), 149 | .ip_rec_destination_addr (ip_rec_destination_addr), 150 | .ip_checksum_error (ip_checksum_error), 151 | 152 | .upper_layer_data_length (upper_layer_data_length ), 153 | 154 | .udp_rec_ram_rdata (udp_rec_ram_rdata), 155 | .udp_rec_ram_read_addr (udp_rec_ram_read_addr), 156 | .udp_rec_data_length (udp_rec_data_length ), 157 | .length (rec_length), 158 | .udp_rec_data_valid (udp_rec_data_valid) 159 | ); 160 | 161 | 162 | arp_rx arp0 163 | ( 164 | .clk (clk) , 165 | .rst_n (rst_n), 166 | 167 | .local_ip_addr (local_ip_addr ), 168 | .local_mac_addr (local_mac_addr), 169 | 170 | .arp_rx_data (mac_rx_dataout ), 171 | .arp_rx_req (arp_rx_req ), 172 | 173 | .arp_reply_ack (arp_reply_ack ), 174 | .arp_rx_end (arp_rx_end ), 175 | .arp_reply_req (arp_reply_req ), 176 | 177 | .arp_rec_source_ip_addr (arp_rec_source_ip_addr ), 178 | .arp_rec_source_mac_addr (arp_rec_source_mac_addr ), 179 | .arp_found (arp_found ) 180 | 181 | ) ; 182 | 183 | 184 | endmodule 185 | -------------------------------------------------------------------------------- /RTL/rtl_2/mac_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_2/mac_test.v -------------------------------------------------------------------------------- /RTL/rtl_2/mac_top.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////////// 2 | //Module Name : mac_top 3 | //Description : 4 | // 5 | ////////////////////////////////////////////////////////////////////////////////////// 6 | `timescale 1 ns/1 ns 7 | module mac_top 8 | ( 9 | input gmii_tx_clk , 10 | input gmii_rx_clk , 11 | input rst_n , 12 | input video_clk, 13 | input [47:0] source_mac_addr , //source mac address 14 | input [7:0] TTL, 15 | input [31:0] source_ip_addr, 16 | input [31:0] destination_ip_addr, 17 | input [15:0] udp_send_source_port, 18 | input [15:0] udp_send_destination_port, 19 | 20 | 21 | 22 | 23 | output almost_full, 24 | 25 | 26 | input arp_request_req, 27 | output mac_data_valid, 28 | output mac_send_end, 29 | output [7:0] mac_tx_data, 30 | 31 | input rx_dv, 32 | input [7:0] mac_rx_datain, 33 | output [7:0] udp_rec_ram_rdata , 34 | input [10:0] udp_rec_ram_read_addr, 35 | output [15:0] udp_rec_data_length, 36 | output udp_rec_data_valid, 37 | 38 | output arp_found, 39 | output mac_not_exist, 40 | // output al_full, 41 | output emp_sum, 42 | output checksum_wr, 43 | output wire[10:0] rec_length, 44 | output [4:0] use_rd 45 | 46 | ) ; 47 | 48 | 49 | wire arp_reply_ack ; 50 | wire arp_reply_req ; 51 | wire [31:0] arp_rec_source_ip_addr ; 52 | wire [47:0] arp_rec_source_mac_addr ; 53 | wire [47:0] destination_mac_addr ; 54 | 55 | wire [7:0] mac_rx_dataout ; 56 | wire [15:0] upper_layer_data_length ; 57 | wire icmp_rx_req ; 58 | wire icmp_rev_error ; 59 | wire upper_data_req ; 60 | wire icmp_tx_ready ; 61 | wire [7:0] icmp_tx_data ; 62 | wire icmp_tx_end ; 63 | wire icmp_tx_req ; 64 | wire icmp_tx_ack ; 65 | wire [15:0] icmp_send_data_length ; 66 | 67 | mac_tx_top mac_tx0 68 | ( 69 | .clk (gmii_tx_clk) , 70 | .rst_n (rst_n) , 71 | 72 | .destination_mac_addr (destination_mac_addr) , //destination mac address 73 | .source_mac_addr (source_mac_addr) , //source mac address 74 | .TTL (TTL), 75 | .source_ip_addr (source_ip_addr), 76 | .destination_ip_addr (destination_ip_addr), 77 | 78 | .udp_send_source_port (udp_send_source_port), 79 | .udp_send_destination_port (udp_send_destination_port), 80 | 81 | .arp_reply_ack (arp_reply_ack ), 82 | .arp_reply_req (arp_reply_req ), 83 | .arp_rec_source_ip_addr (arp_rec_source_ip_addr ), 84 | .arp_rec_source_mac_addr (arp_rec_source_mac_addr ), 85 | .arp_request_req (arp_request_req ), 86 | 87 | 88 | .almost_full (almost_full ), 89 | 90 | .upper_data_req (upper_data_req ), 91 | .icmp_tx_ready (icmp_tx_ready ), 92 | .icmp_tx_data (icmp_tx_data ), 93 | .icmp_tx_end (icmp_tx_end ), 94 | .icmp_tx_req (icmp_tx_req ), 95 | .icmp_tx_ack (icmp_tx_ack ), 96 | .icmp_send_data_length (icmp_send_data_length), 97 | 98 | .mac_data_valid (mac_data_valid), 99 | .mac_send_end (mac_send_end), 100 | .mac_tx_data (mac_tx_data), 101 | // .al_full (al_full), 102 | .emp_sum (emp_sum), 103 | .checksum_wr(checksum_wr), 104 | .use_rd (use_rd) 105 | ) ; 106 | 107 | 108 | 109 | 110 | 111 | 112 | mac_rx_top mac_rx0 113 | ( 114 | .clk (gmii_rx_clk) , 115 | .rst_n (rst_n) , 116 | .video_clk (video_clk), 117 | .rx_dv (rx_dv ), 118 | .mac_rx_datain (mac_rx_datain ), 119 | 120 | .local_ip_addr (source_ip_addr ), 121 | .local_mac_addr (source_mac_addr), 122 | .arp_reply_ack (arp_reply_ack ), 123 | .arp_reply_req (arp_reply_req ), 124 | .arp_rec_source_ip_addr (arp_rec_source_ip_addr ), 125 | .arp_rec_source_mac_addr (arp_rec_source_mac_addr ), 126 | 127 | .udp_rec_ram_rdata (udp_rec_ram_rdata), 128 | .udp_rec_ram_read_addr (udp_rec_ram_read_addr), 129 | .udp_rec_data_length (udp_rec_data_length ), 130 | .udp_rec_data_valid (udp_rec_data_valid), 131 | 132 | .mac_rx_dataout (mac_rx_dataout ), 133 | .upper_layer_data_length (upper_layer_data_length ), 134 | .ip_total_data_length (icmp_send_data_length), 135 | .icmp_rx_req (icmp_rx_req ), 136 | .icmp_rev_error (icmp_rev_error ), 137 | .rec_length (rec_length), 138 | .arp_found (arp_found ) 139 | ) ; 140 | 141 | 142 | icmp_reply icmp0 143 | ( 144 | .clk (gmii_rx_clk) , 145 | .rst_n (rst_n) , 146 | .mac_send_end (mac_send_end ), 147 | .icmp_rx_data (mac_rx_dataout ), 148 | .icmp_rx_req (icmp_rx_req ), 149 | .icmp_rev_error (icmp_rev_error ), 150 | 151 | .upper_layer_data_length (upper_layer_data_length ), 152 | 153 | .icmp_data_req (upper_data_req ), 154 | .icmp_tx_ready (icmp_tx_ready ), 155 | .icmp_tx_data (icmp_tx_data ), 156 | .icmp_tx_end (icmp_tx_end ), 157 | .ip_tx_ack (icmp_tx_ack ), 158 | .icmp_tx_req (icmp_tx_req ) 159 | 160 | 161 | ); 162 | 163 | 164 | arp_cache cache0 165 | ( 166 | .clk (gmii_tx_clk), 167 | .rst_n (rst_n), 168 | .arp_found (arp_found ), 169 | .arp_rec_source_ip_addr (arp_rec_source_ip_addr ), 170 | .arp_rec_source_mac_addr (arp_rec_source_mac_addr ), 171 | .destination_ip_addr (destination_ip_addr), 172 | .destination_mac_addr (destination_mac_addr) , 173 | .mac_not_exist (mac_not_exist ) 174 | ); 175 | endmodule 176 | 177 | -------------------------------------------------------------------------------- /RTL/rtl_2/mac_tx.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////////// 2 | //Module Name : mac_tx 3 | //Description : This module is MAC layer module, which receive data from ARP or IP module, 4 | // In this module, CRC checksum is generated 5 | // 6 | ////////////////////////////////////////////////////////////////////////////////////// 7 | `timescale 1 ns/1 ns 8 | module mac_tx 9 | ( 10 | input clk, 11 | input rst_n, 12 | 13 | input [31:0] crc_result , 14 | output reg crcen, 15 | output reg crcre, 16 | output reg [7:0] crc_din, 17 | 18 | input mac_tx_req, 19 | input [7:0] mac_frame_data, //data from ip or arp 20 | input mac_tx_ready, //ready from ip or arp 21 | input mac_tx_end, //end from ip or arp 22 | 23 | output reg mac_tx_ack, 24 | output reg [7:0] mac_tx_data, 25 | output reg mac_send_end, 26 | output reg mac_data_valid, 27 | output reg mac_data_req //request data from arp or ip 28 | 29 | ) ; 30 | 31 | 32 | reg [3:0] mac_tx_cnt ; 33 | reg [31:0] crc ; 34 | 35 | reg [7:0] mac_frame_data_dly ; 36 | reg mac_tx_end_dly ; 37 | reg [7:0] mac_tx_data_tmp ; 38 | reg mac_data_valid_tmp ; 39 | reg [15:0] timeout ; 40 | 41 | 42 | //MAC send FSM 43 | parameter SEND_IDLE = 6'b000_001 ; 44 | parameter SEND_START = 6'b000_010 ; 45 | parameter SEND_PREAMBLE = 6'b000_100 ; 46 | parameter SEND_DATA = 6'b001_000 ; 47 | parameter SEND_CRC = 6'b010_000 ; 48 | parameter SEND_END = 6'b100_000 ; 49 | 50 | reg [5:0] send_state ; 51 | reg [5:0] send_next_state ; 52 | 53 | always @(posedge clk or negedge rst_n) 54 | begin 55 | if (~rst_n) 56 | send_state <= SEND_START ; 57 | else 58 | send_state <= send_next_state ; 59 | end 60 | 61 | always @(*) 62 | begin 63 | case(send_state) 64 | SEND_IDLE : 65 | begin 66 | if (mac_tx_req) 67 | send_next_state <= SEND_START ; 68 | else 69 | send_next_state <= SEND_IDLE ; 70 | end 71 | SEND_START : 72 | begin 73 | if (mac_tx_ready) 74 | send_next_state <= SEND_PREAMBLE ; 75 | else 76 | send_next_state <= SEND_START ; 77 | end 78 | SEND_PREAMBLE : 79 | begin 80 | if (mac_tx_cnt == 7) 81 | send_next_state <= SEND_DATA ; 82 | else 83 | send_next_state <= SEND_PREAMBLE ; 84 | end 85 | SEND_DATA : 86 | begin 87 | if (mac_tx_end_dly) 88 | send_next_state <= SEND_CRC ; 89 | else if (timeout == 16'hffff) 90 | send_next_state <= SEND_END ; 91 | else 92 | send_next_state <= SEND_DATA ; 93 | end 94 | SEND_CRC : 95 | begin 96 | if (mac_tx_cnt == 4) 97 | send_next_state <= SEND_END ; 98 | else 99 | send_next_state <= SEND_CRC ; 100 | end 101 | SEND_END : 102 | send_next_state <= SEND_IDLE ; 103 | default : 104 | send_next_state <= SEND_IDLE ; 105 | endcase 106 | end 107 | 108 | always @(posedge clk or negedge rst_n) 109 | begin 110 | if (~rst_n) 111 | mac_tx_ack <= 1'b0 ; 112 | else if (send_state == SEND_START) 113 | mac_tx_ack <= 1'b1 ; 114 | else 115 | mac_tx_ack <= 1'b0 ; 116 | end 117 | 118 | always @(posedge clk or negedge rst_n) 119 | begin 120 | if (~rst_n) 121 | mac_send_end <= 1'b0 ; 122 | else if (send_state == SEND_END) 123 | mac_send_end <= 1'b1 ; 124 | else 125 | mac_send_end <= 1'b0 ; 126 | end 127 | 128 | always @(posedge clk or negedge rst_n) 129 | begin 130 | if (~rst_n) 131 | begin 132 | crcre <= 1'b1 ; 133 | crcen <= 1'b0 ; 134 | crc_din <= 8'd0 ; 135 | end 136 | else if (send_state == SEND_DATA || (send_state == SEND_PREAMBLE && mac_tx_cnt == 7)) 137 | begin 138 | crcre <= 1'b0 ; 139 | crcen <= 1'b1 ; 140 | crc_din <= mac_frame_data ; 141 | end 142 | else 143 | begin 144 | crcre <= 1'b1 ; 145 | crcen <= 1'b0 ; 146 | crc_din <= 8'd0 ; 147 | end 148 | end 149 | 150 | 151 | always @(posedge clk or negedge rst_n) 152 | begin 153 | if (~rst_n) 154 | mac_data_valid_tmp <= 1'b0 ; 155 | else if (send_state == SEND_PREAMBLE || send_state == SEND_DATA || (send_state == SEND_CRC && mac_tx_cnt < 4)) 156 | mac_data_valid_tmp <= 1'b1 ; 157 | else 158 | mac_data_valid_tmp <= 1'b0 ; 159 | end 160 | 161 | always @(posedge clk or negedge rst_n) 162 | begin 163 | if (~rst_n) 164 | mac_data_valid <= 1'b0 ; 165 | else 166 | mac_data_valid <= mac_data_valid_tmp ; 167 | end 168 | //request data from arp or ip 169 | always @(posedge clk or negedge rst_n) 170 | begin 171 | if (~rst_n) 172 | mac_data_req <= 1'b0 ; 173 | else if (send_state == SEND_PREAMBLE && mac_tx_cnt == 3) 174 | mac_data_req <= 1'b1 ; 175 | else 176 | mac_data_req <= 1'b0 ; 177 | end 178 | //timeout counter 179 | always @(posedge clk or negedge rst_n) 180 | begin 181 | if (~rst_n) 182 | timeout <= 16'd0 ; 183 | else if (send_state == SEND_DATA) 184 | timeout <= timeout + 1'b1 ; 185 | else 186 | timeout <= 16'd0 ; 187 | end 188 | 189 | 190 | always @(posedge clk or negedge rst_n) 191 | begin 192 | if (~rst_n) 193 | crc <= 32'hffffffff ; 194 | else if (crcen) 195 | crc <= crc_result ; 196 | end 197 | 198 | always @(posedge clk or negedge rst_n) 199 | begin 200 | if (~rst_n) 201 | begin 202 | mac_frame_data_dly <= 8'd0 ; 203 | mac_tx_end_dly <= 1'b0 ; 204 | end 205 | else 206 | begin 207 | mac_frame_data_dly <= mac_frame_data ; 208 | mac_tx_end_dly <= mac_tx_end ; 209 | end 210 | end 211 | 212 | always @(posedge clk or negedge rst_n) 213 | begin 214 | if (~rst_n) 215 | mac_tx_cnt <= 4'd0 ; 216 | else if (send_state == SEND_PREAMBLE || send_state == SEND_CRC) 217 | mac_tx_cnt <= mac_tx_cnt + 1'b1 ; 218 | else 219 | mac_tx_cnt <= 4'd0 ; 220 | end 221 | //mac send data frame 222 | always @(posedge clk or negedge rst_n) 223 | begin 224 | if (~rst_n) 225 | mac_tx_data_tmp <= 8'h00 ; 226 | else if (send_state == SEND_PREAMBLE) 227 | begin 228 | if (mac_tx_cnt < 7) 229 | mac_tx_data_tmp <= 8'h55 ; 230 | else 231 | mac_tx_data_tmp <= 8'hd5 ; 232 | end 233 | else if (send_state == SEND_DATA) 234 | mac_tx_data_tmp <= mac_frame_data_dly ; 235 | end 236 | 237 | always @(posedge clk or negedge rst_n) 238 | begin 239 | if (~rst_n) 240 | mac_tx_data <= 8'h00 ; 241 | else if (send_state == SEND_CRC) 242 | begin 243 | case(mac_tx_cnt) 244 | 4'd0 : mac_tx_data <= mac_tx_data_tmp ; 245 | 4'd1 : mac_tx_data <= {~crc[24], ~crc[25], ~crc[26], ~crc[27], ~crc[28], ~crc[29], ~crc[30], ~crc[31]} ; 246 | 4'd2 : mac_tx_data <= {~crc[16], ~crc[17], ~crc[18], ~crc[19], ~crc[20], ~crc[21], ~crc[22], ~crc[23]} ; 247 | 4'd3 : mac_tx_data <= {~crc[8], ~crc[9], ~crc[10], ~crc[11], ~crc[12], ~crc[13], ~crc[14], ~crc[15]} ; 248 | 4'd4 : mac_tx_data <= {~crc[0], ~crc[1], ~crc[2], ~crc[3], ~crc[4], ~crc[5], ~crc[6], ~crc[7]} ; 249 | default : mac_tx_data <= 8'h00 ; 250 | endcase 251 | end 252 | else 253 | mac_tx_data <= mac_tx_data_tmp ; 254 | end 255 | 256 | endmodule 257 | -------------------------------------------------------------------------------- /RTL/rtl_2/mac_tx_mode.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////////// 2 | //Module Name : mac_tx_mode 3 | //Description : This module is arbitration for MAC layer signal, which from IP and ARP 4 | // 5 | ////////////////////////////////////////////////////////////////////////////////////// 6 | `timescale 1 ns/1 ns 7 | module mac_tx_mode 8 | ( 9 | input clk , 10 | input rst_n, 11 | input mac_send_end, 12 | 13 | input arp_tx_req, 14 | input arp_tx_ready , 15 | input [7:0] arp_tx_data, 16 | input arp_tx_end, 17 | output reg arp_tx_ack, 18 | 19 | input ip_tx_req, 20 | input ip_tx_ready, 21 | input [7:0] ip_tx_data, 22 | input ip_tx_end, 23 | output reg ip_tx_ack, 24 | 25 | input mac_tx_ack, 26 | output reg mac_tx_req, 27 | output reg mac_tx_ready, 28 | output reg [7:0] mac_tx_data, 29 | output reg mac_tx_end 30 | ); 31 | 32 | 33 | 34 | reg [15:0] timeout ; 35 | 36 | parameter IDLE = 5'b00001 ; 37 | parameter ARP_WAIT = 5'b00010 ; 38 | parameter ARP = 5'b00100 ; 39 | parameter IP_WAIT = 5'b01000 ; 40 | parameter IP = 5'b10000 ; 41 | 42 | 43 | reg [4:0] state ; 44 | reg [4:0] next_state ; 45 | 46 | always @(posedge clk or negedge rst_n) 47 | begin 48 | if (~rst_n) 49 | state <= IDLE ; 50 | else 51 | state <= next_state ; 52 | end 53 | 54 | always @(*) 55 | begin 56 | case(state) 57 | IDLE : 58 | begin 59 | if (arp_tx_req) 60 | next_state <= ARP_WAIT ; 61 | else if (ip_tx_req) 62 | next_state <= IP_WAIT ; 63 | else 64 | next_state <= IDLE ; 65 | end 66 | ARP_WAIT : 67 | begin 68 | if (mac_tx_ack) 69 | next_state <= ARP ; 70 | else 71 | next_state <= IP ; 72 | end 73 | ARP : 74 | begin 75 | if (mac_send_end) 76 | next_state <= IDLE ; 77 | else if (timeout == 16'hffff) 78 | next_state <= IDLE ; 79 | else 80 | next_state <= ARP ; 81 | end 82 | IP_WAIT : 83 | begin 84 | if (mac_tx_ack) 85 | next_state <= IP ; 86 | else 87 | next_state <= IP_WAIT ; 88 | end 89 | IP : 90 | begin 91 | if (mac_send_end) 92 | next_state <= IDLE ; 93 | else if (timeout == 16'hffff) 94 | next_state <= IDLE ; 95 | else 96 | next_state <= IP ; 97 | end 98 | default : 99 | next_state <= IDLE ; 100 | endcase 101 | end 102 | 103 | 104 | always @(posedge clk or negedge rst_n) 105 | begin 106 | if (~rst_n) 107 | timeout <= 16'd0 ; 108 | else if (state == ARP || state == IP) 109 | timeout <= timeout + 1'b1 ; 110 | else 111 | timeout <= 16'd0 ; 112 | end 113 | 114 | always @(posedge clk or negedge rst_n) 115 | begin 116 | if (~rst_n) 117 | arp_tx_ack <= 1'b0 ; 118 | else if (state == ARP) 119 | arp_tx_ack <= 1'b1 ; 120 | else 121 | arp_tx_ack <= 1'b0 ; 122 | end 123 | 124 | always @(posedge clk or negedge rst_n) 125 | begin 126 | if (~rst_n) 127 | ip_tx_ack <= 1'b0 ; 128 | else if (state == IP) 129 | ip_tx_ack <= 1'b1 ; 130 | else 131 | ip_tx_ack <= 1'b0 ; 132 | end 133 | 134 | always @(posedge clk or negedge rst_n) 135 | begin 136 | if (~rst_n) 137 | mac_tx_req <= 1'b0 ; 138 | else if (state == ARP_WAIT || state == IP_WAIT) 139 | mac_tx_req <= 1'b1 ; 140 | else 141 | mac_tx_req <= 1'b0 ; 142 | end 143 | 144 | always @(posedge clk or negedge rst_n) 145 | begin 146 | if (~rst_n) 147 | begin 148 | mac_tx_ready <= 1'b0 ; 149 | mac_tx_data <= 8'h00 ; 150 | mac_tx_end <= 1'b0 ; 151 | end 152 | else if (state == ARP) 153 | begin 154 | mac_tx_ready <= arp_tx_ready ; 155 | mac_tx_data <= arp_tx_data ; 156 | mac_tx_end <= arp_tx_end ; 157 | end 158 | else if (state == IP) 159 | begin 160 | mac_tx_ready <= ip_tx_ready ; 161 | mac_tx_data <= ip_tx_data ; 162 | mac_tx_end <= ip_tx_end ; 163 | end 164 | else 165 | begin 166 | mac_tx_ready <= 1'b0 ; 167 | mac_tx_data <= 8'h00 ; 168 | mac_tx_end <= 1'b0 ; 169 | end 170 | end 171 | 172 | endmodule 173 | 174 | 175 | -------------------------------------------------------------------------------- /RTL/rtl_2/osd_display.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_2/osd_display.v -------------------------------------------------------------------------------- /RTL/rtl_2/timing_gen_xy.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // // 4 | // Author: meisq // 5 | // msq@qq.com // 6 | // ALINX(shanghai) Technology Co.,Ltd // 7 | // heijin // 8 | // WEB: http://www.alinx.cn/ // 9 | // BBS: http://www.heijin.org/ // 10 | // // 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | // // 13 | // Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd // 14 | // All rights reserved // 15 | // // 16 | // This source file may be used and distributed without restriction provided // 17 | // that this copyright statement is not removed from the file and that any // 18 | // derivative work contains the original copyright notice and the associated // 19 | // disclaimer. // 20 | // // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | //================================================================================ 24 | // Revision History: 25 | // Date By Revision Change Description 26 | //-------------------------------------------------------------------------------- 27 | // 2017/7/14 meisq 1.0 Original 28 | //********************************************************************************/ 29 | module timing_gen_xy( 30 | input rst_n, 31 | input clk, 32 | input i_hs, 33 | input i_vs, 34 | input i_de, 35 | input[23:0] i_data, 36 | output o_hs, 37 | output o_vs, 38 | output o_de, 39 | output[23:0] o_data, 40 | output[11:0] x, // video position X 41 | output[11:0] y // video position y 42 | ); 43 | reg de_d0; 44 | reg de_d1; 45 | reg de_d2; 46 | reg vs_d0; 47 | reg vs_d1; 48 | reg vs_d2; 49 | reg hs_d0; 50 | reg hs_d1; 51 | reg hs_d2; 52 | reg[23:0] i_data_d0; 53 | reg[23:0] i_data_d1; 54 | reg[23:0] i_data_d2; 55 | reg[11:0] x_cnt = 12'd0; 56 | reg[11:0] y_cnt = 12'd0; 57 | wire vs_edge; 58 | wire de_falling; 59 | /*assign vs_edge = vs_d0 & ~vs_d1; 60 | assign de_falling = ~de_d0 & de_d1; 61 | assign o_de = de_d1; 62 | assign o_vs = vs_d1; 63 | assign o_hs = hs_d1; 64 | assign o_data = i_data_d1;*/ 65 | assign vs_edge = vs_d0 & ~vs_d1; 66 | assign de_falling = ~de_d0 & de_d1; 67 | assign o_de = de_d1; 68 | assign o_vs = vs_d1; 69 | assign o_hs = hs_d1; 70 | assign o_data = i_data_d1; 71 | always@(posedge clk) 72 | begin 73 | de_d0 <= i_de; 74 | de_d1 <= de_d0; 75 | de_d2 <= de_d1; 76 | vs_d0 <= i_vs; 77 | vs_d1 <= vs_d0; 78 | vs_d2 <= vs_d1; 79 | hs_d0 <= i_hs; 80 | hs_d1 <= hs_d0; 81 | hs_d2 <= hs_d1; 82 | i_data_d0 <= i_data; 83 | i_data_d1 <= i_data_d0; 84 | i_data_d2 <= i_data_d1; 85 | end 86 | always@(posedge clk or negedge rst_n) 87 | begin 88 | if(rst_n == 1'b0) 89 | x_cnt <= 12'd0; 90 | else if(de_d0 == 1'b1) 91 | x_cnt <= x_cnt + 12'd1; 92 | else 93 | x_cnt <= 12'd0; 94 | end 95 | always@(posedge clk or negedge rst_n) 96 | begin 97 | if(rst_n == 1'b0) 98 | y_cnt <= 12'd0; 99 | else if(vs_edge == 1'b1) 100 | y_cnt <= 12'd0; 101 | else if(de_falling == 1'b1) 102 | y_cnt <= y_cnt + 12'd1; 103 | else 104 | y_cnt <= y_cnt; 105 | end 106 | assign x = x_cnt; 107 | assign y = y_cnt; 108 | endmodule -------------------------------------------------------------------------------- /RTL/rtl_2/udp_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/rtl_2/udp_rx.v -------------------------------------------------------------------------------- /RTL/rtl_3/coor_trans.v: -------------------------------------------------------------------------------- 1 | module coor_trans 2 | #( 3 | parameter IMAGE_W = 1024, 4 | parameter IMAGE_H = 768 5 | 6 | ) 7 | ( 8 | input clk, 9 | input rst_n, 10 | 11 | input signed [9:0] angle, 12 | input signed [31:0] x_in, 13 | input signed [31:0] y_in, 14 | 15 | 16 | output signed [31:0] x_out, 17 | output signed [31:0] y_out 18 | 19 | ); 20 | 21 | wire signed [31:0] x_wire; 22 | wire signed [31:0] y_wire; 23 | 24 | wire signed [31:0] x_rotate_temp; 25 | wire signed [31:0] y_rotate_temp; 26 | 27 | wire signed [31:0] x_rotate; 28 | wire signed [31:0] y_rotate; 29 | 30 | wire signed [9:0] sin_value; 31 | wire signed [9:0] cos_value; 32 | 33 | coor_trans_forward coor_trans_forward_inst 34 | ( 35 | .clk ( clk ), 36 | .rst_n ( rst_n ), 37 | .x_in ( x_in ) , // input [31:0] x_in 38 | .y_in ( y_in ) , // input [31:0] y_in 39 | .x_out ( x_wire ) , // output [31:0] x_out 40 | .y_out ( y_wire ) // output [31:0] y_out 41 | ); 42 | 43 | defparam coor_trans_forward_inst.IMAGE_W = IMAGE_W; 44 | defparam coor_trans_forward_inst.IMAGE_H = IMAGE_H; 45 | 46 | cos_table cos_table_inst 47 | ( 48 | .clk ( clk ), 49 | .rst_n ( rst_n ), 50 | .angle ( angle ) , // input [9:0] angle 51 | .cos_value ( cos_value ) // output [9:0] cos_value 52 | ); 53 | 54 | 55 | sin_table sin_table_inst 56 | ( 57 | .clk ( clk ), 58 | .rst_n ( rst_n ), 59 | 60 | .angle ( angle ) , // input [9:0] angle 61 | .sin_value ( sin_value ) // output [9:0] sin_value 62 | ); 63 | 64 | assign x_rotate_temp = ( x_wire <<< 8 ) * cos_value - ( y_wire <<< 8 ) * sin_value; 65 | assign y_rotate_temp = ( x_wire <<< 8 ) * sin_value + ( y_wire <<< 8 ) * cos_value; 66 | 67 | assign x_rotate = x_rotate_temp >>> 16; 68 | assign y_rotate = y_rotate_temp >>> 16; 69 | 70 | 71 | coor_trans_reverse coor_trans_reverse_inst 72 | ( 73 | .clk ( clk ), 74 | .rst_n ( rst_n ), 75 | 76 | .x_in ( x_rotate ) , // input [31:0] x_in 77 | .y_in ( y_rotate ) , // input [31:0] y_in 78 | .x_out ( x_out ) , // output [31:0] x_out 79 | .y_out ( y_out ) // output [31:0] y_out 80 | ); 81 | 82 | 83 | defparam coor_trans_reverse_inst.IMAGE_W = IMAGE_W; 84 | defparam coor_trans_reverse_inst.IMAGE_H = IMAGE_H; 85 | 86 | 87 | endmodule -------------------------------------------------------------------------------- /RTL/rtl_3/coor_trans_forward.v: -------------------------------------------------------------------------------- 1 | module coor_trans_forward 2 | #( 3 | parameter IMAGE_W = 1024, 4 | parameter IMAGE_H = 768 5 | 6 | ) 7 | ( 8 | input clk, 9 | input rst_n, 10 | 11 | input signed [31:0] x_in, 12 | input signed [31:0] y_in, 13 | 14 | output signed [31:0] x_out, 15 | output signed [31:0] y_out 16 | 17 | ); 18 | 19 | assign x_out = x_in - IMAGE_W/2; 20 | assign y_out = IMAGE_H/2 - y_in; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /RTL/rtl_3/coor_trans_reverse.v: -------------------------------------------------------------------------------- 1 | module coor_trans_reverse 2 | #( 3 | parameter IMAGE_W = 1024, 4 | parameter IMAGE_H = 768 5 | 6 | ) 7 | ( 8 | input clk, 9 | input rst_n, 10 | 11 | input signed [31:0] x_in, 12 | input signed [31:0] y_in, 13 | 14 | output signed [31:0] x_out, 15 | output signed [31:0] y_out 16 | 17 | ); 18 | 19 | 20 | assign x_out = x_in + IMAGE_W/2; 21 | assign y_out = IMAGE_H/2 - y_in; 22 | 23 | endmodule -------------------------------------------------------------------------------- /RTL/rtl_3/cos_table.v: -------------------------------------------------------------------------------- 1 | module cos_table 2 | ( 3 | input clk, 4 | input rst_n, 5 | 6 | input [9:0] angle, 7 | 8 | output reg signed [9:0] cos_value 9 | 10 | ); 11 | 12 | 13 | 14 | always@(*) 15 | begin 16 | case(angle) 17 | 0 : cos_value = 256 ; 18 | 1 : cos_value = 255 ; 19 | 2 : cos_value = 255 ; 20 | 3 : cos_value = 255 ; 21 | 4 : cos_value = 255 ; 22 | 5 : cos_value = 255 ; 23 | 6 : cos_value = 254 ; 24 | 7 : cos_value = 254 ; 25 | 8 : cos_value = 253 ; 26 | 9 : cos_value = 252 ; 27 | 10 : cos_value = 252 ; 28 | 11 : cos_value = 251 ; 29 | 12 : cos_value = 250 ; 30 | 13 : cos_value = 249 ; 31 | 14 : cos_value = 248 ; 32 | 15 : cos_value = 247 ; 33 | 16 : cos_value = 246 ; 34 | 17 : cos_value = 244 ; 35 | 18 : cos_value = 243 ; 36 | 19 : cos_value = 242 ; 37 | 20 : cos_value = 240 ; 38 | 21 : cos_value = 238 ; 39 | 22 : cos_value = 237 ; 40 | 23 : cos_value = 235 ; 41 | 24 : cos_value = 233 ; 42 | 25 : cos_value = 232 ; 43 | 26 : cos_value = 230 ; 44 | 27 : cos_value = 228 ; 45 | 28 : cos_value = 226 ; 46 | 29 : cos_value = 223 ; 47 | 30 : cos_value = 221 ; 48 | 31 : cos_value = 219 ; 49 | 32 : cos_value = 217 ; 50 | 33 : cos_value = 214 ; 51 | 34 : cos_value = 212 ; 52 | 35 : cos_value = 209 ; 53 | 36 : cos_value = 207 ; 54 | 37 : cos_value = 204 ; 55 | 38 : cos_value = 201 ; 56 | 39 : cos_value = 198 ; 57 | 40 : cos_value = 196 ; 58 | 41 : cos_value = 193 ; 59 | 42 : cos_value = 190 ; 60 | 43 : cos_value = 187 ; 61 | 44 : cos_value = 184 ; 62 | 45 : cos_value = 181 ; 63 | 46 : cos_value = 177 ; 64 | 47 : cos_value = 174 ; 65 | 48 : cos_value = 171 ; 66 | 49 : cos_value = 167 ; 67 | 50 : cos_value = 164 ; 68 | 51 : cos_value = 161 ; 69 | 52 : cos_value = 157 ; 70 | 53 : cos_value = 154 ; 71 | 54 : cos_value = 150 ; 72 | 55 : cos_value = 146 ; 73 | 56 : cos_value = 143 ; 74 | 57 : cos_value = 139 ; 75 | 58 : cos_value = 135 ; 76 | 59 : cos_value = 131 ; 77 | 60 : cos_value = 128 ; 78 | 61 : cos_value = 124 ; 79 | 62 : cos_value = 120 ; 80 | 63 : cos_value = 116 ; 81 | 64 : cos_value = 112 ; 82 | 65 : cos_value = 108 ; 83 | 66 : cos_value = 104 ; 84 | 67 : cos_value = 100 ; 85 | 68 : cos_value = 95 ; 86 | 69 : cos_value = 91 ; 87 | 70 : cos_value = 87 ; 88 | 71 : cos_value = 83 ; 89 | 72 : cos_value = 79 ; 90 | 73 : cos_value = 74 ; 91 | 74 : cos_value = 70 ; 92 | 75 : cos_value = 66 ; 93 | 76 : cos_value = 61 ; 94 | 77 : cos_value = 57 ; 95 | 78 : cos_value = 53 ; 96 | 79 : cos_value = 48 ; 97 | 80 : cos_value = 44 ; 98 | 81 : cos_value = 40 ; 99 | 82 : cos_value = 35 ; 100 | 83 : cos_value = 31 ; 101 | 84 : cos_value = 26 ; 102 | 85 : cos_value = 22 ; 103 | 86 : cos_value = 17 ; 104 | 87 : cos_value = 13 ; 105 | 88 : cos_value = 8 ; 106 | 89 : cos_value = 4 ; 107 | 90 : cos_value = 0 ; 108 | 91 : cos_value = -4 ; 109 | 92 : cos_value = -8 ; 110 | 93 : cos_value = -13 ; 111 | 94 : cos_value = -17 ; 112 | 95 : cos_value = -22 ; 113 | 96 : cos_value = -26 ; 114 | 97 : cos_value = -31 ; 115 | 98 : cos_value = -35 ; 116 | 99 : cos_value = -40 ; 117 | 100 : cos_value = -44 ; 118 | 101 : cos_value = -48 ; 119 | 102 : cos_value = -53 ; 120 | 103 : cos_value = -57 ; 121 | 104 : cos_value = -61 ; 122 | 105 : cos_value = -66 ; 123 | 106 : cos_value = -70 ; 124 | 107 : cos_value = -74 ; 125 | 108 : cos_value = -79 ; 126 | 109 : cos_value = -83 ; 127 | 110 : cos_value = -87 ; 128 | 111 : cos_value = -91 ; 129 | 112 : cos_value = -95 ; 130 | 113 : cos_value = -100 ; 131 | 114 : cos_value = -104 ; 132 | 115 : cos_value = -108 ; 133 | 116 : cos_value = -112 ; 134 | 117 : cos_value = -116 ; 135 | 118 : cos_value = -120 ; 136 | 119 : cos_value = -124 ; 137 | 120 : cos_value = -127 ; 138 | 121 : cos_value = -131 ; 139 | 122 : cos_value = -135 ; 140 | 123 : cos_value = -139 ; 141 | 124 : cos_value = -143 ; 142 | 125 : cos_value = -146 ; 143 | 126 : cos_value = -150 ; 144 | 127 : cos_value = -154 ; 145 | 128 : cos_value = -157 ; 146 | 129 : cos_value = -161 ; 147 | 130 : cos_value = -164 ; 148 | 131 : cos_value = -167 ; 149 | 132 : cos_value = -171 ; 150 | 133 : cos_value = -174 ; 151 | 134 : cos_value = -177 ; 152 | 135 : cos_value = -181 ; 153 | 136 : cos_value = -184 ; 154 | 137 : cos_value = -187 ; 155 | 138 : cos_value = -190 ; 156 | 139 : cos_value = -193 ; 157 | 140 : cos_value = -196 ; 158 | 141 : cos_value = -198 ; 159 | 142 : cos_value = -201 ; 160 | 143 : cos_value = -204 ; 161 | 144 : cos_value = -207 ; 162 | 145 : cos_value = -209 ; 163 | 146 : cos_value = -212 ; 164 | 147 : cos_value = -214 ; 165 | 148 : cos_value = -217 ; 166 | 149 : cos_value = -219 ; 167 | 150 : cos_value = -221 ; 168 | 151 : cos_value = -223 ; 169 | 152 : cos_value = -226 ; 170 | 153 : cos_value = -228 ; 171 | 154 : cos_value = -230 ; 172 | 155 : cos_value = -232 ; 173 | 156 : cos_value = -233 ; 174 | 157 : cos_value = -235 ; 175 | 158 : cos_value = -237 ; 176 | 159 : cos_value = -238 ; 177 | 160 : cos_value = -240 ; 178 | 161 : cos_value = -242 ; 179 | 162 : cos_value = -243 ; 180 | 163 : cos_value = -244 ; 181 | 164 : cos_value = -246 ; 182 | 165 : cos_value = -247 ; 183 | 166 : cos_value = -248 ; 184 | 167 : cos_value = -249 ; 185 | 168 : cos_value = -250 ; 186 | 169 : cos_value = -251 ; 187 | 170 : cos_value = -252 ; 188 | 171 : cos_value = -252 ; 189 | 172 : cos_value = -253 ; 190 | 173 : cos_value = -254 ; 191 | 174 : cos_value = -254 ; 192 | 175 : cos_value = -255 ; 193 | 176 : cos_value = -255 ; 194 | 177 : cos_value = -255 ; 195 | 178 : cos_value = -255 ; 196 | 179 : cos_value = -255 ; 197 | 180 : cos_value = -256 ; 198 | 181 : cos_value = -255 ; 199 | 182 : cos_value = -255 ; 200 | 183 : cos_value = -255 ; 201 | 184 : cos_value = -255 ; 202 | 185 : cos_value = -255 ; 203 | 186 : cos_value = -254 ; 204 | 187 : cos_value = -254 ; 205 | 188 : cos_value = -253 ; 206 | 189 : cos_value = -252 ; 207 | 190 : cos_value = -252 ; 208 | 191 : cos_value = -251 ; 209 | 192 : cos_value = -250 ; 210 | 193 : cos_value = -249 ; 211 | 194 : cos_value = -248 ; 212 | 195 : cos_value = -247 ; 213 | 196 : cos_value = -246 ; 214 | 197 : cos_value = -244 ; 215 | 198 : cos_value = -243 ; 216 | 199 : cos_value = -242 ; 217 | 200 : cos_value = -240 ; 218 | 201 : cos_value = -238 ; 219 | 202 : cos_value = -237 ; 220 | 203 : cos_value = -235 ; 221 | 204 : cos_value = -233 ; 222 | 205 : cos_value = -232 ; 223 | 206 : cos_value = -230 ; 224 | 207 : cos_value = -228 ; 225 | 208 : cos_value = -226 ; 226 | 209 : cos_value = -223 ; 227 | 210 : cos_value = -221 ; 228 | 211 : cos_value = -219 ; 229 | 212 : cos_value = -217 ; 230 | 213 : cos_value = -214 ; 231 | 214 : cos_value = -212 ; 232 | 215 : cos_value = -209 ; 233 | 216 : cos_value = -207 ; 234 | 217 : cos_value = -204 ; 235 | 218 : cos_value = -201 ; 236 | 219 : cos_value = -198 ; 237 | 220 : cos_value = -196 ; 238 | 221 : cos_value = -193 ; 239 | 222 : cos_value = -190 ; 240 | 223 : cos_value = -187 ; 241 | 224 : cos_value = -184 ; 242 | 225 : cos_value = -181 ; 243 | 226 : cos_value = -177 ; 244 | 227 : cos_value = -174 ; 245 | 228 : cos_value = -171 ; 246 | 229 : cos_value = -167 ; 247 | 230 : cos_value = -164 ; 248 | 231 : cos_value = -161 ; 249 | 232 : cos_value = -157 ; 250 | 233 : cos_value = -154 ; 251 | 234 : cos_value = -150 ; 252 | 235 : cos_value = -146 ; 253 | 236 : cos_value = -143 ; 254 | 237 : cos_value = -139 ; 255 | 238 : cos_value = -135 ; 256 | 239 : cos_value = -131 ; 257 | 240 : cos_value = -127 ; 258 | 241 : cos_value = -124 ; 259 | 242 : cos_value = -120 ; 260 | 243 : cos_value = -116 ; 261 | 244 : cos_value = -112 ; 262 | 245 : cos_value = -108 ; 263 | 246 : cos_value = -104 ; 264 | 247 : cos_value = -100 ; 265 | 248 : cos_value = -95 ; 266 | 249 : cos_value = -91 ; 267 | 250 : cos_value = -87 ; 268 | 251 : cos_value = -83 ; 269 | 252 : cos_value = -79 ; 270 | 253 : cos_value = -74 ; 271 | 254 : cos_value = -70 ; 272 | 255 : cos_value = -66 ; 273 | 256 : cos_value = -61 ; 274 | 257 : cos_value = -57 ; 275 | 258 : cos_value = -53 ; 276 | 259 : cos_value = -48 ; 277 | 260 : cos_value = -44 ; 278 | 261 : cos_value = -40 ; 279 | 262 : cos_value = -35 ; 280 | 263 : cos_value = -31 ; 281 | 264 : cos_value = -26 ; 282 | 265 : cos_value = -22 ; 283 | 266 : cos_value = -17 ; 284 | 267 : cos_value = -13 ; 285 | 268 : cos_value = -8 ; 286 | 269 : cos_value = -4 ; 287 | 270 : cos_value = 0 ; 288 | 271 : cos_value = 4 ; 289 | 272 : cos_value = 8 ; 290 | 273 : cos_value = 13 ; 291 | 274 : cos_value = 17 ; 292 | 275 : cos_value = 22 ; 293 | 276 : cos_value = 26 ; 294 | 277 : cos_value = 31 ; 295 | 278 : cos_value = 35 ; 296 | 279 : cos_value = 40 ; 297 | 280 : cos_value = 44 ; 298 | 281 : cos_value = 48 ; 299 | 282 : cos_value = 53 ; 300 | 283 : cos_value = 57 ; 301 | 284 : cos_value = 61 ; 302 | 285 : cos_value = 66 ; 303 | 286 : cos_value = 70 ; 304 | 287 : cos_value = 74 ; 305 | 288 : cos_value = 79 ; 306 | 289 : cos_value = 83 ; 307 | 290 : cos_value = 87 ; 308 | 291 : cos_value = 91 ; 309 | 292 : cos_value = 95 ; 310 | 293 : cos_value = 100 ; 311 | 294 : cos_value = 104 ; 312 | 295 : cos_value = 108 ; 313 | 296 : cos_value = 112 ; 314 | 297 : cos_value = 116 ; 315 | 298 : cos_value = 120 ; 316 | 299 : cos_value = 124 ; 317 | 300 : cos_value = 128 ; 318 | 301 : cos_value = 131 ; 319 | 302 : cos_value = 135 ; 320 | 303 : cos_value = 139 ; 321 | 304 : cos_value = 143 ; 322 | 305 : cos_value = 146 ; 323 | 306 : cos_value = 150 ; 324 | 307 : cos_value = 154 ; 325 | 308 : cos_value = 157 ; 326 | 309 : cos_value = 161 ; 327 | 310 : cos_value = 164 ; 328 | 311 : cos_value = 167 ; 329 | 312 : cos_value = 171 ; 330 | 313 : cos_value = 174 ; 331 | 314 : cos_value = 177 ; 332 | 315 : cos_value = 181 ; 333 | 316 : cos_value = 184 ; 334 | 317 : cos_value = 187 ; 335 | 318 : cos_value = 190 ; 336 | 319 : cos_value = 193 ; 337 | 320 : cos_value = 196 ; 338 | 321 : cos_value = 198 ; 339 | 322 : cos_value = 201 ; 340 | 323 : cos_value = 204 ; 341 | 324 : cos_value = 207 ; 342 | 325 : cos_value = 209 ; 343 | 326 : cos_value = 212 ; 344 | 327 : cos_value = 214 ; 345 | 328 : cos_value = 217 ; 346 | 329 : cos_value = 219 ; 347 | 330 : cos_value = 221 ; 348 | 331 : cos_value = 223 ; 349 | 332 : cos_value = 226 ; 350 | 333 : cos_value = 228 ; 351 | 334 : cos_value = 230 ; 352 | 335 : cos_value = 232 ; 353 | 336 : cos_value = 233 ; 354 | 337 : cos_value = 235 ; 355 | 338 : cos_value = 237 ; 356 | 339 : cos_value = 238 ; 357 | 340 : cos_value = 240 ; 358 | 341 : cos_value = 242 ; 359 | 342 : cos_value = 243 ; 360 | 343 : cos_value = 244 ; 361 | 344 : cos_value = 246 ; 362 | 345 : cos_value = 247 ; 363 | 346 : cos_value = 248 ; 364 | 347 : cos_value = 249 ; 365 | 348 : cos_value = 250 ; 366 | 349 : cos_value = 251 ; 367 | 350 : cos_value = 252 ; 368 | 351 : cos_value = 252 ; 369 | 352 : cos_value = 253 ; 370 | 353 : cos_value = 254 ; 371 | 354 : cos_value = 254 ; 372 | 355 : cos_value = 255 ; 373 | 356 : cos_value = 255 ; 374 | 357 : cos_value = 255 ; 375 | 358 : cos_value = 255 ; 376 | 359 : cos_value = 255 ; 377 | default :cos_value = 256 ; 378 | endcase 379 | end 380 | 381 | endmodule 382 | 383 | -------------------------------------------------------------------------------- /RTL/testbench/axi_interconnect_rd_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module axi_interconnect_rd_tb (); 3 | 4 | 5 | reg clk; 6 | reg rst; 7 | 8 | reg axi_wr_buf_wait; 9 | reg [1:0] channel_sel ; 10 | reg axi_arready ; 11 | 12 | reg axi_rvalid ; 13 | reg axi_rlast ; 14 | 15 | 16 | reg hdmi_vsync ; 17 | reg hdmi_href ; 18 | 19 | integer i; 20 | integer j; 21 | 22 | initial begin 23 | clk <= 1'b1; 24 | rst <= 1'b0; 25 | axi_wr_buf_wait <= 1'b0; 26 | channel_sel <= 2'b00; 27 | axi_arready <= 1'b0; 28 | axi_rvalid <= 1'b0; 29 | axi_rlast <= 1'b0; 30 | hdmi_vsync <= 1'b0; 31 | hdmi_href <= 1'b0; 32 | 33 | #20; 34 | rst <=1'b1; 35 | #20; 36 | hdmi_vsync <= 1'b1; 37 | #(20*50); 38 | hdmi_vsync <= 1'b0; 39 | #40; 40 | 41 | for (i=1;i<5;i=i+1)begin 42 | task1(); 43 | end 44 | 45 | #(20*50); 46 | 47 | for (j=1;j<183;j=j+1) begin 48 | hdmi_href <= 1'b1; 49 | #(20*1280); 50 | hdmi_href <= 1'b0; 51 | for (i=1;i<5;i=i+1)begin 52 | task1(); 53 | end 54 | #1000; 55 | end 56 | end 57 | 58 | 59 | 60 | always #10 clk =~clk; 61 | //initial begin 62 | // #40; 63 | // for (i=1;i<1580;i=i+1)begin 64 | // task1(); 65 | // end 66 | // axi_arready <= 1'b1; 67 | // #20; 68 | // axi_wr_buf_wait <= 1'b1; 69 | // channel_sel <= 2'b10; 70 | // axi_arready <= 1'b0; 71 | // axi_rvalid <= 1'b1; 72 | // #(19*20); 73 | // axi_rlast <= 1'b1; 74 | // #20; 75 | // axi_rvalid <= 1'b0; 76 | // axi_rlast <= 1'b0; 77 | // #60; 78 | // 79 | // for (i=1;i<5000;i=i+1)begin 80 | // task1(); 81 | // end 82 | // axi_wr_buf_wait <= 1'b0; 83 | // channel_sel <= 2'b01; 84 | // for (i=1;i<100;i=i+1)begin 85 | // task1(); 86 | // end 87 | // 88 | //end 89 | 90 | task task1(); 91 | begin 92 | #60; 93 | axi_arready <= 1'b1; 94 | #20; 95 | axi_arready <= 1'b0; 96 | axi_rvalid <= 1'b1; 97 | #(19*20); 98 | axi_rlast <= 1'b1; 99 | #20; 100 | axi_rvalid <= 1'b0; 101 | axi_rlast <= 1'b0; 102 | 103 | end 104 | endtask 105 | 106 | axi_interconnect_rd axi_interconnect_rd_inst( 107 | .clk (clk), 108 | .rst (rst), 109 | .axi_wr_buf_wait (axi_wr_buf_wait), 110 | .channel_sel (channel_sel), 111 | .axi_arready (axi_arready), 112 | .axi_rvalid (axi_rvalid), 113 | .axi_rlast (axi_rlast), 114 | .hdmi_vsync (hdmi_vsync), 115 | .hdmi_href (hdmi_href) 116 | 117 | ); 118 | endmodule -------------------------------------------------------------------------------- /RTL/testbench/axi_interconnect_wr_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module axi_interconnect_wr_tb ( 3 | 4 | ); 5 | 6 | reg clk; 7 | reg rst; 8 | reg channel1_rready; 9 | reg [255:0] channel1_data; 10 | reg frame_end_flag_1; 11 | 12 | reg channel2_rready; 13 | reg [255:0] channel2_data; 14 | reg frame_end_flag_2; 15 | 16 | reg channel3_rready; 17 | reg [255:0] channel3_data; 18 | reg frame_end_flag_3; 19 | 20 | reg channel4_rready; 21 | reg [255:0] channel4_data; 22 | reg frame_end_flag_4; 23 | 24 | reg channel5_rready; 25 | reg [255:0] channel5_data; 26 | reg frame_end_flag_5; 27 | 28 | reg axi_awready; 29 | reg axi_wlast; 30 | reg axi_wready; 31 | 32 | initial begin 33 | clk = 1'b1; 34 | rst <= 1'b0; 35 | axi_wlast <= 1'b0; 36 | channel1_rready <= 1'b0; 37 | channel2_rready <= 1'b0; 38 | channel3_rready <= 1'b0; 39 | channel4_rready <= 1'b0; 40 | channel5_rready <= 1'b0; 41 | axi_awready <= 1'b0; 42 | axi_wready <= 1'b0; 43 | frame_end_flag_1<= 1'b0; 44 | frame_end_flag_2<= 1'b0; 45 | frame_end_flag_3<= 1'b0; 46 | frame_end_flag_4<= 1'b0; 47 | frame_end_flag_5<= 1'b0; 48 | #20 49 | rst <= 1'b1; 50 | #20 51 | channel1_rready <=1'b1; //当buff区够一次突发读写时，channel1_rready拉高，这里模拟拉高，等待一拍axi_awvalid拉高，等待axi_awready空闲回应（握手） 52 | #40 53 | axi_awready <=1'b1; //模拟axi_awready回应（写地址握手成功），这时，等待一拍axi_wr_en拉高，再等待一拍axi_wvalid拉高（写数据请求），等待axi_wready空闲回应 54 | #100 55 | axi_wready <=1'b1; //模拟axi_wready回应（握手成功），等待一拍开始数据长度计数burst_len_count（通过burst_len_count计数信号，生成buff区读取地址，读取buff区的数据），同时生成axi_awaddr的首地址 56 | #(16*20) 57 | axi_wlast <=1'b1; //模拟axi接收到最后一个数据，拉高一个时钟周期，此时，状态机跳转到ch2_wait,一个通道储存完毕 58 | #20 59 | axi_wlast <=1'b0; 60 | 61 | 62 | #(200) 63 | channel2_rready <=1'b1; 64 | #40 65 | axi_awready <=1'b1; 66 | #100 67 | axi_wready <=1'b1; 68 | #(16*20) 69 | axi_wlast <=1'b1; 70 | #20 71 | axi_wlast <=1'b0; 72 | 73 | #(200) 74 | channel3_rready <=1'b1; 75 | #40 76 | axi_awready <=1'b1; 77 | #100 78 | axi_wready <=1'b1; 79 | #(16*20) 80 | axi_wlast <=1'b1; 81 | #20 82 | axi_wlast <=1'b0; 83 | 84 | #(200) 85 | channel4_rready <=1'b1; 86 | #40 87 | axi_awready <=1'b1; 88 | #100 89 | axi_wready <=1'b1; 90 | #(16*20) 91 | axi_wlast <=1'b1; 92 | #20 93 | axi_wlast <=1'b0; 94 | 95 | #(200) 96 | channel5_rready <=1'b1; 97 | #40 98 | axi_awready <=1'b1; 99 | #100 100 | axi_wready <=1'b1; 101 | #(16*20) 102 | axi_wlast <=1'b1; 103 | #20 104 | axi_wlast <=1'b0; 105 | #200 106 | channel1_rready <=1'b1; 107 | #40 108 | axi_awready <=1'b1; 109 | #100 110 | axi_wready <=1'b1; 111 | #(16*20) 112 | axi_wlast <=1'b1; 113 | #20 114 | axi_wlast <=1'b0; 115 | end 116 | 117 | always #10 clk = ~clk; 118 | axi_interconnect_wr axi_interconnect_wr_inst( 119 | .clk(clk), 120 | .rst(rst), 121 | .channel1_rready(channel1_rready), 122 | .frame_end_flag_1(frame_end_flag_1), 123 | .channel2_rready(channel2_rready), 124 | .frame_end_flag_2(frame_end_flag_2), 125 | .channel3_rready(channel3_rready), 126 | .frame_end_flag_3(frame_end_flag_3), 127 | .channel4_rready(channel4_rready), 128 | .frame_end_flag_4(frame_end_flag_4), 129 | .channel5_rready(channel5_rready), 130 | .frame_end_flag_5(frame_end_flag_5), 131 | .axi_awready(axi_awready), 132 | .axi_wlast(axi_wlast), 133 | .axi_wready(axi_wready) 134 | 135 | ); 136 | reg grs_n; 137 | GTP_GRS GRS_INST( 138 | .GRS_N (grs_n) 139 | ); 140 | endmodule -------------------------------------------------------------------------------- /RTL/testbench/test_hdmi_data_in.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MongooseOrion/Multi_Channel_Image_Splicing/a14339d83a263a837db7e5e1269d75a02d8172e0/RTL/testbench/test_hdmi_data_in.v -------------------------------------------------------------------------------- /RTL/testbench/video_sampling_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module video_sampling_tb (); 3 | 4 | reg clk; 5 | reg rd_clk; 6 | reg rst; 7 | reg de_in; 8 | reg vs_in; 9 | reg rd_valid; 10 | reg [15:0] rgb565_in; 11 | 12 | parameter RED = 16'hF800, //红色 13 | ORANGE = 16'hFC00, //橙色 14 | YELLOW = 16'hFFE0, //黄色 15 | GREEN = 16'h07E0; //绿色 四色彩带 16 | 17 | initial begin 18 | clk <= 1'b1; 19 | rd_clk <= 1'b1; 20 | rst <= 1'b0; 21 | vs_in <= 1'b0; 22 | de_in <= 1'b0; 23 | rd_valid <=1'b0; 24 | rgb565_in <= 16'd0; 25 | #28 26 | rst <= 1'b1; 27 | rd_valid <=1'b1; 28 | vs_in <= 1'b1; 29 | #(14*20); 30 | vs_in <= 1'b0; 31 | end 32 | integer i; 33 | integer j; 34 | 35 | initial begin 36 | for (i = 1; i <= 720; i = i + 1) begin 37 | row_task(); 38 | end 39 | end 40 | 41 | always #10 clk = ~clk; // 50m 42 | always #7 rd_clk = ~rd_clk; // 大约74.25 43 | 44 | // 定义发送一行图像数据的任务 45 | task row_task(); 46 | begin 47 | #(14*200); 48 | de_in <= 1'b1; 49 | for(j=0;j<1280;j=j+1) begin 50 | rgb565_in <= rgb565_in+16'b1; 51 | #(14); 52 | if(j==1040)begin 53 | rd_valid <=1'b0; 54 | end 55 | else if(j==1050)begin 56 | rd_valid <=1'b1; 57 | end 58 | end 59 | rgb565_in <= 16'd0; 60 | de_in <= 1'b0; 61 | 62 | // rgb565_in = RED; 63 | // #(1280*14*0.25); 64 | // rgb565_in = ORANGE; 65 | // #(1280*14*0.25); 66 | // rgb565_in = YELLOW; 67 | // #(1280*14*0.25); 68 | // rgb565_in = GREEN; 69 | // #(1280*14*0.25); 70 | // de_in = 1'b0; 71 | // #(14*50); 72 | end 73 | endtask 74 | reg grs_n; 75 | GTP_GRS GRS_INST( 76 | .GRS_N (grs_n) 77 | ); 78 | 79 | video_sampling video_sampling_inst( 80 | .clk(rd_clk), 81 | .rd_clk(clk), 82 | .rst(rst), 83 | .de_in(de_in), 84 | .vs_in(vs_in), 85 | .rgb565_in(rgb565_in), 86 | .rd_valid(rd_valid) 87 | ); 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /RTL/uart_rx.v: -------------------------------------------------------------------------------- 1 | /* ======================================================================= 2 | * Copyright (c) 2023, MongooseOrion. 3 | * All rights reserved. 4 | * 5 | * The following code snippet may contain portions that are derived from 6 | * OPEN-SOURCE communities, and these portions will be licensed with: 7 | * 8 | * 9 | * 10 | * If there is no OPEN-SOURCE licenses are listed, it indicates none of 11 | * content in this Code document is sourced from OPEN-SOURCE communities. 12 | * 13 | * In this case, the document is protected by copyright, and any use of 14 | * all or part of its content by individuals, organizations, or companies 15 | * without authorization is prohibited, unless the project repository 16 | * associated with this document has added relevant OPEN-SOURCE licenses 17 | * by github.com/MongooseOrion. 18 | * 19 | * Please make sure using the content of this document in accordance with 20 | * the respective OPEN-SOURCE licenses. 21 | * 22 | * THIS CODE IS PROVIDED BY https://github.com/MongooseOrion. 23 | * ======================================================================== 24 | */ 25 | // 26 | // uart 接收模块，电脑 to 板上 27 | 28 | module uart_rx#( 29 | parameter CLK_FEQ = 26'd50_000_000, 30 | parameter UART_BOT = 15'd9600 31 | )( 32 | input clk, 33 | input rst, 34 | input uart_rx, 35 | output reg [7:0] data_out, 36 | output reg data_out_flag 37 | ); 38 | 39 | reg rx_reg1; 40 | reg rx_reg2; 41 | reg rx_reg3; 42 | reg start_nedge; 43 | reg work_en; 44 | reg [15:0] baud_cnt; 45 | reg bit_flag; 46 | reg [3:0] bit_cnt; 47 | reg [7:0] rx_data; 48 | reg rx_flag; 49 | 50 | localparam BIT_CNT_MAX = CLK_FEQ / UART_BOT; 51 | 52 | 53 | // 延迟 3 个时钟周期 54 | always @(posedge clk or negedge rst) begin 55 | if(!rst) begin 56 | rx_reg1 <= 1'b1; 57 | rx_reg2 <= 1'b1; 58 | rx_reg3 <= 1'b1; 59 | end 60 | else begin 61 | rx_reg1 <= uart_rx; 62 | rx_reg2 <= rx_reg1; 63 | rx_reg3 <= rx_reg2; 64 | end 65 | end 66 | 67 | 68 | // 下降沿检测 69 | always @(posedge clk or negedge rst) begin 70 | if(!rst) begin 71 | start_nedge <= 1'b0; 72 | end 73 | else if((~rx_reg2) && (rx_reg3)) begin 74 | start_nedge <= 1'b1; 75 | end 76 | else begin 77 | start_nedge <= 1'b0; 78 | end 79 | end 80 | 81 | 82 | // 数据传输使能 83 | always @(posedge clk or negedge rst) begin 84 | if(!rst) begin 85 | work_en <= 1'b0; 86 | end 87 | else if(start_nedge) begin 88 | work_en <= 1'b1; 89 | end 90 | else if((bit_flag == 1'b1) && (bit_cnt == 4'd8)) begin 91 | work_en <= 1'b0; 92 | end 93 | else begin 94 | work_en <= work_en; 95 | end 96 | end 97 | 98 | 99 | // 波特率设定 100 | always @(posedge clk or negedge rst) begin 101 | if(!rst) begin 102 | baud_cnt <= 13'd0; 103 | end 104 | else if((baud_cnt == BIT_CNT_MAX - 1'b1) || (work_en == 1'b0)) begin 105 | baud_cnt <= 13'd0; 106 | end 107 | else begin 108 | baud_cnt <= baud_cnt + 1'b1; 109 | end 110 | end 111 | 112 | 113 | // 读取数据标志信号 114 | always @(posedge clk or negedge rst) begin 115 | if(!rst) begin 116 | bit_flag <= 1'b0; 117 | end 118 | else if(baud_cnt == BIT_CNT_MAX/2 - 1'b1) begin 119 | bit_flag <= 1'b1; 120 | end 121 | else begin 122 | bit_flag <= 1'b0; 123 | end 124 | end 125 | 126 | 127 | // 读取数据位数计数 128 | always @(posedge clk or negedge rst) begin 129 | if(!rst) begin 130 | bit_cnt <= 4'b0; 131 | end 132 | else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) begin 133 | bit_cnt <= 4'b0; 134 | end 135 | else if(bit_flag) begin 136 | bit_cnt <= bit_cnt + 1'b1; 137 | end 138 | else begin 139 | bit_cnt <= bit_cnt; 140 | end 141 | end 142 | 143 | 144 | // 串行接收数据 145 | always @(posedge clk or negedge rst) begin 146 | if(!rst) begin 147 | rx_data <= 8'd0; 148 | end 149 | else if((bit_flag == 1'b1) && (bit_cnt > 4'd0)) begin 150 | rx_data <= {rx_reg3, rx_data[7:1]}; 151 | end 152 | else begin 153 | rx_data <= rx_data; 154 | end 155 | end 156 | 157 | 158 | // 数据接收完成标志信号 159 | always @(posedge clk or negedge rst) begin 160 | if(!rst) begin 161 | rx_flag <= 1'b0; 162 | end 163 | else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) begin 164 | rx_flag <= 1'b1; 165 | end 166 | else begin 167 | rx_flag <= 1'b0; 168 | end 169 | end 170 | 171 | 172 | // 保存数据 173 | always @(posedge clk or negedge rst) begin 174 | if(!rst) begin 175 | data_out <= 8'd0; 176 | end 177 | else if(rx_flag) begin 178 | data_out <= rx_data; 179 | end 180 | else begin 181 | data_out <= data_out; 182 | end 183 | end 184 | 185 | 186 | // 输出有效标志信号 187 | always @(posedge clk or negedge rst) begin 188 | if(!rst) begin 189 | data_out_flag <= 1'b0; 190 | end 191 | else begin 192 | data_out_flag <= rx_flag; 193 | end 194 | end 195 | 196 | endmodule -------------------------------------------------------------------------------- /RTL/uart_trans.v: -------------------------------------------------------------------------------- 1 | /* ======================================================================= 2 | * Copyright (c) 2023, MongooseOrion. 3 | * All rights reserved. 4 | * 5 | * The following code snippet may contain portions that are derived from 6 | * OPEN-SOURCE communities, and these portions will be licensed with: 7 | * 8 | * 9 | * 10 | * If there is no OPEN-SOURCE licenses are listed, it indicates none of 11 | * content in this Code document is sourced from OPEN-SOURCE communities. 12 | * 13 | * In this case, the document is protected by copyright, and any use of 14 | * all or part of its content by individuals, organizations, or companies 15 | * without authorization is prohibited, unless the project repository 16 | * associated with this document has added relevant OPEN-SOURCE licenses 17 | * by github.com/MongooseOrion. 18 | * 19 | * Please make sure using the content of this document in accordance with 20 | * the respective OPEN-SOURCE licenses. 21 | * 22 | * THIS CODE IS PROVIDED BY https://github.com/MongooseOrion. 23 | * FILE ENCODER TYPE: UTF-8 24 | * ======================================================================== 25 | */ 26 | // UART 指令控制模块 27 | // 28 | module uart_trans( 29 | input clk, 30 | input rst, 31 | input uart_rx, 32 | input [7:0] command_in, 33 | input command_in_flag, 34 | output uart_tx, 35 | output [3:0] ctrl_command_out/*synthesis PAP_MARK_DEBUG="1"*/, 36 | output [3:0] value_command_out/*synthesis PAP_MARK_DEBUG="1"*/, 37 | output reg command_out_flag/*synthesis PAP_MARK_DEBUG="1"*/ 38 | ); 39 | 40 | wire data_out_flag; 41 | wire [7:0] command_out; 42 | 43 | reg [3:0] reg_ctrl_command; 44 | reg [3:0] reg_value_command; 45 | 46 | assign ctrl_command_out = reg_ctrl_command; 47 | assign value_command_out = reg_value_command; 48 | 49 | 50 | // 从电脑接收控制信号 51 | uart_rx command_recv( 52 | .clk (clk), 53 | .rst (rst), 54 | .data_out (command_out), 55 | .data_out_flag (data_out_flag), 56 | .uart_rx (uart_rx) 57 | ); 58 | 59 | // 延迟一个周期 60 | always @(posedge clk or negedge rst) begin 61 | if(!rst) begin 62 | command_out_flag <= 'b0; 63 | end 64 | else begin 65 | command_out_flag <= data_out_flag; 66 | end 67 | end 68 | 69 | 70 | // 控制信号只有效一个时钟周期 71 | always @(posedge clk or negedge rst) begin 72 | if(!rst) begin 73 | reg_ctrl_command <= 'b0; 74 | reg_value_command <= 'b0; 75 | end 76 | else if(data_out_flag) begin 77 | reg_ctrl_command <= command_out[7:4]; 78 | reg_value_command <= command_out[3:0]; 79 | end 80 | else begin 81 | reg_ctrl_command <= reg_ctrl_command; 82 | reg_value_command <= 4'b0; 83 | end 84 | end 85 | 86 | 87 | // 板上反馈信息 88 | uart_tx command_deliver( 89 | .clk (clk), 90 | .rst (rst), 91 | .data_in (command_in), 92 | .data_in_flag (command_in_flag), 93 | .uart_tx (uart_tx) 94 | ); 95 | 96 | 97 | endmodule -------------------------------------------------------------------------------- /RTL/uart_tx.v: -------------------------------------------------------------------------------- 1 | /* ======================================================================= 2 | * Copyright (c) 2023, MongooseOrion. 3 | * All rights reserved. 4 | * 5 | * The following code snippet may contain portions that are derived from 6 | * OPEN-SOURCE communities, and these portions will be licensed with: 7 | * 8 | * 9 | * 10 | * If there is no OPEN-SOURCE licenses are listed, it indicates none of 11 | * content in this Code document is sourced from OPEN-SOURCE communities. 12 | * 13 | * In this case, the document is protected by copyright, and any use of 14 | * all or part of its content by individuals, organizations, or companies 15 | * without authorization is prohibited, unless the project repository 16 | * associated with this document has added relevant OPEN-SOURCE licenses 17 | * by github.com/MongooseOrion. 18 | * 19 | * Please make sure using the content of this document in accordance with 20 | * the respective OPEN-SOURCE licenses. 21 | * 22 | * THIS CODE IS PROVIDED BY https://github.com/MongooseOrion. 23 | * FILE ENCODER TYPE: UTF-8 24 | * ======================================================================== 25 | */ 26 | // uart uart_tx 模块 27 | // 28 | module uart_tx#( 29 | parameter CLK_FEQ = 26'd50_000_000, 30 | parameter UART_BOT = 15'd9600 31 | )( 32 | input clk, 33 | input rst, 34 | input [7:0] data_in, 35 | input data_in_flag, 36 | output reg uart_tx 37 | ); 38 | 39 | localparam BIT_CNT_MAX = CLK_FEQ / UART_BOT; 40 | 41 | reg work_en; 42 | reg [15:0] baud_cnt; 43 | reg [3:0] bit_cnt; 44 | 45 | 46 | // 发送使能 47 | always @(posedge clk or negedge rst) begin 48 | if(!rst) begin 49 | work_en <= 1'b0; 50 | end 51 | else if(data_in_flag) begin 52 | work_en <= 1'b1; 53 | end 54 | else if((bit_cnt == 4'd9) && (baud_cnt == BIT_CNT_MAX/2 - 1'b1)) begin 55 | work_en <= 1'b0; 56 | end 57 | end 58 | 59 | 60 | // 发送周期（波特率9600） 61 | always @(posedge clk or negedge rst) begin 62 | if(!rst) begin 63 | baud_cnt <= 16'd0; 64 | end 65 | else if((work_en==1'b0) || (baud_cnt==BIT_CNT_MAX - 1'b1)) begin 66 | baud_cnt <= 16'd0; 67 | end 68 | else if(work_en) begin 69 | baud_cnt <= baud_cnt + 1'b1; 70 | end 71 | else begin 72 | baud_cnt <= baud_cnt; 73 | end 74 | end 75 | 76 | 77 | // 发送数据位置计数 78 | always @(posedge clk or negedge rst) begin 79 | if(!rst) begin 80 | bit_cnt <= 4'b0; 81 | end 82 | else if((bit_cnt==4'd9) && (baud_cnt==BIT_CNT_MAX/2 - 1'b1)) begin 83 | bit_cnt <= 4'b0; 84 | end 85 | else if(baud_cnt==BIT_CNT_MAX/2 - 1'b1) begin 86 | bit_cnt <= bit_cnt+1'b1; 87 | end 88 | else begin 89 | bit_cnt <= bit_cnt; 90 | end 91 | end 92 | 93 | 94 | always @(posedge clk or negedge rst) begin 95 | if(!rst) 96 | uart_tx <= 1'b1; 97 | else if(bit_cnt==4'b1) 98 | uart_tx <= 1'b0; 99 | else if(bit_cnt==4'd2) 100 | uart_tx <= data_in[0]; 101 | else if(bit_cnt==4'd3) 102 | uart_tx <= data_in[1]; 103 | else if(bit_cnt==4'd4) 104 | uart_tx <= data_in[2]; 105 | else if(bit_cnt==4'd5) 106 | uart_tx <= data_in[3]; 107 | else if(bit_cnt==4'd6) 108 | uart_tx <= data_in[4]; 109 | else if(bit_cnt==4'd7) 110 | uart_tx <= data_in[5]; 111 | else if(bit_cnt==4'd8) 112 | uart_tx <= data_in[6]; 113 | else if(bit_cnt==4'd9) 114 | uart_tx <= data_in[7]; 115 | else 116 | uart_tx <= 1'b1; 117 | end 118 | 119 | 120 | endmodule 121 | -------------------------------------------------------------------------------- /RTL/video_fusion.v: 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/Software/auto_test.py: -------------------------------------------------------------------------------- 1 | import serial 2 | import time 3 | import socket 4 | import codecs 5 | import binascii 6 | 7 | def send_data(serial_port, data): 8 | try: 9 | # 打开串口 10 | ser = serial.Serial(serial_port, baudrate=9600, timeout=1) 11 | 12 | # 将数据转换为十六进制格式 13 | hex_data = format(data, '02x') 14 | 15 | # 发送数据 16 | ser.write(bytearray.fromhex(hex_data)) 17 | 18 | # 关闭串口 19 | ser.close() 20 | 21 | print(f"成功发送数据: {hex_data}") 22 | except Exception as e: 23 | print(f"发送数据时出错: {str(e)}") 24 | 25 | # 设置串口号 26 | serial_port = 'COM19' 27 | udp_host = '192.168.0.2' 28 | udp_port = 8080 29 | 30 | input_value = [0xF1,0xF2,0xf3,0xf4,0x2a,0x29,0x28,0x27,0x26,0x24,0x23,0x22,0x21, 31 | 0x20,0x31,0x30,0x41,0x42,0x40,0x61,0x60,0x77,0x77,0x70, 32 | 0x7f,0x7f,0x7f,0x70,0x87,0x87,0x87,0x80] 33 | 34 | with open('../FPGA/ethernet_character_1.txt', 'r', encoding = 'UTF-8') as ecfile: 35 | hex_string = ecfile.read().strip() 36 | 37 | # 创建UDP套接字 38 | udp_socket = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) 39 | 40 | #formatted_string = ''.join(['\\x{}'.format(hex_string[i:i+2]) for i in range(0, len(hex_string), 2)]) 41 | #byte_data = bytearray.fromhex(''.join(hex_string.split())) 42 | 43 | byte_data = bytearray.fromhex(hex_string) 44 | print(' '.join(hex(b) for b in byte_data)) 45 | 46 | udp_socket.sendto(byte_data, (udp_host, udp_port)) 47 | udp_socket.close() 48 | print(f"成功发送UDP数据") 49 | 50 | 51 | # 设置要发送的8位数据 52 | for i in range(32): 53 | data_to_send = input_value[i] 54 | send_data(serial_port, data_to_send) 55 | time.sleep(3) 56 | -------------------------------------------------------------------------------- /readme.md: -------------------------------------------------------------------------------- 1 | # 基于 FPGA 的多路视频拼接系统 2 | 3 | 此项目用于将多路视频源拼合输出为一路视频源，其中 3 路为照相机源，1 路为 HDMI 源。同时还具备图像旋转和缩放功能，以下是关键功能参数表： 4 | 5 | | 受支持的类别 | 值 | 6 | | :--- | :--- | 7 | | 照相机输入分辨率 | $1280\times 720$ | 8 | | HDMI 输入分辨率 | $1280\times 720$ | 9 | | 照相机输入帧率 | 30 | 10 | | HDMI输入帧率 | 60 | 11 | | 输入通道数 | 4 | 12 | | 显示通道数 | 5 | 13 | | 双路视频融合 | 两路照相机视频源融合，输出画面为第 3 路视频源 | 14 | | 支持的缩放倍率 | 0.25，0.5~0.75 步长为 0.015（对于输入分辨率而言） | 15 | | 支持的旋转角度 | $0^\circ$, ${180}^\circ$ | 16 | | 支持的翻转模式 | 水平、垂直 | 17 | | 支持的图像处理操作 | 亮度调整、色相调整、灰阶显示 | 18 | | HDMI输出分辨率 | $1280\times 720$ | 19 | | 支持的HDMI输出帧率 | 30, 60 | 20 | | 串口控制 | 8 位 | 21 | | 字符显示 | 固化字符/网络传输 | 22 | 23 | 24 | 开发平台： 25 | * 紫光同创 PGL50H-6FBG484，DDR 拥有 32bit 输入位宽，仅支持通过一组 AXI 接口输入； 26 | 27 | ## 仓库目录 28 | 29 | ``` 30 | |-- Document // 存放项目文档 31 | |-- FPGA // 存放工程文件，例如比特流文件和 ROM 数据 32 | |-- bitstream_backup 33 | |-- RTL // Verilog 代码 34 | |-- Software // Python 代码 35 | ``` 36 | 37 | ## 硬件设计 38 | 39 | ### 系统总体结构 40 | 41 | 下图显示了该系统的结构拓扑图： 42 | 43 |
44 | 45 | 该系统可输入 3 路摄像头信号，1 路 HDMI 信号，通过分别缩放为输出视频画面的 $\frac{1}{16}$ 大小，排布在画面的上部。另外，在下部由电脑传入串口数据来控制显示的视频通道，此内容会被缩放为输出视频画面的 $\frac{9}{16}$ ，图像缩放和旋转操作均仅在此处生效。而输出视频画面剩余的 $\frac{6}{16}$ 画面空间，将会显示预设字符串。如果你对 AXI 总线比较了解，也可以尝试增加更多的输入源，由于在设计时已经将关键图像参数全部参数化，使得接入更多图像源成为可能。 46 | 47 | 详细的输出视频画面分布可见下图： 48 |
49 | 50 | ### 图像数据写入 DDR 逻辑 51 | 52 | 由于该芯片只提供 1 个 DDR AXI 接口，因此所有读写操作必须经过仲裁，保证在同一时间只有一路信号占用 AXI 总线通道。 53 | 54 | 对于写缓冲器的设计，采用的是 BRAM FIFO，当存入的数据量满足一次突发写所需的数据量时，拉高数据准备好信号。以下是伪代码逻辑： 55 | 56 | ```verilog 57 | `define INPUT CMOS_1 58 | 59 | fifo_wr u_fifo_wr( 60 | .wr_en (wr_en ), 61 | .wr_data (wr_data ), // [15:0] 62 | .almost_full (data_ready ), 63 | .rd_en (rd_valid ), 64 | .rd_data (axi_wdata ) // [255:0] 65 | ); 66 | 67 | assign wr_en = frame_href; 68 | assign wr_data = rgb565; // [15:0] 69 | 70 | parameter almost_full_number = 255 * axi_awlen; 71 | ``` 72 | 73 | AXI 时分复用利用状态机实现，当任一缓冲存储模块的 `data_ready` 信号为高，则开始占用 AXI 总线突发传输一次，然后跳转到下一路视频传输。 74 | 75 | 关于地址，已为每路视频开辟 2 帧的存储空间，以便于进行图像处理。在每路视频传输时，地址会赋值基地址初值，当一帧存满时，同样赋值另一个基地址值。基地址设置可见下述伪代码： 76 | ```verilog 77 | // 地址偏移量 78 | parameter FRAME_ADDR_OFFSET_1 = 'd30_000; 79 | parameter FRAME_ADDR_OFFSET_2 = 'd260_000; 80 | parameter ADDR_OFFSET_1 = 'd0, 81 | ADDR_OFFSET_2 = FRAME_ADDR_OFFSET_1 * 2, 82 | ADDR_OFFSET_3 = ADDR_OFFSET_2 + 2 * (FRAME_ADDR_OFFSET_1), 83 | ADDR_OFFSET_4 = ADDR_OFFSET_3 + 2 * (FRAME_ADDR_OFFSET_1), 84 | ADDR_OFFSET_5 = ADDR_OFFSET_4 + 2 * (FRAME_ADDR_OFFSET_1); 85 | parameter ADDR_STEP = BURST_LEN * 8; // 首地址自增步长，1 个地址 32 位数据，这与芯片的 DQ 宽度有关 86 | ``` 87 | 88 | ### 图像数据从 DDR 读取逻辑 89 | 90 | 对于写入 DDR 的逻辑，必须采用 “传输一次则握手 `awvalid && arready` 一次” 的机制，这是因为每次只对一路视频传输一个突发长度的数据，因此必须依赖握手机制和 `wlast` 信号对数据的 “钳制” 作用。 91 | 92 | 然而对于读取来说，对一路视频地址空间的读取可以不局限在一个突发长度的数据传输中，而可以多读取几个突发长度，因此可以一直拉高 `arvalid` 信号，等待某一通道完成传输后再拉低，也即采用 AXI outstanding 机制。 93 | 94 | 不同于写入的逻辑，读取的逻辑必须是按照实际输出画面的先后通道，动态地调整所需要读取的地址空间，只有这样才能保证重新生成的 HDMI 时序所需要使用的像素数据是按照实际的显示顺序排布的。读取逻辑伪代码如下述所示： 95 | 96 | ```verilog 97 | case(buf_rd_state) 98 | CH_1: begin 99 | if(pixel_count == VIDEO_WIDTH / 4) begin 100 | buf_rd_state <= CH_2; 101 | end 102 | else begin 103 | buf_rd_state <= buf_rd_state; 104 | end 105 | end 106 | CH_2: begin 107 | if(pixel_count == VIDEO_WIDTH / 4) begin 108 | buf_rd_state <= CH_3; 109 | end 110 | else begin 111 | buf_rd_state <= buf_rd_state; 112 | end 113 | end 114 | CH_3: begin 115 | if(pixel_count == VIDEO_WIDTH / 4) begin 116 | buf_rd_state <= CH_4; 117 | end 118 | else begin 119 | buf_rd_state <= buf_rd_state; 120 | end 121 | end 122 | CH_4: begin 123 | if((pixel_count == VIDEO_WIDTH / 4) 124 | && (row_count == VIDEO_HEIGHT / 4)) begin 125 | buf_rd_state <= CH_5; 126 | end 127 | else if((pixel_count == VIDEO_WIDTH / 4) 128 | && (row_count < VIDEO_HEIGHT / 4)) begin 129 | buf_rd_state <= CH_1; 130 | end 131 | else begin 132 | buf_rd_state <= buf_rd_state; 133 | end 134 | end 135 | CH_5: begin 136 | if((pixel_count == VIDEO_WIDTH * (3/4) 137 | && (row_count == VIDEO_HEIGHT)) begin 138 | buf_rd_state <= CH_1; 139 | end 140 | else begin 141 | buf_rd_state <= buf_rd_state; 142 | end 143 | end 144 | endcase 145 | ``` 146 | 147 | ### 图像旋转逻辑 148 | 149 | 在计算旋转后的坐标后，基于该坐标寻找原图中的数据，如果无法找到对应的数据则不显示，这样可以避免产生空像素的情况。坐标对应关系的计算方法如下述所示： 150 | 151 | $$\begin{bmatrix} 152 | x_0 & y_0 & 1 153 | \end{bmatrix} = 154 | \begin{bmatrix} 155 | x_1 & y_1 & 1 156 | \end{bmatrix} = 157 | \begin{bmatrix} 158 | \cos(\theta) & -\sin (\theta) & 0 \\ 159 | \sin(\theta) & \cos(\theta) & 0 \\ 160 | 0 & 0 & 1 161 | \end{bmatrix}$$ 162 | 163 | 如果想要 RTL 实现三角函数运算是比较困难的，因此可以直接利用查找表来控制运算过程，直接给出每个角度对应三角函数的运算结果。你可以自行查看位于 `RTL` 文件夹中的相关内容。 164 | 165 | 坐标变换的伪代码如下述所示： 166 | ```verilog 167 | assign x_rotate_temp = (x_wire <<< 8) * cos_value - (y_wire <<< 8) * sin_value; 168 | assign y_rotate_temp = (x_wire <<< 8) * sin_value + (y_wire <<< 8) * cos_value; 169 | 170 | assign x_rotate = x_rotate_temp >>> 16; 171 | assign y_rotate = y_rotate_temp >>> 16; 172 | ``` 173 | 174 | ### 图像缩放逻辑 175 | 176 | 通过直接抽取缩放后的坐标对应地址的数据，可实现对图像的缩放，也即对完整的视频抽掉其中的部分像素实现缩放功能，这种方法可以与旋转模块实现无缝集成，降低资源使用率。坐标变换的伪代码如下述所示： 177 | 178 | ```verilog 179 | assign x_cnt = write_read_len[9:0]; 180 | assign y_cnt = write_read_len[31:10]; 181 | 182 | rd_addr <= scale_value*x_cnt + scale_value*VIDEO_WIDTH*y_cnt; 183 | ``` 184 | 185 | ### 其他模块 186 | 187 | #### 视频融合模块 188 | 189 | 此模块旨在将双目摄像头输入的两路视频信号叠加融合为新的一路视频源，为实现完美融合，你可能需要将第一路视频进行偏移处理，这需要 $1280\times n + a$ 个地址的存储单元，其中 $n$ 表示偏移行数， $a$ 表示偏移列数。默认仅将两路视频各取 50% 叠加。 190 | 191 | #### UART 指令控制模块 192 | 193 | 此模块旨在将电脑传输的串口数据转为控制指令，点击[此处](https://github.com/MongooseOrion/Multi-channel-video-splicing/blob/main/Document/command.md)可查看控制指令对应的功能。 194 | 195 | #### 字符显示模块 196 | 197 | 该模块用于显示字符，包括初始化的固化内容和以太网字符传输模块，固化的 ROM 资源已初始化 16 个字符和所有数字，通过以太网可传输多达 5 个中文字符。若要使用以太网传输字符功能，你需将目标主机 IP 地址设置为 `192.168.0.2`。 198 | 199 | #### 亮度和色相调整模块 200 | 201 | 该模块用于调整输出图像的亮度和颜色，这包括色相和灰阶调整。 202 | 203 | ## 资源使用量 204 | 205 | | 逻辑资源类别 | 使用量 | 使用百分比 | 206 | | :--- | :---: | :---: | 207 | | FF（Flip-Flops） | 8738 | 14 | 208 | | LUT | 12279 | 29 | 209 | | LUT-FF pairs | 4056 | 9 | 210 | | BRAM | 24 | 31 | 211 | | 分布式 RAM | 444 | 3 | 212 | | DLL（Delay Locked Loop）| 1 | 10 | 213 | | PLL（Phase Locked Loop）| 4 | 80 | 214 | | 算术运算单元（APM）| 1 | 2 | 215 | | 时钟缓冲器（RCKB） | 0 | 0 | 216 | | I/O Blocks Data | 28 | 44 | 217 | | I/O Blocks Register | 6 | 40 | 218 | | I/O Blocks Special | 135 | 62 | 219 | | I/O Logic | 169 | 43 | 220 | | 低压差稳压器（LDO） | 0 | 0 | 221 | 222 | ## 实际效果 223 | 224 | 你可以点击[此处](https://www.bilibili.com/video/BV17C4y1m7Rr/)前往 bilibili 视频网观看相关的演示视频。 --------------------------------------------------------------------------------