├── SqrtCORDIC ├── db │ ├── SqrtCORDIC.map.logdb │ ├── SqrtCORDIC.map_bb.logdb │ ├── SqrtCORDIC.smart_action.txt │ ├── .cmp.kpt │ ├── SqrtCORDIC.hif │ ├── SqrtCORDIC.ae.hdb │ ├── SqrtCORDIC.asm.rdb │ ├── SqrtCORDIC.cmp.bpm │ ├── SqrtCORDIC.cmp.cdb │ ├── SqrtCORDIC.cmp.hdb │ ├── SqrtCORDIC.cmp.idb │ ├── SqrtCORDIC.cmp.rdb │ ├── SqrtCORDIC.lpc.rdb │ ├── SqrtCORDIC.map.bpm │ ├── SqrtCORDIC.map.cdb │ ├── SqrtCORDIC.map.hdb │ ├── SqrtCORDIC.map.kpt │ ├── SqrtCORDIC.map.rdb │ ├── SqrtCORDIC.sta.rdb │ ├── SqrtCORDIC.map.ammdb │ ├── SqrtCORDIC.map_bb.cdb │ ├── SqrtCORDIC.map_bb.hdb │ ├── SqrtCORDIC.rtlv.hdb │ ├── SqrtCORDIC.sgate.nvd │ ├── SqrtCORDIC.vpr.ammdb │ ├── SqrtCORDIC.(0).cnf.cdb │ ├── SqrtCORDIC.(0).cnf.hdb │ ├── SqrtCORDIC.pre_map.cdb │ ├── SqrtCORDIC.pre_map.hdb │ ├── SqrtCORDIC.routing.rdb │ ├── SqrtCORDIC.rtlv_sg.cdb │ ├── SqrtCORDIC.sgate_sm.nvd │ ├── SqrtCORDIC.cmp_merge.kpt │ ├── SqrtCORDIC.tis_db_list.ddb │ ├── SqrtCORDIC.cbx.xml │ ├── SqrtCORDIC.rtlv_sg_swap.cdb │ ├── SqrtCORDIC.sgate_sm_bdd.nvd │ ├── SqrtCORDIC.sld_design_entry.sci │ ├── SqrtCORDIC.sld_design_entry_dsc.sci │ ├── SqrtCORDIC.tiscmp.fast_1100mv_0c.ddb │ ├── SqrtCORDIC.tiscmp.slow_1100mv_0c.ddb │ ├── SqrtCORDIC.tiscmp.fast_1100mv_85c.ddb │ ├── SqrtCORDIC.tiscmp.slow_1100mv_85c.ddb │ ├── SqrtCORDIC.root_partition.map.reg_db.cdb │ ├── SqrtCORDIC.sta_cmp.8_H7_slow_1100mv_85c.tdb │ ├── SqrtCORDIC.tiscmp.fastest_slow_1100mv_0c.ddb │ ├── SqrtCORDIC.tiscmp.fastest_slow_1100mv_85c.ddb │ ├── SqrtCORDIC.cyclonev_io_sim_cache.ff_0c_fast.hsd │ ├── SqrtCORDIC.cyclonev_io_sim_cache.ff_85c_fast.hsd │ ├── SqrtCORDIC.cyclonev_io_sim_cache.ss_0c_slow.hsd │ ├── SqrtCORDIC.cyclonev_io_sim_cache.ss_85c_slow.hsd │ ├── SqrtCORDIC.db_info │ ├── SqrtCORDIC.tmw_info │ ├── SqrtCORDIC.lpc.html │ ├── SqrtCORDIC.lpc.txt │ ├── SqrtCORDIC.npp.qmsg │ ├── SqrtCORDIC.asm.qmsg │ ├── SqrtCORDIC_partition_pins.json │ ├── SqrtCORDIC.hier_info │ ├── SqrtCORDIC.map.qmsg │ ├── SqrtCORDIC.eda.qmsg │ ├── prev_cmp_SqrtCORDIC.qmsg │ ├── SqrtCORDIC.fit.qmsg │ └── SqrtCORDIC.sta.qmsg ├── output_files │ ├── SqrtCORDIC.sld │ ├── SqrtCORDIC.done │ ├── SqrtCORDIC.sof │ ├── SqrtCORDIC.fit.rpt │ ├── SqrtCORDIC.jdi │ ├── SqrtCORDIC.fit.smsg │ ├── SqrtCORDIC.map.summary │ ├── SqrtCORDIC.fit.summary │ ├── SqrtCORDIC.sta.summary │ ├── SqrtCORDIC.asm.rpt │ ├── SqrtCORDIC.eda.rpt │ └── SqrtCORDIC.flow.rpt ├── ModelSim │ ├── SqrtCORDIC │ │ ├── _vmake │ │ ├── _lib.qdb │ │ ├── _lib1_1.qdb │ │ ├── _lib1_1.qpg │ │ ├── _lib1_1.qtl │ │ └── _info │ ├── SqrtCORDIC.cr.mti │ ├── SqrtCORDIC.v │ ├── SimDataDec.txt │ ├── Testbench.v.bak │ ├── Testbench.v │ ├── SimDataBin.txt │ └── SqrtCORDIC.mpf ├── simulation │ ├── qsim │ │ ├── work │ │ │ ├── _vmake │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_7.qdb │ │ │ ├── _lib1_7.qpg │ │ │ ├── _lib1_7.qtl │ │ │ └── _info │ │ ├── SqrtCORDIC.sft │ │ ├── SqrtCORDIC.do │ │ ├── transcript │ │ ├── Waveform.vwf.vt │ │ └── SqrtCORDIC_modelsim.xrf │ └── modelsim │ │ ├── SqrtCORDIC.sft │ │ └── SqrtCORDIC_modelsim.xrf ├── incremental_db │ ├── compiled_partitions │ │ ├── SqrtCORDIC.root_partition.cmp.logdb │ │ ├── SqrtCORDIC.root_partition.cmp.hbdb.sig │ │ ├── SqrtCORDIC.root_partition.map.hbdb.sig │ │ ├── SqrtCORDIC.rrp.hdb │ │ ├── SqrtCORDIC.rrs.cdb │ │ ├── SqrtCORDIC.db_info │ │ ├── SqrtCORDIC.root_partition.cmp.cdb │ │ ├── SqrtCORDIC.root_partition.cmp.dfp │ │ ├── SqrtCORDIC.root_partition.cmp.hdb │ │ ├── SqrtCORDIC.root_partition.map.cdb │ │ ├── SqrtCORDIC.root_partition.map.dpi │ │ ├── SqrtCORDIC.root_partition.map.hdb │ │ ├── SqrtCORDIC.root_partition.map.kpt │ │ ├── SqrtCORDIC.root_partition.cmp.ammdb │ │ ├── SqrtCORDIC.root_partition.cmp.rcfdb │ │ ├── SqrtCORDIC.root_partition.cmp.hbdb.cdb │ │ ├── SqrtCORDIC.root_partition.cmp.hbdb.hdb │ │ ├── SqrtCORDIC.root_partition.map.hbdb.cdb │ │ ├── SqrtCORDIC.root_partition.map.hbdb.hdb │ │ └── SqrtCORDIC.root_partition.map.hbdb.hb_info │ └── README ├── Capture1.PNG ├── Capture2.PNG ├── SqrtCORDIC.qws ├── SqrtCORDIC.v.bak ├── SqrtCORDIC.qpf ├── SqrtCORDIC.v ├── SqrtCORDIC.qsf └── c5_pin_model_dump.txt ├── Dataflow.png └── README.md /SqrtCORDIC/db/SqrtCORDIC.map.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map_bb.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.smart_action.txt: -------------------------------------------------------------------------------- 1 | SOURCE 2 | -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.sld: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.done: -------------------------------------------------------------------------------- 1 | Sun Nov 03 16:46:50 2019 2 | -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SqrtCORDIC/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /Dataflow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/Dataflow.png -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/SqrtCORDIC.sft: -------------------------------------------------------------------------------- 1 | set tool_name "ModelSim-Altera (Verilog)" 2 | -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/modelsim/SqrtCORDIC.sft: -------------------------------------------------------------------------------- 1 | set tool_name "ModelSim-Altera (Verilog)" 2 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/.cmp.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/.cmp.kpt -------------------------------------------------------------------------------- /SqrtCORDIC/Capture1.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/Capture1.PNG -------------------------------------------------------------------------------- /SqrtCORDIC/Capture2.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/Capture2.PNG -------------------------------------------------------------------------------- /SqrtCORDIC/SqrtCORDIC.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/SqrtCORDIC.qws -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.hbdb.sig: -------------------------------------------------------------------------------- 1 | 7aee213afbf8301ed5eefc8c827f49a3 -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.hbdb.sig: -------------------------------------------------------------------------------- 1 | 7aee213afbf8301ed5eefc8c827f49a3 -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.hif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.hif -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.ae.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.ae.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.asm.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.asm.rdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cmp.bpm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cmp.bpm -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cmp.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cmp.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cmp.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cmp.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cmp.idb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cmp.idb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cmp.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cmp.rdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.lpc.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.lpc.rdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map.bpm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.map.bpm -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.map.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.map.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.map.kpt -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.map.rdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.sta.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.sta.rdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map.ammdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.map.ammdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map_bb.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.map_bb.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map_bb.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.map_bb.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.rtlv.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.rtlv.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.sgate.nvd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.sgate.nvd -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.vpr.ammdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.vpr.ammdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.(0).cnf.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.(0).cnf.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.(0).cnf.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.(0).cnf.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.pre_map.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.pre_map.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.pre_map.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.pre_map.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.routing.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.routing.rdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.rtlv_sg.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.rtlv_sg.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.sgate_sm.nvd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.sgate_sm.nvd -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SqrtCORDIC/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/ModelSim/SqrtCORDIC/_lib.qdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cmp_merge.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cmp_merge.kpt -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.tis_db_list.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.tis_db_list.ddb -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/output_files/SqrtCORDIC.sof -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/work/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/simulation/qsim/work/_lib.qdb -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SqrtCORDIC/_lib1_1.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/ModelSim/SqrtCORDIC/_lib1_1.qdb -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SqrtCORDIC/_lib1_1.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/ModelSim/SqrtCORDIC/_lib1_1.qpg -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SqrtCORDIC/_lib1_1.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/ModelSim/SqrtCORDIC/_lib1_1.qtl -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cbx.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.rtlv_sg_swap.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.rtlv_sg_swap.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.sgate_sm_bdd.nvd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.sgate_sm_bdd.nvd -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/output_files/SqrtCORDIC.fit.rpt -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.sld_design_entry.sci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.sld_design_entry.sci -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/work/_lib1_7.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/simulation/qsim/work/_lib1_7.qdb -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/work/_lib1_7.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/simulation/qsim/work/_lib1_7.qpg -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/work/_lib1_7.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/simulation/qsim/work/_lib1_7.qtl -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.sld_design_entry_dsc.sci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.sld_design_entry_dsc.sci -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.tiscmp.fast_1100mv_0c.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.tiscmp.fast_1100mv_0c.ddb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.tiscmp.slow_1100mv_0c.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.tiscmp.slow_1100mv_0c.ddb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.tiscmp.fast_1100mv_85c.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.tiscmp.fast_1100mv_85c.ddb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.tiscmp.slow_1100mv_85c.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.tiscmp.slow_1100mv_85c.ddb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.root_partition.map.reg_db.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.root_partition.map.reg_db.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.sta_cmp.8_H7_slow_1100mv_85c.tdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.sta_cmp.8_H7_slow_1100mv_85c.tdb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.tiscmp.fastest_slow_1100mv_0c.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.tiscmp.fastest_slow_1100mv_0c.ddb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.tiscmp.fastest_slow_1100mv_85c.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.tiscmp.fastest_slow_1100mv_85c.ddb -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cyclonev_io_sim_cache.ff_0c_fast.hsd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cyclonev_io_sim_cache.ff_0c_fast.hsd -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cyclonev_io_sim_cache.ff_85c_fast.hsd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cyclonev_io_sim_cache.ff_85c_fast.hsd -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cyclonev_io_sim_cache.ss_0c_slow.hsd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cyclonev_io_sim_cache.ss_0c_slow.hsd -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.cyclonev_io_sim_cache.ss_85c_slow.hsd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/db/SqrtCORDIC.cyclonev_io_sim_cache.ss_85c_slow.hsd -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 2 | Version_Index = 402707200 3 | Creation_Time = Sun Nov 03 16:43:11 2019 4 | -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.rrp.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.rrp.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.rrs.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.rrs.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 2 | Version_Index = 402707200 3 | Creation_Time = Fri Nov 01 14:50:08 2019 4 | -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.dfp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.dfp -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.dpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.dpi -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.kpt -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.ammdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.ammdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.rcfdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.rcfdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.hbdb.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.hbdb.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.hbdb.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.cmp.hbdb.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.hbdb.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.hbdb.cdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.hbdb.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.hbdb.hdb -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.hbdb.hb_info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Muhazam-Mustapha/SqrtCORDIC/HEAD/SqrtCORDIC/incremental_db/compiled_partitions/SqrtCORDIC.root_partition.map.hbdb.hb_info -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /SqrtCORDIC/SqrtCORDIC.v.bak: -------------------------------------------------------------------------------- 1 | module SqrtCORDIC(input Start, 2 | input clk, 3 | output Stop); 4 | 5 | 6 | /// D A T A U N I T variables 7 | 8 | wire gatedClk; 9 | 10 | assign gatedClk = clk & ~Stop; 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.tmw_info: -------------------------------------------------------------------------------- 1 | start_full_compilation:s:00:01:29 2 | start_analysis_synthesis:s:00:00:16-start_full_compilation 3 | start_analysis_elaboration:s-start_full_compilation 4 | start_fitter:s:00:00:49-start_full_compilation 5 | start_assembler:s:00:00:12-start_full_compilation 6 | start_timing_analyzer:s:00:00:09-start_full_compilation 7 | start_eda_netlist_writer:s:00:00:03-start_full_compilation 8 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.lpc.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 |
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
19 | -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/SqrtCORDIC.do: -------------------------------------------------------------------------------- 1 | onerror {exit -code 1} 2 | vlib work 3 | vlog -work work SqrtCORDIC.vo 4 | vlog -work work Waveform.vwf.vt 5 | vsim -novopt -c -t 1ps -L cyclonev_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.SqrtCORDIC_vlg_vec_tst -voptargs="+acc" 6 | vcd file -direction SqrtCORDIC.msim.vcd 7 | vcd add -internal SqrtCORDIC_vlg_vec_tst/* 8 | vcd add -internal SqrtCORDIC_vlg_vec_tst/i1/* 9 | run -all 10 | quit -f 11 | -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.fit.smsg: -------------------------------------------------------------------------------- 1 | Extra Info (176236): Started Fast Input/Output/OE register processing 2 | Extra Info (176237): Finished Fast Input/Output/OE register processing 3 | Extra Info (176238): Start inferring scan chains for DSP blocks 4 | Extra Info (176239): Inferring scan chains for DSP blocks is complete 5 | Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density 6 | Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks 7 | -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Sun Nov 03 16:44:54 2019 2 | Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Lite Edition 3 | Revision Name : SqrtCORDIC 4 | Top-level Entity Name : SqrtCORDIC 5 | Family : Cyclone V 6 | Logic utilization (in ALMs) : N/A 7 | Total registers : 86 8 | Total pins : 59 9 | Total virtual pins : 0 10 | Total block memory bits : 0 11 | Total DSP Blocks : 1 12 | Total HSSI RX PCSs : 0 13 | Total HSSI PMA RX Deserializers : 0 14 | Total HSSI TX PCSs : 0 15 | Total HSSI PMA TX Serializers : 0 16 | Total PLLs : 0 17 | Total DLLs : 0 18 | -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SqrtCORDIC.cr.mti: -------------------------------------------------------------------------------- 1 | C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/SqrtCORDIC.v {1 {vlog -work SqrtCORDIC -stats=none C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/SqrtCORDIC.v 2 | Model Technology ModelSim ALTERA vlog 10.4d Compiler 2015.12 Dec 30 2015 3 | -- Compiling module SqrtCORDIC 4 | 5 | Top level modules: 6 | SqrtCORDIC 7 | 8 | } {} {}} C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/Testbench.v {1 {vlog -work SqrtCORDIC -stats=none C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/Testbench.v 9 | Model Technology ModelSim ALTERA vlog 10.4d Compiler 2015.12 Dec 30 2015 10 | -- Compiling module Testbench 11 | 12 | Top level modules: 13 | Testbench 14 | 15 | } {} {}} 16 | -------------------------------------------------------------------------------- /SqrtCORDIC/incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Sun Nov 03 16:45:42 2019 2 | Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Lite Edition 3 | Revision Name : SqrtCORDIC 4 | Top-level Entity Name : SqrtCORDIC 5 | Family : Cyclone V 6 | Device : 5CGXFC7C7F23C8 7 | Timing Models : Final 8 | Logic utilization (in ALMs) : 54 / 56,480 ( < 1 % ) 9 | Total registers : 86 10 | Total pins : 59 / 268 ( 22 % ) 11 | Total virtual pins : 0 12 | Total block memory bits : 0 / 7,024,640 ( 0 % ) 13 | Total RAM Blocks : 0 / 686 ( 0 % ) 14 | Total DSP Blocks : 1 / 156 ( < 1 % ) 15 | Total HSSI RX PCSs : 0 / 6 ( 0 % ) 16 | Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % ) 17 | Total HSSI TX PCSs : 0 / 6 ( 0 % ) 18 | Total HSSI PMA TX Serializers : 0 / 6 ( 0 % ) 19 | Total PLLs : 0 / 13 ( 0 % ) 20 | Total DLLs : 0 / 4 ( 0 % ) 21 | -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z2 4 | 13 5 | !s112 1.1 6 | !i10d 8192 7 | !i10e 25 8 | !i10f 100 9 | cModel Technology 10 | Z0 dC:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim 11 | vSqrtCORDIC 12 | Z1 !s110 1572771067 13 | !i10b 1 14 | !s100 ]mUjA@2JboKXA52:JiEn:2 15 | Id;CkIh]:Bgh2UN>i:11 36 | IN92ni6Bi@zdnQC2HFX;BC1 37 | R2 38 | R0 39 | w1572771064 40 | 8Waveform.vwf.vt 41 | FWaveform.vwf.vt 42 | L0 30 43 | R3 44 | r1 45 | !s85 0 46 | 31 47 | !s108 1572771067.000000 48 | !s107 Waveform.vwf.vt| 49 | !s90 -work|work|Waveform.vwf.vt| 50 | !i113 1 51 | R4 52 | n@sqrt@c@o@r@d@i@c_vlg_vec_tst 53 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.lpc.txt: -------------------------------------------------------------------------------- 1 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 2 | ; Legal Partition Candidates ; 3 | +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 4 | ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; 5 | +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 6 | -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SqrtCORDIC/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z2 4 | 13 5 | !s112 1.1 6 | !i10d 8192 7 | !i10e 25 8 | !i10f 100 9 | cModel Technology 10 | dC:/altera_lite/16.0 11 | vSqrtCORDIC 12 | !s110 1572768210 13 | !i10b 1 14 | !s100 lO>Ua2 15 | I:[?I[`EYFL5_^Uk=1edE00 16 | Z0 VDg1SIo80bB@j0V0VzS_@n1 17 | Z1 dC:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim 18 | w1572767608 19 | 8C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/SqrtCORDIC.v 20 | FC:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/SqrtCORDIC.v 21 | L0 1 22 | Z2 OV;L;10.4d;61 23 | r1 24 | !s85 0 25 | 31 26 | !s108 1572768210.000000 27 | !s107 C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/SqrtCORDIC.v| 28 | !s90 -reportprogress|300|-work|SqrtCORDIC|-stats=none|C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/SqrtCORDIC.v| 29 | !i113 1 30 | Z3 o-work SqrtCORDIC 31 | n@sqrt@c@o@r@d@i@c 32 | vTestbench 33 | !s110 1572769547 34 | !i10b 1 35 | !s100 m17nc<^E`Y3m7zl8jY;]K0 36 | I[?`[R<5>Wf_^3mf]o6Gc<3 37 | R0 38 | R1 39 | w1572769537 40 | 8C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/Testbench.v 41 | FC:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/Testbench.v 42 | L0 5 43 | R2 44 | r1 45 | !s85 0 46 | 31 47 | !s108 1572769547.000000 48 | !s107 C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/Testbench.v| 49 | !s90 -reportprogress|300|-work|SqrtCORDIC|-stats=none|C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/Testbench.v| 50 | !i113 1 51 | R3 52 | n@testbench 53 | -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.sta.summary: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------ 2 | TimeQuest Timing Analyzer Summary 3 | ------------------------------------------------------------ 4 | 5 | Type : Slow 1100mV 85C Model Setup 'clk' 6 | Slack : -14.685 7 | TNS : -394.828 8 | 9 | Type : Slow 1100mV 85C Model Hold 'clk' 10 | Slack : 0.354 11 | TNS : 0.000 12 | 13 | Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk' 14 | Slack : -0.724 15 | TNS : -102.263 16 | 17 | Type : Slow 1100mV 0C Model Setup 'clk' 18 | Slack : -14.666 19 | TNS : -393.838 20 | 21 | Type : Slow 1100mV 0C Model Hold 'clk' 22 | Slack : 0.336 23 | TNS : 0.000 24 | 25 | Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk' 26 | Slack : -0.724 27 | TNS : -104.822 28 | 29 | Type : Fast 1100mV 85C Model Setup 'clk' 30 | Slack : -5.703 31 | TNS : -147.412 32 | 33 | Type : Fast 1100mV 85C Model Hold 'clk' 34 | Slack : 0.091 35 | TNS : 0.000 36 | 37 | Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk' 38 | Slack : -0.476 39 | TNS : -44.946 40 | 41 | Type : Fast 1100mV 0C Model Setup 'clk' 42 | Slack : -5.186 43 | TNS : -132.556 44 | 45 | Type : Fast 1100mV 0C Model Hold 'clk' 46 | Slack : 0.079 47 | TNS : 0.000 48 | 49 | Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk' 50 | Slack : -0.466 51 | TNS : -43.569 52 | 53 | ------------------------------------------------------------ 54 | -------------------------------------------------------------------------------- /SqrtCORDIC/SqrtCORDIC.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 22 | # Date created = 14:09:31 November 01, 2019 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "16.0" 27 | DATE = "14:09:31 November 01, 2019" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "SqrtCORDIC" 32 | -------------------------------------------------------------------------------- /SqrtCORDIC/SqrtCORDIC.v: -------------------------------------------------------------------------------- 1 | module SqrtCORDIC(input Start, 2 | input clk, 3 | input [31:0] InpNum, 4 | output [23:0] Result, 5 | output reg Stop); 6 | 7 | 8 | /// D A T A U N I T variables 9 | 10 | wire init; 11 | wire gatedClk; 12 | wire le; 13 | wire [23:0] added; 14 | wire [23:0] addOrNot; 15 | wire [47:0] squared; 16 | wire [31:0] squaredRestr; 17 | 18 | reg [23:0] OneShReg; 19 | reg [23:0] Sqrt; 20 | reg [31:0] InputReg; 21 | 22 | assign gatedClk = clk & ~Stop; 23 | 24 | 25 | /// C O N T R O L U N I T variables 26 | 27 | reg [4:0] ctr; 28 | 29 | 30 | /// D A T A U N I T definition 31 | 32 | assign added = OneShReg + Sqrt; 33 | assign squared = added * added; 34 | assign squaredRestr = squared >> 16; 35 | assign le = (squaredRestr <= InputReg) ? 1'b1 : 1'b0; 36 | assign addOrNot = (le == 1) ? added : Sqrt; 37 | assign Result = Sqrt; 38 | 39 | always@(negedge gatedClk) 40 | begin 41 | OneShReg <= (init == 1'b1) ? (24'b1 << 23) : (OneShReg >>> 1); 42 | Sqrt <= (init == 1'b1) ? 24'b0 : addOrNot; 43 | InputReg <= (init == 1'b1) ? InpNum : InputReg; 44 | end 45 | 46 | 47 | /// C O N T R O L U N I T definition 48 | 49 | assign init = Start; 50 | 51 | always@(posedge clk) 52 | if (Start == 1'b1) 53 | begin 54 | ctr <= 5'b0; 55 | Stop <= 1'b0; 56 | end 57 | else 58 | if (ctr >= 5'd23) 59 | begin 60 | ctr <= ctr; 61 | Stop <= 1'b1; 62 | end 63 | else 64 | begin 65 | ctr <= ctr + 5'b1; 66 | Stop <= 1'b0; 67 | end 68 | 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SqrtCORDIC.v: -------------------------------------------------------------------------------- 1 | module SqrtCORDIC(input Start, 2 | input clk, 3 | input [31:0] InpNum, 4 | output [23:0] Result, 5 | output reg Stop); 6 | 7 | 8 | /// D A T A U N I T variables 9 | 10 | wire init; 11 | wire gatedClk; 12 | wire le; 13 | wire [23:0] added; 14 | wire [23:0] addOrNot; 15 | wire [47:0] squared; 16 | wire [31:0] squaredRestr; 17 | 18 | reg [23:0] OneShReg; 19 | reg [23:0] Sqrt; 20 | reg [31:0] InputReg; 21 | 22 | assign gatedClk = clk & ~Stop; 23 | 24 | 25 | /// C O N T R O L U N I T variables 26 | 27 | reg [4:0] ctr; 28 | 29 | 30 | /// D A T A U N I T definition 31 | 32 | assign added = OneShReg + Sqrt; 33 | assign squared = added * added; 34 | assign squaredRestr = squared >> 16; 35 | assign le = (squaredRestr <= InputReg) ? 1'b1 : 1'b0; 36 | assign addOrNot = (le == 1) ? added : Sqrt; 37 | assign Result = Sqrt; 38 | 39 | always@(negedge gatedClk) 40 | begin 41 | OneShReg <= (init == 1'b1) ? (24'b1 << 23) : (OneShReg >>> 1); 42 | Sqrt <= (init == 1'b1) ? 24'b0 : addOrNot; 43 | InputReg <= (init == 1'b1) ? InpNum : InputReg; 44 | end 45 | 46 | 47 | /// C O N T R O L U N I T definition 48 | 49 | assign init = Start; 50 | 51 | always@(posedge clk) 52 | if (Start == 1'b1) 53 | begin 54 | ctr <= 5'b0; 55 | Stop <= 1'b0; 56 | end 57 | else 58 | if (ctr >= 5'd23) 59 | begin 60 | ctr <= ctr; 61 | Stop <= 1'b1; 62 | end 63 | else 64 | begin 65 | ctr <= ctr + 5'b1; 66 | Stop <= 1'b0; 67 | end 68 | 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SqrtCORDIC v1.0 2 | A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well. 3 | 4 | ## Input 5 | **Format:** \[16.16\] fixed point notation - 16 bits for integer part, 16 bits for fraction part. 6 | 7 | The value that is to be fed into the input is a positive 32-bit integer value of *N*×216 where *N* is the a real number (with fraction part). Largest value accepted for *N* is 1111 1111 1111 1111.1111 1111 1111 11112. 8 | 9 | For example, if you want to calculate the square root of 35.6110, you have to feed the input with the nearest integer of 35.6110×216 = 233373710 which a sequence of 32 bits of 0000 0000 0010 0011 1001 1100 0010 1001\[16.16\]. There is a radix (base) point at the middle of the sequence which makes it equal to 10 0011.1001 1100 0010 10012. 10 | 11 | ## Output 12 | **Format:** \[8.16\] fixed point notation - 8 bits for integer part, 16 bits for fraction part. 13 | * Number of bits in integer part of the square root is half of the original number, but the number of bits in the fraction part is kept at 16 to preserve accuracy. 14 | 15 | For example, if you are reading a binary sequence of 0011 1100 0110 1011 0000 1000 at the output after the calculation completed, the actual value in decimal is the plain integer binary value divided by 216 = 3959560×2−16 = 60.418. 16 | 17 | ## Signaling Sequence 18 | Start signal needs to go up for at least a complete 2 clock cycles, then goes down again. After that the calculation starts. 19 | 20 | The calculation requires 8+16 = 24 clocks to finish. The completion of the calculation is signifies by the raise of Stop signal. 21 | 22 | The diagram below shows the waveform of the calculation of the square root of 2000.4510 = 131101491\[16.16\]. When the Stop signal finally goes high, the value of the square root (Result) is 2931188\[8.16\] = 293118810×2−16 = 44.72610, accurate to 3 decimal fraction places. 23 | 24 | ![Signaling Sequence](https://github.com/Muhazam-Mustapha/SqrtCORDIC/blob/master/SqrtCORDIC/Capture2.PNG) 25 | 26 | ## Data Flow Diagram 27 | ![Data Flow Diagram](https://github.com/Muhazam-Mustapha/SqrtCORDIC/blob/master/Dataflow.png) 28 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.npp.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1572770809683 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572770809698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 03 16:46:49 2019 " "Processing started: Sun Nov 03 16:46:49 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1572770809698 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1572770809698 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp SqrtCORDIC -c SqrtCORDIC --netlist_type=sgate " "Command: quartus_npp SqrtCORDIC -c SqrtCORDIC --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1572770809698 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1572770809870 ""} 5 | { "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4543 " "Peak virtual memory: 4543 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1572770809917 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 03 16:46:49 2019 " "Processing ended: Sun Nov 03 16:46:49 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1572770809917 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1572770809917 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1572770809917 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1572770809917 ""} 6 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.asm.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1572770745485 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572770745485 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 03 16:45:45 2019 " "Processing started: Sun Nov 03 16:45:45 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1572770745485 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1572770745485 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off SqrtCORDIC -c SqrtCORDIC " "Command: quartus_asm --read_settings_files=off --write_settings_files=off SqrtCORDIC -c SqrtCORDIC" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1572770745485 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1572770746328 ""} 5 | { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1572770754798 ""} 6 | { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5039 " "Peak virtual memory: 5039 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1572770755396 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 03 16:45:55 2019 " "Processing ended: Sun Nov 03 16:45:55 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1572770755396 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1572770755396 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1572770755396 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1572770755396 ""} 7 | -------------------------------------------------------------------------------- /SqrtCORDIC/SqrtCORDIC.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 22 | # Date created = 14:09:31 November 01, 2019 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # SqrtCORDIC_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus Prime software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "Cyclone V" 41 | set_global_assignment -name DEVICE 5CGXFC7C7F23C8 42 | set_global_assignment -name TOP_LEVEL_ENTITY SqrtCORDIC 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:09:31 NOVEMBER 01, 2019" 45 | set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 46 | set_global_assignment -name VERILOG_FILE SqrtCORDIC.v 47 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 49 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 50 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 51 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 52 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 53 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 54 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 55 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 56 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 57 | set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf 58 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/transcript: -------------------------------------------------------------------------------- 1 | # do SqrtCORDIC.do 2 | # ** Warning: (vlib-34) Library already exists at "work". 3 | # 4 | # Model Technology ModelSim ALTERA vlog 10.4d Compiler 2015.12 Dec 30 2015 5 | # Start time: 16:51:06 on Nov 03,2019 6 | # vlog -work work SqrtCORDIC.vo 7 | # -- Compiling module SqrtCORDIC 8 | # 9 | # Top level modules: 10 | # SqrtCORDIC 11 | # End time: 16:51:07 on Nov 03,2019, Elapsed time: 0:00:01 12 | # Errors: 0, Warnings: 0 13 | # Model Technology ModelSim ALTERA vlog 10.4d Compiler 2015.12 Dec 30 2015 14 | # Start time: 16:51:07 on Nov 03,2019 15 | # vlog -work work Waveform.vwf.vt 16 | # -- Compiling module SqrtCORDIC_vlg_vec_tst 17 | # 18 | # Top level modules: 19 | # SqrtCORDIC_vlg_vec_tst 20 | # End time: 16:51:07 on Nov 03,2019, Elapsed time: 0:00:00 21 | # Errors: 0, Warnings: 0 22 | # vsim -novopt -c -t 1ps -L cyclonev_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.SqrtCORDIC_vlg_vec_tst -voptargs=""+acc"" 23 | # Start time: 16:51:07 on Nov 03,2019 24 | # Loading work.SqrtCORDIC_vlg_vec_tst 25 | # Loading work.SqrtCORDIC 26 | # Loading altera_ver.dffeas 27 | # Loading altera_ver.PRIM_GDFF_LOW 28 | # ** Warning: (vsim-3015) SqrtCORDIC.vo(2804): [PCDPC] - Port size (1) does not match connection size (26) for port 'az'. The port definition is at: nofile(38). 29 | # Time: 0 ps Iteration: 0 Instance: /SqrtCORDIC_vlg_vec_tst/i1/\Mult0~8 File: nofile 30 | # ** Warning: (vsim-3015) SqrtCORDIC.vo(2804): [PCDPC] - Port size (16) does not match connection size (18) for port 'bx'. The port definition is at: nofile(38). 31 | # Time: 0 ps Iteration: 0 Instance: /SqrtCORDIC_vlg_vec_tst/i1/\Mult0~8 File: nofile 32 | # ** Warning: (vsim-3015) SqrtCORDIC.vo(2804): [PCDPC] - Port size (16) does not match connection size (19) for port 'by'. The port definition is at: nofile(38). 33 | # Time: 0 ps Iteration: 0 Instance: /SqrtCORDIC_vlg_vec_tst/i1/\Mult0~8 File: nofile 34 | # ** Warning: (vsim-3015) SqrtCORDIC.vo(2804): [PCDPC] - Port size (1) does not match connection size (18) for port 'bz'. The port definition is at: nofile(38). 35 | # Time: 0 ps Iteration: 0 Instance: /SqrtCORDIC_vlg_vec_tst/i1/\Mult0~8 File: nofile 36 | # ** Warning: (vsim-3015) SqrtCORDIC.vo(2804): [PCDPC] - Port size (24) does not match connection size (27) for port 'scanin'. The port definition is at: nofile(38). 37 | # Time: 0 ps Iteration: 0 Instance: /SqrtCORDIC_vlg_vec_tst/i1/\Mult0~8 File: nofile 38 | # ** Warning: (vsim-3015) SqrtCORDIC.vo(2804): [PCDPC] - Port size (64) does not match connection size (1) for port 'chainin'. The port definition is at: nofile(38). 39 | # Time: 0 ps Iteration: 0 Instance: /SqrtCORDIC_vlg_vec_tst/i1/\Mult0~8 File: nofile 40 | # ** Warning: (vsim-3015) (): [PCDPC] - Port size () does not match connection size () for . 41 | # Time: 0 ps Iteration: 0 Protected: /SqrtCORDIC_vlg_vec_tst/i1/\Mult0~8 // File: nofile 42 | # ** Warning: (vsim-3015) (): [PCDPC] - Port size () does not match connection size () for . 43 | # Time: 0 ps Iteration: 0 Protected: /SqrtCORDIC_vlg_vec_tst/i1/\Mult0~8 // File: nofile 44 | # ** Note: $finish : Waveform.vwf.vt(51) 45 | # Time: 1 us Iteration: 0 Instance: /SqrtCORDIC_vlg_vec_tst 46 | # End time: 16:51:08 on Nov 03,2019, Elapsed time: 0:00:01 47 | # Errors: 0, Warnings: 8 48 | -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SimDataDec.txt: -------------------------------------------------------------------------------- 1 | Start clk Shift Register Result Stop 2 | 0 0 0xxxxxxxxxxxxxxxxxxxxxxx 0.000000 x 3 | 1 1 0xxxxxxxxxxxxxxxxxxxxxxx 0.000000 0 4 | 1 0 100000000000000000000000 0.000000 0 5 | 1 1 100000000000000000000000 0.000000 0 6 | 1 0 100000000000000000000000 0.000000 0 7 | 0 1 100000000000000000000000 0.000000 0 8 | 0 0 010000000000000000000000 0.000000 0 9 | 0 1 010000000000000000000000 0.000000 0 10 | 0 0 001000000000000000000000 0.000000 0 11 | 0 1 001000000000000000000000 0.000000 0 12 | 0 0 000100000000000000000000 32.000000 0 13 | 0 1 000100000000000000000000 32.000000 0 14 | 0 0 000010000000000000000000 32.000000 0 15 | 0 1 000010000000000000000000 32.000000 0 16 | 0 0 000001000000000000000000 40.000000 0 17 | 0 1 000001000000000000000000 40.000000 0 18 | 0 0 000000100000000000000000 44.000000 0 19 | 0 1 000000100000000000000000 44.000000 0 20 | 0 0 000000010000000000000000 44.000000 0 21 | 0 1 000000010000000000000000 44.000000 0 22 | 0 0 000000001000000000000000 44.000000 0 23 | 0 1 000000001000000000000000 44.000000 0 24 | 0 0 000000000100000000000000 44.500000 0 25 | 0 1 000000000100000000000000 44.500000 0 26 | 0 0 000000000010000000000000 44.500000 0 27 | 0 1 000000000010000000000000 44.500000 0 28 | 0 0 000000000001000000000000 44.625000 0 29 | 0 1 000000000001000000000000 44.625000 0 30 | 0 0 000000000000100000000000 44.687500 0 31 | 0 1 000000000000100000000000 44.687500 0 32 | 0 0 000000000000010000000000 44.718750 0 33 | 0 1 000000000000010000000000 44.718750 0 34 | 0 0 000000000000001000000000 44.718750 0 35 | 0 1 000000000000001000000000 44.718750 0 36 | 0 0 000000000000000100000000 44.718750 0 37 | 0 1 000000000000000100000000 44.718750 0 38 | 0 0 000000000000000010000000 44.722656 0 39 | 0 1 000000000000000010000000 44.722656 0 40 | 0 0 000000000000000001000000 44.724609 0 41 | 0 1 000000000000000001000000 44.724609 0 42 | 0 0 000000000000000000100000 44.725586 0 43 | 0 1 000000000000000000100000 44.725586 0 44 | 0 0 000000000000000000010000 44.726074 0 45 | 0 1 000000000000000000010000 44.726074 0 46 | 0 0 000000000000000000001000 44.726318 0 47 | 0 1 000000000000000000001000 44.726318 0 48 | 0 0 000000000000000000000100 44.726318 0 49 | 0 1 000000000000000000000100 44.726318 0 50 | 0 0 000000000000000000000010 44.726379 0 51 | 0 1 000000000000000000000010 44.726379 0 52 | 0 0 000000000000000000000001 44.726379 0 53 | 0 1 000000000000000000000000 44.726379 1 54 | 0 0 000000000000000000000000 44.726379 1 55 | 0 1 000000000000000000000000 44.726379 1 56 | 0 0 000000000000000000000000 44.726379 1 57 | 0 1 000000000000000000000000 44.726379 1 58 | 0 0 000000000000000000000000 44.726379 1 59 | 0 1 000000000000000000000000 44.726379 1 60 | 0 0 000000000000000000000000 44.726379 1 61 | 0 1 000000000000000000000000 44.726379 1 62 | 0 0 000000000000000000000000 44.726379 1 63 | 0 1 000000000000000000000000 44.726379 1 64 | 0 0 000000000000000000000000 44.726379 1 65 | 0 1 000000000000000000000000 44.726379 1 66 | 0 0 000000000000000000000000 44.726379 1 67 | 0 1 000000000000000000000000 44.726379 1 68 | -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/Testbench.v.bak: -------------------------------------------------------------------------------- 1 | `timescale 1ms/1us 2 | `define CapBin $fdisplay(SimDataBin, " %b %b %b %b %b", sr.Start, sr.clk, sr.OneShReg, sr.Sqrt, sr.Stop) 3 | `define CapDec $fdisplay(SimDataDec, " %b %b %b %d %b", sr.Start, sr.clk, sr.OneShReg, sr.Sqrt/(2.0**16), sr.Stop) 4 | 5 | module Testbench(); 6 | 7 | reg [31:0] num; 8 | reg clk ; 9 | reg start; 10 | wire [23:0] result; 11 | wire stop; 12 | 13 | initial 14 | 15 | begin: SimBlock 16 | 17 | integer SimDataBin; 18 | integer SimDataDec; 19 | SimDataBin = $fopen ("SimDataBin.txt","w"); 20 | SimDataDec = $fopen ("SimDataDec.txt","w"); 21 | $fdisplay(SimDataBin, "start clk shift register stop " ); 22 | $fdisplay(SimDataDec, "start clk shift register stop " ); 23 | 24 | num = 2000.45 * 2**16; 25 | 26 | start = 0; clk = 0; #1; `CapBin; `CapDec; 27 | start = 1; clk = 1; #1; `CapBin; `CapDec; 28 | clk = 0; #1; `CapBin; `CapDec; 29 | clk = 1; #1; `CapBin; `CapDec; 30 | clk = 0; #1; `CapBin; `CapDec; 31 | start = 0; clk = 1; #1; `CapBin; `CapDec; 32 | clk = 0; #1; `CapBin; `CapDec; 33 | clk = 1; #1; `CapBin; `CapDec; 34 | clk = 0; #1; `CapBin; `CapDec; 35 | clk = 1; #1; `CapBin; `CapDec; 36 | clk = 0; #1; `CapBin; `CapDec; 37 | clk = 1; #1; `CapBin; `CapDec; 38 | clk = 0; #1; `CapBin; `CapDec; 39 | clk = 1; #1; `CapBin; `CapDec; 40 | clk = 0; #1; `CapBin; `CapDec; 41 | clk = 1; #1; `CapBin; `CapDec; 42 | clk = 0; #1; `CapBin; `CapDec; 43 | clk = 1; #1; `CapBin; `CapDec; 44 | clk = 0; #1; `CapBin; `CapDec; 45 | clk = 1; #1; `CapBin; `CapDec; 46 | clk = 0; #1; `CapBin; `CapDec; 47 | clk = 1; #1; `CapBin; `CapDec; 48 | clk = 0; #1; `CapBin; `CapDec; 49 | clk = 1; #1; `CapBin; `CapDec; 50 | clk = 0; #1; `CapBin; `CapDec; 51 | clk = 1; #1; `CapBin; `CapDec; 52 | clk = 0; #1; `CapBin; `CapDec; 53 | clk = 1; #1; `CapBin; `CapDec; 54 | clk = 0; #1; `CapBin; `CapDec; 55 | clk = 1; #1; `CapBin; `CapDec; 56 | clk = 0; #1; `CapBin; `CapDec; 57 | clk = 1; #1; `CapBin; `CapDec; 58 | clk = 0; #1; `CapBin; `CapDec; 59 | clk = 1; #1; `CapBin; `CapDec; 60 | clk = 0; #1; `CapBin; `CapDec; 61 | clk = 1; #1; `CapBin; `CapDec; 62 | clk = 0; #1; `CapBin; `CapDec; 63 | clk = 1; #1; `CapBin; `CapDec; 64 | clk = 0; #1; `CapBin; `CapDec; 65 | clk = 1; #1; `CapBin; `CapDec; 66 | clk = 0; #1; `CapBin; `CapDec; 67 | clk = 1; #1; `CapBin; `CapDec; 68 | clk = 0; #1; `CapBin; `CapDec; 69 | clk = 1; #1; `CapBin; `CapDec; 70 | clk = 0; #1; `CapBin; `CapDec; 71 | clk = 1; #1; `CapBin; `CapDec; 72 | clk = 0; #1; `CapBin; `CapDec; 73 | clk = 1; #1; `CapBin; `CapDec; 74 | clk = 0; #1; `CapBin; `CapDec; 75 | clk = 1; #1; `CapBin; `CapDec; 76 | clk = 0; #1; `CapBin; `CapDec; 77 | clk = 1; #1; `CapBin; `CapDec; 78 | clk = 0; #1; `CapBin; `CapDec; 79 | clk = 1; #1; `CapBin; `CapDec; 80 | clk = 0; #1; `CapBin; `CapDec; 81 | clk = 1; #1; `CapBin; `CapDec; 82 | clk = 0; #1; `CapBin; `CapDec; 83 | clk = 1; #1; `CapBin; `CapDec; 84 | clk = 0; #1; `CapBin; `CapDec; 85 | clk = 1; #1; `CapBin; `CapDec; 86 | clk = 0; #1; `CapBin; `CapDec; 87 | clk = 1; #1; `CapBin; `CapDec; 88 | clk = 0; #1; `CapBin; `CapDec; 89 | clk = 1; #1; `CapBin; `CapDec; 90 | clk = 0; #1; `CapBin; `CapDec; 91 | clk = 1; #1; `CapBin; `CapDec; 92 | 93 | $fclose(SimDataBin); 94 | $fclose(SimDataDec); 95 | $finish; 96 | end 97 | 98 | SqrtCORDIC sr(.Start(start), 99 | .clk(clk), 100 | .InpNum(num), 101 | .Result(), 102 | .Stop()); 103 | 104 | endmodule 105 | -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/Testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ms/1us 2 | `define CapBin $fdisplay(SimDataBin, " %b %b %b %b %b", sr.Start, sr.clk, sr.OneShReg, sr.Sqrt, sr.Stop) 3 | `define CapDec $fdisplay(SimDataDec, " %b %b %b %9.6f %b", sr.Start, sr.clk, sr.OneShReg, sr.Sqrt/(2.0**16), sr.Stop) 4 | 5 | module Testbench(); 6 | 7 | reg [31:0] num; 8 | reg clk ; 9 | reg start; 10 | wire [23:0] result; 11 | wire stop; 12 | 13 | initial 14 | 15 | begin: SimBlock 16 | 17 | integer SimDataBin; 18 | integer SimDataDec; 19 | SimDataBin = $fopen ("SimDataBin.txt","w"); 20 | SimDataDec = $fopen ("SimDataDec.txt","w"); 21 | $fdisplay(SimDataBin, "Start clk Shift Register Result Stop " ); 22 | $fdisplay(SimDataDec, "Start clk Shift Register Result Stop " ); 23 | 24 | num = 2000.45 * 2**16; 25 | 26 | start = 0; clk = 0; #1; `CapBin; `CapDec; 27 | start = 1; clk = 1; #1; `CapBin; `CapDec; 28 | clk = 0; #1; `CapBin; `CapDec; 29 | clk = 1; #1; `CapBin; `CapDec; 30 | clk = 0; #1; `CapBin; `CapDec; 31 | start = 0; clk = 1; #1; `CapBin; `CapDec; 32 | clk = 0; #1; `CapBin; `CapDec; 33 | clk = 1; #1; `CapBin; `CapDec; 34 | clk = 0; #1; `CapBin; `CapDec; 35 | clk = 1; #1; `CapBin; `CapDec; 36 | clk = 0; #1; `CapBin; `CapDec; 37 | clk = 1; #1; `CapBin; `CapDec; 38 | clk = 0; #1; `CapBin; `CapDec; 39 | clk = 1; #1; `CapBin; `CapDec; 40 | clk = 0; #1; `CapBin; `CapDec; 41 | clk = 1; #1; `CapBin; `CapDec; 42 | clk = 0; #1; `CapBin; `CapDec; 43 | clk = 1; #1; `CapBin; `CapDec; 44 | clk = 0; #1; `CapBin; `CapDec; 45 | clk = 1; #1; `CapBin; `CapDec; 46 | clk = 0; #1; `CapBin; `CapDec; 47 | clk = 1; #1; `CapBin; `CapDec; 48 | clk = 0; #1; `CapBin; `CapDec; 49 | clk = 1; #1; `CapBin; `CapDec; 50 | clk = 0; #1; `CapBin; `CapDec; 51 | clk = 1; #1; `CapBin; `CapDec; 52 | clk = 0; #1; `CapBin; `CapDec; 53 | clk = 1; #1; `CapBin; `CapDec; 54 | clk = 0; #1; `CapBin; `CapDec; 55 | clk = 1; #1; `CapBin; `CapDec; 56 | clk = 0; #1; `CapBin; `CapDec; 57 | clk = 1; #1; `CapBin; `CapDec; 58 | clk = 0; #1; `CapBin; `CapDec; 59 | clk = 1; #1; `CapBin; `CapDec; 60 | clk = 0; #1; `CapBin; `CapDec; 61 | clk = 1; #1; `CapBin; `CapDec; 62 | clk = 0; #1; `CapBin; `CapDec; 63 | clk = 1; #1; `CapBin; `CapDec; 64 | clk = 0; #1; `CapBin; `CapDec; 65 | clk = 1; #1; `CapBin; `CapDec; 66 | clk = 0; #1; `CapBin; `CapDec; 67 | clk = 1; #1; `CapBin; `CapDec; 68 | clk = 0; #1; `CapBin; `CapDec; 69 | clk = 1; #1; `CapBin; `CapDec; 70 | clk = 0; #1; `CapBin; `CapDec; 71 | clk = 1; #1; `CapBin; `CapDec; 72 | clk = 0; #1; `CapBin; `CapDec; 73 | clk = 1; #1; `CapBin; `CapDec; 74 | clk = 0; #1; `CapBin; `CapDec; 75 | clk = 1; #1; `CapBin; `CapDec; 76 | clk = 0; #1; `CapBin; `CapDec; 77 | clk = 1; #1; `CapBin; `CapDec; 78 | clk = 0; #1; `CapBin; `CapDec; 79 | clk = 1; #1; `CapBin; `CapDec; 80 | clk = 0; #1; `CapBin; `CapDec; 81 | clk = 1; #1; `CapBin; `CapDec; 82 | clk = 0; #1; `CapBin; `CapDec; 83 | clk = 1; #1; `CapBin; `CapDec; 84 | clk = 0; #1; `CapBin; `CapDec; 85 | clk = 1; #1; `CapBin; `CapDec; 86 | clk = 0; #1; `CapBin; `CapDec; 87 | clk = 1; #1; `CapBin; `CapDec; 88 | clk = 0; #1; `CapBin; `CapDec; 89 | clk = 1; #1; `CapBin; `CapDec; 90 | clk = 0; #1; `CapBin; `CapDec; 91 | clk = 1; #1; `CapBin; `CapDec; 92 | 93 | $fclose(SimDataBin); 94 | $fclose(SimDataDec); 95 | $finish; 96 | end 97 | 98 | SqrtCORDIC sr(.Start(start), 99 | .clk(clk), 100 | .InpNum(num), 101 | .Result(), 102 | .Stop()); 103 | 104 | endmodule 105 | -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SimDataBin.txt: -------------------------------------------------------------------------------- 1 | Start clk Shift Register Result Stop 2 | 0 0 0xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx x 3 | 1 1 0xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx 0 4 | 1 0 100000000000000000000000 000000000000000000000000 0 5 | 1 1 100000000000000000000000 000000000000000000000000 0 6 | 1 0 100000000000000000000000 000000000000000000000000 0 7 | 0 1 100000000000000000000000 000000000000000000000000 0 8 | 0 0 010000000000000000000000 000000000000000000000000 0 9 | 0 1 010000000000000000000000 000000000000000000000000 0 10 | 0 0 001000000000000000000000 000000000000000000000000 0 11 | 0 1 001000000000000000000000 000000000000000000000000 0 12 | 0 0 000100000000000000000000 001000000000000000000000 0 13 | 0 1 000100000000000000000000 001000000000000000000000 0 14 | 0 0 000010000000000000000000 001000000000000000000000 0 15 | 0 1 000010000000000000000000 001000000000000000000000 0 16 | 0 0 000001000000000000000000 001010000000000000000000 0 17 | 0 1 000001000000000000000000 001010000000000000000000 0 18 | 0 0 000000100000000000000000 001011000000000000000000 0 19 | 0 1 000000100000000000000000 001011000000000000000000 0 20 | 0 0 000000010000000000000000 001011000000000000000000 0 21 | 0 1 000000010000000000000000 001011000000000000000000 0 22 | 0 0 000000001000000000000000 001011000000000000000000 0 23 | 0 1 000000001000000000000000 001011000000000000000000 0 24 | 0 0 000000000100000000000000 001011001000000000000000 0 25 | 0 1 000000000100000000000000 001011001000000000000000 0 26 | 0 0 000000000010000000000000 001011001000000000000000 0 27 | 0 1 000000000010000000000000 001011001000000000000000 0 28 | 0 0 000000000001000000000000 001011001010000000000000 0 29 | 0 1 000000000001000000000000 001011001010000000000000 0 30 | 0 0 000000000000100000000000 001011001011000000000000 0 31 | 0 1 000000000000100000000000 001011001011000000000000 0 32 | 0 0 000000000000010000000000 001011001011100000000000 0 33 | 0 1 000000000000010000000000 001011001011100000000000 0 34 | 0 0 000000000000001000000000 001011001011100000000000 0 35 | 0 1 000000000000001000000000 001011001011100000000000 0 36 | 0 0 000000000000000100000000 001011001011100000000000 0 37 | 0 1 000000000000000100000000 001011001011100000000000 0 38 | 0 0 000000000000000010000000 001011001011100100000000 0 39 | 0 1 000000000000000010000000 001011001011100100000000 0 40 | 0 0 000000000000000001000000 001011001011100110000000 0 41 | 0 1 000000000000000001000000 001011001011100110000000 0 42 | 0 0 000000000000000000100000 001011001011100111000000 0 43 | 0 1 000000000000000000100000 001011001011100111000000 0 44 | 0 0 000000000000000000010000 001011001011100111100000 0 45 | 0 1 000000000000000000010000 001011001011100111100000 0 46 | 0 0 000000000000000000001000 001011001011100111110000 0 47 | 0 1 000000000000000000001000 001011001011100111110000 0 48 | 0 0 000000000000000000000100 001011001011100111110000 0 49 | 0 1 000000000000000000000100 001011001011100111110000 0 50 | 0 0 000000000000000000000010 001011001011100111110100 0 51 | 0 1 000000000000000000000010 001011001011100111110100 0 52 | 0 0 000000000000000000000001 001011001011100111110100 0 53 | 0 1 000000000000000000000000 001011001011100111110100 1 54 | 0 0 000000000000000000000000 001011001011100111110100 1 55 | 0 1 000000000000000000000000 001011001011100111110100 1 56 | 0 0 000000000000000000000000 001011001011100111110100 1 57 | 0 1 000000000000000000000000 001011001011100111110100 1 58 | 0 0 000000000000000000000000 001011001011100111110100 1 59 | 0 1 000000000000000000000000 001011001011100111110100 1 60 | 0 0 000000000000000000000000 001011001011100111110100 1 61 | 0 1 000000000000000000000000 001011001011100111110100 1 62 | 0 0 000000000000000000000000 001011001011100111110100 1 63 | 0 1 000000000000000000000000 001011001011100111110100 1 64 | 0 0 000000000000000000000000 001011001011100111110100 1 65 | 0 1 000000000000000000000000 001011001011100111110100 1 66 | 0 0 000000000000000000000000 001011001011100111110100 1 67 | 0 1 000000000000000000000000 001011001011100111110100 1 68 | -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.asm.rpt: -------------------------------------------------------------------------------- 1 | Assembler report for SqrtCORDIC 2 | Sun Nov 03 16:45:55 2019 3 | Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Assembler Summary 11 | 3. Assembler Settings 12 | 4. Assembler Generated Files 13 | 5. Assembler Device Options: C:/Users/UPNM/Desktop/SqrtCORDIC/output_files/SqrtCORDIC.sof 14 | 6. Assembler Messages 15 | 16 | 17 | 18 | ---------------- 19 | ; Legal Notice ; 20 | ---------------- 21 | Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 22 | Your use of Altera Corporation's design tools, logic functions 23 | and other software and tools, and its AMPP partner logic 24 | functions, and any output files from any of the foregoing 25 | (including device programming or simulation files), and any 26 | associated documentation or information are expressly subject 27 | to the terms and conditions of the Altera Program License 28 | Subscription Agreement, the Altera Quartus Prime License Agreement, 29 | the Altera MegaCore Function License Agreement, or other 30 | applicable license agreement, including, without limitation, 31 | that your use is for the sole purpose of programming logic 32 | devices manufactured by Altera and sold by Altera or its 33 | authorized distributors. Please refer to the applicable 34 | agreement for further details. 35 | 36 | 37 | 38 | +---------------------------------------------------------------+ 39 | ; Assembler Summary ; 40 | +-----------------------+---------------------------------------+ 41 | ; Assembler Status ; Successful - Sun Nov 03 16:45:55 2019 ; 42 | ; Revision Name ; SqrtCORDIC ; 43 | ; Top-level Entity Name ; SqrtCORDIC ; 44 | ; Family ; Cyclone V ; 45 | ; Device ; 5CGXFC7C7F23C8 ; 46 | +-----------------------+---------------------------------------+ 47 | 48 | 49 | +----------------------------------+ 50 | ; Assembler Settings ; 51 | +--------+---------+---------------+ 52 | ; Option ; Setting ; Default Value ; 53 | +--------+---------+---------------+ 54 | 55 | 56 | +--------------------------------------------------------------+ 57 | ; Assembler Generated Files ; 58 | +--------------------------------------------------------------+ 59 | ; File Name ; 60 | +--------------------------------------------------------------+ 61 | ; C:/Users/UPNM/Desktop/SqrtCORDIC/output_files/SqrtCORDIC.sof ; 62 | +--------------------------------------------------------------+ 63 | 64 | 65 | +----------------------------------------------------------------------------------------+ 66 | ; Assembler Device Options: C:/Users/UPNM/Desktop/SqrtCORDIC/output_files/SqrtCORDIC.sof ; 67 | +----------------+-----------------------------------------------------------------------+ 68 | ; Option ; Setting ; 69 | +----------------+-----------------------------------------------------------------------+ 70 | ; Device ; 5CGXFC7C7F23C8 ; 71 | ; JTAG usercode ; 0x00EEE683 ; 72 | ; Checksum ; 0x00EEE683 ; 73 | +----------------+-----------------------------------------------------------------------+ 74 | 75 | 76 | +--------------------+ 77 | ; Assembler Messages ; 78 | +--------------------+ 79 | Info: ******************************************************************* 80 | Info: Running Quartus Prime Assembler 81 | Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 82 | Info: Processing started: Sun Nov 03 16:45:45 2019 83 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off SqrtCORDIC -c SqrtCORDIC 84 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. 85 | Info (115030): Assembler is generating device programming files 86 | Info: Quartus Prime Assembler was successful. 0 errors, 1 warning 87 | Info: Peak virtual memory: 5039 megabytes 88 | Info: Processing ended: Sun Nov 03 16:45:55 2019 89 | Info: Elapsed time: 00:00:10 90 | Info: Total CPU time (on all processors): 00:00:08 91 | 92 | 93 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC_partition_pins.json: -------------------------------------------------------------------------------- 1 | { 2 | "partitions" : [ 3 | { 4 | "name" : "Top", 5 | "pins" : [ 6 | { 7 | "name" : "Result[0]", 8 | "strict" : false 9 | }, 10 | { 11 | "name" : "Result[1]", 12 | "strict" : false 13 | }, 14 | { 15 | "name" : "Result[2]", 16 | "strict" : false 17 | }, 18 | { 19 | "name" : "Result[3]", 20 | "strict" : false 21 | }, 22 | { 23 | "name" : "Result[4]", 24 | "strict" : false 25 | }, 26 | { 27 | "name" : "Result[5]", 28 | "strict" : false 29 | }, 30 | { 31 | "name" : "Result[6]", 32 | "strict" : false 33 | }, 34 | { 35 | "name" : "Result[7]", 36 | "strict" : false 37 | }, 38 | { 39 | "name" : "Result[8]", 40 | "strict" : false 41 | }, 42 | { 43 | "name" : "Result[9]", 44 | "strict" : false 45 | }, 46 | { 47 | "name" : "Result[10]", 48 | "strict" : false 49 | }, 50 | { 51 | "name" : "Result[11]", 52 | "strict" : false 53 | }, 54 | { 55 | "name" : "Result[12]", 56 | "strict" : false 57 | }, 58 | { 59 | "name" : "Result[13]", 60 | "strict" : false 61 | }, 62 | { 63 | "name" : "Result[14]", 64 | "strict" : false 65 | }, 66 | { 67 | "name" : "Result[15]", 68 | "strict" : false 69 | }, 70 | { 71 | "name" : "Result[16]", 72 | "strict" : false 73 | }, 74 | { 75 | "name" : "Result[17]", 76 | "strict" : false 77 | }, 78 | { 79 | "name" : "Result[18]", 80 | "strict" : false 81 | }, 82 | { 83 | "name" : "Result[19]", 84 | "strict" : false 85 | }, 86 | { 87 | "name" : "Result[20]", 88 | "strict" : false 89 | }, 90 | { 91 | "name" : "Result[21]", 92 | "strict" : false 93 | }, 94 | { 95 | "name" : "Result[22]", 96 | "strict" : false 97 | }, 98 | { 99 | "name" : "Result[23]", 100 | "strict" : false 101 | }, 102 | { 103 | "name" : "Stop", 104 | "strict" : false 105 | }, 106 | { 107 | "name" : "Start", 108 | "strict" : false 109 | }, 110 | { 111 | "name" : "clk", 112 | "strict" : false 113 | }, 114 | { 115 | "name" : "InpNum[7]", 116 | "strict" : false 117 | }, 118 | { 119 | "name" : "InpNum[6]", 120 | "strict" : false 121 | }, 122 | { 123 | "name" : "InpNum[5]", 124 | "strict" : false 125 | }, 126 | { 127 | "name" : "InpNum[4]", 128 | "strict" : false 129 | }, 130 | { 131 | "name" : "InpNum[1]", 132 | "strict" : false 133 | }, 134 | { 135 | "name" : "InpNum[0]", 136 | "strict" : false 137 | }, 138 | { 139 | "name" : "InpNum[3]", 140 | "strict" : false 141 | }, 142 | { 143 | "name" : "InpNum[2]", 144 | "strict" : false 145 | }, 146 | { 147 | "name" : "InpNum[14]", 148 | "strict" : false 149 | }, 150 | { 151 | "name" : "InpNum[13]", 152 | "strict" : false 153 | }, 154 | { 155 | "name" : "InpNum[12]", 156 | "strict" : false 157 | }, 158 | { 159 | "name" : "InpNum[11]", 160 | "strict" : false 161 | }, 162 | { 163 | "name" : "InpNum[9]", 164 | "strict" : false 165 | }, 166 | { 167 | "name" : "InpNum[10]", 168 | "strict" : false 169 | }, 170 | { 171 | "name" : "InpNum[8]", 172 | "strict" : false 173 | }, 174 | { 175 | "name" : "InpNum[18]", 176 | "strict" : false 177 | }, 178 | { 179 | "name" : "InpNum[21]", 180 | "strict" : false 181 | }, 182 | { 183 | "name" : "InpNum[20]", 184 | "strict" : false 185 | }, 186 | { 187 | "name" : "InpNum[19]", 188 | "strict" : false 189 | }, 190 | { 191 | "name" : "InpNum[17]", 192 | "strict" : false 193 | }, 194 | { 195 | "name" : "InpNum[16]", 196 | "strict" : false 197 | }, 198 | { 199 | "name" : "InpNum[15]", 200 | "strict" : false 201 | }, 202 | { 203 | "name" : "InpNum[25]", 204 | "strict" : false 205 | }, 206 | { 207 | "name" : "InpNum[28]", 208 | "strict" : false 209 | }, 210 | { 211 | "name" : "InpNum[27]", 212 | "strict" : false 213 | }, 214 | { 215 | "name" : "InpNum[26]", 216 | "strict" : false 217 | }, 218 | { 219 | "name" : "InpNum[24]", 220 | "strict" : false 221 | }, 222 | { 223 | "name" : "InpNum[23]", 224 | "strict" : false 225 | }, 226 | { 227 | "name" : "InpNum[22]", 228 | "strict" : false 229 | }, 230 | { 231 | "name" : "InpNum[31]", 232 | "strict" : false 233 | }, 234 | { 235 | "name" : "InpNum[30]", 236 | "strict" : false 237 | }, 238 | { 239 | "name" : "InpNum[29]", 240 | "strict" : false 241 | } 242 | ] 243 | } 244 | ] 245 | } -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/Waveform.vwf.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Altera Program License 8 | // Subscription Agreement, the Altera Quartus Prime License Agreement, 9 | // the Altera MegaCore Function License Agreement, or other 10 | // applicable license agreement, including, without limitation, 11 | // that your use is for the sole purpose of programming logic 12 | // devices manufactured by Altera and sold by Altera or its 13 | // authorized distributors. Please refer to the applicable 14 | // agreement for further details. 15 | 16 | // ***************************************************************************** 17 | // This file contains a Verilog test bench with test vectors .The test vectors 18 | // are exported from a vector file in the Quartus Waveform Editor and apply to 19 | // the top level entity of the current Quartus project .The user can use this 20 | // testbench to simulate his design using a third-party simulation tool . 21 | // ***************************************************************************** 22 | // Generated on "11/03/2019 16:51:04" 23 | 24 | // Verilog Test Bench (with test vectors) for design : SqrtCORDIC 25 | // 26 | // Simulation tool : 3rd Party 27 | // 28 | 29 | `timescale 1 ps/ 1 ps 30 | module SqrtCORDIC_vlg_vec_tst(); 31 | // constants 32 | // general purpose registers 33 | reg [31:0] InpNum; 34 | reg Start; 35 | reg clk; 36 | // wires 37 | wire [23:0] Result; 38 | wire Stop; 39 | 40 | // assign statements (if any) 41 | SqrtCORDIC i1 ( 42 | // port map - connection between master ports and signals/registers 43 | .InpNum(InpNum), 44 | .Result(Result), 45 | .Start(Start), 46 | .Stop(Stop), 47 | .clk(clk) 48 | ); 49 | initial 50 | begin 51 | #1000000 $finish; 52 | end 53 | 54 | // clk 55 | always 56 | begin 57 | clk = 1'b0; 58 | clk = #10000 1'b1; 59 | #10000; 60 | end 61 | // InpNum[ 31 ] 62 | initial 63 | begin 64 | InpNum[31] = 1'b0; 65 | end 66 | // InpNum[ 30 ] 67 | initial 68 | begin 69 | InpNum[30] = 1'b0; 70 | end 71 | // InpNum[ 29 ] 72 | initial 73 | begin 74 | InpNum[29] = 1'b0; 75 | end 76 | // InpNum[ 28 ] 77 | initial 78 | begin 79 | InpNum[28] = 1'b0; 80 | end 81 | // InpNum[ 27 ] 82 | initial 83 | begin 84 | InpNum[27] = 1'b0; 85 | end 86 | // InpNum[ 26 ] 87 | initial 88 | begin 89 | InpNum[26] = 1'b1; 90 | end 91 | // InpNum[ 25 ] 92 | initial 93 | begin 94 | InpNum[25] = 1'b1; 95 | end 96 | // InpNum[ 24 ] 97 | initial 98 | begin 99 | InpNum[24] = 1'b1; 100 | end 101 | // InpNum[ 23 ] 102 | initial 103 | begin 104 | InpNum[23] = 1'b1; 105 | end 106 | // InpNum[ 22 ] 107 | initial 108 | begin 109 | InpNum[22] = 1'b1; 110 | end 111 | // InpNum[ 21 ] 112 | initial 113 | begin 114 | InpNum[21] = 1'b0; 115 | end 116 | // InpNum[ 20 ] 117 | initial 118 | begin 119 | InpNum[20] = 1'b1; 120 | end 121 | // InpNum[ 19 ] 122 | initial 123 | begin 124 | InpNum[19] = 1'b0; 125 | end 126 | // InpNum[ 18 ] 127 | initial 128 | begin 129 | InpNum[18] = 1'b0; 130 | end 131 | // InpNum[ 17 ] 132 | initial 133 | begin 134 | InpNum[17] = 1'b0; 135 | end 136 | // InpNum[ 16 ] 137 | initial 138 | begin 139 | InpNum[16] = 1'b0; 140 | end 141 | // InpNum[ 15 ] 142 | initial 143 | begin 144 | InpNum[15] = 1'b0; 145 | end 146 | // InpNum[ 14 ] 147 | initial 148 | begin 149 | InpNum[14] = 1'b1; 150 | end 151 | // InpNum[ 13 ] 152 | initial 153 | begin 154 | InpNum[13] = 1'b1; 155 | end 156 | // InpNum[ 12 ] 157 | initial 158 | begin 159 | InpNum[12] = 1'b1; 160 | end 161 | // InpNum[ 11 ] 162 | initial 163 | begin 164 | InpNum[11] = 1'b0; 165 | end 166 | // InpNum[ 10 ] 167 | initial 168 | begin 169 | InpNum[10] = 1'b0; 170 | end 171 | // InpNum[ 9 ] 172 | initial 173 | begin 174 | InpNum[9] = 1'b1; 175 | end 176 | // InpNum[ 8 ] 177 | initial 178 | begin 179 | InpNum[8] = 1'b1; 180 | end 181 | // InpNum[ 7 ] 182 | initial 183 | begin 184 | InpNum[7] = 1'b0; 185 | end 186 | // InpNum[ 6 ] 187 | initial 188 | begin 189 | InpNum[6] = 1'b0; 190 | end 191 | // InpNum[ 5 ] 192 | initial 193 | begin 194 | InpNum[5] = 1'b1; 195 | end 196 | // InpNum[ 4 ] 197 | initial 198 | begin 199 | InpNum[4] = 1'b1; 200 | end 201 | // InpNum[ 3 ] 202 | initial 203 | begin 204 | InpNum[3] = 1'b0; 205 | end 206 | // InpNum[ 2 ] 207 | initial 208 | begin 209 | InpNum[2] = 1'b0; 210 | end 211 | // InpNum[ 1 ] 212 | initial 213 | begin 214 | InpNum[1] = 1'b1; 215 | end 216 | // InpNum[ 0 ] 217 | initial 218 | begin 219 | InpNum[0] = 1'b1; 220 | end 221 | 222 | // Start 223 | initial 224 | begin 225 | Start = 1'b0; 226 | Start = #6181 1'b1; 227 | Start = #37969 1'b0; 228 | end 229 | endmodule 230 | 231 | -------------------------------------------------------------------------------- /SqrtCORDIC/c5_pin_model_dump.txt: -------------------------------------------------------------------------------- 1 | io_4iomodule_c5_index: 77gpio_index: 2 2 | io_4iomodule_c5_index: 60gpio_index: 476 3 | io_4iomodule_c5_index: 62gpio_index: 6 4 | io_4iomodule_c5_index: 26gpio_index: 472 5 | io_4iomodule_c5_index: 20gpio_index: 10 6 | io_4iomodule_c5_index: 12gpio_index: 468 7 | io_4iomodule_c5_index: 27gpio_index: 14 8 | io_4iomodule_c5_index: 71gpio_index: 464 9 | io_4iomodule_c5_index: 56gpio_index: 19 10 | io_4iomodule_c5_index: 14gpio_index: 460 11 | io_4iomodule_c5_index: 22gpio_index: 22 12 | io_4iomodule_c5_index: 10gpio_index: 456 13 | io_4iomodule_c5_index: 11gpio_index: 27 14 | io_4iomodule_c5_index: 73gpio_index: 452 15 | io_4iomodule_c5_index: 74gpio_index: 30 16 | io_4iomodule_c5_index: 76gpio_index: 448 17 | io_4iomodule_c5_index: 2gpio_index: 35 18 | io_4iomodule_c5_index: 78gpio_index: 444 19 | io_4iomodule_c5_index: 9gpio_index: 38 20 | io_4iomodule_c5_index: 36gpio_index: 440 21 | io_4iomodule_c5_index: 51gpio_index: 43 22 | io_4iomodule_c5_index: 23gpio_index: 436 23 | io_4iomodule_c5_index: 53gpio_index: 46 24 | io_4iomodule_c5_index: 50gpio_index: 432 25 | io_4iomodule_c5_index: 0gpio_index: 51 26 | io_4iomodule_c5_index: 43gpio_index: 428 27 | io_4iomodule_c5_index: 67gpio_index: 54 28 | io_4iomodule_c5_index: 16gpio_index: 424 29 | io_4iomodule_c5_index: 44gpio_index: 59 30 | io_4iomodule_c5_index: 29gpio_index: 420 31 | io_4iomodule_c5_index: 1gpio_index: 62 32 | io_4iomodule_c5_index: 8gpio_index: 416 33 | io_4iomodule_c5_index: 65gpio_index: 67 34 | io_4iomodule_c5_index: 25gpio_index: 412 35 | io_4iomodule_c5_index: 40gpio_index: 70 36 | io_4iomodule_c5_index: 55gpio_index: 408 37 | io_4iomodule_c5_index: 66gpio_index: 75 38 | io_4iomodule_c5_index: 5gpio_index: 404 39 | io_4iomodule_c5_index: 61gpio_index: 78 40 | io_4iomodule_c5_index: 17gpio_index: 400 41 | io_4iomodule_c5_index: 42gpio_index: 83 42 | io_4iomodule_c5_index: 59gpio_index: 396 43 | io_4iomodule_c5_index: 54gpio_index: 86 44 | io_4iomodule_c5_index: 58gpio_index: 392 45 | io_4iomodule_c5_index: 33gpio_index: 91 46 | io_4iomodule_c5_index: 41gpio_index: 388 47 | io_4iomodule_c5_index: 69gpio_index: 94 48 | io_4iomodule_c5_index: 3gpio_index: 384 49 | io_4iomodule_c5_index: 18gpio_index: 99 50 | io_4iomodule_c5_index: 15gpio_index: 380 51 | io_4iomodule_c5_index: 6gpio_index: 102 52 | io_4iomodule_c5_index: 7gpio_index: 376 53 | io_4iomodule_c5_index: 47gpio_index: 107 54 | io_4iomodule_c5_index: 39gpio_index: 372 55 | io_4iomodule_c5_index: 32gpio_index: 110 56 | io_4iomodule_c5_index: 24gpio_index: 368 57 | io_4iomodule_c5_index: 48gpio_index: 115 58 | io_4iomodule_c5_index: 57gpio_index: 364 59 | io_4iomodule_c5_index: 64gpio_index: 118 60 | io_4iomodule_c5_index: 31gpio_index: 360 61 | io_4iomodule_c5_index: 46gpio_index: 123 62 | io_4iomodule_c5_index: 21gpio_index: 356 63 | io_4iomodule_c5_index: 72gpio_index: 126 64 | io_4iomodule_c5_index: 70gpio_index: 352 65 | io_4iomodule_c5_index: 49gpio_index: 131 66 | io_4iomodule_c5_index: 63gpio_index: 348 67 | io_4iomodule_c5_index: 79gpio_index: 134 68 | io_4iomodule_c5_index: 28gpio_index: 344 69 | io_4iomodule_c5_index: 34gpio_index: 139 70 | io_4iomodule_c5_index: 4gpio_index: 340 71 | io_4iomodule_c5_index: 68gpio_index: 142 72 | io_4iomodule_c5_index: 37gpio_index: 336 73 | io_4iomodule_c5_index: 45gpio_index: 147 74 | io_4iomodule_c5_index: 35gpio_index: 332 75 | io_4iomodule_c5_index: 38gpio_index: 150 76 | io_4iomodule_c5_index: 19gpio_index: 328 77 | io_4iomodule_c5_index: 52gpio_index: 155 78 | io_4iomodule_c5_index: 30gpio_index: 324 79 | io_4iomodule_c5_index: 75gpio_index: 158 80 | io_4iomodule_c5_index: 13gpio_index: 320 81 | io_4iomodule_h_c5_index: 0gpio_index: 161 82 | io_4iomodule_h_c5_index: 15gpio_index: 165 83 | io_4iomodule_h_c5_index: 27gpio_index: 169 84 | io_4iomodule_h_c5_index: 30gpio_index: 173 85 | io_4iomodule_h_c5_index: 36gpio_index: 176 86 | io_4iomodule_h_c5_index: 37gpio_index: 180 87 | io_4iomodule_h_c5_index: 26gpio_index: 184 88 | io_4iomodule_h_c5_index: 24gpio_index: 188 89 | io_4iomodule_h_c5_index: 1gpio_index: 192 90 | io_4iomodule_h_c5_index: 21gpio_index: 196 91 | io_4iomodule_h_c5_index: 18gpio_index: 200 92 | io_4iomodule_h_c5_index: 6gpio_index: 204 93 | io_4iomodule_h_c5_index: 31gpio_index: 208 94 | io_4iomodule_h_c5_index: 3gpio_index: 212 95 | io_4iomodule_h_c5_index: 20gpio_index: 216 96 | io_4iomodule_h_c5_index: 4gpio_index: 220 97 | io_4iomodule_h_c5_index: 29gpio_index: 224 98 | io_4iomodule_h_c5_index: 22gpio_index: 228 99 | io_4iomodule_h_c5_index: 16gpio_index: 232 100 | io_4iomodule_h_c5_index: 9gpio_index: 236 101 | io_4iomodule_h_c5_index: 25gpio_index: 240 102 | io_4iomodule_h_c5_index: 11gpio_index: 244 103 | io_4iomodule_h_c5_index: 19gpio_index: 248 104 | io_4iomodule_h_c5_index: 23gpio_index: 252 105 | io_4iomodule_h_c5_index: 17gpio_index: 256 106 | io_4iomodule_h_c5_index: 8gpio_index: 260 107 | io_4iomodule_h_c5_index: 38gpio_index: 264 108 | io_4iomodule_h_c5_index: 2gpio_index: 268 109 | io_4iomodule_h_c5_index: 12gpio_index: 272 110 | io_4iomodule_h_c5_index: 35gpio_index: 276 111 | io_4iomodule_h_c5_index: 13gpio_index: 280 112 | io_4iomodule_h_c5_index: 5gpio_index: 284 113 | io_4iomodule_h_c5_index: 28gpio_index: 288 114 | io_4iomodule_h_c5_index: 7gpio_index: 292 115 | io_4iomodule_h_c5_index: 34gpio_index: 296 116 | io_4iomodule_h_c5_index: 14gpio_index: 300 117 | io_4iomodule_h_c5_index: 33gpio_index: 304 118 | io_4iomodule_h_c5_index: 39gpio_index: 308 119 | io_4iomodule_h_c5_index: 32gpio_index: 312 120 | io_4iomodule_h_c5_index: 10gpio_index: 316 121 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.hier_info: -------------------------------------------------------------------------------- 1 | |SqrtCORDIC 2 | Start => OneShReg.OUTPUTSELECT 3 | Start => OneShReg.OUTPUTSELECT 4 | Start => OneShReg.OUTPUTSELECT 5 | Start => OneShReg.OUTPUTSELECT 6 | Start => OneShReg.OUTPUTSELECT 7 | Start => OneShReg.OUTPUTSELECT 8 | Start => OneShReg.OUTPUTSELECT 9 | Start => OneShReg.OUTPUTSELECT 10 | Start => OneShReg.OUTPUTSELECT 11 | Start => OneShReg.OUTPUTSELECT 12 | Start => OneShReg.OUTPUTSELECT 13 | Start => OneShReg.OUTPUTSELECT 14 | Start => OneShReg.OUTPUTSELECT 15 | Start => OneShReg.OUTPUTSELECT 16 | Start => OneShReg.OUTPUTSELECT 17 | Start => OneShReg.OUTPUTSELECT 18 | Start => OneShReg.OUTPUTSELECT 19 | Start => OneShReg.OUTPUTSELECT 20 | Start => OneShReg.OUTPUTSELECT 21 | Start => OneShReg.OUTPUTSELECT 22 | Start => OneShReg.OUTPUTSELECT 23 | Start => OneShReg.OUTPUTSELECT 24 | Start => OneShReg.OUTPUTSELECT 25 | Start => Sqrt.OUTPUTSELECT 26 | Start => Sqrt.OUTPUTSELECT 27 | Start => Sqrt.OUTPUTSELECT 28 | Start => Sqrt.OUTPUTSELECT 29 | Start => Sqrt.OUTPUTSELECT 30 | Start => Sqrt.OUTPUTSELECT 31 | Start => Sqrt.OUTPUTSELECT 32 | Start => Sqrt.OUTPUTSELECT 33 | Start => Sqrt.OUTPUTSELECT 34 | Start => Sqrt.OUTPUTSELECT 35 | Start => Sqrt.OUTPUTSELECT 36 | Start => Sqrt.OUTPUTSELECT 37 | Start => Sqrt.OUTPUTSELECT 38 | Start => Sqrt.OUTPUTSELECT 39 | Start => Sqrt.OUTPUTSELECT 40 | Start => Sqrt.OUTPUTSELECT 41 | Start => Sqrt.OUTPUTSELECT 42 | Start => Sqrt.OUTPUTSELECT 43 | Start => Sqrt.OUTPUTSELECT 44 | Start => Sqrt.OUTPUTSELECT 45 | Start => Sqrt.OUTPUTSELECT 46 | Start => Sqrt.OUTPUTSELECT 47 | Start => Sqrt.OUTPUTSELECT 48 | Start => Sqrt.OUTPUTSELECT 49 | Start => ctr.OUTPUTSELECT 50 | Start => ctr.OUTPUTSELECT 51 | Start => ctr.OUTPUTSELECT 52 | Start => ctr.OUTPUTSELECT 53 | Start => ctr.OUTPUTSELECT 54 | Start => Stop.OUTPUTSELECT 55 | Start => OneShReg[23].DATAIN 56 | Start => InputReg[0].ENA 57 | Start => InputReg[1].ENA 58 | Start => InputReg[2].ENA 59 | Start => InputReg[3].ENA 60 | Start => InputReg[4].ENA 61 | Start => InputReg[5].ENA 62 | Start => InputReg[6].ENA 63 | Start => InputReg[7].ENA 64 | Start => InputReg[8].ENA 65 | Start => InputReg[9].ENA 66 | Start => InputReg[10].ENA 67 | Start => InputReg[11].ENA 68 | Start => InputReg[12].ENA 69 | Start => InputReg[13].ENA 70 | Start => InputReg[14].ENA 71 | Start => InputReg[15].ENA 72 | Start => InputReg[16].ENA 73 | Start => InputReg[17].ENA 74 | Start => InputReg[18].ENA 75 | Start => InputReg[19].ENA 76 | Start => InputReg[20].ENA 77 | Start => InputReg[21].ENA 78 | Start => InputReg[22].ENA 79 | Start => InputReg[23].ENA 80 | Start => InputReg[24].ENA 81 | Start => InputReg[25].ENA 82 | Start => InputReg[26].ENA 83 | Start => InputReg[27].ENA 84 | Start => InputReg[28].ENA 85 | Start => InputReg[29].ENA 86 | Start => InputReg[30].ENA 87 | Start => InputReg[31].ENA 88 | clk => gatedClk.IN1 89 | clk => Stop~reg0.CLK 90 | clk => ctr[0].CLK 91 | clk => ctr[1].CLK 92 | clk => ctr[2].CLK 93 | clk => ctr[3].CLK 94 | clk => ctr[4].CLK 95 | InpNum[0] => InputReg[0].DATAIN 96 | InpNum[1] => InputReg[1].DATAIN 97 | InpNum[2] => InputReg[2].DATAIN 98 | InpNum[3] => InputReg[3].DATAIN 99 | InpNum[4] => InputReg[4].DATAIN 100 | InpNum[5] => InputReg[5].DATAIN 101 | InpNum[6] => InputReg[6].DATAIN 102 | InpNum[7] => InputReg[7].DATAIN 103 | InpNum[8] => InputReg[8].DATAIN 104 | InpNum[9] => InputReg[9].DATAIN 105 | InpNum[10] => InputReg[10].DATAIN 106 | InpNum[11] => InputReg[11].DATAIN 107 | InpNum[12] => InputReg[12].DATAIN 108 | InpNum[13] => InputReg[13].DATAIN 109 | InpNum[14] => InputReg[14].DATAIN 110 | InpNum[15] => InputReg[15].DATAIN 111 | InpNum[16] => InputReg[16].DATAIN 112 | InpNum[17] => InputReg[17].DATAIN 113 | InpNum[18] => InputReg[18].DATAIN 114 | InpNum[19] => InputReg[19].DATAIN 115 | InpNum[20] => InputReg[20].DATAIN 116 | InpNum[21] => InputReg[21].DATAIN 117 | InpNum[22] => InputReg[22].DATAIN 118 | InpNum[23] => InputReg[23].DATAIN 119 | InpNum[24] => InputReg[24].DATAIN 120 | InpNum[25] => InputReg[25].DATAIN 121 | InpNum[26] => InputReg[26].DATAIN 122 | InpNum[27] => InputReg[27].DATAIN 123 | InpNum[28] => InputReg[28].DATAIN 124 | InpNum[29] => InputReg[29].DATAIN 125 | InpNum[30] => InputReg[30].DATAIN 126 | InpNum[31] => InputReg[31].DATAIN 127 | Result[0] << Sqrt[0].DB_MAX_OUTPUT_PORT_TYPE 128 | Result[1] << Sqrt[1].DB_MAX_OUTPUT_PORT_TYPE 129 | Result[2] << Sqrt[2].DB_MAX_OUTPUT_PORT_TYPE 130 | Result[3] << Sqrt[3].DB_MAX_OUTPUT_PORT_TYPE 131 | Result[4] << Sqrt[4].DB_MAX_OUTPUT_PORT_TYPE 132 | Result[5] << Sqrt[5].DB_MAX_OUTPUT_PORT_TYPE 133 | Result[6] << Sqrt[6].DB_MAX_OUTPUT_PORT_TYPE 134 | Result[7] << Sqrt[7].DB_MAX_OUTPUT_PORT_TYPE 135 | Result[8] << Sqrt[8].DB_MAX_OUTPUT_PORT_TYPE 136 | Result[9] << Sqrt[9].DB_MAX_OUTPUT_PORT_TYPE 137 | Result[10] << Sqrt[10].DB_MAX_OUTPUT_PORT_TYPE 138 | Result[11] << Sqrt[11].DB_MAX_OUTPUT_PORT_TYPE 139 | Result[12] << Sqrt[12].DB_MAX_OUTPUT_PORT_TYPE 140 | Result[13] << Sqrt[13].DB_MAX_OUTPUT_PORT_TYPE 141 | Result[14] << Sqrt[14].DB_MAX_OUTPUT_PORT_TYPE 142 | Result[15] << Sqrt[15].DB_MAX_OUTPUT_PORT_TYPE 143 | Result[16] << Sqrt[16].DB_MAX_OUTPUT_PORT_TYPE 144 | Result[17] << Sqrt[17].DB_MAX_OUTPUT_PORT_TYPE 145 | Result[18] << Sqrt[18].DB_MAX_OUTPUT_PORT_TYPE 146 | Result[19] << Sqrt[19].DB_MAX_OUTPUT_PORT_TYPE 147 | Result[20] << Sqrt[20].DB_MAX_OUTPUT_PORT_TYPE 148 | Result[21] << Sqrt[21].DB_MAX_OUTPUT_PORT_TYPE 149 | Result[22] << Sqrt[22].DB_MAX_OUTPUT_PORT_TYPE 150 | Result[23] << Sqrt[23].DB_MAX_OUTPUT_PORT_TYPE 151 | Stop << Stop~reg0.DB_MAX_OUTPUT_PORT_TYPE 152 | 153 | 154 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.map.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1572770681623 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572770681639 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 03 16:44:41 2019 " "Processing started: Sun Nov 03 16:44:41 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1572770681639 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1572770681639 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SqrtCORDIC -c SqrtCORDIC " "Command: quartus_map --read_settings_files=on --write_settings_files=off SqrtCORDIC -c SqrtCORDIC" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1572770681639 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1572770682655 ""} 5 | { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1572770682655 ""} 6 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sqrtcordic.v 1 1 " "Found 1 design units, including 1 entities, in source file sqrtcordic.v" { { "Info" "ISGN_ENTITY_NAME" "1 SqrtCORDIC " "Found entity 1: SqrtCORDIC" { } { { "SqrtCORDIC.v" "" { Text "C:/Users/UPNM/Desktop/SqrtCORDIC/SqrtCORDIC.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1572770691771 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1572770691771 ""} 7 | { "Info" "ISGN_START_ELABORATION_TOP" "SqrtCORDIC " "Elaborating entity \"SqrtCORDIC\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1572770691817 ""} 8 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "48 32 SqrtCORDIC.v(34) " "Verilog HDL assignment warning at SqrtCORDIC.v(34): truncated value with size 48 to match size of target (32)" { } { { "SqrtCORDIC.v" "" { Text "C:/Users/UPNM/Desktop/SqrtCORDIC/SqrtCORDIC.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1572770691864 "|SqrtCORDIC"} 9 | { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1572770692959 ""} 10 | { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1572770693647 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1572770693647 ""} 11 | { "Info" "ICUT_CUT_TM_SUMMARY" "213 " "Implemented 213 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "34 " "Implemented 34 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1572770694303 ""} { "Info" "ICUT_CUT_TM_OPINS" "25 " "Implemented 25 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1572770694303 ""} { "Info" "ICUT_CUT_TM_LCELLS" "153 " "Implemented 153 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1572770694303 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "1 " "Implemented 1 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 -1 1572770694303 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1572770694303 ""} 12 | { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5051 " "Peak virtual memory: 5051 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1572770694459 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 03 16:44:54 2019 " "Processing ended: Sun Nov 03 16:44:54 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1572770694459 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1572770694459 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1572770694459 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1572770694459 ""} 13 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.eda.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1572771065045 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 1991-2016 Altera Corporation. All rights reserved. " "Copyright (C) 1991-2016 Altera Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Altera Corporation's design tools, logic functions " "Your use of Altera Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic " "and other software and tools, and its AMPP partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Altera Program License " "to the terms and conditions of the Altera Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Altera Quartus Prime License Agreement, " "Subscription Agreement, the Altera Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Altera MegaCore Function License Agreement, or other " "the Altera MegaCore Function License Agreement, or other " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable license agreement, including, without limitation, " "applicable license agreement, including, without limitation, " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "that your use is for the sole purpose of programming logic " "that your use is for the sole purpose of programming logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "devices manufactured by Altera and sold by Altera or its " "devices manufactured by Altera and sold by Altera or its " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "authorized distributors. Please refer to the applicable " "authorized distributors. Please refer to the applicable " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement for further details. " "agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 03 16:51:04 2019 " "Processing started: Sun Nov 03 16:51:04 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1572771065045 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1572771065045 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=C:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim/ SqrtCORDIC -c SqrtCORDIC " "Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=C:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim/ SqrtCORDIC -c SqrtCORDIC" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1572771065060 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1572771065858 ""} 5 | { "Info" "IWSC_DONE_HDL_GENERATION" "SqrtCORDIC.vo C:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim// simulation " "Generated file SqrtCORDIC.vo in folder \"C:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1572771065920 ""} 6 | { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4934 " "Peak virtual memory: 4934 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1572771065998 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 03 16:51:05 2019 " "Processing ended: Sun Nov 03 16:51:05 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1572771065998 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1572771065998 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1572771065998 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1572771065998 ""} 7 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/prev_cmp_SqrtCORDIC.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1572749643651 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus Prime " "Running Quartus Prime Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572749643651 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 03 10:54:03 2019 " "Processing started: Sun Nov 03 10:54:03 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1572749643651 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1572749643651 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SqrtCORDIC -c SqrtCORDIC --analysis_and_elaboration " "Command: quartus_map --read_settings_files=on --write_settings_files=off SqrtCORDIC -c SqrtCORDIC --analysis_and_elaboration" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1572749643651 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1572749644103 ""} 5 | { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1572749644103 ""} 6 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sqrtcordic.v 1 1 " "Found 1 design units, including 1 entities, in source file sqrtcordic.v" { { "Info" "ISGN_ENTITY_NAME" "1 SqrtCORDIC " "Found entity 1: SqrtCORDIC" { } { { "SqrtCORDIC.v" "" { Text "C:/Users/UPNM/Desktop/SqrtCORDIC/SqrtCORDIC.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1572749654092 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1572749654092 ""} 7 | { "Info" "ISGN_START_ELABORATION_TOP" "SqrtCORDIC " "Elaborating entity \"SqrtCORDIC\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Design Software" 0 -1 1572749654125 ""} 8 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "48 32 SqrtCORDIC.v(43) " "Verilog HDL assignment warning at SqrtCORDIC.v(43): truncated value with size 48 to match size of target (32)" { } { { "SqrtCORDIC.v" "" { Text "C:/Users/UPNM/Desktop/SqrtCORDIC/SqrtCORDIC.v" 43 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1572749654127 "|SqrtCORDIC"} 9 | { "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Elaboration was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4987 " "Peak virtual memory: 4987 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1572749654362 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 03 10:54:14 2019 " "Processing ended: Sun Nov 03 10:54:14 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1572749654362 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1572749654362 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1572749654362 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1572749654362 ""} 10 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1572749656536 ""} 11 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572749656542 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 03 10:54:16 2019 " "Processing started: Sun Nov 03 10:54:16 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1572749656542 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1572749656542 ""} 12 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp SqrtCORDIC -c SqrtCORDIC --netlist_type=sgate " "Command: quartus_npp SqrtCORDIC -c SqrtCORDIC --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1572749656542 ""} 13 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1572749656776 ""} 14 | { "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4543 " "Peak virtual memory: 4543 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1572749656845 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 03 10:54:16 2019 " "Processing ended: Sun Nov 03 10:54:16 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1572749656845 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1572749656845 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1572749656845 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1572749656845 ""} 15 | -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.eda.rpt: -------------------------------------------------------------------------------- 1 | EDA Netlist Writer report for SqrtCORDIC 2 | Sun Nov 03 16:51:05 2019 3 | Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. EDA Netlist Writer Summary 11 | 3. Simulation Settings 12 | 4. Simulation Generated Files 13 | 5. EDA Netlist Writer Messages 14 | 15 | 16 | 17 | ---------------- 18 | ; Legal Notice ; 19 | ---------------- 20 | Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 21 | Your use of Altera Corporation's design tools, logic functions 22 | and other software and tools, and its AMPP partner logic 23 | functions, and any output files from any of the foregoing 24 | (including device programming or simulation files), and any 25 | associated documentation or information are expressly subject 26 | to the terms and conditions of the Altera Program License 27 | Subscription Agreement, the Altera Quartus Prime License Agreement, 28 | the Altera MegaCore Function License Agreement, or other 29 | applicable license agreement, including, without limitation, 30 | that your use is for the sole purpose of programming logic 31 | devices manufactured by Altera and sold by Altera or its 32 | authorized distributors. Please refer to the applicable 33 | agreement for further details. 34 | 35 | 36 | 37 | +-------------------------------------------------------------------+ 38 | ; EDA Netlist Writer Summary ; 39 | +---------------------------+---------------------------------------+ 40 | ; EDA Netlist Writer Status ; Successful - Sun Nov 03 16:51:05 2019 ; 41 | ; Revision Name ; SqrtCORDIC ; 42 | ; Top-level Entity Name ; SqrtCORDIC ; 43 | ; Family ; Cyclone V ; 44 | ; Simulation Files Creation ; Successful ; 45 | +---------------------------+---------------------------------------+ 46 | 47 | 48 | +-------------------------------------------------------------------------------------------------------------------------------+ 49 | ; Simulation Settings ; 50 | +---------------------------------------------------------------------------------------------------+---------------------------+ 51 | ; Option ; Setting ; 52 | +---------------------------------------------------------------------------------------------------+---------------------------+ 53 | ; Tool Name ; ModelSim-Altera (Verilog) ; 54 | ; Generate functional simulation netlist ; On ; 55 | ; Truncate long hierarchy paths ; Off ; 56 | ; Map illegal HDL characters ; Off ; 57 | ; Flatten buses into individual nodes ; Off ; 58 | ; Maintain hierarchy ; Off ; 59 | ; Bring out device-wide set/reset signals as ports ; Off ; 60 | ; Enable glitch filtering ; Off ; 61 | ; Do not write top level VHDL entity ; Off ; 62 | ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; 63 | ; Architecture name in VHDL output netlist ; structure ; 64 | ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; 65 | ; Generate third-party EDA tool command script for gate-level simulation ; Off ; 66 | +---------------------------------------------------------------------------------------------------+---------------------------+ 67 | 68 | 69 | +-----------------------------------------------------------------+ 70 | ; Simulation Generated Files ; 71 | +-----------------------------------------------------------------+ 72 | ; Generated Files ; 73 | +-----------------------------------------------------------------+ 74 | ; C:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim//SqrtCORDIC.vo ; 75 | +-----------------------------------------------------------------+ 76 | 77 | 78 | +-----------------------------+ 79 | ; EDA Netlist Writer Messages ; 80 | +-----------------------------+ 81 | Info: ******************************************************************* 82 | Info: Running Quartus Prime EDA Netlist Writer 83 | Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 84 | Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 85 | Info: Your use of Altera Corporation's design tools, logic functions 86 | Info: and other software and tools, and its AMPP partner logic 87 | Info: functions, and any output files from any of the foregoing 88 | Info: (including device programming or simulation files), and any 89 | Info: associated documentation or information are expressly subject 90 | Info: to the terms and conditions of the Altera Program License 91 | Info: Subscription Agreement, the Altera Quartus Prime License Agreement, 92 | Info: the Altera MegaCore Function License Agreement, or other 93 | Info: applicable license agreement, including, without limitation, 94 | Info: that your use is for the sole purpose of programming logic 95 | Info: devices manufactured by Altera and sold by Altera or its 96 | Info: authorized distributors. Please refer to the applicable 97 | Info: agreement for further details. 98 | Info: Processing started: Sun Nov 03 16:51:04 2019 99 | Info: Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=C:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim/ SqrtCORDIC -c SqrtCORDIC 100 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. 101 | Info (204019): Generated file SqrtCORDIC.vo in folder "C:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim//" for EDA simulation tool 102 | Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning 103 | Info: Peak virtual memory: 4934 megabytes 104 | Info: Processing ended: Sun Nov 03 16:51:05 2019 105 | Info: Elapsed time: 00:00:01 106 | Info: Total CPU time (on all processors): 00:00:01 107 | 108 | 109 | -------------------------------------------------------------------------------- /SqrtCORDIC/output_files/SqrtCORDIC.flow.rpt: -------------------------------------------------------------------------------- 1 | Flow report for SqrtCORDIC 2 | Sun Nov 03 16:51:05 2019 3 | Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Flow Summary 11 | 3. Flow Settings 12 | 4. Flow Non-Default Global Settings 13 | 5. Flow Elapsed Time 14 | 6. Flow OS Summary 15 | 7. Flow Log 16 | 8. Flow Messages 17 | 9. Flow Suppressed Messages 18 | 19 | 20 | 21 | ---------------- 22 | ; Legal Notice ; 23 | ---------------- 24 | Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 25 | Your use of Altera Corporation's design tools, logic functions 26 | and other software and tools, and its AMPP partner logic 27 | functions, and any output files from any of the foregoing 28 | (including device programming or simulation files), and any 29 | associated documentation or information are expressly subject 30 | to the terms and conditions of the Altera Program License 31 | Subscription Agreement, the Altera Quartus Prime License Agreement, 32 | the Altera MegaCore Function License Agreement, or other 33 | applicable license agreement, including, without limitation, 34 | that your use is for the sole purpose of programming logic 35 | devices manufactured by Altera and sold by Altera or its 36 | authorized distributors. Please refer to the applicable 37 | agreement for further details. 38 | 39 | 40 | 41 | +-------------------------------------------------------------------------------+ 42 | ; Flow Summary ; 43 | +---------------------------------+---------------------------------------------+ 44 | ; Flow Status ; Successful - Sun Nov 03 16:51:05 2019 ; 45 | ; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Lite Edition ; 46 | ; Revision Name ; SqrtCORDIC ; 47 | ; Top-level Entity Name ; SqrtCORDIC ; 48 | ; Family ; Cyclone V ; 49 | ; Device ; 5CGXFC7C7F23C8 ; 50 | ; Timing Models ; Final ; 51 | ; Logic utilization (in ALMs) ; 54 / 56,480 ( < 1 % ) ; 52 | ; Total registers ; 86 ; 53 | ; Total pins ; 59 / 268 ( 22 % ) ; 54 | ; Total virtual pins ; 0 ; 55 | ; Total block memory bits ; 0 / 7,024,640 ( 0 % ) ; 56 | ; Total DSP Blocks ; 1 / 156 ( < 1 % ) ; 57 | ; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ; 58 | ; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ; 59 | ; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ; 60 | ; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ; 61 | ; Total PLLs ; 0 / 13 ( 0 % ) ; 62 | ; Total DLLs ; 0 / 4 ( 0 % ) ; 63 | +---------------------------------+---------------------------------------------+ 64 | 65 | 66 | +-----------------------------------------+ 67 | ; Flow Settings ; 68 | +-------------------+---------------------+ 69 | ; Option ; Setting ; 70 | +-------------------+---------------------+ 71 | ; Start date & time ; 11/03/2019 16:44:42 ; 72 | ; Main task ; Compilation ; 73 | ; Revision Name ; SqrtCORDIC ; 74 | +-------------------+---------------------+ 75 | 76 | 77 | +----------------------------------------------------------------------------------------------------------------------+ 78 | ; Flow Non-Default Global Settings ; 79 | +-------------------------------------+---------------------------------+---------------+-------------+----------------+ 80 | ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; 81 | +-------------------------------------+---------------------------------+---------------+-------------+----------------+ 82 | ; COMPILER_SIGNATURE_ID ; 168202111031803.157277068215532 ; -- ; -- ; -- ; 83 | ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; 84 | ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; 85 | ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; 86 | ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; 87 | ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; 88 | ; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; 89 | ; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; 90 | ; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; 91 | ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; 92 | +-------------------------------------+---------------------------------+---------------+-------------+----------------+ 93 | 94 | 95 | +-------------------------------------------------------------------------------------------------------------------------------+ 96 | ; Flow Elapsed Time ; 97 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 98 | ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; 99 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 100 | ; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 5051 MB ; 00:00:25 ; 101 | ; Fitter ; 00:00:47 ; 1.1 ; 6941 MB ; 00:01:25 ; 102 | ; Assembler ; 00:00:10 ; 1.0 ; 5038 MB ; 00:00:08 ; 103 | ; TimeQuest Timing Analyzer ; 00:00:09 ; 1.1 ; 5426 MB ; 00:00:08 ; 104 | ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4955 MB ; 00:00:01 ; 105 | ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4929 MB ; 00:00:01 ; 106 | ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4934 MB ; 00:00:01 ; 107 | ; Total ; 00:01:21 ; -- ; -- ; 00:02:09 ; 108 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 109 | 110 | 111 | +----------------------------------------------------------------------------------------+ 112 | ; Flow OS Summary ; 113 | +---------------------------+------------------+-----------+------------+----------------+ 114 | ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; 115 | +---------------------------+------------------+-----------+------------+----------------+ 116 | ; Analysis & Synthesis ; DESKTOP-DC6OMNL ; Windows 8 ; 6.2 ; x86_64 ; 117 | ; Fitter ; DESKTOP-DC6OMNL ; Windows 8 ; 6.2 ; x86_64 ; 118 | ; Assembler ; DESKTOP-DC6OMNL ; Windows 8 ; 6.2 ; x86_64 ; 119 | ; TimeQuest Timing Analyzer ; DESKTOP-DC6OMNL ; Windows 8 ; 6.2 ; x86_64 ; 120 | ; EDA Netlist Writer ; DESKTOP-DC6OMNL ; Windows 8 ; 6.2 ; x86_64 ; 121 | ; EDA Netlist Writer ; DESKTOP-DC6OMNL ; Windows 8 ; 6.2 ; x86_64 ; 122 | ; EDA Netlist Writer ; DESKTOP-DC6OMNL ; Windows 8 ; 6.2 ; x86_64 ; 123 | +---------------------------+------------------+-----------+------------+----------------+ 124 | 125 | 126 | ------------ 127 | ; Flow Log ; 128 | ------------ 129 | quartus_map --read_settings_files=on --write_settings_files=off SqrtCORDIC -c SqrtCORDIC 130 | quartus_fit --read_settings_files=off --write_settings_files=off SqrtCORDIC -c SqrtCORDIC 131 | quartus_asm --read_settings_files=off --write_settings_files=off SqrtCORDIC -c SqrtCORDIC 132 | quartus_sta SqrtCORDIC -c SqrtCORDIC 133 | quartus_eda --read_settings_files=off --write_settings_files=off SqrtCORDIC -c SqrtCORDIC 134 | quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off SqrtCORDIC -c SqrtCORDIC --vector_source=C:/Users/UPNM/Desktop/SqrtCORDIC/Waveform.vwf --testbench_file=C:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim/Waveform.vwf.vt 135 | quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=C:/Users/UPNM/Desktop/SqrtCORDIC/simulation/qsim/ SqrtCORDIC -c SqrtCORDIC 136 | 137 | 138 | 139 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.fit.qmsg: -------------------------------------------------------------------------------- 1 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1572770697834 ""} 2 | { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1572770697834 ""} 3 | { "Info" "IMPP_MPP_USER_DEVICE" "SqrtCORDIC 5CGXFC7C7F23C8 " "Selected device 5CGXFC7C7F23C8 for design \"SqrtCORDIC\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1572770697834 ""} 4 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1572770697881 ""} 5 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1572770697881 ""} 6 | { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1572770698475 ""} 7 | { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1572770698522 ""} 8 | { "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1572770699070 ""} 9 | { "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "59 59 " "No exact pin location assignment(s) for 59 pins of 59 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1572770699273 ""} 10 | { "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1572770707353 ""} 11 | { "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clk~inputCLKENA0 6 global CLKCTRL_G10 " "clk~inputCLKENA0 with 6 fanout uses global clock CLKCTRL_G10" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1572770707635 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1572770707635 ""} 12 | { "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1572770707635 ""} 13 | { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1572770707682 ""} 14 | { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1572770707682 ""} 15 | { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1572770707682 ""} 16 | { "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1572770707682 ""} 17 | { "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1572770707682 ""} 18 | { "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1572770707682 ""} 19 | { "Critical Warning" "WSTA_SDC_NOT_FOUND" "SqrtCORDIC.sdc " "Synopsys Design Constraints File file not found: 'SqrtCORDIC.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1572770708916 ""} 20 | { "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1572770708916 ""} 21 | { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1572770708916 ""} 22 | { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1572770708916 ""} 23 | { "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1572770708916 ""} 24 | { "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1572770708994 ""} 25 | { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1572770708994 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1572770708994 ""} 26 | { "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1572770709150 ""} 27 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1572770715010 ""} 28 | { "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1572770715229 ""} 29 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:03 " "Fitter placement preparation operations ending: elapsed time is 00:00:03" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1572770717964 ""} 30 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1572770719495 ""} 31 | { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1572770724402 ""} 32 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:06 " "Fitter placement operations ending: elapsed time is 00:00:06" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1572770724402 ""} 33 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1572770726106 ""} 34 | { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X78_Y23 X89_Y34 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y23 to location X89_Y34" { } { { "loc" "" { Generic "C:/Users/UPNM/Desktop/SqrtCORDIC/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y23 to location X89_Y34"} { { 12 { 0 ""} 78 23 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1572770731893 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1572770731893 ""} 35 | { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1572770734776 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1572770734776 ""} 36 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1572770734776 ""} 37 | { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 1.31 " "Total time spent on timing analysis during the Fitter is 1.31 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1572770737481 ""} 38 | { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1572770737527 ""} 39 | { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1572770738043 ""} 40 | { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1572770738043 ""} 41 | { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1572770739043 ""} 42 | { "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:05 " "Fitter post-fit operations ending: elapsed time is 00:00:05" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1572770742140 ""} 43 | { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/UPNM/Desktop/SqrtCORDIC/output_files/SqrtCORDIC.fit.smsg " "Generated suppressed messages file C:/Users/UPNM/Desktop/SqrtCORDIC/output_files/SqrtCORDIC.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1572770742437 ""} 44 | { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6941 " "Peak virtual memory: 6941 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1572770743375 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 03 16:45:43 2019 " "Processing ended: Sun Nov 03 16:45:43 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1572770743375 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:48 " "Elapsed time: 00:00:48" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1572770743375 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:26 " "Total CPU time (on all processors): 00:01:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1572770743375 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1572770743375 ""} 45 | -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/qsim/SqrtCORDIC_modelsim.xrf: -------------------------------------------------------------------------------- 1 | vendor_name = ModelSim 2 | source_file = 1, C:/Users/UPNM/Desktop/SqrtCORDIC/SqrtCORDIC.v 3 | source_file = 1, C:/Users/UPNM/Desktop/SqrtCORDIC/Waveform.vwf 4 | source_file = 1, C:/Users/UPNM/Desktop/SqrtCORDIC/db/SqrtCORDIC.cbx.xml 5 | design_name = SqrtCORDIC 6 | instance = comp, \Result[0]~output , Result[0]~output, SqrtCORDIC, 1 7 | instance = comp, \Result[1]~output , Result[1]~output, SqrtCORDIC, 1 8 | instance = comp, \Result[2]~output , Result[2]~output, SqrtCORDIC, 1 9 | instance = comp, \Result[3]~output , Result[3]~output, SqrtCORDIC, 1 10 | instance = comp, \Result[4]~output , Result[4]~output, SqrtCORDIC, 1 11 | instance = comp, \Result[5]~output , Result[5]~output, SqrtCORDIC, 1 12 | instance = comp, \Result[6]~output , Result[6]~output, SqrtCORDIC, 1 13 | instance = comp, \Result[7]~output , Result[7]~output, SqrtCORDIC, 1 14 | instance = comp, \Result[8]~output , Result[8]~output, SqrtCORDIC, 1 15 | instance = comp, \Result[9]~output , Result[9]~output, SqrtCORDIC, 1 16 | instance = comp, \Result[10]~output , Result[10]~output, SqrtCORDIC, 1 17 | instance = comp, \Result[11]~output , Result[11]~output, SqrtCORDIC, 1 18 | instance = comp, \Result[12]~output , Result[12]~output, SqrtCORDIC, 1 19 | instance = comp, \Result[13]~output , Result[13]~output, SqrtCORDIC, 1 20 | instance = comp, \Result[14]~output , Result[14]~output, SqrtCORDIC, 1 21 | instance = comp, \Result[15]~output , Result[15]~output, SqrtCORDIC, 1 22 | instance = comp, \Result[16]~output , Result[16]~output, SqrtCORDIC, 1 23 | instance = comp, \Result[17]~output , Result[17]~output, SqrtCORDIC, 1 24 | instance = comp, \Result[18]~output , Result[18]~output, SqrtCORDIC, 1 25 | instance = comp, \Result[19]~output , Result[19]~output, SqrtCORDIC, 1 26 | instance = comp, \Result[20]~output , Result[20]~output, SqrtCORDIC, 1 27 | instance = comp, \Result[21]~output , Result[21]~output, SqrtCORDIC, 1 28 | instance = comp, \Result[22]~output , Result[22]~output, SqrtCORDIC, 1 29 | instance = comp, \Result[23]~output , Result[23]~output, SqrtCORDIC, 1 30 | instance = comp, \Stop~output , Stop~output, SqrtCORDIC, 1 31 | instance = comp, \clk~input , clk~input, SqrtCORDIC, 1 32 | instance = comp, \clk~inputCLKENA0 , clk~inputCLKENA0, SqrtCORDIC, 1 33 | instance = comp, \Start~input , Start~input, SqrtCORDIC, 1 34 | instance = comp, \ctr[4]~0 , ctr[4]~0, SqrtCORDIC, 1 35 | instance = comp, \ctr[4] , ctr[4], SqrtCORDIC, 1 36 | instance = comp, \ctr[3]~1 , ctr[3]~1, SqrtCORDIC, 1 37 | instance = comp, \ctr[3] , ctr[3], SqrtCORDIC, 1 38 | instance = comp, \ctr[2]~2 , ctr[2]~2, SqrtCORDIC, 1 39 | instance = comp, \ctr[2] , ctr[2], SqrtCORDIC, 1 40 | instance = comp, \ctr[0]~3 , ctr[0]~3, SqrtCORDIC, 1 41 | instance = comp, \ctr[0] , ctr[0], SqrtCORDIC, 1 42 | instance = comp, \ctr[1]~4 , ctr[1]~4, SqrtCORDIC, 1 43 | instance = comp, \ctr[1] , ctr[1], SqrtCORDIC, 1 44 | instance = comp, \LessThan1~0 , LessThan1~0, SqrtCORDIC, 1 45 | instance = comp, \Stop~reg0 , Stop~reg0, SqrtCORDIC, 1 46 | instance = comp, \OneShReg[23] , OneShReg[23], SqrtCORDIC, 1 47 | instance = comp, \OneShReg[22] , OneShReg[22], SqrtCORDIC, 1 48 | instance = comp, \OneShReg[21] , OneShReg[21], SqrtCORDIC, 1 49 | instance = comp, \OneShReg[20] , OneShReg[20], SqrtCORDIC, 1 50 | instance = comp, \OneShReg[19]~feeder , OneShReg[19]~feeder, SqrtCORDIC, 1 51 | instance = comp, \OneShReg[19] , OneShReg[19], SqrtCORDIC, 1 52 | instance = comp, \OneShReg[18]~feeder , OneShReg[18]~feeder, SqrtCORDIC, 1 53 | instance = comp, \OneShReg[18] , OneShReg[18], SqrtCORDIC, 1 54 | instance = comp, \OneShReg[17] , OneShReg[17], SqrtCORDIC, 1 55 | instance = comp, \OneShReg[16] , OneShReg[16], SqrtCORDIC, 1 56 | instance = comp, \OneShReg[15] , OneShReg[15], SqrtCORDIC, 1 57 | instance = comp, \OneShReg[14] , OneShReg[14], SqrtCORDIC, 1 58 | instance = comp, \OneShReg[13] , OneShReg[13], SqrtCORDIC, 1 59 | instance = comp, \OneShReg[12]~feeder , OneShReg[12]~feeder, SqrtCORDIC, 1 60 | instance = comp, \OneShReg[12] , OneShReg[12], SqrtCORDIC, 1 61 | instance = comp, \OneShReg[11] , OneShReg[11], SqrtCORDIC, 1 62 | instance = comp, \OneShReg[10] , OneShReg[10], SqrtCORDIC, 1 63 | instance = comp, \OneShReg[9] , OneShReg[9], SqrtCORDIC, 1 64 | instance = comp, \OneShReg[8]~feeder , OneShReg[8]~feeder, SqrtCORDIC, 1 65 | instance = comp, \OneShReg[8] , OneShReg[8], SqrtCORDIC, 1 66 | instance = comp, \OneShReg[7]~feeder , OneShReg[7]~feeder, SqrtCORDIC, 1 67 | instance = comp, \OneShReg[7] , OneShReg[7], SqrtCORDIC, 1 68 | instance = comp, \OneShReg[6]~feeder , OneShReg[6]~feeder, SqrtCORDIC, 1 69 | instance = comp, \OneShReg[6] , OneShReg[6], SqrtCORDIC, 1 70 | instance = comp, \OneShReg[5] , OneShReg[5], SqrtCORDIC, 1 71 | instance = comp, \OneShReg[4]~feeder , OneShReg[4]~feeder, SqrtCORDIC, 1 72 | instance = comp, \OneShReg[4] , OneShReg[4], SqrtCORDIC, 1 73 | instance = comp, \OneShReg[3] , OneShReg[3], SqrtCORDIC, 1 74 | instance = comp, \OneShReg[2] , OneShReg[2], SqrtCORDIC, 1 75 | instance = comp, \OneShReg[1] , OneShReg[1], SqrtCORDIC, 1 76 | instance = comp, \OneShReg[0] , OneShReg[0], SqrtCORDIC, 1 77 | instance = comp, \Add0~1 , Add0~1, SqrtCORDIC, 1 78 | instance = comp, \InpNum[30]~input , InpNum[30]~input, SqrtCORDIC, 1 79 | instance = comp, \InputReg[30] , InputReg[30], SqrtCORDIC, 1 80 | instance = comp, \InpNum[31]~input , InpNum[31]~input, SqrtCORDIC, 1 81 | instance = comp, \InputReg[31] , InputReg[31], SqrtCORDIC, 1 82 | instance = comp, \Sqrt[1] , Sqrt[1], SqrtCORDIC, 1 83 | instance = comp, \Add0~5 , Add0~5, SqrtCORDIC, 1 84 | instance = comp, \Sqrt[2] , Sqrt[2], SqrtCORDIC, 1 85 | instance = comp, \Add0~9 , Add0~9, SqrtCORDIC, 1 86 | instance = comp, \Sqrt[3] , Sqrt[3], SqrtCORDIC, 1 87 | instance = comp, \Add0~13 , Add0~13, SqrtCORDIC, 1 88 | instance = comp, \Sqrt[4] , Sqrt[4], SqrtCORDIC, 1 89 | instance = comp, \Add0~17 , Add0~17, SqrtCORDIC, 1 90 | instance = comp, \Sqrt[5] , Sqrt[5], SqrtCORDIC, 1 91 | instance = comp, \Add0~21 , Add0~21, SqrtCORDIC, 1 92 | instance = comp, \Sqrt[6] , Sqrt[6], SqrtCORDIC, 1 93 | instance = comp, \Add0~25 , Add0~25, SqrtCORDIC, 1 94 | instance = comp, \Sqrt[7] , Sqrt[7], SqrtCORDIC, 1 95 | instance = comp, \Add0~29 , Add0~29, SqrtCORDIC, 1 96 | instance = comp, \Sqrt[8] , Sqrt[8], SqrtCORDIC, 1 97 | instance = comp, \Add0~33 , Add0~33, SqrtCORDIC, 1 98 | instance = comp, \Sqrt[9] , Sqrt[9], SqrtCORDIC, 1 99 | instance = comp, \Add0~37 , Add0~37, SqrtCORDIC, 1 100 | instance = comp, \Sqrt[10] , Sqrt[10], SqrtCORDIC, 1 101 | instance = comp, \Add0~41 , Add0~41, SqrtCORDIC, 1 102 | instance = comp, \Sqrt[11] , Sqrt[11], SqrtCORDIC, 1 103 | instance = comp, \Add0~45 , Add0~45, SqrtCORDIC, 1 104 | instance = comp, \Sqrt[12] , Sqrt[12], SqrtCORDIC, 1 105 | instance = comp, \Add0~49 , Add0~49, SqrtCORDIC, 1 106 | instance = comp, \Sqrt[13] , Sqrt[13], SqrtCORDIC, 1 107 | instance = comp, \Add0~53 , Add0~53, SqrtCORDIC, 1 108 | instance = comp, \Sqrt[14] , Sqrt[14], SqrtCORDIC, 1 109 | instance = comp, \Add0~57 , Add0~57, SqrtCORDIC, 1 110 | instance = comp, \Sqrt[15] , Sqrt[15], SqrtCORDIC, 1 111 | instance = comp, \Add0~61 , Add0~61, SqrtCORDIC, 1 112 | instance = comp, \Sqrt[16] , Sqrt[16], SqrtCORDIC, 1 113 | instance = comp, \Add0~65 , Add0~65, SqrtCORDIC, 1 114 | instance = comp, \Sqrt[17] , Sqrt[17], SqrtCORDIC, 1 115 | instance = comp, \Add0~69 , Add0~69, SqrtCORDIC, 1 116 | instance = comp, \Sqrt[18] , Sqrt[18], SqrtCORDIC, 1 117 | instance = comp, \Add0~73 , Add0~73, SqrtCORDIC, 1 118 | instance = comp, \Sqrt[19] , Sqrt[19], SqrtCORDIC, 1 119 | instance = comp, \Add0~77 , Add0~77, SqrtCORDIC, 1 120 | instance = comp, \Sqrt[20] , Sqrt[20], SqrtCORDIC, 1 121 | instance = comp, \Add0~81 , Add0~81, SqrtCORDIC, 1 122 | instance = comp, \Sqrt[21] , Sqrt[21], SqrtCORDIC, 1 123 | instance = comp, \Add0~85 , Add0~85, SqrtCORDIC, 1 124 | instance = comp, \Sqrt[22] , Sqrt[22], SqrtCORDIC, 1 125 | instance = comp, \Add0~89 , Add0~89, SqrtCORDIC, 1 126 | instance = comp, \Sqrt[23] , Sqrt[23], SqrtCORDIC, 1 127 | instance = comp, \Add0~93 , Add0~93, SqrtCORDIC, 1 128 | instance = comp, \Mult0~8 , Mult0~8, SqrtCORDIC, 1 129 | instance = comp, \InpNum[29]~input , InpNum[29]~input, SqrtCORDIC, 1 130 | instance = comp, \InputReg[29] , InputReg[29], SqrtCORDIC, 1 131 | instance = comp, \Sqrt[0]~1 , Sqrt[0]~1, SqrtCORDIC, 1 132 | instance = comp, \Sqrt[0]~2 , Sqrt[0]~2, SqrtCORDIC, 1 133 | instance = comp, \InpNum[25]~input , InpNum[25]~input, SqrtCORDIC, 1 134 | instance = comp, \InputReg[25] , InputReg[25], SqrtCORDIC, 1 135 | instance = comp, \InpNum[22]~input , InpNum[22]~input, SqrtCORDIC, 1 136 | instance = comp, \InputReg[22] , InputReg[22], SqrtCORDIC, 1 137 | instance = comp, \LessThan0~27 , LessThan0~27, SqrtCORDIC, 1 138 | instance = comp, \InpNum[24]~input , InpNum[24]~input, SqrtCORDIC, 1 139 | instance = comp, \InputReg[24] , InputReg[24], SqrtCORDIC, 1 140 | instance = comp, \LessThan0~25 , LessThan0~25, SqrtCORDIC, 1 141 | instance = comp, \InpNum[23]~input , InpNum[23]~input, SqrtCORDIC, 1 142 | instance = comp, \InputReg[23] , InputReg[23], SqrtCORDIC, 1 143 | instance = comp, \LessThan0~26 , LessThan0~26, SqrtCORDIC, 1 144 | instance = comp, \InpNum[26]~input , InpNum[26]~input, SqrtCORDIC, 1 145 | instance = comp, \InputReg[26] , InputReg[26], SqrtCORDIC, 1 146 | instance = comp, \InpNum[28]~input , InpNum[28]~input, SqrtCORDIC, 1 147 | instance = comp, \InputReg[28] , InputReg[28], SqrtCORDIC, 1 148 | instance = comp, \InpNum[27]~input , InpNum[27]~input, SqrtCORDIC, 1 149 | instance = comp, \InputReg[27] , InputReg[27], SqrtCORDIC, 1 150 | instance = comp, \LessThan0~24 , LessThan0~24, SqrtCORDIC, 1 151 | instance = comp, \LessThan0~28 , LessThan0~28, SqrtCORDIC, 1 152 | instance = comp, \LessThan0~30 , LessThan0~30, SqrtCORDIC, 1 153 | instance = comp, \LessThan0~31 , LessThan0~31, SqrtCORDIC, 1 154 | instance = comp, \LessThan0~29 , LessThan0~29, SqrtCORDIC, 1 155 | instance = comp, \LessThan0~32 , LessThan0~32, SqrtCORDIC, 1 156 | instance = comp, \LessThan0~33 , LessThan0~33, SqrtCORDIC, 1 157 | instance = comp, \Sqrt[0]~0 , Sqrt[0]~0, SqrtCORDIC, 1 158 | instance = comp, \InpNum[16]~input , InpNum[16]~input, SqrtCORDIC, 1 159 | instance = comp, \InputReg[16] , InputReg[16], SqrtCORDIC, 1 160 | instance = comp, \InpNum[15]~input , InpNum[15]~input, SqrtCORDIC, 1 161 | instance = comp, \InputReg[15] , InputReg[15], SqrtCORDIC, 1 162 | instance = comp, \InpNum[18]~input , InpNum[18]~input, SqrtCORDIC, 1 163 | instance = comp, \InputReg[18] , InputReg[18], SqrtCORDIC, 1 164 | instance = comp, \InpNum[17]~input , InpNum[17]~input, SqrtCORDIC, 1 165 | instance = comp, \InputReg[17] , InputReg[17], SqrtCORDIC, 1 166 | instance = comp, \LessThan0~15 , LessThan0~15, SqrtCORDIC, 1 167 | instance = comp, \InpNum[19]~input , InpNum[19]~input, SqrtCORDIC, 1 168 | instance = comp, \InputReg[19] , InputReg[19], SqrtCORDIC, 1 169 | instance = comp, \InpNum[21]~input , InpNum[21]~input, SqrtCORDIC, 1 170 | instance = comp, \InputReg[21] , InputReg[21], SqrtCORDIC, 1 171 | instance = comp, \InpNum[20]~input , InpNum[20]~input, SqrtCORDIC, 1 172 | instance = comp, \InputReg[20] , InputReg[20], SqrtCORDIC, 1 173 | instance = comp, \LessThan0~14 , LessThan0~14, SqrtCORDIC, 1 174 | instance = comp, \LessThan0~20 , LessThan0~20, SqrtCORDIC, 1 175 | instance = comp, \LessThan0~21 , LessThan0~21, SqrtCORDIC, 1 176 | instance = comp, \LessThan0~22 , LessThan0~22, SqrtCORDIC, 1 177 | instance = comp, \LessThan0~23 , LessThan0~23, SqrtCORDIC, 1 178 | instance = comp, \InpNum[9]~input , InpNum[9]~input, SqrtCORDIC, 1 179 | instance = comp, \InputReg[9] , InputReg[9], SqrtCORDIC, 1 180 | instance = comp, \InpNum[12]~input , InpNum[12]~input, SqrtCORDIC, 1 181 | instance = comp, \InputReg[12] , InputReg[12], SqrtCORDIC, 1 182 | instance = comp, \InpNum[11]~input , InpNum[11]~input, SqrtCORDIC, 1 183 | instance = comp, \InputReg[11] , InputReg[11], SqrtCORDIC, 1 184 | instance = comp, \InpNum[8]~input , InpNum[8]~input, SqrtCORDIC, 1 185 | instance = comp, \InputReg[8] , InputReg[8], SqrtCORDIC, 1 186 | instance = comp, \InpNum[10]~input , InpNum[10]~input, SqrtCORDIC, 1 187 | instance = comp, \InputReg[10] , InputReg[10], SqrtCORDIC, 1 188 | instance = comp, \LessThan0~36 , LessThan0~36, SqrtCORDIC, 1 189 | instance = comp, \InpNum[13]~input , InpNum[13]~input, SqrtCORDIC, 1 190 | instance = comp, \InputReg[13] , InputReg[13], SqrtCORDIC, 1 191 | instance = comp, \InpNum[14]~input , InpNum[14]~input, SqrtCORDIC, 1 192 | instance = comp, \InputReg[14] , InputReg[14], SqrtCORDIC, 1 193 | instance = comp, \LessThan0~37 , LessThan0~37, SqrtCORDIC, 1 194 | instance = comp, \LessThan0~9 , LessThan0~9, SqrtCORDIC, 1 195 | instance = comp, \LessThan0~16 , LessThan0~16, SqrtCORDIC, 1 196 | instance = comp, \LessThan0~17 , LessThan0~17, SqrtCORDIC, 1 197 | instance = comp, \LessThan0~18 , LessThan0~18, SqrtCORDIC, 1 198 | instance = comp, \LessThan0~7 , LessThan0~7, SqrtCORDIC, 1 199 | instance = comp, \LessThan0~8 , LessThan0~8, SqrtCORDIC, 1 200 | instance = comp, \LessThan0~12 , LessThan0~12, SqrtCORDIC, 1 201 | instance = comp, \LessThan0~6 , LessThan0~6, SqrtCORDIC, 1 202 | instance = comp, \LessThan0~13 , LessThan0~13, SqrtCORDIC, 1 203 | instance = comp, \InpNum[4]~input , InpNum[4]~input, SqrtCORDIC, 1 204 | instance = comp, \InputReg[4] , InputReg[4], SqrtCORDIC, 1 205 | instance = comp, \InpNum[6]~input , InpNum[6]~input, SqrtCORDIC, 1 206 | instance = comp, \InputReg[6] , InputReg[6], SqrtCORDIC, 1 207 | instance = comp, \InpNum[7]~input , InpNum[7]~input, SqrtCORDIC, 1 208 | instance = comp, \InputReg[7]~feeder , InputReg[7]~feeder, SqrtCORDIC, 1 209 | instance = comp, \InputReg[7] , InputReg[7], SqrtCORDIC, 1 210 | instance = comp, \LessThan0~4 , LessThan0~4, SqrtCORDIC, 1 211 | instance = comp, \InpNum[5]~input , InpNum[5]~input, SqrtCORDIC, 1 212 | instance = comp, \InputReg[5] , InputReg[5], SqrtCORDIC, 1 213 | instance = comp, \LessThan0~0 , LessThan0~0, SqrtCORDIC, 1 214 | instance = comp, \LessThan0~5 , LessThan0~5, SqrtCORDIC, 1 215 | instance = comp, \LessThan0~10 , LessThan0~10, SqrtCORDIC, 1 216 | instance = comp, \LessThan0~11 , LessThan0~11, SqrtCORDIC, 1 217 | instance = comp, \LessThan0~34 , LessThan0~34, SqrtCORDIC, 1 218 | instance = comp, \InpNum[2]~input , InpNum[2]~input, SqrtCORDIC, 1 219 | instance = comp, \InputReg[2] , InputReg[2], SqrtCORDIC, 1 220 | instance = comp, \InpNum[3]~input , InpNum[3]~input, SqrtCORDIC, 1 221 | instance = comp, \InputReg[3] , InputReg[3], SqrtCORDIC, 1 222 | instance = comp, \LessThan0~1 , LessThan0~1, SqrtCORDIC, 1 223 | instance = comp, \LessThan0~2 , LessThan0~2, SqrtCORDIC, 1 224 | instance = comp, \InpNum[1]~input , InpNum[1]~input, SqrtCORDIC, 1 225 | instance = comp, \InputReg[1] , InputReg[1], SqrtCORDIC, 1 226 | instance = comp, \InpNum[0]~input , InpNum[0]~input, SqrtCORDIC, 1 227 | instance = comp, \InputReg[0] , InputReg[0], SqrtCORDIC, 1 228 | instance = comp, \LessThan0~35 , LessThan0~35, SqrtCORDIC, 1 229 | instance = comp, \LessThan0~3 , LessThan0~3, SqrtCORDIC, 1 230 | instance = comp, \LessThan0~19 , LessThan0~19, SqrtCORDIC, 1 231 | instance = comp, \Sqrt[0]~3 , Sqrt[0]~3, SqrtCORDIC, 1 232 | instance = comp, \Sqrt[0] , Sqrt[0], SqrtCORDIC, 1 233 | instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, SqrtCORDIC, 1 234 | -------------------------------------------------------------------------------- /SqrtCORDIC/simulation/modelsim/SqrtCORDIC_modelsim.xrf: -------------------------------------------------------------------------------- 1 | vendor_name = ModelSim 2 | source_file = 1, C:/Users/UPNM/Desktop/SqrtCORDIC/SqrtCORDIC.v 3 | source_file = 1, C:/Users/UPNM/Desktop/SqrtCORDIC/Waveform.vwf 4 | source_file = 1, C:/Users/UPNM/Desktop/SqrtCORDIC/db/SqrtCORDIC.cbx.xml 5 | design_name = SqrtCORDIC 6 | instance = comp, \Result[0]~output , Result[0]~output, SqrtCORDIC, 1 7 | instance = comp, \Result[1]~output , Result[1]~output, SqrtCORDIC, 1 8 | instance = comp, \Result[2]~output , Result[2]~output, SqrtCORDIC, 1 9 | instance = comp, \Result[3]~output , Result[3]~output, SqrtCORDIC, 1 10 | instance = comp, \Result[4]~output , Result[4]~output, SqrtCORDIC, 1 11 | instance = comp, \Result[5]~output , Result[5]~output, SqrtCORDIC, 1 12 | instance = comp, \Result[6]~output , Result[6]~output, SqrtCORDIC, 1 13 | instance = comp, \Result[7]~output , Result[7]~output, SqrtCORDIC, 1 14 | instance = comp, \Result[8]~output , Result[8]~output, SqrtCORDIC, 1 15 | instance = comp, \Result[9]~output , Result[9]~output, SqrtCORDIC, 1 16 | instance = comp, \Result[10]~output , Result[10]~output, SqrtCORDIC, 1 17 | instance = comp, \Result[11]~output , Result[11]~output, SqrtCORDIC, 1 18 | instance = comp, \Result[12]~output , Result[12]~output, SqrtCORDIC, 1 19 | instance = comp, \Result[13]~output , Result[13]~output, SqrtCORDIC, 1 20 | instance = comp, \Result[14]~output , Result[14]~output, SqrtCORDIC, 1 21 | instance = comp, \Result[15]~output , Result[15]~output, SqrtCORDIC, 1 22 | instance = comp, \Result[16]~output , Result[16]~output, SqrtCORDIC, 1 23 | instance = comp, \Result[17]~output , Result[17]~output, SqrtCORDIC, 1 24 | instance = comp, \Result[18]~output , Result[18]~output, SqrtCORDIC, 1 25 | instance = comp, \Result[19]~output , Result[19]~output, SqrtCORDIC, 1 26 | instance = comp, \Result[20]~output , Result[20]~output, SqrtCORDIC, 1 27 | instance = comp, \Result[21]~output , Result[21]~output, SqrtCORDIC, 1 28 | instance = comp, \Result[22]~output , Result[22]~output, SqrtCORDIC, 1 29 | instance = comp, \Result[23]~output , Result[23]~output, SqrtCORDIC, 1 30 | instance = comp, \Stop~output , Stop~output, SqrtCORDIC, 1 31 | instance = comp, \clk~input , clk~input, SqrtCORDIC, 1 32 | instance = comp, \clk~inputCLKENA0 , clk~inputCLKENA0, SqrtCORDIC, 1 33 | instance = comp, \Start~input , Start~input, SqrtCORDIC, 1 34 | instance = comp, \ctr[4]~0 , ctr[4]~0, SqrtCORDIC, 1 35 | instance = comp, \ctr[4] , ctr[4], SqrtCORDIC, 1 36 | instance = comp, \ctr[3]~1 , ctr[3]~1, SqrtCORDIC, 1 37 | instance = comp, \ctr[3] , ctr[3], SqrtCORDIC, 1 38 | instance = comp, \ctr[2]~2 , ctr[2]~2, SqrtCORDIC, 1 39 | instance = comp, \ctr[2] , ctr[2], SqrtCORDIC, 1 40 | instance = comp, \ctr[0]~3 , ctr[0]~3, SqrtCORDIC, 1 41 | instance = comp, \ctr[0] , ctr[0], SqrtCORDIC, 1 42 | instance = comp, \ctr[1]~4 , ctr[1]~4, SqrtCORDIC, 1 43 | instance = comp, \ctr[1] , ctr[1], SqrtCORDIC, 1 44 | instance = comp, \LessThan1~0 , LessThan1~0, SqrtCORDIC, 1 45 | instance = comp, \Stop~reg0 , Stop~reg0, SqrtCORDIC, 1 46 | instance = comp, \OneShReg[23] , OneShReg[23], SqrtCORDIC, 1 47 | instance = comp, \OneShReg[22] , OneShReg[22], SqrtCORDIC, 1 48 | instance = comp, \OneShReg[21] , OneShReg[21], SqrtCORDIC, 1 49 | instance = comp, \OneShReg[20] , OneShReg[20], SqrtCORDIC, 1 50 | instance = comp, \OneShReg[19]~feeder , OneShReg[19]~feeder, SqrtCORDIC, 1 51 | instance = comp, \OneShReg[19] , OneShReg[19], SqrtCORDIC, 1 52 | instance = comp, \OneShReg[18]~feeder , OneShReg[18]~feeder, SqrtCORDIC, 1 53 | instance = comp, \OneShReg[18] , OneShReg[18], SqrtCORDIC, 1 54 | instance = comp, \OneShReg[17] , OneShReg[17], SqrtCORDIC, 1 55 | instance = comp, \OneShReg[16] , OneShReg[16], SqrtCORDIC, 1 56 | instance = comp, \OneShReg[15] , OneShReg[15], SqrtCORDIC, 1 57 | instance = comp, \OneShReg[14] , OneShReg[14], SqrtCORDIC, 1 58 | instance = comp, \OneShReg[13] , OneShReg[13], SqrtCORDIC, 1 59 | instance = comp, \OneShReg[12]~feeder , OneShReg[12]~feeder, SqrtCORDIC, 1 60 | instance = comp, \OneShReg[12] , OneShReg[12], SqrtCORDIC, 1 61 | instance = comp, \OneShReg[11] , OneShReg[11], SqrtCORDIC, 1 62 | instance = comp, \OneShReg[10] , OneShReg[10], SqrtCORDIC, 1 63 | instance = comp, \OneShReg[9] , OneShReg[9], SqrtCORDIC, 1 64 | instance = comp, \OneShReg[8]~feeder , OneShReg[8]~feeder, SqrtCORDIC, 1 65 | instance = comp, \OneShReg[8] , OneShReg[8], SqrtCORDIC, 1 66 | instance = comp, \OneShReg[7]~feeder , OneShReg[7]~feeder, SqrtCORDIC, 1 67 | instance = comp, \OneShReg[7] , OneShReg[7], SqrtCORDIC, 1 68 | instance = comp, \OneShReg[6]~feeder , OneShReg[6]~feeder, SqrtCORDIC, 1 69 | instance = comp, \OneShReg[6] , OneShReg[6], SqrtCORDIC, 1 70 | instance = comp, \OneShReg[5] , OneShReg[5], SqrtCORDIC, 1 71 | instance = comp, \OneShReg[4]~feeder , OneShReg[4]~feeder, SqrtCORDIC, 1 72 | instance = comp, \OneShReg[4] , OneShReg[4], SqrtCORDIC, 1 73 | instance = comp, \OneShReg[3] , OneShReg[3], SqrtCORDIC, 1 74 | instance = comp, \OneShReg[2] , OneShReg[2], SqrtCORDIC, 1 75 | instance = comp, \OneShReg[1] , OneShReg[1], SqrtCORDIC, 1 76 | instance = comp, \OneShReg[0] , OneShReg[0], SqrtCORDIC, 1 77 | instance = comp, \Add0~1 , Add0~1, SqrtCORDIC, 1 78 | instance = comp, \InpNum[30]~input , InpNum[30]~input, SqrtCORDIC, 1 79 | instance = comp, \InputReg[30] , InputReg[30], SqrtCORDIC, 1 80 | instance = comp, \InpNum[31]~input , InpNum[31]~input, SqrtCORDIC, 1 81 | instance = comp, \InputReg[31] , InputReg[31], SqrtCORDIC, 1 82 | instance = comp, \Sqrt[1] , Sqrt[1], SqrtCORDIC, 1 83 | instance = comp, \Add0~5 , Add0~5, SqrtCORDIC, 1 84 | instance = comp, \Sqrt[2] , Sqrt[2], SqrtCORDIC, 1 85 | instance = comp, \Add0~9 , Add0~9, SqrtCORDIC, 1 86 | instance = comp, \Sqrt[3] , Sqrt[3], SqrtCORDIC, 1 87 | instance = comp, \Add0~13 , Add0~13, SqrtCORDIC, 1 88 | instance = comp, \Sqrt[4] , Sqrt[4], SqrtCORDIC, 1 89 | instance = comp, \Add0~17 , Add0~17, SqrtCORDIC, 1 90 | instance = comp, \Sqrt[5] , Sqrt[5], SqrtCORDIC, 1 91 | instance = comp, \Add0~21 , Add0~21, SqrtCORDIC, 1 92 | instance = comp, \Sqrt[6] , Sqrt[6], SqrtCORDIC, 1 93 | instance = comp, \Add0~25 , Add0~25, SqrtCORDIC, 1 94 | instance = comp, \Sqrt[7] , Sqrt[7], SqrtCORDIC, 1 95 | instance = comp, \Add0~29 , Add0~29, SqrtCORDIC, 1 96 | instance = comp, \Sqrt[8] , Sqrt[8], SqrtCORDIC, 1 97 | instance = comp, \Add0~33 , Add0~33, SqrtCORDIC, 1 98 | instance = comp, \Sqrt[9] , Sqrt[9], SqrtCORDIC, 1 99 | instance = comp, \Add0~37 , Add0~37, SqrtCORDIC, 1 100 | instance = comp, \Sqrt[10] , Sqrt[10], SqrtCORDIC, 1 101 | instance = comp, \Add0~41 , Add0~41, SqrtCORDIC, 1 102 | instance = comp, \Sqrt[11] , Sqrt[11], SqrtCORDIC, 1 103 | instance = comp, \Add0~45 , Add0~45, SqrtCORDIC, 1 104 | instance = comp, \Sqrt[12] , Sqrt[12], SqrtCORDIC, 1 105 | instance = comp, \Add0~49 , Add0~49, SqrtCORDIC, 1 106 | instance = comp, \Sqrt[13] , Sqrt[13], SqrtCORDIC, 1 107 | instance = comp, \Add0~53 , Add0~53, SqrtCORDIC, 1 108 | instance = comp, \Sqrt[14] , Sqrt[14], SqrtCORDIC, 1 109 | instance = comp, \Add0~57 , Add0~57, SqrtCORDIC, 1 110 | instance = comp, \Sqrt[15] , Sqrt[15], SqrtCORDIC, 1 111 | instance = comp, \Add0~61 , Add0~61, SqrtCORDIC, 1 112 | instance = comp, \Sqrt[16] , Sqrt[16], SqrtCORDIC, 1 113 | instance = comp, \Add0~65 , Add0~65, SqrtCORDIC, 1 114 | instance = comp, \Sqrt[17] , Sqrt[17], SqrtCORDIC, 1 115 | instance = comp, \Add0~69 , Add0~69, SqrtCORDIC, 1 116 | instance = comp, \Sqrt[18] , Sqrt[18], SqrtCORDIC, 1 117 | instance = comp, \Add0~73 , Add0~73, SqrtCORDIC, 1 118 | instance = comp, \Sqrt[19] , Sqrt[19], SqrtCORDIC, 1 119 | instance = comp, \Add0~77 , Add0~77, SqrtCORDIC, 1 120 | instance = comp, \Sqrt[20] , Sqrt[20], SqrtCORDIC, 1 121 | instance = comp, \Add0~81 , Add0~81, SqrtCORDIC, 1 122 | instance = comp, \Sqrt[21] , Sqrt[21], SqrtCORDIC, 1 123 | instance = comp, \Add0~85 , Add0~85, SqrtCORDIC, 1 124 | instance = comp, \Sqrt[22] , Sqrt[22], SqrtCORDIC, 1 125 | instance = comp, \Add0~89 , Add0~89, SqrtCORDIC, 1 126 | instance = comp, \Sqrt[23] , Sqrt[23], SqrtCORDIC, 1 127 | instance = comp, \Add0~93 , Add0~93, SqrtCORDIC, 1 128 | instance = comp, \Mult0~8 , Mult0~8, SqrtCORDIC, 1 129 | instance = comp, \InpNum[29]~input , InpNum[29]~input, SqrtCORDIC, 1 130 | instance = comp, \InputReg[29] , InputReg[29], SqrtCORDIC, 1 131 | instance = comp, \Sqrt[0]~1 , Sqrt[0]~1, SqrtCORDIC, 1 132 | instance = comp, \Sqrt[0]~2 , Sqrt[0]~2, SqrtCORDIC, 1 133 | instance = comp, \InpNum[25]~input , InpNum[25]~input, SqrtCORDIC, 1 134 | instance = comp, \InputReg[25] , InputReg[25], SqrtCORDIC, 1 135 | instance = comp, \InpNum[22]~input , InpNum[22]~input, SqrtCORDIC, 1 136 | instance = comp, \InputReg[22] , InputReg[22], SqrtCORDIC, 1 137 | instance = comp, \LessThan0~27 , LessThan0~27, SqrtCORDIC, 1 138 | instance = comp, \InpNum[24]~input , InpNum[24]~input, SqrtCORDIC, 1 139 | instance = comp, \InputReg[24] , InputReg[24], SqrtCORDIC, 1 140 | instance = comp, \LessThan0~25 , LessThan0~25, SqrtCORDIC, 1 141 | instance = comp, \InpNum[23]~input , InpNum[23]~input, SqrtCORDIC, 1 142 | instance = comp, \InputReg[23] , InputReg[23], SqrtCORDIC, 1 143 | instance = comp, \LessThan0~26 , LessThan0~26, SqrtCORDIC, 1 144 | instance = comp, \InpNum[26]~input , InpNum[26]~input, SqrtCORDIC, 1 145 | instance = comp, \InputReg[26] , InputReg[26], SqrtCORDIC, 1 146 | instance = comp, \InpNum[28]~input , InpNum[28]~input, SqrtCORDIC, 1 147 | instance = comp, \InputReg[28] , InputReg[28], SqrtCORDIC, 1 148 | instance = comp, \InpNum[27]~input , InpNum[27]~input, SqrtCORDIC, 1 149 | instance = comp, \InputReg[27] , InputReg[27], SqrtCORDIC, 1 150 | instance = comp, \LessThan0~24 , LessThan0~24, SqrtCORDIC, 1 151 | instance = comp, \LessThan0~28 , LessThan0~28, SqrtCORDIC, 1 152 | instance = comp, \LessThan0~30 , LessThan0~30, SqrtCORDIC, 1 153 | instance = comp, \LessThan0~31 , LessThan0~31, SqrtCORDIC, 1 154 | instance = comp, \LessThan0~29 , LessThan0~29, SqrtCORDIC, 1 155 | instance = comp, \LessThan0~32 , LessThan0~32, SqrtCORDIC, 1 156 | instance = comp, \LessThan0~33 , LessThan0~33, SqrtCORDIC, 1 157 | instance = comp, \Sqrt[0]~0 , Sqrt[0]~0, SqrtCORDIC, 1 158 | instance = comp, \InpNum[16]~input , InpNum[16]~input, SqrtCORDIC, 1 159 | instance = comp, \InputReg[16] , InputReg[16], SqrtCORDIC, 1 160 | instance = comp, \InpNum[15]~input , InpNum[15]~input, SqrtCORDIC, 1 161 | instance = comp, \InputReg[15] , InputReg[15], SqrtCORDIC, 1 162 | instance = comp, \InpNum[18]~input , InpNum[18]~input, SqrtCORDIC, 1 163 | instance = comp, \InputReg[18] , InputReg[18], SqrtCORDIC, 1 164 | instance = comp, \InpNum[17]~input , InpNum[17]~input, SqrtCORDIC, 1 165 | instance = comp, \InputReg[17] , InputReg[17], SqrtCORDIC, 1 166 | instance = comp, \LessThan0~15 , LessThan0~15, SqrtCORDIC, 1 167 | instance = comp, \InpNum[19]~input , InpNum[19]~input, SqrtCORDIC, 1 168 | instance = comp, \InputReg[19] , InputReg[19], SqrtCORDIC, 1 169 | instance = comp, \InpNum[21]~input , InpNum[21]~input, SqrtCORDIC, 1 170 | instance = comp, \InputReg[21] , InputReg[21], SqrtCORDIC, 1 171 | instance = comp, \InpNum[20]~input , InpNum[20]~input, SqrtCORDIC, 1 172 | instance = comp, \InputReg[20] , InputReg[20], SqrtCORDIC, 1 173 | instance = comp, \LessThan0~14 , LessThan0~14, SqrtCORDIC, 1 174 | instance = comp, \LessThan0~20 , LessThan0~20, SqrtCORDIC, 1 175 | instance = comp, \LessThan0~21 , LessThan0~21, SqrtCORDIC, 1 176 | instance = comp, \LessThan0~22 , LessThan0~22, SqrtCORDIC, 1 177 | instance = comp, \LessThan0~23 , LessThan0~23, SqrtCORDIC, 1 178 | instance = comp, \InpNum[9]~input , InpNum[9]~input, SqrtCORDIC, 1 179 | instance = comp, \InputReg[9] , InputReg[9], SqrtCORDIC, 1 180 | instance = comp, \InpNum[12]~input , InpNum[12]~input, SqrtCORDIC, 1 181 | instance = comp, \InputReg[12] , InputReg[12], SqrtCORDIC, 1 182 | instance = comp, \InpNum[11]~input , InpNum[11]~input, SqrtCORDIC, 1 183 | instance = comp, \InputReg[11] , InputReg[11], SqrtCORDIC, 1 184 | instance = comp, \InpNum[8]~input , InpNum[8]~input, SqrtCORDIC, 1 185 | instance = comp, \InputReg[8] , InputReg[8], SqrtCORDIC, 1 186 | instance = comp, \InpNum[10]~input , InpNum[10]~input, SqrtCORDIC, 1 187 | instance = comp, \InputReg[10] , InputReg[10], SqrtCORDIC, 1 188 | instance = comp, \LessThan0~36 , LessThan0~36, SqrtCORDIC, 1 189 | instance = comp, \InpNum[13]~input , InpNum[13]~input, SqrtCORDIC, 1 190 | instance = comp, \InputReg[13] , InputReg[13], SqrtCORDIC, 1 191 | instance = comp, \InpNum[14]~input , InpNum[14]~input, SqrtCORDIC, 1 192 | instance = comp, \InputReg[14] , InputReg[14], SqrtCORDIC, 1 193 | instance = comp, \LessThan0~37 , LessThan0~37, SqrtCORDIC, 1 194 | instance = comp, \LessThan0~9 , LessThan0~9, SqrtCORDIC, 1 195 | instance = comp, \LessThan0~16 , LessThan0~16, SqrtCORDIC, 1 196 | instance = comp, \LessThan0~17 , LessThan0~17, SqrtCORDIC, 1 197 | instance = comp, \LessThan0~18 , LessThan0~18, SqrtCORDIC, 1 198 | instance = comp, \LessThan0~7 , LessThan0~7, SqrtCORDIC, 1 199 | instance = comp, \LessThan0~8 , LessThan0~8, SqrtCORDIC, 1 200 | instance = comp, \LessThan0~12 , LessThan0~12, SqrtCORDIC, 1 201 | instance = comp, \LessThan0~6 , LessThan0~6, SqrtCORDIC, 1 202 | instance = comp, \LessThan0~13 , LessThan0~13, SqrtCORDIC, 1 203 | instance = comp, \InpNum[4]~input , InpNum[4]~input, SqrtCORDIC, 1 204 | instance = comp, \InputReg[4] , InputReg[4], SqrtCORDIC, 1 205 | instance = comp, \InpNum[6]~input , InpNum[6]~input, SqrtCORDIC, 1 206 | instance = comp, \InputReg[6] , InputReg[6], SqrtCORDIC, 1 207 | instance = comp, \InpNum[7]~input , InpNum[7]~input, SqrtCORDIC, 1 208 | instance = comp, \InputReg[7]~feeder , InputReg[7]~feeder, SqrtCORDIC, 1 209 | instance = comp, \InputReg[7] , InputReg[7], SqrtCORDIC, 1 210 | instance = comp, \LessThan0~4 , LessThan0~4, SqrtCORDIC, 1 211 | instance = comp, \InpNum[5]~input , InpNum[5]~input, SqrtCORDIC, 1 212 | instance = comp, \InputReg[5] , InputReg[5], SqrtCORDIC, 1 213 | instance = comp, \LessThan0~0 , LessThan0~0, SqrtCORDIC, 1 214 | instance = comp, \LessThan0~5 , LessThan0~5, SqrtCORDIC, 1 215 | instance = comp, \LessThan0~10 , LessThan0~10, SqrtCORDIC, 1 216 | instance = comp, \LessThan0~11 , LessThan0~11, SqrtCORDIC, 1 217 | instance = comp, \LessThan0~34 , LessThan0~34, SqrtCORDIC, 1 218 | instance = comp, \InpNum[2]~input , InpNum[2]~input, SqrtCORDIC, 1 219 | instance = comp, \InputReg[2] , InputReg[2], SqrtCORDIC, 1 220 | instance = comp, \InpNum[3]~input , InpNum[3]~input, SqrtCORDIC, 1 221 | instance = comp, \InputReg[3] , InputReg[3], SqrtCORDIC, 1 222 | instance = comp, \LessThan0~1 , LessThan0~1, SqrtCORDIC, 1 223 | instance = comp, \LessThan0~2 , LessThan0~2, SqrtCORDIC, 1 224 | instance = comp, \InpNum[1]~input , InpNum[1]~input, SqrtCORDIC, 1 225 | instance = comp, \InputReg[1] , InputReg[1], SqrtCORDIC, 1 226 | instance = comp, \InpNum[0]~input , InpNum[0]~input, SqrtCORDIC, 1 227 | instance = comp, \InputReg[0] , InputReg[0], SqrtCORDIC, 1 228 | instance = comp, \LessThan0~35 , LessThan0~35, SqrtCORDIC, 1 229 | instance = comp, \LessThan0~3 , LessThan0~3, SqrtCORDIC, 1 230 | instance = comp, \LessThan0~19 , LessThan0~19, SqrtCORDIC, 1 231 | instance = comp, \Sqrt[0]~3 , Sqrt[0]~3, SqrtCORDIC, 1 232 | instance = comp, \Sqrt[0] , Sqrt[0], SqrtCORDIC, 1 233 | instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, SqrtCORDIC, 1 234 | -------------------------------------------------------------------------------- /SqrtCORDIC/ModelSim/SqrtCORDIC.mpf: -------------------------------------------------------------------------------- 1 | ; Copyright 1991-2009 Mentor Graphics Corporation 2 | ; 3 | ; All Rights Reserved. 4 | ; 5 | ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 6 | ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. 7 | ; 8 | 9 | [Library] 10 | std = $MODEL_TECH/../std 11 | ieee = $MODEL_TECH/../ieee 12 | verilog = $MODEL_TECH/../verilog 13 | vital2000 = $MODEL_TECH/../vital2000 14 | std_developerskit = $MODEL_TECH/../std_developerskit 15 | synopsys = $MODEL_TECH/../synopsys 16 | modelsim_lib = $MODEL_TECH/../modelsim_lib 17 | sv_std = $MODEL_TECH/../sv_std 18 | 19 | ; Altera Primitive libraries 20 | ; 21 | ; VHDL Section 22 | ; 23 | altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf 24 | altera = $MODEL_TECH/../altera/vhdl/altera 25 | altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim 26 | lpm = $MODEL_TECH/../altera/vhdl/220model 27 | 220model = $MODEL_TECH/../altera/vhdl/220model 28 | maxii = $MODEL_TECH/../altera/vhdl/maxii 29 | maxv = $MODEL_TECH/../altera/vhdl/maxv 30 | fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm 31 | sgate = $MODEL_TECH/../altera/vhdl/sgate 32 | arriaii = $MODEL_TECH/../altera/vhdl/arriaii 33 | arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi 34 | arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip 35 | arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz 36 | arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi 37 | arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip 38 | stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv 39 | stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi 40 | stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip 41 | cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv 42 | cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi 43 | cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip 44 | cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive 45 | stratixv = $MODEL_TECH/../altera/vhdl/stratixv 46 | stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi 47 | stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip 48 | arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz 49 | arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi 50 | arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip 51 | arriav = $MODEL_TECH/../altera/vhdl/arriav 52 | cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev 53 | twentynm = $MODEL_TECH/../altera/vhdl/twentynm 54 | twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi 55 | twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip 56 | fourteennm = $MODEL_TECH/../altera/vhdl/fourteennm 57 | ; 58 | ; Verilog Section 59 | ; 60 | altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf 61 | altera_ver = $MODEL_TECH/../altera/verilog/altera 62 | altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim 63 | lpm_ver = $MODEL_TECH/../altera/verilog/220model 64 | 220model_ver = $MODEL_TECH/../altera/verilog/220model 65 | maxii_ver = $MODEL_TECH/../altera/verilog/maxii 66 | maxv_ver = $MODEL_TECH/../altera/verilog/maxv 67 | fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm 68 | sgate_ver = $MODEL_TECH/../altera/verilog/sgate 69 | arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii 70 | arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi 71 | arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip 72 | arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz 73 | arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi 74 | arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip 75 | stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv 76 | stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi 77 | stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip 78 | stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv 79 | stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi 80 | stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip 81 | arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz 82 | arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi 83 | arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip 84 | arriav_ver = $MODEL_TECH/../altera/verilog/arriav 85 | arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi 86 | arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip 87 | cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev 88 | cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi 89 | cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip 90 | cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv 91 | cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi 92 | cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip 93 | cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive 94 | twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm 95 | twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi 96 | twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip 97 | fourteennm_ver = $MODEL_TECH/../altera/verilog/fourteennm 98 | 99 | work = SqrtCORDIC 100 | [vcom] 101 | ; VHDL93 variable selects language version as the default. 102 | ; Default is VHDL-2002. 103 | ; Value of 0 or 1987 for VHDL-1987. 104 | ; Value of 1 or 1993 for VHDL-1993. 105 | ; Default or value of 2 or 2002 for VHDL-2002. 106 | ; Default or value of 3 or 2008 for VHDL-2008. 107 | VHDL93 = 2002 108 | 109 | ; Show source line containing error. Default is off. 110 | ; Show_source = 1 111 | 112 | ; Turn off unbound-component warnings. Default is on. 113 | ; Show_Warning1 = 0 114 | 115 | ; Turn off process-without-a-wait-statement warnings. Default is on. 116 | ; Show_Warning2 = 0 117 | 118 | ; Turn off null-range warnings. Default is on. 119 | ; Show_Warning3 = 0 120 | 121 | ; Turn off no-space-in-time-literal warnings. Default is on. 122 | ; Show_Warning4 = 0 123 | 124 | ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. 125 | ; Show_Warning5 = 0 126 | 127 | ; Turn off optimization for IEEE std_logic_1164 package. Default is on. 128 | ; Optimize_1164 = 0 129 | 130 | ; Turn on resolving of ambiguous function overloading in favor of the 131 | ; "explicit" function declaration (not the one automatically created by 132 | ; the compiler for each type declaration). Default is off. 133 | ; The .ini file has Explicit enabled so that std_logic_signed/unsigned 134 | ; will match the behavior of synthesis tools. 135 | Explicit = 1 136 | 137 | ; Turn off acceleration of the VITAL packages. Default is to accelerate. 138 | ; NoVital = 1 139 | 140 | ; Turn off VITAL compliance checking. Default is checking on. 141 | ; NoVitalCheck = 1 142 | 143 | ; Ignore VITAL compliance checking errors. Default is to not ignore. 144 | ; IgnoreVitalErrors = 1 145 | 146 | ; Turn off VITAL compliance checking warnings. Default is to show warnings. 147 | ; Show_VitalChecksWarnings = 0 148 | 149 | ; Keep silent about case statement static warnings. 150 | ; Default is to give a warning. 151 | ; NoCaseStaticError = 1 152 | 153 | ; Keep silent about warnings caused by aggregates that are not locally static. 154 | ; Default is to give a warning. 155 | ; NoOthersStaticError = 1 156 | 157 | ; Turn off inclusion of debugging info within design units. 158 | ; Default is to include debugging info. 159 | ; NoDebug = 1 160 | 161 | ; Turn off "Loading..." messages. Default is messages on. 162 | ; Quiet = 1 163 | 164 | ; Turn on some limited synthesis rule compliance checking. Checks only: 165 | ; -- signals used (read) by a process must be in the sensitivity list 166 | ; CheckSynthesis = 1 167 | 168 | ; Activate optimizations on expressions that do not involve signals, 169 | ; waits, or function/procedure/task invocations. Default is off. 170 | ; ScalarOpts = 1 171 | 172 | ; Require the user to specify a configuration for all bindings, 173 | ; and do not generate a compile time default binding for the 174 | ; component. This will result in an elaboration error of 175 | ; 'component not bound' if the user fails to do so. Avoids the rare 176 | ; issue of a false dependency upon the unused default binding. 177 | ; RequireConfigForAllDefaultBinding = 1 178 | 179 | ; Inhibit range checking on subscripts of arrays. Range checking on 180 | ; scalars defined with subtypes is inhibited by default. 181 | ; NoIndexCheck = 1 182 | 183 | ; Inhibit range checks on all (implicit and explicit) assignments to 184 | ; scalar objects defined with subtypes. 185 | ; NoRangeCheck = 1 186 | 187 | [vlog] 188 | 189 | ; Turn off inclusion of debugging info within design units. 190 | ; Default is to include debugging info. 191 | ; NoDebug = 1 192 | 193 | ; Turn off "loading..." messages. Default is messages on. 194 | ; Quiet = 1 195 | 196 | ; Turn on Verilog hazard checking (order-dependent accessing of global vars). 197 | ; Default is off. 198 | ; Hazard = 1 199 | 200 | ; Turn on converting regular Verilog identifiers to uppercase. Allows case 201 | ; insensitivity for module names. Default is no conversion. 202 | ; UpCase = 1 203 | 204 | ; Turn on incremental compilation of modules. Default is off. 205 | ; Incremental = 1 206 | 207 | ; Turns on lint-style checking. 208 | ; Show_Lint = 1 209 | 210 | [vsim] 211 | ; Simulator resolution 212 | ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. 213 | Resolution = ps 214 | 215 | ; User time unit for run commands 216 | ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the 217 | ; unit specified for Resolution. For example, if Resolution is 100ps, 218 | ; then UserTimeUnit defaults to ps. 219 | ; Should generally be set to default. 220 | UserTimeUnit = default 221 | 222 | ; Default run length 223 | RunLength = 100 us 224 | 225 | ; Maximum iterations that can be run without advancing simulation time 226 | IterationLimit = 5000 227 | 228 | ; Directive to license manager: 229 | ; vhdl Immediately reserve a VHDL license 230 | ; vlog Immediately reserve a Verilog license 231 | ; plus Immediately reserve a VHDL and Verilog license 232 | ; nomgc Do not look for Mentor Graphics Licenses 233 | ; nomti Do not look for Model Technology Licenses 234 | ; noqueue Do not wait in the license queue when a license isn't available 235 | ; viewsim Try for viewer license but accept simulator license(s) instead 236 | ; of queuing for viewer license 237 | ; License = plus 238 | 239 | ; Stop the simulator after a VHDL/Verilog assertion message 240 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 241 | BreakOnAssertion = 3 242 | 243 | ; Assertion Message Format 244 | ; %S - Severity Level 245 | ; %R - Report Message 246 | ; %T - Time of assertion 247 | ; %D - Delta 248 | ; %I - Instance or Region pathname (if available) 249 | ; %% - print '%' character 250 | ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" 251 | 252 | ; Assertion File - alternate file for storing VHDL/Verilog assertion messages 253 | ; AssertFile = assert.log 254 | 255 | ; Default radix for all windows and commands... 256 | ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned 257 | DefaultRadix = symbolic 258 | 259 | ; VSIM Startup command 260 | ; Startup = do startup.do 261 | 262 | ; File for saving command transcript 263 | TranscriptFile = transcript 264 | 265 | ; File for saving command history 266 | ; CommandHistory = cmdhist.log 267 | 268 | ; Specify whether paths in simulator commands should be described 269 | ; in VHDL or Verilog format. 270 | ; For VHDL, PathSeparator = / 271 | ; For Verilog, PathSeparator = . 272 | ; Must not be the same character as DatasetSeparator. 273 | PathSeparator = / 274 | 275 | ; Specify the dataset separator for fully rooted contexts. 276 | ; The default is ':'. For example, sim:/top 277 | ; Must not be the same character as PathSeparator. 278 | DatasetSeparator = : 279 | 280 | ; Disable VHDL assertion messages 281 | ; IgnoreNote = 1 282 | ; IgnoreWarning = 1 283 | ; IgnoreError = 1 284 | ; IgnoreFailure = 1 285 | 286 | ; Default force kind. May be freeze, drive, deposit, or default 287 | ; or in other terms, fixed, wired, or charged. 288 | ; A value of "default" will use the signal kind to determine the 289 | ; force kind, drive for resolved signals, freeze for unresolved signals 290 | ; DefaultForceKind = freeze 291 | 292 | ; If zero, open files when elaborated; otherwise, open files on 293 | ; first read or write. Default is 0. 294 | ; DelayFileOpen = 1 295 | 296 | ; Control VHDL files opened for write. 297 | ; 0 = Buffered, 1 = Unbuffered 298 | UnbufferedOutput = 0 299 | 300 | ; Control the number of VHDL files open concurrently. 301 | ; This number should always be less than the current ulimit 302 | ; setting for max file descriptors. 303 | ; 0 = unlimited 304 | ConcurrentFileLimit = 40 305 | 306 | ; Control the number of hierarchical regions displayed as 307 | ; part of a signal name shown in the Wave window. 308 | ; A value of zero tells VSIM to display the full name. 309 | ; The default is 0. 310 | ; WaveSignalNameWidth = 0 311 | 312 | ; Turn off warnings from the std_logic_arith, std_logic_unsigned 313 | ; and std_logic_signed packages. 314 | ; StdArithNoWarnings = 1 315 | 316 | ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. 317 | ; NumericStdNoWarnings = 1 318 | 319 | ; Control the format of the (VHDL) FOR generate statement label 320 | ; for each iteration. Do not quote it. 321 | ; The format string here must contain the conversion codes %s and %d, 322 | ; in that order, and no other conversion codes. The %s represents 323 | ; the generate_label; the %d represents the generate parameter value 324 | ; at a particular generate iteration (this is the position number if 325 | ; the generate parameter is of an enumeration type). Embedded whitespace 326 | ; is allowed (but discouraged); leading and trailing whitespace is ignored. 327 | ; Application of the format must result in a unique scope name over all 328 | ; such names in the design so that name lookup can function properly. 329 | ; GenerateFormat = %s__%d 330 | 331 | ; Specify whether checkpoint files should be compressed. 332 | ; The default is 1 (compressed). 333 | ; CheckpointCompressMode = 0 334 | 335 | ; List of dynamically loaded objects for Verilog PLI applications 336 | ; Veriuser = veriuser.sl 337 | 338 | ; Specify default options for the restart command. Options can be one 339 | ; or more of: -force -nobreakpoint -nolist -nolog -nowave 340 | ; DefaultRestartOptions = -force 341 | 342 | ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs 343 | ; (> 500 megabyte memory footprint). Default is disabled. 344 | ; Specify number of megabytes to lock. 345 | ; LockedMemory = 1000 346 | 347 | ; Turn on (1) or off (0) WLF file compression. 348 | ; The default is 1 (compress WLF file). 349 | ; WLFCompress = 0 350 | 351 | ; Specify whether to save all design hierarchy (1) in the WLF file 352 | ; or only regions containing logged signals (0). 353 | ; The default is 0 (save only regions with logged signals). 354 | ; WLFSaveAllRegions = 1 355 | 356 | ; WLF file time limit. Limit WLF file by time, as closely as possible, 357 | ; to the specified amount of simulation time. When the limit is exceeded 358 | ; the earliest times get truncated from the file. 359 | ; If both time and size limits are specified the most restrictive is used. 360 | ; UserTimeUnits are used if time units are not specified. 361 | ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} 362 | ; WLFTimeLimit = 0 363 | 364 | ; WLF file size limit. Limit WLF file size, as closely as possible, 365 | ; to the specified number of megabytes. If both time and size limits 366 | ; are specified then the most restrictive is used. 367 | ; The default is 0 (no limit). 368 | ; WLFSizeLimit = 1000 369 | 370 | ; Specify whether or not a WLF file should be deleted when the 371 | ; simulation ends. A value of 1 will cause the WLF file to be deleted. 372 | ; The default is 0 (do not delete WLF file when simulation ends). 373 | ; WLFDeleteOnQuit = 1 374 | 375 | ; Automatic SDF compilation 376 | ; Disables automatic compilation of SDF files in flows that support it. 377 | ; Default is on, uncomment to turn off. 378 | ; NoAutoSDFCompile = 1 379 | 380 | [lmc] 381 | 382 | [msg_system] 383 | ; Change a message severity or suppress a message. 384 | ; The format is: = [,...] 385 | ; Examples: 386 | ; note = 3009 387 | ; warning = 3033 388 | ; error = 3010,3016 389 | ; fatal = 3016,3033 390 | ; suppress = 3009,3016,3043 391 | ; The command verror can be used to get the complete 392 | ; description of a message. 393 | 394 | ; Control transcripting of elaboration/runtime messages. 395 | ; The default is to have messages appear in the transcript and 396 | ; recorded in the wlf file (messages that are recorded in the 397 | ; wlf file can be viewed in the MsgViewer). The other settings 398 | ; are to send messages only to the transcript or only to the 399 | ; wlf file. The valid values are 400 | ; both {default} 401 | ; tran {transcript only} 402 | ; wlf {wlf file only} 403 | ; msgmode = both 404 | [Project] 405 | ; Warning -- Do not edit the project properties directly. 406 | ; Property names are dynamic in nature and property 407 | ; values have special syntax. Changing property data directly 408 | ; can result in a corrupt MPF file. All project properties 409 | ; can be modified through project window dialogs. 410 | Project_Version = 6 411 | Project_DefaultLib = work 412 | Project_SortMethod = unused 413 | Project_Files_Count = 2 414 | Project_File_0 = C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/SqrtCORDIC.v 415 | Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1572767608 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to SqrtCORDIC vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 416 | Project_File_1 = C:/Users/UPNM/Desktop/SqrtCORDIC/ModelSim/Testbench.v 417 | Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1572769537 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to SqrtCORDIC vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 418 | Project_Sim_Count = 0 419 | Project_Folder_Count = 0 420 | Echo_Compile_Output = 0 421 | Save_Compile_Report = 1 422 | Project_Opt_Count = 0 423 | ForceSoftPaths = 0 424 | ProjectStatusDelay = 5000 425 | VERILOG_DoubleClick = Edit 426 | VERILOG_CustomDoubleClick = 427 | SYSTEMVERILOG_DoubleClick = Edit 428 | SYSTEMVERILOG_CustomDoubleClick = 429 | VHDL_DoubleClick = Edit 430 | VHDL_CustomDoubleClick = 431 | PSL_DoubleClick = Edit 432 | PSL_CustomDoubleClick = 433 | TEXT_DoubleClick = Edit 434 | TEXT_CustomDoubleClick = 435 | SYSTEMC_DoubleClick = Edit 436 | SYSTEMC_CustomDoubleClick = 437 | TCL_DoubleClick = Edit 438 | TCL_CustomDoubleClick = 439 | MACRO_DoubleClick = Edit 440 | MACRO_CustomDoubleClick = 441 | VCD_DoubleClick = Edit 442 | VCD_CustomDoubleClick = 443 | SDF_DoubleClick = Edit 444 | SDF_CustomDoubleClick = 445 | XML_DoubleClick = Edit 446 | XML_CustomDoubleClick = 447 | LOGFILE_DoubleClick = Edit 448 | LOGFILE_CustomDoubleClick = 449 | UCDB_DoubleClick = Edit 450 | UCDB_CustomDoubleClick = 451 | TDB_DoubleClick = Edit 452 | TDB_CustomDoubleClick = 453 | UPF_DoubleClick = Edit 454 | UPF_CustomDoubleClick = 455 | PCF_DoubleClick = Edit 456 | PCF_CustomDoubleClick = 457 | PROJECT_DoubleClick = Edit 458 | PROJECT_CustomDoubleClick = 459 | VRM_DoubleClick = Edit 460 | VRM_CustomDoubleClick = 461 | DEBUGDATABASE_DoubleClick = Edit 462 | DEBUGDATABASE_CustomDoubleClick = 463 | DEBUGARCHIVE_DoubleClick = Edit 464 | DEBUGARCHIVE_CustomDoubleClick = 465 | Project_Major_Version = 10 466 | Project_Minor_Version = 4 467 | -------------------------------------------------------------------------------- /SqrtCORDIC/db/SqrtCORDIC.sta.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1572770757158 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1572770757158 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 03 16:45:56 2019 " "Processing started: Sun Nov 03 16:45:56 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1572770757158 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770757158 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta SqrtCORDIC -c SqrtCORDIC " "Command: quartus_sta SqrtCORDIC -c SqrtCORDIC" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770757158 ""} 4 | { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1572770757533 ""} 5 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770758173 ""} 6 | { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770758173 ""} 7 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770758220 ""} 8 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770758220 ""} 9 | { "Critical Warning" "WSTA_SDC_NOT_FOUND" "SqrtCORDIC.sdc " "Synopsys Design Constraints File file not found: 'SqrtCORDIC.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770758845 ""} 10 | { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770758845 ""} 11 | { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1572770758845 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770758845 ""} 12 | { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770758845 ""} 13 | { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770758877 ""} 14 | { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1572770758877 ""} 15 | { "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1572770758908 ""} 16 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1572770759002 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770759002 ""} 17 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -14.685 " "Worst-case setup slack is -14.685" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770759002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770759002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.685 -394.828 clk " " -14.685 -394.828 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770759002 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770759002 ""} 18 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.354 " "Worst-case hold slack is 0.354" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770759033 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770759033 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.354 0.000 clk " " 0.354 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770759033 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770759033 ""} 19 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770759049 ""} 20 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770759049 ""} 21 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.724 " "Worst-case minimum pulse width slack is -0.724" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770759049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770759049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.724 -102.263 clk " " -0.724 -102.263 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770759049 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770759049 ""} 22 | { "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1572770759111 ""} 23 | { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770759158 ""} 24 | { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770761209 ""} 25 | { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770761381 ""} 26 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1572770761397 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770761397 ""} 27 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -14.666 " "Worst-case setup slack is -14.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770761428 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770761428 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.666 -393.838 clk " " -14.666 -393.838 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770761428 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770761428 ""} 28 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.336 " "Worst-case hold slack is 0.336" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770761443 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770761443 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.336 0.000 clk " " 0.336 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770761443 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770761443 ""} 29 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770761443 ""} 30 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770761443 ""} 31 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.724 " "Worst-case minimum pulse width slack is -0.724" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770761475 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770761475 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.724 -104.822 clk " " -0.724 -104.822 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770761475 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770761475 ""} 32 | { "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1572770761506 ""} 33 | { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770761787 ""} 34 | { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770762897 ""} 35 | { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770762991 ""} 36 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1572770762991 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770762991 ""} 37 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -5.703 " "Worst-case setup slack is -5.703" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763006 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763006 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.703 -147.412 clk " " -5.703 -147.412 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763006 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763006 ""} 38 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.091 " "Worst-case hold slack is 0.091" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763022 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763022 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.091 0.000 clk " " 0.091 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763022 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763022 ""} 39 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763022 ""} 40 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763037 ""} 41 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.476 " "Worst-case minimum pulse width slack is -0.476" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.476 -44.946 clk " " -0.476 -44.946 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763037 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763037 ""} 42 | { "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1572770763053 ""} 43 | { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763256 ""} 44 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1572770763256 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763256 ""} 45 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -5.186 " "Worst-case setup slack is -5.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763256 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763256 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.186 -132.556 clk " " -5.186 -132.556 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763256 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763256 ""} 46 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.079 " "Worst-case hold slack is 0.079" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.079 0.000 clk " " 0.079 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763272 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763272 ""} 47 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763287 ""} 48 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763287 ""} 49 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.466 " "Worst-case minimum pulse width slack is -0.466" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.466 -43.569 clk " " -0.466 -43.569 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1572770763287 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770763287 ""} 50 | { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770765006 ""} 51 | { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770765006 ""} 52 | { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5426 " "Peak virtual memory: 5426 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1572770765256 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 03 16:46:05 2019 " "Processing ended: Sun Nov 03 16:46:05 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1572770765256 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1572770765256 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1572770765256 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1572770765256 ""} 53 | --------------------------------------------------------------------------------