├── .gitignore ├── .github └── pull_request_template.md ├── device_tree └── data │ └── kernel_dtsi │ ├── 2023.2 │ ├── zynq │ │ └── skeleton.dtsi │ ├── BOARD │ │ ├── kcu105.dtsi │ │ ├── kcu105-tmr.dtsi │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ ├── versal-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-reva.dtsi │ │ ├── versal-vck190-rev1.1.dtsi │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-rev1.1.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ ├── sp701-rev1.0.dtsi │ │ └── versal-x-ebm-01-reva.dtsi │ └── include │ │ └── dt-bindings │ │ ├── power │ │ └── xlnx-versal-regnode.h │ │ ├── dma │ │ └── xlnx-zynqmp-dpdma.h │ │ ├── phy │ │ └── phy.h │ │ ├── interrupt-controller │ │ └── irq.h │ │ └── pinctrl │ │ └── pinctrl-zynqmp.h │ ├── 2024.1 │ ├── zynq │ │ └── skeleton.dtsi │ ├── BOARD │ │ ├── kcu105.dtsi │ │ ├── kcu105-tmr.dtsi │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ ├── versal-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-reva.dtsi │ │ ├── versal-vck190-rev1.1.dtsi │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-rev1.1.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ ├── sp701-rev1.0.dtsi │ │ └── versal-x-ebm-01-reva.dtsi │ └── include │ │ └── dt-bindings │ │ ├── power │ │ └── xlnx-versal-regnode.h │ │ ├── dma │ │ └── xlnx-zynqmp-dpdma.h │ │ ├── phy │ │ └── phy.h │ │ ├── interrupt-controller │ │ └── irq.h │ │ └── pinctrl │ │ └── pinctrl-zynqmp.h │ ├── 2024.2 │ ├── zynq │ │ └── skeleton.dtsi │ ├── BOARD │ │ ├── kcu105.dtsi │ │ ├── kcu105-tmr.dtsi │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ ├── versal-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-reva.dtsi │ │ ├── versal-vck190-rev1.1.dtsi │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-rev1.1.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ ├── sp701-rev1.0.dtsi │ │ └── versal-x-ebm-01-reva.dtsi │ └── include │ │ └── dt-bindings │ │ ├── power │ │ └── xlnx-versal-regnode.h │ │ ├── dma │ │ └── xlnx-zynqmp-dpdma.h │ │ ├── phy │ │ └── phy.h │ │ ├── interrupt-controller │ │ └── irq.h │ │ └── pinctrl │ │ └── pinctrl-zynqmp.h │ ├── 2023.1 │ ├── BOARD │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ ├── versal-x-ebm-02-reva.dtsi │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ ├── versal-vck190-reva.dtsi │ │ ├── versal-vck190-rev1.1.dtsi │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-rev1.1.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ ├── kcu105.dtsi │ │ ├── kcu105-tmr.dtsi │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ └── versal-x-ebm-01-reva.dtsi │ └── include │ │ └── dt-bindings │ │ ├── power │ │ └── xlnx-versal-regnode.h │ │ ├── dma │ │ └── xlnx-zynqmp-dpdma.h │ │ ├── phy │ │ └── phy.h │ │ ├── interrupt-controller │ │ └── irq.h │ │ └── pinctrl │ │ └── pinctrl-zynqmp.h │ ├── 2022.1 │ ├── BOARD │ │ ├── versal-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-reva.dtsi │ │ ├── versal-vck190-rev1.1.dtsi │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ ├── kcu105.dtsi │ │ ├── kcu105-tmr.dtsi │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ └── versal-x-ebm-01-reva.dtsi │ └── include │ │ └── dt-bindings │ │ ├── dma │ │ └── xlnx-zynqmp-dpdma.h │ │ ├── phy │ │ └── phy.h │ │ ├── interrupt-controller │ │ └── irq.h │ │ └── pinctrl │ │ └── pinctrl-zynqmp.h │ ├── 2022.2 │ ├── BOARD │ │ ├── versal-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-reva.dtsi │ │ ├── versal-vck190-rev1.1.dtsi │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-rev1.1.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ ├── kcu105.dtsi │ │ ├── kcu105-tmr.dtsi │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ └── versal-x-ebm-01-reva.dtsi │ └── include │ │ └── dt-bindings │ │ ├── power │ │ └── xlnx-versal-regnode.h │ │ ├── dma │ │ └── xlnx-zynqmp-dpdma.h │ │ ├── phy │ │ └── phy.h │ │ ├── interrupt-controller │ │ └── irq.h │ │ └── pinctrl │ │ └── pinctrl-zynqmp.h │ ├── 2021.1 │ ├── include │ │ └── dt-bindings │ │ │ ├── dma │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── phy │ │ │ └── phy.h │ │ │ └── interrupt-controller │ │ │ └── irq.h │ └── BOARD │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ └── kcu105.dtsi │ ├── 2021.2 │ ├── include │ │ └── dt-bindings │ │ │ ├── dma │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── phy │ │ │ └── phy.h │ │ │ └── interrupt-controller │ │ │ └── irq.h │ └── BOARD │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ ├── kcu105.dtsi │ │ └── kcu105-tmr.dtsi │ ├── 2019.2 │ ├── BOARD │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ └── kcu105.dtsi │ └── include │ │ └── dt-bindings │ │ ├── phy │ │ └── phy.h │ │ └── interrupt-controller │ │ └── irq.h │ ├── v4.17 │ └── board │ │ ├── zc1275-reva.dtsi │ │ ├── zc1254-reva.dtsi │ │ └── zc1751-dc5.dtsi │ ├── 2019.1 │ ├── include │ │ └── dt-bindings │ │ │ ├── phy │ │ │ └── phy.h │ │ │ └── interrupt-controller │ │ │ └── irq.h │ └── BOARD │ │ ├── sp701-rev1.0.dtsi │ │ └── kcu105.dtsi │ ├── 2020.1 │ ├── include │ │ └── dt-bindings │ │ │ ├── phy │ │ │ └── phy.h │ │ │ └── interrupt-controller │ │ │ └── irq.h │ └── BOARD │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ └── kcu105.dtsi │ ├── 2020.2 │ ├── include │ │ └── dt-bindings │ │ │ ├── phy │ │ │ └── phy.h │ │ │ └── interrupt-controller │ │ │ └── irq.h │ └── BOARD │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ └── kcu105.dtsi │ ├── v5.0 │ └── board │ │ ├── zc1254-reva.dtsi │ │ ├── zc1275-reva.dtsi │ │ └── zc1751-dc5.dtsi │ ├── v5.1 │ └── board │ │ ├── zc1275-reva.dtsi │ │ ├── zc1254-reva.dtsi │ │ └── zc1751-dc5.dtsi │ ├── v5.3 │ └── board │ │ ├── zc1254-reva.dtsi │ │ ├── zc1275-reva.dtsi │ │ └── zc1751-dc5.dtsi │ ├── v4.18 │ └── board │ │ ├── zc1254-reva.dtsi │ │ ├── zc1275-reva.dtsi │ │ └── zc1751-dc5.dtsi │ ├── v4.19 │ └── board │ │ ├── zc1254-reva.dtsi │ │ ├── zc1275-reva.dtsi │ │ └── zc1751-dc5.dtsi │ ├── v4.20 │ └── board │ │ ├── zc1254-reva.dtsi │ │ ├── zc1275-reva.dtsi │ │ └── zc1751-dc5.dtsi │ ├── v5.2 │ └── board │ │ ├── zc1254-reva.dtsi │ │ ├── zc1275-reva.dtsi │ │ └── zc1751-dc5.dtsi │ ├── v5.4 │ └── board │ │ ├── zc1254-reva.dtsi │ │ ├── zc1275-reva.dtsi │ │ └── zc1751-dc5.dtsi │ ├── 2017.1 │ └── BOARD │ │ └── kcu105.dtsi │ ├── 2017.2 │ └── BOARD │ │ └── kcu105.dtsi │ ├── 2017.3 │ └── BOARD │ │ └── kcu105.dtsi │ ├── 2017.4 │ └── BOARD │ │ └── kcu105.dtsi │ ├── 2018.1 │ └── BOARD │ │ └── kcu105.dtsi │ ├── 2018.2 │ └── BOARD │ │ └── kcu105.dtsi │ └── 2018.3 │ └── BOARD │ └── kcu105.dtsi ├── apmps └── data │ ├── apmps.tcl │ └── apmps.mdd ├── canps └── data │ └── canps.tcl ├── ddrcps └── data │ └── ddrcps.tcl ├── devcfg └── data │ └── devcfg.tcl ├── ocmcps └── data │ └── ocmcps.tcl ├── pmups └── data │ └── pmups.tcl ├── scuwdt └── data │ └── scuwdt.tcl ├── smccps └── data │ └── smccps.tcl ├── ttcps └── data │ └── ttcps.tcl ├── wdtps └── data │ └── wdtps.tcl ├── xadcps └── data │ └── xadcps.tcl ├── canfdps └── data │ └── canfdps.tcl ├── pl310ps └── data │ └── pl310ps.tcl ├── scutimer └── data │ └── scutimer.tcl ├── axi_tft └── data │ └── axi_tft.tcl ├── axi_sysace └── data │ └── axi_sysace.tcl ├── globaltimerps └── data │ └── globaltimerps.tcl ├── ramps └── data │ └── ramps.tcl ├── generic └── data │ └── generic.mdd ├── RM └── data │ └── RM.tcl ├── isppipeline └── data │ └── ispipeline.mdd ├── vtc └── data │ └── vtc.mdd ├── ams └── data │ └── ams.mdd ├── dp └── data │ └── dp.mdd ├── tpg └── data │ └── tpg.mdd ├── mixer └── data │ └── mixer.mdd ├── axi_vcu └── data │ └── axi_vcu.mdd ├── axi_vdu └── data │ └── axi_vdu.mdd └── dmaps └── data └── dmaps.tcl /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | -------------------------------------------------------------------------------- /.github/pull_request_template.md: -------------------------------------------------------------------------------- 1 | Please do not submit a Pull Request via github. Our project makes use 2 | of mailing lists for patch submission and review. For more details 3 | please see 4 | https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842172/Create+and+Submit+a+Patch 5 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/zynq/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/zynq/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/zynq/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | &tmr_0_MB1_axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | &tmr_0_MB1_axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | &tmr_0_MB1_axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-vek280-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VEK280 revB 4 | * 5 | * (C) Copyright 2022, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sc-vek280-reva.dtsi" 11 | 12 | &{/} { 13 | compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", 14 | "xlnx,zynqmp-vek280", "xlnx,zynqmp"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-vek280-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VEK280 revB 4 | * 5 | * (C) Copyright 2022, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sc-vek280-reva.dtsi" 11 | 12 | &{/} { 13 | compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", 14 | "xlnx,zynqmp-vek280", "xlnx,zynqmp"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-vek280-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VEK280 revB 4 | * 5 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sc-vek280-reva.dtsi" 11 | 12 | &{/} { 13 | compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", 14 | "xlnx,zynqmp-vek280", "xlnx,zynqmp"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-vek280-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VEK280 revB 4 | * 5 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sc-vek280-reva.dtsi" 11 | 12 | &{/} { 13 | compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", 14 | "xlnx,zynqmp-vek280", "xlnx,zynqmp"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | bus-width = <8>; 15 | xlnx,mio-bank = <0>; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | bus-width = <8>; 15 | xlnx,mio-bank = <0>; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | bus-width = <8>; 15 | xlnx,mio-bank = <0>; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | bus-width = <8>; 15 | xlnx,mio-bank = <0>; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | bus-width = <8>; 15 | xlnx,mio-bank = <0>; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | bus-width = <8>; 15 | xlnx,mio-bank = <0>; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SM-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SM-K24 RevA"; 15 | compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal NET IPP/SPP OSPI 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-net-ipp-rev1.9.dtsi" 12 | 13 | / { 14 | model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; 15 | }; 16 | 17 | &ospi { 18 | status = "okay"; 19 | }; 20 | 21 | &qspi { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal NET IPP/SPP OSPI 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-net-ipp-rev1.9.dtsi" 12 | 13 | / { 14 | model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; 15 | }; 16 | 17 | &ospi { 18 | status = "okay"; 19 | }; 20 | 21 | &qspi { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k24-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K24 RevA"; 15 | compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | 19 | &sdhci0 { 20 | status = "disabled"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal NET IPP/SPP OSPI 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-net-ipp-rev1.9.dtsi" 12 | 13 | / { 14 | model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; 15 | }; 16 | 17 | &ospi { 18 | status = "okay"; 19 | }; 20 | 21 | &qspi { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-smk-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k24-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K24 RevA"; 15 | compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | 19 | &sdhci0 { 20 | status = "disabled"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022-2022 Xilinx, Inc. 4 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022-2022 Xilinx, Inc. 4 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022-2022 Xilinx, Inc. 4 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal NET IPP/SPP OSPI 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-net-ipp-rev1.9.dtsi" 12 | 13 | / { 14 | model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; 15 | }; 16 | 17 | &ospi { 18 | status = "okay"; 19 | }; 20 | 21 | &qspi { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-smk-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k24-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K24 RevA"; 15 | compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | 19 | &sdhci0 { 20 | status = "disabled"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal NET IPP/SPP OSPI 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-net-ipp-rev1.9.dtsi" 12 | 13 | / { 14 | model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; 15 | }; 16 | 17 | &ospi { 18 | status = "okay"; 19 | }; 20 | 21 | &qspi { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-smk-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k24-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K24 RevA"; 15 | compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | 19 | &sdhci0 { 20 | status = "disabled"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sm-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SM-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SM-K24 RevA/B/1"; 15 | compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", 16 | "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 17 | "xlnx,zynqmp"; 18 | }; 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022-2022 Xilinx, Inc. 4 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022-2022 Xilinx, Inc. 4 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sm-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SM-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SM-K24 RevA/B/1"; 15 | compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", 16 | "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 17 | "xlnx,zynqmp"; 18 | }; 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sm-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SM-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SM-K24 RevA/B/1"; 15 | compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", 16 | "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 17 | "xlnx,zynqmp"; 18 | }; 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | }; 18 | 19 | &dcc { 20 | status = "okay"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.17/board/zc1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | / { 13 | model = "ZynqMP ZC1275 RevA"; 14 | compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; 15 | 16 | aliases { 17 | serial0 = &uart0; 18 | serial1 = &dcc; 19 | }; 20 | }; 21 | 22 | &dcc { 23 | status = "okay"; 24 | }; 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.17/board/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | }; 22 | 23 | &dcc { 24 | status = "okay"; 25 | }; 26 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_SGMII 7 21 | 22 | #endif /* _DT_BINDINGS_PHY */ 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_SGMII 7 21 | 22 | #endif /* _DT_BINDINGS_PHY */ 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_SGMII 7 21 | 22 | #endif /* _DT_BINDINGS_PHY */ 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_SGMII 7 21 | 22 | #endif /* _DT_BINDINGS_PHY */ 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_SGMII 7 21 | 22 | #endif /* _DT_BINDINGS_PHY */ 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_SGMII 7 21 | 22 | #endif /* _DT_BINDINGS_PHY */ 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 16 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 17 | "xlnx,zynqmp"; 18 | }; 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 16 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 17 | "xlnx,zynqmp"; 18 | }; 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.0/board/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.0/board/zc1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1275 RevA"; 15 | compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.1/board/zc1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1275 RevA"; 15 | compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | }; 22 | 23 | &dcc { 24 | status = "okay"; 25 | }; 26 | 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.3/board/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.3/board/zc1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1275 RevA"; 15 | compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.18/board/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.18/board/zc1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1275 RevA"; 15 | compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.19/board/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.19/board/zc1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1275 RevA"; 15 | compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.20/board/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.20/board/zc1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1275 RevA"; 15 | compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.1/board/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.2/board/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.2/board/zc1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1275 RevA"; 15 | compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.4/board/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.4/board/zc1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1275 RevA"; 15 | compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | &dcc { 25 | status = "okay"; 26 | }; 27 | 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | }; 18 | 19 | &dcc { 20 | status = "okay"; 21 | }; 22 | 23 | &sdhci0 { 24 | no-1-8-v; 25 | }; 26 | 27 | &sdhci1 { 28 | no-1-8-v; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | }; 18 | 19 | &dcc { 20 | status = "okay"; 21 | }; 22 | 23 | &sdhci0 { 24 | no-1-8-v; 25 | }; 26 | 27 | &sdhci1 { 28 | no-1-8-v; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | }; 18 | 19 | &dcc { 20 | status = "okay"; 21 | }; 22 | 23 | &sdhci0 { 24 | no-1-8-v; 25 | }; 26 | 27 | &sdhci1 { 28 | no-1-8-v; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | }; 18 | 19 | &dcc { 20 | status = "okay"; 21 | }; 22 | 23 | &sdhci0 { 24 | no-1-8-v; 25 | }; 26 | 27 | &sdhci1 { 28 | no-1-8-v; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | }; 18 | 19 | &dcc { 20 | status = "okay"; 21 | }; 22 | 23 | &sdhci0 { 24 | no-1-8-v; 25 | }; 26 | 27 | &sdhci1 { 28 | no-1-8-v; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | }; 18 | 19 | &dcc { 20 | status = "okay"; 21 | }; 22 | 23 | &sdhci0 { 24 | no-1-8-v; 25 | }; 26 | 27 | &sdhci1 { 28 | no-1-8-v; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | }; 18 | 19 | &dcc { 20 | status = "okay"; 21 | }; 22 | 23 | &sdhci0 { 24 | no-1-8-v; 25 | }; 26 | 27 | &sdhci1 { 28 | no-1-8-v; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 16 | }; 17 | 18 | &qspi { 19 | #include "versal-x-ebm-01-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 16 | }; 17 | 18 | &qspi { 19 | #include "versal-x-ebm-01-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 16 | }; 17 | 18 | &qspi { 19 | #include "versal-x-ebm-01-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 16 | }; 17 | 18 | &qspi { 19 | #include "versal-x-ebm-01-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 16 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 17 | "xlnx,zynqmp"; 18 | }; 19 | 20 | &sdhci0 { 21 | status = "disabled"; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 16 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 17 | "xlnx,zynqmp"; 18 | }; 19 | 20 | &sdhci0 { 21 | status = "disabled"; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 16 | }; 17 | 18 | &qspi { 19 | #include "versal-x-ebm-01-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 16 | }; 17 | 18 | &qspi { 19 | #include "versal-x-ebm-01-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 16 | }; 17 | 18 | &ospi { 19 | #include "versal-x-ebm-03-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_XPCS 7 21 | #define PHY_TYPE_SGMII 8 22 | #define PHY_TYPE_QSGMII 9 23 | 24 | #endif /* _DT_BINDINGS_PHY */ 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 16 | }; 17 | 18 | &ospi { 19 | #include "versal-x-ebm-03-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_XPCS 7 21 | #define PHY_TYPE_SGMII 8 22 | #define PHY_TYPE_QSGMII 9 23 | 24 | #endif /* _DT_BINDINGS_PHY */ 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 16 | }; 17 | 18 | &ospi { 19 | #include "versal-x-ebm-03-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_XPCS 7 21 | #define PHY_TYPE_SGMII 8 22 | #define PHY_TYPE_QSGMII 9 23 | 24 | #endif /* _DT_BINDINGS_PHY */ 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 16 | }; 17 | 18 | &ospi { 19 | #include "versal-x-ebm-03-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_XPCS 7 21 | #define PHY_TYPE_SGMII 8 22 | #define PHY_TYPE_QSGMII 9 23 | 24 | #endif /* _DT_BINDINGS_PHY */ 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 16 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 17 | "xlnx,zynqmp"; 18 | }; 19 | 20 | &sdhci0 { 21 | status = "disabled"; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_XPCS 7 21 | #define PHY_TYPE_SGMII 8 22 | #define PHY_TYPE_QSGMII 9 23 | 24 | #endif /* _DT_BINDINGS_PHY */ 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 16 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 17 | "xlnx,zynqmp"; 18 | }; 19 | 20 | &sdhci0 { 21 | status = "disabled"; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_XPCS 7 21 | #define PHY_TYPE_SGMII 8 22 | #define PHY_TYPE_QSGMII 9 23 | 24 | #endif /* _DT_BINDINGS_PHY */ 25 | -------------------------------------------------------------------------------- /apmps/data/apmps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2019-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /canps/data/canps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /ddrcps/data/ddrcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /devcfg/data/devcfg.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-04 revA (SE4) 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" 12 | 13 | / { 14 | chosen { 15 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 16 | stdout-path = "serial0:115200"; 17 | }; 18 | 19 | aliases { 20 | spi0 = &ospi; 21 | }; 22 | }; 23 | 24 | &qspi { 25 | status = "disabled"; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-04 revA (SE4) 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" 12 | 13 | / { 14 | chosen { 15 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 16 | stdout-path = "serial0:115200"; 17 | }; 18 | 19 | aliases { 20 | spi0 = &ospi; 21 | }; 22 | }; 23 | 24 | &qspi { 25 | status = "disabled"; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 16 | }; 17 | 18 | &ospi { 19 | #include "versal-x-ebm-03-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 16 | }; 17 | 18 | &ospi { 19 | #include "versal-x-ebm-03-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /ocmcps/data/ocmcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /pmups/data/pmups.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /scuwdt/data/scuwdt.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /smccps/data/smccps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /ttcps/data/ttcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /wdtps/data/wdtps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /xadcps/data/xadcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /canfdps/data/canfdps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2019-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-04 revA (SE4) 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" 12 | 13 | / { 14 | chosen { 15 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 16 | stdout-path = "serial0:115200"; 17 | }; 18 | 19 | aliases { 20 | spi0 = &ospi; 21 | }; 22 | }; 23 | 24 | &qspi { 25 | status = "disabled"; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-04 revA (SE4) 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" 12 | 13 | / { 14 | chosen { 15 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 16 | stdout-path = "serial0:115200"; 17 | }; 18 | 19 | aliases { 20 | spi0 = &ospi; 21 | }; 22 | }; 23 | 24 | &qspi { 25 | status = "disabled"; 26 | }; 27 | -------------------------------------------------------------------------------- /pl310ps/data/pl310ps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /scutimer/data/scutimer.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /axi_tft/data/axi_tft.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2019.1/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze sp701. 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Venkatesh Yadav Abbarapu 9 | */ 10 | 11 | &axi_ethernet_0 { 12 | phy-handle = <&phy0>; 13 | /delete-node/ mdio; 14 | axi_ethernet_mdio: mdio { 15 | #address-cells = <1>; 16 | #size-cells = <0>; 17 | phy0: phy@1 { 18 | device_type = "ethernet-phy"; 19 | reg = <1>; 20 | ti,rx-internal-delay = <0x3>; 21 | ti,tx-internal-delay = <0x3>; 22 | ti,fifo-depth = <0x1>; 23 | }; 24 | }; 25 | }; 26 | -------------------------------------------------------------------------------- /axi_sysace/data/axi_sysace.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | 19 | -------------------------------------------------------------------------------- /globaltimerps/data/globaltimerps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2020.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | &axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | &axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | &axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | &axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | &axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | i * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | &axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | aliases { 18 | serial2 = &dcc; 19 | }; 20 | }; 21 | 22 | &dcc { 23 | status = "okay"; 24 | }; 25 | 26 | &sdhci0 { 27 | no-1-8-v; 28 | }; 29 | 30 | &sdhci1 { 31 | no-1-8-v; 32 | }; 33 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | aliases { 18 | serial2 = &dcc; 19 | }; 20 | }; 21 | 22 | &dcc { 23 | status = "okay"; 24 | }; 25 | 26 | &sdhci0 { 27 | no-1-8-v; 28 | }; 29 | 30 | &sdhci1 { 31 | no-1-8-v; 32 | }; 33 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | aliases { 18 | serial2 = &dcc; 19 | }; 20 | }; 21 | 22 | &dcc { 23 | status = "okay"; 24 | }; 25 | 26 | &sdhci0 { 27 | no-1-8-v; 28 | }; 29 | 30 | &sdhci1 { 31 | no-1-8-v; 32 | }; 33 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2021.2/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Venkatesh Yadav Abbarapu 9 | */ 10 | 11 | &tmr_0_MB1_axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Venkatesh Yadav Abbarapu 9 | */ 10 | 11 | &tmr_0_MB1_axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Venkatesh Yadav Abbarapu 9 | */ 10 | 11 | &tmr_0_MB1_axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105-tmr. 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Venkatesh Yadav Abbarapu 9 | */ 10 | 11 | &tmr_0_MB1_axi_iic_0 { 12 | #address-cells = <1>; 13 | #size-cells = <0>; 14 | i2c-mux@75 { 15 | compatible = "nxp,pca9544"; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reg = <0x75>; 19 | i2c@3 { 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <3>; 23 | eeprom@54 { 24 | compatible = "atmel,24c08"; 25 | reg = <0x54>; 26 | }; 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 16 | 17 | aliases { 18 | spi0 = &ospi; 19 | }; 20 | }; 21 | 22 | &ospi { 23 | #include "versal-x-ebm-03-reva.dtsi" 24 | }; 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 16 | 17 | aliases { 18 | spi0 = &ospi; 19 | }; 20 | }; 21 | 22 | &ospi { 23 | #include "versal-x-ebm-03-reva.dtsi" 24 | }; 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 16 | 17 | aliases { 18 | spi0 = &ospi; 19 | }; 20 | }; 21 | 22 | &ospi { 23 | #include "versal-x-ebm-03-reva.dtsi" 24 | }; 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 16 | 17 | aliases { 18 | spi0 = &ospi; 19 | }; 20 | }; 21 | 22 | &ospi { 23 | #include "versal-x-ebm-03-reva.dtsi" 24 | }; 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 16 | 17 | aliases { 18 | spi0 = &ospi; 19 | }; 20 | }; 21 | 22 | &ospi { 23 | #include "versal-x-ebm-03-reva.dtsi" 24 | }; 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 16 | 17 | aliases { 18 | spi0 = &ospi; 19 | }; 20 | }; 21 | 22 | &ospi { 23 | #include "versal-x-ebm-03-reva.dtsi" 24 | }; 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-vn-p-b2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) 4 | * 5 | * (C) Copyright 2022, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "xlnx,versal-net-vn-p-b2197-00-revA", 13 | "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; 14 | }; 15 | 16 | &i2c0 { 17 | /* Access via J70/J71 or J82/J83 */ 18 | clock-frequency = <100000>; 19 | }; 20 | 21 | &i2c1 { 22 | /* Access via J70/J71 or J82/J83 */ 23 | /* By default this bus should have eeprom for board identification at 0x54 */ 24 | /* SE/X-PRC card identification is also on this bus at 0x52 */ 25 | clock-frequency = <100000>; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-vn-p-b2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) 4 | * 5 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "xlnx,versal-net-vn-p-b2197-00-revA", 13 | "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; 14 | }; 15 | 16 | &i2c0 { 17 | /* Access via J70/J71 or J82/J83 */ 18 | clock-frequency = <100000>; 19 | }; 20 | 21 | &i2c1 { 22 | /* Access via J70/J71 or J82/J83 */ 23 | /* By default this bus should have eeprom for board identification at 0x54 */ 24 | /* SE/X-PRC card identification is also on this bus at 0x52 */ 25 | clock-frequency = <100000>; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-vn-p-b2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) 4 | * 5 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "xlnx,versal-net-vn-p-b2197-00-revA", 13 | "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; 14 | }; 15 | 16 | &i2c0 { 17 | /* Access via J70/J71 or J82/J83 */ 18 | clock-frequency = <100000>; 19 | }; 20 | 21 | &i2c1 { 22 | /* Access via J70/J71 or J82/J83 */ 23 | /* By default this bus should have eeprom for board identification at 0x54 */ 24 | /* SE/X-PRC card identification is also on this bus at 0x52 */ 25 | clock-frequency = <100000>; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2017.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | i * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2cswitch@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "at,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2017.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2cswitch@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "at,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2017.3/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2cswitch@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "at,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2017.4/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2cswitch@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "at,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2018.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2cswitch@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "at,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2018.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2cswitch@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "at,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2018.3/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2cswitch@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "at,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2019.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2c-mux@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "atmel,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2019.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2c-mux@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "atmel,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2020.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx Microblaze kcu105. 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Naga Sureshkumar Relli 9 | */ 10 | 11 | / { 12 | hard-reset-gpios = <&reset_gpio 0 1>; 13 | }; 14 | 15 | &iic_main { 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | i2c-mux@75 { 19 | compatible = "nxp,pca9544"; 20 | #address-cells = <1>; 21 | #size-cells = <0>; 22 | reg = <0x75>; 23 | i2c@3 { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | reg = <3>; 27 | eeprom@54 { 28 | compatible = "atmel,24c08"; 29 | reg = <0x54>; 30 | }; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-node/ mdio; 4 | axi_ethernet_mdio: mdio { 5 | #address-cells = <1>; 6 | #size-cells = <0>; 7 | phy0: phy@1 { 8 | device_type = "ethernet-phy"; 9 | reg = <1>; 10 | ti,rx-internal-delay = <0x3>; 11 | ti,tx-internal-delay = <0x3>; 12 | ti,fifo-depth = <0x1>; 13 | }; 14 | }; 15 | }; 16 | 17 | &axi_iic_0 { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | i2c-mux@75 { 21 | compatible = "nxp,pca9548"; 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | reg = <0x75>; 25 | i2c@0 { 26 | #address-cells = <1>; 27 | #size-cells = <0>; 28 | reg = <0>; 29 | eeprom@50 { 30 | compatible = "atmel,24c08"; 31 | reg = <0x50>; 32 | }; 33 | }; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-node/ mdio; 4 | axi_ethernet_mdio: mdio { 5 | #address-cells = <1>; 6 | #size-cells = <0>; 7 | phy0: phy@1 { 8 | device_type = "ethernet-phy"; 9 | reg = <1>; 10 | ti,rx-internal-delay = <0x3>; 11 | ti,tx-internal-delay = <0x3>; 12 | ti,fifo-depth = <0x1>; 13 | }; 14 | }; 15 | }; 16 | 17 | &axi_iic_0 { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | i2c-mux@75 { 21 | compatible = "nxp,pca9548"; 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | reg = <0x75>; 25 | i2c@0 { 26 | #address-cells = <1>; 27 | #size-cells = <0>; 28 | reg = <0>; 29 | eeprom@50 { 30 | compatible = "atmel,24c08"; 31 | reg = <0x50>; 32 | }; 33 | }; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-node/ mdio; 4 | axi_ethernet_mdio: mdio { 5 | #address-cells = <1>; 6 | #size-cells = <0>; 7 | phy0: phy@1 { 8 | device_type = "ethernet-phy"; 9 | reg = <1>; 10 | ti,rx-internal-delay = <0x3>; 11 | ti,tx-internal-delay = <0x3>; 12 | ti,fifo-depth = <0x1>; 13 | }; 14 | }; 15 | }; 16 | 17 | &axi_iic_0 { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | i2c-mux@75 { 21 | compatible = "nxp,pca9548"; 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | reg = <0x75>; 25 | i2c@0 { 26 | #address-cells = <1>; 27 | #size-cells = <0>; 28 | reg = <0>; 29 | eeprom@50 { 30 | compatible = "atmel,24c08"; 31 | reg = <0x50>; 32 | }; 33 | }; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <1>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | is-dual = <1>; 17 | flash@0 { 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 21 | reg = <0>; 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; 24 | spi-max-frequency = <150000000>; 25 | partition@0 { 26 | label = "spi0-flash0"; 27 | reg = <0x0 0x10000000>; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <1>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | is-dual = <1>; 17 | flash@0 { 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 21 | reg = <0>; 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; 24 | spi-max-frequency = <150000000>; 25 | partition@0 { 26 | label = "spi0-flash0"; 27 | reg = <0x0 0x10000000>; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-vn-p-b2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) 4 | * 5 | * (C) Copyright 2022, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-net.dtsi" 11 | #include "versal-net-clk-ccf.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-net-vn-p-b2197-00-revA", 15 | "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; 16 | }; 17 | 18 | &i2c0 { 19 | /* Access via J70/J71 or J82/J83 */ 20 | clock-frequency = <100000>; 21 | }; 22 | 23 | &i2c1 { 24 | /* Access via J70/J71 or J82/J83 */ 25 | /* By default this bus should have eeprom for board identification at 0x54 */ 26 | /* SE/X-PRC card identification is also on this bus at 0x52 */ 27 | clock-frequency = <100000>; 28 | }; 29 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020-2022 Xilinx, Inc. 6 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | /* Bit values for Pin drive strength */ 21 | #define DRIVE_STRENGTH_2MA 2 22 | #define DRIVE_STRENGTH_4MA 4 23 | #define DRIVE_STRENGTH_8MA 8 24 | #define DRIVE_STRENGTH_12MA 12 25 | 26 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020-2022 Xilinx, Inc. 6 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | /* Bit values for Pin drive strength */ 21 | #define DRIVE_STRENGTH_2MA 2 22 | #define DRIVE_STRENGTH_4MA 4 23 | #define DRIVE_STRENGTH_8MA 8 24 | #define DRIVE_STRENGTH_12MA 12 25 | 26 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020-2022 Xilinx, Inc. 6 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | /* Bit values for Pin drive strength */ 21 | #define DRIVE_STRENGTH_2MA 2 22 | #define DRIVE_STRENGTH_4MA 4 23 | #define DRIVE_STRENGTH_8MA 8 24 | #define DRIVE_STRENGTH_12MA 12 25 | 26 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020-2022 Xilinx, Inc. 6 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | /* Bit values for Pin drive strength */ 21 | #define DRIVE_STRENGTH_2MA 2 22 | #define DRIVE_STRENGTH_4MA 4 23 | #define DRIVE_STRENGTH_8MA 8 24 | #define DRIVE_STRENGTH_12MA 12 25 | 26 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020-2022 Xilinx, Inc. 6 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | /* Bit values for Pin drive strength */ 21 | #define DRIVE_STRENGTH_2MA 2 22 | #define DRIVE_STRENGTH_4MA 4 23 | #define DRIVE_STRENGTH_8MA 8 24 | #define DRIVE_STRENGTH_12MA 12 25 | 26 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020-2022 Xilinx, Inc. 6 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | /* Bit values for Pin drive strength */ 21 | #define DRIVE_STRENGTH_2MA 2 22 | #define DRIVE_STRENGTH_4MA 4 23 | #define DRIVE_STRENGTH_8MA 8 24 | #define DRIVE_STRENGTH_12MA 12 25 | 26 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 27 | -------------------------------------------------------------------------------- /ramps/data/ramps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | set ip [get_cells -hier $drv_handle] 18 | if { [string match -nocase $ip "ps7_ram_1"] } { 19 | set_property NAME none $drv_handle 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <2>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | flash@0 { 17 | #address-cells = <1>; 18 | #size-cells = <1>; 19 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 20 | reg = <0>, <1>; 21 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; 24 | spi-max-frequency = <150000000>; 25 | partition@0 { 26 | label = "spi0-flash0"; 27 | reg = <0x0 0x10000000>; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <2>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | flash@0 { 17 | #address-cells = <1>; 18 | #size-cells = <1>; 19 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 20 | reg = <0>, <1>; 21 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; 24 | spi-max-frequency = <150000000>; 25 | partition@0 { 26 | label = "spi0-flash0"; 27 | reg = <0x0 0x10000000>; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /generic/data/generic.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | OPTION psf_version = 3.0; 17 | 18 | BEGIN driver generic 19 | 20 | OPTION NAME = generic; 21 | OPTION supported_os_types = (DTS); 22 | DTGPARAM name = dtg.ip_params, type = boolean; 23 | 24 | END driver 25 | -------------------------------------------------------------------------------- /RM/data/RM.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2017-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | set val [get_property FAMILY [get_hw_designs]] 18 | switch -glob $val { 19 | "zynq" { 20 | hsi::utils::add_new_property $drv_handle "fpga-mgr" string "<&devcfg>" 21 | } 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc5.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP zc1751-xm019-dc5 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Siva Durga Prasad 9 | * Michal Simek 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP zc1751-xm019-dc5 RevA"; 15 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | ethernet0 = &gem1; 19 | i2c0 = &i2c0; 20 | i2c1 = &i2c1; 21 | mmc0 = &sdhci0; 22 | serial0 = &uart0; 23 | serial1 = &uart1; 24 | }; 25 | }; 26 | 27 | &gem1 { 28 | status = "okay"; 29 | phy-handle = <&phy0>; 30 | phy-mode = "rgmii-id"; 31 | phy0: phy@0 { 32 | reg = <0>; 33 | }; 34 | }; 35 | 36 | &sdhci0 { 37 | status = "okay"; 38 | no-1-8-v; 39 | }; 40 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc5.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP zc1751-xm019-dc5 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Siva Durga Prasad 9 | * Michal Simek 10 | */ 11 | 12 | / { 13 | model = "ZynqMP zc1751-xm019-dc5 RevA"; 14 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 15 | 16 | aliases { 17 | ethernet0 = &gem1; 18 | i2c0 = &i2c0; 19 | i2c1 = &i2c1; 20 | mmc0 = &sdhci0; 21 | serial0 = &uart0; 22 | serial1 = &uart1; 23 | }; 24 | 25 | }; 26 | 27 | &gem1 { 28 | status = "okay"; 29 | phy-handle = <&phy0>; 30 | phy-mode = "rgmii-id"; 31 | phy0: phy@0 { 32 | reg = <0>; 33 | }; 34 | }; 35 | 36 | &sdhci0 { 37 | status = "okay"; 38 | no-1-8-v; 39 | }; 40 | -------------------------------------------------------------------------------- /isppipeline/data/ispipeline.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | OPTION psf_version = 3.0; 16 | 17 | BEGIN driver ispipeline 18 | 19 | OPTION supported_peripherals = (ISPPipeline_accel); 20 | OPTION supported_os_types = (DTS); 21 | OPTION driver_state = ACTIVE; 22 | OPTION NAME = ispipeline; 23 | 24 | END driver 25 | -------------------------------------------------------------------------------- /vtc/data/vtc.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | OPTION psf_version = 3.0; 17 | 18 | BEGIN driver vtc 19 | 20 | OPTION supported_peripherals = (v_tc); 21 | OPTION supported_os_types = (DTS); 22 | OPTION driver_state = ACTIVE; 23 | OPTION NAME = vtc; 24 | 25 | END driver 26 | -------------------------------------------------------------------------------- /ams/data/ams.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2017-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | OPTION psf_version = 3.0; 17 | 18 | BEGIN driver ams 19 | 20 | OPTION supported_peripherals = (psu_ams); 21 | OPTION supported_os_types = (DTS); 22 | OPTION driver_state = ACTIVE; 23 | OPTION NAME = ams; 24 | 25 | END driver 26 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <2>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | is-dual = <1>; 17 | flash@0 { 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 21 | reg = <0>, <1>; 22 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 23 | spi-tx-bus-width = <4>; 24 | spi-rx-bus-width = <4>; 25 | spi-max-frequency = <150000000>; 26 | partition@0 { 27 | label = "spi0-flash0"; 28 | reg = <0x0 0x10000000>; 29 | }; 30 | }; 31 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <2>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | is-dual = <1>; 17 | flash@0 { 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 21 | reg = <0>, <1>; 22 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 23 | spi-tx-bus-width = <4>; 24 | spi-rx-bus-width = <4>; 25 | spi-max-frequency = <150000000>; 26 | partition@0 { 27 | label = "spi0-flash0"; 28 | reg = <0x0 0x10000000>; 29 | }; 30 | }; 31 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc5.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP zc1751-xm019-dc5 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Siva Durga Prasad 9 | * Michal Simek 10 | */ 11 | 12 | / { 13 | model = "ZynqMP zc1751-xm019-dc5 RevA"; 14 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 15 | 16 | aliases { 17 | ethernet0 = &gem1; 18 | i2c0 = &i2c0; 19 | i2c1 = &i2c1; 20 | mmc0 = &sdhci0; 21 | serial0 = &uart0; 22 | serial1 = &uart1; 23 | }; 24 | 25 | }; 26 | 27 | &gem1 { 28 | status = "okay"; 29 | phy-handle = <&phy0>; 30 | phy-mode = "rgmii-id"; 31 | phy0: phy@0 { 32 | reg = <0>; 33 | }; 34 | }; 35 | 36 | &sdhci0 { 37 | status = "okay"; 38 | no-1-8-v; 39 | }; 40 | 41 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc5.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP zc1751-xm019-dc5 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Siva Durga Prasad 9 | * Michal Simek 10 | */ 11 | 12 | / { 13 | model = "ZynqMP zc1751-xm019-dc5 RevA"; 14 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 15 | 16 | aliases { 17 | ethernet0 = &gem1; 18 | i2c0 = &i2c0; 19 | i2c1 = &i2c1; 20 | mmc0 = &sdhci0; 21 | serial0 = &uart0; 22 | serial1 = &uart1; 23 | }; 24 | 25 | }; 26 | 27 | &gem1 { 28 | status = "okay"; 29 | phy-handle = <&phy0>; 30 | phy-mode = "rgmii-id"; 31 | phy0: phy@0 { 32 | reg = <0>; 33 | }; 34 | }; 35 | 36 | &sdhci0 { 37 | status = "okay"; 38 | no-1-8-v; 39 | }; 40 | 41 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc5.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP zc1751-xm019-dc5 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Siva Durga Prasad 9 | * Michal Simek 10 | */ 11 | 12 | / { 13 | model = "ZynqMP zc1751-xm019-dc5 RevA"; 14 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 15 | 16 | aliases { 17 | ethernet0 = &gem1; 18 | i2c0 = &i2c0; 19 | i2c1 = &i2c1; 20 | mmc0 = &sdhci0; 21 | serial0 = &uart0; 22 | serial1 = &uart1; 23 | }; 24 | 25 | }; 26 | 27 | &gem1 { 28 | status = "okay"; 29 | phy-handle = <&phy0>; 30 | phy-mode = "rgmii-id"; 31 | phy0: phy@0 { 32 | reg = <0>; 33 | }; 34 | }; 35 | 36 | &sdhci0 { 37 | status = "okay"; 38 | no-1-8-v; 39 | }; 40 | 41 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc5.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP zc1751-xm019-dc5 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Siva Durga Prasad 9 | * Michal Simek 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP zc1751-xm019-dc5 RevA"; 15 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | ethernet0 = &gem1; 19 | i2c0 = &i2c0; 20 | i2c1 = &i2c1; 21 | mmc0 = &sdhci0; 22 | serial0 = &uart0; 23 | serial1 = &uart1; 24 | }; 25 | 26 | }; 27 | 28 | &gem1 { 29 | status = "okay"; 30 | phy-handle = <&phy0>; 31 | phy-mode = "rgmii-id"; 32 | phy0: phy@0 { 33 | reg = <0>; 34 | }; 35 | }; 36 | 37 | &sdhci0 { 38 | status = "okay"; 39 | no-1-8-v; 40 | }; 41 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc5.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP zc1751-xm019-dc5 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Siva Durga Prasad 9 | * Michal Simek 10 | */ 11 | 12 | / { 13 | model = "ZynqMP zc1751-xm019-dc5 RevA"; 14 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 15 | 16 | aliases { 17 | ethernet0 = &gem1; 18 | i2c0 = &i2c0; 19 | i2c1 = &i2c1; 20 | mmc0 = &sdhci0; 21 | serial0 = &uart0; 22 | serial1 = &uart1; 23 | }; 24 | 25 | }; 26 | 27 | &gem1 { 28 | status = "okay"; 29 | phy-handle = <&phy0>; 30 | phy-mode = "rgmii-id"; 31 | phy0: phy@0 { 32 | reg = <0>; 33 | }; 34 | }; 35 | 36 | &sdhci0 { 37 | status = "okay"; 38 | no-1-8-v; 39 | }; 40 | 41 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc5.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP zc1751-xm019-dc5 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Siva Durga Prasad 9 | * Michal Simek 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP zc1751-xm019-dc5 RevA"; 15 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | ethernet0 = &gem1; 19 | i2c0 = &i2c0; 20 | i2c1 = &i2c1; 21 | mmc0 = &sdhci0; 22 | serial0 = &uart0; 23 | serial1 = &uart1; 24 | }; 25 | 26 | }; 27 | 28 | &gem1 { 29 | status = "okay"; 30 | phy-handle = <&phy0>; 31 | phy-mode = "rgmii-id"; 32 | phy0: phy@0 { 33 | reg = <0>; 34 | }; 35 | }; 36 | 37 | &sdhci0 { 38 | status = "okay"; 39 | no-1-8-v; 40 | }; 41 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc5.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP zc1751-xm019-dc5 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Siva Durga Prasad 9 | * Michal Simek 10 | */ 11 | 12 | / { 13 | model = "ZynqMP zc1751-xm019-dc5 RevA"; 14 | compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 15 | 16 | aliases { 17 | ethernet0 = &gem1; 18 | i2c0 = &i2c0; 19 | i2c1 = &i2c1; 20 | mmc0 = &sdhci0; 21 | serial0 = &uart0; 22 | serial1 = &uart1; 23 | }; 24 | 25 | }; 26 | 27 | &gem1 { 28 | status = "okay"; 29 | phy-handle = <&phy0>; 30 | phy-mode = "rgmii-id"; 31 | phy0: phy@0 { 32 | reg = <0>; 33 | }; 34 | }; 35 | 36 | &sdhci0 { 37 | status = "okay"; 38 | no-1-8-v; 39 | }; 40 | 41 | -------------------------------------------------------------------------------- /dp/data/dp.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | OPTION psf_version = 3.0; 17 | 18 | BEGIN driver dp 19 | 20 | OPTION supported_peripherals = (psu_dp psv_dp); 21 | OPTION supported_os_types = (DTS); 22 | OPTION driver_state = ACTIVE; 23 | OPTION NAME = dp; 24 | 25 | END driver 26 | -------------------------------------------------------------------------------- /tpg/data/tpg.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | OPTION psf_version = 3.0; 17 | 18 | BEGIN driver tpg 19 | 20 | OPTION supported_peripherals = (v_tpg); 21 | OPTION supported_os_types = (DTS); 22 | OPTION driver_state = ACTIVE; 23 | OPTION NAME = tpg; 24 | 25 | END driver 26 | -------------------------------------------------------------------------------- /mixer/data/mixer.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | OPTION psf_version = 3.0; 17 | 18 | BEGIN driver mixer 19 | 20 | OPTION supported_peripherals = (v_mix); 21 | OPTION supported_os_types = (DTS); 22 | OPTION driver_state = ACTIVE; 23 | OPTION NAME = mixer; 24 | 25 | END driver 26 | -------------------------------------------------------------------------------- /apmps/data/apmps.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2019-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | OPTION psf_version = 3.0; 17 | 18 | BEGIN driver apmps 19 | OPTION supported_peripherals = (psu_apm psv_apm psx_apm); 20 | OPTION supported_os_types = (DTS); 21 | OPTION driver_state = ACTIVE; 22 | OPTION NAME = apmps; 23 | END driver 24 | -------------------------------------------------------------------------------- /axi_vcu/data/axi_vcu.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2017-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | OPTION psf_version = 3.0; 17 | 18 | BEGIN driver axi_vcu 19 | 20 | OPTION supported_peripherals = (vcu); 21 | OPTION supported_os_types = (DTS); 22 | OPTION driver_state = ACTIVE; 23 | OPTION NAME = axi_vcu; 24 | 25 | END driver 26 | -------------------------------------------------------------------------------- /axi_vdu/data/axi_vdu.mdd: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2017-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | OPTION psf_version = 3.0; 17 | 18 | BEGIN driver axi_vdu 19 | 20 | OPTION supported_peripherals = (vdu); 21 | OPTION supported_os_types = (DTS); 22 | OPTION driver_state = ACTIVE; 23 | OPTION NAME = axi_vdu; 24 | 25 | END driver 26 | -------------------------------------------------------------------------------- /dmaps/data/dmaps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generate {drv_handle} { 17 | set ip [get_cells -hier $drv_handle] 18 | 19 | #disabling non-secure dma 20 | if { [string match -nocase $ip "ps7_dma_ns"] } { 21 | set_property NAME none $drv_handle 22 | } 23 | } 24 | --------------------------------------------------------------------------------