├── .gitignore ├── tegra20 ├── avionic-design │ ├── tec │ │ ├── tegra20-tec.img.cfg │ │ ├── Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg │ │ ├── build.sh │ │ └── Makefile │ ├── plutux │ │ ├── tegra20-plutux.img.cfg │ │ ├── Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg │ │ ├── build.sh │ │ └── Makefile │ ├── medcom-wide │ │ ├── tegra20-medcom-wide.img.cfg │ │ ├── Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg │ │ ├── build.sh │ │ └── Makefile │ └── tamonten │ │ ├── tegra20.img.cfg │ │ └── Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg ├── nvidia │ ├── harmony │ │ ├── build.sh │ │ ├── harmony-nand.img.cfg │ │ ├── Makefile │ │ └── harmony_a02_12Mhz_H5PS1G83EFR-S6C_333Mhz_1GB_2K8Nand_HY27UF084G2B-TP.bct.cfg │ ├── seaboard │ │ ├── build.sh │ │ ├── seaboard-nand.img.cfg │ │ ├── Makefile │ │ └── PM282_Hynix_1GB_H5PS2G83AFR-S6C_380MHz_nand.bct.cfg │ └── ventana │ │ ├── build.sh │ │ ├── ventana-emmc.img.cfg │ │ ├── Makefile │ │ └── ventana_A03_12MHz_EDB8132B1PB6DF_300Mhz_1GB_emmc_THGBM1G6D4EBAI4.bct.cfg ├── compulab │ └── trimslice │ │ ├── build.sh │ │ ├── trimslice-spi.img.cfg │ │ ├── README.txt │ │ ├── trimslice-mmc.img.cfg │ │ ├── Makefile │ │ ├── trimslice-spi.bct.cfg │ │ └── trimslice-mmc.bct.cfg └── toradex │ └── colibri_t20 │ ├── build.sh │ ├── colibri_t20-256-hsmmc.img.cfg │ ├── colibri_t20-512-hsmmc.img.cfg │ ├── colibri_t20-256-v11-nand.img.cfg │ ├── colibri_t20-256-v12-nand.img.cfg │ ├── colibri_t20-512-v11-nand.img.cfg │ ├── colibri_t20-512-v12-nand.img.cfg │ ├── Makefile │ ├── colibri_t20-256-hsmmc.bct.cfg │ ├── colibri_t20-512-hsmmc.bct.cfg │ └── colibri_t20-256-v11-nand.bct.cfg ├── tegra30 ├── avionic-design │ ├── tec-ng │ │ ├── tegra30-tec-ng.img.cfg │ │ ├── TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct.cfg │ │ ├── build.sh │ │ └── Makefile │ └── tamonten-ng │ │ ├── tegra30.img.cfg │ │ └── TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct.cfg ├── nvidia │ ├── beaver │ │ ├── build.sh │ │ ├── beaver-emmc.img.cfg │ │ └── Makefile │ └── cardhu │ │ ├── build.sh │ │ ├── cardhu-a05-2gb-emmc.img.cfg │ │ ├── cardhu-a02-a04-1gb-emmc.img.cfg │ │ ├── cardhu-a02-a04-2gb-emmc.img.cfg │ │ ├── Makefile │ │ └── README.txt └── toradex │ └── colibri_t30 │ ├── build.sh │ ├── colibri_t30.img.cfg │ └── Makefile ├── tegra114 └── nvidia │ └── dalmore │ ├── README.txt │ ├── build.sh │ ├── dalmore-t40s-1600.img.cfg │ ├── dalmore-t40s-1866.img.cfg │ ├── dalmore-t40x-1866.img.cfg │ └── Makefile ├── tegra124 └── nvidia │ ├── norrin │ ├── build.sh │ ├── norrin-spi.img.cfg │ └── Makefile │ ├── venice2 │ ├── build.sh │ ├── venice2-spi.img.cfg │ └── Makefile │ └── jetson-tk1 │ ├── build.sh │ ├── jetson-tk1-emmc.img.cfg │ └── Makefile └── README.txt /.gitignore: -------------------------------------------------------------------------------- 1 | .*.d 2 | .*.swp 3 | *.bct 4 | *.img 5 | u-boot.bin 6 | -------------------------------------------------------------------------------- /tegra20/avionic-design/tec/tegra20-tec.img.cfg: -------------------------------------------------------------------------------- 1 | ../tamonten/tegra20.img.cfg -------------------------------------------------------------------------------- /tegra20/avionic-design/plutux/tegra20-plutux.img.cfg: -------------------------------------------------------------------------------- 1 | ../tamonten/tegra20.img.cfg -------------------------------------------------------------------------------- /tegra30/avionic-design/tec-ng/tegra30-tec-ng.img.cfg: -------------------------------------------------------------------------------- 1 | ../tamonten-ng/tegra30.img.cfg -------------------------------------------------------------------------------- /tegra20/avionic-design/medcom-wide/tegra20-medcom-wide.img.cfg: -------------------------------------------------------------------------------- 1 | ../tamonten/tegra20.img.cfg -------------------------------------------------------------------------------- /tegra20/avionic-design/plutux/Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg: -------------------------------------------------------------------------------- 1 | ../tamonten/Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg -------------------------------------------------------------------------------- /tegra20/avionic-design/tec/Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg: -------------------------------------------------------------------------------- 1 | ../tamonten/Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg -------------------------------------------------------------------------------- /tegra20/avionic-design/medcom-wide/Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg: -------------------------------------------------------------------------------- 1 | ../tamonten/Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg -------------------------------------------------------------------------------- /tegra30/avionic-design/tec-ng/TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct.cfg: -------------------------------------------------------------------------------- 1 | ../tamonten-ng/TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct.cfg -------------------------------------------------------------------------------- /tegra114/nvidia/dalmore/README.txt: -------------------------------------------------------------------------------- 1 | Three different BCTs exist for Dalmore. To determine which to use, please 2 | determine your SoC SKU (T40X or T40S), and SDRAM frequency (1866MHz, or 3 | 1600MHz). 4 | 5 | The image filenames (*.img.cfg) are named based on which SoC SKU and SDRAM 6 | frequency they support. You can look inside these files, at the Bctfile line, 7 | to determine which BCT to use for each configuration. 8 | -------------------------------------------------------------------------------- /tegra114/nvidia/dalmore/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra124/nvidia/norrin/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra124/nvidia/venice2/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra20/nvidia/harmony/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra20/nvidia/seaboard/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra20/nvidia/ventana/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra30/nvidia/beaver/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra30/nvidia/cardhu/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra124/nvidia/jetson-tk1/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra20/avionic-design/plutux/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra20/avionic-design/tec/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra20/compulab/trimslice/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra30/avionic-design/tec-ng/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra30/toradex/colibri_t30/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra20/avionic-design/medcom-wide/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # 5 | # This software is provided 'as-is', without any express or implied 6 | # warranty. In no event will the authors be held liable for any damages 7 | # arising from the use of this software. 8 | # 9 | # Permission is granted to anyone to use this software for any purpose, 10 | # including commercial applications, and to alter it and redistribute it 11 | # freely, subject to the following restrictions: 12 | # 13 | # 1. The origin of this software must not be misrepresented; you must not 14 | # claim that you wrote the original software. If you use this software 15 | # in a product, an acknowledgment in the product documentation would be 16 | # appreciated but is not required. 17 | # 2. Altered source versions must be plainly marked as such, and must not be 18 | # misrepresented as being the original software. 19 | # 3. This notice may not be removed or altered from any source distribution. 20 | 21 | make 22 | -------------------------------------------------------------------------------- /tegra20/compulab/trimslice/trimslice-spi.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctfile = trimslice-spi.bct; 21 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 22 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/colibri_t20-256-hsmmc.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Lucas Stach 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = colibri_t20-256-hsmmc.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/colibri_t20-512-hsmmc.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Lucas Stach 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = colibri_t20-512-hsmmc.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/colibri_t20-256-v11-nand.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Lucas Stach 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = colibri_t20-256-v11-nand.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/colibri_t20-256-v12-nand.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Lucas Stach 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = colibri_t20-256-v12-nand.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/colibri_t20-512-v11-nand.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Lucas Stach 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = colibri_t20-512-v11-nand.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/colibri_t20-512-v12-nand.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Lucas Stach 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = colibri_t20-512-v12-nand.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra20/avionic-design/tamonten/tegra20.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2013 Avionic Design GmbH 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra20/compulab/trimslice/README.txt: -------------------------------------------------------------------------------- 1 | The TrimSlice board is designed and sold by CompuLab, and is not an NVIDIA 2 | reference board. The configuration files here are graciously provided by 3 | CompuLab and relicensed with their permission for inclusion in this 4 | repository. 5 | 6 | The files in this directory were derived from CompuLab's repository, 7 | available at: 8 | 9 | git://gitorious.org/cbootimage/cbootimage-scripts.git 10 | 11 | The following repository also contains similar content: 12 | 13 | git://gitorious.org/cbootimage/cbootimage.git (branch trimslice) 14 | 15 | Changes made relative to cbootimage-scripts.git were: 16 | * Merged separate DDR and MMC, or DDR and SPI, config files into combined 17 | files to simplify their usage, and added header variables such as Version, 18 | BlockSize, etc. 19 | * Created image-generation config files. 20 | * Added OdmData, based on Compulab's U-Boot code, with debug UART value fixed 21 | to be UART A not UART D. 22 | * Switched U-Boot load/entry address from 0x00e08000 to 0x00108000 to match 23 | upstream U-Boot. 24 | * Set PreBctPadBlocks and Bctcopy for MMC, to match the recovery images 25 | provided by Compulab. 26 | -------------------------------------------------------------------------------- /tegra30/toradex/colibri_t30/colibri_t30.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2013 Toradex AG 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = colibri_t30_12MHz_1GB_NT5CC256M16CP-DI_400MHz-shmoo.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra30/avionic-design/tamonten-ng/tegra30.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2013 Avionic Design GmbH 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra124/nvidia/venice2/venice2-spi.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00400001; 20 | Bctcopy = 1; 21 | Bctfile = PM371_Hynix_2GB_H5TC4G63AFR_RDA_792MHz_0719.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra124/nvidia/norrin/norrin-spi.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00400001; 20 | Bctcopy = 1; 21 | Bctfile = PM370_Hynix_2GB_H5TC4G63AFR_PBA_924MHz_01212014.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra20/compulab/trimslice/trimslice-mmc.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | PreBctPadBlocks = 8; 21 | Bctcopy = 1; 22 | Bctfile = trimslice-mmc.bct; 23 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 24 | -------------------------------------------------------------------------------- /tegra20/nvidia/seaboard/seaboard-nand.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = PM282_Hynix_1GB_H5PS2G83AFR-S6C_380MHz_nand.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra114/nvidia/dalmore/dalmore-t40s-1600.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00350001; 20 | Bctcopy = 1; 21 | Bctfile = E1611_Hynix_2GB_H5TC4G63MFR-PBA_792Mhz_r403_v05.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra114/nvidia/dalmore/dalmore-t40s-1866.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00350001; 20 | Bctcopy = 1; 21 | Bctfile = E1611_Hynix_2GB_H5TC4G63AFR-RDA_792Mhz_r403_v2.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra114/nvidia/dalmore/dalmore-t40x-1866.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00350001; 20 | Bctcopy = 1; 21 | Bctfile = E1611_Hynix_2GB_H5TC4G63AFR-RDA_792MHz_r403_v03.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra124/nvidia/jetson-tk1/jetson-tk1-emmc.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00400001; 20 | Bctcopy = 1; 21 | Bctfile = PM375_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra30/nvidia/beaver/beaver-emmc.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = Pm315_Hynix_2GB_H5TC4G83MFR-PBA_400MHz_120613_sdmmc4_x8.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra124/nvidia/norrin/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t124 22 | 23 | bcts := \ 24 | PM370_Hynix_2GB_H5TC4G63AFR_PBA_924MHz_01212014.bct 25 | 26 | images := \ 27 | norrin-spi.img 28 | 29 | include ../../../build/post.mk 30 | -------------------------------------------------------------------------------- /tegra124/nvidia/venice2/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t124 22 | 23 | bcts := \ 24 | PM371_Hynix_2GB_H5TC4G63AFR_RDA_792MHz_0719.bct 25 | 26 | images := \ 27 | venice2-spi.img 28 | 29 | include ../../../build/post.mk 30 | -------------------------------------------------------------------------------- /tegra124/nvidia/jetson-tk1/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t124 22 | 23 | bcts := \ 24 | PM375_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.bct 25 | 26 | images := \ 27 | jetson-tk1-emmc.img 28 | 29 | include ../../../build/post.mk 30 | -------------------------------------------------------------------------------- /tegra20/nvidia/harmony/harmony-nand.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = harmony_a02_12Mhz_H5PS1G83EFR-S6C_333Mhz_1GB_2K8Nand_HY27UF084G2B-TP.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra20/nvidia/seaboard/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t20 22 | 23 | bcts := \ 24 | PM282_Hynix_1GB_H5PS2G83AFR-S6C_380MHz_nand.bct 25 | 26 | images := \ 27 | seaboard-nand.img 28 | 29 | include ../../../build/post.mk 30 | -------------------------------------------------------------------------------- /tegra20/nvidia/ventana/ventana-emmc.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = ventana_A03_12MHz_EDB8132B1PB6DF_300Mhz_1GB_emmc_THGBM1G6D4EBAI4.bct; 22 | BootLoader = u-boot.bin,0x00108000,0x00108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra30/nvidia/cardhu/cardhu-a05-2gb-emmc.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = E1198_Hynix_2GB_H5TC4G83MFR-PBA_375MHz_111122_317_sdmmc4_x8.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra30/nvidia/cardhu/cardhu-a02-a04-1gb-emmc.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = E1186_Hynix_1GB_H5TC2G83BFR-PBA_375MHz_111114_317_sdmmc4_x8.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra30/nvidia/cardhu/cardhu-a02-a04-2gb-emmc.img.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | Bctcopy = 1; 21 | Bctfile = E1198_Hynix_2GB_H5TC2G83BFR-PBA_667MHz_111121_317_sdmmc4_x8.bct; 22 | BootLoader = u-boot.bin,0x80108000,0x80108000,Complete; 23 | -------------------------------------------------------------------------------- /tegra30/nvidia/beaver/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t30 22 | 23 | bcts := \ 24 | Pm315_Hynix_2GB_H5TC4G83MFR-PBA_400MHz_120613_sdmmc4_x8.bct 25 | 26 | images := \ 27 | beaver-emmc.img 28 | 29 | include ../../../build/post.mk 30 | -------------------------------------------------------------------------------- /tegra20/nvidia/ventana/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t20 22 | 23 | bcts := \ 24 | ventana_A03_12MHz_EDB8132B1PB6DF_300Mhz_1GB_emmc_THGBM1G6D4EBAI4.bct 25 | 26 | images := \ 27 | ventana-emmc.img 28 | 29 | include ../../../build/post.mk 30 | -------------------------------------------------------------------------------- /tegra20/compulab/trimslice/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t20 22 | 23 | bcts := \ 24 | trimslice-mmc.bct \ 25 | trimslice-spi.bct 26 | 27 | images := \ 28 | trimslice-mmc.img \ 29 | trimslice-spi.img 30 | 31 | include ../../../build/post.mk 32 | -------------------------------------------------------------------------------- /tegra20/nvidia/harmony/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t20 22 | 23 | bcts := \ 24 | harmony_a02_12Mhz_H5PS1G83EFR-S6C_333Mhz_1GB_2K8Nand_HY27UF084G2B-TP.bct 25 | 26 | images := \ 27 | harmony-nand.img 28 | 29 | include ../../../build/post.mk 30 | -------------------------------------------------------------------------------- /tegra20/avionic-design/tec/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2013 Avionic Design GmbH 2 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 3 | # 4 | # This software is provided 'as-is', without any express or implied 5 | # warranty. In no event will the authors be held liable for any damages 6 | # arising from the use of this software. 7 | # 8 | # Permission is granted to anyone to use this software for any purpose, 9 | # including commercial applications, and to alter it and redistribute it 10 | # freely, subject to the following restrictions: 11 | # 12 | # 1. The origin of this software must not be misrepresented; you must not 13 | # claim that you wrote the original software. If you use this software 14 | # in a product, an acknowledgment in the product documentation would be 15 | # appreciated but is not required. 16 | # 2. Altered source versions must be plainly marked as such, and must not be 17 | # misrepresented as being the original software. 18 | # 3. This notice may not be removed or altered from any source distribution. 19 | 20 | include ../../../build/pre.mk 21 | 22 | soc := t20 23 | 24 | bcts := \ 25 | Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct 26 | 27 | images := \ 28 | tegra20-tec.img 29 | 30 | include ../../../build/post.mk 31 | -------------------------------------------------------------------------------- /tegra20/avionic-design/plutux/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2013 Avionic Design GmbH 2 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 3 | # 4 | # This software is provided 'as-is', without any express or implied 5 | # warranty. In no event will the authors be held liable for any damages 6 | # arising from the use of this software. 7 | # 8 | # Permission is granted to anyone to use this software for any purpose, 9 | # including commercial applications, and to alter it and redistribute it 10 | # freely, subject to the following restrictions: 11 | # 12 | # 1. The origin of this software must not be misrepresented; you must not 13 | # claim that you wrote the original software. If you use this software 14 | # in a product, an acknowledgment in the product documentation would be 15 | # appreciated but is not required. 16 | # 2. Altered source versions must be plainly marked as such, and must not be 17 | # misrepresented as being the original software. 18 | # 3. This notice may not be removed or altered from any source distribution. 19 | 20 | include ../../../build/pre.mk 21 | 22 | soc := t20 23 | 24 | bcts := \ 25 | Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct 26 | 27 | images := \ 28 | tegra20-plutux.img 29 | 30 | include ../../../build/post.mk 31 | -------------------------------------------------------------------------------- /tegra30/avionic-design/tec-ng/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2013 Avionic Design GmbH 2 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 3 | # 4 | # This software is provided 'as-is', without any express or implied 5 | # warranty. In no event will the authors be held liable for any damages 6 | # arising from the use of this software. 7 | # 8 | # Permission is granted to anyone to use this software for any purpose, 9 | # including commercial applications, and to alter it and redistribute it 10 | # freely, subject to the following restrictions: 11 | # 12 | # 1. The origin of this software must not be misrepresented; you must not 13 | # claim that you wrote the original software. If you use this software 14 | # in a product, an acknowledgment in the product documentation would be 15 | # appreciated but is not required. 16 | # 2. Altered source versions must be plainly marked as such, and must not be 17 | # misrepresented as being the original software. 18 | # 3. This notice may not be removed or altered from any source distribution. 19 | 20 | include ../../../build/pre.mk 21 | 22 | soc := t30 23 | 24 | bcts := \ 25 | TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct 26 | 27 | images := \ 28 | tegra30-tec-ng.img 29 | 30 | include ../../../build/post.mk 31 | -------------------------------------------------------------------------------- /tegra20/avionic-design/medcom-wide/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2013 Avionic Design GmbH 2 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 3 | # 4 | # This software is provided 'as-is', without any express or implied 5 | # warranty. In no event will the authors be held liable for any damages 6 | # arising from the use of this software. 7 | # 8 | # Permission is granted to anyone to use this software for any purpose, 9 | # including commercial applications, and to alter it and redistribute it 10 | # freely, subject to the following restrictions: 11 | # 12 | # 1. The origin of this software must not be misrepresented; you must not 13 | # claim that you wrote the original software. If you use this software 14 | # in a product, an acknowledgment in the product documentation would be 15 | # appreciated but is not required. 16 | # 2. Altered source versions must be plainly marked as such, and must not be 17 | # misrepresented as being the original software. 18 | # 3. This notice may not be removed or altered from any source distribution. 19 | 20 | include ../../../build/pre.mk 21 | 22 | soc := t20 23 | 24 | bcts := \ 25 | Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct 26 | 27 | images := \ 28 | tegra20-medcom-wide.img 29 | 30 | include ../../../build/post.mk 31 | -------------------------------------------------------------------------------- /tegra30/toradex/colibri_t30/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Toradex AG. All rights reserved. 2 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 3 | # 4 | # This software is provided 'as-is', without any express or implied 5 | # warranty. In no event will the authors be held liable for any damages 6 | # arising from the use of this software. 7 | # 8 | # Permission is granted to anyone to use this software for any purpose, 9 | # including commercial applications, and to alter it and redistribute it 10 | # freely, subject to the following restrictions: 11 | # 12 | # 1. The origin of this software must not be misrepresented; you must not 13 | # claim that you wrote the original software. If you use this software 14 | # in a product, an acknowledgment in the product documentation would be 15 | # appreciated but is not required. 16 | # 2. Altered source versions must be plainly marked as such, and must not be 17 | # misrepresented as being the original software. 18 | # 3. This notice may not be removed or altered from any source distribution. 19 | 20 | include ../../../build/pre.mk 21 | 22 | soc := t30 23 | 24 | bcts := \ 25 | colibri_t30_12MHz_1GB_NT5CC256M16CP-DI_400MHz-shmoo.bct 26 | 27 | images := \ 28 | colibri_t30.img 29 | 30 | include ../../../build/post.mk 31 | -------------------------------------------------------------------------------- /tegra114/nvidia/dalmore/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t114 22 | 23 | bcts := \ 24 | E1611_Hynix_2GB_H5TC4G63AFR-RDA_792MHz_r403_v03.bct \ 25 | E1611_Hynix_2GB_H5TC4G63AFR-RDA_792Mhz_r403_v2.bct \ 26 | E1611_Hynix_2GB_H5TC4G63MFR-PBA_792Mhz_r403_v05.bct 27 | 28 | images := \ 29 | dalmore-t40x-1866.img \ 30 | dalmore-t40s-1866.img \ 31 | dalmore-t40s-1600.img 32 | 33 | include ../../../build/post.mk 34 | -------------------------------------------------------------------------------- /tegra30/nvidia/cardhu/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | include ../../../build/pre.mk 20 | 21 | soc := t30 22 | 23 | bcts := \ 24 | E1186_Hynix_1GB_H5TC2G83BFR-PBA_375MHz_111114_317_sdmmc4_x8.bct \ 25 | E1198_Hynix_2GB_H5TC2G83BFR-PBA_667MHz_111121_317_sdmmc4_x8.bct \ 26 | E1198_Hynix_2GB_H5TC4G83MFR-PBA_375MHz_111122_317_sdmmc4_x8.bct 27 | 28 | images := \ 29 | cardhu-a02-a04-1gb-emmc.img \ 30 | cardhu-a02-a04-2gb-emmc.img \ 31 | cardhu-a05-2gb-emmc.img 32 | 33 | include ../../../build/post.mk 34 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Lucas Stach 2 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 3 | # 4 | # This software is provided 'as-is', without any express or implied 5 | # warranty. In no event will the authors be held liable for any damages 6 | # arising from the use of this software. 7 | # 8 | # Permission is granted to anyone to use this software for any purpose, 9 | # including commercial applications, and to alter it and redistribute it 10 | # freely, subject to the following restrictions: 11 | # 12 | # 1. The origin of this software must not be misrepresented; you must not 13 | # claim that you wrote the original software. If you use this software 14 | # in a product, an acknowledgment in the product documentation would be 15 | # appreciated but is not required. 16 | # 2. Altered source versions must be plainly marked as such, and must not be 17 | # misrepresented as being the original software. 18 | # 3. This notice may not be removed or altered from any source distribution. 19 | 20 | include ../../../build/pre.mk 21 | 22 | soc := t20 23 | 24 | bcts := \ 25 | colibri_t20-256-hsmmc.bct \ 26 | colibri_t20-512-hsmmc.bct \ 27 | colibri_t20-256-v11-nand.bct \ 28 | colibri_t20-256-v12-nand.bct \ 29 | colibri_t20-512-v11-nand.bct \ 30 | colibri_t20-512-v12-nand.bct 31 | 32 | images := \ 33 | colibri_t20-256-hsmmc.img \ 34 | colibri_t20-512-hsmmc.img \ 35 | colibri_t20-256-v11-nand.img \ 36 | colibri_t20-256-v12-nand.img \ 37 | colibri_t20-512-v11-nand.img \ 38 | colibri_t20-512-v12-nand.img 39 | 40 | include ../../../build/post.mk 41 | -------------------------------------------------------------------------------- /tegra30/nvidia/cardhu/README.txt: -------------------------------------------------------------------------------- 1 | How to identify your Cardhu 2 | =========================== 3 | 4 | Cardhu exists in two forms: 5 | 6 | 1) A form-factor device, fully enclosed in plastics, which thus looks like 7 | a production tablet. Note that it is possible for a "door" to have been 8 | removed from the rear plastic cover of the device. 9 | 10 | Devices of this type should have a sticker, attached to the outer plastics, 11 | of the form 940-81290-1001-000. The 3rd component of that number ("1001" in 12 | the example) indicates the SKU of the device. Use this SKU to determine 13 | which BCT to use. 14 | 15 | The SKU uniquely determines the revision and configuration of the main 16 | board in the device. The following table describes the mapping: 17 | 18 | SKU implies: Board Revision RAM size 19 | ==== ============== ======== 20 | 1000 A04 2 GB 21 | 1001 A04 1 GB 22 | 1003 A05 2 GB 23 | 1005 A05 2 GB 24 | 25 | 2) An engineering device, with all internal circuit boards fully exposed, 26 | which can have 1" metal stand-offs screwed into the chassis for support. 27 | 28 | Devices of this type should have a sticker, attached to the main circuit 29 | board, of the form 600-81291-1000-002. The final component of that number 30 | ("002" in the example) indicates the revision of the board. 002 means A02, 31 | 004 means A04, 005 means A05, etc. 32 | 33 | For reference, these engineering devices are known as SKU 4000. 34 | 35 | These boards may contain either 1 GB or 2 GB of RAM. The exposed side of 36 | the main board will always contain 4 chips that are the first GB or RAM. 37 | The rear side of the board may contain 4 additional chips that are the 38 | second GB of RAM. Carefully check the rear of the board to determine your 39 | device's RAM size. 40 | 41 | Selecting a BCT for Cardhu 42 | ========================== 43 | 44 | Once you know your board revision and RAM size, you may select the appropriate 45 | BCT to use. The cbootimage configuration files *.img.cfg in this directory are 46 | named based on the board revision and RAM size they apply to. Similarly, when 47 | the build script generates flashable *.img files, those are also named based 48 | on the board revision and RAM size they apply to. Select the appropriate image 49 | based on the image file name. 50 | -------------------------------------------------------------------------------- /README.txt: -------------------------------------------------------------------------------- 1 | Introduction 2 | ============ 3 | 4 | The cbootimage-configs project contains cbootimage configuration files for 5 | many Tegra boards, both those designed by NVIDIA, and various third-parties. 6 | 7 | The directory hierarchy is first by chip/SoC, then by vendor, then by board 8 | name. For example, tegra20/nvidia/harmony. 9 | 10 | If you wish to use cbootimage with a board that is not yet supported by this 11 | project, you might try contacting the vendor of the board to see if they'd be 12 | willing to contribute configuration files to this project. 13 | 14 | Adding Board Support 15 | ==================== 16 | 17 | If that doesn't work out, you may create the required configuration files 18 | using the following process: 19 | 20 | 1) 21 | 22 | Extract the BCT from the existing device. Various methods exist to do this: 23 | 24 | 1a) 25 | 26 | Recent versions of tegrarcm now have the capability to read the BCT from the 27 | device without requiring any HW-specific binaries, nor code already installed 28 | on the device: 29 | 30 | tegrarcm --bct board.bct readbct 31 | 32 | 1b) 33 | 34 | If you have access to Linux running on the device already, then you can use 35 | dump the memory device directly: 36 | 37 | For devices which boot from eMMC: 38 | 39 | dd if=/dev/mmcblk0boot0 of=bct.bin bs=65536 count=1 40 | 41 | For devices which boot from SPI: 42 | 43 | dd if=/dev/mtd0ro of=bct.bin bs=65536 count=1 44 | 45 | 1c) 46 | 47 | If you have a working nvflash for your device, then this can also extract the 48 | BCT: 49 | 50 | nvflash --bl fastboot.bin --getbct --bct board.bct 51 | 52 | If that doesn't work, you could try reading the content of the BCT partition 53 | or the start of the raw device, then extracting the BCT: 54 | 55 | nvflash --bl fastboot.bin --read 2 board.bct 56 | 57 | or: 58 | 59 | nvflash --bl fastboot.bin --rawdeviceread 0 128 board.bct 60 | 61 | Note that some of the above commands extract many more bytes of data that is 62 | strictly required. However, this avoids updating these instructions for each 63 | new chip; Tegra20's BCT is just under 4KiB, Tegra30's around 6KiB, etc. 64 | 65 | 2) 66 | 67 | Convert the BCT to a cbootimage configuration file: 68 | 69 | bct_dump board.bct > board.bct.cfg 70 | 71 | This will de-compile the extracted BCT binary into a text configuration file 72 | suitable for later use by cbootimage. 73 | 74 | To follow the same structure as the rest of the configuration files in this 75 | project, it's then best to split up board.bct.cfg into separate board.bct.cfg 76 | (DevType, DeviceParam, and SDRAM lines), and board.img.cfg (all other header 77 | parameters). Use the existing configuration files as a guide. 78 | 79 | Once you have performed these steps, you will have configuration files 80 | suitable for your personal use. We don't accept contributions to this project 81 | that were derived in this fashion. We encourage you to contact the vendor 82 | and request them to submit their own configuration files. 83 | 84 | Submitting Changes 85 | ================== 86 | 87 | To submit patches to this project, please use the following commands: 88 | 89 | * git format-patch --subject-prefix="cbootimage-configs PATCH" 90 | 91 | Creates a patch file from your git commit. 92 | 93 | * git send-email --to linux-tegra@vger.kernel.org *.patch 94 | 95 | Sends the patch by email to the Tegra mailing list. 96 | 97 | Even though the primary upstream repository for this project is hosted on 98 | github, contributions aren't accepted via github pull requests. Github pull 99 | requests would bypass public code review on the project mailing list. 100 | 101 | Patches should be signed off (include a signed-off-by line) to indicate your 102 | acceptance of the code's license (see COPYING and the license header in each 103 | file). See http://developercertificate.org/ for details of what signed-off-by 104 | implies. 105 | -------------------------------------------------------------------------------- /tegra20/avionic-design/tamonten/Tamonten_T2_512MB_MEM2G16D2D-ABG-25_366MHz.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2011-2013 Avionic Design GmbH 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | BlockSize = 0x00020000; 21 | PageSize = 0x00000800; 22 | PartitionSize = 0x01000000; 23 | OdmData = 0x2b2d8011; 24 | 25 | DevType[0] = NvBootDevType_Nand; 26 | DeviceParam[0].NandParams.ClockDivider = 0x00000004; 27 | DeviceParam[0].NandParams.NandTiming2 = 0x0000000a; 28 | DeviceParam[0].NandParams.NandTiming = 0x3b269213; 29 | DeviceParam[0].NandParams.BlockSizeLog2 = 0x00000000; 30 | DeviceParam[0].NandParams.PageSizeLog2 = 0x00000000; 31 | 32 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr2; 33 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 34 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 35 | SDRAM[0].PllMInputDivider = 0x0000000c; 36 | SDRAM[0].PllMFeedbackDivider = 0x0000029a; 37 | SDRAM[0].PllMPostDivider = 0x00000000; 38 | SDRAM[0].PllMStableTime = 0x0000012c; 39 | SDRAM[0].EmcClockDivider = 0x00000001; 40 | SDRAM[0].EmcAutoCalInterval = 0x00000000; 41 | SDRAM[0].EmcAutoCalConfig = 0xe0a61111; 42 | SDRAM[0].EmcAutoCalWait = 0x00000000; 43 | SDRAM[0].EmcPinProgramWait = 0x00000000; 44 | SDRAM[0].EmcRc = 0x00000014; 45 | SDRAM[0].EmcRfc = 0x00000041; 46 | SDRAM[0].EmcRas = 0x0000000f; 47 | SDRAM[0].EmcRp = 0x00000005; 48 | SDRAM[0].EmcR2w = 0x00000004; 49 | SDRAM[0].EmcW2r = 0x00000005; 50 | SDRAM[0].EmcR2p = 0x00000003; 51 | SDRAM[0].EmcW2p = 0x0000000b; 52 | SDRAM[0].EmcRrd = 0x00000004; 53 | SDRAM[0].EmcRdRcd = 0x00000005; 54 | SDRAM[0].EmcWrRcd = 0x00000005; 55 | SDRAM[0].EmcRext = 0x00000001; 56 | SDRAM[0].EmcWdv = 0x00000003; 57 | SDRAM[0].EmcQUseExtra = 0x00000000; 58 | SDRAM[0].EmcQUse = 0x00000004; 59 | SDRAM[0].EmcQRst = 0x00000003; 60 | SDRAM[0].EmcQSafe = 0x00000009; 61 | SDRAM[0].EmcRdv = 0x0000000c; 62 | SDRAM[0].EmcRefresh = 0x000004df; 63 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 64 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 65 | SDRAM[0].EmcPdEx2Rd = 0x00000003; 66 | SDRAM[0].EmcPChg2Pden = 0x00000005; 67 | SDRAM[0].EmcAct2Pden = 0x00000005; 68 | SDRAM[0].EmcAr2Pden = 0x00000001; 69 | SDRAM[0].EmcRw2Pden = 0x0000000e; 70 | SDRAM[0].EmcTxsr = 0x000000c8; 71 | SDRAM[0].EmcTcke = 0x00000003; 72 | SDRAM[0].EmcTfaw = 0x0000000f; 73 | SDRAM[0].EmcTrpab = 0x00000006; 74 | SDRAM[0].EmcTClkStable = 0x0000000f; 75 | SDRAM[0].EmcTClkStop = 0x00000002; 76 | SDRAM[0].EmcTRefBw = 0x00000000; 77 | SDRAM[0].EmcFbioCfg1 = 0x00000000; 78 | SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000; 79 | SDRAM[0].EmcFbioDqsibDly = 0x2f2f2f2f; 80 | SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000; 81 | SDRAM[0].EmcFbioQuseDly = 0x2f2f2f2f; 82 | SDRAM[0].EmcFbioCfg5 = 0x00000083; 83 | SDRAM[0].EmcFbioCfg6 = 0x00000002; 84 | SDRAM[0].EmcFbioSpare = 0x00000000; 85 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 86 | SDRAM[0].EmcMrsResetDll = 0x00000000; 87 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000100; 88 | SDRAM[0].EmcMrs = 0x00000a5a; 89 | SDRAM[0].EmcEmrsEmr2 = 0x00200000; 90 | SDRAM[0].EmcEmrsEmr3 = 0x00300000; 91 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000; 92 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100382; 93 | SDRAM[0].EmcEmrs = 0x00100002; 94 | SDRAM[0].EmcMrw1 = 0x00000000; 95 | SDRAM[0].EmcMrw2 = 0x00000000; 96 | SDRAM[0].EmcMrw3 = 0x00000000; 97 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 98 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 99 | SDRAM[0].EmcAdrCfg1 = 0x00070303; 100 | SDRAM[0].EmcAdrCfg = 0x00070303; 101 | SDRAM[0].McEmemCfg = 0x00080000; 102 | SDRAM[0].McLowLatencyConfig = 0x80000003; 103 | SDRAM[0].EmcCfg2 = 0x00000405; 104 | SDRAM[0].EmcCfgDigDll = 0x00380006; 105 | SDRAM[0].EmcCfgClktrim0 = 0x00000000; 106 | SDRAM[0].EmcCfgClktrim1 = 0x00000000; 107 | SDRAM[0].EmcCfgClktrim2 = 0x00000000; 108 | SDRAM[0].EmcCfg = 0x0001ff00; 109 | SDRAM[0].EmcDbg = 0x01000000; 110 | SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000; 111 | SDRAM[0].EmcDllXformDqs = 0x00000010; 112 | SDRAM[0].EmcDllXformQUse = 0x00000008; 113 | SDRAM[0].WarmBootWait = 0x00000002; 114 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 115 | SDRAM[0].EmcOdtWrite = 0x00000000; 116 | SDRAM[0].EmcOdtRead = 0x00000000; 117 | SDRAM[0].EmcZcalRefCnt = 0x00000000; 118 | SDRAM[0].EmcZcalWaitCnt = 0x00000000; 119 | SDRAM[0].EmcZcalMrwCmd = 0x00000000; 120 | SDRAM[0].EmcMrwZqInitDev0 = 0x00000000; 121 | SDRAM[0].EmcMrwZqInitDev1 = 0x00000000; 122 | SDRAM[0].EmcMrwZqInitWait = 0x00000000; 123 | SDRAM[0].EmcDdr2Wait = 0x00000002; 124 | SDRAM[0].PmcDdrPwr = 0x00000001; 125 | SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 126 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 127 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 128 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 129 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 130 | SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 131 | SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 132 | SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 133 | -------------------------------------------------------------------------------- /tegra20/compulab/trimslice/trimslice-spi.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, CompuLab Ltd. All rights reserved. 2 | # 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # See README.txt for a description of NVIDIA's changes relative to CompuLab's 5 | # original. 6 | # 7 | # This software is provided 'as-is', without any express or implied 8 | # warranty. In no event will the authors be held liable for any damages 9 | # arising from the use of this software. 10 | # 11 | # Permission is granted to anyone to use this software for any purpose, 12 | # including commercial applications, and to alter it and redistribute it 13 | # freely, subject to the following restrictions: 14 | # 15 | # 1. The origin of this software must not be misrepresented; you must not 16 | # claim that you wrote the original software. If you use this software 17 | # in a product, an acknowledgment in the product documentation would be 18 | # appreciated but is not required. 19 | # 2. Altered source versions must be plainly marked as such, and must not be 20 | # misrepresented as being the original software. 21 | # 3. This notice may not be removed or altered from any source distribution. 22 | 23 | Version = 0x00020001; 24 | BlockSize = 0x00008000; 25 | PageSize = 0x00000800; 26 | PartitionSize = 0x01000000; 27 | OdmData = 0x300c0000; 28 | 29 | DevType[0] = NvBootDevType_Spi; 30 | DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = 0; 31 | DeviceParam[0].SpiFlashParams.ClockDivider = 12; 32 | DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; 33 | 34 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr2; 35 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 36 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 37 | SDRAM[0].PllMInputDivider = 0x0000000c; 38 | SDRAM[0].PllMFeedbackDivider = 0x0000029a; 39 | SDRAM[0].PllMPostDivider = 0x00000000; 40 | SDRAM[0].PllMStableTime = 0x0000012c; 41 | SDRAM[0].EmcClockDivider = 0x00000001; 42 | SDRAM[0].EmcAutoCalInterval = 0x00000000; 43 | SDRAM[0].EmcAutoCalConfig = 0xe0a61818; 44 | SDRAM[0].EmcAutoCalWait = 0x00000000; 45 | SDRAM[0].EmcPinProgramWait = 0x00000000; 46 | SDRAM[0].EmcRc = 0x00000014; 47 | SDRAM[0].EmcRfc = 0x0000002b; 48 | SDRAM[0].EmcRas = 0x0000000f; 49 | SDRAM[0].EmcRp = 0x00000005; 50 | SDRAM[0].EmcR2w = 0x00000004; 51 | SDRAM[0].EmcW2r = 0x00000005; 52 | SDRAM[0].EmcR2p = 0x00000003; 53 | SDRAM[0].EmcW2p = 0x0000000c; 54 | SDRAM[0].EmcRrd = 0x00000003; 55 | SDRAM[0].EmcRdRcd = 0x00000005; 56 | SDRAM[0].EmcWrRcd = 0x00000005; 57 | SDRAM[0].EmcRext = 0x00000001; 58 | SDRAM[0].EmcWdv = 0x00000004; 59 | SDRAM[0].EmcQUseExtra = 0x00000000; 60 | SDRAM[0].EmcQUse = 0x00000005; 61 | SDRAM[0].EmcQRst = 0x00000004; 62 | SDRAM[0].EmcQSafe = 0x00000009; 63 | SDRAM[0].EmcRdv = 0x0000000d; 64 | SDRAM[0].EmcRefresh = 0x000009ff; 65 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 66 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 67 | SDRAM[0].EmcPdEx2Rd = 0x00000003; 68 | SDRAM[0].EmcPChg2Pden = 0x00000005; 69 | SDRAM[0].EmcAct2Pden = 0x00000005; 70 | SDRAM[0].EmcAr2Pden = 0x00000001; 71 | SDRAM[0].EmcRw2Pden = 0x0000000f; 72 | SDRAM[0].EmcTxsr = 0x000000c8; 73 | SDRAM[0].EmcTcke = 0x00000003; 74 | SDRAM[0].EmcTfaw = 0x0000000c; 75 | SDRAM[0].EmcTrpab = 0x00000006; 76 | SDRAM[0].EmcTClkStable = 0x00000008; 77 | SDRAM[0].EmcTClkStop = 0x00000002; 78 | SDRAM[0].EmcTRefBw = 0x00000000; 79 | SDRAM[0].EmcFbioCfg1 = 0x00000000; 80 | SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000; 81 | SDRAM[0].EmcFbioDqsibDly = 0x1c1c2020; 82 | SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000; 83 | SDRAM[0].EmcFbioQuseDly = 0x5a504646; 84 | SDRAM[0].EmcFbioCfg5 = 0x00000083; 85 | SDRAM[0].EmcFbioCfg6 = 0x00000002; 86 | SDRAM[0].EmcFbioSpare = 0x00000000; 87 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 88 | SDRAM[0].EmcMrsResetDll = 0x00000000; 89 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000100; 90 | SDRAM[0].EmcMrs = 0x00000a6a; 91 | SDRAM[0].EmcEmrsEmr2 = 0x00200000; 92 | SDRAM[0].EmcEmrsEmr3 = 0x00300000; 93 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000; 94 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100384; 95 | SDRAM[0].EmcEmrs = 0x00100004; 96 | SDRAM[0].EmcMrw1 = 0x00000000; 97 | SDRAM[0].EmcMrw2 = 0x00000000; 98 | SDRAM[0].EmcMrw3 = 0x00000000; 99 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 100 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 101 | SDRAM[0].EmcAdrCfg1 = 0x00070303; 102 | SDRAM[0].EmcAdrCfg = 0x01070303; 103 | SDRAM[0].McEmemCfg = 0x00100000; 104 | SDRAM[0].McLowLatencyConfig = 0x80000003; 105 | SDRAM[0].EmcCfg2 = 0x00000405; 106 | SDRAM[0].EmcCfgDigDll = 0xf0000313; 107 | SDRAM[0].EmcCfgClktrim0 = 0x00000000; 108 | SDRAM[0].EmcCfgClktrim1 = 0x00000000; 109 | SDRAM[0].EmcCfgClktrim2 = 0x00000000; 110 | SDRAM[0].EmcCfg = 0x2001ff01; 111 | SDRAM[0].EmcDbg = 0x01000000; 112 | SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000; 113 | SDRAM[0].EmcDllXformDqs = 0x00000010; 114 | SDRAM[0].EmcDllXformQUse = 0x00000008; 115 | SDRAM[0].WarmBootWait = 0x00000002; 116 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 117 | SDRAM[0].EmcOdtWrite = 0x00000000; 118 | SDRAM[0].EmcOdtRead = 0x00000000; 119 | SDRAM[0].EmcZcalRefCnt = 0x00000000; 120 | SDRAM[0].EmcZcalWaitCnt = 0x00000000; 121 | SDRAM[0].EmcZcalMrwCmd = 0x00000000; 122 | SDRAM[0].EmcMrwZqInitDev0 = 0x00000000; 123 | SDRAM[0].EmcMrwZqInitDev1 = 0x00000000; 124 | SDRAM[0].EmcMrwZqInitWait = 0x00000000; 125 | SDRAM[0].EmcDdr2Wait = 0x00000002; 126 | SDRAM[0].PmcDdrPwr = 0x00000001; 127 | SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 128 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 129 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 130 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 131 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 132 | SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 133 | SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 134 | SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 135 | -------------------------------------------------------------------------------- /tegra20/nvidia/ventana/ventana_A03_12MHz_EDB8132B1PB6DF_300Mhz_1GB_emmc_THGBM1G6D4EBAI4.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | BlockSize = 0x00004000; 21 | PageSize = 0x00000200; 22 | PartitionSize = 0x01000000; 23 | OdmData = 0x300d8000; 24 | 25 | DevType[0] = NvBootDevType_Sdmmc; 26 | DeviceParam[0].SdmmcParams.ClockDivider = 0x0000000c; 27 | DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 28 | DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000; 29 | 30 | DevType[1] = NvBootDevType_Sdmmc; 31 | DeviceParam[1].SdmmcParams.ClockDivider = 0x0000000c; 32 | DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 33 | DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000; 34 | 35 | DevType[2] = NvBootDevType_Sdmmc; 36 | DeviceParam[2].SdmmcParams.ClockDivider = 0x0000000c; 37 | DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 38 | DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000; 39 | 40 | DevType[3] = NvBootDevType_Sdmmc; 41 | DeviceParam[3].SdmmcParams.ClockDivider = 0x0000000c; 42 | DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 43 | DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000; 44 | 45 | SDRAM[0].MemoryType = NvBootMemoryType_LpDdr2; 46 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 47 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 48 | SDRAM[0].PllMInputDivider = 0x0000000c; 49 | SDRAM[0].PllMFeedbackDivider = 0x00000258; 50 | SDRAM[0].PllMPostDivider = 0x00000000; 51 | SDRAM[0].PllMStableTime = 0x0000012c; 52 | SDRAM[0].EmcClockDivider = 0x00000001; 53 | SDRAM[0].EmcAutoCalInterval = 0x00000000; 54 | SDRAM[0].EmcAutoCalConfig = 0xe0a61111; 55 | SDRAM[0].EmcAutoCalWait = 0x00000000; 56 | SDRAM[0].EmcPinProgramWait = 0x00000000; 57 | SDRAM[0].EmcRc = 0x00000012; 58 | SDRAM[0].EmcRfc = 0x00000027; 59 | SDRAM[0].EmcRas = 0x0000000d; 60 | SDRAM[0].EmcRp = 0x00000007; 61 | SDRAM[0].EmcR2w = 0x00000007; 62 | SDRAM[0].EmcW2r = 0x00000005; 63 | SDRAM[0].EmcR2p = 0x00000003; 64 | SDRAM[0].EmcW2p = 0x00000009; 65 | SDRAM[0].EmcRrd = 0x00000003; 66 | SDRAM[0].EmcRdRcd = 0x00000006; 67 | SDRAM[0].EmcWrRcd = 0x00000006; 68 | SDRAM[0].EmcRext = 0x00000003; 69 | SDRAM[0].EmcWdv = 0x00000002; 70 | SDRAM[0].EmcQUseExtra = 0x00000005; 71 | SDRAM[0].EmcQUse = 0x00000006; 72 | SDRAM[0].EmcQRst = 0x00000003; 73 | SDRAM[0].EmcQSafe = 0x00000009; 74 | SDRAM[0].EmcRdv = 0x0000000c; 75 | SDRAM[0].EmcRefresh = 0x0000045f; 76 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 77 | SDRAM[0].EmcPdEx2Wr = 0x00000004; 78 | SDRAM[0].EmcPdEx2Rd = 0x00000004; 79 | SDRAM[0].EmcPChg2Pden = 0x00000007; 80 | SDRAM[0].EmcAct2Pden = 0x00000006; 81 | SDRAM[0].EmcAr2Pden = 0x00000001; 82 | SDRAM[0].EmcRw2Pden = 0x0000000e; 83 | SDRAM[0].EmcTxsr = 0x0000002a; 84 | SDRAM[0].EmcTcke = 0x00000003; 85 | SDRAM[0].EmcTfaw = 0x0000000f; 86 | SDRAM[0].EmcTrpab = 0x00000008; 87 | SDRAM[0].EmcTClkStable = 0x00000005; 88 | SDRAM[0].EmcTClkStop = 0x00000002; 89 | SDRAM[0].EmcTRefBw = 0x000004e0; 90 | SDRAM[0].EmcFbioCfg1 = 0x00000000; 91 | SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000; 92 | SDRAM[0].EmcFbioDqsibDly = 0x383c443c; 93 | SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000; 94 | SDRAM[0].EmcFbioQuseDly = 0x6e6e6e6e; 95 | SDRAM[0].EmcFbioCfg5 = 0x00000282; 96 | SDRAM[0].EmcFbioCfg6 = 0x00000002; 97 | SDRAM[0].EmcFbioSpare = 0x00000000; 98 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 99 | SDRAM[0].EmcMrsResetDll = 0x00000000; 100 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; 101 | SDRAM[0].EmcMrs = 0x00000000; 102 | SDRAM[0].EmcEmrsEmr2 = 0x00000000; 103 | SDRAM[0].EmcEmrsEmr3 = 0x00000000; 104 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; 105 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; 106 | SDRAM[0].EmcEmrs = 0x00000000; 107 | SDRAM[0].EmcMrw1 = 0x0001006a; 108 | SDRAM[0].EmcMrw2 = 0x00020003; 109 | SDRAM[0].EmcMrw3 = 0x00030002; 110 | SDRAM[0].EmcMrwResetCommand = 0x003f0000; 111 | SDRAM[0].EmcMrwResetNInitWait = 0x0000000a; 112 | SDRAM[0].EmcAdrCfg1 = 0x00070303; 113 | SDRAM[0].EmcAdrCfg = 0x01070303; 114 | SDRAM[0].McEmemCfg = 0x00100000; 115 | SDRAM[0].McLowLatencyConfig = 0x80000003; 116 | SDRAM[0].EmcCfg2 = 0x00000403; 117 | SDRAM[0].EmcCfgDigDll = 0xe0000313; 118 | SDRAM[0].EmcCfgClktrim0 = 0x00000000; 119 | SDRAM[0].EmcCfgClktrim1 = 0x00000000; 120 | SDRAM[0].EmcCfgClktrim2 = 0x00000000; 121 | SDRAM[0].EmcCfg = 0x0001ff00; 122 | SDRAM[0].EmcDbg = 0x01000020; 123 | SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000; 124 | SDRAM[0].EmcDllXformDqs = 0x00000010; 125 | SDRAM[0].EmcDllXformQUse = 0x00000008; 126 | SDRAM[0].WarmBootWait = 0x00000001; 127 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 128 | SDRAM[0].EmcOdtWrite = 0x00000000; 129 | SDRAM[0].EmcOdtRead = 0x00000000; 130 | SDRAM[0].EmcZcalRefCnt = 0x00000000; 131 | SDRAM[0].EmcZcalWaitCnt = 0x0000001b; 132 | SDRAM[0].EmcZcalMrwCmd = 0x000a0056; 133 | SDRAM[0].EmcMrwZqInitDev0 = 0x800a00ff; 134 | SDRAM[0].EmcMrwZqInitDev1 = 0x400a00ff; 135 | SDRAM[0].EmcMrwZqInitWait = 0x00000001; 136 | SDRAM[0].EmcDdr2Wait = 0x00000000; 137 | SDRAM[0].PmcDdrPwr = 0x00000000; 138 | SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 139 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080040; 140 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff8; 141 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440000; 142 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff8; 143 | SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 144 | SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 145 | SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x00005500; 146 | -------------------------------------------------------------------------------- /tegra20/compulab/trimslice/trimslice-mmc.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, CompuLab Ltd. All rights reserved. 2 | # 3 | # Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 | # See README.txt for a description of NVIDIA's changes relative to CompuLab's 5 | # original. 6 | # 7 | # This software is provided 'as-is', without any express or implied 8 | # warranty. In no event will the authors be held liable for any damages 9 | # arising from the use of this software. 10 | # 11 | # Permission is granted to anyone to use this software for any purpose, 12 | # including commercial applications, and to alter it and redistribute it 13 | # freely, subject to the following restrictions: 14 | # 15 | # 1. The origin of this software must not be misrepresented; you must not 16 | # claim that you wrote the original software. If you use this software 17 | # in a product, an acknowledgment in the product documentation would be 18 | # appreciated but is not required. 19 | # 2. Altered source versions must be plainly marked as such, and must not be 20 | # misrepresented as being the original software. 21 | # 3. This notice may not be removed or altered from any source distribution. 22 | 23 | Version = 0x00020001; 24 | BlockSize = 0x00004000; 25 | PageSize = 0x00000200; 26 | PartitionSize = 0x01000000; 27 | OdmData = 0x300c0000; 28 | 29 | DevType[0] = NvBootDevType_Sdmmc; 30 | DeviceParam[0].SdmmcParams.ClockDivider = 0x0000000c; 31 | DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 32 | DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000; 33 | 34 | DevType[1] = NvBootDevType_Sdmmc; 35 | DeviceParam[1].SdmmcParams.ClockDivider = 0x0000000c; 36 | DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 37 | DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000; 38 | 39 | DevType[2] = NvBootDevType_Sdmmc; 40 | DeviceParam[2].SdmmcParams.ClockDivider = 0x0000000c; 41 | DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 42 | DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000; 43 | 44 | DevType[3] = NvBootDevType_Sdmmc; 45 | DeviceParam[3].SdmmcParams.ClockDivider = 0x0000000c; 46 | DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 47 | DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000; 48 | 49 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr2; 50 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 51 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 52 | SDRAM[0].PllMInputDivider = 0x0000000c; 53 | SDRAM[0].PllMFeedbackDivider = 0x0000029a; 54 | SDRAM[0].PllMPostDivider = 0x00000000; 55 | SDRAM[0].PllMStableTime = 0x0000012c; 56 | SDRAM[0].EmcClockDivider = 0x00000001; 57 | SDRAM[0].EmcAutoCalInterval = 0x00000000; 58 | SDRAM[0].EmcAutoCalConfig = 0xe0a61818; 59 | SDRAM[0].EmcAutoCalWait = 0x00000000; 60 | SDRAM[0].EmcPinProgramWait = 0x00000000; 61 | SDRAM[0].EmcRc = 0x00000014; 62 | SDRAM[0].EmcRfc = 0x0000002b; 63 | SDRAM[0].EmcRas = 0x0000000f; 64 | SDRAM[0].EmcRp = 0x00000005; 65 | SDRAM[0].EmcR2w = 0x00000004; 66 | SDRAM[0].EmcW2r = 0x00000005; 67 | SDRAM[0].EmcR2p = 0x00000003; 68 | SDRAM[0].EmcW2p = 0x0000000c; 69 | SDRAM[0].EmcRrd = 0x00000003; 70 | SDRAM[0].EmcRdRcd = 0x00000005; 71 | SDRAM[0].EmcWrRcd = 0x00000005; 72 | SDRAM[0].EmcRext = 0x00000001; 73 | SDRAM[0].EmcWdv = 0x00000004; 74 | SDRAM[0].EmcQUseExtra = 0x00000000; 75 | SDRAM[0].EmcQUse = 0x00000005; 76 | SDRAM[0].EmcQRst = 0x00000004; 77 | SDRAM[0].EmcQSafe = 0x00000009; 78 | SDRAM[0].EmcRdv = 0x0000000d; 79 | SDRAM[0].EmcRefresh = 0x000009ff; 80 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 81 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 82 | SDRAM[0].EmcPdEx2Rd = 0x00000003; 83 | SDRAM[0].EmcPChg2Pden = 0x00000005; 84 | SDRAM[0].EmcAct2Pden = 0x00000005; 85 | SDRAM[0].EmcAr2Pden = 0x00000001; 86 | SDRAM[0].EmcRw2Pden = 0x0000000f; 87 | SDRAM[0].EmcTxsr = 0x000000c8; 88 | SDRAM[0].EmcTcke = 0x00000003; 89 | SDRAM[0].EmcTfaw = 0x0000000c; 90 | SDRAM[0].EmcTrpab = 0x00000006; 91 | SDRAM[0].EmcTClkStable = 0x00000008; 92 | SDRAM[0].EmcTClkStop = 0x00000002; 93 | SDRAM[0].EmcTRefBw = 0x00000000; 94 | SDRAM[0].EmcFbioCfg1 = 0x00000000; 95 | SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000; 96 | SDRAM[0].EmcFbioDqsibDly = 0x1c1c2020; 97 | SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000; 98 | SDRAM[0].EmcFbioQuseDly = 0x5a504646; 99 | SDRAM[0].EmcFbioCfg5 = 0x00000083; 100 | SDRAM[0].EmcFbioCfg6 = 0x00000002; 101 | SDRAM[0].EmcFbioSpare = 0x00000000; 102 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 103 | SDRAM[0].EmcMrsResetDll = 0x00000000; 104 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000100; 105 | SDRAM[0].EmcMrs = 0x00000a6a; 106 | SDRAM[0].EmcEmrsEmr2 = 0x00200000; 107 | SDRAM[0].EmcEmrsEmr3 = 0x00300000; 108 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000; 109 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100384; 110 | SDRAM[0].EmcEmrs = 0x00100004; 111 | SDRAM[0].EmcMrw1 = 0x00000000; 112 | SDRAM[0].EmcMrw2 = 0x00000000; 113 | SDRAM[0].EmcMrw3 = 0x00000000; 114 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 115 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 116 | SDRAM[0].EmcAdrCfg1 = 0x00070303; 117 | SDRAM[0].EmcAdrCfg = 0x01070303; 118 | SDRAM[0].McEmemCfg = 0x00100000; 119 | SDRAM[0].McLowLatencyConfig = 0x80000003; 120 | SDRAM[0].EmcCfg2 = 0x00000405; 121 | SDRAM[0].EmcCfgDigDll = 0xf0000313; 122 | SDRAM[0].EmcCfgClktrim0 = 0x00000000; 123 | SDRAM[0].EmcCfgClktrim1 = 0x00000000; 124 | SDRAM[0].EmcCfgClktrim2 = 0x00000000; 125 | SDRAM[0].EmcCfg = 0x2001ff01; 126 | SDRAM[0].EmcDbg = 0x01000000; 127 | SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000; 128 | SDRAM[0].EmcDllXformDqs = 0x00000010; 129 | SDRAM[0].EmcDllXformQUse = 0x00000008; 130 | SDRAM[0].WarmBootWait = 0x00000002; 131 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 132 | SDRAM[0].EmcOdtWrite = 0x00000000; 133 | SDRAM[0].EmcOdtRead = 0x00000000; 134 | SDRAM[0].EmcZcalRefCnt = 0x00000000; 135 | SDRAM[0].EmcZcalWaitCnt = 0x00000000; 136 | SDRAM[0].EmcZcalMrwCmd = 0x00000000; 137 | SDRAM[0].EmcMrwZqInitDev0 = 0x00000000; 138 | SDRAM[0].EmcMrwZqInitDev1 = 0x00000000; 139 | SDRAM[0].EmcMrwZqInitWait = 0x00000000; 140 | SDRAM[0].EmcDdr2Wait = 0x00000002; 141 | SDRAM[0].PmcDdrPwr = 0x00000001; 142 | SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 143 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 144 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 145 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 146 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 147 | SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 148 | SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 149 | SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 150 | -------------------------------------------------------------------------------- /tegra20/nvidia/seaboard/PM282_Hynix_1GB_H5PS2G83AFR-S6C_380MHz_nand.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | BlockSize = 0x00020000; 21 | PageSize = 0x00000800; 22 | PartitionSize = 0x01000000; 23 | OdmData = 0x300d8000; 24 | 25 | DevType[0] = NvBootDevType_Nand; 26 | DeviceParam[0].NandParams.ClockDivider = 0x00000004; 27 | DeviceParam[0].NandParams.NandTiming2 = 0x0000000a; 28 | DeviceParam[0].NandParams.NandTiming = 0x3b269213; 29 | DeviceParam[0].NandParams.BlockSizeLog2 = 0x00000000; 30 | DeviceParam[0].NandParams.PageSizeLog2 = 0x00000000; 31 | 32 | DevType[1] = NvBootDevType_Nand; 33 | DeviceParam[1].NandParams.ClockDivider = 0x00000004; 34 | DeviceParam[1].NandParams.NandTiming2 = 0x0000000a; 35 | DeviceParam[1].NandParams.NandTiming = 0x3b269213; 36 | DeviceParam[1].NandParams.BlockSizeLog2 = 0x00000000; 37 | DeviceParam[1].NandParams.PageSizeLog2 = 0x00000000; 38 | 39 | DevType[2] = NvBootDevType_Nand; 40 | DeviceParam[2].NandParams.ClockDivider = 0x00000004; 41 | DeviceParam[2].NandParams.NandTiming2 = 0x0000000a; 42 | DeviceParam[2].NandParams.NandTiming = 0x3b269213; 43 | DeviceParam[2].NandParams.BlockSizeLog2 = 0x00000000; 44 | DeviceParam[2].NandParams.PageSizeLog2 = 0x00000000; 45 | 46 | DevType[3] = NvBootDevType_Nand; 47 | DeviceParam[3].NandParams.ClockDivider = 0x00000004; 48 | DeviceParam[3].NandParams.NandTiming2 = 0x0000000a; 49 | DeviceParam[3].NandParams.NandTiming = 0x3b269213; 50 | DeviceParam[3].NandParams.BlockSizeLog2 = 0x00000000; 51 | DeviceParam[3].NandParams.PageSizeLog2 = 0x00000000; 52 | 53 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr2; 54 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 55 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 56 | SDRAM[0].PllMInputDivider = 0x0000000c; 57 | SDRAM[0].PllMFeedbackDivider = 0x000002f8; 58 | SDRAM[0].PllMPostDivider = 0x00000000; 59 | SDRAM[0].PllMStableTime = 0x0000012c; 60 | SDRAM[0].EmcClockDivider = 0x00000001; 61 | SDRAM[0].EmcAutoCalInterval = 0x00000000; 62 | SDRAM[0].EmcAutoCalConfig = 0xe0a61818; 63 | SDRAM[0].EmcAutoCalWait = 0x00000000; 64 | SDRAM[0].EmcPinProgramWait = 0x00000000; 65 | SDRAM[0].EmcRc = 0x00000017; 66 | SDRAM[0].EmcRfc = 0x0000004b; 67 | SDRAM[0].EmcRas = 0x00000012; 68 | SDRAM[0].EmcRp = 0x00000006; 69 | SDRAM[0].EmcR2w = 0x00000004; 70 | SDRAM[0].EmcW2r = 0x00000005; 71 | SDRAM[0].EmcR2p = 0x00000003; 72 | SDRAM[0].EmcW2p = 0x0000000c; 73 | SDRAM[0].EmcRrd = 0x00000003; 74 | SDRAM[0].EmcRdRcd = 0x00000006; 75 | SDRAM[0].EmcWrRcd = 0x00000006; 76 | SDRAM[0].EmcRext = 0x00000001; 77 | SDRAM[0].EmcWdv = 0x00000004; 78 | SDRAM[0].EmcQUseExtra = 0x00000000; 79 | SDRAM[0].EmcQUse = 0x00000005; 80 | SDRAM[0].EmcQRst = 0x00000004; 81 | SDRAM[0].EmcQSafe = 0x00000009; 82 | SDRAM[0].EmcRdv = 0x0000000d; 83 | SDRAM[0].EmcRefresh = 0x00000b5f; 84 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 85 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 86 | SDRAM[0].EmcPdEx2Rd = 0x00000003; 87 | SDRAM[0].EmcPChg2Pden = 0x00000006; 88 | SDRAM[0].EmcAct2Pden = 0x00000006; 89 | SDRAM[0].EmcAr2Pden = 0x00000001; 90 | SDRAM[0].EmcRw2Pden = 0x00000011; 91 | SDRAM[0].EmcTxsr = 0x000000c8; 92 | SDRAM[0].EmcTcke = 0x00000003; 93 | SDRAM[0].EmcTfaw = 0x0000000e; 94 | SDRAM[0].EmcTrpab = 0x00000007; 95 | SDRAM[0].EmcTClkStable = 0x0000000f; 96 | SDRAM[0].EmcTClkStop = 0x00000002; 97 | SDRAM[0].EmcTRefBw = 0x00000000; 98 | SDRAM[0].EmcFbioCfg1 = 0x00000000; 99 | SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000; 100 | SDRAM[0].EmcFbioDqsibDly = 0x24242424; 101 | SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000; 102 | SDRAM[0].EmcFbioQuseDly = 0x64646464; 103 | SDRAM[0].EmcFbioCfg5 = 0x00000083; 104 | SDRAM[0].EmcFbioCfg6 = 0x00000002; 105 | SDRAM[0].EmcFbioSpare = 0x00000000; 106 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 107 | SDRAM[0].EmcMrsResetDll = 0x00000000; 108 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000100; 109 | SDRAM[0].EmcMrs = 0x00000a6a; 110 | SDRAM[0].EmcEmrsEmr2 = 0x00200000; 111 | SDRAM[0].EmcEmrsEmr3 = 0x00300000; 112 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000; 113 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100380; 114 | SDRAM[0].EmcEmrs = 0x00100000; 115 | SDRAM[0].EmcMrw1 = 0x00000000; 116 | SDRAM[0].EmcMrw2 = 0x00000000; 117 | SDRAM[0].EmcMrw3 = 0x00000000; 118 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 119 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 120 | SDRAM[0].EmcAdrCfg1 = 0x00080303; 121 | SDRAM[0].EmcAdrCfg = 0x00080303; 122 | SDRAM[0].McEmemCfg = 0x00100000; 123 | SDRAM[0].McLowLatencyConfig = 0x80000003; 124 | SDRAM[0].EmcCfg2 = 0x00000405; 125 | SDRAM[0].EmcCfgDigDll = 0xf0000413; 126 | SDRAM[0].EmcCfgClktrim0 = 0x00000000; 127 | SDRAM[0].EmcCfgClktrim1 = 0x00000000; 128 | SDRAM[0].EmcCfgClktrim2 = 0x00000000; 129 | SDRAM[0].EmcCfg = 0x0001ff00; 130 | SDRAM[0].EmcDbg = 0x01000000; 131 | SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000; 132 | SDRAM[0].EmcDllXformDqs = 0x00000010; 133 | SDRAM[0].EmcDllXformQUse = 0x00000008; 134 | SDRAM[0].WarmBootWait = 0x00000002; 135 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 136 | SDRAM[0].EmcOdtWrite = 0x00000000; 137 | SDRAM[0].EmcOdtRead = 0x00000000; 138 | SDRAM[0].EmcZcalRefCnt = 0x00000000; 139 | SDRAM[0].EmcZcalWaitCnt = 0x00000000; 140 | SDRAM[0].EmcZcalMrwCmd = 0x00000000; 141 | SDRAM[0].EmcMrwZqInitDev0 = 0x00000000; 142 | SDRAM[0].EmcMrwZqInitDev1 = 0x00000000; 143 | SDRAM[0].EmcMrwZqInitWait = 0x00000000; 144 | SDRAM[0].EmcDdr2Wait = 0x00000002; 145 | SDRAM[0].PmcDdrPwr = 0x00000001; 146 | SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 147 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 148 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 149 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x00000009; 150 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 151 | SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 152 | SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 153 | SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 154 | -------------------------------------------------------------------------------- /tegra20/nvidia/harmony/harmony_a02_12Mhz_H5PS1G83EFR-S6C_333Mhz_1GB_2K8Nand_HY27UF084G2B-TP.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | BlockSize = 0x00020000; 21 | PageSize = 0x00000800; 22 | PartitionSize = 0x01000000; 23 | OdmData = 0x300d8000; 24 | 25 | DevType[0] = NvBootDevType_Nand; 26 | DeviceParam[0].NandParams.ClockDivider = 0x00000004; 27 | DeviceParam[0].NandParams.NandTiming2 = 0x0000000a; 28 | DeviceParam[0].NandParams.NandTiming = 0x3b269213; 29 | DeviceParam[0].NandParams.BlockSizeLog2 = 0x00000000; 30 | DeviceParam[0].NandParams.PageSizeLog2 = 0x00000000; 31 | 32 | DevType[1] = NvBootDevType_Nand; 33 | DeviceParam[1].NandParams.ClockDivider = 0x00000004; 34 | DeviceParam[1].NandParams.NandTiming2 = 0x0000000a; 35 | DeviceParam[1].NandParams.NandTiming = 0x3b269213; 36 | DeviceParam[1].NandParams.BlockSizeLog2 = 0x00000000; 37 | DeviceParam[1].NandParams.PageSizeLog2 = 0x00000000; 38 | 39 | DevType[2] = NvBootDevType_Nand; 40 | DeviceParam[2].NandParams.ClockDivider = 0x00000004; 41 | DeviceParam[2].NandParams.NandTiming2 = 0x0000000a; 42 | DeviceParam[2].NandParams.NandTiming = 0x3b269213; 43 | DeviceParam[2].NandParams.BlockSizeLog2 = 0x00000000; 44 | DeviceParam[2].NandParams.PageSizeLog2 = 0x00000000; 45 | 46 | DevType[3] = NvBootDevType_Nand; 47 | DeviceParam[3].NandParams.ClockDivider = 0x00000004; 48 | DeviceParam[3].NandParams.NandTiming2 = 0x0000000a; 49 | DeviceParam[3].NandParams.NandTiming = 0x3b269213; 50 | DeviceParam[3].NandParams.BlockSizeLog2 = 0x00000000; 51 | DeviceParam[3].NandParams.PageSizeLog2 = 0x00000000; 52 | 53 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr2; 54 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 55 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 56 | SDRAM[0].PllMInputDivider = 0x0000000c; 57 | SDRAM[0].PllMFeedbackDivider = 0x0000029a; 58 | SDRAM[0].PllMPostDivider = 0x00000000; 59 | SDRAM[0].PllMStableTime = 0x0000012c; 60 | SDRAM[0].EmcClockDivider = 0x00000001; 61 | SDRAM[0].EmcAutoCalInterval = 0x00000000; 62 | SDRAM[0].EmcAutoCalConfig = 0xe0a61818; 63 | SDRAM[0].EmcAutoCalWait = 0x00000000; 64 | SDRAM[0].EmcPinProgramWait = 0x00000000; 65 | SDRAM[0].EmcRc = 0x00000014; 66 | SDRAM[0].EmcRfc = 0x0000002b; 67 | SDRAM[0].EmcRas = 0x0000000f; 68 | SDRAM[0].EmcRp = 0x00000005; 69 | SDRAM[0].EmcR2w = 0x00000004; 70 | SDRAM[0].EmcW2r = 0x00000005; 71 | SDRAM[0].EmcR2p = 0x00000003; 72 | SDRAM[0].EmcW2p = 0x0000000c; 73 | SDRAM[0].EmcRrd = 0x00000003; 74 | SDRAM[0].EmcRdRcd = 0x00000005; 75 | SDRAM[0].EmcWrRcd = 0x00000005; 76 | SDRAM[0].EmcRext = 0x00000001; 77 | SDRAM[0].EmcWdv = 0x00000004; 78 | SDRAM[0].EmcQUseExtra = 0x00000000; 79 | SDRAM[0].EmcQUse = 0x00000005; 80 | SDRAM[0].EmcQRst = 0x00000004; 81 | SDRAM[0].EmcQSafe = 0x00000009; 82 | SDRAM[0].EmcRdv = 0x0000000d; 83 | SDRAM[0].EmcRefresh = 0x000009ff; 84 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 85 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 86 | SDRAM[0].EmcPdEx2Rd = 0x00000003; 87 | SDRAM[0].EmcPChg2Pden = 0x00000005; 88 | SDRAM[0].EmcAct2Pden = 0x00000005; 89 | SDRAM[0].EmcAr2Pden = 0x00000001; 90 | SDRAM[0].EmcRw2Pden = 0x0000000f; 91 | SDRAM[0].EmcTxsr = 0x000000c8; 92 | SDRAM[0].EmcTcke = 0x00000003; 93 | SDRAM[0].EmcTfaw = 0x0000000c; 94 | SDRAM[0].EmcTrpab = 0x00000006; 95 | SDRAM[0].EmcTClkStable = 0x00000008; 96 | SDRAM[0].EmcTClkStop = 0x00000002; 97 | SDRAM[0].EmcTRefBw = 0x00000000; 98 | SDRAM[0].EmcFbioCfg1 = 0x00000000; 99 | SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000; 100 | SDRAM[0].EmcFbioDqsibDly = 0x1c1c2020; 101 | SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000; 102 | SDRAM[0].EmcFbioQuseDly = 0x5a504646; 103 | SDRAM[0].EmcFbioCfg5 = 0x00000083; 104 | SDRAM[0].EmcFbioCfg6 = 0x00000002; 105 | SDRAM[0].EmcFbioSpare = 0x00000000; 106 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 107 | SDRAM[0].EmcMrsResetDll = 0x00000000; 108 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000100; 109 | SDRAM[0].EmcMrs = 0x00000a6a; 110 | SDRAM[0].EmcEmrsEmr2 = 0x00200000; 111 | SDRAM[0].EmcEmrsEmr3 = 0x00300000; 112 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000; 113 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100384; 114 | SDRAM[0].EmcEmrs = 0x00100004; 115 | SDRAM[0].EmcMrw1 = 0x00000000; 116 | SDRAM[0].EmcMrw2 = 0x00000000; 117 | SDRAM[0].EmcMrw3 = 0x00000000; 118 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 119 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 120 | SDRAM[0].EmcAdrCfg1 = 0x00070303; 121 | SDRAM[0].EmcAdrCfg = 0x01070303; 122 | SDRAM[0].McEmemCfg = 0x00100000; 123 | SDRAM[0].McLowLatencyConfig = 0x80000003; 124 | SDRAM[0].EmcCfg2 = 0x00000405; 125 | SDRAM[0].EmcCfgDigDll = 0xf0000313; 126 | SDRAM[0].EmcCfgClktrim0 = 0x00000000; 127 | SDRAM[0].EmcCfgClktrim1 = 0x00000000; 128 | SDRAM[0].EmcCfgClktrim2 = 0x00000000; 129 | SDRAM[0].EmcCfg = 0x2001ff01; 130 | SDRAM[0].EmcDbg = 0x01000000; 131 | SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000; 132 | SDRAM[0].EmcDllXformDqs = 0x00000010; 133 | SDRAM[0].EmcDllXformQUse = 0x00000008; 134 | SDRAM[0].WarmBootWait = 0x00000002; 135 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 136 | SDRAM[0].EmcOdtWrite = 0x00000000; 137 | SDRAM[0].EmcOdtRead = 0x00000000; 138 | SDRAM[0].EmcZcalRefCnt = 0x00000000; 139 | SDRAM[0].EmcZcalWaitCnt = 0x00000000; 140 | SDRAM[0].EmcZcalMrwCmd = 0x00000000; 141 | SDRAM[0].EmcMrwZqInitDev0 = 0x00000000; 142 | SDRAM[0].EmcMrwZqInitDev1 = 0x00000000; 143 | SDRAM[0].EmcMrwZqInitWait = 0x00000000; 144 | SDRAM[0].EmcDdr2Wait = 0x00000002; 145 | SDRAM[0].PmcDdrPwr = 0x00000001; 146 | SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 147 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 148 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 149 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 150 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 151 | SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 152 | SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 153 | SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 154 | -------------------------------------------------------------------------------- /tegra30/avionic-design/tamonten-ng/TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2013 Avionic Design GmbH 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00030001; 20 | BlockSize = 0x00004000; 21 | PageSize = 0x00000200; 22 | PartitionSize = 0x02000000; 23 | OdmData = 0x400c0000; 24 | 25 | DevType[0] = NvBootDevType_Sdmmc; 26 | DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009; 27 | DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit; 28 | DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000; 29 | DeviceParam[0].SdmmcParams.SdController = 0x00000000; 30 | 31 | DevType[1] = NvBootDevType_Sdmmc; 32 | DeviceParam[1].SdmmcParams.ClockDivider = 0x00000009; 33 | DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit; 34 | DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000; 35 | DeviceParam[1].SdmmcParams.SdController = 0x00000000; 36 | 37 | DevType[2] = NvBootDevType_Sdmmc; 38 | DeviceParam[2].SdmmcParams.ClockDivider = 0x00000009; 39 | DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit; 40 | DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000; 41 | DeviceParam[2].SdmmcParams.SdController = 0x00000000; 42 | 43 | DevType[3] = NvBootDevType_Sdmmc; 44 | DeviceParam[3].SdmmcParams.ClockDivider = 0x00000009; 45 | DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit; 46 | DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000; 47 | DeviceParam[3].SdmmcParams.SdController = 0x00000000; 48 | 49 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; 50 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 51 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 52 | SDRAM[0].PllMInputDivider = 0x0000000c; 53 | SDRAM[0].PllMFeedbackDivider = 0x000002ee; 54 | SDRAM[0].PllMPostDivider = 0x00000000; 55 | SDRAM[0].PllMStableTime = 0x0000012c; 56 | SDRAM[0].EmcClockDivider = 0x00000000; 57 | SDRAM[0].EmcClockSource = 0x00000000; 58 | SDRAM[0].EmcClockUsePllMUD = 0x00000001; 59 | SDRAM[0].EmcAutoCalInterval = 0x001fffff; 60 | SDRAM[0].EmcAutoCalConfig = 0xa0f10000; 61 | SDRAM[0].EmcAutoCalWait = 0x00000064; 62 | SDRAM[0].EmcAdrCfg = 0x00000000; 63 | SDRAM[0].EmcPinProgramWait = 0x00000001; 64 | SDRAM[0].EmcPinExtraWait = 0x00000000; 65 | SDRAM[0].EmcTimingControlWait = 0x00000000; 66 | SDRAM[0].EmcRc = 0x00000023; 67 | SDRAM[0].EmcRfc = 0x00000094; 68 | SDRAM[0].EmcRas = 0x00000019; 69 | SDRAM[0].EmcRp = 0x00000009; 70 | SDRAM[0].EmcR2w = 0x00000005; 71 | SDRAM[0].EmcW2r = 0x0000000d; 72 | SDRAM[0].EmcR2p = 0x00000004; 73 | SDRAM[0].EmcW2p = 0x00000013; 74 | SDRAM[0].EmcRdRcd = 0x00000009; 75 | SDRAM[0].EmcWrRcd = 0x00000009; 76 | SDRAM[0].EmcRrd = 0x00000004; 77 | SDRAM[0].EmcRext = 0x00000001; 78 | SDRAM[0].EmcWext = 0x00000000; 79 | SDRAM[0].EmcWdv = 0x00000007; 80 | SDRAM[0].EmcQUse = 0x0000000c; 81 | SDRAM[0].EmcQRst = 0x00000009; 82 | SDRAM[0].EmcQSafe = 0x0000000a; 83 | SDRAM[0].EmcRdv = 0x00000012; 84 | SDRAM[0].EmcCtt = 0x00000000; 85 | SDRAM[0].EmcCttDuration = 0x00000000; 86 | SDRAM[0].EmcRefresh = 0x0000169a; 87 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 88 | SDRAM[0].EmcPreRefreshReqCnt = 0x000005a6; 89 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 90 | SDRAM[0].EmcPdEx2Rd = 0x00000010; 91 | SDRAM[0].EmcPChg2Pden = 0x00000001; 92 | SDRAM[0].EmcAct2Pden = 0x00000000; 93 | SDRAM[0].EmcAr2Pden = 0x0000000e; 94 | SDRAM[0].EmcRw2Pden = 0x00000018; 95 | SDRAM[0].EmcTxsr = 0x0000009e; 96 | SDRAM[0].EmcTxsrDll = 0x00000200; 97 | SDRAM[0].EmcTcke = 0x00000005; 98 | SDRAM[0].EmcTfaw = 0x0000001e; 99 | SDRAM[0].EmcTrpab = 0x00000000; 100 | SDRAM[0].EmcTClkStable = 0x00000007; 101 | SDRAM[0].EmcTClkStop = 0x00000008; 102 | SDRAM[0].EmcTRefBw = 0x000016da; 103 | SDRAM[0].EmcQUseExtra = 0x00000000; 104 | SDRAM[0].EmcFbioCfg5 = 0x00005088; 105 | SDRAM[0].EmcFbioCfg6 = 0x00000004; 106 | SDRAM[0].EmcFbioSpare = 0xd8000000; 107 | SDRAM[0].EmcCfgRsv = 0xff00ff49; 108 | SDRAM[0].EmcMrs = 0x80000d71; 109 | SDRAM[0].EmcEmrs = 0x80100002; 110 | SDRAM[0].EmcMrw1 = 0x00000000; 111 | SDRAM[0].EmcMrw2 = 0x00000000; 112 | SDRAM[0].EmcMrw3 = 0x00000000; 113 | SDRAM[0].EmcMrwExtra = 0x00000000; 114 | SDRAM[0].EmcWarmBootMrw1 = 0x00000000; 115 | SDRAM[0].EmcWarmBootMrw2 = 0x00000000; 116 | SDRAM[0].EmcWarmBootMrw3 = 0x00000000; 117 | SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; 118 | SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; 119 | SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; 120 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 121 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 122 | SDRAM[0].EmcMrsWaitCnt = 0x012a000c; 123 | SDRAM[0].EmcCfg = 0x23e00000; 124 | SDRAM[0].EmcCfg2 = 0x000c0099; 125 | SDRAM[0].EmcDbg = 0x01000400; 126 | SDRAM[0].EmcCmdQ = 0x10004408; 127 | SDRAM[0].EmcMc2EmcQ = 0x06000404; 128 | SDRAM[0].EmcDynSelfRefControl = 0x80002d93; 129 | SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; 130 | SDRAM[0].EmcCfgDigDll = 0xf0080191; 131 | SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; 132 | SDRAM[0].EmcDevSelect = 0x00000002; 133 | SDRAM[0].EmcSelDpdCtrl = 0x0004032c; 134 | SDRAM[0].EmcDllXformDqs0 = 0x00000008; 135 | SDRAM[0].EmcDllXformDqs1 = 0x00000008; 136 | SDRAM[0].EmcDllXformDqs2 = 0x00000008; 137 | SDRAM[0].EmcDllXformDqs3 = 0x00000008; 138 | SDRAM[0].EmcDllXformDqs4 = 0x00000008; 139 | SDRAM[0].EmcDllXformDqs5 = 0x00000008; 140 | SDRAM[0].EmcDllXformDqs6 = 0x00000008; 141 | SDRAM[0].EmcDllXformDqs7 = 0x00000008; 142 | SDRAM[0].EmcDllXformQUse0 = 0x00000000; 143 | SDRAM[0].EmcDllXformQUse1 = 0x00000000; 144 | SDRAM[0].EmcDllXformQUse2 = 0x00000000; 145 | SDRAM[0].EmcDllXformQUse3 = 0x00000000; 146 | SDRAM[0].EmcDllXformQUse4 = 0x00000000; 147 | SDRAM[0].EmcDllXformQUse5 = 0x00000000; 148 | SDRAM[0].EmcDllXformQUse6 = 0x00000000; 149 | SDRAM[0].EmcDllXformQUse7 = 0x00000000; 150 | SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; 151 | SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; 152 | SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; 153 | SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; 154 | SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; 155 | SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; 156 | SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; 157 | SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; 158 | SDRAM[0].EmcDllXformDq0 = 0x0000000c; 159 | SDRAM[0].EmcDllXformDq1 = 0x0000000c; 160 | SDRAM[0].EmcDllXformDq2 = 0x0000000c; 161 | SDRAM[0].EmcDllXformDq3 = 0x0000000c; 162 | SDRAM[0].WarmBootWait = 0x00000002; 163 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 164 | SDRAM[0].EmcOdtWrite = 0x00000000; 165 | SDRAM[0].EmcOdtRead = 0x00000000; 166 | SDRAM[0].EmcZcalInterval = 0x00020000; 167 | SDRAM[0].EmcZcalWaitCnt = 0x00000040; 168 | SDRAM[0].EmcZcalMrwCmd = 0x80000000; 169 | SDRAM[0].EmcMrsResetDll = 0x00000000; 170 | SDRAM[0].EmcZcalInitDev0 = 0x80000011; 171 | SDRAM[0].EmcZcalInitDev1 = 0x00000000; 172 | SDRAM[0].EmcZcalInitWait = 0x00000001; 173 | SDRAM[0].EmcZcalColdBootEnable = 0x00000001; 174 | SDRAM[0].EmcZcalWarmBootEnable = 0x00000001; 175 | SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab; 176 | SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000011; 177 | SDRAM[0].EmcZcalWarmBootWait = 0x00000001; 178 | SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; 179 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 180 | SDRAM[0].EmcEmrsEmr2 = 0x80200018; 181 | SDRAM[0].EmcEmrsEmr3 = 0x80300000; 182 | SDRAM[0].EmcMrsExtra = 0x80000d71; 183 | SDRAM[0].EmcWarmBootMrs = 0x80100002; 184 | SDRAM[0].EmcWarmBootEmrs = 0x80000d71; 185 | SDRAM[0].EmcWarmBootEmr2 = 0x80200018; 186 | SDRAM[0].EmcWarmBootEmr3 = 0x80300000; 187 | SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; 188 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; 189 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; 190 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; 191 | SDRAM[0].EmcDdr2Wait = 0x00000000; 192 | SDRAM[0].EmcClkenOverride = 0x00000000; 193 | SDRAM[0].EmcExtraRefreshNum = 0x00000002; 194 | SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; 195 | SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; 196 | SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; 197 | SDRAM[0].PmcVddpSel = 0x00000002; 198 | SDRAM[0].PmcDdrPwr = 0x00000003; 199 | SDRAM[0].PmcDdrCfg = 0x00000002; 200 | SDRAM[0].PmcIoDpdReq = 0x80800000; 201 | SDRAM[0].PmcENoVttGen = 0x00000000; 202 | SDRAM[0].PmcNoIoPower = 0x00000000; 203 | SDRAM[0].EmcXm2CmdPadCtrl = 0x000002a0; 204 | SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; 205 | SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; 206 | SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0800013d; 207 | SDRAM[0].EmcXm2DqsPadCtrl3 = 0x08000021; 208 | SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; 209 | SDRAM[0].EmcXm2DqPadCtrl2 = 0x22220000; 210 | SDRAM[0].EmcXm2ClkPadCtrl = 0x77fff884; 211 | SDRAM[0].EmcXm2CompPadCtrl = 0x01f1f501; 212 | SDRAM[0].EmcXm2VttGenPadCtrl = 0x07077404; 213 | SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x54000000; 214 | SDRAM[0].EmcXm2QUsePadCtrl = 0x080001e8; 215 | SDRAM[0].McEmemAdrCfg = 0x00000000; 216 | SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; 217 | SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; 218 | SDRAM[0].McEmemCfg = 0x00000400; 219 | SDRAM[0].McEmemArbCfg = 0x0000000b; 220 | SDRAM[0].McEmemArbOutstandingReq = 0x80000087; 221 | SDRAM[0].McEmemArbTimingRcd = 0x00000004; 222 | SDRAM[0].McEmemArbTimingRp = 0x00000005; 223 | SDRAM[0].McEmemArbTimingRc = 0x00000012; 224 | SDRAM[0].McEmemArbTimingRas = 0x0000000c; 225 | SDRAM[0].McEmemArbTimingFaw = 0x0000000e; 226 | SDRAM[0].McEmemArbTimingRrd = 0x00000002; 227 | SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003; 228 | SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c; 229 | SDRAM[0].McEmemArbTimingR2R = 0x00000002; 230 | SDRAM[0].McEmemArbTimingW2W = 0x00000002; 231 | SDRAM[0].McEmemArbTimingR2W = 0x00000004; 232 | SDRAM[0].McEmemArbTimingW2R = 0x00000008; 233 | SDRAM[0].McEmemArbDaTurns = 0x08040202; 234 | SDRAM[0].McEmemArbDaCovers = 0x00160d12; 235 | SDRAM[0].McEmemArbMisc0 = 0x710c2213; 236 | SDRAM[0].McEmemArbMisc1 = 0x78000000; 237 | SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; 238 | SDRAM[0].McEmemArbOverride = 0x00000080; 239 | SDRAM[0].McEmemArbRsv = 0xff00ff00; 240 | SDRAM[0].McClkenOverride = 0x00000000; 241 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/colibri_t20-256-hsmmc.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Toradex AG. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | PartitionSize = 16777216; 21 | BlockSize = 16384; 22 | PageSize = 512; 23 | OdmData = 0x100C0000; 24 | 25 | DevType[0] = Sdmmc; 26 | DeviceParam[0].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz. 27 | DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 28 | DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0; 29 | 30 | DevType[1] = Sdmmc; 31 | DeviceParam[1].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz. 32 | DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 33 | DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0; 34 | 35 | DevType[2] = Sdmmc; 36 | DeviceParam[2].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz. 37 | DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 38 | DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0; 39 | 40 | DevType[3] = Sdmmc; 41 | DeviceParam[3].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz. 42 | DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 43 | DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0; 44 | 45 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr2; 46 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 47 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 48 | SDRAM[0].PllMInputDivider = 0x0000000d; 49 | SDRAM[0].PllMFeedbackDivider = 0x0000029a; 50 | SDRAM[0].PllMPostDivider = 0x00000000; 51 | SDRAM[0].PllMStableTime = 0x0000012c; 52 | SDRAM[0].EmcClockDivider = 0x00000001; 53 | SDRAM[0].EmcAutoCalInterval = 0x00000000; 54 | SDRAM[0].EmcAutoCalConfig = 0xe0a61111; 55 | SDRAM[0].EmcAutoCalWait = 0x00000000; 56 | SDRAM[0].EmcPinProgramWait = 0x00000000; 57 | SDRAM[0].EmcRc = 0x00000014; 58 | SDRAM[0].EmcRfc = 0x0000002b; 59 | SDRAM[0].EmcRas = 0x0000000f; 60 | SDRAM[0].EmcRp = 0x00000005; 61 | SDRAM[0].EmcR2w = 0x00000005; 62 | SDRAM[0].EmcW2r = 0x00000005; 63 | SDRAM[0].EmcR2p = 0x00000003; 64 | SDRAM[0].EmcW2p = 0x0000000c; 65 | SDRAM[0].EmcRdRcd = 0x00000005; 66 | SDRAM[0].EmcWrRcd = 0x00000005; 67 | SDRAM[0].EmcRrd = 0x00000003; 68 | SDRAM[0].EmcRext = 0x00000001; 69 | SDRAM[0].EmcWdv = 0x00000004; 70 | SDRAM[0].EmcQUse = 0x00000005; 71 | SDRAM[0].EmcQRst = 0x00000004; 72 | SDRAM[0].EmcQSafe = 0x00000009; 73 | SDRAM[0].EmcRdv = 0x0000000d; 74 | SDRAM[0].EmcRefresh = 0x000009ff; 75 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 76 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 77 | SDRAM[0].EmcPdEx2Rd = 0x00000003; 78 | SDRAM[0].EmcPChg2Pden = 0x00000005; 79 | SDRAM[0].EmcAct2Pden = 0x00000005; 80 | SDRAM[0].EmcAr2Pden = 0x00000001; 81 | SDRAM[0].EmcRw2Pden = 0x0000000f; 82 | SDRAM[0].EmcTxsr = 0x000000c8; 83 | SDRAM[0].EmcTcke = 0x00000003; 84 | SDRAM[0].EmcTfaw = 0x0000000c; 85 | SDRAM[0].EmcTrpab = 0x00000006; 86 | SDRAM[0].EmcTClkStable = 0x00000008; 87 | SDRAM[0].EmcTClkStop = 0x00000002; 88 | SDRAM[0].EmcTRefBw = 0x00000000; 89 | SDRAM[0].EmcQUseExtra = 0x00000000; 90 | SDRAM[0].EmcFbioCfg1 = 0x00000000; 91 | SDRAM[0].EmcFbioDqsibDly = 0x20202020; 92 | SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000; 93 | SDRAM[0].EmcFbioQuseDly = 0x50465046; 94 | SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000; 95 | SDRAM[0].EmcFbioCfg5 = 0x00000183; 96 | SDRAM[0].EmcFbioCfg6 = 0x00000002; 97 | SDRAM[0].EmcFbioSpare = 0x00000000; 98 | SDRAM[0].EmcMrs = 0x00000a6a; 99 | SDRAM[0].EmcEmrs = 0x00100006; 100 | SDRAM[0].EmcMrw1 = 0x00000000; 101 | SDRAM[0].EmcMrw2 = 0x00000000; 102 | SDRAM[0].EmcMrw3 = 0x00000000; 103 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 104 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 105 | SDRAM[0].EmcAdrCfg = 0x00060303; 106 | SDRAM[0].EmcAdrCfg1 = 0x00060303; 107 | SDRAM[0].McEmemCfg = 0x00040000; 108 | SDRAM[0].McLowLatencyConfig = 0x80000003; 109 | SDRAM[0].EmcCfg = 0x0301ff00; 110 | SDRAM[0].EmcCfg2 = 0x00000405; 111 | SDRAM[0].EmcDbg = 0x01000400; 112 | SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000; 113 | SDRAM[0].EmcCfgDigDll = 0xf0000313; 114 | SDRAM[0].EmcDllXformDqs = 0x00000010; 115 | SDRAM[0].EmcDllXformQUse = 0x00000008; 116 | SDRAM[0].WarmBootWait = 0x00000002; 117 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 118 | SDRAM[0].EmcOdtWrite = 0x80000001; 119 | SDRAM[0].EmcOdtRead = 0x80000001; 120 | SDRAM[0].EmcZcalRefCnt = 0x00000000; 121 | SDRAM[0].EmcZcalWaitCnt = 0x00000000; 122 | SDRAM[0].EmcZcalMrwCmd = 0x00000000; 123 | SDRAM[0].EmcMrsResetDll = 0x00000000; 124 | SDRAM[0].EmcMrwZqInitDev0 = 0x00000000; 125 | SDRAM[0].EmcMrwZqInitDev1 = 0x00000000; 126 | SDRAM[0].EmcMrwZqInitWait = 0x00000000; 127 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 128 | SDRAM[0].EmcEmrsEmr2 = 0x00200000; 129 | SDRAM[0].EmcEmrsEmr3 = 0x00300000; 130 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000; 131 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000100; 132 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100386; 133 | SDRAM[0].EmcDdr2Wait = 0x00000002; 134 | SDRAM[0].EmcCfgClktrim0 = 0x00000000; 135 | SDRAM[0].EmcCfgClktrim1 = 0x00000000; 136 | SDRAM[0].EmcCfgClktrim2 = 0x00000000; 137 | SDRAM[0].PmcDdrPwr = 0x00000001; 138 | SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 139 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 140 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 141 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 142 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 143 | SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 144 | SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 145 | SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 146 | 147 | SDRAM[1].MemoryType = NvBootMemoryType_Ddr2; 148 | SDRAM[1].PllMChargePumpSetupControl = 0x00000008; 149 | SDRAM[1].PllMLoopFilterSetupControl = 0x00000000; 150 | SDRAM[1].PllMInputDivider = 0x0000000d; 151 | SDRAM[1].PllMFeedbackDivider = 0x0000029a; 152 | SDRAM[1].PllMPostDivider = 0x00000000; 153 | SDRAM[1].PllMStableTime = 0x0000012c; 154 | SDRAM[1].EmcClockDivider = 0x00000001; 155 | SDRAM[1].EmcAutoCalInterval = 0x00000000; 156 | SDRAM[1].EmcAutoCalConfig = 0xe0a61111; 157 | SDRAM[1].EmcAutoCalWait = 0x00000000; 158 | SDRAM[1].EmcPinProgramWait = 0x00000000; 159 | SDRAM[1].EmcRc = 0x00000014; 160 | SDRAM[1].EmcRfc = 0x0000002b; 161 | SDRAM[1].EmcRas = 0x0000000f; 162 | SDRAM[1].EmcRp = 0x00000005; 163 | SDRAM[1].EmcR2w = 0x00000005; 164 | SDRAM[1].EmcW2r = 0x00000005; 165 | SDRAM[1].EmcR2p = 0x00000003; 166 | SDRAM[1].EmcW2p = 0x0000000c; 167 | SDRAM[1].EmcRdRcd = 0x00000005; 168 | SDRAM[1].EmcWrRcd = 0x00000005; 169 | SDRAM[1].EmcRrd = 0x00000003; 170 | SDRAM[1].EmcRext = 0x00000001; 171 | SDRAM[1].EmcWdv = 0x00000004; 172 | SDRAM[1].EmcQUse = 0x00000005; 173 | SDRAM[1].EmcQRst = 0x00000004; 174 | SDRAM[1].EmcQSafe = 0x00000009; 175 | SDRAM[1].EmcRdv = 0x0000000d; 176 | SDRAM[1].EmcRefresh = 0x000009ff; 177 | SDRAM[1].EmcBurstRefreshNum = 0x00000000; 178 | SDRAM[1].EmcPdEx2Wr = 0x00000003; 179 | SDRAM[1].EmcPdEx2Rd = 0x00000003; 180 | SDRAM[1].EmcPChg2Pden = 0x00000005; 181 | SDRAM[1].EmcAct2Pden = 0x00000005; 182 | SDRAM[1].EmcAr2Pden = 0x00000001; 183 | SDRAM[1].EmcRw2Pden = 0x0000000f; 184 | SDRAM[1].EmcTxsr = 0x000000c8; 185 | SDRAM[1].EmcTcke = 0x00000003; 186 | SDRAM[1].EmcTfaw = 0x0000000c; 187 | SDRAM[1].EmcTrpab = 0x00000006; 188 | SDRAM[1].EmcTClkStable = 0x00000008; 189 | SDRAM[1].EmcTClkStop = 0x00000002; 190 | SDRAM[1].EmcTRefBw = 0x00000000; 191 | SDRAM[1].EmcQUseExtra = 0x00000000; 192 | SDRAM[1].EmcFbioCfg1 = 0x00000000; 193 | SDRAM[1].EmcFbioDqsibDly = 0x20202020; 194 | SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000; 195 | SDRAM[1].EmcFbioQuseDly = 0x50465046; 196 | SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000; 197 | SDRAM[1].EmcFbioCfg5 = 0x00000183; 198 | SDRAM[1].EmcFbioCfg6 = 0x00000002; 199 | SDRAM[1].EmcFbioSpare = 0x00000000; 200 | SDRAM[1].EmcMrs = 0x00000a6a; 201 | SDRAM[1].EmcEmrs = 0x00100006; 202 | SDRAM[1].EmcMrw1 = 0x00000000; 203 | SDRAM[1].EmcMrw2 = 0x00000000; 204 | SDRAM[1].EmcMrw3 = 0x00000000; 205 | SDRAM[1].EmcMrwResetCommand = 0x00000000; 206 | SDRAM[1].EmcMrwResetNInitWait = 0x00000000; 207 | SDRAM[1].EmcAdrCfg = 0x00060303; 208 | SDRAM[1].EmcAdrCfg1 = 0x00060303; 209 | SDRAM[1].McEmemCfg = 0x00040000; 210 | SDRAM[1].McLowLatencyConfig = 0x80000003; 211 | SDRAM[1].EmcCfg = 0x0301ff00; 212 | SDRAM[1].EmcCfg2 = 0x00000405; 213 | SDRAM[1].EmcDbg = 0x01000400; 214 | SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000; 215 | SDRAM[1].EmcCfgDigDll = 0xf0000313; 216 | SDRAM[1].EmcDllXformDqs = 0x00000010; 217 | SDRAM[1].EmcDllXformQUse = 0x00000008; 218 | SDRAM[1].WarmBootWait = 0x00000002; 219 | SDRAM[1].EmcCttTermCtrl = 0x00000802; 220 | SDRAM[1].EmcOdtWrite = 0x80000001; 221 | SDRAM[1].EmcOdtRead = 0x80000001; 222 | SDRAM[1].EmcZcalRefCnt = 0x00000000; 223 | SDRAM[1].EmcZcalWaitCnt = 0x00000000; 224 | SDRAM[1].EmcZcalMrwCmd = 0x00000000; 225 | SDRAM[1].EmcMrsResetDll = 0x00000000; 226 | SDRAM[1].EmcMrwZqInitDev0 = 0x00000000; 227 | SDRAM[1].EmcMrwZqInitDev1 = 0x00000000; 228 | SDRAM[1].EmcMrwZqInitWait = 0x00000000; 229 | SDRAM[1].EmcMrsResetDllWait = 0x00000000; 230 | SDRAM[1].EmcEmrsEmr2 = 0x00200000; 231 | SDRAM[1].EmcEmrsEmr3 = 0x00300000; 232 | SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000; 233 | SDRAM[1].EmcMrsDdr2DllReset = 0x00000100; 234 | SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100386; 235 | SDRAM[1].EmcDdr2Wait = 0x00000002; 236 | SDRAM[1].EmcCfgClktrim0 = 0x00000000; 237 | SDRAM[1].EmcCfgClktrim1 = 0x00000000; 238 | SDRAM[1].EmcCfgClktrim2 = 0x00000000; 239 | SDRAM[1].PmcDdrPwr = 0x00000001; 240 | SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 241 | SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 242 | SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 243 | SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 244 | SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 245 | SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 246 | SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 247 | SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 248 | 249 | SDRAM[2].MemoryType = NvBootMemoryType_Ddr2; 250 | SDRAM[2].PllMChargePumpSetupControl = 0x00000008; 251 | SDRAM[2].PllMLoopFilterSetupControl = 0x00000000; 252 | SDRAM[2].PllMInputDivider = 0x0000000d; 253 | SDRAM[2].PllMFeedbackDivider = 0x0000029a; 254 | SDRAM[2].PllMPostDivider = 0x00000000; 255 | SDRAM[2].PllMStableTime = 0x0000012c; 256 | SDRAM[2].EmcClockDivider = 0x00000001; 257 | SDRAM[2].EmcAutoCalInterval = 0x00000000; 258 | SDRAM[2].EmcAutoCalConfig = 0xe0a61111; 259 | SDRAM[2].EmcAutoCalWait = 0x00000000; 260 | SDRAM[2].EmcPinProgramWait = 0x00000000; 261 | SDRAM[2].EmcRc = 0x00000014; 262 | SDRAM[2].EmcRfc = 0x0000002b; 263 | SDRAM[2].EmcRas = 0x0000000f; 264 | SDRAM[2].EmcRp = 0x00000005; 265 | SDRAM[2].EmcR2w = 0x00000005; 266 | SDRAM[2].EmcW2r = 0x00000005; 267 | SDRAM[2].EmcR2p = 0x00000003; 268 | SDRAM[2].EmcW2p = 0x0000000c; 269 | SDRAM[2].EmcRdRcd = 0x00000005; 270 | SDRAM[2].EmcWrRcd = 0x00000005; 271 | SDRAM[2].EmcRrd = 0x00000003; 272 | SDRAM[2].EmcRext = 0x00000001; 273 | SDRAM[2].EmcWdv = 0x00000004; 274 | SDRAM[2].EmcQUse = 0x00000005; 275 | SDRAM[2].EmcQRst = 0x00000004; 276 | SDRAM[2].EmcQSafe = 0x00000009; 277 | SDRAM[2].EmcRdv = 0x0000000d; 278 | SDRAM[2].EmcRefresh = 0x000009ff; 279 | SDRAM[2].EmcBurstRefreshNum = 0x00000000; 280 | SDRAM[2].EmcPdEx2Wr = 0x00000003; 281 | SDRAM[2].EmcPdEx2Rd = 0x00000003; 282 | SDRAM[2].EmcPChg2Pden = 0x00000005; 283 | SDRAM[2].EmcAct2Pden = 0x00000005; 284 | SDRAM[2].EmcAr2Pden = 0x00000001; 285 | SDRAM[2].EmcRw2Pden = 0x0000000f; 286 | SDRAM[2].EmcTxsr = 0x000000c8; 287 | SDRAM[2].EmcTcke = 0x00000003; 288 | SDRAM[2].EmcTfaw = 0x0000000c; 289 | SDRAM[2].EmcTrpab = 0x00000006; 290 | SDRAM[2].EmcTClkStable = 0x00000008; 291 | SDRAM[2].EmcTClkStop = 0x00000002; 292 | SDRAM[2].EmcTRefBw = 0x00000000; 293 | SDRAM[2].EmcQUseExtra = 0x00000000; 294 | SDRAM[2].EmcFbioCfg1 = 0x00000000; 295 | SDRAM[2].EmcFbioDqsibDly = 0x20202020; 296 | SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000; 297 | SDRAM[2].EmcFbioQuseDly = 0x50465046; 298 | SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000; 299 | SDRAM[2].EmcFbioCfg5 = 0x00000183; 300 | SDRAM[2].EmcFbioCfg6 = 0x00000002; 301 | SDRAM[2].EmcFbioSpare = 0x00000000; 302 | SDRAM[2].EmcMrs = 0x00000a6a; 303 | SDRAM[2].EmcEmrs = 0x00100006; 304 | SDRAM[2].EmcMrw1 = 0x00000000; 305 | SDRAM[2].EmcMrw2 = 0x00000000; 306 | SDRAM[2].EmcMrw3 = 0x00000000; 307 | SDRAM[2].EmcMrwResetCommand = 0x00000000; 308 | SDRAM[2].EmcMrwResetNInitWait = 0x00000000; 309 | SDRAM[2].EmcAdrCfg = 0x00060303; 310 | SDRAM[2].EmcAdrCfg1 = 0x00060303; 311 | SDRAM[2].McEmemCfg = 0x00040000; 312 | SDRAM[2].McLowLatencyConfig = 0x80000003; 313 | SDRAM[2].EmcCfg = 0x0301ff00; 314 | SDRAM[2].EmcCfg2 = 0x00000405; 315 | SDRAM[2].EmcDbg = 0x01000400; 316 | SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000; 317 | SDRAM[2].EmcCfgDigDll = 0xf0000313; 318 | SDRAM[2].EmcDllXformDqs = 0x00000010; 319 | SDRAM[2].EmcDllXformQUse = 0x00000008; 320 | SDRAM[2].WarmBootWait = 0x00000002; 321 | SDRAM[2].EmcCttTermCtrl = 0x00000802; 322 | SDRAM[2].EmcOdtWrite = 0x80000001; 323 | SDRAM[2].EmcOdtRead = 0x80000001; 324 | SDRAM[2].EmcZcalRefCnt = 0x00000000; 325 | SDRAM[2].EmcZcalWaitCnt = 0x00000000; 326 | SDRAM[2].EmcZcalMrwCmd = 0x00000000; 327 | SDRAM[2].EmcMrsResetDll = 0x00000000; 328 | SDRAM[2].EmcMrwZqInitDev0 = 0x00000000; 329 | SDRAM[2].EmcMrwZqInitDev1 = 0x00000000; 330 | SDRAM[2].EmcMrwZqInitWait = 0x00000000; 331 | SDRAM[2].EmcMrsResetDllWait = 0x00000000; 332 | SDRAM[2].EmcEmrsEmr2 = 0x00200000; 333 | SDRAM[2].EmcEmrsEmr3 = 0x00300000; 334 | SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000; 335 | SDRAM[2].EmcMrsDdr2DllReset = 0x00000100; 336 | SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100386; 337 | SDRAM[2].EmcDdr2Wait = 0x00000002; 338 | SDRAM[2].EmcCfgClktrim0 = 0x00000000; 339 | SDRAM[2].EmcCfgClktrim1 = 0x00000000; 340 | SDRAM[2].EmcCfgClktrim2 = 0x00000000; 341 | SDRAM[2].PmcDdrPwr = 0x00000001; 342 | SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 343 | SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 344 | SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 345 | SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 346 | SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 347 | SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 348 | SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 349 | SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 350 | 351 | SDRAM[3].MemoryType = NvBootMemoryType_Ddr2; 352 | SDRAM[3].PllMChargePumpSetupControl = 0x00000008; 353 | SDRAM[3].PllMLoopFilterSetupControl = 0x00000000; 354 | SDRAM[3].PllMInputDivider = 0x0000000d; 355 | SDRAM[3].PllMFeedbackDivider = 0x0000029a; 356 | SDRAM[3].PllMPostDivider = 0x00000000; 357 | SDRAM[3].PllMStableTime = 0x0000012c; 358 | SDRAM[3].EmcClockDivider = 0x00000001; 359 | SDRAM[3].EmcAutoCalInterval = 0x00000000; 360 | SDRAM[3].EmcAutoCalConfig = 0xe0a61111; 361 | SDRAM[3].EmcAutoCalWait = 0x00000000; 362 | SDRAM[3].EmcPinProgramWait = 0x00000000; 363 | SDRAM[3].EmcRc = 0x00000014; 364 | SDRAM[3].EmcRfc = 0x0000002b; 365 | SDRAM[3].EmcRas = 0x0000000f; 366 | SDRAM[3].EmcRp = 0x00000005; 367 | SDRAM[3].EmcR2w = 0x00000005; 368 | SDRAM[3].EmcW2r = 0x00000005; 369 | SDRAM[3].EmcR2p = 0x00000003; 370 | SDRAM[3].EmcW2p = 0x0000000c; 371 | SDRAM[3].EmcRdRcd = 0x00000005; 372 | SDRAM[3].EmcWrRcd = 0x00000005; 373 | SDRAM[3].EmcRrd = 0x00000003; 374 | SDRAM[3].EmcRext = 0x00000001; 375 | SDRAM[3].EmcWdv = 0x00000004; 376 | SDRAM[3].EmcQUse = 0x00000005; 377 | SDRAM[3].EmcQRst = 0x00000004; 378 | SDRAM[3].EmcQSafe = 0x00000009; 379 | SDRAM[3].EmcRdv = 0x0000000d; 380 | SDRAM[3].EmcRefresh = 0x000009ff; 381 | SDRAM[3].EmcBurstRefreshNum = 0x00000000; 382 | SDRAM[3].EmcPdEx2Wr = 0x00000003; 383 | SDRAM[3].EmcPdEx2Rd = 0x00000003; 384 | SDRAM[3].EmcPChg2Pden = 0x00000005; 385 | SDRAM[3].EmcAct2Pden = 0x00000005; 386 | SDRAM[3].EmcAr2Pden = 0x00000001; 387 | SDRAM[3].EmcRw2Pden = 0x0000000f; 388 | SDRAM[3].EmcTxsr = 0x000000c8; 389 | SDRAM[3].EmcTcke = 0x00000003; 390 | SDRAM[3].EmcTfaw = 0x0000000c; 391 | SDRAM[3].EmcTrpab = 0x00000006; 392 | SDRAM[3].EmcTClkStable = 0x00000008; 393 | SDRAM[3].EmcTClkStop = 0x00000002; 394 | SDRAM[3].EmcTRefBw = 0x00000000; 395 | SDRAM[3].EmcQUseExtra = 0x00000000; 396 | SDRAM[3].EmcFbioCfg1 = 0x00000000; 397 | SDRAM[3].EmcFbioDqsibDly = 0x20202020; 398 | SDRAM[3].EmcFbioDqsibDlyMsb = 0x00000000; 399 | SDRAM[3].EmcFbioQuseDly = 0x50465046; 400 | SDRAM[3].EmcFbioQuseDlyMsb = 0x00000000; 401 | SDRAM[3].EmcFbioCfg5 = 0x00000183; 402 | SDRAM[3].EmcFbioCfg6 = 0x00000002; 403 | SDRAM[3].EmcFbioSpare = 0x00000000; 404 | SDRAM[3].EmcMrs = 0x00000a6a; 405 | SDRAM[3].EmcEmrs = 0x00100006; 406 | SDRAM[3].EmcMrw1 = 0x00000000; 407 | SDRAM[3].EmcMrw2 = 0x00000000; 408 | SDRAM[3].EmcMrw3 = 0x00000000; 409 | SDRAM[3].EmcMrwResetCommand = 0x00000000; 410 | SDRAM[3].EmcMrwResetNInitWait = 0x00000000; 411 | SDRAM[3].EmcAdrCfg = 0x00060303; 412 | SDRAM[3].EmcAdrCfg1 = 0x00060303; 413 | SDRAM[3].McEmemCfg = 0x00040000; 414 | SDRAM[3].McLowLatencyConfig = 0x80000003; 415 | SDRAM[3].EmcCfg = 0x0301ff00; 416 | SDRAM[3].EmcCfg2 = 0x00000405; 417 | SDRAM[3].EmcDbg = 0x01000400; 418 | SDRAM[3].AhbArbitrationXbarCtrl = 0x00010000; 419 | SDRAM[3].EmcCfgDigDll = 0xf0000313; 420 | SDRAM[3].EmcDllXformDqs = 0x00000010; 421 | SDRAM[3].EmcDllXformQUse = 0x00000008; 422 | SDRAM[3].WarmBootWait = 0x00000002; 423 | SDRAM[3].EmcCttTermCtrl = 0x00000802; 424 | SDRAM[3].EmcOdtWrite = 0x80000001; 425 | SDRAM[3].EmcOdtRead = 0x80000001; 426 | SDRAM[3].EmcZcalRefCnt = 0x00000000; 427 | SDRAM[3].EmcZcalWaitCnt = 0x00000000; 428 | SDRAM[3].EmcZcalMrwCmd = 0x00000000; 429 | SDRAM[3].EmcMrsResetDll = 0x00000000; 430 | SDRAM[3].EmcMrwZqInitDev0 = 0x00000000; 431 | SDRAM[3].EmcMrwZqInitDev1 = 0x00000000; 432 | SDRAM[3].EmcMrwZqInitWait = 0x00000000; 433 | SDRAM[3].EmcMrsResetDllWait = 0x00000000; 434 | SDRAM[3].EmcEmrsEmr2 = 0x00200000; 435 | SDRAM[3].EmcEmrsEmr3 = 0x00300000; 436 | SDRAM[3].EmcEmrsDdr2DllEnable = 0x00100000; 437 | SDRAM[3].EmcMrsDdr2DllReset = 0x00000100; 438 | SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00100386; 439 | SDRAM[3].EmcDdr2Wait = 0x00000002; 440 | SDRAM[3].EmcCfgClktrim0 = 0x00000000; 441 | SDRAM[3].EmcCfgClktrim1 = 0x00000000; 442 | SDRAM[3].EmcCfgClktrim2 = 0x00000000; 443 | SDRAM[3].PmcDdrPwr = 0x00000001; 444 | SDRAM[3].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 445 | SDRAM[3].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 446 | SDRAM[3].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 447 | SDRAM[3].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 448 | SDRAM[3].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 449 | SDRAM[3].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 450 | SDRAM[3].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 451 | SDRAM[3].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 452 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/colibri_t20-512-hsmmc.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Toradex AG. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | PartitionSize = 16777216; 21 | BlockSize = 16384; 22 | PageSize = 512; 23 | OdmData = 0x200C0000; 24 | 25 | DevType[0] = Sdmmc; 26 | DeviceParam[0].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz. 27 | DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 28 | DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0; 29 | 30 | DevType[1] = Sdmmc; 31 | DeviceParam[1].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz. 32 | DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 33 | DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0; 34 | 35 | DevType[2] = Sdmmc; 36 | DeviceParam[2].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz. 37 | DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 38 | DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0; 39 | 40 | DevType[3] = Sdmmc; 41 | DeviceParam[3].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz. 42 | DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit; 43 | DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0; 44 | 45 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr2; 46 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 47 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 48 | SDRAM[0].PllMInputDivider = 0x0000000d; 49 | SDRAM[0].PllMFeedbackDivider = 0x0000029a; 50 | SDRAM[0].PllMPostDivider = 0x00000000; 51 | SDRAM[0].PllMStableTime = 0x0000012c; 52 | SDRAM[0].EmcClockDivider = 0x00000001; 53 | SDRAM[0].EmcAutoCalInterval = 0x00000000; 54 | SDRAM[0].EmcAutoCalConfig = 0xe0a61111; 55 | SDRAM[0].EmcAutoCalWait = 0x00000000; 56 | SDRAM[0].EmcPinProgramWait = 0x00000000; 57 | SDRAM[0].EmcRc = 0x00000014; 58 | SDRAM[0].EmcRfc = 0x00000041; 59 | SDRAM[0].EmcRas = 0x0000000f; 60 | SDRAM[0].EmcRp = 0x00000005; 61 | SDRAM[0].EmcR2w = 0x00000004; 62 | SDRAM[0].EmcW2r = 0x00000005; 63 | SDRAM[0].EmcR2p = 0x00000003; 64 | SDRAM[0].EmcW2p = 0x0000000a; 65 | SDRAM[0].EmcRdRcd = 0x00000005; 66 | SDRAM[0].EmcWrRcd = 0x00000005; 67 | SDRAM[0].EmcRrd = 0x00000004; 68 | SDRAM[0].EmcRext = 0x00000001; 69 | SDRAM[0].EmcWdv = 0x00000003; 70 | SDRAM[0].EmcQUse = 0x00000004; 71 | SDRAM[0].EmcQRst = 0x00000003; 72 | SDRAM[0].EmcQSafe = 0x00000009; 73 | SDRAM[0].EmcRdv = 0x0000000c; 74 | SDRAM[0].EmcRefresh = 0x000009ff; 75 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 76 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 77 | SDRAM[0].EmcPdEx2Rd = 0x00000003; 78 | SDRAM[0].EmcPChg2Pden = 0x00000005; 79 | SDRAM[0].EmcAct2Pden = 0x00000005; 80 | SDRAM[0].EmcAr2Pden = 0x00000001; 81 | SDRAM[0].EmcRw2Pden = 0x0000000e; 82 | SDRAM[0].EmcTxsr = 0x000000c8; 83 | SDRAM[0].EmcTcke = 0x00000003; 84 | SDRAM[0].EmcTfaw = 0x00000011; 85 | SDRAM[0].EmcTrpab = 0x00000006; 86 | SDRAM[0].EmcTClkStable = 0x0000000c; 87 | SDRAM[0].EmcTClkStop = 0x00000002; 88 | SDRAM[0].EmcTRefBw = 0x00000000; 89 | SDRAM[0].EmcQUseExtra = 0x00000000; 90 | SDRAM[0].EmcFbioCfg1 = 0x00000000; 91 | SDRAM[0].EmcFbioDqsibDly = 0x1c1c1c1c; 92 | SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000; 93 | SDRAM[0].EmcFbioQuseDly = 0x74747474; 94 | SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000; 95 | SDRAM[0].EmcFbioCfg5 = 0x00000083; 96 | SDRAM[0].EmcFbioCfg6 = 0x00000002; 97 | SDRAM[0].EmcFbioSpare = 0x00000000; 98 | SDRAM[0].EmcMrs = 0x0000085a; 99 | SDRAM[0].EmcEmrs = 0x00100002; 100 | SDRAM[0].EmcMrw1 = 0x00000000; 101 | SDRAM[0].EmcMrw2 = 0x00000000; 102 | SDRAM[0].EmcMrw3 = 0x00000000; 103 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 104 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 105 | SDRAM[0].EmcAdrCfg = 0x00070303; 106 | SDRAM[0].EmcAdrCfg1 = 0x00070303; 107 | SDRAM[0].McEmemCfg = 0x00080000; 108 | SDRAM[0].McLowLatencyConfig = 0x80000003; 109 | SDRAM[0].EmcCfg = 0x0301ff00; 110 | SDRAM[0].EmcCfg2 = 0x00000405; 111 | SDRAM[0].EmcDbg = 0x01000400; 112 | SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000; 113 | SDRAM[0].EmcCfgDigDll = 0xf0000313; 114 | SDRAM[0].EmcDllXformDqs = 0x00000010; 115 | SDRAM[0].EmcDllXformQUse = 0x00000008; 116 | SDRAM[0].WarmBootWait = 0x00000002; 117 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 118 | SDRAM[0].EmcOdtWrite = 0x00000000; 119 | SDRAM[0].EmcOdtRead = 0x00000000; 120 | SDRAM[0].EmcZcalRefCnt = 0x00000000; 121 | SDRAM[0].EmcZcalWaitCnt = 0x00000000; 122 | SDRAM[0].EmcZcalMrwCmd = 0x00000000; 123 | SDRAM[0].EmcMrsResetDll = 0x00000000; 124 | SDRAM[0].EmcMrwZqInitDev0 = 0x00000000; 125 | SDRAM[0].EmcMrwZqInitDev1 = 0x00000000; 126 | SDRAM[0].EmcMrwZqInitWait = 0x00000000; 127 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 128 | SDRAM[0].EmcEmrsEmr2 = 0x00200000; 129 | SDRAM[0].EmcEmrsEmr3 = 0x00300000; 130 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000; 131 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000100; 132 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100386; 133 | SDRAM[0].EmcDdr2Wait = 0x00000002; 134 | SDRAM[0].EmcCfgClktrim0 = 0x00000000; 135 | SDRAM[0].EmcCfgClktrim1 = 0x00000000; 136 | SDRAM[0].EmcCfgClktrim2 = 0x00000000; 137 | SDRAM[0].PmcDdrPwr = 0x00000001; 138 | SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 139 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 140 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 141 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 142 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 143 | SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 144 | SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 145 | SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 146 | 147 | SDRAM[1].MemoryType = NvBootMemoryType_Ddr2; 148 | SDRAM[1].PllMChargePumpSetupControl = 0x00000008; 149 | SDRAM[1].PllMLoopFilterSetupControl = 0x00000000; 150 | SDRAM[1].PllMInputDivider = 0x0000000d; 151 | SDRAM[1].PllMFeedbackDivider = 0x0000029a; 152 | SDRAM[1].PllMPostDivider = 0x00000000; 153 | SDRAM[1].PllMStableTime = 0x0000012c; 154 | SDRAM[1].EmcClockDivider = 0x00000001; 155 | SDRAM[1].EmcAutoCalInterval = 0x00000000; 156 | SDRAM[1].EmcAutoCalConfig = 0xe0a61111; 157 | SDRAM[1].EmcAutoCalWait = 0x00000000; 158 | SDRAM[1].EmcPinProgramWait = 0x00000000; 159 | SDRAM[1].EmcRc = 0x00000014; 160 | SDRAM[1].EmcRfc = 0x00000041; 161 | SDRAM[1].EmcRas = 0x0000000f; 162 | SDRAM[1].EmcRp = 0x00000005; 163 | SDRAM[1].EmcR2w = 0x00000004; 164 | SDRAM[1].EmcW2r = 0x00000005; 165 | SDRAM[1].EmcR2p = 0x00000003; 166 | SDRAM[1].EmcW2p = 0x0000000a; 167 | SDRAM[1].EmcRdRcd = 0x00000005; 168 | SDRAM[1].EmcWrRcd = 0x00000005; 169 | SDRAM[1].EmcRrd = 0x00000004; 170 | SDRAM[1].EmcRext = 0x00000001; 171 | SDRAM[1].EmcWdv = 0x00000003; 172 | SDRAM[1].EmcQUse = 0x00000004; 173 | SDRAM[1].EmcQRst = 0x00000003; 174 | SDRAM[1].EmcQSafe = 0x00000009; 175 | SDRAM[1].EmcRdv = 0x0000000c; 176 | SDRAM[1].EmcRefresh = 0x000009ff; 177 | SDRAM[1].EmcBurstRefreshNum = 0x00000000; 178 | SDRAM[1].EmcPdEx2Wr = 0x00000003; 179 | SDRAM[1].EmcPdEx2Rd = 0x00000003; 180 | SDRAM[1].EmcPChg2Pden = 0x00000005; 181 | SDRAM[1].EmcAct2Pden = 0x00000005; 182 | SDRAM[1].EmcAr2Pden = 0x00000001; 183 | SDRAM[1].EmcRw2Pden = 0x0000000e; 184 | SDRAM[1].EmcTxsr = 0x000000c8; 185 | SDRAM[1].EmcTcke = 0x00000003; 186 | SDRAM[1].EmcTfaw = 0x00000011; 187 | SDRAM[1].EmcTrpab = 0x00000006; 188 | SDRAM[1].EmcTClkStable = 0x0000000c; 189 | SDRAM[1].EmcTClkStop = 0x00000002; 190 | SDRAM[1].EmcTRefBw = 0x00000000; 191 | SDRAM[1].EmcQUseExtra = 0x00000000; 192 | SDRAM[1].EmcFbioCfg1 = 0x00000000; 193 | SDRAM[1].EmcFbioDqsibDly = 0x1c1c1c1c; 194 | SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000; 195 | SDRAM[1].EmcFbioQuseDly = 0x74747474; 196 | SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000; 197 | SDRAM[1].EmcFbioCfg5 = 0x00000083; 198 | SDRAM[1].EmcFbioCfg6 = 0x00000002; 199 | SDRAM[1].EmcFbioSpare = 0x00000000; 200 | SDRAM[1].EmcMrs = 0x0000085a; 201 | SDRAM[1].EmcEmrs = 0x00100002; 202 | SDRAM[1].EmcMrw1 = 0x00000000; 203 | SDRAM[1].EmcMrw2 = 0x00000000; 204 | SDRAM[1].EmcMrw3 = 0x00000000; 205 | SDRAM[1].EmcMrwResetCommand = 0x00000000; 206 | SDRAM[1].EmcMrwResetNInitWait = 0x00000000; 207 | SDRAM[1].EmcAdrCfg = 0x00070303; 208 | SDRAM[1].EmcAdrCfg1 = 0x00070303; 209 | SDRAM[1].McEmemCfg = 0x00080000; 210 | SDRAM[1].McLowLatencyConfig = 0x80000003; 211 | SDRAM[1].EmcCfg = 0x0301ff00; 212 | SDRAM[1].EmcCfg2 = 0x00000405; 213 | SDRAM[1].EmcDbg = 0x01000400; 214 | SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000; 215 | SDRAM[1].EmcCfgDigDll = 0xf0000313; 216 | SDRAM[1].EmcDllXformDqs = 0x00000010; 217 | SDRAM[1].EmcDllXformQUse = 0x00000008; 218 | SDRAM[1].WarmBootWait = 0x00000002; 219 | SDRAM[1].EmcCttTermCtrl = 0x00000802; 220 | SDRAM[1].EmcOdtWrite = 0x00000000; 221 | SDRAM[1].EmcOdtRead = 0x00000000; 222 | SDRAM[1].EmcZcalRefCnt = 0x00000000; 223 | SDRAM[1].EmcZcalWaitCnt = 0x00000000; 224 | SDRAM[1].EmcZcalMrwCmd = 0x00000000; 225 | SDRAM[1].EmcMrsResetDll = 0x00000000; 226 | SDRAM[1].EmcMrwZqInitDev0 = 0x00000000; 227 | SDRAM[1].EmcMrwZqInitDev1 = 0x00000000; 228 | SDRAM[1].EmcMrwZqInitWait = 0x00000000; 229 | SDRAM[1].EmcMrsResetDllWait = 0x00000000; 230 | SDRAM[1].EmcEmrsEmr2 = 0x00200000; 231 | SDRAM[1].EmcEmrsEmr3 = 0x00300000; 232 | SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000; 233 | SDRAM[1].EmcMrsDdr2DllReset = 0x00000100; 234 | SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100386; 235 | SDRAM[1].EmcDdr2Wait = 0x00000002; 236 | SDRAM[1].EmcCfgClktrim0 = 0x00000000; 237 | SDRAM[1].EmcCfgClktrim1 = 0x00000000; 238 | SDRAM[1].EmcCfgClktrim2 = 0x00000000; 239 | SDRAM[1].PmcDdrPwr = 0x00000001; 240 | SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 241 | SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 242 | SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 243 | SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 244 | SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 245 | SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 246 | SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 247 | SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 248 | 249 | SDRAM[2].MemoryType = NvBootMemoryType_Ddr2; 250 | SDRAM[2].PllMChargePumpSetupControl = 0x00000008; 251 | SDRAM[2].PllMLoopFilterSetupControl = 0x00000000; 252 | SDRAM[2].PllMInputDivider = 0x0000000d; 253 | SDRAM[2].PllMFeedbackDivider = 0x0000029a; 254 | SDRAM[2].PllMPostDivider = 0x00000000; 255 | SDRAM[2].PllMStableTime = 0x0000012c; 256 | SDRAM[2].EmcClockDivider = 0x00000001; 257 | SDRAM[2].EmcAutoCalInterval = 0x00000000; 258 | SDRAM[2].EmcAutoCalConfig = 0xe0a61111; 259 | SDRAM[2].EmcAutoCalWait = 0x00000000; 260 | SDRAM[2].EmcPinProgramWait = 0x00000000; 261 | SDRAM[2].EmcRc = 0x00000014; 262 | SDRAM[2].EmcRfc = 0x00000041; 263 | SDRAM[2].EmcRas = 0x0000000f; 264 | SDRAM[2].EmcRp = 0x00000005; 265 | SDRAM[2].EmcR2w = 0x00000004; 266 | SDRAM[2].EmcW2r = 0x00000005; 267 | SDRAM[2].EmcR2p = 0x00000003; 268 | SDRAM[2].EmcW2p = 0x0000000a; 269 | SDRAM[2].EmcRdRcd = 0x00000005; 270 | SDRAM[2].EmcWrRcd = 0x00000005; 271 | SDRAM[2].EmcRrd = 0x00000004; 272 | SDRAM[2].EmcRext = 0x00000001; 273 | SDRAM[2].EmcWdv = 0x00000003; 274 | SDRAM[2].EmcQUse = 0x00000004; 275 | SDRAM[2].EmcQRst = 0x00000003; 276 | SDRAM[2].EmcQSafe = 0x00000009; 277 | SDRAM[2].EmcRdv = 0x0000000c; 278 | SDRAM[2].EmcRefresh = 0x000009ff; 279 | SDRAM[2].EmcBurstRefreshNum = 0x00000000; 280 | SDRAM[2].EmcPdEx2Wr = 0x00000003; 281 | SDRAM[2].EmcPdEx2Rd = 0x00000003; 282 | SDRAM[2].EmcPChg2Pden = 0x00000005; 283 | SDRAM[2].EmcAct2Pden = 0x00000005; 284 | SDRAM[2].EmcAr2Pden = 0x00000001; 285 | SDRAM[2].EmcRw2Pden = 0x0000000e; 286 | SDRAM[2].EmcTxsr = 0x000000c8; 287 | SDRAM[2].EmcTcke = 0x00000003; 288 | SDRAM[2].EmcTfaw = 0x00000011; 289 | SDRAM[2].EmcTrpab = 0x00000006; 290 | SDRAM[2].EmcTClkStable = 0x0000000c; 291 | SDRAM[2].EmcTClkStop = 0x00000002; 292 | SDRAM[2].EmcTRefBw = 0x00000000; 293 | SDRAM[2].EmcQUseExtra = 0x00000000; 294 | SDRAM[2].EmcFbioCfg1 = 0x00000000; 295 | SDRAM[2].EmcFbioDqsibDly = 0x1c1c1c1c; 296 | SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000; 297 | SDRAM[2].EmcFbioQuseDly = 0x74747474; 298 | SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000; 299 | SDRAM[2].EmcFbioCfg5 = 0x00000083; 300 | SDRAM[2].EmcFbioCfg6 = 0x00000002; 301 | SDRAM[2].EmcFbioSpare = 0x00000000; 302 | SDRAM[2].EmcMrs = 0x0000085a; 303 | SDRAM[2].EmcEmrs = 0x00100002; 304 | SDRAM[2].EmcMrw1 = 0x00000000; 305 | SDRAM[2].EmcMrw2 = 0x00000000; 306 | SDRAM[2].EmcMrw3 = 0x00000000; 307 | SDRAM[2].EmcMrwResetCommand = 0x00000000; 308 | SDRAM[2].EmcMrwResetNInitWait = 0x00000000; 309 | SDRAM[2].EmcAdrCfg = 0x00070303; 310 | SDRAM[2].EmcAdrCfg1 = 0x00070303; 311 | SDRAM[2].McEmemCfg = 0x00080000; 312 | SDRAM[2].McLowLatencyConfig = 0x80000003; 313 | SDRAM[2].EmcCfg = 0x0301ff00; 314 | SDRAM[2].EmcCfg2 = 0x00000405; 315 | SDRAM[2].EmcDbg = 0x01000400; 316 | SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000; 317 | SDRAM[2].EmcCfgDigDll = 0xf0000313; 318 | SDRAM[2].EmcDllXformDqs = 0x00000010; 319 | SDRAM[2].EmcDllXformQUse = 0x00000008; 320 | SDRAM[2].WarmBootWait = 0x00000002; 321 | SDRAM[2].EmcCttTermCtrl = 0x00000802; 322 | SDRAM[2].EmcOdtWrite = 0x00000000; 323 | SDRAM[2].EmcOdtRead = 0x00000000; 324 | SDRAM[2].EmcZcalRefCnt = 0x00000000; 325 | SDRAM[2].EmcZcalWaitCnt = 0x00000000; 326 | SDRAM[2].EmcZcalMrwCmd = 0x00000000; 327 | SDRAM[2].EmcMrsResetDll = 0x00000000; 328 | SDRAM[2].EmcMrwZqInitDev0 = 0x00000000; 329 | SDRAM[2].EmcMrwZqInitDev1 = 0x00000000; 330 | SDRAM[2].EmcMrwZqInitWait = 0x00000000; 331 | SDRAM[2].EmcMrsResetDllWait = 0x00000000; 332 | SDRAM[2].EmcEmrsEmr2 = 0x00200000; 333 | SDRAM[2].EmcEmrsEmr3 = 0x00300000; 334 | SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000; 335 | SDRAM[2].EmcMrsDdr2DllReset = 0x00000100; 336 | SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100386; 337 | SDRAM[2].EmcDdr2Wait = 0x00000002; 338 | SDRAM[2].EmcCfgClktrim0 = 0x00000000; 339 | SDRAM[2].EmcCfgClktrim1 = 0x00000000; 340 | SDRAM[2].EmcCfgClktrim2 = 0x00000000; 341 | SDRAM[2].PmcDdrPwr = 0x00000001; 342 | SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 343 | SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 344 | SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 345 | SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 346 | SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 347 | SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 348 | SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 349 | SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 350 | 351 | SDRAM[3].MemoryType = NvBootMemoryType_Ddr2; 352 | SDRAM[3].PllMChargePumpSetupControl = 0x00000008; 353 | SDRAM[3].PllMLoopFilterSetupControl = 0x00000000; 354 | SDRAM[3].PllMInputDivider = 0x0000000d; 355 | SDRAM[3].PllMFeedbackDivider = 0x0000029a; 356 | SDRAM[3].PllMPostDivider = 0x00000000; 357 | SDRAM[3].PllMStableTime = 0x0000012c; 358 | SDRAM[3].EmcClockDivider = 0x00000001; 359 | SDRAM[3].EmcAutoCalInterval = 0x00000000; 360 | SDRAM[3].EmcAutoCalConfig = 0xe0a61111; 361 | SDRAM[3].EmcAutoCalWait = 0x00000000; 362 | SDRAM[3].EmcPinProgramWait = 0x00000000; 363 | SDRAM[3].EmcRc = 0x00000014; 364 | SDRAM[3].EmcRfc = 0x00000041; 365 | SDRAM[3].EmcRas = 0x0000000f; 366 | SDRAM[3].EmcRp = 0x00000005; 367 | SDRAM[3].EmcR2w = 0x00000004; 368 | SDRAM[3].EmcW2r = 0x00000005; 369 | SDRAM[3].EmcR2p = 0x00000003; 370 | SDRAM[3].EmcW2p = 0x0000000a; 371 | SDRAM[3].EmcRdRcd = 0x00000005; 372 | SDRAM[3].EmcWrRcd = 0x00000005; 373 | SDRAM[3].EmcRrd = 0x00000004; 374 | SDRAM[3].EmcRext = 0x00000001; 375 | SDRAM[3].EmcWdv = 0x00000003; 376 | SDRAM[3].EmcQUse = 0x00000004; 377 | SDRAM[3].EmcQRst = 0x00000003; 378 | SDRAM[3].EmcQSafe = 0x00000009; 379 | SDRAM[3].EmcRdv = 0x0000000c; 380 | SDRAM[3].EmcRefresh = 0x000009ff; 381 | SDRAM[3].EmcBurstRefreshNum = 0x00000000; 382 | SDRAM[3].EmcPdEx2Wr = 0x00000003; 383 | SDRAM[3].EmcPdEx2Rd = 0x00000003; 384 | SDRAM[3].EmcPChg2Pden = 0x00000005; 385 | SDRAM[3].EmcAct2Pden = 0x00000005; 386 | SDRAM[3].EmcAr2Pden = 0x00000001; 387 | SDRAM[3].EmcRw2Pden = 0x0000000e; 388 | SDRAM[3].EmcTxsr = 0x000000c8; 389 | SDRAM[3].EmcTcke = 0x00000003; 390 | SDRAM[3].EmcTfaw = 0x00000011; 391 | SDRAM[3].EmcTrpab = 0x00000006; 392 | SDRAM[3].EmcTClkStable = 0x0000000c; 393 | SDRAM[3].EmcTClkStop = 0x00000002; 394 | SDRAM[3].EmcTRefBw = 0x00000000; 395 | SDRAM[3].EmcQUseExtra = 0x00000000; 396 | SDRAM[3].EmcFbioCfg1 = 0x00000000; 397 | SDRAM[3].EmcFbioDqsibDly = 0x1c1c1c1c; 398 | SDRAM[3].EmcFbioDqsibDlyMsb = 0x00000000; 399 | SDRAM[3].EmcFbioQuseDly = 0x74747474; 400 | SDRAM[3].EmcFbioQuseDlyMsb = 0x00000000; 401 | SDRAM[3].EmcFbioCfg5 = 0x00000083; 402 | SDRAM[3].EmcFbioCfg6 = 0x00000002; 403 | SDRAM[3].EmcFbioSpare = 0x00000000; 404 | SDRAM[3].EmcMrs = 0x0000085a; 405 | SDRAM[3].EmcEmrs = 0x00100002; 406 | SDRAM[3].EmcMrw1 = 0x00000000; 407 | SDRAM[3].EmcMrw2 = 0x00000000; 408 | SDRAM[3].EmcMrw3 = 0x00000000; 409 | SDRAM[3].EmcMrwResetCommand = 0x00000000; 410 | SDRAM[3].EmcMrwResetNInitWait = 0x00000000; 411 | SDRAM[3].EmcAdrCfg = 0x00070303; 412 | SDRAM[3].EmcAdrCfg1 = 0x00070303; 413 | SDRAM[3].McEmemCfg = 0x00080000; 414 | SDRAM[3].McLowLatencyConfig = 0x80000003; 415 | SDRAM[3].EmcCfg = 0x0301ff00; 416 | SDRAM[3].EmcCfg2 = 0x00000405; 417 | SDRAM[3].EmcDbg = 0x01000400; 418 | SDRAM[3].AhbArbitrationXbarCtrl = 0x00010000; 419 | SDRAM[3].EmcCfgDigDll = 0xf0000313; 420 | SDRAM[3].EmcDllXformDqs = 0x00000010; 421 | SDRAM[3].EmcDllXformQUse = 0x00000008; 422 | SDRAM[3].WarmBootWait = 0x00000002; 423 | SDRAM[3].EmcCttTermCtrl = 0x00000802; 424 | SDRAM[3].EmcOdtWrite = 0x00000000; 425 | SDRAM[3].EmcOdtRead = 0x00000000; 426 | SDRAM[3].EmcZcalRefCnt = 0x00000000; 427 | SDRAM[3].EmcZcalWaitCnt = 0x00000000; 428 | SDRAM[3].EmcZcalMrwCmd = 0x00000000; 429 | SDRAM[3].EmcMrsResetDll = 0x00000000; 430 | SDRAM[3].EmcMrwZqInitDev0 = 0x00000000; 431 | SDRAM[3].EmcMrwZqInitDev1 = 0x00000000; 432 | SDRAM[3].EmcMrwZqInitWait = 0x00000000; 433 | SDRAM[3].EmcMrsResetDllWait = 0x00000000; 434 | SDRAM[3].EmcEmrsEmr2 = 0x00200000; 435 | SDRAM[3].EmcEmrsEmr3 = 0x00300000; 436 | SDRAM[3].EmcEmrsDdr2DllEnable = 0x00100000; 437 | SDRAM[3].EmcMrsDdr2DllReset = 0x00000100; 438 | SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00100386; 439 | SDRAM[3].EmcDdr2Wait = 0x00000002; 440 | SDRAM[3].EmcCfgClktrim0 = 0x00000000; 441 | SDRAM[3].EmcCfgClktrim1 = 0x00000000; 442 | SDRAM[3].EmcCfgClktrim2 = 0x00000000; 443 | SDRAM[3].PmcDdrPwr = 0x00000001; 444 | SDRAM[3].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 445 | SDRAM[3].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 446 | SDRAM[3].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 447 | SDRAM[3].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 448 | SDRAM[3].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 449 | SDRAM[3].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 450 | SDRAM[3].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 451 | SDRAM[3].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 452 | -------------------------------------------------------------------------------- /tegra20/toradex/colibri_t20/colibri_t20-256-v11-nand.bct.cfg: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2013, Toradex AG. All rights reserved. 2 | # 3 | # This software is provided 'as-is', without any express or implied 4 | # warranty. In no event will the authors be held liable for any damages 5 | # arising from the use of this software. 6 | # 7 | # Permission is granted to anyone to use this software for any purpose, 8 | # including commercial applications, and to alter it and redistribute it 9 | # freely, subject to the following restrictions: 10 | # 11 | # 1. The origin of this software must not be misrepresented; you must not 12 | # claim that you wrote the original software. If you use this software 13 | # in a product, an acknowledgment in the product documentation would be 14 | # appreciated but is not required. 15 | # 2. Altered source versions must be plainly marked as such, and must not be 16 | # misrepresented as being the original software. 17 | # 3. This notice may not be removed or altered from any source distribution. 18 | 19 | Version = 0x00020001; 20 | PartitionSize = 8388608; 21 | BlockSize = 524288; 22 | PageSize = 4096; 23 | OdmData = 0x100C0000; 24 | 25 | DevType[0] = Nand; 26 | DeviceParam[0].NandParams.ClockDivider = 0x4; # Clock source of 108MHz 27 | DeviceParam[0].NandParams.NandTiming2 = 0xA; # For 108MHz clock 28 | DeviceParam[0].NandParams.NandTiming = 0x3B269213; # For 108MHz clock 29 | DeviceParam[0].NandParams.BlockSizeLog2 = 0; 30 | DeviceParam[0].NandParams.PageSizeLog2 = 0; 31 | 32 | DevType[1] = Nand; 33 | DeviceParam[1].NandParams.ClockDivider = 0x4; # Clock source of 108MHz 34 | DeviceParam[1].NandParams.NandTiming2 = 0xA; # For 108MHz clock 35 | DeviceParam[1].NandParams.NandTiming = 0x3B269213; # For 108MHz clock 36 | DeviceParam[1].NandParams.BlockSizeLog2 = 0; 37 | DeviceParam[1].NandParams.PageSizeLog2 = 0; 38 | 39 | DevType[2] = Nand; 40 | DeviceParam[2].NandParams.ClockDivider = 0x4; # Clock source of 108MHz 41 | DeviceParam[2].NandParams.NandTiming2 = 0xA; # For 108MHz clock 42 | DeviceParam[2].NandParams.NandTiming = 0x3B269213; # For 108MHz clock 43 | DeviceParam[2].NandParams.BlockSizeLog2 = 0; 44 | DeviceParam[2].NandParams.PageSizeLog2 = 0; 45 | 46 | DevType[3] = Nand; 47 | DeviceParam[3].NandParams.ClockDivider = 0x4; # Clock source of 108MHz 48 | DeviceParam[3].NandParams.NandTiming2 = 0xA; # For 108MHz clock 49 | DeviceParam[3].NandParams.NandTiming = 0x3B269213; # For 108MHz clock 50 | DeviceParam[3].NandParams.BlockSizeLog2 = 0; 51 | DeviceParam[3].NandParams.PageSizeLog2 = 0; 52 | 53 | SDRAM[0].MemoryType = NvBootMemoryType_Ddr2; 54 | SDRAM[0].PllMChargePumpSetupControl = 0x00000008; 55 | SDRAM[0].PllMLoopFilterSetupControl = 0x00000000; 56 | SDRAM[0].PllMInputDivider = 0x0000000d; 57 | SDRAM[0].PllMFeedbackDivider = 0x0000029a; 58 | SDRAM[0].PllMPostDivider = 0x00000000; 59 | SDRAM[0].PllMStableTime = 0x0000012c; 60 | SDRAM[0].EmcClockDivider = 0x00000001; 61 | SDRAM[0].EmcAutoCalInterval = 0x00000000; 62 | SDRAM[0].EmcAutoCalConfig = 0xe0a61111; 63 | SDRAM[0].EmcAutoCalWait = 0x00000000; 64 | SDRAM[0].EmcPinProgramWait = 0x00000000; 65 | SDRAM[0].EmcRc = 0x00000014; 66 | SDRAM[0].EmcRfc = 0x0000002b; 67 | SDRAM[0].EmcRas = 0x0000000f; 68 | SDRAM[0].EmcRp = 0x00000005; 69 | SDRAM[0].EmcR2w = 0x00000004; 70 | SDRAM[0].EmcW2r = 0x00000005; 71 | SDRAM[0].EmcR2p = 0x00000003; 72 | SDRAM[0].EmcW2p = 0x0000000a; 73 | SDRAM[0].EmcRdRcd = 0x00000005; 74 | SDRAM[0].EmcWrRcd = 0x00000005; 75 | SDRAM[0].EmcRrd = 0x00000004; 76 | SDRAM[0].EmcRext = 0x00000001; 77 | SDRAM[0].EmcWdv = 0x00000003; 78 | SDRAM[0].EmcQUse = 0x00000004; 79 | SDRAM[0].EmcQRst = 0x00000003; 80 | SDRAM[0].EmcQSafe = 0x00000009; 81 | SDRAM[0].EmcRdv = 0x0000000c; 82 | SDRAM[0].EmcRefresh = 0x000009ff; 83 | SDRAM[0].EmcBurstRefreshNum = 0x00000000; 84 | SDRAM[0].EmcPdEx2Wr = 0x00000003; 85 | SDRAM[0].EmcPdEx2Rd = 0x00000003; 86 | SDRAM[0].EmcPChg2Pden = 0x00000005; 87 | SDRAM[0].EmcAct2Pden = 0x00000005; 88 | SDRAM[0].EmcAr2Pden = 0x00000001; 89 | SDRAM[0].EmcRw2Pden = 0x0000000e; 90 | SDRAM[0].EmcTxsr = 0x000000c8; 91 | SDRAM[0].EmcTcke = 0x00000003; 92 | SDRAM[0].EmcTfaw = 0x00000011; 93 | SDRAM[0].EmcTrpab = 0x00000006; 94 | SDRAM[0].EmcTClkStable = 0x00000006; 95 | SDRAM[0].EmcTClkStop = 0x00000002; 96 | SDRAM[0].EmcTRefBw = 0x00000000; 97 | SDRAM[0].EmcQUseExtra = 0x00000000; 98 | SDRAM[0].EmcFbioCfg1 = 0x00000000; 99 | SDRAM[0].EmcFbioDqsibDly = 0x1c1c1c1c; 100 | SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000; 101 | SDRAM[0].EmcFbioQuseDly = 0x74747474; 102 | SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000; 103 | SDRAM[0].EmcFbioCfg5 = 0x00000083; 104 | SDRAM[0].EmcFbioCfg6 = 0x00000002; 105 | SDRAM[0].EmcFbioSpare = 0x00000000; 106 | SDRAM[0].EmcMrs = 0x0000085a; 107 | SDRAM[0].EmcEmrs = 0x00100002; 108 | SDRAM[0].EmcMrw1 = 0x00000000; 109 | SDRAM[0].EmcMrw2 = 0x00000000; 110 | SDRAM[0].EmcMrw3 = 0x00000000; 111 | SDRAM[0].EmcMrwResetCommand = 0x00000000; 112 | SDRAM[0].EmcMrwResetNInitWait = 0x00000000; 113 | SDRAM[0].EmcAdrCfg = 0x00060303; 114 | SDRAM[0].EmcAdrCfg1 = 0x00060303; 115 | SDRAM[0].McEmemCfg = 0x00040000; 116 | SDRAM[0].McLowLatencyConfig = 0x80000003; 117 | SDRAM[0].EmcCfg = 0x0301ff00; 118 | SDRAM[0].EmcCfg2 = 0x00000405; 119 | SDRAM[0].EmcDbg = 0x01000400; 120 | SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000; 121 | SDRAM[0].EmcCfgDigDll = 0xf0000313; 122 | SDRAM[0].EmcDllXformDqs = 0x00000010; 123 | SDRAM[0].EmcDllXformQUse = 0x00000008; 124 | SDRAM[0].WarmBootWait = 0x00000002; 125 | SDRAM[0].EmcCttTermCtrl = 0x00000802; 126 | SDRAM[0].EmcOdtWrite = 0x00000000; 127 | SDRAM[0].EmcOdtRead = 0x00000000; 128 | SDRAM[0].EmcZcalRefCnt = 0x00000000; 129 | SDRAM[0].EmcZcalWaitCnt = 0x00000000; 130 | SDRAM[0].EmcZcalMrwCmd = 0x00000000; 131 | SDRAM[0].EmcMrsResetDll = 0x00000000; 132 | SDRAM[0].EmcMrwZqInitDev0 = 0x00000000; 133 | SDRAM[0].EmcMrwZqInitDev1 = 0x00000000; 134 | SDRAM[0].EmcMrwZqInitWait = 0x00000000; 135 | SDRAM[0].EmcMrsResetDllWait = 0x00000000; 136 | SDRAM[0].EmcEmrsEmr2 = 0x00200000; 137 | SDRAM[0].EmcEmrsEmr3 = 0x00300000; 138 | SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000; 139 | SDRAM[0].EmcMrsDdr2DllReset = 0x00000100; 140 | SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100386; 141 | SDRAM[0].EmcDdr2Wait = 0x00000002; 142 | SDRAM[0].EmcCfgClktrim0 = 0x00000000; 143 | SDRAM[0].EmcCfgClktrim1 = 0x00000000; 144 | SDRAM[0].EmcCfgClktrim2 = 0x00000000; 145 | SDRAM[0].PmcDdrPwr = 0x00000001; 146 | SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 147 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 148 | SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 149 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 150 | SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 151 | SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 152 | SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 153 | SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 154 | 155 | SDRAM[1].MemoryType = NvBootMemoryType_Ddr2; 156 | SDRAM[1].PllMChargePumpSetupControl = 0x00000008; 157 | SDRAM[1].PllMLoopFilterSetupControl = 0x00000000; 158 | SDRAM[1].PllMInputDivider = 0x0000000d; 159 | SDRAM[1].PllMFeedbackDivider = 0x0000029a; 160 | SDRAM[1].PllMPostDivider = 0x00000000; 161 | SDRAM[1].PllMStableTime = 0x0000012c; 162 | SDRAM[1].EmcClockDivider = 0x00000001; 163 | SDRAM[1].EmcAutoCalInterval = 0x00000000; 164 | SDRAM[1].EmcAutoCalConfig = 0xe0a61111; 165 | SDRAM[1].EmcAutoCalWait = 0x00000000; 166 | SDRAM[1].EmcPinProgramWait = 0x00000000; 167 | SDRAM[1].EmcRc = 0x00000014; 168 | SDRAM[1].EmcRfc = 0x0000002b; 169 | SDRAM[1].EmcRas = 0x0000000f; 170 | SDRAM[1].EmcRp = 0x00000005; 171 | SDRAM[1].EmcR2w = 0x00000004; 172 | SDRAM[1].EmcW2r = 0x00000005; 173 | SDRAM[1].EmcR2p = 0x00000003; 174 | SDRAM[1].EmcW2p = 0x0000000a; 175 | SDRAM[1].EmcRdRcd = 0x00000005; 176 | SDRAM[1].EmcWrRcd = 0x00000005; 177 | SDRAM[1].EmcRrd = 0x00000004; 178 | SDRAM[1].EmcRext = 0x00000001; 179 | SDRAM[1].EmcWdv = 0x00000003; 180 | SDRAM[1].EmcQUse = 0x00000004; 181 | SDRAM[1].EmcQRst = 0x00000003; 182 | SDRAM[1].EmcQSafe = 0x00000009; 183 | SDRAM[1].EmcRdv = 0x0000000c; 184 | SDRAM[1].EmcRefresh = 0x000009ff; 185 | SDRAM[1].EmcBurstRefreshNum = 0x00000000; 186 | SDRAM[1].EmcPdEx2Wr = 0x00000003; 187 | SDRAM[1].EmcPdEx2Rd = 0x00000003; 188 | SDRAM[1].EmcPChg2Pden = 0x00000005; 189 | SDRAM[1].EmcAct2Pden = 0x00000005; 190 | SDRAM[1].EmcAr2Pden = 0x00000001; 191 | SDRAM[1].EmcRw2Pden = 0x0000000e; 192 | SDRAM[1].EmcTxsr = 0x000000c8; 193 | SDRAM[1].EmcTcke = 0x00000003; 194 | SDRAM[1].EmcTfaw = 0x00000011; 195 | SDRAM[1].EmcTrpab = 0x00000006; 196 | SDRAM[1].EmcTClkStable = 0x00000006; 197 | SDRAM[1].EmcTClkStop = 0x00000002; 198 | SDRAM[1].EmcTRefBw = 0x00000000; 199 | SDRAM[1].EmcQUseExtra = 0x00000000; 200 | SDRAM[1].EmcFbioCfg1 = 0x00000000; 201 | SDRAM[1].EmcFbioDqsibDly = 0x1c1c1c1c; 202 | SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000; 203 | SDRAM[1].EmcFbioQuseDly = 0x74747474; 204 | SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000; 205 | SDRAM[1].EmcFbioCfg5 = 0x00000083; 206 | SDRAM[1].EmcFbioCfg6 = 0x00000002; 207 | SDRAM[1].EmcFbioSpare = 0x00000000; 208 | SDRAM[1].EmcMrs = 0x0000085a; 209 | SDRAM[1].EmcEmrs = 0x00100002; 210 | SDRAM[1].EmcMrw1 = 0x00000000; 211 | SDRAM[1].EmcMrw2 = 0x00000000; 212 | SDRAM[1].EmcMrw3 = 0x00000000; 213 | SDRAM[1].EmcMrwResetCommand = 0x00000000; 214 | SDRAM[1].EmcMrwResetNInitWait = 0x00000000; 215 | SDRAM[1].EmcAdrCfg = 0x00060303; 216 | SDRAM[1].EmcAdrCfg1 = 0x00060303; 217 | SDRAM[1].McEmemCfg = 0x00040000; 218 | SDRAM[1].McLowLatencyConfig = 0x80000003; 219 | SDRAM[1].EmcCfg = 0x0301ff00; 220 | SDRAM[1].EmcCfg2 = 0x00000405; 221 | SDRAM[1].EmcDbg = 0x01000400; 222 | SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000; 223 | SDRAM[1].EmcCfgDigDll = 0xf0000313; 224 | SDRAM[1].EmcDllXformDqs = 0x00000010; 225 | SDRAM[1].EmcDllXformQUse = 0x00000008; 226 | SDRAM[1].WarmBootWait = 0x00000002; 227 | SDRAM[1].EmcCttTermCtrl = 0x00000802; 228 | SDRAM[1].EmcOdtWrite = 0x00000000; 229 | SDRAM[1].EmcOdtRead = 0x00000000; 230 | SDRAM[1].EmcZcalRefCnt = 0x00000000; 231 | SDRAM[1].EmcZcalWaitCnt = 0x00000000; 232 | SDRAM[1].EmcZcalMrwCmd = 0x00000000; 233 | SDRAM[1].EmcMrsResetDll = 0x00000000; 234 | SDRAM[1].EmcMrwZqInitDev0 = 0x00000000; 235 | SDRAM[1].EmcMrwZqInitDev1 = 0x00000000; 236 | SDRAM[1].EmcMrwZqInitWait = 0x00000000; 237 | SDRAM[1].EmcMrsResetDllWait = 0x00000000; 238 | SDRAM[1].EmcEmrsEmr2 = 0x00200000; 239 | SDRAM[1].EmcEmrsEmr3 = 0x00300000; 240 | SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000; 241 | SDRAM[1].EmcMrsDdr2DllReset = 0x00000100; 242 | SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100386; 243 | SDRAM[1].EmcDdr2Wait = 0x00000002; 244 | SDRAM[1].EmcCfgClktrim0 = 0x00000000; 245 | SDRAM[1].EmcCfgClktrim1 = 0x00000000; 246 | SDRAM[1].EmcCfgClktrim2 = 0x00000000; 247 | SDRAM[1].PmcDdrPwr = 0x00000001; 248 | SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 249 | SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 250 | SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 251 | SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 252 | SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 253 | SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 254 | SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 255 | SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 256 | 257 | SDRAM[2].MemoryType = NvBootMemoryType_Ddr2; 258 | SDRAM[2].PllMChargePumpSetupControl = 0x00000008; 259 | SDRAM[2].PllMLoopFilterSetupControl = 0x00000000; 260 | SDRAM[2].PllMInputDivider = 0x0000000d; 261 | SDRAM[2].PllMFeedbackDivider = 0x0000029a; 262 | SDRAM[2].PllMPostDivider = 0x00000000; 263 | SDRAM[2].PllMStableTime = 0x0000012c; 264 | SDRAM[2].EmcClockDivider = 0x00000001; 265 | SDRAM[2].EmcAutoCalInterval = 0x00000000; 266 | SDRAM[2].EmcAutoCalConfig = 0xe0a61111; 267 | SDRAM[2].EmcAutoCalWait = 0x00000000; 268 | SDRAM[2].EmcPinProgramWait = 0x00000000; 269 | SDRAM[2].EmcRc = 0x00000014; 270 | SDRAM[2].EmcRfc = 0x0000002b; 271 | SDRAM[2].EmcRas = 0x0000000f; 272 | SDRAM[2].EmcRp = 0x00000005; 273 | SDRAM[2].EmcR2w = 0x00000004; 274 | SDRAM[2].EmcW2r = 0x00000005; 275 | SDRAM[2].EmcR2p = 0x00000003; 276 | SDRAM[2].EmcW2p = 0x0000000a; 277 | SDRAM[2].EmcRdRcd = 0x00000005; 278 | SDRAM[2].EmcWrRcd = 0x00000005; 279 | SDRAM[2].EmcRrd = 0x00000004; 280 | SDRAM[2].EmcRext = 0x00000001; 281 | SDRAM[2].EmcWdv = 0x00000003; 282 | SDRAM[2].EmcQUse = 0x00000004; 283 | SDRAM[2].EmcQRst = 0x00000003; 284 | SDRAM[2].EmcQSafe = 0x00000009; 285 | SDRAM[2].EmcRdv = 0x0000000c; 286 | SDRAM[2].EmcRefresh = 0x000009ff; 287 | SDRAM[2].EmcBurstRefreshNum = 0x00000000; 288 | SDRAM[2].EmcPdEx2Wr = 0x00000003; 289 | SDRAM[2].EmcPdEx2Rd = 0x00000003; 290 | SDRAM[2].EmcPChg2Pden = 0x00000005; 291 | SDRAM[2].EmcAct2Pden = 0x00000005; 292 | SDRAM[2].EmcAr2Pden = 0x00000001; 293 | SDRAM[2].EmcRw2Pden = 0x0000000e; 294 | SDRAM[2].EmcTxsr = 0x000000c8; 295 | SDRAM[2].EmcTcke = 0x00000003; 296 | SDRAM[2].EmcTfaw = 0x00000011; 297 | SDRAM[2].EmcTrpab = 0x00000006; 298 | SDRAM[2].EmcTClkStable = 0x00000006; 299 | SDRAM[2].EmcTClkStop = 0x00000002; 300 | SDRAM[2].EmcTRefBw = 0x00000000; 301 | SDRAM[2].EmcQUseExtra = 0x00000000; 302 | SDRAM[2].EmcFbioCfg1 = 0x00000000; 303 | SDRAM[2].EmcFbioDqsibDly = 0x1c1c1c1c; 304 | SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000; 305 | SDRAM[2].EmcFbioQuseDly = 0x74747474; 306 | SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000; 307 | SDRAM[2].EmcFbioCfg5 = 0x00000083; 308 | SDRAM[2].EmcFbioCfg6 = 0x00000002; 309 | SDRAM[2].EmcFbioSpare = 0x00000000; 310 | SDRAM[2].EmcMrs = 0x0000085a; 311 | SDRAM[2].EmcEmrs = 0x00100002; 312 | SDRAM[2].EmcMrw1 = 0x00000000; 313 | SDRAM[2].EmcMrw2 = 0x00000000; 314 | SDRAM[2].EmcMrw3 = 0x00000000; 315 | SDRAM[2].EmcMrwResetCommand = 0x00000000; 316 | SDRAM[2].EmcMrwResetNInitWait = 0x00000000; 317 | SDRAM[2].EmcAdrCfg = 0x00060303; 318 | SDRAM[2].EmcAdrCfg1 = 0x00060303; 319 | SDRAM[2].McEmemCfg = 0x00040000; 320 | SDRAM[2].McLowLatencyConfig = 0x80000003; 321 | SDRAM[2].EmcCfg = 0x0301ff00; 322 | SDRAM[2].EmcCfg2 = 0x00000405; 323 | SDRAM[2].EmcDbg = 0x01000400; 324 | SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000; 325 | SDRAM[2].EmcCfgDigDll = 0xf0000313; 326 | SDRAM[2].EmcDllXformDqs = 0x00000010; 327 | SDRAM[2].EmcDllXformQUse = 0x00000008; 328 | SDRAM[2].WarmBootWait = 0x00000002; 329 | SDRAM[2].EmcCttTermCtrl = 0x00000802; 330 | SDRAM[2].EmcOdtWrite = 0x00000000; 331 | SDRAM[2].EmcOdtRead = 0x00000000; 332 | SDRAM[2].EmcZcalRefCnt = 0x00000000; 333 | SDRAM[2].EmcZcalWaitCnt = 0x00000000; 334 | SDRAM[2].EmcZcalMrwCmd = 0x00000000; 335 | SDRAM[2].EmcMrsResetDll = 0x00000000; 336 | SDRAM[2].EmcMrwZqInitDev0 = 0x00000000; 337 | SDRAM[2].EmcMrwZqInitDev1 = 0x00000000; 338 | SDRAM[2].EmcMrwZqInitWait = 0x00000000; 339 | SDRAM[2].EmcMrsResetDllWait = 0x00000000; 340 | SDRAM[2].EmcEmrsEmr2 = 0x00200000; 341 | SDRAM[2].EmcEmrsEmr3 = 0x00300000; 342 | SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000; 343 | SDRAM[2].EmcMrsDdr2DllReset = 0x00000100; 344 | SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100386; 345 | SDRAM[2].EmcDdr2Wait = 0x00000002; 346 | SDRAM[2].EmcCfgClktrim0 = 0x00000000; 347 | SDRAM[2].EmcCfgClktrim1 = 0x00000000; 348 | SDRAM[2].EmcCfgClktrim2 = 0x00000000; 349 | SDRAM[2].PmcDdrPwr = 0x00000001; 350 | SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 351 | SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 352 | SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 353 | SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 354 | SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 355 | SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 356 | SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 357 | SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 358 | 359 | SDRAM[3].MemoryType = NvBootMemoryType_Ddr2; 360 | SDRAM[3].PllMChargePumpSetupControl = 0x00000008; 361 | SDRAM[3].PllMLoopFilterSetupControl = 0x00000000; 362 | SDRAM[3].PllMInputDivider = 0x0000000d; 363 | SDRAM[3].PllMFeedbackDivider = 0x0000029a; 364 | SDRAM[3].PllMPostDivider = 0x00000000; 365 | SDRAM[3].PllMStableTime = 0x0000012c; 366 | SDRAM[3].EmcClockDivider = 0x00000001; 367 | SDRAM[3].EmcAutoCalInterval = 0x00000000; 368 | SDRAM[3].EmcAutoCalConfig = 0xe0a61111; 369 | SDRAM[3].EmcAutoCalWait = 0x00000000; 370 | SDRAM[3].EmcPinProgramWait = 0x00000000; 371 | SDRAM[3].EmcRc = 0x00000014; 372 | SDRAM[3].EmcRfc = 0x0000002b; 373 | SDRAM[3].EmcRas = 0x0000000f; 374 | SDRAM[3].EmcRp = 0x00000005; 375 | SDRAM[3].EmcR2w = 0x00000004; 376 | SDRAM[3].EmcW2r = 0x00000005; 377 | SDRAM[3].EmcR2p = 0x00000003; 378 | SDRAM[3].EmcW2p = 0x0000000a; 379 | SDRAM[3].EmcRdRcd = 0x00000005; 380 | SDRAM[3].EmcWrRcd = 0x00000005; 381 | SDRAM[3].EmcRrd = 0x00000004; 382 | SDRAM[3].EmcRext = 0x00000001; 383 | SDRAM[3].EmcWdv = 0x00000003; 384 | SDRAM[3].EmcQUse = 0x00000004; 385 | SDRAM[3].EmcQRst = 0x00000003; 386 | SDRAM[3].EmcQSafe = 0x00000009; 387 | SDRAM[3].EmcRdv = 0x0000000c; 388 | SDRAM[3].EmcRefresh = 0x000009ff; 389 | SDRAM[3].EmcBurstRefreshNum = 0x00000000; 390 | SDRAM[3].EmcPdEx2Wr = 0x00000003; 391 | SDRAM[3].EmcPdEx2Rd = 0x00000003; 392 | SDRAM[3].EmcPChg2Pden = 0x00000005; 393 | SDRAM[3].EmcAct2Pden = 0x00000005; 394 | SDRAM[3].EmcAr2Pden = 0x00000001; 395 | SDRAM[3].EmcRw2Pden = 0x0000000e; 396 | SDRAM[3].EmcTxsr = 0x000000c8; 397 | SDRAM[3].EmcTcke = 0x00000003; 398 | SDRAM[3].EmcTfaw = 0x00000011; 399 | SDRAM[3].EmcTrpab = 0x00000006; 400 | SDRAM[3].EmcTClkStable = 0x00000006; 401 | SDRAM[3].EmcTClkStop = 0x00000002; 402 | SDRAM[3].EmcTRefBw = 0x00000000; 403 | SDRAM[3].EmcQUseExtra = 0x00000000; 404 | SDRAM[3].EmcFbioCfg1 = 0x00000000; 405 | SDRAM[3].EmcFbioDqsibDly = 0x1c1c1c1c; 406 | SDRAM[3].EmcFbioDqsibDlyMsb = 0x00000000; 407 | SDRAM[3].EmcFbioQuseDly = 0x74747474; 408 | SDRAM[3].EmcFbioQuseDlyMsb = 0x00000000; 409 | SDRAM[3].EmcFbioCfg5 = 0x00000083; 410 | SDRAM[3].EmcFbioCfg6 = 0x00000002; 411 | SDRAM[3].EmcFbioSpare = 0x00000000; 412 | SDRAM[3].EmcMrs = 0x0000085a; 413 | SDRAM[3].EmcEmrs = 0x00100002; 414 | SDRAM[3].EmcMrw1 = 0x00000000; 415 | SDRAM[3].EmcMrw2 = 0x00000000; 416 | SDRAM[3].EmcMrw3 = 0x00000000; 417 | SDRAM[3].EmcMrwResetCommand = 0x00000000; 418 | SDRAM[3].EmcMrwResetNInitWait = 0x00000000; 419 | SDRAM[3].EmcAdrCfg = 0x00060303; 420 | SDRAM[3].EmcAdrCfg1 = 0x00060303; 421 | SDRAM[3].McEmemCfg = 0x00040000; 422 | SDRAM[3].McLowLatencyConfig = 0x80000003; 423 | SDRAM[3].EmcCfg = 0x0301ff00; 424 | SDRAM[3].EmcCfg2 = 0x00000405; 425 | SDRAM[3].EmcDbg = 0x01000400; 426 | SDRAM[3].AhbArbitrationXbarCtrl = 0x00010000; 427 | SDRAM[3].EmcCfgDigDll = 0xf0000313; 428 | SDRAM[3].EmcDllXformDqs = 0x00000010; 429 | SDRAM[3].EmcDllXformQUse = 0x00000008; 430 | SDRAM[3].WarmBootWait = 0x00000002; 431 | SDRAM[3].EmcCttTermCtrl = 0x00000802; 432 | SDRAM[3].EmcOdtWrite = 0x00000000; 433 | SDRAM[3].EmcOdtRead = 0x00000000; 434 | SDRAM[3].EmcZcalRefCnt = 0x00000000; 435 | SDRAM[3].EmcZcalWaitCnt = 0x00000000; 436 | SDRAM[3].EmcZcalMrwCmd = 0x00000000; 437 | SDRAM[3].EmcMrsResetDll = 0x00000000; 438 | SDRAM[3].EmcMrwZqInitDev0 = 0x00000000; 439 | SDRAM[3].EmcMrwZqInitDev1 = 0x00000000; 440 | SDRAM[3].EmcMrwZqInitWait = 0x00000000; 441 | SDRAM[3].EmcMrsResetDllWait = 0x00000000; 442 | SDRAM[3].EmcEmrsEmr2 = 0x00200000; 443 | SDRAM[3].EmcEmrsEmr3 = 0x00300000; 444 | SDRAM[3].EmcEmrsDdr2DllEnable = 0x00100000; 445 | SDRAM[3].EmcMrsDdr2DllReset = 0x00000100; 446 | SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00100386; 447 | SDRAM[3].EmcDdr2Wait = 0x00000002; 448 | SDRAM[3].EmcCfgClktrim0 = 0x00000000; 449 | SDRAM[3].EmcCfgClktrim1 = 0x00000000; 450 | SDRAM[3].EmcCfgClktrim2 = 0x00000000; 451 | SDRAM[3].PmcDdrPwr = 0x00000001; 452 | SDRAM[3].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000; 453 | SDRAM[3].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0; 454 | SDRAM[3].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079; 455 | SDRAM[3].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0; 456 | SDRAM[3].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009; 457 | SDRAM[3].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000; 458 | SDRAM[3].ApbMiscGpXm2CompPadCtrl = 0x01f1f008; 459 | SDRAM[3].ApbMiscGpXm2VttGenPadCtrl = 0x07076600; 460 | --------------------------------------------------------------------------------