├── Kconfig ├── Makefile ├── README ├── gk20a ├── as_gk20a.c ├── as_gk20a.h ├── channel_gk20a.c ├── channel_gk20a.h ├── channel_sync_gk20a.c ├── channel_sync_gk20a.h ├── clk_gk20a.c ├── clk_gk20a.h ├── ctrl_gk20a.c ├── ctrl_gk20a.h ├── dbg_gpu_gk20a.c ├── dbg_gpu_gk20a.h ├── debug_gk20a.c ├── debug_gk20a.h ├── fb_gk20a.c ├── fb_gk20a.h ├── fence_gk20a.c ├── fence_gk20a.h ├── fifo_gk20a.c ├── fifo_gk20a.h ├── gk20a.c ├── gk20a.h ├── gk20a_allocator.c ├── gk20a_allocator.h ├── gk20a_gating_reglist.c ├── gk20a_gating_reglist.h ├── gk20a_scale.c ├── gk20a_scale.h ├── gk20a_sysfs.c ├── gr_ctx_gk20a.c ├── gr_ctx_gk20a.h ├── gr_gk20a.c ├── gr_gk20a.h ├── gr_pri_gk20a.h ├── hal.c ├── hal.h ├── hal_gk20a.c ├── hal_gk20a.h ├── hw_bus_gk20a.h ├── hw_ccsr_gk20a.h ├── hw_ctxsw_prog_gk20a.h ├── hw_fb_gk20a.h ├── hw_fifo_gk20a.h ├── hw_flush_gk20a.h ├── hw_gmmu_gk20a.h ├── hw_gr_gk20a.h ├── hw_ltc_gk20a.h ├── hw_mc_gk20a.h ├── hw_pbdma_gk20a.h ├── hw_pri_ringmaster_gk20a.h ├── hw_pri_ringstation_fbp_gk20a.h ├── hw_pri_ringstation_gpc_gk20a.h ├── hw_pri_ringstation_sys_gk20a.h ├── hw_proj_gk20a.h ├── hw_pwr_gk20a.h ├── hw_ram_gk20a.h ├── hw_therm_gk20a.h ├── hw_timer_gk20a.h ├── hw_top_gk20a.h ├── hw_trim_gk20a.h ├── kind_gk20a.c ├── kind_gk20a.h ├── ltc_common.c ├── ltc_gk20a.c ├── ltc_gk20a.h ├── mc_gk20a.c ├── mc_gk20a.h ├── mm_gk20a.c ├── mm_gk20a.h ├── platform_gk20a.h ├── platform_gk20a_generic.c ├── platform_gk20a_tegra.c ├── pmu_gk20a.c ├── pmu_gk20a.h ├── priv_ring_gk20a.c ├── priv_ring_gk20a.h ├── regops_gk20a.c ├── regops_gk20a.h ├── semaphore_gk20a.c ├── semaphore_gk20a.h ├── sync_gk20a.c ├── sync_gk20a.h ├── therm_gk20a.c ├── therm_gk20a.h ├── tsg_gk20a.c └── tsg_gk20a.h ├── include ├── linux │ └── gk20a.h └── trace │ └── events │ └── gk20a.h ├── scripts └── nvgpu_ucode │ ├── README │ └── ucodesignature.py └── uapi └── linux └── nvgpu.h /Kconfig: -------------------------------------------------------------------------------- 1 | config GK20A 2 | tristate "Nvidia GK20A GPU support" 3 | default y 4 | help 5 | Choose this option if you have an SoC with integrated 6 | Nvidia GPU IP. 7 | 8 | config GK20A_DEFAULT_TIMEOUT 9 | depends on GK20A 10 | int "Default timeout for submits" 11 | default 10000 12 | help 13 | Default timeout for jobs in milliseconds. Set to zero for no timeout. 14 | 15 | config GK20A_PMU 16 | bool "Support GK20A PMU" 17 | depends on GK20A 18 | default n 19 | help 20 | Say Y here to enable GK20A PMU features. 21 | 22 | choice 23 | depends on GK20A 24 | prompt "Enable GK20A frequency scaling" 25 | default GK20A_PERFMON 26 | optional 27 | help 28 | Select this entry to enable gk20a scaling 29 | 30 | config GK20A_PERFMON 31 | bool "Use Perfmon" 32 | help 33 | Select this to enable built-in perfmon scaling. 34 | The built-in scaling option uses simplistic 35 | scaling mechanism (if busy, increase frequency and 36 | decrease frequency if idle). 37 | 38 | config GK20A_DEVFREQ 39 | depends on TEGRA_CLK_FRAMEWORK 40 | bool "Use Devfreq" 41 | help 42 | Select this to use devfreq based scaling. 43 | Devfreq is a common framework that allows using 44 | variety of different governors and changing 45 | between governors on the fly. By default, no 46 | governor is selected. 47 | 48 | endchoice 49 | 50 | config GK20A_CYCLE_STATS 51 | bool "Support GK20A GPU CYCLE STATS" 52 | depends on GK20A 53 | default y 54 | help 55 | Say Y here to enable the cycle stats debugging features. 56 | 57 | config TEGRA_GK20A 58 | bool "Enable the GK20A GPU on Tegra" 59 | depends on TEGRA_GRHOST 60 | depends on GK20A 61 | default y 62 | help 63 | Enable support for the GK20A graphics engine on Tegra 64 | by adding a Tegra platfrom interface to the GK20A driver. 65 | The Tegra platform interface requires TEGRA_GRHOST (host1x). 66 | 67 | config TEGRA_USE_NA_GPCPLL 68 | bool "Enable noise aware mode of GPCPLL on Tegra" 69 | depends on TEGRA_CLK_FRAMEWORK 70 | default n 71 | help 72 | Enable noise aware (NA) mode of GPCPLL. In this mode PLL output 73 | frequency is automatically adjusted when voltage is fluctuating 74 | because of transient PMIC or power distribution tree noise. 75 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | GCOV_PROFILE := y 2 | 3 | ccflags-y += -Idrivers/gpu/nvgpu 4 | ccflags-y += -Idrivers/video/tegra/host 5 | ccflags-y += -Idrivers/devfreq 6 | ccflags-y += -Wno-multichar 7 | ccflags-y += -Werror 8 | 9 | obj-$(CONFIG_GK20A) := nvgpu.o 10 | 11 | nvgpu-y := \ 12 | gk20a/gk20a.o \ 13 | gk20a/as_gk20a.o \ 14 | gk20a/ctrl_gk20a.o \ 15 | gk20a/fifo_gk20a.o \ 16 | gk20a/channel_gk20a.o \ 17 | gk20a/channel_sync_gk20a.o \ 18 | gk20a/debug_gk20a.o \ 19 | gk20a/dbg_gpu_gk20a.o \ 20 | gk20a/regops_gk20a.o \ 21 | gk20a/gr_gk20a.o \ 22 | gk20a/kind_gk20a.o \ 23 | gk20a/mm_gk20a.o \ 24 | gk20a/pmu_gk20a.o \ 25 | gk20a/priv_ring_gk20a.o \ 26 | gk20a/semaphore_gk20a.o \ 27 | gk20a/fence_gk20a.o \ 28 | gk20a/therm_gk20a.o \ 29 | gk20a/gr_ctx_gk20a.o \ 30 | gk20a/gk20a_gating_reglist.o \ 31 | gk20a/gk20a_sysfs.o \ 32 | gk20a/ltc_gk20a.o \ 33 | gk20a/fb_gk20a.o \ 34 | gk20a/hal.o \ 35 | gk20a/hal_gk20a.o \ 36 | gk20a/gk20a_allocator.o \ 37 | gk20a/platform_gk20a_generic.o \ 38 | gk20a/tsg_gk20a.o \ 39 | gk20a/mc_gk20a.o 40 | 41 | nvgpu-$(CONFIG_TEGRA_GK20A) += gk20a/platform_gk20a_tegra.o 42 | nvgpu-$(CONFIG_SYNC) += gk20a/sync_gk20a.o 43 | 44 | nvgpu-$(CONFIG_TEGRA_CLK_FRAMEWORK) += \ 45 | gk20a/clk_gk20a.o 46 | 47 | nvgpu-$(CONFIG_GK20A_DEVFREQ) += \ 48 | gk20a/gk20a_scale.o 49 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | The code presented here is from NVIDIA's internal dev-kernel-3.10 Linux 2 | kernel branch @ commit 85e66d9e32f18056d55cd1781c9c76d80c0bc069. 3 | 4 | .../kernel/drivers/gpu/nvgpu/*.[ch] 5 | .../kernel/include/uapi/linux/nvgpu.h 6 | .../kernel/scripts/nvgpu_ucode 7 | .../kernel/include/linux/gk20a.h 8 | .../kernel/include/trace/events/gk20a.h 9 | .../kernel/drivers/gpu/nvgpu/gk20a/ 10 | 11 | The dev-kernel branch within NVIDIA is used for Android and Linux for Tegra 12 | (L4T) product distributions. Examples of these: 13 | . Android: https://android.googlesource.com/kernel/tegra/ 14 | . L4T: https://developer.nvidia.com/linux-tegra 15 | 16 | The code presented will be morphed into a form which can be made directly 17 | useful to Nouveau. That effort includes: 18 | 19 | . Normalizing headers with regard to NVIDIA GPU concepts/engines already 20 | present within Nouveau. 21 | . Eliminating superfluous code within 'nvgpu.' 22 | . Bolstering Nouveau code with nvgpu functionality. 23 | . Adapting to Nouveau run-time behaviour/formulation. 24 | 25 | Ken Adams 26 | kadams@nvidia.com 27 | -------------------------------------------------------------------------------- /gk20a/as_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * GK20A Address Spaces 3 | * 4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | */ 15 | #ifndef AS_GK20A_H 16 | #define AS_GK20A_H 17 | 18 | #include 19 | #include 20 | #include 21 | 22 | struct gk20a_as; 23 | struct gk20a_as_share; 24 | struct vm_gk20a; 25 | 26 | struct gk20a_as_share { 27 | struct gk20a_as *as; 28 | atomic_t ref_cnt; 29 | int id; 30 | struct vm_gk20a *vm; 31 | }; 32 | 33 | struct gk20a_as { 34 | int last_share_id; /* dummy allocator for now */ 35 | struct cdev cdev; 36 | struct device *node; 37 | }; 38 | 39 | int gk20a_as_release_share(struct gk20a_as_share *as_share); 40 | 41 | /* struct file_operations driver interface */ 42 | int gk20a_as_dev_open(struct inode *inode, struct file *filp); 43 | int gk20a_as_dev_release(struct inode *inode, struct file *filp); 44 | long gk20a_as_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); 45 | int gk20a_as_alloc_share(struct gk20a_as *as, 46 | u32 flags, struct gk20a_as_share **out); 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /gk20a/channel_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * GK20A graphics channel 3 | * 4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | #ifndef CHANNEL_GK20A_H 19 | #define CHANNEL_GK20A_H 20 | 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | 29 | struct gk20a; 30 | struct gr_gk20a; 31 | struct dbg_session_gk20a; 32 | struct gk20a_fence; 33 | 34 | #include "channel_sync_gk20a.h" 35 | 36 | #include "mm_gk20a.h" 37 | #include "gr_gk20a.h" 38 | #include "fence_gk20a.h" 39 | 40 | struct gpfifo { 41 | u32 entry0; 42 | u32 entry1; 43 | }; 44 | 45 | struct notification { 46 | struct { 47 | u32 nanoseconds[2]; 48 | } timestamp; 49 | u32 info32; 50 | u16 info16; 51 | u16 status; 52 | }; 53 | 54 | struct fence { 55 | u32 hw_chid; 56 | u32 syncpt_val; 57 | }; 58 | 59 | /* contexts associated with a channel */ 60 | struct channel_ctx_gk20a { 61 | struct gr_ctx_desc *gr_ctx; 62 | struct pm_ctx_desc pm_ctx; 63 | struct patch_desc patch_ctx; 64 | struct zcull_ctx_desc zcull_ctx; 65 | u64 global_ctx_buffer_va[NR_GLOBAL_CTX_BUF_VA]; 66 | u64 global_ctx_buffer_size[NR_GLOBAL_CTX_BUF_VA]; 67 | bool global_ctx_buffer_mapped; 68 | }; 69 | 70 | struct channel_gk20a_job { 71 | struct mapped_buffer_node **mapped_buffers; 72 | int num_mapped_buffers; 73 | struct gk20a_fence *pre_fence; 74 | struct gk20a_fence *post_fence; 75 | struct list_head list; 76 | }; 77 | 78 | struct channel_gk20a_poll_events { 79 | struct mutex lock; 80 | bool events_enabled; 81 | int num_pending_events; 82 | }; 83 | 84 | /* this is the priv element of struct nvhost_channel */ 85 | struct channel_gk20a { 86 | struct gk20a *g; 87 | bool in_use; 88 | int hw_chid; 89 | bool bound; 90 | bool first_init; 91 | bool vpr; 92 | pid_t pid; 93 | 94 | int tsgid; 95 | struct list_head ch_entry; /* channel's entry in TSG */ 96 | 97 | struct list_head jobs; 98 | struct mutex jobs_lock; 99 | struct mutex submit_lock; 100 | 101 | struct vm_gk20a *vm; 102 | 103 | struct gpfifo_desc gpfifo; 104 | 105 | struct channel_ctx_gk20a ch_ctx; 106 | 107 | struct inst_desc inst_block; 108 | struct mem_desc_sub ramfc; 109 | 110 | void *userd_cpu_va; 111 | u64 userd_iova; 112 | u64 userd_gpu_va; 113 | 114 | s32 num_objects; 115 | u32 obj_class; /* we support only one obj per channel */ 116 | 117 | struct priv_cmd_queue priv_cmd_q; 118 | 119 | wait_queue_head_t notifier_wq; 120 | wait_queue_head_t semaphore_wq; 121 | wait_queue_head_t submit_wq; 122 | 123 | u32 timeout_accumulated_ms; 124 | u32 timeout_gpfifo_get; 125 | 126 | bool cmds_pending; 127 | struct { 128 | /* These fences should be accessed with submit_lock held. */ 129 | struct gk20a_fence *pre_fence; 130 | struct gk20a_fence *post_fence; 131 | } last_submit; 132 | 133 | void (*remove_support)(struct channel_gk20a *); 134 | #if defined(CONFIG_GK20A_CYCLE_STATS) 135 | struct { 136 | void *cyclestate_buffer; 137 | u32 cyclestate_buffer_size; 138 | struct dma_buf *cyclestate_buffer_handler; 139 | struct mutex cyclestate_buffer_mutex; 140 | } cyclestate; 141 | #endif 142 | struct mutex dbg_s_lock; 143 | struct list_head dbg_s_list; 144 | 145 | bool has_timedout; 146 | u32 timeout_ms_max; 147 | bool timeout_debug_dump; 148 | 149 | struct dma_buf *error_notifier_ref; 150 | struct nvgpu_notification *error_notifier; 151 | void *error_notifier_va; 152 | 153 | struct gk20a_channel_sync *sync; 154 | 155 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION 156 | u64 virt_ctx; 157 | #endif 158 | 159 | /* event support */ 160 | struct channel_gk20a_poll_events poll_events; 161 | 162 | /* signal channel owner via a callback, if set, in gk20a_channel_update 163 | * via schedule_work */ 164 | void (*update_fn)(struct channel_gk20a *, void *); 165 | void *update_fn_data; 166 | spinlock_t update_fn_lock; /* make access to the two above atomic */ 167 | struct work_struct update_fn_work; 168 | }; 169 | 170 | static inline bool gk20a_channel_as_bound(struct channel_gk20a *ch) 171 | { 172 | return !!ch->vm; 173 | } 174 | int channel_gk20a_commit_va(struct channel_gk20a *c); 175 | int gk20a_init_channel_support(struct gk20a *, u32 chid); 176 | void gk20a_free_channel(struct channel_gk20a *ch, bool finish); 177 | bool gk20a_channel_update_and_check_timeout(struct channel_gk20a *ch, 178 | u32 timeout_delta_ms); 179 | void gk20a_disable_channel(struct channel_gk20a *ch, 180 | bool wait_for_finish, 181 | unsigned long finish_timeout); 182 | void gk20a_channel_abort(struct channel_gk20a *ch); 183 | int gk20a_channel_finish(struct channel_gk20a *ch, unsigned long timeout); 184 | void gk20a_set_error_notifier(struct channel_gk20a *ch, __u32 error); 185 | void gk20a_channel_semaphore_wakeup(struct gk20a *g); 186 | int gk20a_channel_alloc_priv_cmdbuf(struct channel_gk20a *c, u32 size, 187 | struct priv_cmd_entry **entry); 188 | 189 | int gk20a_channel_suspend(struct gk20a *g); 190 | int gk20a_channel_resume(struct gk20a *g); 191 | 192 | /* Channel file operations */ 193 | int gk20a_channel_open(struct inode *inode, struct file *filp); 194 | long gk20a_channel_ioctl(struct file *filp, 195 | unsigned int cmd, 196 | unsigned long arg); 197 | int gk20a_channel_release(struct inode *inode, struct file *filp); 198 | struct channel_gk20a *gk20a_get_channel_from_file(int fd); 199 | void gk20a_channel_update(struct channel_gk20a *c, int nr_completed); 200 | unsigned int gk20a_channel_poll(struct file *filep, poll_table *wait); 201 | void gk20a_channel_event(struct channel_gk20a *ch); 202 | 203 | void gk20a_init_channel(struct gpu_ops *gops); 204 | 205 | int gk20a_wait_channel_idle(struct channel_gk20a *ch); 206 | struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g); 207 | struct channel_gk20a *gk20a_open_new_channel_with_cb(struct gk20a *g, 208 | void (*update_fn)(struct channel_gk20a *, void *), 209 | void *update_fn_data); 210 | void channel_gk20a_unbind(struct channel_gk20a *ch_gk20a); 211 | 212 | int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, 213 | struct nvgpu_gpfifo *gpfifo, 214 | u32 num_entries, 215 | u32 flags, 216 | struct nvgpu_fence *fence, 217 | struct gk20a_fence **fence_out); 218 | 219 | int gk20a_alloc_channel_gpfifo(struct channel_gk20a *c, 220 | struct nvgpu_alloc_gpfifo_args *args); 221 | 222 | void channel_gk20a_unbind(struct channel_gk20a *ch_gk20a); 223 | void channel_gk20a_disable(struct channel_gk20a *ch); 224 | int channel_gk20a_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); 225 | void channel_gk20a_free_inst(struct gk20a *g, struct channel_gk20a *ch); 226 | int channel_gk20a_setup_ramfc(struct channel_gk20a *c, 227 | u64 gpfifo_base, u32 gpfifo_entries); 228 | void channel_gk20a_enable(struct channel_gk20a *ch); 229 | #endif /* CHANNEL_GK20A_H */ 230 | -------------------------------------------------------------------------------- /gk20a/channel_sync_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/channel_sync_gk20a.h 3 | * 4 | * GK20A Channel Synchronization Abstraction 5 | * 6 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | */ 17 | 18 | #ifndef _GK20A_CHANNEL_SYNC_H_ 19 | #define _GK20A_CHANNEL_SYNC_H_ 20 | 21 | #include 22 | 23 | struct gk20a_channel_sync; 24 | struct priv_cmd_entry; 25 | struct channel_gk20a; 26 | struct gk20a_semaphore; 27 | struct gk20a_fence; 28 | 29 | struct gk20a_channel_sync { 30 | /* Generate a gpu wait cmdbuf from syncpoint. 31 | * Returns 32 | * - a gpu cmdbuf that performs the wait when executed, 33 | * - possibly a helper fence that the caller must hold until the 34 | * cmdbuf is executed. 35 | */ 36 | int (*wait_syncpt)(struct gk20a_channel_sync *s, u32 id, u32 thresh, 37 | struct priv_cmd_entry **entry, 38 | struct gk20a_fence **fence); 39 | 40 | /* Generate a gpu wait cmdbuf from sync fd. 41 | * Returns 42 | * - a gpu cmdbuf that performs the wait when executed, 43 | * - possibly a helper fence that the caller must hold until the 44 | * cmdbuf is executed. 45 | */ 46 | int (*wait_fd)(struct gk20a_channel_sync *s, int fd, 47 | struct priv_cmd_entry **entry, 48 | struct gk20a_fence **fence); 49 | 50 | /* Increment syncpoint/semaphore. 51 | * Returns 52 | * - a gpu cmdbuf that performs the increment when executed, 53 | * - a fence that can be passed to wait_cpu() and is_expired(). 54 | */ 55 | int (*incr)(struct gk20a_channel_sync *s, 56 | struct priv_cmd_entry **entry, 57 | struct gk20a_fence **fence); 58 | 59 | /* Increment syncpoint/semaphore, preceded by a wfi. 60 | * Returns 61 | * - a gpu cmdbuf that performs the increment when executed, 62 | * - a fence that can be passed to wait_cpu() and is_expired(). 63 | */ 64 | int (*incr_wfi)(struct gk20a_channel_sync *s, 65 | struct priv_cmd_entry **entry, 66 | struct gk20a_fence **fence); 67 | 68 | /* Increment syncpoint/semaphore, so that the returned fence represents 69 | * work completion (may need wfi) and can be returned to user space. 70 | * Returns 71 | * - a gpu cmdbuf that performs the increment when executed, 72 | * - a fence that can be passed to wait_cpu() and is_expired(), 73 | * - a gk20a_fence that signals when the incr has happened. 74 | */ 75 | int (*incr_user)(struct gk20a_channel_sync *s, 76 | int wait_fence_fd, 77 | struct priv_cmd_entry **entry, 78 | struct gk20a_fence **fence, 79 | bool wfi); 80 | 81 | /* Reset the channel syncpoint/semaphore. */ 82 | void (*set_min_eq_max)(struct gk20a_channel_sync *s); 83 | 84 | /* Signals the sync timeline (if owned by the gk20a_channel_sync layer). 85 | * This should be called when we notice that a gk20a_fence is 86 | * expired. */ 87 | void (*signal_timeline)(struct gk20a_channel_sync *s); 88 | 89 | /* flag to set sync destroy aggressiveness */ 90 | bool aggressive_destroy; 91 | 92 | /* Free the resources allocated by gk20a_channel_sync_create. */ 93 | void (*destroy)(struct gk20a_channel_sync *s); 94 | }; 95 | 96 | struct gk20a_channel_sync *gk20a_channel_sync_create(struct channel_gk20a *c); 97 | 98 | #endif 99 | -------------------------------------------------------------------------------- /gk20a/clk_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2011 - 2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | #ifndef CLK_GK20A_H 17 | #define CLK_GK20A_H 18 | 19 | #include 20 | 21 | #define GPUFREQ_TABLE_END ~(u32)1 22 | enum { 23 | /* only one PLL for gk20a */ 24 | GK20A_GPC_PLL = 0, 25 | }; 26 | 27 | enum gpc_pll_mode { 28 | GPC_PLL_MODE_F = 0, 29 | GPC_PLL_MODE_DVFS, 30 | }; 31 | 32 | struct na_dvfs { 33 | u32 n_int; 34 | u32 sdm_din; 35 | int dfs_coeff; 36 | int dfs_det_max; 37 | int dfs_ext_cal; 38 | int uv_cal; 39 | int mv; 40 | }; 41 | 42 | struct pll { 43 | u32 id; 44 | u32 clk_in; /* KHz */ 45 | u32 M; 46 | u32 N; 47 | u32 PL; 48 | u32 freq; /* KHz */ 49 | bool enabled; 50 | enum gpc_pll_mode mode; 51 | struct na_dvfs dvfs; 52 | }; 53 | 54 | struct pll_parms { 55 | u32 min_freq, max_freq; /* KHz */ 56 | u32 min_vco, max_vco; /* KHz */ 57 | u32 min_u, max_u; /* KHz */ 58 | u32 min_M, max_M; 59 | u32 min_N, max_N; 60 | u32 min_PL, max_PL; 61 | /* NA mode parameters*/ 62 | int coeff_slope, coeff_offs; /* coeff = slope * V + offs */ 63 | int uvdet_slope, uvdet_offs; /* uV = slope * det + offs */ 64 | u32 vco_ctrl; 65 | }; 66 | 67 | struct clk_gk20a { 68 | struct gk20a *g; 69 | struct clk *tegra_clk; 70 | struct pll gpc_pll; 71 | struct pll gpc_pll_last; 72 | u32 pll_delay; /* default PLL settle time */ 73 | u32 na_pll_delay; /* default PLL settle time in NA mode */ 74 | struct mutex clk_mutex; 75 | bool sw_ready; 76 | bool clk_hw_on; 77 | bool debugfs_set; 78 | }; 79 | 80 | struct gpu_ops; 81 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK 82 | void gk20a_init_clk_ops(struct gpu_ops *gops); 83 | #else 84 | static inline void gk20a_init_clk_ops(struct gpu_ops *gops) {} 85 | #endif 86 | 87 | /* APIs used for GK20A */ 88 | unsigned long gk20a_clk_get_rate(struct gk20a *g); 89 | int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate); 90 | long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate); 91 | struct clk *gk20a_clk_get(struct gk20a *g); 92 | 93 | #define KHZ 1000 94 | #define MHZ 1000000 95 | 96 | static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate) 97 | { 98 | /* convert the kHz gpc2clk frequency to Hz gpcpll frequency */ 99 | return (rate * KHZ) / 2; 100 | } 101 | static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate) 102 | { 103 | /* convert the Hz gpcpll frequency to kHz gpc2clk frequency */ 104 | return (rate * 2) / KHZ; 105 | } 106 | 107 | #endif /* CLK_GK20A_H */ 108 | -------------------------------------------------------------------------------- /gk20a/ctrl_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | #ifndef CTRL_GK20A_H 17 | #define CTRL_GK20A_H 18 | 19 | int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp); 20 | int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp); 21 | long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); 22 | 23 | #endif /* CTRL_GK20A_H */ 24 | -------------------------------------------------------------------------------- /gk20a/dbg_gpu_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Tegra GK20A GPU Debugger Driver 3 | * 4 | * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | #ifndef DBG_GPU_GK20A_H 19 | #define DBG_GPU_GK20A_H 20 | #include 21 | 22 | /* module debug driver interface */ 23 | int gk20a_dbg_gpu_dev_release(struct inode *inode, struct file *filp); 24 | int gk20a_dbg_gpu_dev_open(struct inode *inode, struct file *filp); 25 | long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); 26 | unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait); 27 | 28 | /* used by profiler driver interface */ 29 | int gk20a_prof_gpu_dev_open(struct inode *inode, struct file *filp); 30 | 31 | /* used by the interrupt handler to post events */ 32 | void gk20a_dbg_gpu_post_events(struct channel_gk20a *fault_ch); 33 | 34 | struct dbg_gpu_session_ops { 35 | int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s, 36 | struct nvgpu_dbg_gpu_reg_op *ops, 37 | u64 num_ops); 38 | }; 39 | 40 | struct dbg_gpu_session_events { 41 | wait_queue_head_t wait_queue; 42 | bool events_enabled; 43 | int num_pending_events; 44 | }; 45 | 46 | struct dbg_session_gk20a { 47 | /* dbg session id used for trace/prints */ 48 | int id; 49 | 50 | /* profiler session, if any */ 51 | bool is_profiler; 52 | 53 | /* power enabled or disabled */ 54 | bool is_pg_disabled; 55 | 56 | /* 57 | * There can be different versions of the whitelists 58 | * between both global and per-context sets; as well 59 | * as between debugger and profiler interfaces. 60 | */ 61 | struct regops_whitelist *global; 62 | struct regops_whitelist *per_context; 63 | 64 | /* gpu module vagaries */ 65 | struct device *dev; 66 | struct platform_device *pdev; 67 | struct gk20a *g; 68 | 69 | /* bound channel, if any */ 70 | struct file *ch_f; 71 | struct channel_gk20a *ch; 72 | 73 | /* session operations */ 74 | struct dbg_gpu_session_ops *ops; 75 | 76 | /* event support */ 77 | struct dbg_gpu_session_events dbg_events; 78 | struct list_head dbg_s_list_node; 79 | }; 80 | 81 | extern struct dbg_gpu_session_ops dbg_gpu_session_ops_gk20a; 82 | 83 | #endif /* DBG_GPU_GK20A_H */ 84 | -------------------------------------------------------------------------------- /gk20a/debug_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * GK20A Debug functionality 3 | * 4 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This software is licensed under the terms of the GNU General Public 7 | * License version 2, as published by the Free Software Foundation, and 8 | * may be copied, distributed, and modified under those terms. 9 | * 10 | * This program is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | */ 16 | 17 | #ifndef _DEBUG_GK20A_H_ 18 | #define _DEBUG_GK20A_H_ 19 | 20 | struct platform_device; 21 | 22 | extern unsigned int gk20a_debug_trace_cmdbuf; 23 | 24 | void gk20a_debug_dump(struct platform_device *pdev); 25 | void gk20a_debug_init(struct platform_device *pdev); 26 | 27 | #endif 28 | -------------------------------------------------------------------------------- /gk20a/fb_gk20a.c: -------------------------------------------------------------------------------- 1 | /* 2 | * GK20A memory interface 3 | * 4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | */ 15 | 16 | #include 17 | 18 | #include "gk20a.h" 19 | #include "kind_gk20a.h" 20 | #include "hw_mc_gk20a.h" 21 | #include "hw_fb_gk20a.h" 22 | 23 | static void fb_gk20a_reset(struct gk20a *g) 24 | { 25 | gk20a_dbg_info("reset gk20a fb"); 26 | 27 | gk20a_reset(g, mc_enable_pfb_enabled_f() 28 | | mc_enable_l2_enabled_f() 29 | | mc_enable_xbar_enabled_f() 30 | | mc_enable_hub_enabled_f()); 31 | } 32 | 33 | static void gk20a_fb_set_mmu_page_size(struct gk20a *g) 34 | { 35 | /* set large page size in fb */ 36 | u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r()); 37 | 38 | fb_mmu_ctrl = (fb_mmu_ctrl & 39 | ~fb_mmu_ctrl_vm_pg_size_f(~0x0)) | 40 | fb_mmu_ctrl_vm_pg_size_128kb_f(); 41 | 42 | gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl); 43 | } 44 | 45 | void gk20a_init_fb(struct gpu_ops *gops) 46 | { 47 | gops->fb.reset = fb_gk20a_reset; 48 | gops->fb.set_mmu_page_size = gk20a_fb_set_mmu_page_size; 49 | gk20a_init_uncompressed_kind_map(); 50 | gk20a_init_kind_attr(); 51 | } 52 | -------------------------------------------------------------------------------- /gk20a/fb_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | */ 13 | 14 | #ifndef FB_GK20A_H 15 | #define FB_GK20A_H 16 | struct gk20a; 17 | 18 | void gk20a_init_fb(struct gpu_ops *gops); 19 | #endif 20 | -------------------------------------------------------------------------------- /gk20a/fence_gk20a.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | */ 13 | 14 | #include "fence_gk20a.h" 15 | 16 | #include 17 | #include 18 | 19 | #include "gk20a.h" 20 | #include "semaphore_gk20a.h" 21 | #include "channel_gk20a.h" 22 | #include "sync_gk20a.h" 23 | 24 | #ifdef CONFIG_SYNC 25 | #include "../../../staging/android/sync.h" 26 | #endif 27 | 28 | #ifdef CONFIG_TEGRA_GK20A 29 | #include 30 | #include 31 | #endif 32 | 33 | struct gk20a_fence_ops { 34 | int (*wait)(struct gk20a_fence *, long timeout); 35 | bool (*is_expired)(struct gk20a_fence *); 36 | void *(*free)(struct kref *); 37 | }; 38 | 39 | static void gk20a_fence_free(struct kref *ref) 40 | { 41 | struct gk20a_fence *f = 42 | container_of(ref, struct gk20a_fence, ref); 43 | #ifdef CONFIG_SYNC 44 | if (f->sync_fence) 45 | sync_fence_put(f->sync_fence); 46 | #endif 47 | if (f->semaphore) 48 | gk20a_semaphore_put(f->semaphore); 49 | kfree(f); 50 | } 51 | 52 | void gk20a_fence_put(struct gk20a_fence *f) 53 | { 54 | if (f) 55 | kref_put(&f->ref, gk20a_fence_free); 56 | } 57 | 58 | struct gk20a_fence *gk20a_fence_get(struct gk20a_fence *f) 59 | { 60 | if (f) 61 | kref_get(&f->ref); 62 | return f; 63 | } 64 | 65 | int gk20a_fence_wait(struct gk20a_fence *f, int timeout) 66 | { 67 | return f->ops->wait(f, timeout); 68 | } 69 | 70 | bool gk20a_fence_is_expired(struct gk20a_fence *f) 71 | { 72 | return f->ops->is_expired(f); 73 | } 74 | 75 | int gk20a_fence_install_fd(struct gk20a_fence *f) 76 | { 77 | #ifdef CONFIG_SYNC 78 | int fd; 79 | 80 | if (!f->sync_fence) 81 | return -EINVAL; 82 | 83 | fd = get_unused_fd(); 84 | if (fd < 0) 85 | return fd; 86 | 87 | sync_fence_get(f->sync_fence); 88 | sync_fence_install(f->sync_fence, fd); 89 | return fd; 90 | #else 91 | return -ENODEV; 92 | #endif 93 | } 94 | 95 | static struct gk20a_fence *alloc_fence(const struct gk20a_fence_ops *ops, 96 | struct sync_fence *sync_fence, bool wfi) 97 | { 98 | struct gk20a_fence *f = kzalloc(sizeof(*f), GFP_KERNEL); 99 | if (!f) 100 | return NULL; 101 | kref_init(&f->ref); 102 | f->ops = ops; 103 | f->sync_fence = sync_fence; 104 | f->wfi = wfi; 105 | f->syncpt_id = -1; 106 | return f; 107 | } 108 | 109 | /* Fences that are backed by GPU semaphores: */ 110 | 111 | static int gk20a_semaphore_fence_wait(struct gk20a_fence *f, long timeout) 112 | { 113 | long remain; 114 | 115 | if (!gk20a_semaphore_is_acquired(f->semaphore)) 116 | return 0; 117 | 118 | remain = wait_event_interruptible_timeout( 119 | *f->semaphore_wq, 120 | !gk20a_semaphore_is_acquired(f->semaphore), 121 | timeout); 122 | if (remain == 0 && gk20a_semaphore_is_acquired(f->semaphore)) 123 | return -ETIMEDOUT; 124 | else if (remain < 0) 125 | return remain; 126 | return 0; 127 | } 128 | 129 | static bool gk20a_semaphore_fence_is_expired(struct gk20a_fence *f) 130 | { 131 | return !gk20a_semaphore_is_acquired(f->semaphore); 132 | } 133 | 134 | static const struct gk20a_fence_ops gk20a_semaphore_fence_ops = { 135 | .wait = &gk20a_semaphore_fence_wait, 136 | .is_expired = &gk20a_semaphore_fence_is_expired, 137 | }; 138 | 139 | /* This function takes ownership of the semaphore */ 140 | struct gk20a_fence *gk20a_fence_from_semaphore( 141 | struct sync_timeline *timeline, 142 | struct gk20a_semaphore *semaphore, 143 | wait_queue_head_t *semaphore_wq, 144 | struct sync_fence *dependency, 145 | bool wfi) 146 | { 147 | struct gk20a_fence *f; 148 | struct sync_fence *sync_fence = NULL; 149 | 150 | #ifdef CONFIG_SYNC 151 | sync_fence = gk20a_sync_fence_create(timeline, semaphore, 152 | dependency, "fence"); 153 | if (!sync_fence) 154 | return NULL; 155 | #endif 156 | 157 | f = alloc_fence(&gk20a_semaphore_fence_ops, sync_fence, wfi); 158 | if (!f) { 159 | #ifdef CONFIG_SYNC 160 | sync_fence_put(sync_fence); 161 | #endif 162 | return NULL; 163 | } 164 | 165 | f->semaphore = semaphore; 166 | f->semaphore_wq = semaphore_wq; 167 | return f; 168 | } 169 | 170 | #ifdef CONFIG_TEGRA_GK20A 171 | /* Fences that are backed by host1x syncpoints: */ 172 | 173 | static int gk20a_syncpt_fence_wait(struct gk20a_fence *f, long timeout) 174 | { 175 | return nvhost_syncpt_wait_timeout_ext( 176 | f->host1x_pdev, f->syncpt_id, f->syncpt_value, 177 | (u32)timeout, NULL, NULL); 178 | } 179 | 180 | static bool gk20a_syncpt_fence_is_expired(struct gk20a_fence *f) 181 | { 182 | return nvhost_syncpt_is_expired_ext(f->host1x_pdev, f->syncpt_id, 183 | f->syncpt_value); 184 | } 185 | 186 | static const struct gk20a_fence_ops gk20a_syncpt_fence_ops = { 187 | .wait = &gk20a_syncpt_fence_wait, 188 | .is_expired = &gk20a_syncpt_fence_is_expired, 189 | }; 190 | 191 | struct gk20a_fence *gk20a_fence_from_syncpt(struct platform_device *host1x_pdev, 192 | u32 id, u32 value, bool wfi) 193 | { 194 | struct gk20a_fence *f; 195 | struct sync_fence *sync_fence = NULL; 196 | 197 | #ifdef CONFIG_SYNC 198 | struct nvhost_ctrl_sync_fence_info pt = { 199 | .id = id, 200 | .thresh = value 201 | }; 202 | 203 | sync_fence = nvhost_sync_create_fence(host1x_pdev, &pt, 1, 204 | "fence"); 205 | if (IS_ERR(sync_fence)) 206 | return NULL; 207 | #endif 208 | 209 | f = alloc_fence(&gk20a_syncpt_fence_ops, sync_fence, wfi); 210 | if (!f) { 211 | #ifdef CONFIG_SYNC 212 | sync_fence_put(sync_fence); 213 | #endif 214 | return NULL; 215 | } 216 | f->host1x_pdev = host1x_pdev; 217 | f->syncpt_id = id; 218 | f->syncpt_value = value; 219 | return f; 220 | } 221 | #else 222 | struct gk20a_fence *gk20a_fence_from_syncpt(struct platform_device *host1x_pdev, 223 | u32 id, u32 value, bool wfi) 224 | { 225 | return NULL; 226 | } 227 | #endif 228 | -------------------------------------------------------------------------------- /gk20a/fence_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/fence_gk20a.h 3 | * 4 | * GK20A Fences 5 | * 6 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | */ 17 | #ifndef _GK20A_FENCE_H_ 18 | #define _GK20A_FENCE_H_ 19 | 20 | #include 21 | #include 22 | #include 23 | 24 | struct platform_device; 25 | struct sync_timeline; 26 | struct sync_fence; 27 | struct gk20a_semaphore; 28 | struct channel_gk20a; 29 | 30 | struct gk20a_fence_ops; 31 | 32 | struct gk20a_fence { 33 | /* Valid for all fence types: */ 34 | struct kref ref; 35 | bool wfi; 36 | struct sync_fence *sync_fence; 37 | const struct gk20a_fence_ops *ops; 38 | 39 | /* Valid for fences created from semaphores: */ 40 | struct gk20a_semaphore *semaphore; 41 | wait_queue_head_t *semaphore_wq; 42 | 43 | /* Valid for fences created from syncpoints: */ 44 | struct platform_device *host1x_pdev; 45 | u32 syncpt_id; 46 | u32 syncpt_value; 47 | }; 48 | 49 | /* Fences can be created from semaphores or syncpoint (id, value) pairs */ 50 | struct gk20a_fence *gk20a_fence_from_semaphore( 51 | struct sync_timeline *timeline, 52 | struct gk20a_semaphore *semaphore, 53 | wait_queue_head_t *semaphore_wq, 54 | struct sync_fence *dependency, 55 | bool wfi); 56 | 57 | struct gk20a_fence *gk20a_fence_from_syncpt( 58 | struct platform_device *host1x_pdev, 59 | u32 id, u32 value, bool wfi); 60 | 61 | /* Fence operations */ 62 | void gk20a_fence_put(struct gk20a_fence *f); 63 | struct gk20a_fence *gk20a_fence_get(struct gk20a_fence *f); 64 | int gk20a_fence_wait(struct gk20a_fence *f, int timeout); 65 | bool gk20a_fence_is_expired(struct gk20a_fence *f); 66 | int gk20a_fence_install_fd(struct gk20a_fence *f); 67 | 68 | #endif 69 | -------------------------------------------------------------------------------- /gk20a/fifo_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/fifo_gk20a.h 3 | * 4 | * GK20A graphics fifo (gr host) 5 | * 6 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | * 17 | * You should have received a copy of the GNU General Public License along with 18 | * this program; if not, write to the Free Software Foundation, Inc., 19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 | */ 21 | #ifndef __FIFO_GK20A_H__ 22 | #define __FIFO_GK20A_H__ 23 | 24 | #include "channel_gk20a.h" 25 | #include "tsg_gk20a.h" 26 | 27 | #define MAX_RUNLIST_BUFFERS 2 28 | 29 | /* generally corresponds to the "pbdma" engine */ 30 | 31 | struct fifo_runlist_info_gk20a { 32 | unsigned long *active_channels; 33 | unsigned long *active_tsgs; 34 | /* Each engine has its own SW and HW runlist buffer.*/ 35 | struct runlist_mem_desc mem[MAX_RUNLIST_BUFFERS]; 36 | u32 cur_buffer; 37 | u32 total_entries; 38 | bool stopped; 39 | bool support_tsg; 40 | struct mutex mutex; /* protect channel preempt and runlist upate */ 41 | }; 42 | 43 | /* so far gk20a has two engines: gr and ce2(gr_copy) */ 44 | enum { 45 | ENGINE_GR_GK20A = 0, 46 | ENGINE_CE2_GK20A = 1, 47 | ENGINE_INVAL_GK20A 48 | }; 49 | 50 | struct fifo_pbdma_exception_info_gk20a { 51 | u32 status_r; /* raw register value from hardware */ 52 | u32 id, next_id; 53 | u32 chan_status_v; /* raw value from hardware */ 54 | bool id_is_chid, next_id_is_chid; 55 | bool chsw_in_progress; 56 | }; 57 | 58 | struct fifo_engine_exception_info_gk20a { 59 | u32 status_r; /* raw register value from hardware */ 60 | u32 id, next_id; 61 | u32 ctx_status_v; /* raw value from hardware */ 62 | bool id_is_chid, next_id_is_chid; 63 | bool faulted, idle, ctxsw_in_progress; 64 | }; 65 | 66 | struct fifo_mmu_fault_info_gk20a { 67 | u32 fault_info_v; 68 | u32 fault_type_v; 69 | u32 engine_subid_v; 70 | u32 client_v; 71 | u32 fault_hi_v; 72 | u32 fault_lo_v; 73 | u64 inst_ptr; 74 | const char *fault_type_desc; 75 | const char *engine_subid_desc; 76 | const char *client_desc; 77 | }; 78 | 79 | struct fifo_engine_info_gk20a { 80 | u32 engine_id; 81 | u32 runlist_id; 82 | u32 intr_id; 83 | u32 reset_id; 84 | u32 pbdma_id; 85 | struct fifo_pbdma_exception_info_gk20a pbdma_exception_info; 86 | struct fifo_engine_exception_info_gk20a engine_exception_info; 87 | struct fifo_mmu_fault_info_gk20a mmu_fault_info; 88 | 89 | }; 90 | 91 | struct fifo_gk20a { 92 | struct gk20a *g; 93 | int num_channels; 94 | 95 | int num_pbdma; 96 | u32 *pbdma_map; 97 | 98 | struct fifo_engine_info_gk20a *engine_info; 99 | u32 max_engines; 100 | u32 num_engines; 101 | 102 | struct fifo_runlist_info_gk20a *runlist_info; 103 | u32 max_runlists; 104 | 105 | struct userd_desc userd; 106 | u32 userd_entry_size; 107 | u32 userd_total_size; 108 | 109 | struct channel_gk20a *channel; 110 | struct mutex ch_inuse_mutex; /* protect unused chid look up */ 111 | 112 | struct tsg_gk20a *tsg; 113 | struct mutex tsg_inuse_mutex; 114 | 115 | void (*remove_support)(struct fifo_gk20a *); 116 | bool sw_ready; 117 | struct { 118 | /* share info between isrs and non-isr code */ 119 | struct { 120 | struct mutex mutex; 121 | } isr; 122 | struct { 123 | u32 device_fatal_0; 124 | u32 channel_fatal_0; 125 | u32 restartable_0; 126 | } pbdma; 127 | struct { 128 | 129 | } engine; 130 | 131 | 132 | } intr; 133 | 134 | u32 mmu_fault_engines; 135 | bool deferred_reset_pending; 136 | struct mutex deferred_reset_mutex; 137 | }; 138 | 139 | int gk20a_init_fifo_support(struct gk20a *g); 140 | 141 | void gk20a_fifo_isr(struct gk20a *g); 142 | void gk20a_fifo_nonstall_isr(struct gk20a *g); 143 | 144 | int gk20a_fifo_preempt_channel(struct gk20a *g, u32 hw_chid); 145 | int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); 146 | int gk20a_fifo_preempt(struct gk20a *g, struct channel_gk20a *ch); 147 | 148 | int gk20a_fifo_enable_engine_activity(struct gk20a *g, 149 | struct fifo_engine_info_gk20a *eng_info); 150 | int gk20a_fifo_disable_engine_activity(struct gk20a *g, 151 | struct fifo_engine_info_gk20a *eng_info, 152 | bool wait_for_idle); 153 | u32 gk20a_fifo_engines_on_ch(struct gk20a *g, u32 hw_chid); 154 | 155 | int gk20a_fifo_update_runlist(struct gk20a *g, u32 engine_id, u32 hw_chid, 156 | bool add, bool wait_for_finish); 157 | 158 | int gk20a_fifo_suspend(struct gk20a *g); 159 | 160 | bool gk20a_fifo_mmu_fault_pending(struct gk20a *g); 161 | void gk20a_fifo_recover(struct gk20a *g, u32 engine_ids, bool verbose); 162 | void gk20a_fifo_recover_ch(struct gk20a *g, u32 hw_chid, bool verbose); 163 | void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose); 164 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose); 165 | int gk20a_init_fifo_reset_enable_hw(struct gk20a *g); 166 | void gk20a_init_fifo(struct gpu_ops *gops); 167 | 168 | void fifo_gk20a_finish_mmu_fault_handling(struct gk20a *g, 169 | unsigned long fault_id); 170 | int gk20a_fifo_wait_engine_idle(struct gk20a *g); 171 | u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g); 172 | #endif /*__GR_GK20A_H__*/ 173 | -------------------------------------------------------------------------------- /gk20a/gk20a_allocator.c: -------------------------------------------------------------------------------- 1 | /* 2 | * gk20a allocator 3 | * 4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | 19 | #include "gk20a_allocator.h" 20 | 21 | /* init allocator struct */ 22 | int gk20a_allocator_init(struct gk20a_allocator *allocator, 23 | const char *name, u32 start, u32 len) 24 | { 25 | memset(allocator, 0, sizeof(struct gk20a_allocator)); 26 | 27 | strncpy(allocator->name, name, 32); 28 | 29 | allocator->base = start; 30 | allocator->limit = start + len - 1; 31 | 32 | allocator->bitmap = kzalloc(BITS_TO_LONGS(len) * sizeof(long), 33 | GFP_KERNEL); 34 | if (!allocator->bitmap) 35 | return -ENOMEM; 36 | 37 | allocator_dbg(allocator, "%s : base %d, limit %d", 38 | allocator->name, allocator->base); 39 | 40 | init_rwsem(&allocator->rw_sema); 41 | 42 | allocator->alloc = gk20a_allocator_block_alloc; 43 | allocator->free = gk20a_allocator_block_free; 44 | 45 | return 0; 46 | } 47 | 48 | /* destroy allocator, free all remaining blocks if any */ 49 | void gk20a_allocator_destroy(struct gk20a_allocator *allocator) 50 | { 51 | down_write(&allocator->rw_sema); 52 | 53 | kfree(allocator->bitmap); 54 | 55 | memset(allocator, 0, sizeof(struct gk20a_allocator)); 56 | } 57 | 58 | /* 59 | * *addr != ~0 for fixed address allocation. if *addr == 0, base addr is 60 | * returned to caller in *addr. 61 | * 62 | * contiguous allocation, which allocates one block of 63 | * contiguous address. 64 | */ 65 | int gk20a_allocator_block_alloc(struct gk20a_allocator *allocator, 66 | u32 *addr, u32 len, u32 align) 67 | { 68 | unsigned long _addr; 69 | 70 | allocator_dbg(allocator, "[in] addr %d, len %d", *addr, len); 71 | 72 | if ((*addr != 0 && *addr < allocator->base) || /* check addr range */ 73 | *addr + len > allocator->limit || /* check addr range */ 74 | *addr & (align - 1) || /* check addr alignment */ 75 | len == 0) /* check len */ 76 | return -EINVAL; 77 | 78 | len = ALIGN(len, align); 79 | if (!len) 80 | return -ENOMEM; 81 | 82 | down_write(&allocator->rw_sema); 83 | 84 | _addr = bitmap_find_next_zero_area(allocator->bitmap, 85 | allocator->limit - allocator->base + 1, 86 | *addr ? (*addr - allocator->base) : 0, 87 | len, 88 | align - 1); 89 | if ((_addr > allocator->limit - allocator->base + 1) || 90 | (*addr && *addr != (_addr + allocator->base))) { 91 | up_write(&allocator->rw_sema); 92 | return -ENOMEM; 93 | } 94 | 95 | bitmap_set(allocator->bitmap, _addr, len); 96 | *addr = allocator->base + _addr; 97 | 98 | up_write(&allocator->rw_sema); 99 | 100 | allocator_dbg(allocator, "[out] addr %d, len %d", *addr, len); 101 | 102 | return 0; 103 | } 104 | 105 | /* free all blocks between start and end */ 106 | int gk20a_allocator_block_free(struct gk20a_allocator *allocator, 107 | u32 addr, u32 len, u32 align) 108 | { 109 | allocator_dbg(allocator, "[in] addr %d, len %d", addr, len); 110 | 111 | if (addr + len > allocator->limit || /* check addr range */ 112 | addr < allocator->base || 113 | addr & (align - 1)) /* check addr alignment */ 114 | return -EINVAL; 115 | 116 | len = ALIGN(len, align); 117 | if (!len) 118 | return -EINVAL; 119 | 120 | down_write(&allocator->rw_sema); 121 | bitmap_clear(allocator->bitmap, addr - allocator->base, len); 122 | up_write(&allocator->rw_sema); 123 | 124 | allocator_dbg(allocator, "[out] addr %d, len %d", addr, len); 125 | 126 | return 0; 127 | } 128 | -------------------------------------------------------------------------------- /gk20a/gk20a_allocator.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | 17 | #ifndef GK20A_ALLOCATOR_H 18 | #define GK20A_ALLOCATOR_H 19 | 20 | #include 21 | #include 22 | #include 23 | 24 | /* #define ALLOCATOR_DEBUG */ 25 | 26 | /* main struct */ 27 | struct gk20a_allocator { 28 | 29 | char name[32]; /* name for allocator */ 30 | struct rb_root rb_root; /* rb tree root for blocks */ 31 | 32 | u32 base; /* min value of this linear space */ 33 | u32 limit; /* max value = limit - 1 */ 34 | 35 | unsigned long *bitmap; /* bitmap */ 36 | 37 | struct gk20a_alloc_block *block_first; /* first block in list */ 38 | struct gk20a_alloc_block *block_recent; /* last visited block */ 39 | 40 | u32 first_free_addr; /* first free addr, non-contigous 41 | allocation preferred start, 42 | in order to pick up small holes */ 43 | u32 last_free_addr; /* last free addr, contiguous 44 | allocation preferred start */ 45 | u32 cached_hole_size; /* max free hole size up to 46 | last_free_addr */ 47 | u32 block_count; /* number of blocks */ 48 | 49 | struct rw_semaphore rw_sema; /* lock */ 50 | struct kmem_cache *block_cache; /* slab cache */ 51 | 52 | /* if enabled, constrain to [base, limit) */ 53 | struct { 54 | bool enable; 55 | u32 base; 56 | u32 limit; 57 | } constraint; 58 | 59 | int (*alloc)(struct gk20a_allocator *allocator, 60 | u32 *addr, u32 len, u32 align); 61 | int (*free)(struct gk20a_allocator *allocator, 62 | u32 addr, u32 len, u32 align); 63 | 64 | }; 65 | 66 | int gk20a_allocator_init(struct gk20a_allocator *allocator, 67 | const char *name, u32 base, u32 size); 68 | void gk20a_allocator_destroy(struct gk20a_allocator *allocator); 69 | 70 | int gk20a_allocator_block_alloc(struct gk20a_allocator *allocator, 71 | u32 *addr, u32 len, u32 align); 72 | 73 | int gk20a_allocator_block_free(struct gk20a_allocator *allocator, 74 | u32 addr, u32 len, u32 align); 75 | 76 | #if defined(ALLOCATOR_DEBUG) 77 | 78 | #define allocator_dbg(alloctor, format, arg...) \ 79 | do { \ 80 | if (1) \ 81 | pr_debug("gk20a_allocator (%s) %s: " format "\n",\ 82 | alloctor->name, __func__, ##arg);\ 83 | } while (0) 84 | 85 | #else /* ALLOCATOR_DEBUG */ 86 | 87 | #define allocator_dbg(format, arg...) 88 | 89 | #endif /* ALLOCATOR_DEBUG */ 90 | 91 | #endif /* GK20A_ALLOCATOR_H */ 92 | -------------------------------------------------------------------------------- /gk20a/gk20a_gating_reglist.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/gk20a_gating_reglist.h 3 | * 4 | * Copyright (c) 2012-2014, NVIDIA Corporation. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; either version 2 of the License. 9 | * 10 | * This program is distributed in the hope that it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License along 16 | * with this program; if not, write to the Free Software Foundation, Inc., 17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 18 | * 19 | * This file is autogenerated. Do not edit. 20 | */ 21 | 22 | #include "gk20a.h" 23 | 24 | void gr_gk20a_slcg_gr_load_gating_prod(struct gk20a *g, 25 | bool prod); 26 | 27 | void gr_gk20a_slcg_perf_load_gating_prod(struct gk20a *g, 28 | bool prod); 29 | 30 | void ltc_gk20a_slcg_ltc_load_gating_prod(struct gk20a *g, 31 | bool prod); 32 | 33 | void gr_gk20a_blcg_gr_load_gating_prod(struct gk20a *g, 34 | bool prod); 35 | 36 | void gr_gk20a_pg_gr_load_gating_prod(struct gk20a *g, 37 | bool prod); 38 | 39 | void gr_gk20a_slcg_therm_load_gating_prod(struct gk20a *g, 40 | bool prod); 41 | 42 | 43 | -------------------------------------------------------------------------------- /gk20a/gk20a_scale.h: -------------------------------------------------------------------------------- 1 | /* 2 | * gk20a clock scaling profile 3 | * 4 | * Copyright (c) 2013-2014, NVIDIA Corporation. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | 19 | #ifndef GK20A_SCALE_H 20 | #define GK20A_SCALE_H 21 | 22 | #include 23 | 24 | struct platform_device; 25 | struct clk; 26 | 27 | struct gk20a_scale_profile { 28 | struct platform_device *pdev; 29 | ktime_t last_event_time; 30 | struct devfreq_dev_profile devfreq_profile; 31 | struct devfreq_dev_status dev_stat; 32 | struct notifier_block qos_notify_block; 33 | void *private_data; 34 | }; 35 | 36 | /* Initialization and de-initialization for module */ 37 | void gk20a_scale_init(struct platform_device *); 38 | void gk20a_scale_hw_init(struct platform_device *pdev); 39 | 40 | #ifdef CONFIG_GK20A_DEVFREQ 41 | /* 42 | * call when performing submit to notify scaling mechanism that the module is 43 | * in use 44 | */ 45 | void gk20a_scale_notify_busy(struct platform_device *); 46 | void gk20a_scale_notify_idle(struct platform_device *); 47 | 48 | void gk20a_scale_suspend(struct platform_device *); 49 | void gk20a_scale_resume(struct platform_device *); 50 | #else 51 | static inline void gk20a_scale_notify_busy(struct platform_device *pdev) {} 52 | static inline void gk20a_scale_notify_idle(struct platform_device *pdev) {} 53 | static inline void gk20a_scale_suspend(struct platform_device *pdev) {} 54 | static inline void gk20a_scale_resume(struct platform_device *pdev) {} 55 | #endif 56 | 57 | #endif 58 | -------------------------------------------------------------------------------- /gk20a/gr_ctx_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * GK20A Graphics Context 3 | * 4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | #ifndef __GR_CTX_GK20A_H__ 19 | #define __GR_CTX_GK20A_H__ 20 | 21 | /* production netlist, one and only one from below */ 22 | /*#undef GK20A_NETLIST_IMAGE_FW_NAME*/ 23 | #define GK20A_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_B 24 | 25 | /* emulation netlists, match majorV with HW */ 26 | #define GK20A_NETLIST_IMAGE_A "NETA_img.bin" 27 | #define GK20A_NETLIST_IMAGE_B "NETB_img.bin" 28 | #define GK20A_NETLIST_IMAGE_C "NETC_img.bin" 29 | #define GK20A_NETLIST_IMAGE_D "NETD_img.bin" 30 | 31 | union __max_name { 32 | #ifdef GK20A_NETLIST_IMAGE_A 33 | char __name_a[sizeof(GK20A_NETLIST_IMAGE_A)]; 34 | #endif 35 | #ifdef GK20A_NETLIST_IMAGE_B 36 | char __name_b[sizeof(GK20A_NETLIST_IMAGE_B)]; 37 | #endif 38 | #ifdef GK20A_NETLIST_IMAGE_C 39 | char __name_c[sizeof(GK20A_NETLIST_IMAGE_C)]; 40 | #endif 41 | #ifdef GK20A_NETLIST_IMAGE_D 42 | char __name_d[sizeof(GK20A_NETLIST_IMAGE_D)]; 43 | #endif 44 | }; 45 | 46 | #define MAX_NETLIST_NAME sizeof(union __max_name) 47 | 48 | /* index for emulation netlists */ 49 | #define NETLIST_FINAL -1 50 | #define NETLIST_SLOT_A 0 51 | #define NETLIST_SLOT_B 1 52 | #define NETLIST_SLOT_C 2 53 | #define NETLIST_SLOT_D 3 54 | #define MAX_NETLIST 4 55 | 56 | /* netlist regions */ 57 | #define NETLIST_REGIONID_FECS_UCODE_DATA 0 58 | #define NETLIST_REGIONID_FECS_UCODE_INST 1 59 | #define NETLIST_REGIONID_GPCCS_UCODE_DATA 2 60 | #define NETLIST_REGIONID_GPCCS_UCODE_INST 3 61 | #define NETLIST_REGIONID_SW_BUNDLE_INIT 4 62 | #define NETLIST_REGIONID_SW_CTX_LOAD 5 63 | #define NETLIST_REGIONID_SW_NON_CTX_LOAD 6 64 | #define NETLIST_REGIONID_SW_METHOD_INIT 7 65 | #define NETLIST_REGIONID_CTXREG_SYS 8 66 | #define NETLIST_REGIONID_CTXREG_GPC 9 67 | #define NETLIST_REGIONID_CTXREG_TPC 10 68 | #define NETLIST_REGIONID_CTXREG_ZCULL_GPC 11 69 | #define NETLIST_REGIONID_CTXREG_PM_SYS 12 70 | #define NETLIST_REGIONID_CTXREG_PM_GPC 13 71 | #define NETLIST_REGIONID_CTXREG_PM_TPC 14 72 | #define NETLIST_REGIONID_MAJORV 15 73 | #define NETLIST_REGIONID_BUFFER_SIZE 16 74 | #define NETLIST_REGIONID_CTXSW_REG_BASE_INDEX 17 75 | #define NETLIST_REGIONID_NETLIST_NUM 18 76 | #define NETLIST_REGIONID_CTXREG_PPC 19 77 | #define NETLIST_REGIONID_CTXREG_PMPPC 20 78 | 79 | struct netlist_region { 80 | u32 region_id; 81 | u32 data_size; 82 | u32 data_offset; 83 | }; 84 | 85 | struct netlist_image_header { 86 | u32 version; 87 | u32 regions; 88 | }; 89 | 90 | struct netlist_image { 91 | struct netlist_image_header header; 92 | struct netlist_region regions[1]; 93 | }; 94 | 95 | struct av_gk20a { 96 | u32 addr; 97 | u32 value; 98 | }; 99 | struct aiv_gk20a { 100 | u32 addr; 101 | u32 index; 102 | u32 value; 103 | }; 104 | struct aiv_list_gk20a { 105 | struct aiv_gk20a *l; 106 | u32 count; 107 | }; 108 | struct av_list_gk20a { 109 | struct av_gk20a *l; 110 | u32 count; 111 | }; 112 | struct u32_list_gk20a { 113 | u32 *l; 114 | u32 count; 115 | }; 116 | 117 | static inline 118 | struct av_gk20a *alloc_av_list_gk20a(struct av_list_gk20a *avl) 119 | { 120 | avl->l = kzalloc(avl->count * sizeof(*avl->l), GFP_KERNEL); 121 | return avl->l; 122 | } 123 | 124 | static inline 125 | struct aiv_gk20a *alloc_aiv_list_gk20a(struct aiv_list_gk20a *aivl) 126 | { 127 | aivl->l = kzalloc(aivl->count * sizeof(*aivl->l), GFP_KERNEL); 128 | return aivl->l; 129 | } 130 | 131 | static inline 132 | u32 *alloc_u32_list_gk20a(struct u32_list_gk20a *u32l) 133 | { 134 | u32l->l = kzalloc(u32l->count * sizeof(*u32l->l), GFP_KERNEL); 135 | return u32l->l; 136 | } 137 | 138 | struct gr_ucode_gk20a { 139 | struct { 140 | struct u32_list_gk20a inst; 141 | struct u32_list_gk20a data; 142 | } gpccs, fecs; 143 | }; 144 | 145 | /* main entry for grctx loading */ 146 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr); 147 | 148 | struct gpu_ops; 149 | void gk20a_init_gr_ctx(struct gpu_ops *gops); 150 | 151 | #endif /*__GR_CTX_GK20A_H__*/ 152 | -------------------------------------------------------------------------------- /gk20a/gr_pri_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * GK20A Graphics Context Pri Register Addressing 3 | * 4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | #ifndef GR_PRI_GK20A_H 19 | #define GR_PRI_GK20A_H 20 | 21 | /* 22 | * These convenience macros are generally for use in the management/modificaiton 23 | * of the context state store for gr/compute contexts. 24 | */ 25 | 26 | /* 27 | * GPC pri addressing 28 | */ 29 | static inline u32 pri_gpccs_addr_width(void) 30 | { 31 | return 15; /*from where?*/ 32 | } 33 | static inline u32 pri_gpccs_addr_mask(u32 addr) 34 | { 35 | return addr & ((1 << pri_gpccs_addr_width()) - 1); 36 | } 37 | static inline u32 pri_gpc_addr(u32 addr, u32 gpc) 38 | { 39 | return proj_gpc_base_v() + (gpc * proj_gpc_stride_v()) + addr; 40 | } 41 | static inline bool pri_is_gpc_addr_shared(u32 addr) 42 | { 43 | return (addr >= proj_gpc_shared_base_v()) && 44 | (addr < proj_gpc_shared_base_v() + proj_gpc_stride_v()); 45 | } 46 | static inline bool pri_is_gpc_addr(u32 addr) 47 | { 48 | return ((addr >= proj_gpc_base_v()) && 49 | (addr < proj_gpc_base_v() + 50 | proj_scal_litter_num_gpcs_v() * proj_gpc_stride_v())) || 51 | pri_is_gpc_addr_shared(addr); 52 | } 53 | static inline u32 pri_get_gpc_num(u32 addr) 54 | { 55 | u32 i, start; 56 | u32 num_gpcs = proj_scal_litter_num_gpcs_v(); 57 | 58 | for (i = 0; i < num_gpcs; i++) { 59 | start = proj_gpc_base_v() + (i * proj_gpc_stride_v()); 60 | if ((addr >= start) && (addr < (start + proj_gpc_stride_v()))) 61 | return i; 62 | } 63 | return 0; 64 | } 65 | /* 66 | * TPC pri addressing 67 | */ 68 | static inline u32 pri_tpccs_addr_width(void) 69 | { 70 | return 11; /* from where? */ 71 | } 72 | static inline u32 pri_tpccs_addr_mask(u32 addr) 73 | { 74 | return addr & ((1 << pri_tpccs_addr_width()) - 1); 75 | } 76 | static inline u32 pri_tpc_addr(u32 addr, u32 gpc, u32 tpc) 77 | { 78 | return proj_gpc_base_v() + (gpc * proj_gpc_stride_v()) + 79 | proj_tpc_in_gpc_base_v() + (tpc * proj_tpc_in_gpc_stride_v()) + 80 | addr; 81 | } 82 | static inline bool pri_is_tpc_addr_shared(u32 addr) 83 | { 84 | return (addr >= proj_tpc_in_gpc_shared_base_v()) && 85 | (addr < (proj_tpc_in_gpc_shared_base_v() + 86 | proj_tpc_in_gpc_stride_v())); 87 | } 88 | 89 | /* 90 | * BE pri addressing 91 | */ 92 | static inline u32 pri_becs_addr_width(void) 93 | { 94 | return 10;/* from where? */ 95 | } 96 | static inline u32 pri_becs_addr_mask(u32 addr) 97 | { 98 | return addr & ((1 << pri_becs_addr_width()) - 1); 99 | } 100 | static inline bool pri_is_be_addr_shared(u32 addr) 101 | { 102 | return (addr >= proj_rop_shared_base_v()) && 103 | (addr < proj_rop_shared_base_v() + proj_rop_stride_v()); 104 | } 105 | static inline u32 pri_be_shared_addr(u32 addr) 106 | { 107 | return proj_rop_shared_base_v() + pri_becs_addr_mask(addr); 108 | } 109 | static inline bool pri_is_be_addr(u32 addr) 110 | { 111 | return ((addr >= proj_rop_base_v()) && 112 | (addr < proj_rop_base_v()+proj_scal_litter_num_fbps_v() * proj_rop_stride_v())) || 113 | pri_is_be_addr_shared(addr); 114 | } 115 | 116 | static inline u32 pri_get_be_num(u32 addr) 117 | { 118 | u32 i, start; 119 | u32 num_fbps = proj_scal_litter_num_fbps_v(); 120 | for (i = 0; i < num_fbps; i++) { 121 | start = proj_rop_base_v() + (i * proj_rop_stride_v()); 122 | if ((addr >= start) && (addr < (start + proj_rop_stride_v()))) 123 | return i; 124 | } 125 | return 0; 126 | } 127 | 128 | /* 129 | * PPC pri addressing 130 | */ 131 | static inline u32 pri_ppccs_addr_width(void) 132 | { 133 | return 9; /* from where? */ 134 | } 135 | static inline u32 pri_ppccs_addr_mask(u32 addr) 136 | { 137 | return addr & ((1 << pri_ppccs_addr_width()) - 1); 138 | } 139 | static inline u32 pri_ppc_addr(u32 addr, u32 gpc, u32 ppc) 140 | { 141 | return proj_gpc_base_v() + (gpc * proj_gpc_stride_v()) + 142 | proj_ppc_in_gpc_base_v() + (ppc * proj_ppc_in_gpc_stride_v()) + addr; 143 | } 144 | 145 | enum ctxsw_addr_type { 146 | CTXSW_ADDR_TYPE_SYS = 0, 147 | CTXSW_ADDR_TYPE_GPC = 1, 148 | CTXSW_ADDR_TYPE_TPC = 2, 149 | CTXSW_ADDR_TYPE_BE = 3, 150 | CTXSW_ADDR_TYPE_PPC = 4 151 | }; 152 | 153 | #define PRI_BROADCAST_FLAGS_NONE 0 154 | #define PRI_BROADCAST_FLAGS_GPC BIT(0) 155 | #define PRI_BROADCAST_FLAGS_TPC BIT(1) 156 | #define PRI_BROADCAST_FLAGS_BE BIT(2) 157 | #define PRI_BROADCAST_FLAGS_PPC BIT(3) 158 | 159 | #endif /* GR_PRI_GK20A_H */ 160 | -------------------------------------------------------------------------------- /gk20a/hal.c: -------------------------------------------------------------------------------- 1 | /* 2 | * NVIDIA GPU HAL interface. 3 | * 4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | */ 15 | 16 | #include "gk20a.h" 17 | #include "hal_gk20a.h" 18 | 19 | int gpu_init_hal(struct gk20a *g) 20 | { 21 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; 22 | switch (ver) { 23 | case GK20A_GPUID_GK20A: 24 | gk20a_dbg_info("gk20a detected"); 25 | gk20a_init_hal(g); 26 | break; 27 | default: 28 | gk20a_err(&g->dev->dev, "no support for %x", ver); 29 | return -ENODEV; 30 | } 31 | 32 | return 0; 33 | } 34 | -------------------------------------------------------------------------------- /gk20a/hal.h: -------------------------------------------------------------------------------- 1 | /* 2 | * NVIDIA GPU Hardware Abstraction Layer functions definitions. 3 | * 4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | */ 15 | 16 | #ifndef __HAL_GPU__ 17 | #define __HAL_GPU__ 18 | 19 | #include 20 | 21 | struct gk20a; 22 | 23 | int gpu_init_hal(struct gk20a *g); 24 | 25 | #endif /* __HAL_GPU__ */ 26 | -------------------------------------------------------------------------------- /gk20a/hal_gk20a.c: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/hal_gk20a.c 3 | * 4 | * GK20A Tegra HAL interface. 5 | * 6 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | */ 17 | 18 | #include "hal_gk20a.h" 19 | #include "ltc_gk20a.h" 20 | #include "fb_gk20a.h" 21 | #include "gk20a.h" 22 | #include "gk20a_gating_reglist.h" 23 | #include "channel_gk20a.h" 24 | #include "gr_ctx_gk20a.h" 25 | #include "mm_gk20a.h" 26 | #include "mc_gk20a.h" 27 | #include "pmu_gk20a.h" 28 | #include "clk_gk20a.h" 29 | #include "regops_gk20a.h" 30 | 31 | static struct gpu_ops gk20a_ops = { 32 | .clock_gating = { 33 | .slcg_gr_load_gating_prod = 34 | gr_gk20a_slcg_gr_load_gating_prod, 35 | .slcg_perf_load_gating_prod = 36 | gr_gk20a_slcg_perf_load_gating_prod, 37 | .slcg_ltc_load_gating_prod = 38 | ltc_gk20a_slcg_ltc_load_gating_prod, 39 | .blcg_gr_load_gating_prod = 40 | gr_gk20a_blcg_gr_load_gating_prod, 41 | .pg_gr_load_gating_prod = 42 | gr_gk20a_pg_gr_load_gating_prod, 43 | .slcg_therm_load_gating_prod = 44 | gr_gk20a_slcg_therm_load_gating_prod, 45 | } 46 | }; 47 | 48 | int gk20a_init_hal(struct gk20a *g) 49 | { 50 | struct gpu_ops *gops = &g->ops; 51 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; 52 | 53 | *gops = gk20a_ops; 54 | gops->privsecurity = 0; 55 | gk20a_init_mc(gops); 56 | gk20a_init_ltc(gops); 57 | gk20a_init_gr_ops(gops); 58 | gk20a_init_fb(gops); 59 | gk20a_init_fifo(gops); 60 | gk20a_init_gr_ctx(gops); 61 | gk20a_init_mm(gops); 62 | gk20a_init_pmu_ops(gops); 63 | gk20a_init_clk_ops(gops); 64 | gk20a_init_regops(gops); 65 | gops->name = "gk20a"; 66 | 67 | c->twod_class = FERMI_TWOD_A; 68 | c->threed_class = KEPLER_C; 69 | c->compute_class = KEPLER_COMPUTE_A; 70 | c->gpfifo_class = KEPLER_CHANNEL_GPFIFO_C; 71 | c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_A; 72 | c->dma_copy_class = KEPLER_DMA_COPY_A; 73 | 74 | return 0; 75 | } 76 | -------------------------------------------------------------------------------- /gk20a/hal_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/hal_gk20a.h 3 | * 4 | * GK20A Hardware Abstraction Layer functions definitions. 5 | * 6 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | */ 17 | 18 | #ifndef __HAL_GK20A__ 19 | #define __HAL_GK20A__ 20 | 21 | #include 22 | 23 | struct gk20a; 24 | 25 | int gk20a_init_hal(struct gk20a *g); 26 | 27 | #endif /* __HAL_GK20A__ */ 28 | -------------------------------------------------------------------------------- /gk20a/hw_bus_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_bus_gk20a_h_ 51 | #define _hw_bus_gk20a_h_ 52 | 53 | static inline u32 bus_bar1_block_r(void) 54 | { 55 | return 0x00001704; 56 | } 57 | static inline u32 bus_bar1_block_ptr_f(u32 v) 58 | { 59 | return (v & 0xfffffff) << 0; 60 | } 61 | static inline u32 bus_bar1_block_target_vid_mem_f(void) 62 | { 63 | return 0x0; 64 | } 65 | static inline u32 bus_bar1_block_mode_virtual_f(void) 66 | { 67 | return 0x80000000; 68 | } 69 | static inline u32 bus_bar1_block_ptr_shift_v(void) 70 | { 71 | return 0x0000000c; 72 | } 73 | static inline u32 bus_intr_0_r(void) 74 | { 75 | return 0x00001100; 76 | } 77 | static inline u32 bus_intr_0_pri_squash_m(void) 78 | { 79 | return 0x1 << 1; 80 | } 81 | static inline u32 bus_intr_0_pri_fecserr_m(void) 82 | { 83 | return 0x1 << 2; 84 | } 85 | static inline u32 bus_intr_0_pri_timeout_m(void) 86 | { 87 | return 0x1 << 3; 88 | } 89 | static inline u32 bus_intr_en_0_r(void) 90 | { 91 | return 0x00001140; 92 | } 93 | static inline u32 bus_intr_en_0_pri_squash_m(void) 94 | { 95 | return 0x1 << 1; 96 | } 97 | static inline u32 bus_intr_en_0_pri_fecserr_m(void) 98 | { 99 | return 0x1 << 2; 100 | } 101 | static inline u32 bus_intr_en_0_pri_timeout_m(void) 102 | { 103 | return 0x1 << 3; 104 | } 105 | #endif 106 | -------------------------------------------------------------------------------- /gk20a/hw_ccsr_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_ccsr_gk20a_h_ 51 | #define _hw_ccsr_gk20a_h_ 52 | 53 | static inline u32 ccsr_channel_inst_r(u32 i) 54 | { 55 | return 0x00800000 + i*8; 56 | } 57 | static inline u32 ccsr_channel_inst__size_1_v(void) 58 | { 59 | return 0x00000080; 60 | } 61 | static inline u32 ccsr_channel_inst_ptr_f(u32 v) 62 | { 63 | return (v & 0xfffffff) << 0; 64 | } 65 | static inline u32 ccsr_channel_inst_target_vid_mem_f(void) 66 | { 67 | return 0x0; 68 | } 69 | static inline u32 ccsr_channel_inst_bind_false_f(void) 70 | { 71 | return 0x0; 72 | } 73 | static inline u32 ccsr_channel_inst_bind_true_f(void) 74 | { 75 | return 0x80000000; 76 | } 77 | static inline u32 ccsr_channel_r(u32 i) 78 | { 79 | return 0x00800004 + i*8; 80 | } 81 | static inline u32 ccsr_channel__size_1_v(void) 82 | { 83 | return 0x00000080; 84 | } 85 | static inline u32 ccsr_channel_enable_v(u32 r) 86 | { 87 | return (r >> 0) & 0x1; 88 | } 89 | static inline u32 ccsr_channel_enable_set_f(u32 v) 90 | { 91 | return (v & 0x1) << 10; 92 | } 93 | static inline u32 ccsr_channel_enable_set_true_f(void) 94 | { 95 | return 0x400; 96 | } 97 | static inline u32 ccsr_channel_enable_clr_true_f(void) 98 | { 99 | return 0x800; 100 | } 101 | static inline u32 ccsr_channel_runlist_f(u32 v) 102 | { 103 | return (v & 0xf) << 16; 104 | } 105 | static inline u32 ccsr_channel_status_v(u32 r) 106 | { 107 | return (r >> 24) & 0xf; 108 | } 109 | static inline u32 ccsr_channel_busy_v(u32 r) 110 | { 111 | return (r >> 28) & 0x1; 112 | } 113 | #endif 114 | -------------------------------------------------------------------------------- /gk20a/hw_ctxsw_prog_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_ctxsw_prog_gk20a_h_ 51 | #define _hw_ctxsw_prog_gk20a_h_ 52 | 53 | static inline u32 ctxsw_prog_fecs_header_v(void) 54 | { 55 | return 0x00000100; 56 | } 57 | static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) 58 | { 59 | return 0x00000008; 60 | } 61 | static inline u32 ctxsw_prog_main_image_patch_count_o(void) 62 | { 63 | return 0x00000010; 64 | } 65 | static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) 66 | { 67 | return 0x00000014; 68 | } 69 | static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) 70 | { 71 | return 0x00000018; 72 | } 73 | static inline u32 ctxsw_prog_main_image_zcull_o(void) 74 | { 75 | return 0x0000001c; 76 | } 77 | static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) 78 | { 79 | return 0x00000001; 80 | } 81 | static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) 82 | { 83 | return 0x00000002; 84 | } 85 | static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) 86 | { 87 | return 0x00000020; 88 | } 89 | static inline u32 ctxsw_prog_main_image_pm_o(void) 90 | { 91 | return 0x00000028; 92 | } 93 | static inline u32 ctxsw_prog_main_image_pm_mode_m(void) 94 | { 95 | return 0x7 << 0; 96 | } 97 | static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) 98 | { 99 | return 0x0; 100 | } 101 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) 102 | { 103 | return 0x7 << 3; 104 | } 105 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) 106 | { 107 | return 0x8; 108 | } 109 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) 110 | { 111 | return 0x0; 112 | } 113 | static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) 114 | { 115 | return 0x0000002c; 116 | } 117 | static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) 118 | { 119 | return 0x000000f4; 120 | } 121 | static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) 122 | { 123 | return 0x000000f8; 124 | } 125 | static inline u32 ctxsw_prog_main_image_magic_value_o(void) 126 | { 127 | return 0x000000fc; 128 | } 129 | static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) 130 | { 131 | return 0x600dc0de; 132 | } 133 | static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) 134 | { 135 | return 0x0000000c; 136 | } 137 | static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) 138 | { 139 | return (r >> 0) & 0xffff; 140 | } 141 | static inline u32 ctxsw_prog_local_image_ppc_info_o(void) 142 | { 143 | return 0x000000f4; 144 | } 145 | static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) 146 | { 147 | return (r >> 0) & 0xffff; 148 | } 149 | static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) 150 | { 151 | return (r >> 16) & 0xffff; 152 | } 153 | static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) 154 | { 155 | return 0x000000f8; 156 | } 157 | static inline u32 ctxsw_prog_local_magic_value_o(void) 158 | { 159 | return 0x000000fc; 160 | } 161 | static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) 162 | { 163 | return 0xad0becab; 164 | } 165 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) 166 | { 167 | return 0x000000ec; 168 | } 169 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) 170 | { 171 | return (r >> 0) & 0xffff; 172 | } 173 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) 174 | { 175 | return (r >> 16) & 0xff; 176 | } 177 | static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) 178 | { 179 | return 0x00000100; 180 | } 181 | static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) 182 | { 183 | return 0x00000004; 184 | } 185 | static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) 186 | { 187 | return 0x00000005; 188 | } 189 | static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) 190 | { 191 | return 0x00000004; 192 | } 193 | static inline u32 ctxsw_prog_extended_num_smpc_quadrants_v(void) 194 | { 195 | return 0x00000004; 196 | } 197 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) 198 | { 199 | return 0x000000a0; 200 | } 201 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) 202 | { 203 | return 2; 204 | } 205 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) 206 | { 207 | return (v & 0x3) << 0; 208 | } 209 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) 210 | { 211 | return 0x3 << 0; 212 | } 213 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) 214 | { 215 | return (r >> 0) & 0x3; 216 | } 217 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) 218 | { 219 | return 0x0; 220 | } 221 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) 222 | { 223 | return 0x2; 224 | } 225 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) 226 | { 227 | return 0x000000a4; 228 | } 229 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) 230 | { 231 | return 0x000000a8; 232 | } 233 | static inline u32 ctxsw_prog_main_image_misc_options_o(void) 234 | { 235 | return 0x0000003c; 236 | } 237 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) 238 | { 239 | return 0x1 << 3; 240 | } 241 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) 242 | { 243 | return 0x0; 244 | } 245 | #endif 246 | -------------------------------------------------------------------------------- /gk20a/hw_fb_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_fb_gk20a_h_ 51 | #define _hw_fb_gk20a_h_ 52 | 53 | static inline u32 fb_mmu_ctrl_r(void) 54 | { 55 | return 0x00100c80; 56 | } 57 | static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) 58 | { 59 | return (v & 0x1) << 0; 60 | } 61 | static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) 62 | { 63 | return 0x0; 64 | } 65 | static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) 66 | { 67 | return 0x1; 68 | } 69 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) 70 | { 71 | return (r >> 15) & 0x1; 72 | } 73 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) 74 | { 75 | return 0x0; 76 | } 77 | static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) 78 | { 79 | return (r >> 16) & 0xff; 80 | } 81 | static inline u32 fb_mmu_invalidate_pdb_r(void) 82 | { 83 | return 0x00100cb8; 84 | } 85 | static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) 86 | { 87 | return 0x0; 88 | } 89 | static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) 90 | { 91 | return (v & 0xfffffff) << 4; 92 | } 93 | static inline u32 fb_mmu_invalidate_r(void) 94 | { 95 | return 0x00100cbc; 96 | } 97 | static inline u32 fb_mmu_invalidate_all_va_true_f(void) 98 | { 99 | return 0x1; 100 | } 101 | static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) 102 | { 103 | return 0x2; 104 | } 105 | static inline u32 fb_mmu_invalidate_trigger_s(void) 106 | { 107 | return 1; 108 | } 109 | static inline u32 fb_mmu_invalidate_trigger_f(u32 v) 110 | { 111 | return (v & 0x1) << 31; 112 | } 113 | static inline u32 fb_mmu_invalidate_trigger_m(void) 114 | { 115 | return 0x1 << 31; 116 | } 117 | static inline u32 fb_mmu_invalidate_trigger_v(u32 r) 118 | { 119 | return (r >> 31) & 0x1; 120 | } 121 | static inline u32 fb_mmu_invalidate_trigger_true_f(void) 122 | { 123 | return 0x80000000; 124 | } 125 | static inline u32 fb_mmu_debug_wr_r(void) 126 | { 127 | return 0x00100cc8; 128 | } 129 | static inline u32 fb_mmu_debug_wr_aperture_s(void) 130 | { 131 | return 2; 132 | } 133 | static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) 134 | { 135 | return (v & 0x3) << 0; 136 | } 137 | static inline u32 fb_mmu_debug_wr_aperture_m(void) 138 | { 139 | return 0x3 << 0; 140 | } 141 | static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) 142 | { 143 | return (r >> 0) & 0x3; 144 | } 145 | static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) 146 | { 147 | return 0x0; 148 | } 149 | static inline u32 fb_mmu_debug_wr_vol_false_f(void) 150 | { 151 | return 0x0; 152 | } 153 | static inline u32 fb_mmu_debug_wr_vol_true_v(void) 154 | { 155 | return 0x00000001; 156 | } 157 | static inline u32 fb_mmu_debug_wr_vol_true_f(void) 158 | { 159 | return 0x4; 160 | } 161 | static inline u32 fb_mmu_debug_wr_addr_f(u32 v) 162 | { 163 | return (v & 0xfffffff) << 4; 164 | } 165 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) 166 | { 167 | return 0x0000000c; 168 | } 169 | static inline u32 fb_mmu_debug_rd_r(void) 170 | { 171 | return 0x00100ccc; 172 | } 173 | static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) 174 | { 175 | return 0x0; 176 | } 177 | static inline u32 fb_mmu_debug_rd_vol_false_f(void) 178 | { 179 | return 0x0; 180 | } 181 | static inline u32 fb_mmu_debug_rd_addr_f(u32 v) 182 | { 183 | return (v & 0xfffffff) << 4; 184 | } 185 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) 186 | { 187 | return 0x0000000c; 188 | } 189 | static inline u32 fb_mmu_debug_ctrl_r(void) 190 | { 191 | return 0x00100cc4; 192 | } 193 | static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) 194 | { 195 | return (r >> 16) & 0x1; 196 | } 197 | static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) 198 | { 199 | return 0x00000001; 200 | } 201 | static inline u32 fb_mmu_vpr_info_r(void) 202 | { 203 | return 0x00100cd0; 204 | } 205 | static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) 206 | { 207 | return (r >> 2) & 0x1; 208 | } 209 | static inline u32 fb_mmu_vpr_info_fetch_false_v(void) 210 | { 211 | return 0x00000000; 212 | } 213 | static inline u32 fb_mmu_vpr_info_fetch_true_v(void) 214 | { 215 | return 0x00000001; 216 | } 217 | #endif 218 | -------------------------------------------------------------------------------- /gk20a/hw_flush_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_flush_gk20a_h_ 51 | #define _hw_flush_gk20a_h_ 52 | 53 | static inline u32 flush_l2_system_invalidate_r(void) 54 | { 55 | return 0x00070004; 56 | } 57 | static inline u32 flush_l2_system_invalidate_pending_v(u32 r) 58 | { 59 | return (r >> 0) & 0x1; 60 | } 61 | static inline u32 flush_l2_system_invalidate_pending_busy_v(void) 62 | { 63 | return 0x00000001; 64 | } 65 | static inline u32 flush_l2_system_invalidate_pending_busy_f(void) 66 | { 67 | return 0x1; 68 | } 69 | static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) 70 | { 71 | return (r >> 1) & 0x1; 72 | } 73 | static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) 74 | { 75 | return 0x00000001; 76 | } 77 | static inline u32 flush_l2_flush_dirty_r(void) 78 | { 79 | return 0x00070010; 80 | } 81 | static inline u32 flush_l2_flush_dirty_pending_v(u32 r) 82 | { 83 | return (r >> 0) & 0x1; 84 | } 85 | static inline u32 flush_l2_flush_dirty_pending_empty_v(void) 86 | { 87 | return 0x00000000; 88 | } 89 | static inline u32 flush_l2_flush_dirty_pending_empty_f(void) 90 | { 91 | return 0x0; 92 | } 93 | static inline u32 flush_l2_flush_dirty_pending_busy_v(void) 94 | { 95 | return 0x00000001; 96 | } 97 | static inline u32 flush_l2_flush_dirty_pending_busy_f(void) 98 | { 99 | return 0x1; 100 | } 101 | static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) 102 | { 103 | return (r >> 1) & 0x1; 104 | } 105 | static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) 106 | { 107 | return 0x00000000; 108 | } 109 | static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) 110 | { 111 | return 0x0; 112 | } 113 | static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) 114 | { 115 | return 0x00000001; 116 | } 117 | static inline u32 flush_fb_flush_r(void) 118 | { 119 | return 0x00070000; 120 | } 121 | static inline u32 flush_fb_flush_pending_v(u32 r) 122 | { 123 | return (r >> 0) & 0x1; 124 | } 125 | static inline u32 flush_fb_flush_pending_busy_v(void) 126 | { 127 | return 0x00000001; 128 | } 129 | static inline u32 flush_fb_flush_pending_busy_f(void) 130 | { 131 | return 0x1; 132 | } 133 | static inline u32 flush_fb_flush_outstanding_v(u32 r) 134 | { 135 | return (r >> 1) & 0x1; 136 | } 137 | static inline u32 flush_fb_flush_outstanding_true_v(void) 138 | { 139 | return 0x00000001; 140 | } 141 | #endif 142 | -------------------------------------------------------------------------------- /gk20a/hw_mc_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_mc_gk20a_h_ 51 | #define _hw_mc_gk20a_h_ 52 | 53 | static inline u32 mc_boot_0_r(void) 54 | { 55 | return 0x00000000; 56 | } 57 | static inline u32 mc_boot_0_architecture_v(u32 r) 58 | { 59 | return (r >> 24) & 0x1f; 60 | } 61 | static inline u32 mc_boot_0_implementation_v(u32 r) 62 | { 63 | return (r >> 20) & 0xf; 64 | } 65 | static inline u32 mc_boot_0_major_revision_v(u32 r) 66 | { 67 | return (r >> 4) & 0xf; 68 | } 69 | static inline u32 mc_boot_0_minor_revision_v(u32 r) 70 | { 71 | return (r >> 0) & 0xf; 72 | } 73 | static inline u32 mc_intr_0_r(void) 74 | { 75 | return 0x00000100; 76 | } 77 | static inline u32 mc_intr_0_pfifo_pending_f(void) 78 | { 79 | return 0x100; 80 | } 81 | static inline u32 mc_intr_0_pgraph_pending_f(void) 82 | { 83 | return 0x1000; 84 | } 85 | static inline u32 mc_intr_0_pmu_pending_f(void) 86 | { 87 | return 0x1000000; 88 | } 89 | static inline u32 mc_intr_0_ltc_pending_f(void) 90 | { 91 | return 0x2000000; 92 | } 93 | static inline u32 mc_intr_0_priv_ring_pending_f(void) 94 | { 95 | return 0x40000000; 96 | } 97 | static inline u32 mc_intr_0_pbus_pending_f(void) 98 | { 99 | return 0x10000000; 100 | } 101 | static inline u32 mc_intr_1_r(void) 102 | { 103 | return 0x00000104; 104 | } 105 | static inline u32 mc_intr_mask_0_r(void) 106 | { 107 | return 0x00000640; 108 | } 109 | static inline u32 mc_intr_mask_0_pmu_enabled_f(void) 110 | { 111 | return 0x1000000; 112 | } 113 | static inline u32 mc_intr_en_0_r(void) 114 | { 115 | return 0x00000140; 116 | } 117 | static inline u32 mc_intr_en_0_inta_disabled_f(void) 118 | { 119 | return 0x0; 120 | } 121 | static inline u32 mc_intr_en_0_inta_hardware_f(void) 122 | { 123 | return 0x1; 124 | } 125 | static inline u32 mc_intr_mask_1_r(void) 126 | { 127 | return 0x00000644; 128 | } 129 | static inline u32 mc_intr_mask_1_pmu_s(void) 130 | { 131 | return 1; 132 | } 133 | static inline u32 mc_intr_mask_1_pmu_f(u32 v) 134 | { 135 | return (v & 0x1) << 24; 136 | } 137 | static inline u32 mc_intr_mask_1_pmu_m(void) 138 | { 139 | return 0x1 << 24; 140 | } 141 | static inline u32 mc_intr_mask_1_pmu_v(u32 r) 142 | { 143 | return (r >> 24) & 0x1; 144 | } 145 | static inline u32 mc_intr_mask_1_pmu_enabled_f(void) 146 | { 147 | return 0x1000000; 148 | } 149 | static inline u32 mc_intr_en_1_r(void) 150 | { 151 | return 0x00000144; 152 | } 153 | static inline u32 mc_intr_en_1_inta_disabled_f(void) 154 | { 155 | return 0x0; 156 | } 157 | static inline u32 mc_intr_en_1_inta_hardware_f(void) 158 | { 159 | return 0x1; 160 | } 161 | static inline u32 mc_enable_r(void) 162 | { 163 | return 0x00000200; 164 | } 165 | static inline u32 mc_enable_xbar_enabled_f(void) 166 | { 167 | return 0x4; 168 | } 169 | static inline u32 mc_enable_l2_enabled_f(void) 170 | { 171 | return 0x8; 172 | } 173 | static inline u32 mc_enable_pmedia_s(void) 174 | { 175 | return 1; 176 | } 177 | static inline u32 mc_enable_pmedia_f(u32 v) 178 | { 179 | return (v & 0x1) << 4; 180 | } 181 | static inline u32 mc_enable_pmedia_m(void) 182 | { 183 | return 0x1 << 4; 184 | } 185 | static inline u32 mc_enable_pmedia_v(u32 r) 186 | { 187 | return (r >> 4) & 0x1; 188 | } 189 | static inline u32 mc_enable_priv_ring_enabled_f(void) 190 | { 191 | return 0x20; 192 | } 193 | static inline u32 mc_enable_ce0_m(void) 194 | { 195 | return 0x1 << 6; 196 | } 197 | static inline u32 mc_enable_pfifo_enabled_f(void) 198 | { 199 | return 0x100; 200 | } 201 | static inline u32 mc_enable_pgraph_enabled_f(void) 202 | { 203 | return 0x1000; 204 | } 205 | static inline u32 mc_enable_pwr_v(u32 r) 206 | { 207 | return (r >> 13) & 0x1; 208 | } 209 | static inline u32 mc_enable_pwr_disabled_v(void) 210 | { 211 | return 0x00000000; 212 | } 213 | static inline u32 mc_enable_pwr_enabled_f(void) 214 | { 215 | return 0x2000; 216 | } 217 | static inline u32 mc_enable_pfb_enabled_f(void) 218 | { 219 | return 0x100000; 220 | } 221 | static inline u32 mc_enable_ce2_m(void) 222 | { 223 | return 0x1 << 21; 224 | } 225 | static inline u32 mc_enable_ce2_enabled_f(void) 226 | { 227 | return 0x200000; 228 | } 229 | static inline u32 mc_enable_blg_enabled_f(void) 230 | { 231 | return 0x8000000; 232 | } 233 | static inline u32 mc_enable_perfmon_enabled_f(void) 234 | { 235 | return 0x10000000; 236 | } 237 | static inline u32 mc_enable_hub_enabled_f(void) 238 | { 239 | return 0x20000000; 240 | } 241 | static inline u32 mc_enable_pb_r(void) 242 | { 243 | return 0x00000204; 244 | } 245 | static inline u32 mc_enable_pb_0_s(void) 246 | { 247 | return 1; 248 | } 249 | static inline u32 mc_enable_pb_0_f(u32 v) 250 | { 251 | return (v & 0x1) << 0; 252 | } 253 | static inline u32 mc_enable_pb_0_m(void) 254 | { 255 | return 0x1 << 0; 256 | } 257 | static inline u32 mc_enable_pb_0_v(u32 r) 258 | { 259 | return (r >> 0) & 0x1; 260 | } 261 | static inline u32 mc_enable_pb_0_enabled_v(void) 262 | { 263 | return 0x00000001; 264 | } 265 | static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) 266 | { 267 | return (v & 0x1) << (0 + i*1); 268 | } 269 | #endif 270 | -------------------------------------------------------------------------------- /gk20a/hw_pri_ringmaster_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_pri_ringmaster_gk20a_h_ 51 | #define _hw_pri_ringmaster_gk20a_h_ 52 | 53 | static inline u32 pri_ringmaster_command_r(void) 54 | { 55 | return 0x0012004c; 56 | } 57 | static inline u32 pri_ringmaster_command_cmd_m(void) 58 | { 59 | return 0x3f << 0; 60 | } 61 | static inline u32 pri_ringmaster_command_cmd_v(u32 r) 62 | { 63 | return (r >> 0) & 0x3f; 64 | } 65 | static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) 66 | { 67 | return 0x00000000; 68 | } 69 | static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) 70 | { 71 | return 0x1; 72 | } 73 | static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) 74 | { 75 | return 0x2; 76 | } 77 | static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) 78 | { 79 | return 0x3; 80 | } 81 | static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) 82 | { 83 | return 0x0; 84 | } 85 | static inline u32 pri_ringmaster_command_data_r(void) 86 | { 87 | return 0x00120048; 88 | } 89 | static inline u32 pri_ringmaster_start_results_r(void) 90 | { 91 | return 0x00120050; 92 | } 93 | static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) 94 | { 95 | return (r >> 0) & 0x1; 96 | } 97 | static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) 98 | { 99 | return 0x00000001; 100 | } 101 | static inline u32 pri_ringmaster_intr_status0_r(void) 102 | { 103 | return 0x00120058; 104 | } 105 | static inline u32 pri_ringmaster_intr_status1_r(void) 106 | { 107 | return 0x0012005c; 108 | } 109 | static inline u32 pri_ringmaster_global_ctl_r(void) 110 | { 111 | return 0x00120060; 112 | } 113 | static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) 114 | { 115 | return 0x1; 116 | } 117 | static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) 118 | { 119 | return 0x0; 120 | } 121 | static inline u32 pri_ringmaster_enum_fbp_r(void) 122 | { 123 | return 0x00120074; 124 | } 125 | static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) 126 | { 127 | return (r >> 0) & 0x1f; 128 | } 129 | static inline u32 pri_ringmaster_enum_gpc_r(void) 130 | { 131 | return 0x00120078; 132 | } 133 | static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) 134 | { 135 | return (r >> 0) & 0x1f; 136 | } 137 | #endif 138 | -------------------------------------------------------------------------------- /gk20a/hw_pri_ringstation_fbp_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/hw_pri_ringstation_fbp_gk20a.h 3 | * 4 | * Copyright (c) 2012-2013, NVIDIA Corporation. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | * 18 | */ 19 | 20 | /* 21 | * Function naming determines intended use: 22 | * 23 | * _r(void) : Returns the offset for register . 24 | * 25 | * _w(void) : Returns the word offset for word (4 byte) element . 26 | * 27 | * __s(void) : Returns size of field of register in bits. 28 | * 29 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 30 | * and masked to place it at field of register . This value 31 | * can be |'d with others to produce a full register value for 32 | * register . 33 | * 34 | * __m(void) : Returns a mask for field of register . This 35 | * value can be ~'d and then &'d to clear the value of field for 36 | * register . 37 | * 38 | * ___f(void) : Returns the constant value after being shifted 39 | * to place it at field of register . This value can be |'d 40 | * with others to produce a full register value for . 41 | * 42 | * __v(u32 r) : Returns the value of field from a full register 43 | * value 'r' after being shifted to place its LSB at bit 0. 44 | * This value is suitable for direct comparison with other unshifted 45 | * values appropriate for use in field of register . 46 | * 47 | * ___v(void) : Returns the constant value for defined for 48 | * field of register . This value is suitable for direct 49 | * comparison with unshifted values appropriate for use in field 50 | * of register . 51 | */ 52 | 53 | #ifndef __hw_pri_ringstation_fbp_gk20a_h__ 54 | #define __hw_pri_ringstation_fbp_gk20a_h__ 55 | /*This file is autogenerated. Do not edit. */ 56 | 57 | static inline u32 pri_ringstation_fbp_master_config_r(u32 i) 58 | { 59 | return 0x00124300+((i)*4); 60 | } 61 | static inline u32 pri_ringstation_fbp_master_config__size_1_v(void) 62 | { 63 | return 64; 64 | } 65 | static inline u32 pri_ringstation_fbp_master_config_timeout_s(void) 66 | { 67 | return 18; 68 | } 69 | static inline u32 pri_ringstation_fbp_master_config_timeout_f(u32 v) 70 | { 71 | return (v & 0x3ffff) << 0; 72 | } 73 | static inline u32 pri_ringstation_fbp_master_config_timeout_m(void) 74 | { 75 | return 0x3ffff << 0; 76 | } 77 | static inline u32 pri_ringstation_fbp_master_config_timeout_v(u32 r) 78 | { 79 | return (r >> 0) & 0x3ffff; 80 | } 81 | static inline u32 pri_ringstation_fbp_master_config_timeout_i_v(void) 82 | { 83 | return 0x00000064; 84 | } 85 | static inline u32 pri_ringstation_fbp_master_config_timeout_i_f(void) 86 | { 87 | return 0x64; 88 | } 89 | static inline u32 pri_ringstation_fbp_master_config_fs_action_s(void) 90 | { 91 | return 1; 92 | } 93 | static inline u32 pri_ringstation_fbp_master_config_fs_action_f(u32 v) 94 | { 95 | return (v & 0x1) << 30; 96 | } 97 | static inline u32 pri_ringstation_fbp_master_config_fs_action_m(void) 98 | { 99 | return 0x1 << 30; 100 | } 101 | static inline u32 pri_ringstation_fbp_master_config_fs_action_v(u32 r) 102 | { 103 | return (r >> 30) & 0x1; 104 | } 105 | static inline u32 pri_ringstation_fbp_master_config_fs_action_error_v(void) 106 | { 107 | return 0x00000000; 108 | } 109 | static inline u32 pri_ringstation_fbp_master_config_fs_action_error_f(void) 110 | { 111 | return 0x0; 112 | } 113 | static inline u32 pri_ringstation_fbp_master_config_fs_action_soldier_on_v(void) 114 | { 115 | return 0x00000001; 116 | } 117 | static inline u32 pri_ringstation_fbp_master_config_fs_action_soldier_on_f(void) 118 | { 119 | return 0x40000000; 120 | } 121 | static inline u32 pri_ringstation_fbp_master_config_reset_action_s(void) 122 | { 123 | return 1; 124 | } 125 | static inline u32 pri_ringstation_fbp_master_config_reset_action_f(u32 v) 126 | { 127 | return (v & 0x1) << 31; 128 | } 129 | static inline u32 pri_ringstation_fbp_master_config_reset_action_m(void) 130 | { 131 | return 0x1 << 31; 132 | } 133 | static inline u32 pri_ringstation_fbp_master_config_reset_action_v(u32 r) 134 | { 135 | return (r >> 31) & 0x1; 136 | } 137 | static inline u32 pri_ringstation_fbp_master_config_reset_action_error_v(void) 138 | { 139 | return 0x00000000; 140 | } 141 | static inline u32 pri_ringstation_fbp_master_config_reset_action_error_f(void) 142 | { 143 | return 0x0; 144 | } 145 | static inline u32 pri_ringstation_fbp_master_config_reset_action_soldier_on_v(void) 146 | { 147 | return 0x00000001; 148 | } 149 | static inline u32 pri_ringstation_fbp_master_config_reset_action_soldier_on_f(void) 150 | { 151 | return 0x80000000; 152 | } 153 | static inline u32 pri_ringstation_fbp_master_config_setup_clocks_s(void) 154 | { 155 | return 3; 156 | } 157 | static inline u32 pri_ringstation_fbp_master_config_setup_clocks_f(u32 v) 158 | { 159 | return (v & 0x7) << 20; 160 | } 161 | static inline u32 pri_ringstation_fbp_master_config_setup_clocks_m(void) 162 | { 163 | return 0x7 << 20; 164 | } 165 | static inline u32 pri_ringstation_fbp_master_config_setup_clocks_v(u32 r) 166 | { 167 | return (r >> 20) & 0x7; 168 | } 169 | static inline u32 pri_ringstation_fbp_master_config_setup_clocks_i_v(void) 170 | { 171 | return 0x00000000; 172 | } 173 | static inline u32 pri_ringstation_fbp_master_config_setup_clocks_i_f(void) 174 | { 175 | return 0x0; 176 | } 177 | static inline u32 pri_ringstation_fbp_master_config_wait_clocks_s(void) 178 | { 179 | return 3; 180 | } 181 | static inline u32 pri_ringstation_fbp_master_config_wait_clocks_f(u32 v) 182 | { 183 | return (v & 0x7) << 24; 184 | } 185 | static inline u32 pri_ringstation_fbp_master_config_wait_clocks_m(void) 186 | { 187 | return 0x7 << 24; 188 | } 189 | static inline u32 pri_ringstation_fbp_master_config_wait_clocks_v(u32 r) 190 | { 191 | return (r >> 24) & 0x7; 192 | } 193 | static inline u32 pri_ringstation_fbp_master_config_wait_clocks_i_v(void) 194 | { 195 | return 0x00000000; 196 | } 197 | static inline u32 pri_ringstation_fbp_master_config_wait_clocks_i_f(void) 198 | { 199 | return 0x0; 200 | } 201 | static inline u32 pri_ringstation_fbp_master_config_hold_clocks_s(void) 202 | { 203 | return 3; 204 | } 205 | static inline u32 pri_ringstation_fbp_master_config_hold_clocks_f(u32 v) 206 | { 207 | return (v & 0x7) << 27; 208 | } 209 | static inline u32 pri_ringstation_fbp_master_config_hold_clocks_m(void) 210 | { 211 | return 0x7 << 27; 212 | } 213 | static inline u32 pri_ringstation_fbp_master_config_hold_clocks_v(u32 r) 214 | { 215 | return (r >> 27) & 0x7; 216 | } 217 | static inline u32 pri_ringstation_fbp_master_config_hold_clocks_i_v(void) 218 | { 219 | return 0x00000000; 220 | } 221 | static inline u32 pri_ringstation_fbp_master_config_hold_clocks_i_f(void) 222 | { 223 | return 0x0; 224 | } 225 | 226 | #endif /* __hw_pri_ringstation_fbp_gk20a_h__ */ 227 | -------------------------------------------------------------------------------- /gk20a/hw_pri_ringstation_gpc_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/hw_pri_ringstation_gpc_gk20a.h 3 | * 4 | * Copyright (c) 2012-2013, NVIDIA Corporation. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | * 18 | */ 19 | 20 | /* 21 | * Function naming determines intended use: 22 | * 23 | * _r(void) : Returns the offset for register . 24 | * 25 | * _w(void) : Returns the word offset for word (4 byte) element . 26 | * 27 | * __s(void) : Returns size of field of register in bits. 28 | * 29 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 30 | * and masked to place it at field of register . This value 31 | * can be |'d with others to produce a full register value for 32 | * register . 33 | * 34 | * __m(void) : Returns a mask for field of register . This 35 | * value can be ~'d and then &'d to clear the value of field for 36 | * register . 37 | * 38 | * ___f(void) : Returns the constant value after being shifted 39 | * to place it at field of register . This value can be |'d 40 | * with others to produce a full register value for . 41 | * 42 | * __v(u32 r) : Returns the value of field from a full register 43 | * value 'r' after being shifted to place its LSB at bit 0. 44 | * This value is suitable for direct comparison with other unshifted 45 | * values appropriate for use in field of register . 46 | * 47 | * ___v(void) : Returns the constant value for defined for 48 | * field of register . This value is suitable for direct 49 | * comparison with unshifted values appropriate for use in field 50 | * of register . 51 | */ 52 | 53 | #ifndef __hw_pri_ringstation_gpc_gk20a_h__ 54 | #define __hw_pri_ringstation_gpc_gk20a_h__ 55 | /*This file is autogenerated. Do not edit. */ 56 | 57 | static inline u32 pri_ringstation_gpc_master_config_r(u32 i) 58 | { 59 | return 0x00128300+((i)*4); 60 | } 61 | static inline u32 pri_ringstation_gpc_master_config__size_1_v(void) 62 | { 63 | return 64; 64 | } 65 | static inline u32 pri_ringstation_gpc_master_config_timeout_s(void) 66 | { 67 | return 18; 68 | } 69 | static inline u32 pri_ringstation_gpc_master_config_timeout_f(u32 v) 70 | { 71 | return (v & 0x3ffff) << 0; 72 | } 73 | static inline u32 pri_ringstation_gpc_master_config_timeout_m(void) 74 | { 75 | return 0x3ffff << 0; 76 | } 77 | static inline u32 pri_ringstation_gpc_master_config_timeout_v(u32 r) 78 | { 79 | return (r >> 0) & 0x3ffff; 80 | } 81 | static inline u32 pri_ringstation_gpc_master_config_timeout_i_v(void) 82 | { 83 | return 0x00000064; 84 | } 85 | static inline u32 pri_ringstation_gpc_master_config_timeout_i_f(void) 86 | { 87 | return 0x64; 88 | } 89 | static inline u32 pri_ringstation_gpc_master_config_fs_action_s(void) 90 | { 91 | return 1; 92 | } 93 | static inline u32 pri_ringstation_gpc_master_config_fs_action_f(u32 v) 94 | { 95 | return (v & 0x1) << 30; 96 | } 97 | static inline u32 pri_ringstation_gpc_master_config_fs_action_m(void) 98 | { 99 | return 0x1 << 30; 100 | } 101 | static inline u32 pri_ringstation_gpc_master_config_fs_action_v(u32 r) 102 | { 103 | return (r >> 30) & 0x1; 104 | } 105 | static inline u32 pri_ringstation_gpc_master_config_fs_action_error_v(void) 106 | { 107 | return 0x00000000; 108 | } 109 | static inline u32 pri_ringstation_gpc_master_config_fs_action_error_f(void) 110 | { 111 | return 0x0; 112 | } 113 | static inline u32 pri_ringstation_gpc_master_config_fs_action_soldier_on_v(void) 114 | { 115 | return 0x00000001; 116 | } 117 | static inline u32 pri_ringstation_gpc_master_config_fs_action_soldier_on_f(void) 118 | { 119 | return 0x40000000; 120 | } 121 | static inline u32 pri_ringstation_gpc_master_config_reset_action_s(void) 122 | { 123 | return 1; 124 | } 125 | static inline u32 pri_ringstation_gpc_master_config_reset_action_f(u32 v) 126 | { 127 | return (v & 0x1) << 31; 128 | } 129 | static inline u32 pri_ringstation_gpc_master_config_reset_action_m(void) 130 | { 131 | return 0x1 << 31; 132 | } 133 | static inline u32 pri_ringstation_gpc_master_config_reset_action_v(u32 r) 134 | { 135 | return (r >> 31) & 0x1; 136 | } 137 | static inline u32 pri_ringstation_gpc_master_config_reset_action_error_v(void) 138 | { 139 | return 0x00000000; 140 | } 141 | static inline u32 pri_ringstation_gpc_master_config_reset_action_error_f(void) 142 | { 143 | return 0x0; 144 | } 145 | static inline u32 pri_ringstation_gpc_master_config_reset_action_soldier_on_v(void) 146 | { 147 | return 0x00000001; 148 | } 149 | static inline u32 pri_ringstation_gpc_master_config_reset_action_soldier_on_f(void) 150 | { 151 | return 0x80000000; 152 | } 153 | static inline u32 pri_ringstation_gpc_master_config_setup_clocks_s(void) 154 | { 155 | return 3; 156 | } 157 | static inline u32 pri_ringstation_gpc_master_config_setup_clocks_f(u32 v) 158 | { 159 | return (v & 0x7) << 20; 160 | } 161 | static inline u32 pri_ringstation_gpc_master_config_setup_clocks_m(void) 162 | { 163 | return 0x7 << 20; 164 | } 165 | static inline u32 pri_ringstation_gpc_master_config_setup_clocks_v(u32 r) 166 | { 167 | return (r >> 20) & 0x7; 168 | } 169 | static inline u32 pri_ringstation_gpc_master_config_setup_clocks_i_v(void) 170 | { 171 | return 0x00000000; 172 | } 173 | static inline u32 pri_ringstation_gpc_master_config_setup_clocks_i_f(void) 174 | { 175 | return 0x0; 176 | } 177 | static inline u32 pri_ringstation_gpc_master_config_wait_clocks_s(void) 178 | { 179 | return 3; 180 | } 181 | static inline u32 pri_ringstation_gpc_master_config_wait_clocks_f(u32 v) 182 | { 183 | return (v & 0x7) << 24; 184 | } 185 | static inline u32 pri_ringstation_gpc_master_config_wait_clocks_m(void) 186 | { 187 | return 0x7 << 24; 188 | } 189 | static inline u32 pri_ringstation_gpc_master_config_wait_clocks_v(u32 r) 190 | { 191 | return (r >> 24) & 0x7; 192 | } 193 | static inline u32 pri_ringstation_gpc_master_config_wait_clocks_i_v(void) 194 | { 195 | return 0x00000000; 196 | } 197 | static inline u32 pri_ringstation_gpc_master_config_wait_clocks_i_f(void) 198 | { 199 | return 0x0; 200 | } 201 | static inline u32 pri_ringstation_gpc_master_config_hold_clocks_s(void) 202 | { 203 | return 3; 204 | } 205 | static inline u32 pri_ringstation_gpc_master_config_hold_clocks_f(u32 v) 206 | { 207 | return (v & 0x7) << 27; 208 | } 209 | static inline u32 pri_ringstation_gpc_master_config_hold_clocks_m(void) 210 | { 211 | return 0x7 << 27; 212 | } 213 | static inline u32 pri_ringstation_gpc_master_config_hold_clocks_v(u32 r) 214 | { 215 | return (r >> 27) & 0x7; 216 | } 217 | static inline u32 pri_ringstation_gpc_master_config_hold_clocks_i_v(void) 218 | { 219 | return 0x00000000; 220 | } 221 | static inline u32 pri_ringstation_gpc_master_config_hold_clocks_i_f(void) 222 | { 223 | return 0x0; 224 | } 225 | 226 | #endif /* __hw_pri_ringstation_gpc_gk20a_h__ */ 227 | -------------------------------------------------------------------------------- /gk20a/hw_pri_ringstation_sys_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_pri_ringstation_sys_gk20a_h_ 51 | #define _hw_pri_ringstation_sys_gk20a_h_ 52 | 53 | static inline u32 pri_ringstation_sys_master_config_r(u32 i) 54 | { 55 | return 0x00122300 + i*4; 56 | } 57 | static inline u32 pri_ringstation_sys_decode_config_r(void) 58 | { 59 | return 0x00122204; 60 | } 61 | static inline u32 pri_ringstation_sys_decode_config_ring_m(void) 62 | { 63 | return 0x7 << 0; 64 | } 65 | static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) 66 | { 67 | return 0x1; 68 | } 69 | #endif 70 | -------------------------------------------------------------------------------- /gk20a/hw_proj_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_proj_gk20a_h_ 51 | #define _hw_proj_gk20a_h_ 52 | 53 | static inline u32 proj_gpc_base_v(void) 54 | { 55 | return 0x00500000; 56 | } 57 | static inline u32 proj_gpc_shared_base_v(void) 58 | { 59 | return 0x00418000; 60 | } 61 | static inline u32 proj_gpc_stride_v(void) 62 | { 63 | return 0x00008000; 64 | } 65 | static inline u32 proj_ltc_stride_v(void) 66 | { 67 | return 0x00002000; 68 | } 69 | static inline u32 proj_lts_stride_v(void) 70 | { 71 | return 0x00000400; 72 | } 73 | static inline u32 proj_ppc_in_gpc_base_v(void) 74 | { 75 | return 0x00003000; 76 | } 77 | static inline u32 proj_ppc_in_gpc_stride_v(void) 78 | { 79 | return 0x00000200; 80 | } 81 | static inline u32 proj_rop_base_v(void) 82 | { 83 | return 0x00410000; 84 | } 85 | static inline u32 proj_rop_shared_base_v(void) 86 | { 87 | return 0x00408800; 88 | } 89 | static inline u32 proj_rop_stride_v(void) 90 | { 91 | return 0x00000400; 92 | } 93 | static inline u32 proj_tpc_in_gpc_base_v(void) 94 | { 95 | return 0x00004000; 96 | } 97 | static inline u32 proj_tpc_in_gpc_stride_v(void) 98 | { 99 | return 0x00000800; 100 | } 101 | static inline u32 proj_tpc_in_gpc_shared_base_v(void) 102 | { 103 | return 0x00001800; 104 | } 105 | static inline u32 proj_host_num_pbdma_v(void) 106 | { 107 | return 0x00000001; 108 | } 109 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) 110 | { 111 | return 0x00000001; 112 | } 113 | static inline u32 proj_scal_litter_num_fbps_v(void) 114 | { 115 | return 0x00000001; 116 | } 117 | static inline u32 proj_scal_litter_num_gpcs_v(void) 118 | { 119 | return 0x00000001; 120 | } 121 | static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) 122 | { 123 | return 0x00000001; 124 | } 125 | static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) 126 | { 127 | return 0x00000001; 128 | } 129 | static inline u32 proj_scal_litter_num_zcull_banks_v(void) 130 | { 131 | return 0x00000004; 132 | } 133 | static inline u32 proj_scal_max_gpcs_v(void) 134 | { 135 | return 0x00000020; 136 | } 137 | static inline u32 proj_scal_max_tpc_per_gpc_v(void) 138 | { 139 | return 0x00000008; 140 | } 141 | #endif 142 | -------------------------------------------------------------------------------- /gk20a/hw_therm_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_therm_gk20a_h_ 51 | #define _hw_therm_gk20a_h_ 52 | 53 | static inline u32 therm_use_a_r(void) 54 | { 55 | return 0x00020798; 56 | } 57 | static inline u32 therm_evt_ext_therm_0_r(void) 58 | { 59 | return 0x00020700; 60 | } 61 | static inline u32 therm_evt_ext_therm_1_r(void) 62 | { 63 | return 0x00020704; 64 | } 65 | static inline u32 therm_evt_ext_therm_2_r(void) 66 | { 67 | return 0x00020708; 68 | } 69 | static inline u32 therm_weight_1_r(void) 70 | { 71 | return 0x00020024; 72 | } 73 | static inline u32 therm_config1_r(void) 74 | { 75 | return 0x00020050; 76 | } 77 | static inline u32 therm_gate_ctrl_r(u32 i) 78 | { 79 | return 0x00020200 + i*4; 80 | } 81 | static inline u32 therm_gate_ctrl_eng_clk_m(void) 82 | { 83 | return 0x3 << 0; 84 | } 85 | static inline u32 therm_gate_ctrl_eng_clk_run_f(void) 86 | { 87 | return 0x0; 88 | } 89 | static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) 90 | { 91 | return 0x1; 92 | } 93 | static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) 94 | { 95 | return 0x2; 96 | } 97 | static inline u32 therm_gate_ctrl_blk_clk_m(void) 98 | { 99 | return 0x3 << 2; 100 | } 101 | static inline u32 therm_gate_ctrl_blk_clk_run_f(void) 102 | { 103 | return 0x0; 104 | } 105 | static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) 106 | { 107 | return 0x4; 108 | } 109 | static inline u32 therm_gate_ctrl_eng_pwr_m(void) 110 | { 111 | return 0x3 << 4; 112 | } 113 | static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) 114 | { 115 | return 0x10; 116 | } 117 | static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) 118 | { 119 | return 0x00000002; 120 | } 121 | static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) 122 | { 123 | return 0x20; 124 | } 125 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) 126 | { 127 | return (v & 0x1f) << 8; 128 | } 129 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) 130 | { 131 | return 0x1f << 8; 132 | } 133 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) 134 | { 135 | return (v & 0x7) << 13; 136 | } 137 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) 138 | { 139 | return 0x7 << 13; 140 | } 141 | static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) 142 | { 143 | return (v & 0xf) << 20; 144 | } 145 | static inline u32 therm_gate_ctrl_eng_delay_after_m(void) 146 | { 147 | return 0xf << 20; 148 | } 149 | static inline u32 therm_fecs_idle_filter_r(void) 150 | { 151 | return 0x00020288; 152 | } 153 | static inline u32 therm_fecs_idle_filter_value_m(void) 154 | { 155 | return 0xffffffff << 0; 156 | } 157 | static inline u32 therm_hubmmu_idle_filter_r(void) 158 | { 159 | return 0x0002028c; 160 | } 161 | static inline u32 therm_hubmmu_idle_filter_value_m(void) 162 | { 163 | return 0xffffffff << 0; 164 | } 165 | static inline u32 therm_clk_slowdown_r(u32 i) 166 | { 167 | return 0x00020160 + i*4; 168 | } 169 | static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) 170 | { 171 | return (v & 0x3f) << 16; 172 | } 173 | static inline u32 therm_clk_slowdown_idle_factor_m(void) 174 | { 175 | return 0x3f << 16; 176 | } 177 | static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) 178 | { 179 | return (r >> 16) & 0x3f; 180 | } 181 | static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) 182 | { 183 | return 0x0; 184 | } 185 | #endif 186 | -------------------------------------------------------------------------------- /gk20a/hw_timer_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_timer_gk20a_h_ 51 | #define _hw_timer_gk20a_h_ 52 | 53 | static inline u32 timer_pri_timeout_r(void) 54 | { 55 | return 0x00009080; 56 | } 57 | static inline u32 timer_pri_timeout_period_f(u32 v) 58 | { 59 | return (v & 0xffffff) << 0; 60 | } 61 | static inline u32 timer_pri_timeout_period_m(void) 62 | { 63 | return 0xffffff << 0; 64 | } 65 | static inline u32 timer_pri_timeout_period_v(u32 r) 66 | { 67 | return (r >> 0) & 0xffffff; 68 | } 69 | static inline u32 timer_pri_timeout_en_f(u32 v) 70 | { 71 | return (v & 0x1) << 31; 72 | } 73 | static inline u32 timer_pri_timeout_en_m(void) 74 | { 75 | return 0x1 << 31; 76 | } 77 | static inline u32 timer_pri_timeout_en_v(u32 r) 78 | { 79 | return (r >> 31) & 0x1; 80 | } 81 | static inline u32 timer_pri_timeout_en_en_enabled_f(void) 82 | { 83 | return 0x80000000; 84 | } 85 | static inline u32 timer_pri_timeout_en_en_disabled_f(void) 86 | { 87 | return 0x0; 88 | } 89 | static inline u32 timer_pri_timeout_save_0_r(void) 90 | { 91 | return 0x00009084; 92 | } 93 | static inline u32 timer_pri_timeout_save_1_r(void) 94 | { 95 | return 0x00009088; 96 | } 97 | static inline u32 timer_pri_timeout_fecs_errcode_r(void) 98 | { 99 | return 0x0000908c; 100 | } 101 | #endif 102 | -------------------------------------------------------------------------------- /gk20a/hw_top_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_top_gk20a_h_ 51 | #define _hw_top_gk20a_h_ 52 | 53 | static inline u32 top_num_gpcs_r(void) 54 | { 55 | return 0x00022430; 56 | } 57 | static inline u32 top_num_gpcs_value_v(u32 r) 58 | { 59 | return (r >> 0) & 0x1f; 60 | } 61 | static inline u32 top_tpc_per_gpc_r(void) 62 | { 63 | return 0x00022434; 64 | } 65 | static inline u32 top_tpc_per_gpc_value_v(u32 r) 66 | { 67 | return (r >> 0) & 0x1f; 68 | } 69 | static inline u32 top_num_fbps_r(void) 70 | { 71 | return 0x00022438; 72 | } 73 | static inline u32 top_num_fbps_value_v(u32 r) 74 | { 75 | return (r >> 0) & 0x1f; 76 | } 77 | static inline u32 top_device_info_r(u32 i) 78 | { 79 | return 0x00022700 + i*4; 80 | } 81 | static inline u32 top_device_info__size_1_v(void) 82 | { 83 | return 0x00000040; 84 | } 85 | static inline u32 top_device_info_chain_v(u32 r) 86 | { 87 | return (r >> 31) & 0x1; 88 | } 89 | static inline u32 top_device_info_chain_enable_v(void) 90 | { 91 | return 0x00000001; 92 | } 93 | static inline u32 top_device_info_engine_enum_v(u32 r) 94 | { 95 | return (r >> 26) & 0xf; 96 | } 97 | static inline u32 top_device_info_runlist_enum_v(u32 r) 98 | { 99 | return (r >> 21) & 0xf; 100 | } 101 | static inline u32 top_device_info_intr_enum_v(u32 r) 102 | { 103 | return (r >> 15) & 0x1f; 104 | } 105 | static inline u32 top_device_info_reset_enum_v(u32 r) 106 | { 107 | return (r >> 9) & 0x1f; 108 | } 109 | static inline u32 top_device_info_type_enum_v(u32 r) 110 | { 111 | return (r >> 2) & 0x1fffffff; 112 | } 113 | static inline u32 top_device_info_type_enum_graphics_v(void) 114 | { 115 | return 0x00000000; 116 | } 117 | static inline u32 top_device_info_type_enum_graphics_f(void) 118 | { 119 | return 0x0; 120 | } 121 | static inline u32 top_device_info_type_enum_copy0_v(void) 122 | { 123 | return 0x00000001; 124 | } 125 | static inline u32 top_device_info_type_enum_copy0_f(void) 126 | { 127 | return 0x4; 128 | } 129 | static inline u32 top_device_info_entry_v(u32 r) 130 | { 131 | return (r >> 0) & 0x3; 132 | } 133 | static inline u32 top_device_info_entry_not_valid_v(void) 134 | { 135 | return 0x00000000; 136 | } 137 | static inline u32 top_device_info_entry_enum_v(void) 138 | { 139 | return 0x00000002; 140 | } 141 | #endif 142 | -------------------------------------------------------------------------------- /gk20a/hw_trim_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | /* 17 | * Function naming determines intended use: 18 | * 19 | * _r(void) : Returns the offset for register . 20 | * 21 | * _o(void) : Returns the offset for element . 22 | * 23 | * _w(void) : Returns the word offset for word (4 byte) element . 24 | * 25 | * __s(void) : Returns size of field of register in bits. 26 | * 27 | * __f(u32 v) : Returns a value based on 'v' which has been shifted 28 | * and masked to place it at field of register . This value 29 | * can be |'d with others to produce a full register value for 30 | * register . 31 | * 32 | * __m(void) : Returns a mask for field of register . This 33 | * value can be ~'d and then &'d to clear the value of field for 34 | * register . 35 | * 36 | * ___f(void) : Returns the constant value after being shifted 37 | * to place it at field of register . This value can be |'d 38 | * with others to produce a full register value for . 39 | * 40 | * __v(u32 r) : Returns the value of field from a full register 41 | * value 'r' after being shifted to place its LSB at bit 0. 42 | * This value is suitable for direct comparison with other unshifted 43 | * values appropriate for use in field of register . 44 | * 45 | * ___v(void) : Returns the constant value for defined for 46 | * field of register . This value is suitable for direct 47 | * comparison with unshifted values appropriate for use in field 48 | * of register . 49 | */ 50 | #ifndef _hw_trim_gk20a_h_ 51 | #define _hw_trim_gk20a_h_ 52 | 53 | static inline u32 trim_sys_gpcpll_cfg_r(void) 54 | { 55 | return 0x00137000; 56 | } 57 | static inline u32 trim_sys_gpcpll_cfg_enable_m(void) 58 | { 59 | return 0x1 << 0; 60 | } 61 | static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) 62 | { 63 | return (r >> 0) & 0x1; 64 | } 65 | static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) 66 | { 67 | return 0x0; 68 | } 69 | static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) 70 | { 71 | return 0x1; 72 | } 73 | static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) 74 | { 75 | return 0x1 << 1; 76 | } 77 | static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) 78 | { 79 | return (r >> 1) & 0x1; 80 | } 81 | static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) 82 | { 83 | return 0x00000000; 84 | } 85 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) 86 | { 87 | return 0x1 << 4; 88 | } 89 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) 90 | { 91 | return 0x0; 92 | } 93 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) 94 | { 95 | return 0x10; 96 | } 97 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) 98 | { 99 | return (r >> 17) & 0x1; 100 | } 101 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) 102 | { 103 | return 0x20000; 104 | } 105 | static inline u32 trim_sys_gpcpll_coeff_r(void) 106 | { 107 | return 0x00137004; 108 | } 109 | static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) 110 | { 111 | return (v & 0xff) << 0; 112 | } 113 | static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void) 114 | { 115 | return 0xff << 0; 116 | } 117 | static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) 118 | { 119 | return (r >> 0) & 0xff; 120 | } 121 | static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) 122 | { 123 | return (v & 0xff) << 8; 124 | } 125 | static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) 126 | { 127 | return 0xff << 8; 128 | } 129 | static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) 130 | { 131 | return (r >> 8) & 0xff; 132 | } 133 | static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) 134 | { 135 | return (v & 0x3f) << 16; 136 | } 137 | static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void) 138 | { 139 | return 0x3f << 16; 140 | } 141 | static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) 142 | { 143 | return (r >> 16) & 0x3f; 144 | } 145 | static inline u32 trim_sys_sel_vco_r(void) 146 | { 147 | return 0x00137100; 148 | } 149 | static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) 150 | { 151 | return 0x1 << 0; 152 | } 153 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) 154 | { 155 | return 0x00000000; 156 | } 157 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) 158 | { 159 | return 0x0; 160 | } 161 | static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) 162 | { 163 | return 0x0; 164 | } 165 | static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) 166 | { 167 | return 0x1; 168 | } 169 | static inline u32 trim_sys_gpc2clk_out_r(void) 170 | { 171 | return 0x00137250; 172 | } 173 | static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) 174 | { 175 | return 6; 176 | } 177 | static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) 178 | { 179 | return (v & 0x3f) << 0; 180 | } 181 | static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) 182 | { 183 | return 0x3f << 0; 184 | } 185 | static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) 186 | { 187 | return (r >> 0) & 0x3f; 188 | } 189 | static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) 190 | { 191 | return 0x3c; 192 | } 193 | static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void) 194 | { 195 | return 6; 196 | } 197 | static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v) 198 | { 199 | return (v & 0x3f) << 8; 200 | } 201 | static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) 202 | { 203 | return 0x3f << 8; 204 | } 205 | static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r) 206 | { 207 | return (r >> 8) & 0x3f; 208 | } 209 | static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) 210 | { 211 | return 0x0; 212 | } 213 | static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) 214 | { 215 | return 0x1 << 31; 216 | } 217 | static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) 218 | { 219 | return 0x80000000; 220 | } 221 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) 222 | { 223 | return 0x00134124 + i*512; 224 | } 225 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) 226 | { 227 | return (v & 0x3fff) << 0; 228 | } 229 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) 230 | { 231 | return 0x10000; 232 | } 233 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) 234 | { 235 | return 0x100000; 236 | } 237 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) 238 | { 239 | return 0x1000000; 240 | } 241 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) 242 | { 243 | return 0x00134128 + i*512; 244 | } 245 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) 246 | { 247 | return (r >> 0) & 0xfffff; 248 | } 249 | static inline u32 trim_sys_gpcpll_cfg2_r(void) 250 | { 251 | return 0x0013700c; 252 | } 253 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) 254 | { 255 | return (v & 0xff) << 24; 256 | } 257 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) 258 | { 259 | return 0xff << 24; 260 | } 261 | static inline u32 trim_sys_gpcpll_cfg3_r(void) 262 | { 263 | return 0x00137018; 264 | } 265 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) 266 | { 267 | return (v & 0xff) << 16; 268 | } 269 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) 270 | { 271 | return 0xff << 16; 272 | } 273 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) 274 | { 275 | return 0x0013701c; 276 | } 277 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) 278 | { 279 | return 0x1 << 22; 280 | } 281 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) 282 | { 283 | return 0x400000; 284 | } 285 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) 286 | { 287 | return 0x0; 288 | } 289 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) 290 | { 291 | return 0x1 << 31; 292 | } 293 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) 294 | { 295 | return 0x80000000; 296 | } 297 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) 298 | { 299 | return 0x0; 300 | } 301 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) 302 | { 303 | return 0x001328a0; 304 | } 305 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) 306 | { 307 | return (r >> 24) & 0x1; 308 | } 309 | #endif 310 | -------------------------------------------------------------------------------- /gk20a/kind_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/kind_gk20a.h 3 | * 4 | * GK20A memory kind management 5 | * 6 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | * 17 | * You should have received a copy of the GNU General Public License along with 18 | * this program; if not, write to the Free Software Foundation, Inc., 19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 | */ 21 | #ifndef __KIND_GK20A_H__ 22 | #define __KIND_GK20A_H__ 23 | 24 | 25 | void gk20a_init_uncompressed_kind_map(void); 26 | void gk20a_init_kind_attr(void); 27 | 28 | extern u16 gk20a_kind_attr[]; 29 | #define NV_KIND_DEFAULT -1 30 | 31 | #define GK20A_KIND_ATTR_SUPPORTED BIT(0) 32 | #define GK20A_KIND_ATTR_COMPRESSIBLE BIT(1) 33 | #define GK20A_KIND_ATTR_Z BIT(2) 34 | #define GK20A_KIND_ATTR_C BIT(3) 35 | #define GK20A_KIND_ATTR_ZBC BIT(4) 36 | 37 | static inline bool gk20a_kind_is_supported(u8 k) 38 | { 39 | return !!(gk20a_kind_attr[k] & GK20A_KIND_ATTR_SUPPORTED); 40 | } 41 | static inline bool gk20a_kind_is_compressible(u8 k) 42 | { 43 | return !!(gk20a_kind_attr[k] & GK20A_KIND_ATTR_COMPRESSIBLE); 44 | } 45 | 46 | static inline bool gk20a_kind_is_z(u8 k) 47 | { 48 | return !!(gk20a_kind_attr[k] & GK20A_KIND_ATTR_Z); 49 | } 50 | 51 | static inline bool gk20a_kind_is_c(u8 k) 52 | { 53 | return !!(gk20a_kind_attr[k] & GK20A_KIND_ATTR_C); 54 | } 55 | static inline bool gk20a_kind_is_zbc(u8 k) 56 | { 57 | return !!(gk20a_kind_attr[k] & GK20A_KIND_ATTR_ZBC); 58 | } 59 | 60 | /* maps kind to its uncompressed version */ 61 | extern u8 gk20a_uc_kind_map[]; 62 | static inline u8 gk20a_get_uncompressed_kind(u8 k) 63 | { 64 | return gk20a_uc_kind_map[k]; 65 | } 66 | 67 | #endif /* __KIND_GK20A_H__ */ 68 | -------------------------------------------------------------------------------- /gk20a/ltc_common.c: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/ltc_common.c 3 | * 4 | * GK20A Graphics 5 | * 6 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | * 17 | * You should have received a copy of the GNU General Public License 18 | * along with this program. If not, see . 19 | */ 20 | 21 | #include 22 | #include 23 | 24 | #include "gk20a.h" 25 | #include "gr_gk20a.h" 26 | 27 | /* 28 | * Set the maximum number of ways that can have the "EVIST_LAST" class. 29 | */ 30 | static void gk20a_ltc_set_max_ways_evict_last(struct gk20a *g, u32 max_ways) 31 | { 32 | u32 mgmt_reg; 33 | 34 | mgmt_reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_r()) & 35 | ~ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(~0); 36 | mgmt_reg |= ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(max_ways); 37 | 38 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_r(), mgmt_reg); 39 | } 40 | 41 | /* 42 | * Sets the ZBC color for the passed index. 43 | */ 44 | static void gk20a_ltc_set_zbc_color_entry(struct gk20a *g, 45 | struct zbc_entry *color_val, 46 | u32 index) 47 | { 48 | u32 i; 49 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; 50 | 51 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), 52 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); 53 | 54 | for (i = 0; 55 | i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) 56 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), 57 | color_val->color_l2[i]); 58 | } 59 | 60 | /* 61 | * Sets the ZBC depth for the passed index. 62 | */ 63 | static void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g, 64 | struct zbc_entry *depth_val, 65 | u32 index) 66 | { 67 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; 68 | 69 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), 70 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); 71 | 72 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), 73 | depth_val->depth); 74 | } 75 | 76 | static int gk20a_ltc_alloc_phys_cbc(struct gk20a *g, 77 | size_t compbit_backing_size) 78 | { 79 | struct gr_gk20a *gr = &g->gr; 80 | int order = order_base_2(compbit_backing_size >> PAGE_SHIFT); 81 | struct page *pages; 82 | struct sg_table *sgt; 83 | int err = 0; 84 | 85 | /* allocate pages */ 86 | pages = alloc_pages(GFP_KERNEL, order); 87 | if (!pages) { 88 | gk20a_dbg(gpu_dbg_pte, "alloc_pages failed\n"); 89 | err = -ENOMEM; 90 | goto err_alloc_pages; 91 | } 92 | 93 | /* clean up the pages */ 94 | memset(page_address(pages), 0, compbit_backing_size); 95 | 96 | /* allocate room for placing the pages pointer.. */ 97 | gr->compbit_store.pages = 98 | kzalloc(sizeof(*gr->compbit_store.pages), GFP_KERNEL); 99 | if (!gr->compbit_store.pages) { 100 | gk20a_dbg(gpu_dbg_pte, "failed to allocate pages struct"); 101 | err = -ENOMEM; 102 | goto err_alloc_compbit_store; 103 | } 104 | 105 | err = gk20a_get_sgtable_from_pages(&g->dev->dev, &sgt, &pages, 0, 106 | compbit_backing_size); 107 | if (err) { 108 | gk20a_dbg(gpu_dbg_pte, "could not get sg table for pages\n"); 109 | goto err_alloc_sg_table; 110 | } 111 | 112 | /* store the parameters to gr structure */ 113 | *gr->compbit_store.pages = pages; 114 | gr->compbit_store.base_iova = sg_phys(sgt->sgl); 115 | gr->compbit_store.size = compbit_backing_size; 116 | gr->compbit_store.sgt = sgt; 117 | 118 | return 0; 119 | 120 | err_alloc_sg_table: 121 | kfree(gr->compbit_store.pages); 122 | gr->compbit_store.pages = NULL; 123 | err_alloc_compbit_store: 124 | __free_pages(pages, order); 125 | err_alloc_pages: 126 | return err; 127 | } 128 | 129 | static int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, 130 | size_t compbit_backing_size) 131 | { 132 | struct device *d = dev_from_gk20a(g); 133 | struct gr_gk20a *gr = &g->gr; 134 | DEFINE_DMA_ATTRS(attrs); 135 | dma_addr_t iova; 136 | int err; 137 | 138 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); 139 | 140 | gr->compbit_store.pages = 141 | dma_alloc_attrs(d, compbit_backing_size, &iova, 142 | GFP_KERNEL, &attrs); 143 | if (!gr->compbit_store.pages) { 144 | gk20a_err(dev_from_gk20a(g), "failed to allocate backing store for compbit : size %zu", 145 | compbit_backing_size); 146 | return -ENOMEM; 147 | } 148 | 149 | gr->compbit_store.base_iova = iova; 150 | gr->compbit_store.size = compbit_backing_size; 151 | err = gk20a_get_sgtable_from_pages(d, 152 | &gr->compbit_store.sgt, 153 | gr->compbit_store.pages, iova, 154 | compbit_backing_size); 155 | if (err) { 156 | gk20a_err(dev_from_gk20a(g), "failed to allocate sgt for backing store"); 157 | return err; 158 | } 159 | 160 | return 0; 161 | } 162 | 163 | static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) 164 | { 165 | u32 max_size = gr->max_comptag_mem; 166 | u32 max_comptag_lines = max_size << 3; 167 | 168 | u32 compbit_base_post_divide; 169 | u64 compbit_base_post_multiply64; 170 | u64 compbit_store_base_iova; 171 | u64 compbit_base_post_divide64; 172 | 173 | compbit_store_base_iova = gk20a_mm_smmu_vaddr_translate(g, 174 | gr->compbit_store.base_iova); 175 | 176 | compbit_base_post_divide64 = compbit_store_base_iova >> 177 | ltc_ltcs_ltss_cbc_base_alignment_shift_v(); 178 | 179 | do_div(compbit_base_post_divide64, g->ltc_count); 180 | compbit_base_post_divide = u64_lo32(compbit_base_post_divide64); 181 | 182 | compbit_base_post_multiply64 = ((u64)compbit_base_post_divide * 183 | g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); 184 | 185 | if (compbit_base_post_multiply64 < compbit_store_base_iova) 186 | compbit_base_post_divide++; 187 | 188 | /* Bug 1477079 indicates sw adjustment on the posted divided base. */ 189 | if (g->ops.ltc.cbc_fix_config) 190 | compbit_base_post_divide = 191 | g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide); 192 | 193 | gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(), 194 | compbit_base_post_divide); 195 | 196 | gk20a_dbg(gpu_dbg_info | gpu_dbg_map | gpu_dbg_pte, 197 | "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n", 198 | (u32)(compbit_store_base_iova >> 32), 199 | (u32)(compbit_store_base_iova & 0xffffffff), 200 | compbit_base_post_divide); 201 | 202 | gr->compbit_store.base_hw = compbit_base_post_divide; 203 | 204 | g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate, 205 | 0, max_comptag_lines - 1); 206 | 207 | } 208 | 209 | #ifdef CONFIG_DEBUG_FS 210 | static void gk20a_ltc_sync_debugfs(struct gk20a *g) 211 | { 212 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); 213 | 214 | spin_lock(&g->debugfs_lock); 215 | if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { 216 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); 217 | if (g->mm.ltc_enabled_debug) 218 | /* bypass disabled (normal caching ops)*/ 219 | reg &= ~reg_f; 220 | else 221 | /* bypass enabled (no caching) */ 222 | reg |= reg_f; 223 | 224 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); 225 | g->mm.ltc_enabled = g->mm.ltc_enabled_debug; 226 | } 227 | spin_unlock(&g->debugfs_lock); 228 | } 229 | #endif 230 | -------------------------------------------------------------------------------- /gk20a/ltc_gk20a.c: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/ltc_gk20a.c 3 | * 4 | * GK20A Graphics 5 | * 6 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | * 17 | * You should have received a copy of the GNU General Public License 18 | * along with this program. If not, see . 19 | */ 20 | 21 | #include 22 | 23 | #include "hw_ltc_gk20a.h" 24 | #include "hw_proj_gk20a.h" 25 | 26 | #include "ltc_common.c" 27 | 28 | static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) 29 | { 30 | /* max memory size (MB) to cover */ 31 | u32 max_size = gr->max_comptag_mem; 32 | /* one tag line covers 128KB */ 33 | u32 max_comptag_lines = max_size << 3; 34 | 35 | u32 hw_max_comptag_lines = 36 | ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(); 37 | 38 | u32 cbc_param = 39 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); 40 | u32 comptags_per_cacheline = 41 | ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param); 42 | u32 slices_per_fbp = 43 | ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(cbc_param); 44 | u32 cacheline_size = 45 | 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param); 46 | 47 | u32 compbit_backing_size; 48 | 49 | int err; 50 | 51 | gk20a_dbg_fn(""); 52 | 53 | if (max_comptag_lines == 0) { 54 | gr->compbit_store.size = 0; 55 | return 0; 56 | } 57 | 58 | if (max_comptag_lines > hw_max_comptag_lines) 59 | max_comptag_lines = hw_max_comptag_lines; 60 | 61 | /* no hybird fb */ 62 | compbit_backing_size = 63 | DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) * 64 | cacheline_size * slices_per_fbp * gr->num_fbps; 65 | 66 | /* aligned to 2KB * num_fbps */ 67 | compbit_backing_size += 68 | gr->num_fbps << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); 69 | 70 | /* must be a multiple of 64KB */ 71 | compbit_backing_size = roundup(compbit_backing_size, 64*1024); 72 | 73 | max_comptag_lines = 74 | (compbit_backing_size * comptags_per_cacheline) / 75 | cacheline_size * slices_per_fbp * gr->num_fbps; 76 | 77 | if (max_comptag_lines > hw_max_comptag_lines) 78 | max_comptag_lines = hw_max_comptag_lines; 79 | 80 | gk20a_dbg_info("compbit backing store size : %d", 81 | compbit_backing_size); 82 | gk20a_dbg_info("max comptag lines : %d", 83 | max_comptag_lines); 84 | 85 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); 86 | 87 | if (err) 88 | return err; 89 | 90 | gk20a_allocator_init(&gr->comp_tags, "comptag", 91 | 1, /* start */ 92 | max_comptag_lines - 1); /* length*/ 93 | 94 | gr->comptags_per_cacheline = comptags_per_cacheline; 95 | gr->slices_per_ltc = slices_per_fbp / g->ltc_count; 96 | gr->cacheline_size = cacheline_size; 97 | 98 | return 0; 99 | } 100 | 101 | static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, 102 | u32 min, u32 max) 103 | { 104 | int err = 0; 105 | struct gr_gk20a *gr = &g->gr; 106 | u32 fbp, slice, ctrl1, val, hw_op = 0; 107 | unsigned long end_jiffies = jiffies + 108 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); 109 | u32 delay = GR_IDLE_CHECK_DEFAULT; 110 | u32 slices_per_fbp = 111 | ltc_ltcs_ltss_cbc_param_slices_per_fbp_v( 112 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r())); 113 | 114 | gk20a_dbg_fn(""); 115 | 116 | if (gr->compbit_store.size == 0) 117 | return 0; 118 | 119 | mutex_lock(&g->mm.l2_op_lock); 120 | 121 | if (op == gk20a_cbc_op_clear) { 122 | gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl2_r(), 123 | ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(min)); 124 | gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl3_r(), 125 | ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(max)); 126 | hw_op = ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(); 127 | } else if (op == gk20a_cbc_op_clean) { 128 | hw_op = ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(); 129 | } else if (op == gk20a_cbc_op_invalidate) { 130 | hw_op = ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(); 131 | } else { 132 | BUG_ON(1); 133 | } 134 | 135 | gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl1_r(), 136 | gk20a_readl(g, ltc_ltcs_ltss_cbc_ctrl1_r()) | hw_op); 137 | 138 | for (fbp = 0; fbp < gr->num_fbps; fbp++) { 139 | for (slice = 0; slice < slices_per_fbp; slice++) { 140 | 141 | delay = GR_IDLE_CHECK_DEFAULT; 142 | 143 | ctrl1 = ltc_ltc0_lts0_cbc_ctrl1_r() + 144 | fbp * proj_ltc_stride_v() + 145 | slice * proj_lts_stride_v(); 146 | 147 | do { 148 | val = gk20a_readl(g, ctrl1); 149 | if (!(val & hw_op)) 150 | break; 151 | 152 | usleep_range(delay, delay * 2); 153 | delay = min_t(u32, delay << 1, 154 | GR_IDLE_CHECK_MAX); 155 | 156 | } while (time_before(jiffies, end_jiffies) || 157 | !tegra_platform_is_silicon()); 158 | 159 | if (!time_before(jiffies, end_jiffies)) { 160 | gk20a_err(dev_from_gk20a(g), 161 | "comp tag clear timeout\n"); 162 | err = -EBUSY; 163 | goto out; 164 | } 165 | } 166 | } 167 | out: 168 | mutex_unlock(&g->mm.l2_op_lock); 169 | return 0; 170 | } 171 | 172 | 173 | static void gk20a_ltc_init_fs_state(struct gk20a *g) 174 | { 175 | gk20a_dbg_info("initialize gk20a L2"); 176 | 177 | g->max_ltc_count = g->ltc_count = 1; 178 | } 179 | 180 | static void gk20a_ltc_isr(struct gk20a *g) 181 | { 182 | u32 intr; 183 | 184 | intr = gk20a_readl(g, ltc_ltc0_ltss_intr_r()); 185 | gk20a_err(dev_from_gk20a(g), "ltc: %08x\n", intr); 186 | gk20a_writel(g, ltc_ltc0_ltss_intr_r(), intr); 187 | } 188 | 189 | /* Flushes the compression bit cache as well as "data". 190 | * Note: the name here is a bit of a misnomer. ELPG uses this 191 | * internally... but ELPG doesn't have to be on to do it manually. 192 | */ 193 | static void gk20a_mm_g_elpg_flush_locked(struct gk20a *g) 194 | { 195 | u32 data; 196 | s32 retry = 100; 197 | 198 | gk20a_dbg_fn(""); 199 | 200 | /* Make sure all previous writes are committed to the L2. There's no 201 | guarantee that writes are to DRAM. This will be a sysmembar internal 202 | to the L2. */ 203 | gk20a_writel(g, ltc_ltcs_ltss_g_elpg_r(), 204 | ltc_ltcs_ltss_g_elpg_flush_pending_f()); 205 | do { 206 | data = gk20a_readl(g, ltc_ltc0_ltss_g_elpg_r()); 207 | 208 | if (ltc_ltc0_ltss_g_elpg_flush_v(data) == 209 | ltc_ltc0_ltss_g_elpg_flush_pending_v()) { 210 | gk20a_dbg_info("g_elpg_flush 0x%x", data); 211 | retry--; 212 | usleep_range(20, 40); 213 | } else 214 | break; 215 | } while (retry >= 0 || !tegra_platform_is_silicon()); 216 | 217 | if (retry < 0) 218 | gk20a_warn(dev_from_gk20a(g), 219 | "g_elpg_flush too many retries"); 220 | 221 | } 222 | 223 | static int gk20a_determine_L2_size_bytes(struct gk20a *g) 224 | { 225 | u32 lts_per_ltc; 226 | u32 ways; 227 | u32 sets; 228 | u32 bytes_per_line; 229 | u32 active_ltcs; 230 | u32 cache_size; 231 | 232 | u32 tmp; 233 | u32 active_sets_value; 234 | 235 | tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_cfg1_r()); 236 | ways = hweight32(ltc_ltc0_lts0_tstg_cfg1_active_ways_v(tmp)); 237 | 238 | active_sets_value = ltc_ltc0_lts0_tstg_cfg1_active_sets_v(tmp); 239 | if (active_sets_value == ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v()) { 240 | sets = 64; 241 | } else if (active_sets_value == 242 | ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v()) { 243 | sets = 32; 244 | } else if (active_sets_value == 245 | ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v()) { 246 | sets = 16; 247 | } else { 248 | dev_err(dev_from_gk20a(g), 249 | "Unknown constant %u for active sets", 250 | (unsigned)active_sets_value); 251 | sets = 0; 252 | } 253 | 254 | active_ltcs = g->gr.num_fbps; 255 | 256 | /* chip-specific values */ 257 | lts_per_ltc = 1; 258 | bytes_per_line = 128; 259 | cache_size = active_ltcs * lts_per_ltc * ways * sets * bytes_per_line; 260 | 261 | return cache_size; 262 | } 263 | 264 | void gk20a_init_ltc(struct gpu_ops *gops) 265 | { 266 | gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes; 267 | gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last; 268 | gops->ltc.init_comptags = gk20a_ltc_init_comptags; 269 | gops->ltc.cbc_ctrl = gk20a_ltc_cbc_ctrl; 270 | gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; 271 | gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; 272 | gops->ltc.init_cbc = gk20a_ltc_init_cbc; 273 | #ifdef CONFIG_DEBUG_FS 274 | gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; 275 | #endif 276 | gops->ltc.elpg_flush = gk20a_mm_g_elpg_flush_locked; 277 | gops->ltc.init_fs_state = gk20a_ltc_init_fs_state; 278 | gops->ltc.isr = gk20a_ltc_isr; 279 | } 280 | -------------------------------------------------------------------------------- /gk20a/ltc_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * GK20A L2 3 | * 4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | */ 15 | 16 | #ifndef LTC_GK20A_H 17 | #define LTC_GK20A_H 18 | struct gpu_ops; 19 | 20 | void gk20a_init_ltc(struct gpu_ops *gops); 21 | #endif 22 | -------------------------------------------------------------------------------- /gk20a/mc_gk20a.c: -------------------------------------------------------------------------------- 1 | /* 2 | * GK20A memory interface 3 | * 4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | */ 15 | 16 | #include 17 | 18 | #include "gk20a.h" 19 | #include "mc_gk20a.h" 20 | #include "hw_mc_gk20a.h" 21 | 22 | irqreturn_t mc_gk20a_isr_stall(struct gk20a *g) 23 | { 24 | u32 mc_intr_0; 25 | 26 | if (!g->power_on) 27 | return IRQ_NONE; 28 | 29 | /* not from gpu when sharing irq with others */ 30 | mc_intr_0 = gk20a_readl(g, mc_intr_0_r()); 31 | if (unlikely(!mc_intr_0)) 32 | return IRQ_NONE; 33 | 34 | gk20a_writel(g, mc_intr_en_0_r(), 35 | mc_intr_en_0_inta_disabled_f()); 36 | 37 | /* flush previous write */ 38 | gk20a_readl(g, mc_intr_en_0_r()); 39 | 40 | return IRQ_WAKE_THREAD; 41 | } 42 | 43 | irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g) 44 | { 45 | u32 mc_intr_1; 46 | 47 | if (!g->power_on) 48 | return IRQ_NONE; 49 | 50 | /* not from gpu when sharing irq with others */ 51 | mc_intr_1 = gk20a_readl(g, mc_intr_1_r()); 52 | if (unlikely(!mc_intr_1)) 53 | return IRQ_NONE; 54 | 55 | gk20a_writel(g, mc_intr_en_1_r(), 56 | mc_intr_en_1_inta_disabled_f()); 57 | 58 | /* flush previous write */ 59 | gk20a_readl(g, mc_intr_en_1_r()); 60 | 61 | return IRQ_WAKE_THREAD; 62 | } 63 | 64 | irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g) 65 | { 66 | u32 mc_intr_0; 67 | 68 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); 69 | 70 | mc_intr_0 = gk20a_readl(g, mc_intr_0_r()); 71 | 72 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); 73 | 74 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) 75 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); 76 | if (mc_intr_0 & mc_intr_0_pfifo_pending_f()) 77 | gk20a_fifo_isr(g); 78 | if (mc_intr_0 & mc_intr_0_pmu_pending_f()) 79 | gk20a_pmu_isr(g); 80 | if (mc_intr_0 & mc_intr_0_priv_ring_pending_f()) 81 | gk20a_priv_ring_isr(g); 82 | if (mc_intr_0 & mc_intr_0_ltc_pending_f()) 83 | g->ops.ltc.isr(g); 84 | if (mc_intr_0 & mc_intr_0_pbus_pending_f()) 85 | gk20a_pbus_isr(g); 86 | 87 | gk20a_writel(g, mc_intr_en_0_r(), 88 | mc_intr_en_0_inta_hardware_f()); 89 | 90 | /* flush previous write */ 91 | gk20a_readl(g, mc_intr_en_0_r()); 92 | 93 | return IRQ_HANDLED; 94 | } 95 | 96 | irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g) 97 | { 98 | u32 mc_intr_1; 99 | 100 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); 101 | 102 | mc_intr_1 = gk20a_readl(g, mc_intr_1_r()); 103 | 104 | gk20a_dbg(gpu_dbg_intr, "non-stall intr %08x\n", mc_intr_1); 105 | 106 | if (mc_intr_1 & mc_intr_0_pfifo_pending_f()) 107 | gk20a_fifo_nonstall_isr(g); 108 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) 109 | gk20a_gr_nonstall_isr(g); 110 | 111 | gk20a_writel(g, mc_intr_en_1_r(), 112 | mc_intr_en_1_inta_hardware_f()); 113 | 114 | /* flush previous write */ 115 | gk20a_readl(g, mc_intr_en_1_r()); 116 | 117 | return IRQ_HANDLED; 118 | } 119 | 120 | void mc_gk20a_intr_enable(struct gk20a *g) 121 | { 122 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); 123 | 124 | gk20a_writel(g, mc_intr_mask_1_r(), 125 | mc_intr_0_pfifo_pending_f() 126 | | eng_intr_mask); 127 | gk20a_writel(g, mc_intr_en_1_r(), 128 | mc_intr_en_1_inta_hardware_f()); 129 | 130 | gk20a_writel(g, mc_intr_mask_0_r(), 131 | mc_intr_0_pfifo_pending_f() 132 | | mc_intr_0_priv_ring_pending_f() 133 | | mc_intr_0_ltc_pending_f() 134 | | mc_intr_0_pbus_pending_f() 135 | | eng_intr_mask); 136 | gk20a_writel(g, mc_intr_en_0_r(), 137 | mc_intr_en_0_inta_hardware_f()); 138 | } 139 | 140 | void gk20a_init_mc(struct gpu_ops *gops) 141 | { 142 | gops->mc.intr_enable = mc_gk20a_intr_enable; 143 | gops->mc.isr_stall = mc_gk20a_isr_stall; 144 | gops->mc.isr_nonstall = mc_gk20a_isr_nonstall; 145 | gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall; 146 | gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall; 147 | } 148 | -------------------------------------------------------------------------------- /gk20a/mc_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | */ 13 | 14 | #ifndef MC_GK20A_H 15 | #define MC_GK20A_H 16 | struct gk20a; 17 | 18 | void gk20a_init_mc(struct gpu_ops *gops); 19 | void mc_gk20a_intr_enable(struct gk20a *g); 20 | irqreturn_t mc_gk20a_isr_stall(struct gk20a *g); 21 | irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g); 22 | irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g); 23 | irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g); 24 | #endif 25 | -------------------------------------------------------------------------------- /gk20a/platform_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/soc/platform_gk20a.h 3 | * 4 | * GK20A Platform (SoC) Interface 5 | * 6 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | */ 17 | 18 | #ifndef _GK20A_PLATFORM_H_ 19 | #define _GK20A_PLATFORM_H_ 20 | 21 | #include 22 | #include 23 | #include 24 | 25 | struct gk20a; 26 | struct channel_gk20a; 27 | struct gr_ctx_buffer_desc; 28 | struct gk20a_scale_profile; 29 | 30 | struct secure_page_buffer { 31 | void (*destroy)(struct platform_device *, struct secure_page_buffer *); 32 | size_t size; 33 | u64 iova; 34 | struct dma_attrs attrs; 35 | }; 36 | 37 | struct gk20a_platform { 38 | #ifdef CONFIG_TEGRA_GK20A 39 | u32 syncpt_base; 40 | #endif 41 | /* Populated by the gk20a driver before probing the platform. */ 42 | struct gk20a *g; 43 | 44 | /* Should be populated at probe. */ 45 | bool can_railgate; 46 | 47 | /* Should be populated at probe. */ 48 | bool has_syncpoints; 49 | 50 | /* Should be populated by probe. */ 51 | struct dentry *debugfs; 52 | 53 | /* Clock configuration is stored here. Platform probe is responsible 54 | * for filling this data. */ 55 | struct clk *clk[3]; 56 | int num_clks; 57 | 58 | /* Delay before rail gated */ 59 | int railgate_delay; 60 | 61 | /* Delay before clock gated */ 62 | int clockgate_delay; 63 | 64 | /* Second Level Clock Gating: true = enable false = disable */ 65 | bool enable_slcg; 66 | 67 | /* Block Level Clock Gating: true = enable flase = disable */ 68 | bool enable_blcg; 69 | 70 | /* Engine Level Clock Gating: true = enable flase = disable */ 71 | bool enable_elcg; 72 | 73 | /* Engine Level Power Gating: true = enable flase = disable */ 74 | bool enable_elpg; 75 | 76 | /* Adaptative ELPG: true = enable flase = disable */ 77 | bool enable_aelpg; 78 | 79 | /* 80 | * gk20a_do_idle() API can take GPU either into rail gate or CAR reset 81 | * This flag can be used to force CAR reset case instead of rail gate 82 | */ 83 | bool force_reset_in_do_idle; 84 | 85 | /* Default big page size 64K or 128K */ 86 | u32 default_big_page_size; 87 | 88 | /* Initialize the platform interface of the gk20a driver. 89 | * 90 | * The platform implementation of this function must 91 | * - set the power and clocks of the gk20a device to a known 92 | * state, and 93 | * - populate the gk20a_platform structure (a pointer to the 94 | * structure can be obtained by calling gk20a_get_platform). 95 | * 96 | * After this function is finished, the driver will initialise 97 | * pm runtime and genpd based on the platform configuration. 98 | */ 99 | int (*probe)(struct platform_device *dev); 100 | 101 | /* Second stage initialisation - called once all power management 102 | * initialisations are done. 103 | */ 104 | int (*late_probe)(struct platform_device *dev); 105 | 106 | /* Poweron platform dependencies */ 107 | int (*busy)(struct platform_device *dev); 108 | 109 | /* Powerdown platform dependencies */ 110 | void (*idle)(struct platform_device *dev); 111 | 112 | /* This function is called to allocate secure memory (memory that the 113 | * CPU cannot see). The function should fill the context buffer 114 | * descriptor (especially fields destroy, sgt, size). 115 | */ 116 | int (*secure_alloc)(struct platform_device *dev, 117 | struct gr_ctx_buffer_desc *desc, 118 | size_t size); 119 | 120 | /* Function to allocate a secure buffer of PAGE_SIZE at probe time. 121 | * This is also helpful to trigger secure memory resizing 122 | * while GPU is off 123 | */ 124 | int (*secure_page_alloc)(struct platform_device *dev); 125 | struct secure_page_buffer secure_buffer; 126 | bool secure_alloc_ready; 127 | 128 | /* Device is going to be suspended */ 129 | int (*suspend)(struct device *); 130 | 131 | /* Called to turn off the device */ 132 | int (*railgate)(struct platform_device *dev); 133 | 134 | /* Called to turn on the device */ 135 | int (*unrailgate)(struct platform_device *dev); 136 | struct mutex railgate_lock; 137 | 138 | /* Called to check state of device */ 139 | bool (*is_railgated)(struct platform_device *dev); 140 | 141 | /* Postscale callback is called after frequency change */ 142 | void (*postscale)(struct platform_device *pdev, 143 | unsigned long freq); 144 | 145 | /* Pre callback is called before frequency change */ 146 | void (*prescale)(struct platform_device *pdev); 147 | 148 | /* Devfreq governor name. If scaling is enabled, we request 149 | * this governor to be used in scaling */ 150 | const char *devfreq_governor; 151 | 152 | /* Quality of service id. If this is set, the scaling routines 153 | * will register a callback to id. Each time we receive a new value, 154 | * the postscale callback gets called. */ 155 | int qos_id; 156 | 157 | /* Called as part of debug dump. If the gpu gets hung, this function 158 | * is responsible for delivering all necessary debug data of other 159 | * hw units which may interact with the gpu without direct supervision 160 | * of the CPU. 161 | */ 162 | void (*dump_platform_dependencies)(struct platform_device *dev); 163 | 164 | /* Callbacks to assert/deassert GPU reset */ 165 | int (*reset_assert)(struct platform_device *pdev); 166 | int (*reset_deassert)(struct platform_device *pdev); 167 | struct clk *clk_reset; 168 | 169 | bool virtual_dev; 170 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION 171 | u64 virt_handle; 172 | struct task_struct *intr_handler; 173 | #endif 174 | }; 175 | 176 | static inline struct gk20a_platform *gk20a_get_platform( 177 | struct platform_device *dev) 178 | { 179 | return (struct gk20a_platform *)platform_get_drvdata(dev); 180 | } 181 | 182 | extern struct gk20a_platform gk20a_generic_platform; 183 | 184 | static inline bool gk20a_platform_has_syncpoints(struct platform_device *dev) 185 | { 186 | struct gk20a_platform *p = gk20a_get_platform(dev); 187 | return p->has_syncpoints; 188 | } 189 | 190 | int gk20a_tegra_busy(struct platform_device *dev); 191 | void gk20a_tegra_idle(struct platform_device *dev); 192 | void gk20a_tegra_debug_dump(struct platform_device *pdev); 193 | 194 | #endif 195 | -------------------------------------------------------------------------------- /gk20a/platform_gk20a_generic.c: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/platform_gk20a_generic.c 3 | * 4 | * GK20A Generic Platform Interface 5 | * 6 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | * 17 | * You should have received a copy of the GNU General Public License 18 | * along with this program. If not, see . 19 | */ 20 | 21 | #include 22 | #include 23 | #include 24 | 25 | #include "platform_gk20a.h" 26 | #include "hal_gk20a.h" 27 | #include "gk20a.h" 28 | 29 | /* 30 | * gk20a_generic_is_railgated() 31 | * 32 | * Check status of gk20a power rail 33 | */ 34 | 35 | static bool gk20a_generic_is_railgated(struct platform_device *pdev) 36 | { 37 | return !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU); 38 | } 39 | 40 | /* 41 | * gk20a_generic_railgate() 42 | * 43 | * Gate (disable) gk20a power rail 44 | */ 45 | 46 | static int gk20a_generic_railgate(struct platform_device *pdev) 47 | { 48 | if (tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) 49 | tegra_powergate_partition(TEGRA_POWERGATE_GPU); 50 | return 0; 51 | } 52 | 53 | /* 54 | * gk20a_generic_unrailgate() 55 | * 56 | * Ungate (enable) gk20a power rail 57 | */ 58 | 59 | static int gk20a_generic_unrailgate(struct platform_device *pdev) 60 | { 61 | tegra_unpowergate_partition(TEGRA_POWERGATE_GPU); 62 | return 0; 63 | } 64 | 65 | /* 66 | * gk20a_generic_get_clocks() 67 | * 68 | * This function finds clocks in tegra platform and populates 69 | * the clock information to gk20a platform data. 70 | */ 71 | 72 | static int gk20a_generic_get_clocks(struct platform_device *pdev) 73 | { 74 | struct gk20a_platform *platform = platform_get_drvdata(pdev); 75 | 76 | platform->clk[0] = clk_get_sys("tegra_gk20a.0", "PLLG_ref"); 77 | platform->clk[1] = clk_get_sys("tegra_gk20a.0", "pwr"); 78 | platform->clk[2] = clk_get_sys("tegra_gk20a.0", "emc"); 79 | platform->num_clks = 3; 80 | 81 | if (IS_ERR(platform->clk[0]) || 82 | IS_ERR(platform->clk[1]) || 83 | IS_ERR(platform->clk[2])) 84 | goto err_get_clock; 85 | 86 | clk_set_rate(platform->clk[0], UINT_MAX); 87 | clk_set_rate(platform->clk[1], 204000000); 88 | clk_set_rate(platform->clk[2], UINT_MAX); 89 | 90 | return 0; 91 | 92 | err_get_clock: 93 | if (!IS_ERR_OR_NULL(platform->clk[0])) 94 | clk_put(platform->clk[0]); 95 | if (!IS_ERR_OR_NULL(platform->clk[1])) 96 | clk_put(platform->clk[1]); 97 | if (!IS_ERR_OR_NULL(platform->clk[2])) 98 | clk_put(platform->clk[2]); 99 | 100 | platform->clk[0] = NULL; 101 | platform->clk[1] = NULL; 102 | platform->clk[2] = NULL; 103 | return -ENODEV; 104 | } 105 | 106 | static int gk20a_generic_probe(struct platform_device *dev) 107 | { 108 | gk20a_generic_get_clocks(dev); 109 | 110 | return 0; 111 | } 112 | 113 | static int gk20a_generic_late_probe(struct platform_device *dev) 114 | { 115 | struct gk20a_platform *platform = gk20a_get_platform(dev); 116 | 117 | /* Make gk20a power domain a subdomain of mc */ 118 | tegra_pd_add_sd(&platform->g->pd); 119 | 120 | return 0; 121 | } 122 | 123 | struct gk20a_platform gk20a_generic_platform = { 124 | .railgate = gk20a_generic_railgate, 125 | .unrailgate = gk20a_generic_unrailgate, 126 | .is_railgated = gk20a_generic_is_railgated, 127 | 128 | .probe = gk20a_generic_probe, 129 | .late_probe = gk20a_generic_late_probe, 130 | .default_big_page_size = SZ_128K, 131 | }; 132 | -------------------------------------------------------------------------------- /gk20a/priv_ring_gk20a.c: -------------------------------------------------------------------------------- 1 | /* 2 | * GK20A priv ring 3 | * 4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | 19 | #include /* for mdelay */ 20 | 21 | #include "gk20a.h" 22 | #include "hw_mc_gk20a.h" 23 | #include "hw_pri_ringmaster_gk20a.h" 24 | #include "hw_pri_ringstation_sys_gk20a.h" 25 | #include "hw_trim_gk20a.h" 26 | 27 | void gk20a_reset_priv_ring(struct gk20a *g) 28 | { 29 | u32 data; 30 | 31 | data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); 32 | data = set_field(data, 33 | trim_sys_gpc2clk_out_bypdiv_m(), 34 | trim_sys_gpc2clk_out_bypdiv_f(0)); 35 | gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); 36 | 37 | gk20a_reset(g, mc_enable_priv_ring_enabled_f()); 38 | 39 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) 40 | g->ops.clock_gating.slcg_priring_load_gating_prod(g, 41 | g->slcg_enabled); 42 | 43 | gk20a_writel(g,pri_ringmaster_command_r(), 44 | 0x4); 45 | 46 | gk20a_writel(g, pri_ringstation_sys_decode_config_r(), 47 | 0x2); 48 | 49 | gk20a_readl(g, pri_ringstation_sys_decode_config_r()); 50 | } 51 | 52 | void gk20a_priv_ring_isr(struct gk20a *g) 53 | { 54 | u32 status0, status1; 55 | u32 cmd; 56 | s32 retry = 100; 57 | 58 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); 59 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); 60 | 61 | gk20a_dbg_info("ringmaster intr status0: 0x%08x," 62 | "status1: 0x%08x", status0, status1); 63 | 64 | if (status0 & (0x1 | 0x2 | 0x4)) { 65 | gk20a_reset_priv_ring(g); 66 | } 67 | 68 | cmd = gk20a_readl(g, pri_ringmaster_command_r()); 69 | cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), 70 | pri_ringmaster_command_cmd_ack_interrupt_f()); 71 | gk20a_writel(g, pri_ringmaster_command_r(), cmd); 72 | 73 | do { 74 | cmd = pri_ringmaster_command_cmd_v( 75 | gk20a_readl(g, pri_ringmaster_command_r())); 76 | usleep_range(20, 40); 77 | } while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && --retry); 78 | 79 | if (retry <= 0) 80 | gk20a_warn(dev_from_gk20a(g), 81 | "priv ringmaster cmd ack too many retries"); 82 | 83 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); 84 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); 85 | 86 | gk20a_dbg_info("ringmaster intr status0: 0x%08x," 87 | " status1: 0x%08x", status0, status1); 88 | } 89 | 90 | -------------------------------------------------------------------------------- /gk20a/priv_ring_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/priv_ring_gk20a.h 3 | * 4 | * GK20A PRIV ringmaster 5 | * 6 | * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | * 17 | * You should have received a copy of the GNU General Public License along with 18 | * this program; if not, write to the Free Software Foundation, Inc., 19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 | */ 21 | #ifndef __PRIV_RING_GK20A_H__ 22 | #define __PRIV_RING_GK20A_H__ 23 | 24 | void gk20a_reset_priv_ring(struct gk20a *g); 25 | void gk20a_priv_ring_isr(struct gk20a *g); 26 | 27 | #endif /*__PRIV_RING_GK20A_H__*/ 28 | -------------------------------------------------------------------------------- /gk20a/regops_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Tegra GK20A GPU Debugger Driver Register Ops 3 | * 4 | * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | #ifndef REGOPS_GK20A_H 19 | #define REGOPS_GK20A_H 20 | 21 | #include 22 | 23 | struct regop_offset_range { 24 | u32 base:24; 25 | u32 count:8; 26 | }; 27 | 28 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, 29 | struct nvgpu_dbg_gpu_reg_op *ops, 30 | u64 num_ops); 31 | 32 | /* turn seriously unwieldy names -> something shorter */ 33 | #define REGOP(x) NVGPU_DBG_GPU_REG_OP_##x 34 | 35 | static inline bool reg_op_is_gr_ctx(u8 type) 36 | { 37 | return type == REGOP(TYPE_GR_CTX) || 38 | type == REGOP(TYPE_GR_CTX_TPC) || 39 | type == REGOP(TYPE_GR_CTX_SM) || 40 | type == REGOP(TYPE_GR_CTX_CROP) || 41 | type == REGOP(TYPE_GR_CTX_ZROP) || 42 | type == REGOP(TYPE_GR_CTX_QUAD); 43 | } 44 | static inline bool reg_op_is_read(u8 op) 45 | { 46 | return op == REGOP(READ_32) || 47 | op == REGOP(READ_64) ; 48 | } 49 | 50 | bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset); 51 | 52 | void gk20a_init_regops(struct gpu_ops *gops); 53 | #endif /* REGOPS_GK20A_H */ 54 | -------------------------------------------------------------------------------- /gk20a/semaphore_gk20a.c: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/semaphore_gk20a.c 3 | * 4 | * GK20A Semaphores 5 | * 6 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | */ 17 | 18 | #include "semaphore_gk20a.h" 19 | #include 20 | #include 21 | #include "gk20a.h" 22 | #include "mm_gk20a.h" 23 | 24 | static const int SEMAPHORE_SIZE = 16; 25 | 26 | struct gk20a_semaphore_pool *gk20a_semaphore_pool_alloc(struct device *d, 27 | const char *unique_name, size_t capacity) 28 | { 29 | struct gk20a_semaphore_pool *p; 30 | p = kzalloc(sizeof(*p), GFP_KERNEL); 31 | if (!p) 32 | return NULL; 33 | 34 | kref_init(&p->ref); 35 | INIT_LIST_HEAD(&p->maps); 36 | mutex_init(&p->maps_mutex); 37 | p->dev = d; 38 | 39 | /* Alloc one 4k page of semaphore per channel. */ 40 | p->size = roundup(capacity * SEMAPHORE_SIZE, PAGE_SIZE); 41 | p->cpu_va = dma_alloc_coherent(d, p->size, &p->iova, GFP_KERNEL); 42 | if (!p->cpu_va) 43 | goto clean_up; 44 | if (gk20a_get_sgtable(d, &p->sgt, p->cpu_va, p->iova, p->size)) 45 | goto clean_up; 46 | 47 | if (gk20a_allocator_init(&p->alloc, unique_name, 0, 48 | p->size)) 49 | goto clean_up; 50 | 51 | gk20a_dbg_info("cpuva=%p iova=%llx phys=%llx", p->cpu_va, 52 | (u64)sg_dma_address(p->sgt->sgl), (u64)sg_phys(p->sgt->sgl)); 53 | return p; 54 | clean_up: 55 | if (p->cpu_va) 56 | dma_free_coherent(d, p->size, p->cpu_va, p->iova); 57 | if (p->sgt) 58 | gk20a_free_sgtable(&p->sgt); 59 | kfree(p); 60 | return NULL; 61 | } 62 | 63 | static void gk20a_semaphore_pool_free(struct kref *ref) 64 | { 65 | struct gk20a_semaphore_pool *p = 66 | container_of(ref, struct gk20a_semaphore_pool, ref); 67 | mutex_lock(&p->maps_mutex); 68 | WARN_ON(!list_empty(&p->maps)); 69 | mutex_unlock(&p->maps_mutex); 70 | gk20a_free_sgtable(&p->sgt); 71 | dma_free_coherent(p->dev, p->size, p->cpu_va, p->iova); 72 | gk20a_allocator_destroy(&p->alloc); 73 | kfree(p); 74 | } 75 | 76 | static void gk20a_semaphore_pool_get(struct gk20a_semaphore_pool *p) 77 | { 78 | kref_get(&p->ref); 79 | } 80 | 81 | void gk20a_semaphore_pool_put(struct gk20a_semaphore_pool *p) 82 | { 83 | kref_put(&p->ref, gk20a_semaphore_pool_free); 84 | } 85 | 86 | static struct gk20a_semaphore_pool_map * 87 | gk20a_semaphore_pool_find_map_locked(struct gk20a_semaphore_pool *p, 88 | struct vm_gk20a *vm) 89 | { 90 | struct gk20a_semaphore_pool_map *map, *found = NULL; 91 | list_for_each_entry(map, &p->maps, list) { 92 | if (map->vm == vm) { 93 | found = map; 94 | break; 95 | } 96 | } 97 | return found; 98 | } 99 | 100 | int gk20a_semaphore_pool_map(struct gk20a_semaphore_pool *p, 101 | struct vm_gk20a *vm, 102 | enum gk20a_mem_rw_flag rw_flag) 103 | { 104 | struct gk20a_semaphore_pool_map *map; 105 | 106 | map = kzalloc(sizeof(*map), GFP_KERNEL); 107 | if (!map) 108 | return -ENOMEM; 109 | map->vm = vm; 110 | map->rw_flag = rw_flag; 111 | map->gpu_va = gk20a_gmmu_map(vm, &p->sgt, p->size, 112 | 0/*uncached*/, rw_flag); 113 | if (!map->gpu_va) { 114 | kfree(map); 115 | return -ENOMEM; 116 | } 117 | gk20a_vm_get(vm); 118 | 119 | mutex_lock(&p->maps_mutex); 120 | WARN_ON(gk20a_semaphore_pool_find_map_locked(p, vm)); 121 | list_add(&map->list, &p->maps); 122 | mutex_unlock(&p->maps_mutex); 123 | return 0; 124 | } 125 | 126 | void gk20a_semaphore_pool_unmap(struct gk20a_semaphore_pool *p, 127 | struct vm_gk20a *vm) 128 | { 129 | struct gk20a_semaphore_pool_map *map; 130 | WARN_ON(!vm); 131 | 132 | mutex_lock(&p->maps_mutex); 133 | map = gk20a_semaphore_pool_find_map_locked(p, vm); 134 | if (map) { 135 | gk20a_gmmu_unmap(vm, map->gpu_va, p->size, map->rw_flag); 136 | gk20a_vm_put(vm); 137 | list_del(&map->list); 138 | kfree(map); 139 | } 140 | mutex_unlock(&p->maps_mutex); 141 | } 142 | 143 | u64 gk20a_semaphore_pool_gpu_va(struct gk20a_semaphore_pool *p, 144 | struct vm_gk20a *vm) 145 | { 146 | struct gk20a_semaphore_pool_map *map; 147 | u64 gpu_va = 0; 148 | 149 | mutex_lock(&p->maps_mutex); 150 | map = gk20a_semaphore_pool_find_map_locked(p, vm); 151 | if (map) 152 | gpu_va = map->gpu_va; 153 | mutex_unlock(&p->maps_mutex); 154 | 155 | return gpu_va; 156 | } 157 | 158 | struct gk20a_semaphore *gk20a_semaphore_alloc(struct gk20a_semaphore_pool *pool) 159 | { 160 | struct gk20a_semaphore *s; 161 | 162 | s = kzalloc(sizeof(*s), GFP_KERNEL); 163 | if (!s) 164 | return NULL; 165 | 166 | if (pool->alloc.alloc(&pool->alloc, &s->offset, SEMAPHORE_SIZE, 167 | SEMAPHORE_SIZE)) { 168 | gk20a_err(pool->dev, "failed to allocate semaphore"); 169 | kfree(s); 170 | return NULL; 171 | } 172 | 173 | gk20a_semaphore_pool_get(pool); 174 | s->pool = pool; 175 | 176 | kref_init(&s->ref); 177 | s->value = (volatile u32 *)((uintptr_t)pool->cpu_va + s->offset); 178 | *s->value = 0; /* Initially acquired. */ 179 | gk20a_dbg_info("created semaphore offset=%d, value_cpu=%p, value=%d", 180 | s->offset, s->value, *s->value); 181 | return s; 182 | } 183 | 184 | static void gk20a_semaphore_free(struct kref *ref) 185 | { 186 | struct gk20a_semaphore *s = 187 | container_of(ref, struct gk20a_semaphore, ref); 188 | 189 | s->pool->alloc.free(&s->pool->alloc, s->offset, SEMAPHORE_SIZE, 190 | SEMAPHORE_SIZE); 191 | gk20a_semaphore_pool_put(s->pool); 192 | kfree(s); 193 | } 194 | 195 | void gk20a_semaphore_put(struct gk20a_semaphore *s) 196 | { 197 | kref_put(&s->ref, gk20a_semaphore_free); 198 | } 199 | 200 | void gk20a_semaphore_get(struct gk20a_semaphore *s) 201 | { 202 | kref_get(&s->ref); 203 | } 204 | -------------------------------------------------------------------------------- /gk20a/semaphore_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | */ 13 | 14 | #ifndef SEMAPHORE_GK20A_H 15 | #define SEMAPHORE_GK20A_H 16 | 17 | #include 18 | #include "gk20a_allocator.h" 19 | #include "mm_gk20a.h" 20 | 21 | /* A memory pool for holding semaphores. */ 22 | struct gk20a_semaphore_pool { 23 | void *cpu_va; 24 | dma_addr_t iova; 25 | size_t size; 26 | struct device *dev; 27 | struct sg_table *sgt; 28 | struct list_head maps; 29 | struct mutex maps_mutex; 30 | struct kref ref; 31 | struct gk20a_allocator alloc; 32 | }; 33 | 34 | enum gk20a_mem_rw_flag { 35 | gk20a_mem_flag_none = 0, 36 | gk20a_mem_flag_read_only = 1, 37 | gk20a_mem_flag_write_only = 2, 38 | }; 39 | 40 | /* A semaphore pool can be mapped to multiple GPU address spaces. */ 41 | struct gk20a_semaphore_pool_map { 42 | u64 gpu_va; 43 | enum gk20a_mem_rw_flag rw_flag; 44 | struct vm_gk20a *vm; 45 | struct list_head list; 46 | }; 47 | 48 | /* A semaphore that lives inside a semaphore pool. */ 49 | struct gk20a_semaphore { 50 | struct gk20a_semaphore_pool *pool; 51 | u32 offset; /* byte offset within pool */ 52 | struct kref ref; 53 | /* value is a pointer within the pool's coherent cpu_va. 54 | * It is shared between CPU and GPU, hence volatile. */ 55 | volatile u32 *value; /* 0=acquired, 1=released */ 56 | }; 57 | 58 | /* Create a semaphore pool that can hold at most 'capacity' semaphores. */ 59 | struct gk20a_semaphore_pool * 60 | gk20a_semaphore_pool_alloc(struct device *, const char *unique_name, 61 | size_t capacity); 62 | void gk20a_semaphore_pool_put(struct gk20a_semaphore_pool *); 63 | int gk20a_semaphore_pool_map(struct gk20a_semaphore_pool *, 64 | struct vm_gk20a *, 65 | enum gk20a_mem_rw_flag); 66 | void gk20a_semaphore_pool_unmap(struct gk20a_semaphore_pool *, 67 | struct vm_gk20a *); 68 | u64 gk20a_semaphore_pool_gpu_va(struct gk20a_semaphore_pool *, 69 | struct vm_gk20a *); 70 | 71 | /* Allocate a semaphore from the semaphore pool. The newly allocated 72 | * semaphore will be in acquired state (value=0). */ 73 | struct gk20a_semaphore * 74 | gk20a_semaphore_alloc(struct gk20a_semaphore_pool *); 75 | void gk20a_semaphore_put(struct gk20a_semaphore *); 76 | void gk20a_semaphore_get(struct gk20a_semaphore *); 77 | 78 | static inline u64 gk20a_semaphore_gpu_va(struct gk20a_semaphore *s, 79 | struct vm_gk20a *vm) 80 | { 81 | return gk20a_semaphore_pool_gpu_va(s->pool, vm) + s->offset; 82 | } 83 | 84 | static inline bool gk20a_semaphore_is_acquired(struct gk20a_semaphore *s) 85 | { 86 | u32 v = *s->value; 87 | 88 | /* When often block on value reaching a certain threshold. We must make 89 | * sure that if we get unblocked, we haven't read anything too early. */ 90 | smp_rmb(); 91 | return v == 0; 92 | } 93 | 94 | static inline void gk20a_semaphore_release(struct gk20a_semaphore *s) 95 | { 96 | smp_wmb(); 97 | *s->value = 1; 98 | } 99 | #endif 100 | -------------------------------------------------------------------------------- /gk20a/sync_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/sync_gk20a.h 3 | * 4 | * GK20A Sync Framework Integration 5 | * 6 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | */ 17 | 18 | #ifndef _GK20A_SYNC_H_ 19 | #define _GK20A_SYNC_H_ 20 | 21 | #include 22 | 23 | struct sync_timeline; 24 | struct sync_fence; 25 | struct sync_pt; 26 | struct gk20a_semaphore; 27 | 28 | #ifdef CONFIG_SYNC 29 | struct sync_timeline *gk20a_sync_timeline_create(const char *fmt, ...); 30 | void gk20a_sync_timeline_destroy(struct sync_timeline *); 31 | void gk20a_sync_timeline_signal(struct sync_timeline *); 32 | struct sync_fence *gk20a_sync_fence_create(struct sync_timeline *, 33 | struct gk20a_semaphore *, 34 | struct sync_fence *dependency, 35 | const char *fmt, ...); 36 | struct sync_fence *gk20a_sync_fence_fdget(int fd); 37 | #else 38 | static inline void gk20a_sync_timeline_destroy(struct sync_timeline *obj) {} 39 | static inline void gk20a_sync_timeline_signal(struct sync_timeline *obj) {} 40 | static inline struct sync_fence *gk20a_sync_fence_fdget(int fd) 41 | { 42 | return NULL; 43 | } 44 | #endif 45 | 46 | #endif 47 | -------------------------------------------------------------------------------- /gk20a/therm_gk20a.c: -------------------------------------------------------------------------------- 1 | /* 2 | * drivers/video/tegra/host/gk20a/therm_gk20a.c 3 | * 4 | * GK20A Therm 5 | * 6 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * This program is free software; you can redistribute it and/or modify it 9 | * under the terms and conditions of the GNU General Public License, 10 | * version 2, as published by the Free Software Foundation. 11 | * 12 | * This program is distributed in the hope it will be useful, but WITHOUT 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 | * more details. 16 | * 17 | * You should have received a copy of the GNU General Public License along with 18 | * this program; if not, write to the Free Software Foundation, Inc., 19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 | */ 21 | 22 | #include "gk20a.h" 23 | #include "hw_gr_gk20a.h" 24 | #include "hw_therm_gk20a.h" 25 | 26 | static int gk20a_init_therm_reset_enable_hw(struct gk20a *g) 27 | { 28 | return 0; 29 | } 30 | 31 | static int gk20a_init_therm_setup_sw(struct gk20a *g) 32 | { 33 | return 0; 34 | } 35 | 36 | static int gk20a_init_therm_setup_hw(struct gk20a *g) 37 | { 38 | /* program NV_THERM registers */ 39 | gk20a_writel(g, therm_use_a_r(), NV_THERM_USE_A_INIT); 40 | gk20a_writel(g, therm_evt_ext_therm_0_r(), 41 | NV_THERM_EVT_EXT_THERM_0_INIT); 42 | gk20a_writel(g, therm_evt_ext_therm_1_r(), 43 | NV_THERM_EVT_EXT_THERM_1_INIT); 44 | gk20a_writel(g, therm_evt_ext_therm_2_r(), 45 | NV_THERM_EVT_EXT_THERM_2_INIT); 46 | 47 | return 0; 48 | } 49 | 50 | int gk20a_init_therm_support(struct gk20a *g) 51 | { 52 | u32 err; 53 | 54 | gk20a_dbg_fn(""); 55 | 56 | err = gk20a_init_therm_reset_enable_hw(g); 57 | if (err) 58 | return err; 59 | 60 | err = gk20a_init_therm_setup_sw(g); 61 | if (err) 62 | return err; 63 | 64 | err = gk20a_init_therm_setup_hw(g); 65 | if (err) 66 | return err; 67 | 68 | return err; 69 | } 70 | -------------------------------------------------------------------------------- /gk20a/therm_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2011 - 2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | #ifndef THERM_GK20A_H 17 | #define THERM_GK20A_H 18 | 19 | /* priority for EXT_THERM_0 event set to highest */ 20 | #define NV_THERM_EVT_EXT_THERM_0_INIT 0x3000100 21 | #define NV_THERM_EVT_EXT_THERM_1_INIT 0x2000200 22 | #define NV_THERM_EVT_EXT_THERM_2_INIT 0x1000300 23 | /* configures the thermal events that may cause clock slowdown */ 24 | #define NV_THERM_USE_A_INIT 0x7 25 | 26 | int gk20a_init_therm_support(struct gk20a *g); 27 | 28 | #endif /* THERM_GK20A_H */ 29 | -------------------------------------------------------------------------------- /gk20a/tsg_gk20a.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | 25 | #include "gk20a.h" 26 | #include "hw_ccsr_gk20a.h" 27 | 28 | static void gk20a_tsg_release(struct kref *ref); 29 | 30 | bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch) 31 | { 32 | return !(ch->tsgid == NVGPU_INVALID_TSG_ID); 33 | } 34 | 35 | static bool gk20a_is_channel_active(struct gk20a *g, struct channel_gk20a *ch) 36 | { 37 | struct fifo_gk20a *f = &g->fifo; 38 | struct fifo_runlist_info_gk20a *runlist; 39 | int i; 40 | 41 | for (i = 0; i < f->max_runlists; ++i) { 42 | runlist = &f->runlist_info[i]; 43 | if (test_bit(ch->hw_chid, runlist->active_channels)) 44 | return true; 45 | } 46 | 47 | return false; 48 | } 49 | 50 | /* 51 | * API to mark channel as part of TSG 52 | * 53 | * Note that channel is not runnable when we bind it to TSG 54 | */ 55 | static int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, int ch_fd) 56 | { 57 | struct file *f = fget(ch_fd); 58 | struct channel_gk20a *ch; 59 | 60 | gk20a_dbg_fn(""); 61 | 62 | ch = gk20a_get_channel_from_file(ch_fd); 63 | if (!ch) 64 | return -EINVAL; 65 | 66 | /* check if channel is already bound to some TSG */ 67 | if (gk20a_is_channel_marked_as_tsg(ch)) { 68 | fput(f); 69 | return -EINVAL; 70 | } 71 | 72 | /* channel cannot be bound to TSG if it is already active */ 73 | if (gk20a_is_channel_active(tsg->g, ch)) { 74 | fput(f); 75 | return -EINVAL; 76 | } 77 | 78 | ch->tsgid = tsg->tsgid; 79 | 80 | mutex_lock(&tsg->ch_list_lock); 81 | list_add_tail(&ch->ch_entry, &tsg->ch_list); 82 | mutex_unlock(&tsg->ch_list_lock); 83 | 84 | kref_get(&tsg->refcount); 85 | 86 | gk20a_dbg(gpu_dbg_fn, "BIND tsg:%d channel:%d\n", 87 | tsg->tsgid, ch->hw_chid); 88 | 89 | fput(f); 90 | 91 | gk20a_dbg_fn("done"); 92 | return 0; 93 | } 94 | 95 | int gk20a_tsg_unbind_channel(struct channel_gk20a *ch) 96 | { 97 | struct fifo_gk20a *f = &ch->g->fifo; 98 | struct tsg_gk20a *tsg = &f->tsg[ch->tsgid]; 99 | 100 | mutex_lock(&tsg->ch_list_lock); 101 | list_del_init(&ch->ch_entry); 102 | mutex_unlock(&tsg->ch_list_lock); 103 | 104 | kref_put(&tsg->refcount, gk20a_tsg_release); 105 | 106 | ch->tsgid = NVGPU_INVALID_TSG_ID; 107 | 108 | return 0; 109 | } 110 | 111 | int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid) 112 | { 113 | struct tsg_gk20a *tsg = NULL; 114 | 115 | if (tsgid < 0 || tsgid >= g->fifo.num_channels) 116 | return -EINVAL; 117 | 118 | tsg = &g->fifo.tsg[tsgid]; 119 | 120 | tsg->in_use = false; 121 | tsg->tsgid = tsgid; 122 | 123 | INIT_LIST_HEAD(&tsg->ch_list); 124 | mutex_init(&tsg->ch_list_lock); 125 | 126 | return 0; 127 | } 128 | 129 | static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg) 130 | { 131 | mutex_lock(&f->tsg_inuse_mutex); 132 | f->tsg[tsg->tsgid].in_use = false; 133 | mutex_unlock(&f->tsg_inuse_mutex); 134 | } 135 | 136 | static struct tsg_gk20a *acquire_unused_tsg(struct fifo_gk20a *f) 137 | { 138 | struct tsg_gk20a *tsg = NULL; 139 | int tsgid; 140 | 141 | mutex_lock(&f->tsg_inuse_mutex); 142 | for (tsgid = 0; tsgid < f->num_channels; tsgid++) { 143 | if (!f->tsg[tsgid].in_use) { 144 | f->tsg[tsgid].in_use = true; 145 | tsg = &f->tsg[tsgid]; 146 | break; 147 | } 148 | } 149 | mutex_unlock(&f->tsg_inuse_mutex); 150 | 151 | return tsg; 152 | } 153 | 154 | int gk20a_tsg_open(struct gk20a *g, struct file *filp) 155 | { 156 | struct tsg_gk20a *tsg; 157 | struct device *dev; 158 | 159 | dev = dev_from_gk20a(g); 160 | 161 | gk20a_dbg(gpu_dbg_fn, "tsg: %s", dev_name(dev)); 162 | 163 | tsg = acquire_unused_tsg(&g->fifo); 164 | if (!tsg) 165 | return -ENOMEM; 166 | 167 | tsg->g = g; 168 | tsg->num_active_channels = 0; 169 | kref_init(&tsg->refcount); 170 | 171 | tsg->tsg_gr_ctx = NULL; 172 | tsg->vm = NULL; 173 | 174 | filp->private_data = tsg; 175 | 176 | gk20a_dbg(gpu_dbg_fn, "tsg opened %d\n", tsg->tsgid); 177 | 178 | return 0; 179 | } 180 | 181 | int gk20a_tsg_dev_open(struct inode *inode, struct file *filp) 182 | { 183 | struct gk20a *g; 184 | int ret; 185 | 186 | g = container_of(inode->i_cdev, 187 | struct gk20a, tsg.cdev); 188 | gk20a_dbg_fn(""); 189 | ret = gk20a_tsg_open(g, filp); 190 | gk20a_dbg_fn("done"); 191 | return ret; 192 | } 193 | 194 | static void gk20a_tsg_release(struct kref *ref) 195 | { 196 | struct tsg_gk20a *tsg = container_of(ref, struct tsg_gk20a, refcount); 197 | struct gk20a *g = tsg->g; 198 | 199 | if (tsg->tsg_gr_ctx) { 200 | gr_gk20a_free_tsg_gr_ctx(tsg); 201 | tsg->tsg_gr_ctx = NULL; 202 | } 203 | if (tsg->vm) { 204 | gk20a_vm_put(tsg->vm); 205 | tsg->vm = NULL; 206 | } 207 | 208 | release_used_tsg(&g->fifo, tsg); 209 | 210 | gk20a_dbg(gpu_dbg_fn, "tsg released %d\n", tsg->tsgid); 211 | } 212 | 213 | int gk20a_tsg_dev_release(struct inode *inode, struct file *filp) 214 | { 215 | struct tsg_gk20a *tsg = filp->private_data; 216 | kref_put(&tsg->refcount, gk20a_tsg_release); 217 | return 0; 218 | } 219 | 220 | long gk20a_tsg_dev_ioctl(struct file *filp, unsigned int cmd, 221 | unsigned long arg) 222 | { 223 | struct tsg_gk20a *tsg = filp->private_data; 224 | struct gk20a *g = tsg->g; 225 | u8 __maybe_unused buf[NVGPU_TSG_IOCTL_MAX_ARG_SIZE]; 226 | int err = 0; 227 | 228 | gk20a_dbg(gpu_dbg_fn, ""); 229 | 230 | if ((_IOC_TYPE(cmd) != NVGPU_TSG_IOCTL_MAGIC) || 231 | (_IOC_NR(cmd) == 0) || 232 | (_IOC_NR(cmd) > NVGPU_TSG_IOCTL_LAST)) 233 | return -EINVAL; 234 | 235 | BUG_ON(_IOC_SIZE(cmd) > NVGPU_TSG_IOCTL_MAX_ARG_SIZE); 236 | 237 | if (_IOC_DIR(cmd) & _IOC_WRITE) { 238 | if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd))) 239 | return -EFAULT; 240 | } 241 | 242 | if (!g->gr.sw_ready) { 243 | err = gk20a_busy(g->dev); 244 | if (err) 245 | return err; 246 | 247 | gk20a_idle(g->dev); 248 | } 249 | 250 | switch (cmd) { 251 | case NVGPU_TSG_IOCTL_BIND_CHANNEL: 252 | { 253 | int ch_fd = *(int *)buf; 254 | if (ch_fd < 0) { 255 | err = -EINVAL; 256 | break; 257 | } 258 | err = gk20a_tsg_bind_channel(tsg, ch_fd); 259 | break; 260 | } 261 | 262 | case NVGPU_TSG_IOCTL_UNBIND_CHANNEL: 263 | /* We do not support explicitly unbinding channel from TSG. 264 | * Channel will be unbounded from TSG when it is closed. 265 | */ 266 | break; 267 | 268 | case NVGPU_IOCTL_TSG_ENABLE: 269 | { 270 | struct channel_gk20a *ch; 271 | err = gk20a_busy(g->dev); 272 | if (err) { 273 | gk20a_err(&g->dev->dev, 274 | "failed to host gk20a for ioctl cmd: 0x%x", cmd); 275 | return err; 276 | } 277 | mutex_lock(&tsg->ch_list_lock); 278 | list_for_each_entry(ch, &tsg->ch_list, ch_entry) { 279 | gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), 280 | gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) 281 | | ccsr_channel_enable_set_true_f()); 282 | } 283 | mutex_unlock(&tsg->ch_list_lock); 284 | gk20a_idle(g->dev); 285 | break; 286 | } 287 | 288 | case NVGPU_IOCTL_TSG_DISABLE: 289 | { 290 | struct channel_gk20a *ch; 291 | err = gk20a_busy(g->dev); 292 | if (err) { 293 | gk20a_err(&g->dev->dev, 294 | "failed to host gk20a for ioctl cmd: 0x%x", cmd); 295 | return err; 296 | } 297 | mutex_lock(&tsg->ch_list_lock); 298 | list_for_each_entry(ch, &tsg->ch_list, ch_entry) { 299 | gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), 300 | gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) 301 | | ccsr_channel_enable_clr_true_f()); 302 | } 303 | mutex_unlock(&tsg->ch_list_lock); 304 | gk20a_idle(g->dev); 305 | break; 306 | } 307 | 308 | case NVGPU_IOCTL_TSG_PREEMPT: 309 | { 310 | err = gk20a_busy(g->dev); 311 | if (err) { 312 | gk20a_err(&g->dev->dev, 313 | "failed to host gk20a for ioctl cmd: 0x%x", cmd); 314 | return err; 315 | } 316 | /* preempt TSG */ 317 | err = gk20a_fifo_preempt_tsg(g, tsg->tsgid); 318 | gk20a_idle(g->dev); 319 | break; 320 | } 321 | 322 | default: 323 | gk20a_err(dev_from_gk20a(g), 324 | "unrecognized tsg gpu ioctl cmd: 0x%x", 325 | cmd); 326 | err = -ENOTTY; 327 | break; 328 | } 329 | 330 | if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ)) 331 | err = copy_to_user((void __user *)arg, 332 | buf, _IOC_SIZE(cmd)); 333 | 334 | return err; 335 | } 336 | -------------------------------------------------------------------------------- /gk20a/tsg_gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * You should have received a copy of the GNU General Public License 14 | * along with this program. If not, see . 15 | */ 16 | #ifndef __TSG_GK20A_H_ 17 | #define __TSG_GK20A_H_ 18 | 19 | #define NVGPU_INVALID_TSG_ID (-1) 20 | 21 | bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch); 22 | 23 | int gk20a_tsg_dev_release(struct inode *inode, struct file *filp); 24 | int gk20a_tsg_dev_open(struct inode *inode, struct file *filp); 25 | int gk20a_tsg_open(struct gk20a *g, struct file *filp); 26 | long gk20a_tsg_dev_ioctl(struct file *filp, 27 | unsigned int cmd, unsigned long arg); 28 | 29 | int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid); 30 | 31 | int gk20a_tsg_unbind_channel(struct channel_gk20a *ch); 32 | 33 | struct tsg_gk20a { 34 | struct gk20a *g; 35 | 36 | bool in_use; 37 | int tsgid; 38 | 39 | struct kref refcount; 40 | 41 | struct list_head ch_list; 42 | int num_active_channels; 43 | struct mutex ch_list_lock; 44 | 45 | struct gr_ctx_desc *tsg_gr_ctx; 46 | 47 | struct vm_gk20a *vm; 48 | }; 49 | 50 | #endif /* __TSG_GK20A_H_ */ 51 | -------------------------------------------------------------------------------- /include/linux/gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * gk20a GPU driver 3 | * 4 | * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | 19 | #ifndef __GK20A_H 20 | #define __GK20A_H 21 | 22 | #include 23 | 24 | struct channel_gk20a; 25 | struct platform_device; 26 | 27 | #ifdef CONFIG_GK20A 28 | int nvhost_vpr_info_fetch(void); 29 | void gk20a_debug_dump_device(struct platform_device *pdev); 30 | int gk20a_do_idle(void); 31 | int gk20a_do_unidle(void); 32 | #else 33 | static inline void gk20a_debug_dump_device(struct platform_device *pdev) {} 34 | static inline int nvhost_vpr_info_fetch(void) 35 | { 36 | return -ENOSYS; 37 | } 38 | static inline int gk20a_do_idle(void) { return -ENOSYS; } 39 | static inline int gk20a_do_unidle(void) { return -ENOSYS; } 40 | #endif 41 | #endif 42 | -------------------------------------------------------------------------------- /include/trace/events/gk20a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * gk20a event logging to ftrace. 3 | * 4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms and conditions of the GNU General Public License, 8 | * version 2, as published by the Free Software Foundation. 9 | * 10 | * This program is distributed in the hope it will be useful, but WITHOUT 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 | * more details. 14 | */ 15 | 16 | #undef TRACE_SYSTEM 17 | #define TRACE_SYSTEM gk20a 18 | 19 | #if !defined(_TRACE_GK20A_H) || defined(TRACE_HEADER_MULTI_READ) 20 | #define _TRACE_GK20A_H 21 | 22 | #include 23 | #include 24 | 25 | DECLARE_EVENT_CLASS(gk20a, 26 | TP_PROTO(const char *name), 27 | TP_ARGS(name), 28 | TP_STRUCT__entry(__field(const char *, name)), 29 | TP_fast_assign(__entry->name = name;), 30 | TP_printk("name=%s", __entry->name) 31 | ); 32 | 33 | DEFINE_EVENT(gk20a, gk20a_channel_open, 34 | TP_PROTO(const char *name), 35 | TP_ARGS(name) 36 | ); 37 | 38 | DEFINE_EVENT(gk20a, gk20a_channel_release, 39 | TP_PROTO(const char *name), 40 | TP_ARGS(name) 41 | ); 42 | 43 | DEFINE_EVENT(gk20a, gk20a_pm_unrailgate, 44 | TP_PROTO(const char *name), 45 | TP_ARGS(name) 46 | ); 47 | 48 | DEFINE_EVENT(gk20a, gk20a_finalize_poweron, 49 | TP_PROTO(const char *name), 50 | TP_ARGS(name) 51 | ); 52 | 53 | DEFINE_EVENT(gk20a, gk20a_finalize_poweron_done, 54 | TP_PROTO(const char *name), 55 | TP_ARGS(name) 56 | ); 57 | 58 | TRACE_EVENT(gk20a_channel_update, 59 | TP_PROTO(const void *channel), 60 | TP_ARGS(channel), 61 | TP_STRUCT__entry(__field(const void *, channel)), 62 | TP_fast_assign(__entry->channel = channel;), 63 | TP_printk("channel=%p", __entry->channel) 64 | ); 65 | 66 | TRACE_EVENT(gk20a_push_cmdbuf, 67 | TP_PROTO(const char *name, u32 mem_id, 68 | u32 words, u32 offset, void *cmdbuf), 69 | 70 | TP_ARGS(name, mem_id, words, offset, cmdbuf), 71 | 72 | TP_STRUCT__entry( 73 | __field(const char *, name) 74 | __field(u32, mem_id) 75 | __field(u32, words) 76 | __field(u32, offset) 77 | __field(bool, cmdbuf) 78 | __dynamic_array(u32, cmdbuf, words) 79 | ), 80 | 81 | TP_fast_assign( 82 | if (cmdbuf) { 83 | memcpy(__get_dynamic_array(cmdbuf), cmdbuf+offset, 84 | words * sizeof(u32)); 85 | } 86 | __entry->cmdbuf = cmdbuf; 87 | __entry->name = name; 88 | __entry->mem_id = mem_id; 89 | __entry->words = words; 90 | __entry->offset = offset; 91 | ), 92 | 93 | TP_printk("name=%s, mem_id=%08x, words=%u, offset=%d, contents=[%s]", 94 | __entry->name, __entry->mem_id, 95 | __entry->words, __entry->offset, 96 | __print_hex(__get_dynamic_array(cmdbuf), 97 | __entry->cmdbuf ? __entry->words * 4 : 0)) 98 | ); 99 | 100 | TRACE_EVENT(gk20a_channel_submit_gpfifo, 101 | TP_PROTO(const char *name, u32 hw_chid, u32 num_entries, 102 | u32 flags, u32 wait_id, u32 wait_value), 103 | 104 | TP_ARGS(name, hw_chid, num_entries, flags, wait_id, wait_value), 105 | 106 | TP_STRUCT__entry( 107 | __field(const char *, name) 108 | __field(u32, hw_chid) 109 | __field(u32, num_entries) 110 | __field(u32, flags) 111 | __field(u32, wait_id) 112 | __field(u32, wait_value) 113 | ), 114 | 115 | TP_fast_assign( 116 | __entry->name = name; 117 | __entry->hw_chid = hw_chid; 118 | __entry->num_entries = num_entries; 119 | __entry->flags = flags; 120 | __entry->wait_id = wait_id; 121 | __entry->wait_value = wait_value; 122 | ), 123 | 124 | TP_printk("name=%s, hw_chid=%d, num_entries=%u, flags=%u, wait_id=%d," 125 | " wait_value=%u", 126 | __entry->name, __entry->hw_chid, __entry->num_entries, 127 | __entry->flags, __entry->wait_id, __entry->wait_value) 128 | ); 129 | 130 | TRACE_EVENT(gk20a_channel_submitted_gpfifo, 131 | TP_PROTO(const char *name, u32 hw_chid, u32 num_entries, 132 | u32 flags, u32 incr_id, u32 incr_value), 133 | 134 | TP_ARGS(name, hw_chid, num_entries, flags, 135 | incr_id, incr_value), 136 | 137 | TP_STRUCT__entry( 138 | __field(const char *, name) 139 | __field(u32, hw_chid) 140 | __field(u32, num_entries) 141 | __field(u32, flags) 142 | __field(u32, incr_id) 143 | __field(u32, incr_value) 144 | ), 145 | 146 | TP_fast_assign( 147 | __entry->name = name; 148 | __entry->hw_chid = hw_chid; 149 | __entry->num_entries = num_entries; 150 | __entry->flags = flags; 151 | __entry->incr_id = incr_id; 152 | __entry->incr_value = incr_value; 153 | ), 154 | 155 | TP_printk("name=%s, hw_chid=%d, num_entries=%u, flags=%u," 156 | " incr_id=%u, incr_value=%u", 157 | __entry->name, __entry->hw_chid, __entry->num_entries, 158 | __entry->flags, __entry->incr_id, __entry->incr_value) 159 | ); 160 | 161 | 162 | TRACE_EVENT(gk20a_as_dev_open, 163 | TP_PROTO(const char *name), 164 | TP_ARGS(name), 165 | TP_STRUCT__entry( 166 | __field(const char *, name) 167 | ), 168 | TP_fast_assign( 169 | __entry->name = name; 170 | ), 171 | TP_printk("name=%s ", __entry->name) 172 | ); 173 | 174 | TRACE_EVENT(gk20a_as_dev_release, 175 | TP_PROTO(const char *name), 176 | TP_ARGS(name), 177 | TP_STRUCT__entry( 178 | __field(const char *, name) 179 | ), 180 | TP_fast_assign( 181 | __entry->name = name; 182 | ), 183 | TP_printk("name=%s ", __entry->name) 184 | ); 185 | 186 | 187 | TRACE_EVENT(gk20a_as_ioctl_bind_channel, 188 | TP_PROTO(const char *name), 189 | TP_ARGS(name), 190 | TP_STRUCT__entry( 191 | __field(const char *, name) 192 | ), 193 | TP_fast_assign( 194 | __entry->name = name; 195 | ), 196 | TP_printk("name=%s ", __entry->name) 197 | ); 198 | 199 | 200 | TRACE_EVENT(gk20a_as_ioctl_alloc_space, 201 | TP_PROTO(const char *name), 202 | TP_ARGS(name), 203 | TP_STRUCT__entry( 204 | __field(const char *, name) 205 | ), 206 | TP_fast_assign( 207 | __entry->name = name; 208 | ), 209 | TP_printk("name=%s ", __entry->name) 210 | ); 211 | 212 | TRACE_EVENT(gk20a_as_ioctl_free_space, 213 | TP_PROTO(const char *name), 214 | TP_ARGS(name), 215 | TP_STRUCT__entry( 216 | __field(const char *, name) 217 | ), 218 | TP_fast_assign( 219 | __entry->name = name; 220 | ), 221 | TP_printk("name=%s ", __entry->name) 222 | ); 223 | 224 | TRACE_EVENT(gk20a_as_ioctl_map_buffer, 225 | TP_PROTO(const char *name), 226 | TP_ARGS(name), 227 | TP_STRUCT__entry( 228 | __field(const char *, name) 229 | ), 230 | TP_fast_assign( 231 | __entry->name = name; 232 | ), 233 | TP_printk("name=%s ", __entry->name) 234 | ); 235 | 236 | TRACE_EVENT(gk20a_as_ioctl_unmap_buffer, 237 | TP_PROTO(const char *name), 238 | TP_ARGS(name), 239 | TP_STRUCT__entry( 240 | __field(const char *, name) 241 | ), 242 | TP_fast_assign( 243 | __entry->name = name; 244 | ), 245 | TP_printk("name=%s ", __entry->name) 246 | ); 247 | 248 | TRACE_EVENT(gk20a_as_ioctl_get_va_regions, 249 | TP_PROTO(const char *name), 250 | TP_ARGS(name), 251 | TP_STRUCT__entry( 252 | __field(const char *, name) 253 | ), 254 | TP_fast_assign( 255 | __entry->name = name; 256 | ), 257 | TP_printk("name=%s ", __entry->name) 258 | ); 259 | 260 | TRACE_EVENT(gk20a_mmu_fault, 261 | TP_PROTO(u32 fault_hi, u32 fault_lo, 262 | u32 fault_info, 263 | u32 instance, 264 | u32 engine_id, 265 | const char *engine, 266 | const char *client, 267 | const char *fault_type), 268 | TP_ARGS(fault_hi, fault_lo, fault_info, 269 | instance, engine_id, engine, client, fault_type), 270 | TP_STRUCT__entry( 271 | __field(u32, fault_hi) 272 | __field(u32, fault_lo) 273 | __field(u32, fault_info) 274 | __field(u32, instance) 275 | __field(u32, engine_id) 276 | __field(const char *, engine) 277 | __field(const char *, client) 278 | __field(const char *, fault_type) 279 | ), 280 | TP_fast_assign( 281 | __entry->fault_hi = fault_hi; 282 | __entry->fault_lo = fault_lo; 283 | __entry->fault_info = fault_info; 284 | __entry->instance = instance; 285 | __entry->engine_id = engine_id; 286 | __entry->engine = engine; 287 | __entry->client = client; 288 | __entry->fault_type = fault_type; 289 | ), 290 | TP_printk("fault=0x%x,%08x info=0x%x instance=0x%x engine_id=%d engine=%s client=%s type=%s", 291 | __entry->fault_hi, __entry->fault_lo, 292 | __entry->fault_info, __entry->instance, __entry->engine_id, 293 | __entry->engine, __entry->client, __entry->fault_type) 294 | ); 295 | 296 | #endif /* _TRACE_GK20A_H */ 297 | 298 | /* This part must be outside protection */ 299 | #include 300 | -------------------------------------------------------------------------------- /scripts/nvgpu_ucode/README: -------------------------------------------------------------------------------- 1 | Use for fecs.bin, gpccs.bin and add results to drivers/gpu/nvgpu/. If you see 2 | something like: 3 | 4 | unknown falcon ucode boot signature 0x4d6cbc10 with reg_offset 0x00000000 5 | 6 | in the boot logs, then the kernel needs to be updated to know the signatures 7 | and abi of the new ucode boot binaries. 8 | -------------------------------------------------------------------------------- /scripts/nvgpu_ucode/ucodesignature.py: -------------------------------------------------------------------------------- 1 | import sys, struct 2 | headersize = 16 3 | sizeof_u32 = 4 4 | ucode = open(sys.argv[1]).read()[headersize:] 5 | assert struct.calcsize("I") == sizeof_u32 6 | fmt = "I" * (len(ucode) / sizeof_u32) 7 | ints = struct.unpack(fmt, ucode) 8 | print len(ucode), "bytes" 9 | print "sig =", hex(sum(ints) & 0xffffffff) 10 | --------------------------------------------------------------------------------