├── .gitignore ├── LICENSE ├── LICENSE-CODE ├── OAI_CONFIG_LIST ├── README.md ├── autogen ├── THIRD_PARTY_OSS_LICENSE ├── THIRD_PARTY_OSS_LICENSE-CODE ├── __init__.py ├── _pydantic.py ├── agentchat │ ├── __init__.py │ ├── agent.py │ ├── assistant_agent.py │ ├── chat.py │ ├── contrib │ │ ├── __init__.py │ │ ├── agent_builder.py │ │ ├── agent_optimizer.py │ │ ├── capabilities │ │ │ ├── __init__.py │ │ │ ├── agent_capability.py │ │ │ ├── context_handling.py │ │ │ ├── generate_images.py │ │ │ ├── teachability.py │ │ │ ├── transform_messages.py │ │ │ ├── transforms.py │ │ │ └── vision_capability.py │ │ ├── compressible_agent.py │ │ ├── gpt_assistant_agent.py │ │ ├── img_utils.py │ │ ├── llava_agent.py │ │ ├── math_user_proxy_agent.py │ │ ├── multimodal_conversable_agent.py │ │ ├── phi_image_agent.py │ │ ├── qdrant_retrieve_user_proxy_agent.py │ │ ├── retrieve_assistant_agent.py │ │ ├── retrieve_user_proxy_agent.py │ │ ├── society_of_mind_agent.py │ │ ├── text_analyzer_agent.py │ │ ├── vectordb │ │ │ ├── __init__.py │ │ │ ├── base.py │ │ │ ├── chromadb.py │ │ │ ├── pgvectordb.py │ │ │ └── utils.py │ │ └── web_surfer.py │ ├── conversable_agent.py │ ├── groupchat.py │ ├── os_assistant_agent.py │ ├── os_conversable_agent.py │ ├── user_proxy_agent.py │ └── utils.py ├── browser_utils.py ├── cache │ ├── __init__.py │ ├── abstract_cache_base.py │ ├── cache.py │ ├── cache_factory.py │ ├── disk_cache.py │ ├── in_memory_cache.py │ └── redis_cache.py ├── code_utils.py ├── coding │ ├── __init__.py │ ├── base.py │ ├── docker_commandline_code_executor.py │ ├── factory.py │ ├── func_with_reqs.py │ ├── jupyter │ │ ├── __init__.py │ │ ├── base.py │ │ ├── docker_jupyter_server.py │ │ ├── embedded_ipython_code_executor.py │ │ ├── jupyter_client.py │ │ ├── jupyter_code_executor.py │ │ └── local_jupyter_server.py │ ├── local_commandline_code_executor.py │ ├── markdown_code_extractor.py │ └── utils.py ├── exception_utils.py ├── extensions │ └── __init__.py ├── formatting_utils.py ├── function_utils.py ├── graph_utils.py ├── io │ ├── __init__.py │ ├── base.py │ ├── console.py │ └── websockets.py ├── logger │ ├── __init__.py │ ├── base_logger.py │ ├── logger_factory.py │ ├── logger_utils.py │ └── sqlite_logger.py ├── math_utils.py ├── oai │ ├── __init__.py │ ├── client.py │ ├── completion.py │ ├── gemini.py │ └── openai_utils.py ├── retrieve_utils.py ├── runtime_logging.py ├── token_count_utils.py ├── types.py └── version.py ├── hardware_agent ├── examples │ └── VerilogCoder │ │ ├── ICL_examples.py │ │ ├── OS_prompt_templates.py │ │ ├── Tool_examples.py │ │ ├── debug_graph_analyzer.py │ │ ├── llm_prompt_manager.py │ │ ├── load_verilog_cases.py │ │ ├── prompt_templates.py │ │ ├── pyverilog │ │ ├── LICENSE │ │ ├── README.md │ │ ├── examples │ │ │ ├── Makefile │ │ │ ├── example_active_analyzer.py │ │ │ ├── example_active_range.py │ │ │ ├── example_ast_code.py │ │ │ ├── example_codegen.py │ │ │ ├── example_controlflow_analyzer.py │ │ │ ├── example_dataflow_analyzer.py │ │ │ ├── example_dataflow_codegen.py │ │ │ ├── example_graphgen.py │ │ │ ├── example_identifierreplace.py │ │ │ ├── example_identifiervisitor.py │ │ │ ├── example_lexer.py │ │ │ ├── example_merge.py │ │ │ ├── example_optimizer.py │ │ │ ├── example_parser.py │ │ │ ├── example_preprocessor.py │ │ │ ├── example_subset.py │ │ │ ├── example_top_logic_graph.py │ │ │ └── example_walker.py │ │ ├── pyverilog │ │ │ ├── Makefile │ │ │ ├── VERSION │ │ │ ├── __init__.py │ │ │ ├── ast_code_generator │ │ │ │ ├── Makefile │ │ │ │ ├── __init__.py │ │ │ │ ├── codegen.py │ │ │ │ ├── list_ast.txt │ │ │ │ ├── template │ │ │ │ │ ├── __init__.py │ │ │ │ │ ├── always.txt │ │ │ │ │ ├── and.txt │ │ │ │ │ ├── assign.txt │ │ │ │ │ ├── block.txt │ │ │ │ │ ├── blockingsubstitution.txt │ │ │ │ │ ├── case.txt │ │ │ │ │ ├── casestatement.txt │ │ │ │ │ ├── casexstatement.txt │ │ │ │ │ ├── concat.txt │ │ │ │ │ ├── cond.txt │ │ │ │ │ ├── constant.txt │ │ │ │ │ ├── decl.txt │ │ │ │ │ ├── delaystatement.txt │ │ │ │ │ ├── description.txt │ │ │ │ │ ├── disable.txt │ │ │ │ │ ├── divide.txt │ │ │ │ │ ├── eq.txt │ │ │ │ │ ├── eql.txt │ │ │ │ │ ├── eventstatement.txt │ │ │ │ │ ├── floatconst.txt │ │ │ │ │ ├── foreverstatement.txt │ │ │ │ │ ├── forstatement.txt │ │ │ │ │ ├── function.txt │ │ │ │ │ ├── functioncall.txt │ │ │ │ │ ├── generatestatement.txt │ │ │ │ │ ├── genvar.txt │ │ │ │ │ ├── greatereq.txt │ │ │ │ │ ├── greaterthan.txt │ │ │ │ │ ├── identifier.txt │ │ │ │ │ ├── identifierscope.txt │ │ │ │ │ ├── identifierscopelabel.txt │ │ │ │ │ ├── ifstatement.txt │ │ │ │ │ ├── initial.txt │ │ │ │ │ ├── inout.txt │ │ │ │ │ ├── input.txt │ │ │ │ │ ├── instance.txt │ │ │ │ │ ├── instancelist.txt │ │ │ │ │ ├── intconst.txt │ │ │ │ │ ├── integer.txt │ │ │ │ │ ├── ioport.txt │ │ │ │ │ ├── land.txt │ │ │ │ │ ├── lconcat.txt │ │ │ │ │ ├── length.txt │ │ │ │ │ ├── lesseq.txt │ │ │ │ │ ├── lessthan.txt │ │ │ │ │ ├── localparam.txt │ │ │ │ │ ├── lor.txt │ │ │ │ │ ├── lvalue.txt │ │ │ │ │ ├── minus.txt │ │ │ │ │ ├── mod.txt │ │ │ │ │ ├── moduledef.txt │ │ │ │ │ ├── nonblockingsubstitution.txt │ │ │ │ │ ├── noteq.txt │ │ │ │ │ ├── noteql.txt │ │ │ │ │ ├── operator.txt │ │ │ │ │ ├── or.txt │ │ │ │ │ ├── output.txt │ │ │ │ │ ├── parallelblock.txt │ │ │ │ │ ├── paramarg.txt │ │ │ │ │ ├── parameter.txt │ │ │ │ │ ├── paramlist.txt │ │ │ │ │ ├── partselect.txt │ │ │ │ │ ├── plus.txt │ │ │ │ │ ├── pointer.txt │ │ │ │ │ ├── port.txt │ │ │ │ │ ├── portarg.txt │ │ │ │ │ ├── portlist.txt │ │ │ │ │ ├── power.txt │ │ │ │ │ ├── pragma.txt │ │ │ │ │ ├── pragmaentry.txt │ │ │ │ │ ├── real.txt │ │ │ │ │ ├── reg.txt │ │ │ │ │ ├── repeat.txt │ │ │ │ │ ├── rvalue.txt │ │ │ │ │ ├── sens.txt │ │ │ │ │ ├── senslist.txt │ │ │ │ │ ├── singlestatement.txt │ │ │ │ │ ├── sla.txt │ │ │ │ │ ├── sll.txt │ │ │ │ │ ├── source.txt │ │ │ │ │ ├── sra.txt │ │ │ │ │ ├── srl.txt │ │ │ │ │ ├── stringconst.txt │ │ │ │ │ ├── substitution.txt │ │ │ │ │ ├── systemcall.txt │ │ │ │ │ ├── task.txt │ │ │ │ │ ├── times.txt │ │ │ │ │ ├── tri.txt │ │ │ │ │ ├── uand.txt │ │ │ │ │ ├── ulnot.txt │ │ │ │ │ ├── uminus.txt │ │ │ │ │ ├── unand.txt │ │ │ │ │ ├── unaryoperator.txt │ │ │ │ │ ├── unor.txt │ │ │ │ │ ├── unot.txt │ │ │ │ │ ├── uor.txt │ │ │ │ │ ├── uplus.txt │ │ │ │ │ ├── uxnor.txt │ │ │ │ │ ├── uxor.txt │ │ │ │ │ ├── value.txt │ │ │ │ │ ├── variable.txt │ │ │ │ │ ├── waitstatement.txt │ │ │ │ │ ├── whilestatement.txt │ │ │ │ │ ├── width.txt │ │ │ │ │ ├── wire.txt │ │ │ │ │ ├── xnor.txt │ │ │ │ │ └── xor.txt │ │ │ │ └── touch.py │ │ │ ├── controlflow │ │ │ │ ├── Makefile │ │ │ │ ├── __init__.py │ │ │ │ ├── __pycache__ │ │ │ │ │ ├── __init__.cpython-310.pyc │ │ │ │ │ ├── controlflow_analyzer.cpython-310.pyc │ │ │ │ │ ├── splitter.cpython-310.pyc │ │ │ │ │ └── transition.cpython-310.pyc │ │ │ │ ├── active_analyzer.py │ │ │ │ ├── active_range.py │ │ │ │ ├── controlflow_analyzer.py │ │ │ │ ├── splitter.py │ │ │ │ └── transition.py │ │ │ ├── dataflow │ │ │ │ ├── Makefile │ │ │ │ ├── __init__.py │ │ │ │ ├── __pycache__ │ │ │ │ │ ├── __init__.cpython-310.pyc │ │ │ │ │ ├── bindvisitor.cpython-310.pyc │ │ │ │ │ ├── dataflow.cpython-310.pyc │ │ │ │ │ ├── dataflow_analyzer.cpython-310.pyc │ │ │ │ │ ├── merge.cpython-310.pyc │ │ │ │ │ ├── modulevisitor.cpython-310.pyc │ │ │ │ │ ├── optimizer.cpython-310.pyc │ │ │ │ │ ├── reorder.cpython-310.pyc │ │ │ │ │ ├── replace.cpython-310.pyc │ │ │ │ │ ├── signalvisitor.cpython-310.pyc │ │ │ │ │ ├── subset.cpython-310.pyc │ │ │ │ │ ├── visit.cpython-310.pyc │ │ │ │ │ └── walker.cpython-310.pyc │ │ │ │ ├── bindvisitor.py │ │ │ │ ├── dataflow.py │ │ │ │ ├── dataflow_analyzer.py │ │ │ │ ├── dataflow_codegen.py │ │ │ │ ├── graphgen.py │ │ │ │ ├── merge.py │ │ │ │ ├── modulevisitor.py │ │ │ │ ├── optimizer.py │ │ │ │ ├── reorder.py │ │ │ │ ├── replace.py │ │ │ │ ├── signalvisitor.py │ │ │ │ ├── subset.py │ │ │ │ ├── visit.py │ │ │ │ └── walker.py │ │ │ ├── utils │ │ │ │ ├── Makefile │ │ │ │ ├── __init__.py │ │ │ │ ├── __pycache__ │ │ │ │ │ ├── __init__.cpython-310.pyc │ │ │ │ │ ├── inference.cpython-310.pyc │ │ │ │ │ ├── op2mark.cpython-310.pyc │ │ │ │ │ ├── scope.cpython-310.pyc │ │ │ │ │ ├── signaltype.cpython-310.pyc │ │ │ │ │ ├── util.cpython-310.pyc │ │ │ │ │ └── verror.cpython-310.pyc │ │ │ │ ├── identifierreplace.py │ │ │ │ ├── identifiervisitor.py │ │ │ │ ├── inference.py │ │ │ │ ├── op2mark.py │ │ │ │ ├── scope.py │ │ │ │ ├── signaltype.py │ │ │ │ ├── util.py │ │ │ │ └── verror.py │ │ │ └── vparser │ │ │ │ ├── Makefile │ │ │ │ ├── __init__.py │ │ │ │ ├── ast.py │ │ │ │ ├── lexer.py │ │ │ │ ├── parser.py │ │ │ │ └── preprocessor.py │ │ ├── pyverilog_version │ │ └── scripts │ │ │ ├── test-python2.sh │ │ │ ├── test-python3.sh │ │ │ └── upload_pypi.sh │ │ ├── run_verilog_coder.py │ │ ├── task_planner.py │ │ ├── vcd_waveform_analyzer.py │ │ ├── verilog-eval-v2 │ │ ├── dataset_dumpall │ │ │ ├── Prob001_zero_prompt.txt │ │ │ ├── Prob001_zero_ref.sv │ │ │ ├── Prob001_zero_test.sv │ │ │ ├── Prob002_m2014_q4i_prompt.txt │ │ │ ├── Prob002_m2014_q4i_ref.sv │ │ │ ├── Prob002_m2014_q4i_test.sv │ │ │ ├── Prob003_step_one_prompt.txt │ │ │ ├── Prob003_step_one_ref.sv │ │ │ ├── Prob003_step_one_test.sv │ │ │ ├── Prob004_vector2_prompt.txt │ │ │ ├── Prob004_vector2_ref.sv │ │ │ ├── Prob004_vector2_test.sv │ │ │ ├── Prob005_notgate_prompt.txt │ │ │ ├── Prob005_notgate_ref.sv │ │ │ ├── Prob005_notgate_test.sv │ │ │ ├── Prob006_vectorr_prompt.txt │ │ │ ├── Prob006_vectorr_ref.sv │ │ │ ├── Prob006_vectorr_test.sv │ │ │ ├── Prob007_wire_prompt.txt │ │ │ ├── Prob007_wire_ref.sv │ │ │ ├── Prob007_wire_test.sv │ │ │ ├── Prob008_m2014_q4h_prompt.txt │ │ │ ├── Prob008_m2014_q4h_ref.sv │ │ │ ├── Prob008_m2014_q4h_test.sv │ │ │ ├── Prob009_popcount3_prompt.txt │ │ │ ├── Prob009_popcount3_ref.sv │ │ │ ├── Prob009_popcount3_test.sv │ │ │ ├── Prob010_mt2015_q4a_prompt.txt │ │ │ ├── Prob010_mt2015_q4a_ref.sv │ │ │ ├── Prob010_mt2015_q4a_test.sv │ │ │ ├── Prob011_norgate_prompt.txt │ │ │ ├── Prob011_norgate_ref.sv │ │ │ ├── Prob011_norgate_test.sv │ │ │ ├── Prob012_xnorgate_prompt.txt │ │ │ ├── Prob012_xnorgate_ref.sv │ │ │ ├── Prob012_xnorgate_test.sv │ │ │ ├── Prob013_m2014_q4e_prompt.txt │ │ │ ├── Prob013_m2014_q4e_ref.sv │ │ │ ├── Prob013_m2014_q4e_test.sv │ │ │ ├── Prob014_andgate_prompt.txt │ │ │ ├── Prob014_andgate_ref.sv │ │ │ ├── Prob014_andgate_test.sv │ │ │ ├── Prob015_vector1_prompt.txt │ │ │ ├── Prob015_vector1_ref.sv │ │ │ ├── Prob015_vector1_test.sv │ │ │ ├── Prob016_m2014_q4j_prompt.txt │ │ │ ├── Prob016_m2014_q4j_ref.sv │ │ │ ├── Prob016_m2014_q4j_test.sv │ │ │ ├── Prob017_mux2to1v_prompt.txt │ │ │ ├── Prob017_mux2to1v_ref.sv │ │ │ ├── Prob017_mux2to1v_test.sv │ │ │ ├── Prob018_mux256to1_prompt.txt │ │ │ ├── Prob018_mux256to1_ref.sv │ │ │ ├── Prob018_mux256to1_test.sv │ │ │ ├── Prob019_m2014_q4f_prompt.txt │ │ │ ├── Prob019_m2014_q4f_ref.sv │ │ │ ├── Prob019_m2014_q4f_test.sv │ │ │ ├── Prob020_mt2015_eq2_prompt.txt │ │ │ ├── Prob020_mt2015_eq2_ref.sv │ │ │ ├── Prob020_mt2015_eq2_test.sv │ │ │ ├── Prob021_mux256to1v_prompt.txt │ │ │ ├── Prob021_mux256to1v_ref.sv │ │ │ ├── Prob021_mux256to1v_test.sv │ │ │ ├── Prob022_mux2to1_prompt.txt │ │ │ ├── Prob022_mux2to1_ref.sv │ │ │ ├── Prob022_mux2to1_test.sv │ │ │ ├── Prob023_vector100r_prompt.txt │ │ │ ├── Prob023_vector100r_ref.sv │ │ │ ├── Prob023_vector100r_test.sv │ │ │ ├── Prob024_hadd_prompt.txt │ │ │ ├── Prob024_hadd_ref.sv │ │ │ ├── Prob024_hadd_test.sv │ │ │ ├── Prob025_reduction_prompt.txt │ │ │ ├── Prob025_reduction_ref.sv │ │ │ ├── Prob025_reduction_test.sv │ │ │ ├── Prob026_alwaysblock1_prompt.txt │ │ │ ├── Prob026_alwaysblock1_ref.sv │ │ │ ├── Prob026_alwaysblock1_test.sv │ │ │ ├── Prob027_fadd_prompt.txt │ │ │ ├── Prob027_fadd_ref.sv │ │ │ ├── Prob027_fadd_test.sv │ │ │ ├── Prob028_m2014_q4a_prompt.txt │ │ │ ├── Prob028_m2014_q4a_ref.sv │ │ │ ├── Prob028_m2014_q4a_test.sv │ │ │ ├── Prob029_m2014_q4g_prompt.txt │ │ │ ├── Prob029_m2014_q4g_ref.sv │ │ │ ├── Prob029_m2014_q4g_test.sv │ │ │ ├── Prob030_popcount255_prompt.txt │ │ │ ├── Prob030_popcount255_ref.sv │ │ │ ├── Prob030_popcount255_test.sv │ │ │ ├── Prob031_dff_prompt.txt │ │ │ ├── Prob031_dff_ref.sv │ │ │ ├── Prob031_dff_test.sv │ │ │ ├── Prob032_vector0_prompt.txt │ │ │ ├── Prob032_vector0_ref.sv │ │ │ ├── Prob032_vector0_test.sv │ │ │ ├── Prob033_ece241_2014_q1c_prompt.txt │ │ │ ├── Prob033_ece241_2014_q1c_ref.sv │ │ │ ├── Prob033_ece241_2014_q1c_test.sv │ │ │ ├── Prob034_dff8_prompt.txt │ │ │ ├── Prob034_dff8_ref.sv │ │ │ ├── Prob034_dff8_test.sv │ │ │ ├── Prob035_count1to10_prompt.txt │ │ │ ├── Prob035_count1to10_ref.sv │ │ │ ├── Prob035_count1to10_test.sv │ │ │ ├── Prob036_ringer_prompt.txt │ │ │ ├── Prob036_ringer_ref.sv │ │ │ ├── Prob036_ringer_test.sv │ │ │ ├── Prob037_review2015_count1k_prompt.txt │ │ │ ├── Prob037_review2015_count1k_ref.sv │ │ │ ├── Prob037_review2015_count1k_test.sv │ │ │ ├── Prob038_count15_prompt.txt │ │ │ ├── Prob038_count15_ref.sv │ │ │ ├── Prob038_count15_test.sv │ │ │ ├── Prob039_always_if_prompt.txt │ │ │ ├── Prob039_always_if_ref.sv │ │ │ ├── Prob039_always_if_test.sv │ │ │ ├── Prob040_count10_prompt.txt │ │ │ ├── Prob040_count10_ref.sv │ │ │ ├── Prob040_count10_test.sv │ │ │ ├── Prob041_dff8r_prompt.txt │ │ │ ├── Prob041_dff8r_ref.sv │ │ │ ├── Prob041_dff8r_test.sv │ │ │ ├── Prob042_vector4_prompt.txt │ │ │ ├── Prob042_vector4_ref.sv │ │ │ ├── Prob042_vector4_test.sv │ │ │ ├── Prob043_vector5_prompt.txt │ │ │ ├── Prob043_vector5_ref.sv │ │ │ ├── Prob043_vector5_test.sv │ │ │ ├── Prob044_vectorgates_prompt.txt │ │ │ ├── Prob044_vectorgates_ref.sv │ │ │ ├── Prob044_vectorgates_test.sv │ │ │ ├── Prob045_edgedetect2_prompt.txt │ │ │ ├── Prob045_edgedetect2_ref.sv │ │ │ ├── Prob045_edgedetect2_test.sv │ │ │ ├── Prob046_dff8p_prompt.txt │ │ │ ├── Prob046_dff8p_ref.sv │ │ │ ├── Prob046_dff8p_test.sv │ │ │ ├── Prob047_dff8ar_prompt.txt │ │ │ ├── Prob047_dff8ar_ref.sv │ │ │ ├── Prob047_dff8ar_test.sv │ │ │ ├── Prob048_m2014_q4c_prompt.txt │ │ │ ├── Prob048_m2014_q4c_ref.sv │ │ │ ├── Prob048_m2014_q4c_test.sv │ │ │ ├── Prob049_m2014_q4b_prompt.txt │ │ │ ├── Prob049_m2014_q4b_ref.sv │ │ │ ├── Prob049_m2014_q4b_test.sv │ │ │ ├── Prob050_kmap1_prompt.txt │ │ │ ├── Prob050_kmap1_ref.sv │ │ │ ├── Prob050_kmap1_test.sv │ │ │ ├── Prob051_gates4_prompt.txt │ │ │ ├── Prob051_gates4_ref.sv │ │ │ ├── Prob051_gates4_test.sv │ │ │ ├── Prob052_gates100_prompt.txt │ │ │ ├── Prob052_gates100_ref.sv │ │ │ ├── Prob052_gates100_test.sv │ │ │ ├── Prob053_m2014_q4d_prompt.txt │ │ │ ├── Prob053_m2014_q4d_ref.sv │ │ │ ├── Prob053_m2014_q4d_test.sv │ │ │ ├── Prob054_edgedetect_prompt.txt │ │ │ ├── Prob054_edgedetect_ref.sv │ │ │ ├── Prob054_edgedetect_test.sv │ │ │ ├── Prob055_conditional_prompt.txt │ │ │ ├── Prob055_conditional_ref.sv │ │ │ ├── Prob055_conditional_test.sv │ │ │ ├── Prob056_ece241_2013_q7_prompt.txt │ │ │ ├── Prob056_ece241_2013_q7_ref.sv │ │ │ ├── Prob056_ece241_2013_q7_test.sv │ │ │ ├── Prob057_kmap2_prompt.txt │ │ │ ├── Prob057_kmap2_ref.sv │ │ │ ├── Prob057_kmap2_test.sv │ │ │ ├── Prob058_alwaysblock2_prompt.txt │ │ │ ├── Prob058_alwaysblock2_ref.sv │ │ │ ├── Prob058_alwaysblock2_test.sv │ │ │ ├── Prob059_wire4_prompt.txt │ │ │ ├── Prob059_wire4_ref.sv │ │ │ ├── Prob059_wire4_test.sv │ │ │ ├── Prob060_m2014_q4k_prompt.txt │ │ │ ├── Prob060_m2014_q4k_ref.sv │ │ │ ├── Prob060_m2014_q4k_test.sv │ │ │ ├── Prob061_2014_q4a_prompt.txt │ │ │ ├── Prob061_2014_q4a_ref.sv │ │ │ ├── Prob061_2014_q4a_test.sv │ │ │ ├── Prob062_bugs_mux2.sv │ │ │ ├── Prob062_bugs_mux2_prompt.txt │ │ │ ├── Prob062_bugs_mux2_ref.sv │ │ │ ├── Prob062_bugs_mux2_test.sv │ │ │ ├── Prob063_review2015_shiftcount_prompt.txt │ │ │ ├── Prob063_review2015_shiftcount_ref.sv │ │ │ ├── Prob063_review2015_shiftcount_test.sv │ │ │ ├── Prob064_vector3_prompt.txt │ │ │ ├── Prob064_vector3_ref.sv │ │ │ ├── Prob064_vector3_test.sv │ │ │ ├── Prob065_7420_prompt.txt │ │ │ ├── Prob065_7420_ref.sv │ │ │ ├── Prob065_7420_test.sv │ │ │ ├── Prob066_edgecapture_prompt.txt │ │ │ ├── Prob066_edgecapture_ref.sv │ │ │ ├── Prob066_edgecapture_test.sv │ │ │ ├── Prob067_countslow_prompt.txt │ │ │ ├── Prob067_countslow_ref.sv │ │ │ ├── Prob067_countslow_test.sv │ │ │ ├── Prob068_countbcd_prompt.txt │ │ │ ├── Prob068_countbcd_ref.sv │ │ │ ├── Prob068_countbcd_test.sv │ │ │ ├── Prob069_truthtable1_prompt.txt │ │ │ ├── Prob069_truthtable1_ref.sv │ │ │ ├── Prob069_truthtable1_test.sv │ │ │ ├── Prob070_ece241_2013_q2_prompt.txt │ │ │ ├── Prob070_ece241_2013_q2_ref.sv │ │ │ ├── Prob070_ece241_2013_q2_test.sv │ │ │ ├── Prob071_always_casez_prompt.txt │ │ │ ├── Prob071_always_casez_ref.sv │ │ │ ├── Prob071_always_casez_test.sv │ │ │ ├── Prob072_thermostat_prompt.txt │ │ │ ├── Prob072_thermostat_ref.sv │ │ │ ├── Prob072_thermostat_test.sv │ │ │ ├── Prob073_dff16e_prompt.txt │ │ │ ├── Prob073_dff16e_ref.sv │ │ │ ├── Prob073_dff16e_test.sv │ │ │ ├── Prob074_ece241_2014_q4_prompt.txt │ │ │ ├── Prob074_ece241_2014_q4_ref.sv │ │ │ ├── Prob074_ece241_2014_q4_test.sv │ │ │ ├── Prob075_counter_2bc_prompt.txt │ │ │ ├── Prob075_counter_2bc_ref.sv │ │ │ ├── Prob075_counter_2bc_test.sv │ │ │ ├── Prob076_always_case_prompt.txt │ │ │ ├── Prob076_always_case_ref.sv │ │ │ ├── Prob076_always_case_test.sv │ │ │ ├── Prob077_wire_decl_prompt.txt │ │ │ ├── Prob077_wire_decl_ref.sv │ │ │ ├── Prob077_wire_decl_test.sv │ │ │ ├── Prob078_dualedge_prompt.txt │ │ │ ├── Prob078_dualedge_ref.sv │ │ │ ├── Prob078_dualedge_test.sv │ │ │ ├── Prob079_fsm3onehot_prompt.txt │ │ │ ├── Prob079_fsm3onehot_ref.sv │ │ │ ├── Prob079_fsm3onehot_test.sv │ │ │ ├── Prob080_timer_prompt.txt │ │ │ ├── Prob080_timer_ref.sv │ │ │ ├── Prob080_timer_test.sv │ │ │ ├── Prob081_7458_prompt.txt │ │ │ ├── Prob081_7458_ref.sv │ │ │ ├── Prob081_7458_test.sv │ │ │ ├── Prob082_lfsr32_prompt.txt │ │ │ ├── Prob082_lfsr32_ref.sv │ │ │ ├── Prob082_lfsr32_test.sv │ │ │ ├── Prob083_mt2015_q4b_prompt.txt │ │ │ ├── Prob083_mt2015_q4b_ref.sv │ │ │ ├── Prob083_mt2015_q4b_test.sv │ │ │ ├── Prob084_ece241_2013_q12_prompt.txt │ │ │ ├── Prob084_ece241_2013_q12_ref.sv │ │ │ ├── Prob084_ece241_2013_q12_test.sv │ │ │ ├── Prob085_shift4_prompt.txt │ │ │ ├── Prob085_shift4_ref.sv │ │ │ ├── Prob085_shift4_test.sv │ │ │ ├── Prob086_lfsr5_prompt.txt │ │ │ ├── Prob086_lfsr5_ref.sv │ │ │ ├── Prob086_lfsr5_test.sv │ │ │ ├── Prob087_gates_prompt.txt │ │ │ ├── Prob087_gates_ref.sv │ │ │ ├── Prob087_gates_test.sv │ │ │ ├── Prob088_ece241_2014_q5b_prompt.txt │ │ │ ├── Prob088_ece241_2014_q5b_ref.sv │ │ │ ├── Prob088_ece241_2014_q5b_test.sv │ │ │ ├── Prob089_ece241_2014_q5a_prompt.txt │ │ │ ├── Prob089_ece241_2014_q5a_ref.sv │ │ │ ├── Prob089_ece241_2014_q5a_test.sv │ │ │ ├── Prob090_circuit1_prompt.txt │ │ │ ├── Prob090_circuit1_ref.sv │ │ │ ├── Prob090_circuit1_test.sv │ │ │ ├── Prob091_2012_q2b_prompt.txt │ │ │ ├── Prob091_2012_q2b_ref.sv │ │ │ ├── Prob091_2012_q2b_test.sv │ │ │ ├── Prob092_gatesv100_prompt.txt │ │ │ ├── Prob092_gatesv100_ref.sv │ │ │ ├── Prob092_gatesv100_test.sv │ │ │ ├── Prob093_ece241_2014_q3_prompt.txt │ │ │ ├── Prob093_ece241_2014_q3_ref.sv │ │ │ ├── Prob093_ece241_2014_q3_test.sv │ │ │ ├── Prob094_gatesv_prompt.txt │ │ │ ├── Prob094_gatesv_ref.sv │ │ │ ├── Prob094_gatesv_test.sv │ │ │ ├── Prob095_review2015_fsmshift_prompt.txt │ │ │ ├── Prob095_review2015_fsmshift_ref.sv │ │ │ ├── Prob095_review2015_fsmshift_test.sv │ │ │ ├── Prob096_review2015_fsmseq_prompt.txt │ │ │ ├── Prob096_review2015_fsmseq_ref.sv │ │ │ ├── Prob096_review2015_fsmseq_test.sv │ │ │ ├── Prob097_mux9to1v_prompt.txt │ │ │ ├── Prob097_mux9to1v_ref.sv │ │ │ ├── Prob097_mux9to1v_test.sv │ │ │ ├── Prob098_circuit7_prompt.txt │ │ │ ├── Prob098_circuit7_ref.sv │ │ │ ├── Prob098_circuit7_test.sv │ │ │ ├── Prob099_m2014_q6c_prompt.txt │ │ │ ├── Prob099_m2014_q6c_ref.sv │ │ │ ├── Prob099_m2014_q6c_test.sv │ │ │ ├── Prob100_fsm3comb_prompt.txt │ │ │ ├── Prob100_fsm3comb_ref.sv │ │ │ ├── Prob100_fsm3comb_test.sv │ │ │ ├── Prob101_circuit4_prompt.txt │ │ │ ├── Prob101_circuit4_ref.sv │ │ │ ├── Prob101_circuit4_test.sv │ │ │ ├── Prob102_circuit3_prompt.txt │ │ │ ├── Prob102_circuit3_ref.sv │ │ │ ├── Prob102_circuit3_test.sv │ │ │ ├── Prob103_circuit2_prompt.txt │ │ │ ├── Prob103_circuit2_ref.sv │ │ │ ├── Prob103_circuit2_test.sv │ │ │ ├── Prob104_mt2015_muxdff_prompt.txt │ │ │ ├── Prob104_mt2015_muxdff_ref.sv │ │ │ ├── Prob104_mt2015_muxdff_test.sv │ │ │ ├── Prob105_rotate100_prompt.txt │ │ │ ├── Prob105_rotate100_ref.sv │ │ │ ├── Prob105_rotate100_test.sv │ │ │ ├── Prob106_always_nolatches_prompt.txt │ │ │ ├── Prob106_always_nolatches_ref.sv │ │ │ ├── Prob106_always_nolatches_test.sv │ │ │ ├── Prob107_fsm1s_prompt.txt │ │ │ ├── Prob107_fsm1s_ref.sv │ │ │ ├── Prob107_fsm1s_test.sv │ │ │ ├── Prob108_rule90_prompt.txt │ │ │ ├── Prob108_rule90_ref.sv │ │ │ ├── Prob108_rule90_test.sv │ │ │ ├── Prob109_fsm1_prompt.txt │ │ │ ├── Prob109_fsm1_ref.sv │ │ │ ├── Prob109_fsm1_test.sv │ │ │ ├── Prob110_fsm2_prompt.txt │ │ │ ├── Prob110_fsm2_ref.sv │ │ │ ├── Prob110_fsm2_test.sv │ │ │ ├── Prob111_fsm2s_prompt.txt │ │ │ ├── Prob111_fsm2s_ref.sv │ │ │ ├── Prob111_fsm2s_test.sv │ │ │ ├── Prob112_always_case2_prompt.txt │ │ │ ├── Prob112_always_case2_ref.sv │ │ │ ├── Prob112_always_case2_test.sv │ │ │ ├── Prob113_2012_q1g_prompt.txt │ │ │ ├── Prob113_2012_q1g_ref.sv │ │ │ ├── Prob113_2012_q1g_test.sv │ │ │ ├── Prob114_bugs_case_prompt.txt │ │ │ ├── Prob114_bugs_case_ref.sv │ │ │ ├── Prob114_bugs_case_test.sv │ │ │ ├── Prob115_shift18_prompt.txt │ │ │ ├── Prob115_shift18_ref.sv │ │ │ ├── Prob115_shift18_test.sv │ │ │ ├── Prob116_m2014_q3_prompt.txt │ │ │ ├── Prob116_m2014_q3_ref.sv │ │ │ ├── Prob116_m2014_q3_test.sv │ │ │ ├── Prob117_circuit9_prompt.txt │ │ │ ├── Prob117_circuit9_ref.sv │ │ │ ├── Prob117_circuit9_test.sv │ │ │ ├── Prob118_history_shift_prompt.txt │ │ │ ├── Prob118_history_shift_ref.sv │ │ │ ├── Prob118_history_shift_test.sv │ │ │ ├── Prob119_fsm3_prompt.txt │ │ │ ├── Prob119_fsm3_ref.sv │ │ │ ├── Prob119_fsm3_test.sv │ │ │ ├── Prob120_fsm3s_prompt.txt │ │ │ ├── Prob120_fsm3s_ref.sv │ │ │ ├── Prob120_fsm3s_test.sv │ │ │ ├── Prob121_2014_q3bfsm_prompt.txt │ │ │ ├── Prob121_2014_q3bfsm_ref.sv │ │ │ ├── Prob121_2014_q3bfsm_test.sv │ │ │ ├── Prob122_kmap4_prompt.txt │ │ │ ├── Prob122_kmap4_ref.sv │ │ │ ├── Prob122_kmap4_test.sv │ │ │ ├── Prob123_bugs_addsubz_prompt.txt │ │ │ ├── Prob123_bugs_addsubz_ref.sv │ │ │ ├── Prob123_bugs_addsubz_test.sv │ │ │ ├── Prob124_rule110_prompt.txt │ │ │ ├── Prob124_rule110_ref.sv │ │ │ ├── Prob124_rule110_test.sv │ │ │ ├── Prob125_kmap3_prompt.txt │ │ │ ├── Prob125_kmap3_ref.sv │ │ │ ├── Prob125_kmap3_test.sv │ │ │ ├── Prob126_circuit6_prompt.txt │ │ │ ├── Prob126_circuit6_ref.sv │ │ │ ├── Prob126_circuit6_test.sv │ │ │ ├── Prob127_lemmings1_prompt.txt │ │ │ ├── Prob127_lemmings1_ref.sv │ │ │ ├── Prob127_lemmings1_test.sv │ │ │ ├── Prob128_fsm_ps2_prompt.txt │ │ │ ├── Prob128_fsm_ps2_ref.sv │ │ │ ├── Prob128_fsm_ps2_test.sv │ │ │ ├── Prob129_ece241_2013_q8_prompt.txt │ │ │ ├── Prob129_ece241_2013_q8_ref.sv │ │ │ ├── Prob129_ece241_2013_q8_test.sv │ │ │ ├── Prob130_circuit5_prompt.txt │ │ │ ├── Prob130_circuit5_ref.sv │ │ │ ├── Prob130_circuit5_test.sv │ │ │ ├── Prob131_mt2015_q4_prompt.txt │ │ │ ├── Prob131_mt2015_q4_ref.sv │ │ │ ├── Prob131_mt2015_q4_test.sv │ │ │ ├── Prob132_always_if2_prompt.txt │ │ │ ├── Prob132_always_if2_ref.sv │ │ │ ├── Prob132_always_if2_test.sv │ │ │ ├── Prob133_2014_q3fsm_prompt.txt │ │ │ ├── Prob133_2014_q3fsm_ref.sv │ │ │ ├── Prob133_2014_q3fsm_test.sv │ │ │ ├── Prob134_2014_q3c_prompt.txt │ │ │ ├── Prob134_2014_q3c_ref.sv │ │ │ ├── Prob134_2014_q3c_test.sv │ │ │ ├── Prob135_m2014_q6b_prompt.txt │ │ │ ├── Prob135_m2014_q6b_ref.sv │ │ │ ├── Prob135_m2014_q6b_test.sv │ │ │ ├── Prob136_m2014_q6_prompt.txt │ │ │ ├── Prob136_m2014_q6_ref.sv │ │ │ ├── Prob136_m2014_q6_test.sv │ │ │ ├── Prob137_fsm_serial_prompt.txt │ │ │ ├── Prob137_fsm_serial_ref.sv │ │ │ ├── Prob137_fsm_serial_test.sv │ │ │ ├── Prob138_2012_q2fsm_prompt.txt │ │ │ ├── Prob138_2012_q2fsm_ref.sv │ │ │ ├── Prob138_2012_q2fsm_test.sv │ │ │ ├── Prob139_2013_q2bfsm_prompt.txt │ │ │ ├── Prob139_2013_q2bfsm_ref.sv │ │ │ ├── Prob139_2013_q2bfsm_test.sv │ │ │ ├── Prob140_fsm_hdlc_prompt.txt │ │ │ ├── Prob140_fsm_hdlc_ref.sv │ │ │ ├── Prob140_fsm_hdlc_test.sv │ │ │ ├── Prob141_count_clock_prompt.txt │ │ │ ├── Prob141_count_clock_ref.sv │ │ │ ├── Prob141_count_clock_test.sv │ │ │ ├── Prob142_lemmings2_prompt.txt │ │ │ ├── Prob142_lemmings2_ref.sv │ │ │ ├── Prob142_lemmings2_test.sv │ │ │ ├── Prob143_fsm_onehot_prompt.txt │ │ │ ├── Prob143_fsm_onehot_ref.sv │ │ │ ├── Prob143_fsm_onehot_test.sv │ │ │ ├── Prob144_conwaylife_prompt.txt │ │ │ ├── Prob144_conwaylife_ref.sv │ │ │ ├── Prob144_conwaylife_test.sv │ │ │ ├── Prob145_circuit8_prompt.txt │ │ │ ├── Prob145_circuit8_ref.sv │ │ │ ├── Prob145_circuit8_test.sv │ │ │ ├── Prob146_fsm_serialdata_prompt.txt │ │ │ ├── Prob146_fsm_serialdata_ref.sv │ │ │ ├── Prob146_fsm_serialdata_test.sv │ │ │ ├── Prob147_circuit10_prompt.txt │ │ │ ├── Prob147_circuit10_ref.sv │ │ │ ├── Prob147_circuit10_test.sv │ │ │ ├── Prob148_2013_q2afsm_prompt.txt │ │ │ ├── Prob148_2013_q2afsm_ref.sv │ │ │ ├── Prob148_2013_q2afsm_test.sv │ │ │ ├── Prob149_ece241_2013_q4_prompt.txt │ │ │ ├── Prob149_ece241_2013_q4_ref.sv │ │ │ ├── Prob149_ece241_2013_q4_test.sv │ │ │ ├── Prob150_review2015_fsmonehot_prompt.txt │ │ │ ├── Prob150_review2015_fsmonehot_ref.sv │ │ │ ├── Prob150_review2015_fsmonehot_test.sv │ │ │ ├── Prob151_review2015_fsm_prompt.txt │ │ │ ├── Prob151_review2015_fsm_ref.sv │ │ │ ├── Prob151_review2015_fsm_test.sv │ │ │ ├── Prob152_lemmings3_prompt.txt │ │ │ ├── Prob152_lemmings3_ref.sv │ │ │ ├── Prob152_lemmings3_test.sv │ │ │ ├── Prob153_gshare_prompt.txt │ │ │ ├── Prob153_gshare_ref.sv │ │ │ ├── Prob153_gshare_test.sv │ │ │ ├── Prob154_fsm_ps2data_prompt.txt │ │ │ ├── Prob154_fsm_ps2data_ref.sv │ │ │ ├── Prob154_fsm_ps2data_test.sv │ │ │ ├── Prob155_lemmings4_prompt.txt │ │ │ ├── Prob155_lemmings4_ref.sv │ │ │ ├── Prob155_lemmings4_test.sv │ │ │ ├── Prob156_review2015_fancytimer_prompt.txt │ │ │ ├── Prob156_review2015_fancytimer_ref.sv │ │ │ ├── Prob156_review2015_fancytimer_test.sv │ │ │ ├── problems-temp.txt │ │ │ └── problems.txt │ │ ├── plan_output │ │ │ ├── 2012_q1g_0.log │ │ │ ├── 2012_q1g_0.sv │ │ │ ├── 2012_q1g_0.v │ │ │ ├── 2012_q2b_0.sv │ │ │ ├── 2012_q2b_0.v │ │ │ ├── 2012_q2fsm_0.sv │ │ │ ├── 2012_q2fsm_0.v │ │ │ ├── 2013_q2afsm_0.sv │ │ │ ├── 2013_q2afsm_0.v │ │ │ ├── 2013_q2bfsm_0.log │ │ │ ├── 2013_q2bfsm_0.sv │ │ │ ├── 2013_q2bfsm_0.v │ │ │ ├── 2014_q3bfsm_0.sv │ │ │ ├── 2014_q3bfsm_0.v │ │ │ ├── 2014_q3c_0.sv │ │ │ ├── 2014_q3c_0.v │ │ │ ├── 2014_q3fsm_0.sv │ │ │ ├── 2014_q3fsm_0.v │ │ │ ├── 2014_q3fsm_0_success.sv │ │ │ ├── 2014_q3fsm_0_success.v │ │ │ ├── 2014_q4a_0.sv │ │ │ ├── 2014_q4a_0.v │ │ │ ├── 7420_0.sv │ │ │ ├── 7420_0.v │ │ │ ├── 7458_0.sv │ │ │ ├── 7458_0.v │ │ │ ├── always_case2_0.sv │ │ │ ├── always_case2_0.v │ │ │ ├── always_case_0.sv │ │ │ ├── always_case_0.v │ │ │ ├── always_casez_0.sv │ │ │ ├── always_casez_0.v │ │ │ ├── always_if2_0.sv │ │ │ ├── always_if2_0.v │ │ │ ├── always_if_0.sv │ │ │ ├── always_if_0.v │ │ │ ├── always_nolatches_0.sv │ │ │ ├── always_nolatches_0.v │ │ │ ├── alwaysblock1_0.sv │ │ │ ├── alwaysblock1_0.v │ │ │ ├── alwaysblock2_0.sv │ │ │ ├── alwaysblock2_0.v │ │ │ ├── andgate_0.sv │ │ │ ├── andgate_0.v │ │ │ ├── bugs_addsubz_0.sv │ │ │ ├── bugs_addsubz_0.v │ │ │ ├── bugs_case_0.sv │ │ │ ├── bugs_case_0.v │ │ │ ├── bugs_mux2_0.sv │ │ │ ├── bugs_mux2_0.v │ │ │ ├── circuit10_0.sv │ │ │ ├── circuit10_0.v │ │ │ ├── circuit1_0.sv │ │ │ ├── circuit1_0.v │ │ │ ├── circuit2_0.sv │ │ │ ├── circuit2_0.v │ │ │ ├── circuit3_0.sv │ │ │ ├── circuit3_0.v │ │ │ ├── circuit4_0.sv │ │ │ ├── circuit4_0.v │ │ │ ├── circuit5_0.sv │ │ │ ├── circuit5_0.v │ │ │ ├── circuit6_0.sv │ │ │ ├── circuit6_0.v │ │ │ ├── circuit7_0.sv │ │ │ ├── circuit7_0.v │ │ │ ├── circuit8_0.log │ │ │ ├── circuit8_0.sv │ │ │ ├── circuit8_0.v │ │ │ ├── circuit9_0.sv │ │ │ ├── circuit9_0.v │ │ │ ├── conditional_0.sv │ │ │ ├── conditional_0.v │ │ │ ├── conwaylife_0.sv │ │ │ ├── conwaylife_0.v │ │ │ ├── count10_0.sv │ │ │ ├── count10_0.v │ │ │ ├── count15_0.sv │ │ │ ├── count15_0.v │ │ │ ├── count1to10_0.sv │ │ │ ├── count1to10_0.v │ │ │ ├── countbcd_0.log │ │ │ ├── countbcd_0.sv │ │ │ ├── countbcd_0.v │ │ │ ├── counter_2bc_0.sv │ │ │ ├── counter_2bc_0.v │ │ │ ├── countslow_0.sv │ │ │ ├── countslow_0.v │ │ │ ├── dff16e_0.sv │ │ │ ├── dff16e_0.v │ │ │ ├── dff8_0.sv │ │ │ ├── dff8_0.v │ │ │ ├── dff8ar_0.sv │ │ │ ├── dff8ar_0.v │ │ │ ├── dff8p_0.sv │ │ │ ├── dff8p_0.v │ │ │ ├── dff8r_0.sv │ │ │ ├── dff8r_0.v │ │ │ ├── dff_0.sv │ │ │ ├── dff_0.v │ │ │ ├── dualedge_0.sv │ │ │ ├── dualedge_0.v │ │ │ ├── ece241_2013_q12_0.sv │ │ │ ├── ece241_2013_q12_0.v │ │ │ ├── ece241_2013_q7_0.sv │ │ │ ├── ece241_2013_q7_0.v │ │ │ ├── ece241_2013_q8_0.sv │ │ │ ├── ece241_2013_q8_0.v │ │ │ ├── ece241_2014_q1c_0.sv │ │ │ ├── ece241_2014_q1c_0.v │ │ │ ├── ece241_2014_q3_0.log │ │ │ ├── ece241_2014_q3_0.sv │ │ │ ├── ece241_2014_q3_0.v │ │ │ ├── ece241_2014_q4_0.sv │ │ │ ├── ece241_2014_q4_0.v │ │ │ ├── ece241_2014_q5b_0.sv │ │ │ ├── ece241_2014_q5b_0.v │ │ │ ├── edgecapture_0.sv │ │ │ ├── edgecapture_0.v │ │ │ ├── edgedetect2_0.sv │ │ │ ├── edgedetect2_0.v │ │ │ ├── edgedetect_0.sv │ │ │ ├── edgedetect_0.v │ │ │ ├── fadd_0.sv │ │ │ ├── fadd_0.v │ │ │ ├── fsm1_0.sv │ │ │ ├── fsm1_0.v │ │ │ ├── fsm1s_0.sv │ │ │ ├── fsm1s_0.v │ │ │ ├── fsm2_0.sv │ │ │ ├── fsm2_0.v │ │ │ ├── fsm2s_0.sv │ │ │ ├── fsm2s_0.v │ │ │ ├── fsm3_0.sv │ │ │ ├── fsm3_0.v │ │ │ ├── fsm3comb_0.sv │ │ │ ├── fsm3comb_0.v │ │ │ ├── fsm3onehot_0.sv │ │ │ ├── fsm3onehot_0.v │ │ │ ├── fsm3s_0.sv │ │ │ ├── fsm3s_0.v │ │ │ ├── fsm_hdlc_0.log │ │ │ ├── fsm_hdlc_0.sv │ │ │ ├── fsm_hdlc_0.v │ │ │ ├── fsm_onehot_0.sv │ │ │ ├── fsm_onehot_0.v │ │ │ ├── fsm_ps2_0.sv │ │ │ ├── fsm_ps2_0.v │ │ │ ├── fsm_serial_0.sv │ │ │ ├── fsm_serial_0.v │ │ │ ├── fsm_serialdata_0.log │ │ │ ├── fsm_serialdata_0.sv │ │ │ ├── fsm_serialdata_0.v │ │ │ ├── gates100_0.sv │ │ │ ├── gates100_0.v │ │ │ ├── gates4_0.sv │ │ │ ├── gates4_0.v │ │ │ ├── gates_0.sv │ │ │ ├── gates_0.v │ │ │ ├── gatesv100_0.sv │ │ │ ├── gatesv100_0.v │ │ │ ├── gatesv_0.sv │ │ │ ├── gatesv_0.v │ │ │ ├── hadd_0.sv │ │ │ ├── hadd_0.v │ │ │ ├── history_shift_0.sv │ │ │ ├── history_shift_0.v │ │ │ ├── kmap1_0.sv │ │ │ ├── kmap1_0.v │ │ │ ├── kmap2_0.log │ │ │ ├── kmap2_0.sv │ │ │ ├── kmap2_0.v │ │ │ ├── kmap3_0.log │ │ │ ├── kmap3_0.sv │ │ │ ├── kmap3_0.v │ │ │ ├── kmap4_0.sv │ │ │ ├── kmap4_0.v │ │ │ ├── lemmings1_0.sv │ │ │ ├── lemmings1_0.v │ │ │ ├── lemmings2_0.log │ │ │ ├── lemmings2_0.sv │ │ │ ├── lemmings2_0.v │ │ │ ├── lemmings3_0.log │ │ │ ├── lemmings3_0.sv │ │ │ ├── lemmings3_0.v │ │ │ ├── lfsr32_0.log │ │ │ ├── lfsr32_0.sv │ │ │ ├── lfsr32_0.v │ │ │ ├── lfsr5_0.sv │ │ │ ├── lfsr5_0.v │ │ │ ├── m2014_q3_0.log │ │ │ ├── m2014_q3_0.sv │ │ │ ├── m2014_q3_0.v │ │ │ ├── m2014_q4a_0.sv │ │ │ ├── m2014_q4a_0.v │ │ │ ├── m2014_q4b_0.sv │ │ │ ├── m2014_q4b_0.v │ │ │ ├── m2014_q4c_0.sv │ │ │ ├── m2014_q4c_0.v │ │ │ ├── m2014_q4d_0.sv │ │ │ ├── m2014_q4d_0.v │ │ │ ├── m2014_q4e_0.sv │ │ │ ├── m2014_q4e_0.v │ │ │ ├── m2014_q4f_0.sv │ │ │ ├── m2014_q4f_0.v │ │ │ ├── m2014_q4g_0.sv │ │ │ ├── m2014_q4g_0.v │ │ │ ├── m2014_q4h_0.sv │ │ │ ├── m2014_q4h_0.v │ │ │ ├── m2014_q4i_0.sv │ │ │ ├── m2014_q4i_0.v │ │ │ ├── m2014_q4j_0.sv │ │ │ ├── m2014_q4j_0.v │ │ │ ├── m2014_q4k_0.sv │ │ │ ├── m2014_q4k_0.v │ │ │ ├── m2014_q6_0.log │ │ │ ├── m2014_q6_0.sv │ │ │ ├── m2014_q6_0.v │ │ │ ├── m2014_q6b_0.sv │ │ │ ├── m2014_q6b_0.v │ │ │ ├── m2014_q6c_0.log │ │ │ ├── m2014_q6c_0.sv │ │ │ ├── m2014_q6c_0.v │ │ │ ├── mt2015_eq2_0.sv │ │ │ ├── mt2015_eq2_0.v │ │ │ ├── mt2015_muxdff_0.log │ │ │ ├── mt2015_muxdff_0.sv │ │ │ ├── mt2015_muxdff_0.v │ │ │ ├── mt2015_q4_0.sv │ │ │ ├── mt2015_q4_0.v │ │ │ ├── mt2015_q4a_0.sv │ │ │ ├── mt2015_q4a_0.v │ │ │ ├── mt2015_q4b_0.sv │ │ │ ├── mt2015_q4b_0.v │ │ │ ├── mux256to1_0.sv │ │ │ ├── mux256to1_0.v │ │ │ ├── mux256to1v_0.sv │ │ │ ├── mux256to1v_0.v │ │ │ ├── mux2to1_0.sv │ │ │ ├── mux2to1_0.v │ │ │ ├── mux2to1v_0.sv │ │ │ ├── mux2to1v_0.v │ │ │ ├── mux9to1v_0.sv │ │ │ ├── mux9to1v_0.v │ │ │ ├── norgate_0.sv │ │ │ ├── norgate_0.v │ │ │ ├── notgate_0.sv │ │ │ ├── notgate_0.v │ │ │ ├── popcount255_0.sv │ │ │ ├── popcount255_0.v │ │ │ ├── popcount3_0.sv │ │ │ ├── popcount3_0.v │ │ │ ├── reduction_0.sv │ │ │ ├── reduction_0.v │ │ │ ├── review2015_count1k_0.sv │ │ │ ├── review2015_count1k_0.v │ │ │ ├── review2015_fsmonehot_0.log │ │ │ ├── review2015_fsmonehot_0.sv │ │ │ ├── review2015_fsmonehot_0.v │ │ │ ├── review2015_fsmseq_0.log │ │ │ ├── review2015_fsmseq_0.sv │ │ │ ├── review2015_fsmseq_0.v │ │ │ ├── review2015_fsmshift_0.sv │ │ │ ├── review2015_fsmshift_0.v │ │ │ ├── review2015_shiftcount_0.sv │ │ │ ├── review2015_shiftcount_0.v │ │ │ ├── ringer_0.sv │ │ │ ├── ringer_0.v │ │ │ ├── rotate100_0.sv │ │ │ ├── rotate100_0.v │ │ │ ├── rule110_0.log │ │ │ ├── rule110_0.sv │ │ │ ├── rule110_0.v │ │ │ ├── rule90_0.sv │ │ │ ├── rule90_0.v │ │ │ ├── shift18_0.sv │ │ │ ├── shift18_0.v │ │ │ ├── shift4_0.sv │ │ │ ├── shift4_0.v │ │ │ ├── step_one_0.sv │ │ │ ├── step_one_0.v │ │ │ ├── thermostat_0.sv │ │ │ ├── thermostat_0.v │ │ │ ├── timer_0.sv │ │ │ ├── timer_0.v │ │ │ ├── truthtable1_0.sv │ │ │ ├── truthtable1_0.v │ │ │ ├── vector0_0.sv │ │ │ ├── vector0_0.v │ │ │ ├── vector100r_0.sv │ │ │ ├── vector100r_0.v │ │ │ ├── vector1_0.sv │ │ │ ├── vector1_0.v │ │ │ ├── vector2_0.sv │ │ │ ├── vector2_0.v │ │ │ ├── vector3_0.sv │ │ │ ├── vector3_0.v │ │ │ ├── vector4_0.sv │ │ │ ├── vector4_0.v │ │ │ ├── vector5_0.sv │ │ │ ├── vector5_0.v │ │ │ ├── vectorgates_0.sv │ │ │ ├── vectorgates_0.v │ │ │ ├── vectorr_0.sv │ │ │ ├── vectorr_0.v │ │ │ ├── wire4_0.sv │ │ │ ├── wire4_0.v │ │ │ ├── wire_0.sv │ │ │ ├── wire_0.v │ │ │ ├── wire_decl_0.sv │ │ │ ├── wire_decl_0.v │ │ │ ├── xnorgate_0.sv │ │ │ ├── xnorgate_0.v │ │ │ ├── zero_0.sv │ │ │ └── zero_0.v │ │ └── plans │ │ │ ├── 2012_q1g_plan.json │ │ │ ├── 2012_q2b_plan.json │ │ │ ├── 2012_q2fsm_plan.json │ │ │ ├── 2013_q2afsm_plan.json │ │ │ ├── 2013_q2bfsm_plan.json │ │ │ ├── 2014_q3bfsm_plan.json │ │ │ ├── 2014_q3c_plan.json │ │ │ ├── 2014_q3fsm_plan.json │ │ │ ├── 2014_q3fsm_plan_good.json │ │ │ ├── 2014_q3fsm_success.json │ │ │ ├── 2014_q4a_plan.json │ │ │ ├── 7420_plan.json │ │ │ ├── 7458_plan.json │ │ │ ├── always_case2_plan.json │ │ │ ├── always_case_plan.json │ │ │ ├── always_casez_plan.json │ │ │ ├── always_if2_plan.json │ │ │ ├── always_if_plan.json │ │ │ ├── always_nolatches_plan.json │ │ │ ├── alwaysblock1_plan.json │ │ │ ├── alwaysblock2_plan.json │ │ │ ├── andgate_plan.json │ │ │ ├── bugs_addsubz_plan.json │ │ │ ├── bugs_case_plan.json │ │ │ ├── bugs_mux2_plan.json │ │ │ ├── circuit10_plan.json │ │ │ ├── circuit1_plan.json │ │ │ ├── circuit2_plan.json │ │ │ ├── circuit3_plan.json │ │ │ ├── circuit4_plan.json │ │ │ ├── circuit5_plan.json │ │ │ ├── circuit6_plan.json │ │ │ ├── circuit7_plan.json │ │ │ ├── circuit8_plan.json │ │ │ ├── circuit9_plan.json │ │ │ ├── conditional_plan.json │ │ │ ├── conwaylife_plan.json │ │ │ ├── count10_plan.json │ │ │ ├── count15_plan.json │ │ │ ├── count1to10_plan.json │ │ │ ├── count_clock_plan.json │ │ │ ├── countbcd_plan.json │ │ │ ├── counter_2bc_plan.json │ │ │ ├── countslow_plan.json │ │ │ ├── dff16e_plan.json │ │ │ ├── dff8_plan.json │ │ │ ├── dff8ar_plan.json │ │ │ ├── dff8p_plan.json │ │ │ ├── dff8r_plan.json │ │ │ ├── dff_plan.json │ │ │ ├── dualedge_plan.json │ │ │ ├── ece241_2013_q12_plan.json │ │ │ ├── ece241_2013_q2_plan.json │ │ │ ├── ece241_2013_q4_plan.json │ │ │ ├── ece241_2013_q7_plan.json │ │ │ ├── ece241_2013_q8_plan.json │ │ │ ├── ece241_2014_q1c_plan.json │ │ │ ├── ece241_2014_q3_plan.json │ │ │ ├── ece241_2014_q4_plan.json │ │ │ ├── ece241_2014_q5a_plan.json │ │ │ ├── ece241_2014_q5b_plan.json │ │ │ ├── edgecapture_plan.json │ │ │ ├── edgedetect2_plan.json │ │ │ ├── edgedetect_plan.json │ │ │ ├── fadd_plan.json │ │ │ ├── fsm1_plan.json │ │ │ ├── fsm1s_plan.json │ │ │ ├── fsm2_plan.json │ │ │ ├── fsm2s_plan.json │ │ │ ├── fsm3_plan.json │ │ │ ├── fsm3comb_plan.json │ │ │ ├── fsm3onehot_plan.json │ │ │ ├── fsm3s_plan.json │ │ │ ├── fsm_hdlc_plan.json │ │ │ ├── fsm_onehot_plan.json │ │ │ ├── fsm_ps2_plan.json │ │ │ ├── fsm_ps2data_plan.json │ │ │ ├── fsm_serial_plan.json │ │ │ ├── fsm_serialdata_plan.json │ │ │ ├── gates100_plan.json │ │ │ ├── gates4_plan.json │ │ │ ├── gates_plan.json │ │ │ ├── gatesv100_plan.json │ │ │ ├── gatesv_plan.json │ │ │ ├── gshare_plan.json │ │ │ ├── hadd_plan.json │ │ │ ├── history_shift_plan.json │ │ │ ├── kmap1_plan.json │ │ │ ├── kmap2_plan.json │ │ │ ├── kmap3_plan.json │ │ │ ├── kmap4_plan.json │ │ │ ├── lemmings1_plan.json │ │ │ ├── lemmings2_plan.json │ │ │ ├── lemmings3_plan.json │ │ │ ├── lemmings4_plan.json │ │ │ ├── lfsr32_plan.json │ │ │ ├── lfsr5_plan.json │ │ │ ├── m2014_q3_plan.json │ │ │ ├── m2014_q4a_plan.json │ │ │ ├── m2014_q4b_plan.json │ │ │ ├── m2014_q4c_plan.json │ │ │ ├── m2014_q4d_plan.json │ │ │ ├── m2014_q4e_plan.json │ │ │ ├── m2014_q4f_plan.json │ │ │ ├── m2014_q4g_plan.json │ │ │ ├── m2014_q4h_plan.json │ │ │ ├── m2014_q4i_plan.json │ │ │ ├── m2014_q4j_plan.json │ │ │ ├── m2014_q4k_plan.json │ │ │ ├── m2014_q6_plan.json │ │ │ ├── m2014_q6b_plan.json │ │ │ ├── m2014_q6c_plan.json │ │ │ ├── mt2015_eq2_plan.json │ │ │ ├── mt2015_muxdff_plan.json │ │ │ ├── mt2015_q4_plan.json │ │ │ ├── mt2015_q4a_plan.json │ │ │ ├── mt2015_q4b_plan.json │ │ │ ├── mux256to1_plan.json │ │ │ ├── mux256to1v_plan.json │ │ │ ├── mux2to1_plan.json │ │ │ ├── mux2to1v_plan.json │ │ │ ├── mux9to1v_plan.json │ │ │ ├── norgate_plan.json │ │ │ ├── notgate_plan.json │ │ │ ├── popcount255_plan.json │ │ │ ├── popcount3_plan.json │ │ │ ├── reduction_plan.json │ │ │ ├── review2015_count1k_plan.json │ │ │ ├── review2015_fancytimer_plan.json │ │ │ ├── review2015_fsm_plan.json │ │ │ ├── review2015_fsmonehot_plan.json │ │ │ ├── review2015_fsmonehot_plan_0.json │ │ │ ├── review2015_fsmseq_plan.json │ │ │ ├── review2015_fsmshift_plan.json │ │ │ ├── review2015_shiftcount_plan.json │ │ │ ├── ringer_plan.json │ │ │ ├── rotate100_plan.json │ │ │ ├── rule110_plan.json │ │ │ ├── rule90_plan.json │ │ │ ├── shift18_plan.json │ │ │ ├── shift4_plan.json │ │ │ ├── step_one_plan.json │ │ │ ├── thermostat_plan.json │ │ │ ├── timer_plan.json │ │ │ ├── truthtable1_plan.json │ │ │ ├── vector0_plan.json │ │ │ ├── vector100r_plan.json │ │ │ ├── vector1_plan.json │ │ │ ├── vector2_plan.json │ │ │ ├── vector3_plan.json │ │ │ ├── vector4_plan.json │ │ │ ├── vector5_plan.json │ │ │ ├── vectorgates_plan.json │ │ │ ├── vectorr_plan.json │ │ │ ├── wire4_plan.json │ │ │ ├── wire_decl_plan.json │ │ │ ├── wire_plan.json │ │ │ ├── xnorgate_plan.json │ │ │ ├── zero_plan.json │ │ │ └── zero_rough_plan.json │ │ ├── verilog_agent_config_llama3.py │ │ ├── verilog_agent_configs.py │ │ ├── verilog_examples_manager.py │ │ ├── verilog_tools_class.py │ │ └── verilogcoder.py ├── hardware_general_agent.py ├── knowledge_circuit_graph.py ├── output_parser_util.py ├── task.py └── tools_utility.py └── setup.py /LICENSE-CODE: -------------------------------------------------------------------------------- 1 | Copyright [2025] [NVIDIA CORPORATION] 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | -------------------------------------------------------------------------------- /OAI_CONFIG_LIST: -------------------------------------------------------------------------------- 1 | [ 2 | { 3 | "model": "gpt-4-turbo", 4 | "api_key": "" 5 | } 6 | ] 7 | -------------------------------------------------------------------------------- /autogen/__init__.py: -------------------------------------------------------------------------------- 1 | import logging 2 | 3 | from .agentchat import * 4 | from .code_utils import DEFAULT_MODEL, FAST_MODEL 5 | from .exception_utils import * 6 | from .oai import * 7 | from .version import __version__ 8 | 9 | # Set the root logger. 10 | logger = logging.getLogger(__name__) 11 | logger.setLevel(logging.INFO) 12 | -------------------------------------------------------------------------------- /autogen/agentchat/contrib/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NVlabs/VerilogCoder/8b13108869f276c7b644dd88beabcb401a5cfa92/autogen/agentchat/contrib/__init__.py -------------------------------------------------------------------------------- /autogen/agentchat/contrib/capabilities/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NVlabs/VerilogCoder/8b13108869f276c7b644dd88beabcb401a5cfa92/autogen/agentchat/contrib/capabilities/__init__.py -------------------------------------------------------------------------------- /autogen/agentchat/contrib/capabilities/agent_capability.py: -------------------------------------------------------------------------------- 1 | from autogen.agentchat.assistant_agent import ConversableAgent 2 | 3 | 4 | class AgentCapability: 5 | """Base class for composable capabilities that can be added to an agent.""" 6 | 7 | def __init__(self): 8 | pass 9 | 10 | def add_to_agent(self, agent: ConversableAgent): 11 | """ 12 | Adds a particular capability to the given agent. Must be implemented by the capability subclass. 13 | An implementation will typically call agent.register_hook() one or more times. See teachability.py as an example. 14 | """ 15 | raise NotImplementedError 16 | -------------------------------------------------------------------------------- /autogen/agentchat/contrib/vectordb/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NVlabs/VerilogCoder/8b13108869f276c7b644dd88beabcb401a5cfa92/autogen/agentchat/contrib/vectordb/__init__.py -------------------------------------------------------------------------------- /autogen/cache/__init__.py: -------------------------------------------------------------------------------- 1 | from .abstract_cache_base import AbstractCache 2 | from .cache import Cache 3 | 4 | __all__ = ["Cache", "AbstractCache"] 5 | -------------------------------------------------------------------------------- /autogen/coding/__init__.py: -------------------------------------------------------------------------------- 1 | from .base import CodeBlock, CodeExecutor, CodeExtractor, CodeResult 2 | from .docker_commandline_code_executor import DockerCommandLineCodeExecutor 3 | from .factory import CodeExecutorFactory 4 | from .local_commandline_code_executor import LocalCommandLineCodeExecutor 5 | from .markdown_code_extractor import MarkdownCodeExtractor 6 | 7 | __all__ = ( 8 | "CodeBlock", 9 | "CodeResult", 10 | "CodeExtractor", 11 | "CodeExecutor", 12 | "CodeExecutorFactory", 13 | "MarkdownCodeExtractor", 14 | "LocalCommandLineCodeExecutor", 15 | "DockerCommandLineCodeExecutor", 16 | ) 17 | -------------------------------------------------------------------------------- /autogen/coding/jupyter/__init__.py: -------------------------------------------------------------------------------- 1 | from .base import JupyterConnectable, JupyterConnectionInfo 2 | from .docker_jupyter_server import DockerJupyterServer 3 | from .embedded_ipython_code_executor import EmbeddedIPythonCodeExecutor 4 | from .jupyter_client import JupyterClient 5 | from .jupyter_code_executor import JupyterCodeExecutor 6 | from .local_jupyter_server import LocalJupyterServer 7 | 8 | __all__ = [ 9 | "JupyterConnectable", 10 | "JupyterConnectionInfo", 11 | "JupyterClient", 12 | "LocalJupyterServer", 13 | "DockerJupyterServer", 14 | "EmbeddedIPythonCodeExecutor", 15 | "JupyterCodeExecutor", 16 | ] 17 | -------------------------------------------------------------------------------- /autogen/extensions/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NVlabs/VerilogCoder/8b13108869f276c7b644dd88beabcb401a5cfa92/autogen/extensions/__init__.py -------------------------------------------------------------------------------- /autogen/io/__init__.py: -------------------------------------------------------------------------------- 1 | from .base import InputStream, IOStream, OutputStream 2 | from .console import IOConsole 3 | from .websockets import IOWebsockets 4 | 5 | # Set the default input/output stream to the console 6 | IOStream.set_global_default(IOConsole()) 7 | IOStream.set_default(IOConsole()) 8 | 9 | __all__ = ("IOConsole", "IOStream", "InputStream", "OutputStream", "IOWebsockets") 10 | -------------------------------------------------------------------------------- /autogen/logger/__init__.py: -------------------------------------------------------------------------------- 1 | from .logger_factory import LoggerFactory 2 | from .sqlite_logger import SqliteLogger 3 | 4 | __all__ = ("LoggerFactory", "SqliteLogger") 5 | -------------------------------------------------------------------------------- /autogen/logger/logger_factory.py: -------------------------------------------------------------------------------- 1 | from typing import Any, Dict, Optional 2 | 3 | from autogen.logger.base_logger import BaseLogger 4 | from autogen.logger.sqlite_logger import SqliteLogger 5 | 6 | __all__ = ("LoggerFactory",) 7 | 8 | 9 | class LoggerFactory: 10 | @staticmethod 11 | def get_logger(logger_type: str = "sqlite", config: Optional[Dict[str, Any]] = None) -> BaseLogger: 12 | if config is None: 13 | config = {} 14 | 15 | if logger_type == "sqlite": 16 | return SqliteLogger(config) 17 | else: 18 | raise ValueError(f"[logger_factory] Unknown logger type: {logger_type}") 19 | -------------------------------------------------------------------------------- /autogen/types.py: -------------------------------------------------------------------------------- 1 | from typing import Dict, List, Literal, TypedDict, Union 2 | 3 | 4 | class UserMessageTextContentPart(TypedDict): 5 | type: Literal["text"] 6 | text: str 7 | 8 | 9 | class UserMessageImageContentPart(TypedDict): 10 | type: Literal["image_url"] 11 | # Ignoring the other "detail param for now" 12 | image_url: Dict[Literal["url"], str] 13 | -------------------------------------------------------------------------------- /autogen/version.py: -------------------------------------------------------------------------------- 1 | __version__ = "0.2.26" 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/examples/example_identifiervisitor.py: -------------------------------------------------------------------------------- 1 | from __future__ import absolute_import 2 | from __future__ import print_function 3 | import sys 4 | import os 5 | 6 | # the next line can be removed after installation 7 | sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) 8 | 9 | import pyverilog.vparser.ast as vast 10 | from pyverilog.utils.identifiervisitor import getIdentifiers 11 | 12 | 13 | def main(): 14 | a = vast.Identifier('a') 15 | b = vast.Identifier('b') 16 | c = vast.Plus(a, b) 17 | 18 | ids = getIdentifiers(c) 19 | print(ids) 20 | 21 | 22 | if __name__ == '__main__': 23 | main() 24 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: clean 2 | clean: 3 | make clean -C ./utils 4 | make clean -C ./vparser 5 | make clean -C ./dataflow 6 | make clean -C ./controlflow 7 | make clean -C ./ast_code_generator 8 | rm -rf *.pyc __pycache__ *.out parsetab.py *.html 9 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/VERSION: -------------------------------------------------------------------------------- 1 | 1.3.0 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/__init__.py: -------------------------------------------------------------------------------- 1 | from __future__ import absolute_import 2 | from __future__ import print_function 3 | 4 | import os 5 | 6 | with open(os.path.join(os.path.dirname(__file__), "VERSION")) as f: 7 | __version__ = f.read().splitlines()[0] 8 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: clean 2 | clean: 3 | rm -rf *.pyc __pycache__ parsetab.py *.out 4 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NVlabs/VerilogCoder/8b13108869f276c7b644dd88beabcb401a5cfa92/hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/__init__.py -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NVlabs/VerilogCoder/8b13108869f276c7b644dd88beabcb401a5cfa92/hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/__init__.py -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/always.txt: -------------------------------------------------------------------------------- 1 | 2 | always @({{ sens_list }}) {{ statement }} 3 | 4 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/and.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/assign.txt: -------------------------------------------------------------------------------- 1 | assign {{ left }} = {{ right }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/block.txt: -------------------------------------------------------------------------------- 1 | begin{% if scope != '' %} : {{ scope }}{% endif %} 2 | {%- for statement in statements %} 3 | {{ statement }} 4 | {%- endfor %} 5 | end 6 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/blockingsubstitution.txt: -------------------------------------------------------------------------------- 1 | {% if ldelay != '' %}{{ ldelay }} {% endif %}{{ left }} = {% if rdelay != '' %}{{ rdelay }} {% endif %}{{ right }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/case.txt: -------------------------------------------------------------------------------- 1 | {{ cond }}: {{ statement }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/casestatement.txt: -------------------------------------------------------------------------------- 1 | case({{ comp }}) 2 | {%- for case in caselist %} 3 | {{ case }} 4 | {%- endfor %} 5 | endcase 6 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/casexstatement.txt: -------------------------------------------------------------------------------- 1 | casex({{ comp }}) 2 | {%- for case in caselist %} 3 | {{ case }} 4 | {%- endfor %} 5 | endcase 6 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/concat.txt: -------------------------------------------------------------------------------- 1 | { {% for item in items %}{{ item }}{% if loop.index < len_items %}, {% endif %}{% endfor %} } 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/cond.txt: -------------------------------------------------------------------------------- 1 | (({{ cond }})? {{ true_value }} : {{ false_value }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/constant.txt: -------------------------------------------------------------------------------- 1 | {{ value }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/decl.txt: -------------------------------------------------------------------------------- 1 | {%- for item in items %}{{ item }} 2 | {%- endfor %} 3 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/delaystatement.txt: -------------------------------------------------------------------------------- 1 | #{{ delay }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/description.txt: -------------------------------------------------------------------------------- 1 | {% for definition in definitions %} 2 | {{ definition }} 3 | {% endfor %} 4 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/disable.txt: -------------------------------------------------------------------------------- 1 | diable {{ name }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/divide.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/eq.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/eql.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/eventstatement.txt: -------------------------------------------------------------------------------- 1 | @({{ senslist }}); 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/floatconst.txt: -------------------------------------------------------------------------------- 1 | {{ value }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/foreverstatement.txt: -------------------------------------------------------------------------------- 1 | forever {{ statement }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/forstatement.txt: -------------------------------------------------------------------------------- 1 | for({{ pre }} {{ cond }}; {{ post }}) {{ statement }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/function.txt: -------------------------------------------------------------------------------- 1 | 2 | function {{ retwidth }} {{ name }}; 3 | {%- for s in statement %} 4 | {{ s }} 5 | {%- endfor %} 6 | endfunction 7 | 8 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/functioncall.txt: -------------------------------------------------------------------------------- 1 | {{ name }}({% for arg in args %}{{ arg }}{% if loop.index < len_args %}, {% endif %}{% endfor %}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/generatestatement.txt: -------------------------------------------------------------------------------- 1 | 2 | generate {% for item in items %}{{ item }}{% endfor %} 3 | endgenerate 4 | 5 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/genvar.txt: -------------------------------------------------------------------------------- 1 | genvar {{ name }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/greatereq.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/greaterthan.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/identifier.txt: -------------------------------------------------------------------------------- 1 | {{ scope }}{{ name }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/identifierscope.txt: -------------------------------------------------------------------------------- 1 | {% for scope in scopes %}{{ scope }}{% endfor %} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/identifierscopelabel.txt: -------------------------------------------------------------------------------- 1 | {{ name }}{%- if loop != '' %}[{{ loop }}]{%- endif %}. 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/ifstatement.txt: -------------------------------------------------------------------------------- 1 | if({{ cond }}) {{ true_statement }} 2 | {%- if true_statement[-1] != ' ' and true_statement[-1] != '\n' %} {% endif -%} 3 | {%- if true_statement.count('\n') == 0 and false_statement != '' %} 4 | {% endif -%} 5 | {%- if false_statement != '' %}else {{ false_statement }}{% endif -%} 6 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/initial.txt: -------------------------------------------------------------------------------- 1 | 2 | initial {{ statement }} 3 | 4 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/inout.txt: -------------------------------------------------------------------------------- 1 | inout {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/input.txt: -------------------------------------------------------------------------------- 1 | input {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/instance.txt: -------------------------------------------------------------------------------- 1 | {{ name }}{{ array }} 2 | ({% for port in portlist %} 3 | {{ port }}{%- if loop.index < len_portlist -%}, {%- endif -%} 4 | {% endfor %} 5 | ) 6 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/instancelist.txt: -------------------------------------------------------------------------------- 1 | 2 | {{ module }} 3 | {%- if len_parameterlist > 0 %} 4 | #({% for param in parameterlist %} 5 | {{ param }}{%- if loop.index < len_parameterlist -%}, 6 | {%- endif -%}{% endfor %} 7 | ) 8 | {%- endif %} 9 | {%- for instance in instances %} 10 | {{ instance }}{%- if loop.index < len_instances -%}, 11 | {%- endif -%}{%- endfor -%}; 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/intconst.txt: -------------------------------------------------------------------------------- 1 | {{ value }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/integer.txt: -------------------------------------------------------------------------------- 1 | integer {{ name }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/ioport.txt: -------------------------------------------------------------------------------- 1 | {{ first }} {% if second != '' %}{{ second }} {% endif %}{% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/land.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/lconcat.txt: -------------------------------------------------------------------------------- 1 | { {% for item in items %}{{ item }}{% if loop.index < len_items %}, {% endif %}{% endfor %} } 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/length.txt: -------------------------------------------------------------------------------- 1 | [{{ msb }}:{{ lsb }}] 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/lesseq.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/lessthan.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/localparam.txt: -------------------------------------------------------------------------------- 1 | localparam {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }} = {{ value }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/lor.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/lvalue.txt: -------------------------------------------------------------------------------- 1 | {{ var }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/minus.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/mod.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/moduledef.txt: -------------------------------------------------------------------------------- 1 | 2 | module {{ modulename }}{% if paramlist != '' %} # 3 | ( 4 | {{ paramlist }} 5 | ) 6 | {%- endif %} 7 | ( 8 | {{ portlist }} 9 | ); 10 | 11 | {% for item in items %}{{ item }} 12 | {% endfor %} 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/nonblockingsubstitution.txt: -------------------------------------------------------------------------------- 1 | {% if ldelay != '' %}{{ ldelay }} {% endif %}{{ left }} <= {% if rdelay != '' %}{{ rdelay }} {% endif %}{{ right }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/noteq.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/noteql.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/operator.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/or.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/output.txt: -------------------------------------------------------------------------------- 1 | output {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/parallelblock.txt: -------------------------------------------------------------------------------- 1 | fork{% if scope != '' %} : {{ scope }}{% endif %} 2 | {%- for statement in statements %} 3 | {{ statement }} 4 | {%- endfor %} 5 | join 6 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/paramarg.txt: -------------------------------------------------------------------------------- 1 | {%- if paramname != '' -%}.{{ paramname }}({{ argname }}){%- else -%}{{ argname }}{%- endif -%} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/parameter.txt: -------------------------------------------------------------------------------- 1 | parameter {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }} = {{ value }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/paramlist.txt: -------------------------------------------------------------------------------- 1 | {% for param in params %}{{ param }}{% if loop.index < len_params %}, 2 | {% endif %}{% endfor %} 3 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/partselect.txt: -------------------------------------------------------------------------------- 1 | {{ var }}[{{ msb }}:{{ lsb }}] 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/plus.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/pointer.txt: -------------------------------------------------------------------------------- 1 | {{ var }}[{{ ptr }}] 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/port.txt: -------------------------------------------------------------------------------- 1 | {{ name }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/portarg.txt: -------------------------------------------------------------------------------- 1 | {%- if portname != '' -%}.{{ portname }}({{ argname }}){%- else -%}{{ argname }}{%- endif -%} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/portlist.txt: -------------------------------------------------------------------------------- 1 | {% for port in ports %}{{ port }}{% if loop.index < len_ports %}, 2 | {% endif %}{% endfor %} 3 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/power.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/pragma.txt: -------------------------------------------------------------------------------- 1 | (* {{ entry }} *) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/pragmaentry.txt: -------------------------------------------------------------------------------- 1 | {{ name }}{% if value != '' %} = {{ value }}{% endif %} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/real.txt: -------------------------------------------------------------------------------- 1 | real {{ name }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/reg.txt: -------------------------------------------------------------------------------- 1 | reg {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/repeat.txt: -------------------------------------------------------------------------------- 1 | { {{ times }}{{ value }} } 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/rvalue.txt: -------------------------------------------------------------------------------- 1 | {{ var }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/sens.txt: -------------------------------------------------------------------------------- 1 | {% if type != '' %}{{ type }} {% endif %}{{ sig }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/senslist.txt: -------------------------------------------------------------------------------- 1 | {% for item in items %}{{ item }}{% if loop.index < len_items %} or {% endif %}{% endfor %} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/singlestatement.txt: -------------------------------------------------------------------------------- 1 | {{ statement }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/sla.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/sll.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/source.txt: -------------------------------------------------------------------------------- 1 | {{ description }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/sra.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/srl.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/stringconst.txt: -------------------------------------------------------------------------------- 1 | "{{ value }}" 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/substitution.txt: -------------------------------------------------------------------------------- 1 | {% if ldelay != '' %}{{ ldelay }} {% endif %}{{ left }} = {% if rdelay != '' %}{{ rdelay }} {% endif %}{{ right }}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/systemcall.txt: -------------------------------------------------------------------------------- 1 | ${{ syscall }}{% if len_args > 0 %}({% endif %}{% for arg in args %}{{ arg }}{% if loop.index < len_args %}, {% endif %}{% endfor %}{% if len_args > 0 %}){% endif %} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/task.txt: -------------------------------------------------------------------------------- 1 | 2 | task {{ name }}; 3 | {%- for s in statement %} 4 | {{ s }} 5 | {%- endfor %} 6 | endtask 7 | 8 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/times.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/tri.txt: -------------------------------------------------------------------------------- 1 | tri {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/uand.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/ulnot.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/uminus.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/unand.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/unaryoperator.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/unor.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/unot.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/uor.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/uplus.txt: -------------------------------------------------------------------------------- 1 | ({{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/uxnor.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/uxor.txt: -------------------------------------------------------------------------------- 1 | ({{ op }}{{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/value.txt: -------------------------------------------------------------------------------- 1 | {{ value }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/variable.txt: -------------------------------------------------------------------------------- 1 | variable {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/waitstatement.txt: -------------------------------------------------------------------------------- 1 | wait({{ cond }}){% if statement != '' %} {{ statement }}{% else %};{% endif %} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/whilestatement.txt: -------------------------------------------------------------------------------- 1 | while({{ cond }}) {{ statement }} 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/width.txt: -------------------------------------------------------------------------------- 1 | [{{ msb }}:{{ lsb }}] 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/wire.txt: -------------------------------------------------------------------------------- 1 | wire {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}; 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/xnor.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/template/xor.txt: -------------------------------------------------------------------------------- 1 | ({{ left }} {{ op }} {{ right }}) 2 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/ast_code_generator/touch.py: -------------------------------------------------------------------------------- 1 | import os 2 | import sys 3 | import subprocess 4 | 5 | text = open('list_ast.txt', 'r').read() 6 | lines = text.split('\n') 7 | for line in lines: 8 | if line != '': 9 | subprocess.call('touch template/' + line.lower() + '.txt', shell=True) 10 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/controlflow/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: clean 2 | clean: 3 | rm -rf *.pyc __pycache__ parsetab.py *.out *.png *.dot 4 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/controlflow/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NVlabs/VerilogCoder/8b13108869f276c7b644dd88beabcb401a5cfa92/hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/controlflow/__init__.py -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/pyverilog/controlflow/__pycache__/__init__.cpython-310.pyc: -------------------------------------------------------------------------------- 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/hardware_agent/examples/VerilogCoder/pyverilog/scripts/test-python2.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | set -e 3 | 4 | mkdir python 5 | cd python 6 | virtualenv --python=python . 7 | source bin/activate 8 | 9 | git clone https://github.com/PyHDI/Pyverilog.git 10 | cd Pyverilog 11 | python setup.py install 12 | pip install pytest pytest-pythonpath 13 | mv pyverilog pyverilog.old 14 | 15 | python -m pytest -vv . 16 | 17 | mv pyverilog.old pyverilog 18 | cd .. 19 | deactivate 20 | cd .. 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/scripts/test-python3.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | set -e 3 | 4 | mkdir python3 5 | cd python3 6 | virtualenv --python=python3 . 7 | source bin/activate 8 | 9 | git clone https://github.com/PyHDI/Pyverilog.git 10 | cd Pyverilog 11 | python setup.py install 12 | pip install pytest pytest-pythonpath 13 | mv pyverilog pyverilog.old 14 | 15 | python -m pytest -vv . 16 | 17 | mv pyverilog.old pyverilog 18 | cd .. 19 | deactivate 20 | cd .. 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/pyverilog/scripts/upload_pypi.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | set -e 3 | 4 | python3 setup.py sdist 5 | twine upload dist/*.tar.gz 6 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob001_zero_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - output zero 7 | 8 | The module should always outputs a LOW. 9 | 10 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob001_zero_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | output zero 4 | ); 5 | 6 | assign zero = 1'b0; 7 | 8 | endmodule 9 | 10 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob002_m2014_q4i_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - output out 7 | 8 | The module should always drive 0 (or logic low). 9 | 10 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob002_m2014_q4i_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | output out 4 | ); 5 | 6 | assign out = 1'b0; 7 | 8 | endmodule 9 | 10 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob003_step_one_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - output one 7 | 8 | The module should always drive 1 (or logic high). 9 | 10 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob003_step_one_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | output one 4 | ); 5 | 6 | assign one = 1'b1; 7 | 8 | endmodule 9 | 10 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob004_vector2_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (32 bits) 7 | - output out (32 bits) 8 | 9 | The module should reverse the byte order of a 32-bit vector. 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob004_vector2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [31:0] in, 4 | output [31:0] out 5 | ); 6 | 7 | assign out = {in[7:0], in[15:8], in[23:16], in[31:24]}; 8 | 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob005_notgate_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in 7 | - output out 8 | 9 | The module should implement a NOT gate. 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob005_notgate_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input in, 4 | output out 5 | ); 6 | 7 | assign out = ~in; 8 | 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob006_vectorr_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (8 bits) 7 | - output out (8 bits) 8 | 9 | The module should reverse the bit ordering of the input port and write 10 | the result to the output port. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob006_vectorr_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [7:0] in, 4 | output [7:0] out 5 | ); 6 | 7 | assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in; 8 | 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob007_wire_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in 7 | - output out 8 | 9 | The module should behave like a wire. 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob007_wire_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input in, 4 | output out 5 | ); 6 | 7 | assign out = in; 8 | 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob008_m2014_q4h_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in 7 | - output out 8 | 9 | The module should assign the output port to the same value as the input 10 | port combinationally. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob008_m2014_q4h_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input in, 4 | output out 5 | ); 6 | 7 | assign out = in; 8 | 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob009_popcount3_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (3 bits) 7 | - output out (2 bits) 8 | 9 | The module should implement a "population count" circuit that counts the 10 | number of '1's in the input vector. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob009_popcount3_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [2:0] in, 4 | output [1:0] out 5 | ); 6 | 7 | assign out = in[0]+in[1]+in[2]; 8 | 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob010_mt2015_q4a_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input x 7 | - input y 8 | - output z 9 | 10 | The module should implement the boolean function z = (x^y) & x. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob010_mt2015_q4a_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input x, 4 | input y, 5 | output z 6 | ); 7 | 8 | assign z = (x^y) & x; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob011_norgate_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - output out 9 | 10 | The module should implement a NOR gate. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob011_norgate_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | output out 6 | ); 7 | 8 | assign out = ~(a | b); 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob012_xnorgate_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - output out 9 | 10 | The module should implement an XNOR gate. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob012_xnorgate_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | output out 6 | ); 7 | 8 | assign out = ~(a^b); 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob013_m2014_q4e_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in1 7 | - input in2 8 | - output out 9 | 10 | The module should implement a 2-input NOR gate. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob013_m2014_q4e_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input in1, 4 | input in2, 5 | output logic out 6 | ); 7 | 8 | assign out = ~(in1 | in2); 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob014_andgate_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - output out 9 | 10 | The module should implement a 2-input AND gate. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob014_andgate_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | output out 6 | ); 7 | 8 | assign out = a & b; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob015_vector1_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (16 bits) 7 | - output out_hi ( 8 bits) 8 | - output out_lo ( 8 bits) 9 | 10 | The module should implement a combinational circuit that splits an input 11 | half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes. 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob015_vector1_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [15:0] in, 4 | output [7:0] out_hi, 5 | output [7:0] out_lo 6 | ); 7 | 8 | assign {out_hi, out_lo} = in; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob016_m2014_q4j_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input x (4 bits) 7 | - input y (4 bits) 8 | - output sum (5 bits) 9 | 10 | Implement a 4-bit adder with full adders. The output sum should include 11 | the overflow bit. 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob016_m2014_q4j_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [3:0] x, 4 | input [3:0] y, 5 | output [4:0] sum 6 | ); 7 | 8 | assign sum = x+y; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob017_mux2to1v_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a (100 bits) 7 | - input b (100 bits) 8 | - input sel 9 | - output out (100 bits) 10 | 11 | The module should implement a 2-1 multiplexer. When sel=0, choose a. When 12 | sel=1, choose b. 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob017_mux2to1v_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [99:0] a, 4 | input [99:0] b, 5 | input sel, 6 | output [99:0] out 7 | ); 8 | 9 | assign out = sel ? b : a; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob018_mux256to1_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (256 bits) 7 | - input sel ( 8 bits) 8 | - output out 9 | 10 | The module should implement a 1-bit wide, 256-to-1 multiplexer. The 256 11 | inputs are all packed into a single 256-bit input vector. sel=0 should 12 | select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc. 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob018_mux256to1_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [255:0] in, 4 | input [7:0] sel, 5 | output out 6 | ); 7 | 8 | assign out = in[sel]; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob019_m2014_q4f_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in1 7 | - input in2 8 | - output out 9 | 10 | The module should implement the following circuit in Verilog. Two inputs 11 | (in1 and in2) go to an AND gate, but the in2 input to the AND gate has a 12 | bubble. The output of the AND gate is connected to 'out'. 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob019_m2014_q4f_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input in1, 4 | input in2, 5 | output logic out 6 | ); 7 | 8 | assign out = in1 & ~in2; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob020_mt2015_eq2_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input A (2 bits) 7 | - input B (2 bits) 8 | - output z 9 | 10 | The module should implement a circuit that has two 2-bit inputs A[1:0] 11 | and B[1:0], and produces an output z. The value of z should be 1 if A = 12 | B, otherwise z should be 0. 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob020_mt2015_eq2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [1:0] A, 4 | input [1:0] B, 5 | output z 6 | ); 7 | 8 | assign z = A[1:0]==B[1:0]; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob021_mux256to1v_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (1024 bits) 7 | - input sel ( 8 bits) 8 | - output out ( 4 bits) 9 | 10 | The module should implement a 4-bit wide, 256-to-1 multiplexer. The 256 11 | 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 12 | should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects 13 | bits in[11:8], etc. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob021_mux256to1v_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [1023:0] in, 4 | input [7:0] sel, 5 | output [3:0] out 6 | ); 7 | 8 | assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]}; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob022_mux2to1_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - input sel 9 | - output out 10 | 11 | The module should implement a one-bit wide, 2-to-1 multiplexer. When 12 | sel=0, choose a. When sel=1, choose b. 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob022_mux2to1_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input sel, 6 | output out 7 | ); 8 | 9 | assign out = sel ? b : a; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob023_vector100r_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (100 bits) 7 | - output out (100 bits) 8 | 9 | The module should reverse the bit ordering of the input and write to the 10 | output. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob023_vector100r_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [99:0] in, 4 | output reg [99:0] out 5 | ); 6 | 7 | always_comb 8 | for (int i=0;i<$bits(out);i++) 9 | out[i] = in[$bits(out)-i-1]; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob024_hadd_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - output sum 9 | - output cout 10 | 11 | The module should implement a half adder. A half adder adds two bits 12 | (with no carry-in) and produces a sum and carry-out. 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob024_hadd_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | output sum, 6 | output cout 7 | ); 8 | 9 | assign {cout, sum} = a+b; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob025_reduction_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (8 bits) 7 | - output parity 8 | 9 | Parity checking is often used as a simple method of detecting errors when 10 | transmitting data through an imperfect channel. The module should compute 11 | a parity bit for an 8-bit byte (which will add a 9th bit to the byte). We 12 | will use "even" parity, where the parity bit is just the XOR of all 8 13 | data bits. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob025_reduction_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [7:0] in, 4 | output parity 5 | ); 6 | 7 | assign parity = ^in; 8 | 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob026_alwaysblock1_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - output out_assign 9 | - output out_alwaysblock 10 | 11 | The module should implement an AND gate using both an assign statement 12 | and a combinational always block. 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob026_alwaysblock1_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | output out_assign, 6 | output reg out_alwaysblock 7 | ); 8 | 9 | assign out_assign = a & b; 10 | always @(*) out_alwaysblock = a & b; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob027_fadd_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - input cin 9 | - output cout 10 | - output sum 11 | 12 | The module should impement a full adder. A full adder adds three bits 13 | (including carry-in) and produces a sum and carry-out. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob027_fadd_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input cin, 6 | output cout, 7 | output sum 8 | ); 9 | 10 | assign {cout, sum} = a+b+cin; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob028_m2014_q4a_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input d 7 | - input ena 8 | - output q 9 | 10 | The module should impement a D latch using an always block. 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob028_m2014_q4a_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input d, 4 | input ena, 5 | output logic q 6 | ); 7 | 8 | always@(*) begin 9 | if (ena) 10 | q = d; 11 | end 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob029_m2014_q4g_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in1 7 | - input in2 8 | - input in3 9 | - output out 10 | 11 | The module should impement the following circuit: A two-input XNOR 12 | (connected to 'in1' and 'in2) has an output connected to the input of a 13 | two-input XOR. The second input of the XOR is 'in3.' The output of the 14 | XOR is 'out'. 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob029_m2014_q4g_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input in1, 4 | input in2, 5 | input in3, 6 | output logic out 7 | ); 8 | 9 | assign out = (~(in1 ^ in2)) ^ in3; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob030_popcount255_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (255 bits) 7 | - output out ( 8 bits) 8 | 9 | A "population count" circuit counts the number of '1's in an input 10 | vector. The module should implement a population count circuit for a 11 | 255-bit input vector. 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob030_popcount255_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [254:0] in, 4 | output reg [7:0] out 5 | ); 6 | 7 | always_comb begin 8 | out = 0; 9 | for (int i=0;i<255;i++) 10 | out = out + in[i]; 11 | end 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob031_dff_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input d 8 | - input q 9 | 10 | The module should implement a single D flip-flop. Assume all sequential 11 | logic is triggered on the positive edge of the clock. 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob031_dff_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input d, 5 | output reg q 6 | ); 7 | 8 | initial 9 | q = 1'hx; 10 | 11 | always @(posedge clk) 12 | q <= d; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob032_vector0_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input vec (3 bits) 7 | - output outv (3 bits) 8 | - output o2 9 | - output o1 10 | - output o0 11 | 12 | The module has one 3-bit input, then outputs the same vector, and also 13 | splits it into three separate 1-bit outputs. Connect output o0 to the 14 | input vector's position 0, o1 to position 1, etc. 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob032_vector0_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [2:0] vec, 4 | output [2:0] outv, 5 | output o2, 6 | output o1, 7 | output o0 8 | ); 9 | 10 | assign outv = vec; 11 | assign {o2, o1, o0} = vec; 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob033_ece241_2014_q1c_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a (8 bits) 7 | - input b (8 bits) 8 | - output s (8 bits) 9 | - output overflow 10 | 11 | Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. 12 | The module should add these numbers to produce s[7:0]. Also compute 13 | whether a (signed) overflow has occurred. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob033_ece241_2014_q1c_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [7:0] a, 4 | input [7:0] b, 5 | output [7:0] s, 6 | output overflow 7 | ); 8 | 9 | wire [8:0] sum = a+b; 10 | assign s = sum[7:0]; 11 | assign overflow = !(a[7]^b[7]) && (a[7] != s[7]); 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob034_dff8_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input d (8 bits) 8 | - output q (8 bits) 9 | 10 | The module should include 8 D flip-flops. All DFFs should be triggered by 11 | the positive edge of clock. 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob034_dff8_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input [7:0] d, 5 | output reg [7:0] q 6 | ); 7 | 8 | initial 9 | q = 8'h0; 10 | 11 | always @(posedge clk) 12 | q <= d; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob035_count1to10_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input reset 8 | - output q (4 bits) 9 | 10 | The module should implement a decade counter that counts 1 through 10, 11 | inclusive. Assume all sequential logic is triggered on the positive edge 12 | of the clock. The reset input is active high synchronous, and should 13 | reset the counter to 1. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob035_count1to10_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | output reg [3:0] q 6 | ); 7 | 8 | always @(posedge clk) 9 | if (reset || q == 10) 10 | q <= 1; 11 | else 12 | q <= q+1; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob036_ringer_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input ring, 4 | input vibrate_mode, 5 | output ringer, 6 | output motor 7 | ); 8 | 9 | assign ringer = ring & ~vibrate_mode; 10 | assign motor = ring & vibrate_mode; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob037_review2015_count1k_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input reset 8 | - output q (10 bits) 9 | 10 | The module should implement a counter that counts from 0 to 999, 11 | inclusive, with a period of 1000 cycles. Assume all sequential logic is 12 | triggered on the positive edge of the clock. The reset input is active 13 | high synchronous, and should reset the counter to 0. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob037_review2015_count1k_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | output reg [9:0] q 6 | ); 7 | 8 | always @(posedge clk) 9 | if (reset || q == 999) 10 | q <= 0; 11 | else 12 | q <= q+1; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob038_count15_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input reset 8 | - output q (4 bits) 9 | 10 | The module should implement a 4-bit binary counter that counts from 0 11 | through 15, inclusive, with a period of 16. Assume all sequential logic 12 | is triggered on the positive edge of the clock. The reset input is active 13 | high synchronous, and should reset the counter to 0. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob038_count15_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | output reg [3:0] q 6 | ); 7 | 8 | always @(posedge clk) 9 | if (reset) 10 | q <= 0; 11 | else 12 | q <= q+1; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob039_always_if_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - input sel_b1 9 | - input sel_b2 10 | - output out_assign 11 | - output out_always 12 | 13 | The module should implement a 2-to-1 mux that chooses between a and b. 14 | Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the 15 | same twice, once using assign statements and once using a procedural if 16 | statement. 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob039_always_if_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input sel_b1, 6 | input sel_b2, 7 | output out_assign, 8 | output reg out_always 9 | ); 10 | 11 | assign out_assign = (sel_b1 & sel_b2) ? b : a; 12 | always @(*) out_always = (sel_b1 & sel_b2) ? b : a; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob040_count10_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input reset 8 | - output q (4 bits) 9 | 10 | The module should implement a decade counter that counts from 0 through 11 | 9, inclusive, with a period of 10. Assume all sequential logic is 12 | triggered on the positive edge of the clock. The reset input is active 13 | high synchronous, and should reset the counter to 0. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob040_count10_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | output reg [3:0] q 6 | ); 7 | 8 | always @(posedge clk) 9 | if (reset || q == 9) 10 | q <= 0; 11 | else 12 | q <= q+1; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob041_dff8r_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input reset 8 | - input d (8 bits) 9 | - output q (8 bits) 10 | 11 | The module should include 8 D flip-flops with active high synchronous 12 | reset setting the output to zero. All DFFs should be triggered by the 13 | positive edge of clk. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob041_dff8r_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input [7:0] d, 5 | input reset, 6 | output reg [7:0] q 7 | ); 8 | 9 | always @(posedge clk) 10 | if (reset) 11 | q <= 0; 12 | else 13 | q <= d; 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob042_vector4_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [7:0] in, 4 | output [31:0] out 5 | ); 6 | 7 | assign out = { {24{in[7]}}, in }; 8 | 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob043_vector5_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - input c 9 | - input d 10 | - input e 11 | - output out (25 bits) 12 | 13 | Implement a module that given five 1-bit signals (a, b, c, d, and e), 14 | compute all 25 pairwise one-bit comparisons in the 25-bit output vector. 15 | The output should be 1 if the two bits being compared are equal. Example: 16 | out[24] = ~a ^ a; out[23] = ~a ^ b; out[22] = ~a ^ c; ... 17 | out[ 1] = ~e ^ d; out[ 0] = ~e ^ e. 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob043_vector5_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | input e, 8 | output [24:0] out 9 | ); 10 | 11 | assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}}; 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob044_vectorgates_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [2:0] a, 4 | input [2:0] b, 5 | output [2:0] out_or_bitwise, 6 | output out_or_logical, 7 | output [5:0] out_not 8 | ); 9 | 10 | assign out_or_bitwise = a | b; 11 | assign out_or_logical = a || b; 12 | assign out_not = {~b,~a}; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob045_edgedetect2_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input in (8 bits) 8 | - output anyedge (8 bits) 9 | 10 | Implement a module that for each bit in an 8-bit input vector, detect 11 | when the input signal changes from one clock cycle to the next (detect 12 | any edge). The output bit of output_anyedge should be set to 1 the cycle 13 | after the input bit has 0 to 1 or 1 to 0 transition occurs. Assume all 14 | sequential logic is triggered on the positive edge of the clock. 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob045_edgedetect2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input [7:0] in, 5 | output reg [7:0] anyedge 6 | ); 7 | 8 | reg [7:0] d_last; 9 | 10 | always @(posedge clk) begin 11 | d_last <= in; 12 | anyedge <= in ^ d_last; 13 | end 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob046_dff8p_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input reset 8 | - input d (8 bits) 9 | - output q (8 bits) 10 | 11 | Implement a module that includes 8 D flip-flops with active high 12 | synchronous reset. The flip-flops must be reset to 0x34 rather than zero. 13 | All DFFs should be triggered by the negative edge of clk. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob046_dff8p_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input [7:0] d, 5 | input reset, 6 | output reg [7:0] q 7 | ); 8 | 9 | always @(negedge clk) 10 | if (reset) 11 | q <= 8'h34; 12 | else 13 | q <= d; 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob047_dff8ar_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input areset 8 | - input d (8 bits) 9 | - output q (8 bits) 10 | 11 | The module should include 8 D flip-flops with active high asynchronous 12 | reset. The output should be reset to 0. All DFFs should be triggered by 13 | the positive edge of clk. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob047_dff8ar_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input [7:0] d, 5 | input areset, 6 | output reg [7:0] q 7 | ); 8 | 9 | always @(posedge clk, posedge areset) 10 | if (areset) 11 | q <= 0; 12 | else 13 | q <= d; 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob048_m2014_q4c_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input d 8 | - input r 9 | - output q 10 | 11 | The module should implement a simple D flip flop with active high 12 | synchronous reset (reset output to 0). 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob048_m2014_q4c_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input d, 5 | input r, 6 | output logic q 7 | ); 8 | 9 | always@(posedge clk) begin 10 | if (r) 11 | q <= 0; 12 | else 13 | q <= d; 14 | end 15 | 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob049_m2014_q4b_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input ar 8 | - input d 9 | - output q 10 | 11 | The module should implement a D flip flop, positive edge triggered, with 12 | an asynchronous reset "ar". 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob049_m2014_q4b_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input d, 5 | input ar, 6 | output logic q 7 | ); 8 | 9 | always@(posedge clk or posedge ar) begin 10 | if (ar) 11 | q <= 0; 12 | else 13 | q <= d; 14 | end 15 | 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob050_kmap1_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - input c 9 | - output out 10 | 11 | The module should implement the circuit described by the Karnaugh map 12 | below. 13 | 14 | a 15 | bc 0 1 16 | 00 | 0 | 1 | 17 | 01 | 1 | 1 | 18 | 11 | 1 | 1 | 19 | 10 | 1 | 1 | 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob050_kmap1_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | output out 7 | ); 8 | 9 | assign out = (a | b | c); 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob051_gates4_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (4 bits) 7 | - output out_and 8 | - output out_or 9 | - output out_xor 10 | 11 | The module should implement a combinational circuit with four inputs, 12 | in[3:0]. There are 3 outputs: 13 | 14 | (1) out_and : output of a 4-input AND gate 15 | (2) out_or : output of a 4-input OR gate 16 | (3) out_xor : output of a 4-input XOR gate 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob051_gates4_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [3:0] in, 4 | output out_and, 5 | output out_or, 6 | output out_xor 7 | ); 8 | 9 | assign out_and = ∈ 10 | assign out_or = |in; 11 | assign out_xor = ^in; 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob052_gates100_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (100 bits) 7 | - output out_and 8 | - output out_or 9 | - output out_xor 10 | 11 | The module should implement a combinational circuit with 100 inputs, 12 | in[99:0]. There are 3 outputs: 13 | 14 | (1) out_and : output of a 100-input AND gate 15 | (2) out_or : output of a 100-input OR gate 16 | (3) out_xor : output of a 100-input XOR gate 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob052_gates100_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [99:0] in, 4 | output out_and, 5 | output out_or, 6 | output out_xor 7 | ); 8 | 9 | assign out_and = ∈ 10 | assign out_or = |in; 11 | assign out_xor = ^in; 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob053_m2014_q4d_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input in 8 | - output out 9 | 10 | The module should implement the following circuit: A D flip-flop takes as 11 | input the output of a two-input XOR. The flip-flop is positive edge 12 | triggered by clk, but there is no reset. The XOR takes as input 'in' 13 | along with the output 'out' of the flip-flop. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob053_m2014_q4d_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input in, 5 | output logic out 6 | ); 7 | 8 | initial 9 | out = 0; 10 | 11 | always@(posedge clk) begin 12 | out <= in ^ out; 13 | end 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob054_edgedetect_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input in (8 bits) 8 | - output pedge (8 bits) 9 | 10 | The module should examine each bit in an 8-bit vector and detect when the 11 | input signal changes from 0 in one clock cycle to 1 the next (similar to 12 | positive edge detection). The output bit should be set the cycle after a 13 | 0 to 1 transition occurs. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob054_edgedetect_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input [7:0] in, 5 | output reg [7:0] pedge 6 | ); 7 | 8 | reg [7:0] d_last; 9 | 10 | always @(posedge clk) begin 11 | d_last <= in; 12 | pedge <= in & ~d_last; 13 | end 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob055_conditional_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a (8 bits) 7 | - input b (8 bits) 8 | - input c (8 bits) 9 | - input d (8 bits) 10 | - output min (8 bits) 11 | 12 | The module should find the minimum of the four input values. Unsigned 13 | numbers can be compared with standard comparison operators (a < b). 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob055_conditional_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [7:0] a, 4 | input [7:0] b, 5 | input [7:0] c, 6 | input [7:0] d, 7 | output reg [7:0] min 8 | ); 9 | 10 | always_comb begin 11 | min = a; 12 | if (min > b) min = b; 13 | if (min > c) min = c; 14 | if (min > d) min = d; 15 | end 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob056_ece241_2013_q7_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input j 8 | - input k 9 | - output Q 10 | 11 | The module should implement a JK flip-flop with the following truth 12 | table. Note: Qold is the output of the flip-flop before the positive 13 | clock edge. 14 | 15 | J | K | Q 16 | 0 | 0 | Qold 17 | 0 | 1 | 0 18 | 1 | 0 | 1 19 | 1 | 1 | ~Qold 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob056_ece241_2013_q7_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input j, 5 | input k, 6 | output reg Q 7 | ); 8 | 9 | always @(posedge clk) 10 | Q <= j&~Q | ~k&Q; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob057_kmap2_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - input c 9 | - input d 10 | - output out 11 | 12 | The module should implement the circuit described by the Karnaugh map 13 | below. 14 | 15 | a,b 16 | c,d 0,0 0,1 1,1 1,0 17 | 0,0 | 1 | 1 | 0 | 1 | 18 | 0,1 | 1 | 0 | 0 | 1 | 19 | 1,1 | 0 | 1 | 1 | 1 | 20 | 1,0 | 1 | 1 | 0 | 0 | 21 | 22 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob057_kmap2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output out 8 | ); 9 | 10 | assign out = (~c & ~b) | (~d&~a) | (a&c&d) | (b&c&d); 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob058_alwaysblock2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input a, 5 | input b, 6 | output out_assign, 7 | output reg out_always_comb, 8 | output reg out_always_ff 9 | ); 10 | 11 | assign out_assign = a ^ b; 12 | always @(*) out_always_comb = a ^ b; 13 | always @(posedge clk) out_always_ff <= a ^ b; 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob059_wire4_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - input c 9 | - output w 10 | - output x 11 | - output y 12 | - output z 13 | 14 | The module should behave like wires that makes these connections: 15 | 16 | a -> w 17 | b -> x 18 | b -> y 19 | c -> z 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob059_wire4_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | output w, 7 | output x, 8 | output y, 9 | output z 10 | ); 11 | 12 | assign {w,x,y,z} = {a,b,b,c}; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob060_m2014_q4k_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input resetn 8 | - input in 9 | - output out 10 | 11 | The module should implement a shift register with four D flops. Assume 12 | all sequential logic is triggered on the positive edge of the clock. 13 | Reset is active-low synchronous resettable. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob060_m2014_q4k_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input resetn, 5 | input in, 6 | output out 7 | ); 8 | 9 | reg [3:0] sr; 10 | always @(posedge clk) begin 11 | if (~resetn) 12 | sr <= '0; 13 | else 14 | sr <= {sr[2:0], in}; 15 | end 16 | 17 | assign out = sr[3]; 18 | 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob061_2014_q4a_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input w 8 | - input R 9 | - input E 10 | - input L 11 | - output Q 12 | 13 | The module will be one stage in a larger n-bit shift register circuit. 14 | Input E is for enabling shift, R for value to load, L is asserted when it 15 | should load, and w is the input from the prevous stage of the shift 16 | register. Assume all sequential logic is triggered on the positive edge 17 | of the clock. 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob061_2014_q4a_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input w, 5 | input R, 6 | input E, 7 | input L, 8 | output reg Q 9 | ); 10 | 11 | always @(posedge clk) 12 | if (L) 13 | Q <= R; 14 | else if (E) 15 | Q <= w; 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob062_bugs_mux2_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | Consider the following implementation of an 8-bit 2-to-1 mux: 3 | 4 | module TopModule ( 5 | input sel, 6 | input [7:0] a, 7 | input [7:0] b, 8 | output out 9 | ); 10 | 11 | assign out = (~sel & a) | (sel & b); 12 | 13 | endmodule 14 | 15 | Unfortunately, this module has a bug. Implement a new version of this 16 | module that fixes the bug. 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob062_bugs_mux2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input sel, 4 | input [7:0] a, 5 | input [7:0] b, 6 | output reg [7:0] out 7 | ); 8 | 9 | // assign out = (~sel & a) | (sel & b); 10 | assign out = sel ? a : b; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob063_review2015_shiftcount_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input shift_ena, 5 | input count_ena, 6 | input data, 7 | output reg [3:0] q 8 | ); 9 | 10 | always @(posedge clk) begin 11 | if (shift_ena) 12 | q <= { q[2:0], data }; 13 | else if (count_ena) 14 | q <= q - 1'b1; 15 | end 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob064_vector3_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [4:0] a, 4 | input [4:0] b, 5 | input [4:0] c, 6 | input [4:0] d, 7 | input [4:0] e, 8 | input [4:0] f, 9 | output [7:0] w, 10 | output [7:0] x, 11 | output [7:0] y, 12 | output [7:0] z 13 | ); 14 | 15 | assign { w,x,y,z} = {a,b,c,d,e,f,2'b11}; 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob065_7420_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input p1a 7 | - input p1b 8 | - input p1c 9 | - input p1d 10 | - input p2a 11 | - input p2b 12 | - input p2c 13 | - input p2d 14 | - output p1y 15 | - output p2y 16 | 17 | The 7400-series integrated circuits are a series of digital chips with a 18 | few gates each. The 7420 is a chip with two 4-input NAND gates. The 19 | module should implement the same functionality as the 7420 chip. 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob065_7420_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input p1a, 4 | input p1b, 5 | input p1c, 6 | input p1d, 7 | output p1y, 8 | input p2a, 9 | input p2b, 10 | input p2c, 11 | input p2d, 12 | output p2y 13 | ); 14 | 15 | assign p1y = ~&( {p1a, p1b, p1c, p1d} ); 16 | assign p2y = ~&( {p2a, p2b, p2c, p2d} ); 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob066_edgecapture_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | input [31:0] in, 6 | output reg [31:0] out 7 | ); 8 | 9 | reg [31:0] d_last; 10 | 11 | always @(posedge clk) begin 12 | d_last <= in; 13 | if (reset) 14 | out <= '0; 15 | else 16 | out <= out | (~in & d_last); 17 | end 18 | 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob067_countslow_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input slowena, 5 | input reset, 6 | output reg [3:0] q 7 | ); 8 | 9 | always @(posedge clk) 10 | if (reset) 11 | q <= 0; 12 | else if (slowena) begin 13 | if (q == 9) 14 | q <= 0; 15 | else 16 | q <= q+1; 17 | end 18 | 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob068_countbcd_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | output [3:1] ena, 6 | output reg [15:0] q 7 | ); 8 | 9 | wire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1}; 10 | assign ena = enable[3:1]; 11 | always @(posedge clk) 12 | for (int i=0;i<4;i++) begin 13 | if (reset || (q[i*4 +:4] == 9 && enable[i])) 14 | q[i*4 +:4] <= 0; 15 | else if (enable[i]) 16 | q[i*4 +:4] <= q[i*4 +:4]+1; 17 | end 18 | 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob069_truthtable1_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input x3 7 | - input x2 8 | - input x1 9 | - output f 10 | 11 | The module should implement a combinational circuit for the following 12 | truth table: 13 | 14 | x3 | x2 | x1 | f 15 | 0 | 0 | 0 | 0 16 | 0 | 0 | 1 | 0 17 | 0 | 1 | 0 | 1 18 | 0 | 1 | 1 | 1 19 | 1 | 0 | 0 | 0 20 | 1 | 0 | 1 | 1 21 | 1 | 1 | 0 | 0 22 | 1 | 1 | 1 | 1 23 | 24 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob069_truthtable1_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input x3, 4 | input x2, 5 | input x1, 6 | output f 7 | ); 8 | 9 | assign f = ( ~x3 & x2 & ~x1 ) | 10 | ( ~x3 & x2 & x1 ) | 11 | ( x3 & ~x2 & x1 ) | 12 | ( x3 & x2 & x1 ) ; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob070_ece241_2013_q2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output out_sop, 8 | output out_pos 9 | ); 10 | 11 | assign out_sop = c&d | ~a&~b&c; 12 | assign out_pos = (~a & ~b & c) | (b & c & d) | (a & c & d); 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob071_always_casez_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input in (8 bits) 7 | - output pos (3 bits) 8 | 9 | The module should implement a priority encoder for an 8-bit input. Given 10 | an 8-bit vector, the output should report the first (least significant) 11 | bit in the vector that is 1. Report zero if the input vector has no bits 12 | that are high. For example, the input 8'b10010000 should output 3'd4, 13 | because bit[4] is first bit that is high. 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob071_always_casez_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [7:0] in, 4 | output reg [2:0] pos 5 | ); 6 | 7 | always @(*) begin 8 | casez (in) 9 | default : pos = 2'h0; 10 | 8'bzzzzzzz1: pos = 3'h0; 11 | 8'bzzzzzz1z: pos = 3'h1; 12 | 8'bzzzzz1zz: pos = 3'h2; 13 | 8'bzzzz1zzz: pos = 3'h3; 14 | 8'bzzz1zzzz: pos = 3'h4; 15 | 8'bzz1zzzzz: pos = 3'h5; 16 | 8'bz1zzzzzz: pos = 3'h6; 17 | 8'b1zzzzzzz: pos = 3'h7; 18 | endcase 19 | end 20 | 21 | endmodule 22 | 23 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob072_thermostat_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input mode, 4 | input too_cold, 5 | input too_hot, 6 | input fan_on, 7 | output heater, 8 | output aircon, 9 | output fan 10 | ); 11 | 12 | assign fan = (mode ? too_cold : too_hot) | fan_on; 13 | assign heater = (mode & too_cold); 14 | assign aircon = (~mode & too_hot); 15 | 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob073_dff16e_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input resetn, 5 | input [1:0] byteena, 6 | input [15:0] d, 7 | output reg [15:0] q 8 | ); 9 | 10 | always @(posedge clk) begin 11 | if (!resetn) 12 | q <= 0; 13 | else begin 14 | if (byteena[0]) 15 | q[7:0] <= d[7:0]; 16 | if (byteena[1]) 17 | q[15:8] <= d[15:8]; 18 | end 19 | end 20 | 21 | endmodule 22 | 23 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob074_ece241_2014_q4_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input x, 5 | output z 6 | ); 7 | 8 | reg [2:0] s = 0; 9 | 10 | always @(posedge clk) begin 11 | s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x }; 12 | end 13 | 14 | assign z = ~|s; 15 | 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob075_counter_2bc_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input areset, 5 | input train_valid, 6 | input train_taken, 7 | output logic [1:0] state 8 | ); 9 | 10 | always @(posedge clk, posedge areset) begin 11 | if (areset) 12 | state <= 1; 13 | else if (train_valid) begin 14 | if(state < 3 && train_taken) 15 | state <= state + 1; 16 | else if(state > 0 && !train_taken) 17 | state <= state - 1; 18 | end 19 | end 20 | 21 | endmodule 22 | 23 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob076_always_case_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input sel (3 bits) 7 | - input data0 (4 bits) 8 | - input data1 (4 bits) 9 | - input data2 (4 bits) 10 | - input data3 (4 bits) 11 | - input data4 (4 bits) 12 | - input data5 (4 bits) 13 | - output out (4 bits) 14 | ); 15 | 16 | The module should implement a 6-to-1 multiplexer. When sel is between 0 17 | and 5, choose the corresponding data input. Otherwise, output 0. The data 18 | inputs and outputs are all 4 bits wide. 19 | 20 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob076_always_case_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [2:0] sel, 4 | input [3:0] data0, 5 | input [3:0] data1, 6 | input [3:0] data2, 7 | input [3:0] data3, 8 | input [3:0] data4, 9 | input [3:0] data5, 10 | output reg [3:0] out 11 | ); 12 | 13 | always @(*) begin 14 | case (sel) 15 | 3'h0: out = data0; 16 | 3'h1: out = data1; 17 | 3'h2: out = data2; 18 | 3'h3: out = data3; 19 | 3'h4: out = data4; 20 | 3'h5: out = data5; 21 | default: out = 4'b0; 22 | endcase 23 | end 24 | 25 | endmodule 26 | 27 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob077_wire_decl_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output out, 8 | output out_n 9 | ); 10 | 11 | wire w1, w2; 12 | assign w1 = a&b; 13 | assign w2 = c&d; 14 | assign out = w1|w2; 15 | assign out_n = ~out; 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob078_dualedge_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input d 8 | - output q 9 | 10 | A dual-edge triggered flip-flop is triggered on both edges of the clock. 11 | However, FPGAs don't have dual-edge triggered flip-flops, and using an 12 | always @(posedge clk or negedge clk) is not accepted as a legal 13 | sensitivity list. Build a circuit that functionally behaves like a 14 | dual-edge triggered flip-flop. 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob078_dualedge_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input d, 5 | output reg q 6 | ); 7 | 8 | /*always @(posedge clk, negedge clk) begin 9 | q <= d; 10 | end*/ 11 | 12 | reg qp, qn; 13 | always @(posedge clk) 14 | qp <= d; 15 | always @(negedge clk) 16 | qn <= d; 17 | 18 | // This causes q to change too early when clk changes. Need delay by 19 | // delta cycle 20 | // assign q = clk ? qp : qn; 21 | always @(*) 22 | q <= clk ? qp : qn; 23 | 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob079_fsm3onehot_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input in, 4 | input [3:0] state, 5 | output reg [3:0] next_state, 6 | output out 7 | ); 8 | 9 | parameter A=0, B=1, C=2, D=3; 10 | 11 | assign next_state[A] = (state[A] | state[C]) & ~in; 12 | assign next_state[B] = (state[A] | state[B] | state[D]) & in; 13 | assign next_state[C] = (state[B] | state[D]) & ~in; 14 | assign next_state[D] = state[C] & in; 15 | 16 | assign out = (state[D]); 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob080_timer_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input load, 5 | input [9:0] data, 6 | output tc 7 | ); 8 | 9 | logic [9:0] count_value; 10 | 11 | always @(posedge clk) 12 | if(load) count_value <= data; 13 | else if(count_value != 0) count_value <= count_value - 1; 14 | 15 | assign tc = count_value == 0; 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob081_7458_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input p1a, 4 | input p1b, 5 | input p1c, 6 | input p1d, 7 | input p1e, 8 | input p1f, 9 | output p1y, 10 | input p2a, 11 | input p2b, 12 | input p2c, 13 | input p2d, 14 | output p2y 15 | ); 16 | 17 | assign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f}; 18 | assign p2y = &{p2a, p2b} | &{p2c, p2d}; 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob082_lfsr32_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | output reg [31:0] q 6 | ); 7 | 8 | logic [31:0] q_next; 9 | always@(q) begin 10 | q_next = q[31:1]; 11 | q_next[31] = q[0]; 12 | q_next[21] ^= q[0]; 13 | q_next[1] ^= q[0]; 14 | q_next[0] ^= q[0]; 15 | end 16 | 17 | always @(posedge clk) begin 18 | if (reset) 19 | q <= 32'h1; 20 | else 21 | q <= q_next; 22 | end 23 | 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob083_mt2015_q4b_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input x, 4 | input y, 5 | output z 6 | ); 7 | 8 | assign z = ~(x^y); 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob084_ece241_2013_q12_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input enable, 5 | input S, 6 | input A, 7 | input B, 8 | input C, 9 | output reg Z 10 | ); 11 | 12 | reg [7:0] q; 13 | always @(posedge clk) begin 14 | if (enable) 15 | q <= {q[6:0], S}; 16 | end 17 | 18 | assign Z = q[ {A, B, C} ]; 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob085_shift4_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input areset, 5 | input load, 6 | input ena, 7 | input [3:0] data, 8 | output reg [3:0] q 9 | ); 10 | 11 | always @(posedge clk, posedge areset) begin 12 | if (areset) 13 | q <= 0; 14 | else if (load) 15 | q <= data; 16 | else if (ena) 17 | q <= q[3:1]; 18 | end 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob086_lfsr5_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | output reg [4:0] q 6 | ); 7 | 8 | logic [4:0] q_next; 9 | always @(q) begin 10 | q_next = q[4:1]; 11 | q_next[4] = q[0]; 12 | q_next[2] ^= q[0]; 13 | end 14 | 15 | always @(posedge clk) begin 16 | if (reset) 17 | q <= 5'h1; 18 | else 19 | q <= q_next; 20 | end 21 | 22 | endmodule 23 | 24 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob087_gates_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | output out_and, 6 | output out_or, 7 | output out_xor, 8 | output out_nand, 9 | output out_nor, 10 | output out_xnor, 11 | output out_anotb 12 | ); 13 | 14 | assign out_and = a&b; 15 | assign out_or = a|b; 16 | assign out_xor = a^b; 17 | assign out_nand = ~(a&b); 18 | assign out_nor = ~(a|b); 19 | assign out_xnor = a^~b; 20 | assign out_anotb = a & ~b; 21 | 22 | endmodule 23 | 24 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob088_ece241_2014_q5b_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input areset, 5 | input x, 6 | output z 7 | ); 8 | 9 | parameter A=0,B=1; 10 | reg state; 11 | always @(posedge clk, posedge areset) begin 12 | if (areset) 13 | state <= A; 14 | else begin 15 | case (state) 16 | A: state <= x ? B : A; 17 | B: state <= B; 18 | endcase 19 | end 20 | end 21 | 22 | assign z = (state == A && x==1) | (state == B && x==0); 23 | 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob089_ece241_2014_q5a_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input areset, 5 | input x, 6 | output z 7 | ); 8 | 9 | parameter A=0,B=1,C=2; 10 | reg [1:0] state; 11 | always @(posedge clk, posedge areset) begin 12 | if (areset) 13 | state <= A; 14 | else begin 15 | case (state) 16 | A: state <= x ? C : A; 17 | B: state <= x ? B : C; 18 | C: state <= x ? B : C; 19 | endcase 20 | end 21 | end 22 | 23 | assign z = (state == C); 24 | 25 | endmodule 26 | 27 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob090_circuit1_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | output q 6 | ); 7 | 8 | assign q = a&b; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob091_2012_q2b_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [5:0] y, 4 | input w, 5 | output Y1, 6 | output Y3 7 | ); 8 | 9 | assign Y1 = y[0]&w; 10 | assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob092_gatesv100_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [99:0] in, 4 | output [99:0] out_both, 5 | output [99:0] out_any, 6 | output [99:0] out_different 7 | ); 8 | 9 | assign out_both = { 1'b0, (in[98:0] & in[99:1]) }; 10 | 11 | assign out_any = { (in[98:0] | in[99:1]), 1'b0 }; 12 | 13 | assign out_different = in ^ { in[0], in[99:1] }; 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob093_ece241_2014_q3_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input c, 4 | input d, 5 | output [3:0] mux_in 6 | ); 7 | 8 | assign mux_in[0] = c | d; 9 | assign mux_in[1] = 0; 10 | assign mux_in[2] = ~d; 11 | assign mux_in[3] = c&d; 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob094_gatesv_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [3:0] in, 4 | output [3:0] out_both, 5 | output [3:0] out_any, 6 | output [3:0] out_different 7 | ); 8 | 9 | assign out_both[2:0] = in[2:0] & in[3:1]; 10 | assign out_any[3:1] = in[2:0] | in[3:1]; 11 | assign out_different = in^{in[0], in[3:1]}; 12 | 13 | // we don't care about out_both[3] or out_any[0] 14 | assign out_both[3] = 1'bx; 15 | assign out_any[0] = 1'bx; 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob095_review2015_fsmshift_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | output shift_ena 6 | ); 7 | 8 | parameter B0=0, B1=1, B2=2, B3=3, Done=4; 9 | 10 | reg [2:0] state, next; 11 | 12 | always_comb begin 13 | case (state) 14 | B0: next = B1; 15 | B1: next = B2; 16 | B2: next = B3; 17 | B3: next = Done; 18 | Done: next = Done; 19 | endcase 20 | end 21 | 22 | always @(posedge clk) 23 | if (reset) state <= B0; 24 | else state <= next; 25 | 26 | assign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3); 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob096_review2015_fsmseq_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input reset 8 | - input data 9 | - output start_shifting 10 | 11 | The module should implement a finite-state machine that searches for the 12 | sequence 1101 in an input bit stream. When the sequence is found, it 13 | should set start_shifting to 1, forever, until reset. Reset is active 14 | high synchronous. Assume all sequential logic is triggered on the 15 | positive edge of the clock. 16 | 17 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob097_mux9to1v_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [15:0] a, 4 | input [15:0] b, 5 | input [15:0] c, 6 | input [15:0] d, 7 | input [15:0] e, 8 | input [15:0] f, 9 | input [15:0] g, 10 | input [15:0] h, 11 | input [15:0] i, 12 | input [3:0] sel, 13 | output logic [15:0] out 14 | ); 15 | 16 | always @(*) begin 17 | out = '1; 18 | case (sel) 19 | 4'h0: out = a; 20 | 4'h1: out = b; 21 | 4'h2: out = c; 22 | 4'h3: out = d; 23 | 4'h4: out = e; 24 | 4'h5: out = f; 25 | 4'h6: out = g; 26 | 4'h7: out = h; 27 | 4'h8: out = i; 28 | endcase 29 | end 30 | 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob098_circuit7_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input a, 5 | output reg q 6 | ); 7 | 8 | always @(posedge clk) 9 | q <= ~a; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob099_m2014_q6c_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [5:0] y, 4 | input w, 5 | output Y1, 6 | output Y3 7 | ); 8 | 9 | assign Y1 = y[0]&~w; 10 | assign Y3 = (y[1]|y[2]|y[4]|y[5]) & w; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob100_fsm3comb_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input in, 4 | input [1:0] state, 5 | output reg [1:0] next_state, 6 | output out 7 | ); 8 | 9 | parameter A=0, B=1, C=2, D=3; 10 | 11 | always_comb begin 12 | case (state) 13 | A: next_state = in ? B : A; 14 | B: next_state = in ? B : C; 15 | C: next_state = in ? D : A; 16 | D: next_state = in ? B : C; 17 | endcase 18 | end 19 | 20 | assign out = (state==D); 21 | 22 | endmodule 23 | 24 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob101_circuit4_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output q 8 | ); 9 | 10 | assign q = c | b; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob102_circuit3_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output q 8 | ); 9 | 10 | assign q = (a|b) & (c|d); 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob103_circuit2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output q 8 | ); 9 | 10 | assign q = ~a^b^c^d; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob104_mt2015_muxdff_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input L, 5 | input q_in, 6 | input r_in, 7 | output reg Q 8 | ); 9 | 10 | initial Q=0; 11 | always @(posedge clk) 12 | Q <= L ? r_in : q_in; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob105_rotate100_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input load, 5 | input [1:0] ena, 6 | input [99:0] data, 7 | output reg [99:0] q 8 | ); 9 | 10 | always @(posedge clk) begin 11 | if (load) 12 | q <= data; 13 | else if (ena == 2'h1) 14 | q <= {q[0], q[99:1]}; 15 | else if (ena == 2'h2) 16 | q <= {q[98:0], q[99]}; 17 | end 18 | 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob106_always_nolatches_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [15:0] scancode, 4 | output reg left, 5 | output reg down, 6 | output reg right, 7 | output reg up 8 | ); 9 | 10 | always @(*) begin 11 | {up, left, down, right} = 0; 12 | case (scancode) 13 | 16'he06b: left = 1; 14 | 16'he072: down = 1; 15 | 16'he074: right = 1; 16 | 16'he075: up = 1; 17 | endcase 18 | end 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob107_fsm1s_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input reset 8 | - input in 9 | - output out 10 | 11 | Implement the following Moore state machine with two states, one input, 12 | and one output. The reset state is B and reset is active-high 13 | synchronous. 14 | 15 | B (out=1) --in=0--> A 16 | B (out=1) --in=1--> B 17 | A (out=0) --in=0--> B 18 | A (out=0) --in=1--> A 19 | 20 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob107_fsm1s_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input in, 5 | input reset, 6 | output out 7 | ); 8 | 9 | parameter A=0, B=1; 10 | reg state; 11 | reg next; 12 | 13 | always_comb begin 14 | case (state) 15 | A: next = in ? A : B; 16 | B: next = in ? B : A; 17 | endcase 18 | end 19 | 20 | always @(posedge clk) begin 21 | if (reset) state <= B; 22 | else state <= next; 23 | end 24 | 25 | assign out = (state==B); 26 | 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob108_rule90_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input load, 5 | input [511:0] data, 6 | output reg [511:0] q 7 | ); 8 | 9 | always @(posedge clk) begin 10 | if (load) 11 | q <= data; 12 | else begin 13 | q <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ; 14 | end 15 | end 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob109_fsm1_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input areset 8 | - input in 9 | - output out 10 | 11 | The module should implement a Moore machine with the diagram described 12 | below: 13 | 14 | B (1) --0--> A 15 | B (1) --1--> B 16 | A (0) --0--> B 17 | A (0) --1--> A 18 | 19 | It should asynchronously reset into state B if reset if high. 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob109_fsm1_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input in, 5 | input areset, 6 | output out 7 | ); 8 | 9 | parameter A=0, B=1; 10 | reg state; 11 | reg next; 12 | 13 | always_comb begin 14 | case (state) 15 | A: next = in ? A : B; 16 | B: next = in ? B : A; 17 | endcase 18 | end 19 | 20 | always @(posedge clk, posedge areset) begin 21 | if (areset) state <= B; 22 | else state <= next; 23 | end 24 | 25 | assign out = (state==B); 26 | 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob110_fsm2_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input areset 8 | - input j 9 | - input k 10 | - output out 11 | 12 | The module should implement a Moore state machine with two states, two 13 | inputs, and one output according to diagram described below. Reset is an 14 | active-high asynchronous reset to state OFF. 15 | 16 | OFF (out=0) --j=0--> OFF 17 | OFF (out=0) --j=1--> ON 18 | ON (out=1) --k=0--> ON 19 | ON (out=1) --k=1--> OFF 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob110_fsm2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input j, 5 | input k, 6 | input areset, 7 | output out 8 | ); 9 | 10 | parameter A=0, B=1; 11 | reg state; 12 | reg next; 13 | 14 | always_comb begin 15 | case (state) 16 | A: next = j ? B : A; 17 | B: next = k ? A : B; 18 | endcase 19 | end 20 | 21 | always @(posedge clk, posedge areset) begin 22 | if (areset) state <= A; 23 | else state <= next; 24 | end 25 | 26 | assign out = (state==B); 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob111_fsm2s_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input clk 7 | - input reset 8 | - input j 9 | - input k 10 | - output out 11 | 12 | The module should implement a Moore state machine with two states, two 13 | inputs, and one output according to diagram described below. Reset is an 14 | active-high synchronous reset to state OFF. 15 | 16 | OFF (out=0) --j=0--> OFF 17 | OFF (out=0) --j=1--> ON 18 | ON (out=1) --k=0--> ON 19 | ON (out=1) --k=1--> OFF 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob111_fsm2s_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input j, 5 | input k, 6 | input reset, 7 | output out 8 | ); 9 | 10 | parameter A=0, B=1; 11 | reg state; 12 | reg next; 13 | 14 | always_comb begin 15 | case (state) 16 | A: next = j ? B : A; 17 | B: next = k ? A : B; 18 | endcase 19 | end 20 | 21 | always @(posedge clk) begin 22 | if (reset) state <= A; 23 | else state <= next; 24 | end 25 | 26 | assign out = (state==B); 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob113_2012_q1g_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input x (4 bits) 7 | - output f 8 | 9 | The module should implement the function f shown in the Karnaugh map 10 | below. 11 | 12 | x[1],x[0] 13 | x[3],x[2] 0,0 0,1 1,1 1,0 14 | 0,0 | 1 | 1 | 0 | 0 | 15 | 0,1 | 1 | 1 | 0 | 1 | 16 | 1,1 | 1 | 0 | 1 | 1 | 17 | 1,0 | 0 | 0 | 0 | 0 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob113_2012_q1g_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [3:0] x, 4 | output logic f 5 | ); 6 | 7 | always_comb begin 8 | case (x) 9 | 4'h0: f = 1; 10 | 4'h1: f = 1; 11 | 4'h2: f = 0; 12 | 4'h3: f = 0; 13 | 4'h4: f = 1; 14 | 4'h5: f = 1; 15 | 4'h6: f = 1; 16 | 4'h7: f = 0; 17 | 4'h8: f = 0; 18 | 4'h9: f = 0; 19 | 4'ha: f = 0; 20 | 4'hb: f = 0; 21 | 4'hc: f = 1; 22 | 4'hd: f = 0; 23 | 4'he: f = 1; 24 | 4'hf: f = 1; 25 | endcase 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob115_shift18_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input load, 5 | input ena, 6 | input [1:0] amount, 7 | input [63:0] data, 8 | output reg [63:0] q 9 | ); 10 | 11 | always @(posedge clk) begin 12 | if (load) 13 | q <= data; 14 | else if (ena) case (amount) 15 | 2'b00: q <= {q[62:0], 1'b0}; 16 | 2'b01: q <= {q[55:0], 8'b0}; 17 | 2'b10: q <= {q[63], q[63:1]}; 18 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; 19 | default: q <= 64'hx; 20 | endcase 21 | end 22 | 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob116_m2014_q3_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [3:0] x, 4 | output logic f 5 | ); 6 | 7 | always_comb begin 8 | case (x) 9 | 4'h0: f = 1'bx; 10 | 4'h1: f = 1'bx; 11 | 4'h2: f = 0; 12 | 4'h3: f = 1'bx; 13 | 4'h4: f = 1; 14 | 4'h5: f = 1'bx; 15 | 4'h6: f = 1; 16 | 4'h7: f = 0; 17 | 4'h8: f = 0; 18 | 4'h9: f = 0; 19 | 4'ha: f = 1'bx; 20 | 4'hb: f = 1; 21 | 4'hc: f = 1; 22 | 4'hd: f = 1'bx; 23 | 4'he: f = 1; 24 | 4'hf: f = 1'bx; 25 | endcase 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob117_circuit9_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input a, 5 | output reg [2:0] q 6 | ); 7 | 8 | always @(posedge clk) 9 | if (a) 10 | q <= 4; 11 | else if (q == 6) 12 | q <= 0; 13 | else 14 | q <= q + 1'b1; 15 | 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob118_history_shift_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input areset, 5 | input predict_valid, 6 | input predict_taken, 7 | output logic [31:0] predict_history, 8 | 9 | input train_mispredicted, 10 | input train_taken, 11 | input [31:0] train_history 12 | ); 13 | 14 | always@(posedge clk, posedge areset) 15 | if (areset) begin 16 | predict_history = 0; 17 | end else begin 18 | if (train_mispredicted) 19 | predict_history <= {train_history, train_taken}; 20 | else if (predict_valid) 21 | predict_history <= {predict_history, predict_taken}; 22 | end 23 | 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob119_fsm3_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input in, 5 | input areset, 6 | output out 7 | ); 8 | 9 | parameter A=0, B=1, C=2, D=3; 10 | reg [1:0] state; 11 | reg [1:0] next; 12 | 13 | always_comb begin 14 | case (state) 15 | A: next = in ? B : A; 16 | B: next = in ? B : C; 17 | C: next = in ? D : A; 18 | D: next = in ? B : C; 19 | endcase 20 | end 21 | 22 | always @(posedge clk, posedge areset) begin 23 | if (areset) state <= A; 24 | else state <= next; 25 | end 26 | 27 | assign out = (state==D); 28 | 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob120_fsm3s_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input in, 5 | input reset, 6 | output out 7 | ); 8 | 9 | parameter A=0, B=1, C=2, D=3; 10 | reg [1:0] state; 11 | reg [1:0] next; 12 | 13 | always_comb begin 14 | case (state) 15 | A: next = in ? B : A; 16 | B: next = in ? B : C; 17 | C: next = in ? D : A; 18 | D: next = in ? B : C; 19 | endcase 20 | end 21 | 22 | always @(posedge clk) begin 23 | if (reset) state <= A; 24 | else state <= next; 25 | end 26 | 27 | assign out = (state==D); 28 | 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob121_2014_q3bfsm_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input reset, 5 | input x, 6 | output reg z 7 | ); 8 | 9 | parameter A=0, B=1, C=2, D=3, E=4; 10 | reg [2:0] state, next; 11 | 12 | always @(posedge clk) begin 13 | if (reset) state <= A; 14 | else state <= next; 15 | end 16 | 17 | always_comb begin 18 | case (state) 19 | A: next = x ? B : A; 20 | B: next = x ? E : B; 21 | C: next = x ? B : C; 22 | D: next = x ? C : B; 23 | E: next = x ? E : D; 24 | default: next = 'x; 25 | endcase 26 | end 27 | 28 | assign z = (state == D) || (state == E); 29 | 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob122_kmap4_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - input c 9 | - input d 10 | - output out 11 | 12 | The module should implement the Karnaugh map below. 13 | 14 | ab 15 | cd 00 01 11 10 16 | 00 | 0 | 1 | 0 | 1 | 17 | 01 | 1 | 0 | 1 | 0 | 18 | 11 | 0 | 1 | 0 | 1 | 19 | 10 | 1 | 0 | 1 | 0 | 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob122_kmap4_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output reg out 8 | ); 9 | 10 | always @(*) begin 11 | case({a,b,c,d}) 12 | 4'h0: out = 0; 13 | 4'h1: out = 1; 14 | 4'h3: out = 0; 15 | 4'h2: out = 1; 16 | 4'h4: out = 1; 17 | 4'h5: out = 0; 18 | 4'h7: out = 1; 19 | 4'h6: out = 0; 20 | 4'hc: out = 0; 21 | 4'hd: out = 1; 22 | 4'hf: out = 0; 23 | 4'he: out = 1; 24 | 4'h8: out = 1; 25 | 4'h9: out = 0; 26 | 4'hb: out = 1; 27 | 4'ha: out = 0; 28 | endcase 29 | end 30 | 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob123_bugs_addsubz_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input do_sub, 4 | input [7:0] a, 5 | input [7:0] b, 6 | output reg [7:0] out, 7 | output reg result_is_zero 8 | ); 9 | 10 | always @(*) begin 11 | case (do_sub) 12 | 0: out = a + b; 13 | 1: out = a - b; 14 | endcase 15 | result_is_zero = (out == 0); 16 | end 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob124_rule110_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input load, 5 | input [511:0] data, 6 | output reg [511:0] q 7 | ); 8 | 9 | always @(posedge clk) begin 10 | if (load) 11 | q <= data; 12 | else begin 13 | q <= 14 | ~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) | 15 | (~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) | 16 | (q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) ) 17 | ; 18 | end 19 | end 20 | 21 | endmodule 22 | 23 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob125_kmap3_prompt.txt: -------------------------------------------------------------------------------- 1 | 2 | I would like you to implement a module named TopModule with the following 3 | interface. All input and output ports are one bit unless otherwise 4 | specified. 5 | 6 | - input a 7 | - input b 8 | - input c 9 | - input d 10 | - output out 11 | 12 | The module should implement the Karnaugh map below. d is don't-care. 13 | The output out is 1'bx for don't-care case. 14 | 15 | a,b 16 | c,d 0,1 0,0 1,0 1,1 17 | 0,0 | d | 0 | 1 | 1 | 18 | 0,1 | 0 | 0 | d | d | 19 | 1,1 | 0 | 1 | 1 | 1 | 20 | 1,0 | 0 | 1 | 1 | 1 | 21 | 22 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob125_kmap3_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output reg out 8 | ); 9 | 10 | always @(*) begin 11 | case({a,b,c,d}) 12 | 4'h0: out = 0; 13 | 4'h1: out = 0; 14 | 4'h3: out = 1; 15 | 4'h2: out = 1; 16 | 4'h4: out = 1'bx; 17 | 4'h5: out = 0; 18 | 4'h7: out = 0; 19 | 4'h6: out = 0; 20 | 4'hc: out = 1; 21 | 4'hd: out = 1'bx; 22 | 4'hf: out = 1; 23 | 4'he: out = 1; 24 | 4'h8: out = 1; 25 | 4'h9: out = 1'bx; 26 | 4'hb: out = 1; 27 | 4'ha: out = 1; 28 | endcase 29 | end 30 | 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob126_circuit6_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [2:0] a, 4 | output reg [15:0] q 5 | ); 6 | 7 | always @(*) 8 | case (a) 9 | 0: q = 4658; 10 | 1: q = 44768; 11 | 2: q = 10196; 12 | 3: q = 23054; 13 | 4: q = 8294; 14 | 5: q = 25806; 15 | 6: q = 50470; 16 | 7: q = 12057; 17 | endcase 18 | 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob127_lemmings1_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input areset, 5 | input bump_left, 6 | input bump_right, 7 | output walk_left, 8 | output walk_right 9 | ); 10 | 11 | parameter WL=0, WR=1; 12 | reg state; 13 | reg next; 14 | 15 | always_comb begin 16 | case (state) 17 | WL: next = bump_left ? WR : WL; 18 | WR: next = bump_right ? WL: WR; 19 | endcase 20 | end 21 | 22 | always @(posedge clk, posedge areset) begin 23 | if (areset) state <= WL; 24 | else state <= next; 25 | end 26 | 27 | assign walk_left = (state==WL); 28 | assign walk_right = (state==WR); 29 | 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob130_circuit5_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [3:0] a, 4 | input [3:0] b, 5 | input [3:0] c, 6 | input [3:0] d, 7 | input [3:0] e, 8 | output reg [3:0] q 9 | ); 10 | 11 | always @(*) 12 | case (c) 13 | 0: q = b; 14 | 1: q = e; 15 | 2: q = a; 16 | 3: q = d; 17 | default: q = 4'hf; 18 | endcase 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob131_mt2015_q4_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input x, 4 | input y, 5 | output z 6 | ); 7 | 8 | assign z = x|~y; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob132_always_if2_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input cpu_overheated, 4 | output reg shut_off_computer, 5 | input arrived, 6 | input gas_tank_empty, 7 | output reg keep_driving 8 | ); 9 | 10 | always @(*) begin 11 | if (cpu_overheated) 12 | shut_off_computer = 1; 13 | else 14 | shut_off_computer = 0; 15 | end 16 | 17 | always @(*) begin 18 | if (~arrived) 19 | keep_driving = !gas_tank_empty; 20 | else 21 | keep_driving = 1'b0; 22 | end 23 | 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob135_m2014_q6b_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input [2:0] y, 4 | input w, 5 | output reg Y1 6 | ); 7 | 8 | always_comb begin 9 | case ({y, w}) 10 | 4'h0: Y1 = 1'b0; 11 | 4'h1: Y1 = 1'b0; 12 | 4'h2: Y1 = 1'b1; 13 | 4'h3: Y1 = 1'b1; 14 | 4'h4: Y1 = 1'b0; 15 | 4'h5: Y1 = 1'b1; 16 | 4'h6: Y1 = 1'b0; 17 | 4'h7: Y1 = 1'b0; 18 | 4'h8: Y1 = 1'b0; 19 | 4'h9: Y1 = 1'b1; 20 | 4'ha: Y1 = 1'b1; 21 | 4'hb: Y1 = 1'b1; 22 | default: Y1 = 1'bx; 23 | endcase 24 | end 25 | 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob145_circuit8_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clock, 4 | input a, 5 | output reg p, 6 | output reg q 7 | ); 8 | 9 | always @(negedge clock) 10 | q <= a; 11 | 12 | always @(*) 13 | if (clock) 14 | p = a; 15 | 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/Prob147_circuit10_ref.sv: -------------------------------------------------------------------------------- 1 | 2 | module RefModule ( 3 | input clk, 4 | input a, 5 | input b, 6 | output q, 7 | output state 8 | ); 9 | 10 | reg c; 11 | always @(posedge clk) 12 | c <= a&b | a&c | b&c; 13 | 14 | assign q = a^b^c; 15 | assign state = c; 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/dataset_dumpall/problems-temp.txt: -------------------------------------------------------------------------------- 1 | Prob001_zero 2 | Prob016_m2014_q4j 3 | Prob030_popcount255 4 | Prob033_ece241_2014_q1c 5 | Prob036_ringer 6 | Prob042_vector4 7 | Prob050_kmap1 8 | Prob060_m2014_q4k 9 | Prob092_gatesv100 10 | Prob098_circuit7 11 | Prob103_circuit2 12 | Prob107_fsm1s 13 | Prob108_rule90 14 | Prob112_always_case2 15 | Prob115_shift18 16 | Prob122_kmap4 17 | Prob127_lemmings1 18 | Prob128_fsm_ps2 19 | Prob135_m2014_q6b 20 | Prob144_conwaylife 21 | -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/2014_q4a_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic w, 5 | input logic R, 6 | input logic E, 7 | input logic L, 8 | output logic Q 9 | ); 10 | 11 | // Register to hold the current state of the output Q 12 | logic Q_reg; 13 | 14 | always @(posedge clk) begin 15 | if (L) 16 | Q_reg <= R; 17 | else if (E) 18 | Q_reg <= w; 19 | end 20 | 21 | assign Q = Q_reg; 22 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/7420_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic p1a, 4 | input logic p1b, 5 | input logic p1c, 6 | input logic p1d, 7 | input logic p2a, 8 | input logic p2b, 9 | input logic p2c, 10 | input logic p2d, 11 | output logic p1y, 12 | output logic p2y 13 | ); 14 | 15 | // Implement the first 4-input NAND gate logic for output p1y using inputs p1a, p1b, p1c, and p1d. 16 | assign p1y = ~(p1a & p1b & p1c & p1d); 17 | 18 | // Implement the second 4-input NAND gate logic for output p2y using inputs p2a, p2b, p2c, and p2d. 19 | assign p2y = ~(p2a & p2b & p2c & p2d); 20 | 21 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/always_case2_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [3:0] in, 4 | output logic [1:0] pos 5 | ); 6 | 7 | // Combinational logic 8 | 9 | always @(*) begin 10 | if (in[0]) 11 | pos = 2'b00; 12 | else if (in[1]) 13 | pos = 2'b01; 14 | else if (in[2]) 15 | pos = 2'b10; 16 | else if (in[3]) 17 | pos = 2'b11; 18 | else 19 | pos = 2'b00; 20 | end 21 | 22 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/always_casez_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [7:0] in, 4 | output logic [2:0] pos 5 | ); 6 | 7 | always @(*) begin 8 | if (in[0]) pos = 3'b000; 9 | else if (in[1]) pos = 3'b001; 10 | else if (in[2]) pos = 3'b010; 11 | else if (in[3]) pos = 3'b011; 12 | else if (in[4]) pos = 3'b100; 13 | else if (in[5]) pos = 3'b101; 14 | else if (in[6]) pos = 3'b110; 15 | else if (in[7]) pos = 3'b111; 16 | else pos = 3'b000; 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/always_if2_0.v: -------------------------------------------------------------------------------- 1 | module TopModule ( 2 | input logic cpu_overheated, 3 | output reg shut_off_computer, 4 | input logic arrived, 5 | input logic gas_tank_empty, 6 | output reg keep_driving 7 | ); 8 | 9 | always @(*) begin 10 | shut_off_computer = cpu_overheated ? 1 : 0; 11 | end 12 | 13 | always @(*) begin 14 | keep_driving = (~arrived & ~gas_tank_empty) ? 1 : 0; 15 | end 16 | 17 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/always_if_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic sel_b1, 6 | input logic sel_b2, 7 | output logic out_assign, 8 | output logic out_always 9 | ); 10 | 11 | assign out_assign = (sel_b1 & sel_b2) ? b : a; 12 | 13 | always @(*) begin 14 | if (sel_b1 & sel_b2) 15 | out_always = b; 16 | else 17 | out_always = a; 18 | end 19 | 20 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/alwaysblock1_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | output logic out_assign, 6 | output logic out_alwaysblock 7 | ); 8 | 9 | // Implement the AND gate logic using an assign statement for the output 'out_assign'. 10 | assign out_assign = a & b; 11 | 12 | // Implement the AND gate logic using a combinational always block for the output 'out_alwaysblock'. 13 | always @(*) begin 14 | out_alwaysblock = a & b; 15 | end 16 | 17 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/alwaysblock2_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic a, 5 | input logic b, 6 | output logic out_assign, 7 | output logic out_always_comb, 8 | output logic out_always_ff 9 | ); 10 | 11 | // XOR operation using assign statement 12 | assign out_assign = a ^ b; 13 | 14 | // XOR operation using combinational always block 15 | always_comb begin 16 | out_always_comb = a ^ b; 17 | end 18 | 19 | // XOR operation using clocked always block 20 | always_ff @(posedge clk) begin 21 | out_always_ff <= a ^ b; 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/andgate_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | output logic out 6 | ); 7 | 8 | assign out = a & b; 9 | 10 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/bugs_addsubz_0.v: -------------------------------------------------------------------------------- 1 | module TopModule ( 2 | input logic do_sub, 3 | input logic [7:0] a, 4 | input logic [7:0] b, 5 | output logic [7:0] out, 6 | output logic result_is_zero 7 | ); 8 | 9 | always @(*) begin 10 | case (do_sub) 11 | 0: out = a + b; 12 | 1: out = a - b; 13 | endcase 14 | 15 | result_is_zero = ~|out; // Use bitwise negation and reduction AND operation to check if 'out' is zero 16 | end 17 | 18 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/bugs_mux2_0.v: -------------------------------------------------------------------------------- 1 | module TopModule ( 2 | input logic sel, 3 | input logic [7:0] a, 4 | input logic [7:0] b, 5 | output logic [7:0] out 6 | ); 7 | 8 | // Implement the logic for the 'out' signal 9 | assign out = sel ? a : b; 10 | 11 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/circuit1_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | output logic q 6 | ); 7 | 8 | // Combinational logic for q 9 | assign q = a & b; 10 | 11 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/circuit3_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic c, 6 | input logic d, 7 | output logic q 8 | ); 9 | 10 | // Updated combinational logic for output 'q' 11 | assign q = (b & d) | (a & (c | d)) | (b & c); 12 | 13 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/circuit4_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic c, 6 | input logic d, 7 | output logic q 8 | ); 9 | 10 | // Combinational logic 11 | always @(*) begin 12 | q = b | c; 13 | end 14 | 15 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/circuit5_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [3:0] a, 4 | input logic [3:0] b, 5 | input logic [3:0] c, 6 | input logic [3:0] d, 7 | input logic [3:0] e, 8 | output logic [3:0] q 9 | ); 10 | 11 | // Combinational logic 12 | always @(*) begin 13 | if (c == 4'b0000) 14 | q = b; 15 | else if (c == 4'b0001) 16 | q = e; 17 | else if (c == 4'b0010) 18 | q = a; 19 | else if (c == 4'b0011) 20 | q = d; 21 | else 22 | q = 4'b1111; // Default value 'f' for all other values of 'c' 23 | end 24 | 25 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/circuit6_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [2:0] a, 4 | output logic [15:0] q 5 | ); 6 | 7 | // Combinational logic 8 | 9 | always @(*) begin 10 | case (a) 11 | 3'b000: q = 16'h1232; 12 | 3'b001: q = 16'haee0; 13 | 3'b010: q = 16'h27d4; 14 | 3'b011: q = 16'h5a0e; 15 | 3'b100: q = 16'h2066; 16 | 3'b101: q = 16'h64ce; 17 | 3'b110: q = 16'hc526; 18 | 3'b111: q = 16'h2f19; 19 | default: q = 16'h0000; // Default case to handle any unspecified values of 'a' 20 | endcase 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/circuit7_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic a, 5 | output logic q 6 | ); 7 | 8 | // State register 9 | logic q_reg; 10 | logic a_prev; 11 | 12 | always @(posedge clk) begin 13 | a_prev <= a; 14 | if (a && !a_prev) 15 | q_reg <= 0; 16 | else if (!a) 17 | q_reg <= 1'b1; 18 | else 19 | q_reg <= q_reg; 20 | end 21 | 22 | assign q = q_reg; 23 | 24 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/circuit8_0.v: -------------------------------------------------------------------------------- 1 | module TopModule( 2 | input logic clock, 3 | input logic a, 4 | output logic p, 5 | output logic q 6 | ); 7 | 8 | // Latch for output p that is transparent when 'clock' is high 9 | always @(*) begin 10 | if (clock) begin 11 | p = a; 12 | end 13 | end 14 | 15 | // Latch for output q 16 | always @(negedge clock) begin 17 | q <= p; 18 | end 19 | 20 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/circuit9_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic a, 5 | output logic [2:0] q 6 | ); 7 | 8 | // 3-bit register for output 'q' 9 | logic [2:0] q_reg; 10 | 11 | always @(posedge clk) begin 12 | if (a) 13 | q_reg <= 3'b100; // Set 'q' to 4 when 'a' is high during the first clock cycle 14 | else if (!a) begin 15 | if (q_reg == 3'b110) // When 'q' reaches 6 16 | q_reg <= 3'b000; // Reset 'q' to 0 17 | else 18 | q_reg <= q_reg + 1; // Increment 'q' by 1 when 'a' is low 19 | end 20 | end 21 | 22 | assign q = q_reg; 23 | 24 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/count10_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic reset, 5 | output logic [3:0] q 6 | ); 7 | 8 | // 4-bit register to hold the current state of the counter 9 | logic [3:0] reg_q; 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | reg_q <= 4'b0000; // Reset the counter to 0 when reset signal is high 14 | else if (reg_q == 4'b1001) 15 | reg_q <= 4'b0000; // Reset the counter to 0 when it reaches 9 16 | else 17 | reg_q <= reg_q + 1; // Increment the counter on the positive edge of the clock 18 | end 19 | 20 | assign q = reg_q; 21 | 22 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/count15_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic reset, 5 | output logic [3:0] q 6 | ); 7 | 8 | // 4-bit register for the counter 9 | logic [3:0] counter; 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | counter <= 4'b0000; // Reset the counter to 0 14 | else 15 | counter <= counter + 1; // Increment the counter 16 | end 17 | 18 | assign q = counter; // Output the counter value 19 | 20 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/count1to10_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic reset, 5 | output logic [3:0] q 6 | ); 7 | 8 | // 4-bit register to hold the current state of the counter 9 | logic [3:0] counter_reg; 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | counter_reg <= 4'b0001; // Initialize to represent the number 1 14 | else if (counter_reg == 4'b1010) 15 | counter_reg <= 4'b0001; // Wrap around to 1 when counter reaches 10 16 | else 17 | counter_reg <= counter_reg + 1; // Increment the counter by 1 18 | end 19 | 20 | assign q = counter_reg; 21 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/countslow_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic reset, 5 | input logic slowena, 6 | output logic [3:0] q 7 | ); 8 | 9 | // 4-bit register for the decade counter 10 | logic [3:0] counter; 11 | 12 | always @(posedge clk) begin 13 | if (reset) 14 | counter <= 4'b0000; // Reset counter to 0 15 | else if (slowena) begin 16 | if (counter == 4'b1001) // If counter is 9 17 | counter <= 4'b0000; // Wrap around to 0 18 | else 19 | counter <= counter + 1'b1; // Increment counter 20 | end 21 | end 22 | 23 | assign q = counter; 24 | 25 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/dff16e_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic resetn, 5 | input logic [1:0] byteena, 6 | input logic [15:0] d, 7 | output logic [15:0] q 8 | ); 9 | 10 | // Sequential logic 11 | 12 | always @( posedge clk ) begin 13 | if ( ~resetn ) 14 | q <= 16'b0; 15 | else begin 16 | if ( byteena[1] ) 17 | q[15:8] <= d[15:8]; 18 | if ( byteena[0] ) 19 | q[7:0] <= d[7:0]; 20 | end 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/dff8ar_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic areset, 5 | input logic [7:0] d, 6 | output logic [7:0] q 7 | ); 8 | 9 | // Sequential logic 10 | logic [7:0] q_reg; 11 | 12 | genvar i; 13 | generate 14 | for (i = 0; i < 8; i = i + 1) begin : dff 15 | always @( posedge clk or posedge areset ) begin 16 | if ( areset ) 17 | q_reg[i] <= 1'b0; 18 | else 19 | q_reg[i] <= d[i]; 20 | end 21 | end 22 | endgenerate 23 | 24 | assign q = q_reg; 25 | 26 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/dff8p_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic reset, 5 | input logic [7:0] d, 6 | output logic [7:0] q 7 | ); 8 | 9 | // Sequential logic 10 | 11 | always @( negedge clk ) begin 12 | if ( reset ) 13 | q <= 8'h34; 14 | else 15 | q <= d; 16 | end 17 | 18 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/dff_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic d, 5 | output logic q 6 | ); 7 | 8 | // Register to hold the state of the D flip-flop 9 | logic q_reg; 10 | 11 | always @(posedge clk) begin 12 | q_reg <= d; 13 | end 14 | 15 | assign q = q_reg; 16 | 17 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/dualedge_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic d, 5 | output logic q 6 | ); 7 | 8 | // Register to store the current state of the flip-flop 9 | logic q_reg; 10 | 11 | // Sequential logic to update the flip-flop's state on both edges of the clock 12 | always @(posedge clk or negedge clk) begin 13 | q_reg <= d; 14 | end 15 | 16 | // Output assignment 17 | assign q = q_reg; 18 | 19 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/ece241_2013_q7_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic j, 5 | input logic k, 6 | output logic Q 7 | ); 8 | 9 | // Register to hold the current state of the output Q 10 | logic Q_reg; 11 | 12 | // Sequential logic 13 | always @(posedge clk) begin 14 | if (j == 0 && k == 0) 15 | Q_reg <= Q_reg; // Q = Qold 16 | else if (j == 0 && k == 1) 17 | Q_reg <= 0; // Q = 0 18 | else if (j == 1 && k == 0) 19 | Q_reg <= 1; // Q = 1 20 | else if (j == 1 && k == 1) 21 | Q_reg <= ~Q_reg; // Q = ~Qold 22 | end 23 | 24 | // Structural connections 25 | assign Q = Q_reg; 26 | 27 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/ece241_2014_q1c_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [7:0] a, 4 | input logic [7:0] b, 5 | output logic [7:0] s, 6 | output logic overflow 7 | ); 8 | 9 | // Combinational logic for sum 10 | assign s = a + b; 11 | 12 | // Combinational logic for overflow 13 | assign overflow = ((a[7] == b[7]) && (s[7] != a[7])); 14 | 15 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/edgedetect2_0.v: -------------------------------------------------------------------------------- 1 | module TopModule ( 2 | input logic clk, 3 | input logic [7:0] in, 4 | output logic [7:0] anyedge 5 | ); 6 | logic [7:0] in_prev; 7 | logic [7:0] anyedge_prev; 8 | 9 | always_ff @(posedge clk) begin 10 | in_prev <= in; 11 | anyedge_prev <= in ^ in_prev; 12 | end 13 | 14 | always_comb begin 15 | anyedge = anyedge_prev; 16 | end 17 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/fadd_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic cin, 6 | output logic cout, 7 | output logic sum 8 | ); 9 | 10 | // Combinational logic for 'sum' output 11 | assign sum = a ^ b ^ cin; 12 | 13 | // Combinational logic for 'cout' output 14 | assign cout = (a & b) | (b & cin) | (a & cin); 15 | 16 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/gates100_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [99:0] in, 4 | output logic out_and, 5 | output logic out_or, 6 | output logic out_xor 7 | ); 8 | 9 | // Combinational logic for out_and 10 | assign out_and = ∈ 11 | 12 | // Combinational logic for out_or 13 | assign out_or = |in; 14 | 15 | // Combinational logic for out_xor 16 | assign out_xor = ^in; 17 | 18 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/gates4_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [3:0] in, 4 | output logic out_and, 5 | output logic out_or, 6 | output logic out_xor 7 | ); 8 | 9 | // Combinational logic for out_and 10 | assign out_and = in[0] & in[1] & in[2] & in[3]; 11 | 12 | // Combinational logic for out_or 13 | assign out_or = in[0] | in[1] | in[2] | in[3]; 14 | 15 | // Combinational logic for out_xor 16 | assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3]; 17 | 18 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/hadd_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | output logic sum, 6 | output logic cout 7 | ); 8 | 9 | // Combinational logic for sum 10 | assign sum = a ^ b; 11 | 12 | // Combinational logic for cout 13 | assign cout = a & b; 14 | 15 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/kmap1_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic c, 6 | output logic out 7 | ); 8 | 9 | // Combinational logic 10 | assign out = a | b | c; 11 | 12 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/kmap2_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic c, 6 | input logic d, 7 | output logic out 8 | ); 9 | 10 | assign out = (~a & ~b & ~c) | (~a & b & ~c & ~d) | (a & ~b & ~c) | (~a & ~b & c & ~d) | (b & c & d) | (~a & b & c & ~d) | (a & ~b & c & d); 11 | 12 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/kmap4_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic c, 6 | input logic d, 7 | output logic out 8 | ); 9 | 10 | always @(*) begin 11 | out = (a ^ b) ^ (c ^ d); 12 | end 13 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/lfsr5_0.v: -------------------------------------------------------------------------------- 1 | module TopModule ( 2 | input logic clk, 3 | input logic reset, 4 | output logic [4:0] q 5 | ); 6 | 7 | always @(posedge clk) begin 8 | if (reset) begin 9 | q <= 5'b00001; // Set LFSR output to 1 when reset is active-high 10 | end else begin 11 | q[4] <= q[0] ^ 1'b0; // Implement LFSR functionality for q[4] 12 | q[2] <= q[0] ^ q[3]; // Implement LFSR functionality for q[2] with tap at position 3 13 | q[3] <= q[4]; // Shift functionality for q[3] 14 | q[1] <= q[2]; // Shift functionality for q[1] 15 | q[0] <= q[1]; // Shift functionality for q[0] 16 | end 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q4a_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic d, 4 | input logic ena, 5 | output logic q 6 | ); 7 | 8 | always @(ena, d) begin 9 | if (ena) 10 | q <= d; 11 | end 12 | 13 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q4b_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic ar, 5 | input logic d, 6 | output logic q 7 | ); 8 | 9 | // D flip-flop with positive edge-triggered clock and asynchronous reset 10 | always @(posedge clk or posedge ar) begin 11 | if (ar) 12 | q <= 0; 13 | else 14 | q <= d; 15 | end 16 | 17 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q4c_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic d, 5 | input logic r, 6 | output logic q 7 | ); 8 | 9 | always @(posedge clk) begin 10 | if (r) begin 11 | q <= 0; 12 | end else begin 13 | q <= d; 14 | end 15 | end 16 | 17 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q4e_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic in1, 4 | input logic in2, 5 | output logic out 6 | ); 7 | 8 | // NOR gate logic 9 | assign out = ~(in1 | in2); 10 | 11 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q4f_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic in1, 4 | input logic in2, 5 | output logic out 6 | ); 7 | 8 | // Invert the input in2 to create a new signal 9 | logic in2_bubble; 10 | assign in2_bubble = ~in2; 11 | 12 | // Implement AND gate logic using in1 and in2_bubble 13 | assign out = in1 & in2_bubble; 14 | 15 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q4g_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic in1, 4 | input logic in2, 5 | input logic in3, 6 | output logic out 7 | ); 8 | 9 | // Combinational logic 10 | 11 | logic xnor_result; 12 | 13 | assign xnor_result = ~(in1 ^ in2); 14 | assign out = xnor_result ^ in3; 15 | 16 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q4h_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic in, 4 | output logic out 5 | ); 6 | 7 | assign out = in; 8 | 9 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q4i_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | output logic out 4 | ); 5 | 6 | assign out = 0; 7 | 8 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q4k_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic resetn, 5 | input logic in, 6 | output logic out 7 | ); 8 | 9 | // 4-bit shift register 10 | logic [3:0] shift_reg; 11 | 12 | always @(posedge clk) begin 13 | if (!resetn) 14 | shift_reg <= 4'b0000; 15 | else 16 | shift_reg <= {shift_reg[2:0], in}; 17 | end 18 | 19 | // Connect the output of the last D flip-flop to the output port 'out' 20 | assign out = shift_reg[3]; 21 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/m2014_q6c_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [5:0] y, 4 | input logic w, 5 | output logic Y1, 6 | output logic Y3 7 | ); 8 | 9 | // Logic for next-state signal Y1 10 | assign Y1 = y[0] & ~w; 11 | 12 | // Logic for next-state signal Y3 13 | assign Y3 = (y[1] & w) | (y[2] & w) | (y[4] & w) | (y[5] & w); 14 | 15 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/mt2015_eq2_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [1:0] A, 4 | input logic [1:0] B, 5 | output logic z 6 | ); 7 | 8 | assign z = (A == B) ? 1'b1 : 1'b0; 9 | 10 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/mt2015_muxdff_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic L, 5 | input logic q_in, 6 | input logic r_in, 7 | output logic Q 8 | ); 9 | 10 | // Flipflop 11 | logic q_reg; 12 | 13 | // Initialize q_reg 14 | initial begin 15 | q_reg = 0; 16 | end 17 | 18 | always @(posedge clk) begin 19 | if (L) 20 | q_reg <= r_in; 21 | else 22 | q_reg <= q_in; 23 | end 24 | 25 | assign Q = q_reg; 26 | 27 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/mt2015_q4a_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic x, 4 | input logic y, 5 | output logic z 6 | ); 7 | 8 | // Combinational logic 9 | 10 | logic xor_result; 11 | logic and_result; 12 | 13 | assign xor_result = x ^ y; 14 | assign and_result = xor_result & x; 15 | 16 | assign z = and_result; 17 | 18 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/mt2015_q4b_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic x, 4 | input logic y, 5 | output logic z 6 | ); 7 | 8 | // Combinational logic for z 9 | always @(*) begin 10 | if ((x == 1'b0) && (y == 1'b0)) 11 | z = 1'b1; 12 | else if ((x == 1'b1) && (y == 1'b1)) 13 | z = 1'b1; 14 | else 15 | z = 1'b0; 16 | end 17 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/mux256to1_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [255:0] in, 4 | input logic [7:0] sel, 5 | output logic out 6 | ); 7 | 8 | assign out = in[sel]; 9 | 10 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/mux256to1v_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [1023:0] in, 4 | input logic [7:0] sel, 5 | output logic [3:0] out 6 | ); 7 | 8 | // Wire to hold the selected bits 9 | logic [3:0] selected_bits; 10 | 11 | // Multiplexer logic 12 | always @(*) begin 13 | selected_bits = in[sel*4 +: 4]; 14 | end 15 | 16 | // Assign selected bits to output 17 | assign out = selected_bits; 18 | 19 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/mux2to1_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic sel, 6 | output logic out 7 | ); 8 | 9 | // Implement the logic for the output 'out' based on the selection signal 'sel' 10 | assign out = sel ? b : a; 11 | 12 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/mux2to1v_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [99:0] a, 4 | input logic [99:0] b, 5 | input logic sel, 6 | output logic [99:0] out 7 | ); 8 | 9 | // Combinational logic 10 | 11 | logic [99:0] out_mux; 12 | 13 | always @(*) begin 14 | out_mux = sel ? b : a; 15 | end 16 | 17 | // Structural connections 18 | 19 | assign out = out_mux; 20 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/norgate_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | output logic out 6 | ); 7 | 8 | // NOR gate logic 9 | assign out = ~(a | b); 10 | 11 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/notgate_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic in, 4 | output logic out 5 | ); 6 | 7 | assign out = ~in; 8 | 9 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/popcount255_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [254:0] in, 4 | output logic [7:0] out 5 | ); 6 | 7 | // Combinational logic 8 | 9 | always @(*) begin 10 | out = 0; 11 | for (int i = 0; i < 255; i = i + 1) begin 12 | out = out + in[i]; 13 | end 14 | end 15 | 16 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/reduction_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [7:0] in, 4 | output logic parity 5 | ); 6 | 7 | // Combinational logic for parity calculation 8 | assign parity = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[6] ^ in[7]; 9 | 10 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/review2015_count1k_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic clk, 4 | input logic reset, 5 | output logic [9:0] q 6 | ); 7 | 8 | // 10-bit register to hold the current count value 9 | logic [9:0] count_reg; 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | count_reg <= 10'b0; // reset the counter to 0 14 | else if (count_reg == 999) 15 | count_reg <= 10'b0; // wrap around to 0 if counter reaches 999 16 | else 17 | count_reg <= count_reg + 1; // increment the counter 18 | end 19 | 20 | assign q = count_reg; 21 | 22 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/ringer_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic ring, 4 | input logic vibrate_mode, 5 | output logic ringer, 6 | output logic motor 7 | ); 8 | 9 | // Combinational logic for ringer output 10 | always @(*) begin 11 | if (ring && !vibrate_mode) 12 | ringer = 1'b1; 13 | else 14 | ringer = 1'b0; 15 | end 16 | 17 | // Combinational logic for motor output 18 | always @(*) begin 19 | if (ring && vibrate_mode) 20 | motor = 1'b1; 21 | else 22 | motor = 1'b0; 23 | end 24 | 25 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/step_one_0.v: -------------------------------------------------------------------------------- 1 | module TopModule(output logic one); 2 | assign one = 1'b1; 3 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/truthtable1_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic x3, 4 | input logic x2, 5 | input logic x1, 6 | output logic f 7 | ); 8 | 9 | // Combinational logic for output f 10 | always @(*) begin 11 | if (!x3 && x2) 12 | f = 1'b1; 13 | else if (x3 && !x2 && x1) 14 | f = 1'b1; 15 | else if (x3 && !x2 && !x1) 16 | f = 1'b0; 17 | else if (x3 && x2 && !x1) 18 | f = 1'b0; 19 | else if (x3 && x2 && x1) 20 | f = 1'b1; 21 | else if (!x3 && !x2) // default case for x3=0, x2=0 22 | f = 1'b0; 23 | else 24 | f = 1'b0; // default case 25 | end 26 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/vector0_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [2:0] vec, 4 | output logic [2:0] outv, 5 | output logic o2, 6 | output logic o1, 7 | output logic o0 8 | ); 9 | 10 | // Assign the first bit of the input vector 'vec' to the output 'o0'. 11 | assign o0 = vec[0]; 12 | 13 | // Assign the second bit of the input vector 'vec' to the output 'o1'. 14 | assign o1 = vec[1]; 15 | 16 | // Assign the third bit of the input vector 'vec' to the output 'o2'. 17 | assign o2 = vec[2]; 18 | 19 | // Assign the entire 3-bit input vector 'vec' directly to the 3-bit output 'outv'. 20 | assign outv = vec; 21 | 22 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/vector100r_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [99:0] in, 4 | output logic [99:0] out 5 | ); 6 | 7 | genvar i; 8 | generate 9 | for (i = 0; i < 100; i=i+1) begin 10 | assign out[i] = in[99-i]; 11 | end 12 | endgenerate 13 | 14 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/vector1_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [15:0] in, 4 | output logic [7:0] out_hi, 5 | output logic [7:0] out_lo 6 | ); 7 | 8 | // Combinational logic to split the input into upper and lower bytes 9 | assign out_hi = in[15:8]; 10 | assign out_lo = in[7:0]; 11 | 12 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/vector2_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [31:0] in, 4 | output logic [31:0] out 5 | ); 6 | 7 | // Internal wire to hold the reversed byte order of the input 8 | logic [31:0] reversed_in; 9 | 10 | assign reversed_in[31:24] = in[7:0]; 11 | assign reversed_in[23:16] = in[15:8]; 12 | assign reversed_in[15:8] = in[23:16]; // Assign the third 8 bits of the input to the second 8 bits of the internal wire 13 | assign reversed_in[7:0] = in[31:24]; // Assign the last 8 bits of the input to the first 8 bits of the internal wire 14 | 15 | // Connect the internal wire to the output port 16 | assign out = reversed_in; 17 | 18 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/vector4_0.v: -------------------------------------------------------------------------------- 1 | module TopModule( 2 | input logic [7:0] in, 3 | output logic [31:0] out 4 | ); 5 | 6 | // Define a wire to extract the most significant bit (sign bit) from the 8-bit input. 7 | wire sign_bit; 8 | assign sign_bit = in[7]; 9 | 10 | // Replicate the sign bit 24 times to create a 24-bit wire. 11 | wire [23:0] replicated_sign_bits; 12 | assign replicated_sign_bits = {24{sign_bit}}; 13 | 14 | // Concatenate the 24-bit replicated sign bits with the original 8-bit input to form the 32-bit output. 15 | assign out = {replicated_sign_bits, in}; 16 | 17 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/vectorgates_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [2:0] a, 4 | input logic [2:0] b, 5 | output logic [2:0] out_or_bitwise, 6 | output logic out_or_logical, 7 | output logic [5:0] out_not 8 | ); 9 | 10 | // Bitwise OR operation 11 | assign out_or_bitwise = a | b; 12 | 13 | // Logical OR operation 14 | assign out_or_logical = |a | |b; 15 | 16 | // NOT operation on 'a' and assign to lower half of 'out_not' 17 | assign out_not[2:0] = ~a; 18 | 19 | // NOT operation on 'b' and assign to upper half of 'out_not' 20 | assign out_not[5:3] = ~b; 21 | 22 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/vectorr_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic [7:0] in, 4 | output logic [7:0] out 5 | ); 6 | 7 | // Output register 8 | logic [7:0] out_reg; 9 | 10 | always @(*) begin 11 | out_reg[7] = in[0]; 12 | out_reg[6] = in[1]; 13 | out_reg[5] = in[2]; 14 | out_reg[4] = in[3]; 15 | out_reg[3] = in[4]; 16 | out_reg[2] = in[5]; 17 | out_reg[1] = in[6]; 18 | out_reg[0] = in[7]; 19 | end 20 | 21 | // Structural connections 22 | assign out = out_reg; 23 | 24 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/wire4_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic c, 6 | output logic w, 7 | output logic x, 8 | output logic y, 9 | output logic z 10 | ); 11 | 12 | assign w = a; 13 | assign x = b; 14 | assign y = b; 15 | assign z = c; 16 | 17 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/wire_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic in, 4 | output logic out 5 | ); 6 | 7 | assign out = in; 8 | 9 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/wire_decl_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | input logic c, 6 | input logic d, 7 | output logic out, 8 | output logic out_n 9 | ); 10 | 11 | // Intermediate wires 12 | logic wire1; 13 | logic wire2; 14 | 15 | // AND gates 16 | assign wire1 = a & b; // Implement the first AND gate with inputs a and b, and connect the output to wire1. 17 | assign wire2 = c & d; // Implement the second AND gate with inputs c and d, and connect the output to wire2. 18 | 19 | // OR gate 20 | assign out = wire1 | wire2; 21 | 22 | // NOT gate 23 | assign out_n = ~out; 24 | 25 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/xnorgate_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | input logic a, 4 | input logic b, 5 | output logic out 6 | ); 7 | 8 | // Combinational logic for XNOR gate 9 | assign out = ~(a ^ b); 10 | 11 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plan_output/zero_0.v: -------------------------------------------------------------------------------- 1 | module TopModule 2 | ( 3 | output logic zero 4 | ); 5 | 6 | assign zero = 1'b0; 7 | 8 | endmodule -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plans/andgate_plan.json: -------------------------------------------------------------------------------- 1 | [{"id": "1", "content": "Define the module TopModule with input ports 'a' and 'b' and output port 'out'.\n\nRetrieved Related Information:\n- a: 1-bit input signal (Type:Signal)\n- b: 1-bit input signal (Type:Signal)\n- out: 1-bit output signal (Type:Signal)\n\n", "source": "input a\ninput b\noutput out", "parent_tasks": []}, {"id": "2", "content": "Implement the logic for the output 'out' as an AND operation of inputs 'a' and 'b'.\n\nRetrieved Related Information:\n- a: 1-bit input signal\n- b: 1-bit input signal\n- out: 1-bit output signal\n\n", "source": "The module should implement a 2-input AND gate.", "parent_tasks": ["1"]}] -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plans/m2014_q4i_plan.json: -------------------------------------------------------------------------------- 1 | [{"id": "1", "content": "Define the module TopModule with an output port named 'out'.\n\nRetrieved Related Information:\n- out: The module should always drive 0 (or logic low) (Type:Signal)\n\n", "source": "The module should always drive 0 (or logic low).", "parent_tasks": []}, {"id": "2", "content": "Assign a constant value of 0 to the output port 'out'.\n\nRetrieved Related Information:\n- out: The module should always drive 0 (or logic low) (Type:Signal)\n\n", "source": "The module should always drive 0 (or logic low).", "parent_tasks": ["1"]}] -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plans/norgate_plan.json: -------------------------------------------------------------------------------- 1 | [{"id": "1", "content": "Define the module TopModule with input ports 'a' and 'b', and output port 'out'.\n\nRetrieved Related Information:\n- a: input signal\n- b: input signal\n- out: output signal\n\n", "source": "input a\ninput b\noutput out", "parent_tasks": []}, {"id": "2", "content": "```\nImplement the NOR gate logic to compute the output 'out' based on the inputs 'a' and 'b'.\n\nRetrieved Related Information:\na: input signal (Type:Signal)\nb: input signal (Type:Signal)\nout: output signal (Type:Signal)\n```\n", "source": "The module should implement a NOR gate.", "parent_tasks": ["1"]}] -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plans/wire_plan.json: -------------------------------------------------------------------------------- 1 | [{"id": "1", "content": "Define the module TopModule with the specified input and output ports.\n\nRetrieved Related Information:\nout: 1-bit output signal (Type:Signal)\n\n", "source": "input in\noutput out", "parent_tasks": []}, {"id": "2", "content": "Implement the output 'out' as a direct connection from the input 'in'.\n\nRetrieved Related Information:\n- in: 1-bit input signal (Type:Signal)\n- out: 1-bit output signal (Type:Signal)\n\n", "source": "The module should behave like a wire.", "parent_tasks": ["1"]}] -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plans/xnorgate_plan.json: -------------------------------------------------------------------------------- 1 | [{"id": "1", "content": "Define the output signal 'out' as a wire in the module.\n\nRetrieved Related Information:\nout: 1-bit output signal (Type:Signal)\n\n", "source": "output out", "parent_tasks": []}, {"id": "2", "content": "Implement the logic for the XNOR gate using the inputs 'a' and 'b' to drive the output 'out'.\n\nRetrieved Related Information:\n- a: 1-bit input signal (Type:Signal)\n- b: 1-bit input signal (Type:Signal)\n- out: 1-bit output signal (Type:Signal)\n\n", "source": "The module should implement an XNOR gate.", "parent_tasks": ["1"]}] -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plans/zero_plan.json: -------------------------------------------------------------------------------- 1 | [{"id": "1", "content": "Define the module TopModule with an output port named 'zero'.\n\nRetrieved Related Information:\n- zero: The module should always outputs a LOW (Type:Signal)\n\n", "source": "The module should always outputs a LOW.", "parent_tasks": []}, {"id": "2", "content": "Assign a constant LOW value to the output port 'zero'.\n\nRetrieved Related Information:\n- zero: The module should always outputs a LOW (Type:Signal)\n\n", "source": "The module should always outputs a LOW.", "parent_tasks": ["1"]}] -------------------------------------------------------------------------------- /hardware_agent/examples/VerilogCoder/verilog-eval-v2/plans/zero_rough_plan.json: -------------------------------------------------------------------------------- 1 | [{"id": "1", "content": "Define the module TopModule with its input clock port and output port zero", "source": "The module should always outputs a LOW.", "parent_tasks": []}, {"id": "2", "content": "Implement the output signal zero, which should always be LOW, using a flip-flop triggered by the clock signal", "source": "The module should always outputs a LOW.", "parent_tasks": ["1"]}] --------------------------------------------------------------------------------