├── DEBUG
    ├── Agreement.c
    ├── Agreement.h
    ├── DAC.c
    ├── DAC.h
    ├── UART.c
    └── UART.h
├── EventRecorderStub.scvd
├── FOC_Control
    ├── Call_Functions.c
    ├── Call_Functions.h
    ├── INT_ISR.c
    ├── INT_ISR.h
    ├── Motor_Functions.h
    ├── PI_Control.c
    ├── PI_Control.h
    └── SVPWM.h
├── JLinkSettings.ini
├── KEILCLEAN.bat
├── Main
    └── main.c
├── MotorTest.zip
├── Objects
    └── PMSM_FOC.hex
├── PMSM_FOC.uvoptx
├── PMSM_FOC.uvprojx
├── README.md
├── RTE
    ├── Device
    │   ├── XMC4400-F100x512
    │   │   ├── RTE_Device.h
    │   │   ├── startup_XMC4400.s
    │   │   └── system_XMC4400.c
    │   └── XMC4400-F64x512
    │   │   ├── RTE_Device.h
    │   │   ├── startup_XMC4400.s
    │   │   └── system_XMC4400.c
    └── _Target_1
    │   └── RTE_Components.h
├── Readme
    └── README.txt
├── SYS_Init
    ├── MCU_Initialize.c
    ├── MCU_Initialize.h
    ├── VAR_Initialize.c
    └── VAR_Initialize.h
└── Sensorless_Lib
    ├── PMSM_FOC.lib
    └── SVPWM.lib


/DEBUG/Agreement.c:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/DEBUG/Agreement.c


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/DEBUG/Agreement.h:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/DEBUG/Agreement.h


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/DEBUG/DAC.c:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/DEBUG/DAC.c


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/DEBUG/DAC.h:
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 1 | #ifndef _DAC_H_
 2 | #define _DAC_H_
 3 | #include <XMC4400.h>
 4 | 
 5 | void DAC_Init(void);
 6 | void DAC_Output1(int16_t dat);
 7 | void DAC_Output0(int16_t dat);
 8 | void DAC_vInit(void);	
 9 | 
10 | #endif
11 | 


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/DEBUG/UART.c:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/DEBUG/UART.c


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/DEBUG/UART.h:
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 1 | #ifndef UART_H_
 2 | #define UART_H_
 3 | 
 4 | #include <XMC4400.h>
 5 | 
 6 | extern void UART_Init(void);
 7 | extern void UART_SendData(uint16_t uwData);
 8 | extern void UART_SendBuffer(const uint8_t *Buffer, uint16_t length);
 9 | 
10 | #endif
11 | 


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/EventRecorderStub.scvd:
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 1 | <?xml version="1.0" encoding="utf-8"?>
 2 | 
 3 | <component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
 4 | 
 5 | <component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
 6 |   <events>
 7 |   </events>
 8 | 
 9 | </component_viewer>
10 | 


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/FOC_Control/Call_Functions.c:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/FOC_Control/Call_Functions.c


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/FOC_Control/Call_Functions.h:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/FOC_Control/Call_Functions.h


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/FOC_Control/INT_ISR.c:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/FOC_Control/INT_ISR.c


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/FOC_Control/INT_ISR.h:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/FOC_Control/INT_ISR.h


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/FOC_Control/Motor_Functions.h:
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 1 | #ifndef _Motor_Functions_h
 2 | #define _Motor_Functions_h
 3 | 
 4 | #include <XMC4400.h>
 5 | 
 6 | extern const int16_t sintable16[3600];
 7 | 
 8 | extern void Re_Constuct_3_Phase_Current(void);
 9 | 
10 | extern void Iuvw_to_Idq(uint16_t anglee);
11 | 	
12 | extern void Udq_to_UarphaUbeta(uint16_t anglee);
13 | 
14 | extern void Thetae_Lock_CCU8(void);
15 | 	
16 | extern void Thetae_Inc_CCU8(void);    
17 | 
18 | extern void IF_Thetae_Delay(void);   
19 | 
20 | extern void ASMO(void);    
21 |  
22 | extern void SMO_Thetae_Delay(void);  
23 | 
24 | extern void SMOIF_Thetae_Delay(void);   
25 | 
26 | extern void Data_Record(void);
27 | 
28 | extern void IF_SMO_Switch(void);
29 | 
30 | #endif
31 | 


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/FOC_Control/PI_Control.c:
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 1 | #include "PI_Control.h"
 2 | #include "VAR_Initialize.h"
 3 | 
 4 | int32_t SMO_Output;
 5 | 
 6 | float P_output_pos = 0;
 7 | float I_output_pos = 0;
 8 | float I_Sum = 0;
 9 | float I_Max = 50000;
10 | float output = 0;
11 | 
12 | float P_Inc_Iq;
13 | float I_Inc_Iq;
14 | float Inc_Iq;
15 | float Output_Iq;
16 | 
17 | float P_Inc_Id;
18 | float I_Inc_Id;
19 | float Inc_Id;
20 | float Output_Id;
21 | 
22 | void PI_SMO_PLL(void)
23 | {
24 | 	float P_output_inc;
25 | 	float I_output_inc;
26 | 	
27 | 	PI_SMO.i32_e2 = PI_SMO.i32_e1;
28 | 	PI_SMO.i32_e1 = SMO.i32_PLL_Error; 
29 |     
30 | 	P_output_inc = PI_SMO.flo_kp*(PI_SMO.i32_e1-PI_SMO.i32_e2);
31 | 	I_output_inc = PI_SMO.flo_ki*PI_SMO.i32_e1;
32 | 	
33 | 	SMO_Output = P_output_inc + I_output_inc;
34 | 	
35 | 	SMO.i16_Thetae = (SMO.i16_Thetae + SMO_Output + 3600)%3600;  	
36 | }
37 | 
38 | void PI_Id_Loop(void)
39 | {
40 | 	PI_Id.i32_e2 = PI_Id.i32_e1;
41 | 	PI_Id.i32_e1 = Motor.cmd.i16_Id - Motor.info.i16_Id; 
42 |     
43 | 	P_Inc_Id = PI_Id.flo_kp*(PI_Id.i32_e1-PI_Id.i32_e2);
44 | 	I_Inc_Id = PI_Id.flo_ki*PI_Id.i32_e1;
45 | 	
46 | 	Inc_Id = P_Inc_Id + I_Inc_Id;
47 | 	
48 | 	Output_Id = Output_Id + Inc_Id;
49 | 
50 |     if(Output_Id >= PI_Id.i32_output_limit) 
51 | 	{Output_Id = PI_Id.i32_output_limit;}
52 |     else if(Output_Id <= -PI_Id.i32_output_limit)
53 | 	{
54 | 		Output_Id = -PI_Id.i32_output_limit;
55 | 	}
56 | 	
57 | 	Motor.info.i16_Ud = (int)Output_Id;
58 | }
59 | 
60 | void PI_Iq_Loop(void)
61 | {
62 | 	PI_Iq.i32_e2 = PI_Iq.i32_e1;
63 | 	PI_Iq.i32_e1 = Motor.cmd.i16_Iq - Motor.info.i16_Iq; 
64 |     
65 | 	P_Inc_Iq = PI_Iq.flo_kp*(PI_Iq.i32_e1-PI_Iq.i32_e2);
66 | 	I_Inc_Iq = PI_Iq.flo_ki*PI_Iq.i32_e1;
67 | 	
68 | 	Inc_Iq = P_Inc_Iq + I_Inc_Iq;
69 | 	
70 | 	Output_Iq = Output_Iq + Inc_Iq;
71 | 	
72 |     if(Output_Iq >= PI_Iq.i32_output_limit) Output_Iq = PI_Iq.i32_output_limit;
73 |     else if(Output_Iq <= -PI_Iq.i32_output_limit) Output_Iq = -PI_Iq.i32_output_limit;	
74 | 	
75 | 	Motor.info.i16_Uq = (int)Output_Iq;
76 | 
77 | }
78 | 
79 | void PI_Speed_Loop(void)
80 | {
81 | 	float output_inc;
82 | 	float P_output_inc;
83 | 	float I_output_inc;
84 | 	
85 | 	PI_Speed.i32_e2 = PI_Speed.i32_e1;
86 |     PI_Speed.i32_e1 = Motor.cmd.i16_Speed - SMO.i16_Speed_Est; 
87 | 	
88 | 	P_output_inc = PI_Speed.flo_kp*(PI_Speed.i32_e1-PI_Speed.i32_e2);
89 | 	I_output_inc = PI_Speed.flo_ki*PI_Speed.i32_e1;
90 | 	
91 | 	output_inc = P_output_inc + I_output_inc;
92 | 	output = output + output_inc;
93 | 	
94 |     if(output >= PI_Speed.i32_output_limit) output = PI_Speed.i32_output_limit;
95 |     else if(output <  -PI_Speed.i32_output_limit) output = -PI_Speed.i32_output_limit;
96 | 	
97 | 	Motor.cmd.i16_Iq = output;
98 | }
99 | 


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/FOC_Control/PI_Control.h:
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 1 | #ifndef _PI_Control_H_
 2 | #define _PI_Control_H_
 3 | #include <XMC4400.h>
 4 | 
 5 | extern void PI_Id_Loop(void);
 6 | extern void PI_Iq_Loop(void);
 7 | extern void PI_SMO_PLL(void);
 8 | extern void PI_Speed_Loop(void);
 9 | extern float I_Max;
10 | extern float I_Sum;
11 | extern float output;
12 | extern float P_Inc_Iq;
13 | extern float I_Inc_Iq;
14 | extern float Inc_Iq;
15 | extern float Output_Iq;
16 | 
17 | extern float P_Inc_Id;
18 | extern float I_Inc_Id;
19 | extern float Inc_Id;
20 | extern float Output_Id;
21 | extern int32_t SMO_Output;
22 | 
23 | #endif
24 | 
25 | 


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/FOC_Control/SVPWM.h:
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 1 | #ifndef _SVPWM_H_
 2 | #define _SVPWM_H_
 3 | 
 4 | #include <XMC4400.h>
 5 | 
 6 | typedef struct {
 7 |     int16_t PWM_Period;
 8 |     int16_t t1sat;
 9 |     int16_t t2sat;
10 |     int16_t t1;
11 |     int16_t t2;
12 |     int16_t	t_Sum;
13 |     int16_t taon;
14 |     int16_t tbon;
15 |     int16_t tcon;
16 |     int16_t Part;
17 |     int16_t Sector_Old;	
18 |     int16_t Sector;
19 |     int16_t	Sector_NUM;
20 |     int16_t X;
21 |     int16_t Y;
22 |     int16_t Z;
23 |     int16_t A;
24 |     int16_t B;
25 |     int16_t C;
26 |     int16_t Vref1;
27 |     int16_t Vref2;
28 |     int16_t Vref3;
29 |     int16_t PDC_U;
30 |     int16_t PDC_V;
31 |     int16_t PDC_W;
32 | } TSVPWM16_7;
33 | 
34 | 
35 | extern TSVPWM16_7 SVPWM16;
36 | 
37 | 
38 | void SVPWM16_7(int16_t V_alpha, int16_t V_beta);
39 | 
40 | #endif
41 | 


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/JLinkSettings.ini:
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 1 | [BREAKPOINTS]
 2 | ForceImpTypeAny = 0
 3 | ShowInfoWin = 1
 4 | EnableFlashBP = 2
 5 | BPDuringExecution = 0
 6 | [CFI]
 7 | CFISize = 0x00
 8 | CFIAddr = 0x00
 9 | [CPU]
10 | MonModeVTableAddr = 0xFFFFFFFF
11 | MonModeDebug = 0
12 | MaxNumAPs = 0
13 | LowPowerHandlingMode = 0
14 | OverrideMemMap = 0
15 | AllowSimulation = 1
16 | ScriptFile=""
17 | [FLASH]
18 | CacheExcludeSize = 0x00
19 | CacheExcludeAddr = 0x00
20 | MinNumBytesFlashDL = 0
21 | SkipProgOnCRCMatch = 1
22 | VerifyDownload = 1
23 | AllowCaching = 1
24 | EnableFlashDL = 2
25 | Override = 1
26 | Device="Cortex-M4"
27 | [GENERAL]
28 | WorkRAMSize = 0x00
29 | WorkRAMAddr = 0x00
30 | RAMUsageLimit = 0x00
31 | [SWO]
32 | SWOLogFile=""
33 | [MEM]
34 | RdOverrideOrMask = 0x00
35 | RdOverrideAndMask = 0xFFFFFFFF
36 | RdOverrideAddr = 0xFFFFFFFF
37 | WrOverrideOrMask = 0x00
38 | WrOverrideAndMask = 0xFFFFFFFF
39 | WrOverrideAddr = 0xFFFFFFFF
40 | 


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/KEILCLEAN.bat:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/KEILCLEAN.bat


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/Main/main.c:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/Main/main.c


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/MotorTest.zip:
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https://raw.githubusercontent.com/NYCParker/sensorless_foc/85254b37fcbc8c9620cbb7ce2c39b7ee86bdd74e/MotorTest.zip


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/PMSM_FOC.uvoptx:
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  1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
  2 | <ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
  3 | 
  4 |   <SchemaVersion>1.0</SchemaVersion>
  5 | 
  6 |   <Header>### uVision Project, (C) Keil Software</Header>
  7 | 
  8 |   <Extensions>
  9 |     <cExt>*.c</cExt>
 10 |     <aExt>*.s*; *.src; *.a*</aExt>
 11 |     <oExt>*.obj; *.o</oExt>
 12 |     <lExt>*.lib</lExt>
 13 |     <tExt>*.txt; *.h; *.inc</tExt>
 14 |     <pExt>*.plm</pExt>
 15 |     <CppX>*.cpp</CppX>
 16 |     <nMigrate>0</nMigrate>
 17 |   </Extensions>
 18 | 
 19 |   <DaveTm>
 20 |     <dwLowDateTime>0</dwLowDateTime>
 21 |     <dwHighDateTime>0</dwHighDateTime>
 22 |   </DaveTm>
 23 | 
 24 |   <Target>
 25 |     <TargetName>Target 1</TargetName>
 26 |     <ToolsetNumber>0x4</ToolsetNumber>
 27 |     <ToolsetName>ARM-ADS</ToolsetName>
 28 |     <TargetOption>
 29 |       <CLKADS>12000000</CLKADS>
 30 |       <OPTTT>
 31 |         <gFlags>1</gFlags>
 32 |         <BeepAtEnd>1</BeepAtEnd>
 33 |         <RunSim>0</RunSim>
 34 |         <RunTarget>1</RunTarget>
 35 |         <RunAbUc>0</RunAbUc>
 36 |       </OPTTT>
 37 |       <OPTHX>
 38 |         <HexSelection>1</HexSelection>
 39 |         <FlashByte>65535</FlashByte>
 40 |         <HexRangeLowAddress>0</HexRangeLowAddress>
 41 |         <HexRangeHighAddress>0</HexRangeHighAddress>
 42 |         <HexOffset>0</HexOffset>
 43 |       </OPTHX>
 44 |       <OPTLEX>
 45 |         <PageWidth>79</PageWidth>
 46 |         <PageLength>66</PageLength>
 47 |         <TabStop>8</TabStop>
 48 |         <ListingPath>.\Listings\</ListingPath>
 49 |       </OPTLEX>
 50 |       <ListingPage>
 51 |         <CreateCListing>1</CreateCListing>
 52 |         <CreateAListing>1</CreateAListing>
 53 |         <CreateLListing>1</CreateLListing>
 54 |         <CreateIListing>0</CreateIListing>
 55 |         <AsmCond>1</AsmCond>
 56 |         <AsmSymb>1</AsmSymb>
 57 |         <AsmXref>0</AsmXref>
 58 |         <CCond>1</CCond>
 59 |         <CCode>0</CCode>
 60 |         <CListInc>0</CListInc>
 61 |         <CSymb>0</CSymb>
 62 |         <LinkerCodeListing>0</LinkerCodeListing>
 63 |       </ListingPage>
 64 |       <OPTXL>
 65 |         <LMap>1</LMap>
 66 |         <LComments>1</LComments>
 67 |         <LGenerateSymbols>1</LGenerateSymbols>
 68 |         <LLibSym>1</LLibSym>
 69 |         <LLines>1</LLines>
 70 |         <LLocSym>1</LLocSym>
 71 |         <LPubSym>1</LPubSym>
 72 |         <LXref>0</LXref>
 73 |         <LExpSel>0</LExpSel>
 74 |       </OPTXL>
 75 |       <OPTFL>
 76 |         <tvExp>1</tvExp>
 77 |         <tvExpOptDlg>0</tvExpOptDlg>
 78 |         <IsCurrentTarget>1</IsCurrentTarget>
 79 |       </OPTFL>
 80 |       <CpuCode>255</CpuCode>
 81 |       <DebugOpt>
 82 |         <uSim>0</uSim>
 83 |         <uTrg>1</uTrg>
 84 |         <sLdApp>1</sLdApp>
 85 |         <sGomain>1</sGomain>
 86 |         <sRbreak>1</sRbreak>
 87 |         <sRwatch>1</sRwatch>
 88 |         <sRmem>1</sRmem>
 89 |         <sRfunc>1</sRfunc>
 90 |         <sRbox>1</sRbox>
 91 |         <tLdApp>1</tLdApp>
 92 |         <tGomain>1</tGomain>
 93 |         <tRbreak>1</tRbreak>
 94 |         <tRwatch>1</tRwatch>
 95 |         <tRmem>1</tRmem>
 96 |         <tRfunc>0</tRfunc>
 97 |         <tRbox>1</tRbox>
 98 |         <tRtrace>1</tRtrace>
 99 |         <sRSysVw>1</sRSysVw>
100 |         <tRSysVw>1</tRSysVw>
101 |         <sRunDeb>0</sRunDeb>
102 |         <sLrtime>0</sLrtime>
103 |         <bEvRecOn>1</bEvRecOn>
104 |         <bSchkAxf>0</bSchkAxf>
105 |         <bTchkAxf>0</bTchkAxf>
106 |         <nTsel>4</nTsel>
107 |         <sDll></sDll>
108 |         <sDllPa></sDllPa>
109 |         <sDlgDll></sDlgDll>
110 |         <sDlgPa></sDlgPa>
111 |         <sIfile></sIfile>
112 |         <tDll></tDll>
113 |         <tDllPa></tDllPa>
114 |         <tDlgDll></tDlgDll>
115 |         <tDlgPa></tDlgPa>
116 |         <tIfile></tIfile>
117 |         <pMon>Segger\JL2CM3.dll</pMon>
118 |       </DebugOpt>
119 |       <TargetDriverDllRegistry>
120 |         <SetRegEntry>
121 |           <Number>0</Number>
122 |           <Key>UL2CM3</Key>
123 |           <Name>UL2CM3(-S0 -C0 -P0 ) -FN2 -FC1000 -FD20000000 -FF0XMC4400_512 -FF1XMC4400c_512 -FL080000 -FL180000 -FS0C000000 -FS18000000 -FP0($$Device:XMC4400-F100x512$Flash\XMC4400_512.FLM) -FP1($$Device:XMC4400-F100x512$Flash\XMC4400c_512.FLM)</Name>
124 |         </SetRegEntry>
125 |         <SetRegEntry>
126 |           <Number>0</Number>
127 |           <Key>JL2CM3</Key>
128 |           <Name>-U591028154 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC120000000 -TP21 -TDS8077 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN2 -FF0XMC4400_512.FLM -FS0C000000 -FL080000 -FP0($$Device:XMC4400-F100x512$Flash\XMC4400_512.FLM) -FF1XMC4400c_512.FLM -FS18000000 -FL180000 -FP1($$Device:XMC4400-F100x512$Flash\XMC4400c_512.FLM)</Name>
129 |         </SetRegEntry>
130 |         <SetRegEntry>
131 |           <Number>0</Number>
132 |           <Key>DLGUARM</Key>
133 |           <Name></Name>
134 |         </SetRegEntry>
135 |         <SetRegEntry>
136 |           <Number>0</Number>
137 |           <Key>ARMRTXEVENTFLAGS</Key>
138 |           <Name>-L70 -Z18 -C0 -M0 -T1</Name>
139 |         </SetRegEntry>
140 |         <SetRegEntry>
141 |           <Number>0</Number>
142 |           <Key>DLGTARM</Key>
143 |           <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
144 |         </SetRegEntry>
145 |         <SetRegEntry>
146 |           <Number>0</Number>
147 |           <Key>ARMDBGFLAGS</Key>
148 |           <Name></Name>
149 |         </SetRegEntry>
150 |       </TargetDriverDllRegistry>
151 |       <Breakpoint/>
152 |       <WatchWindow1>
153 |         <Ww>
154 |           <count>0</count>
155 |           <WinNumber>1</WinNumber>
156 |           <ItemText>GlobalVar,0x0A</ItemText>
157 |         </Ww>
158 |         <Ww>
159 |           <count>1</count>
160 |           <WinNumber>1</WinNumber>
161 |           <ItemText>Motor,0x0A</ItemText>
162 |         </Ww>
163 |         <Ww>
164 |           <count>2</count>
165 |           <WinNumber>1</WinNumber>
166 |           <ItemText>PI_Id,0x0A</ItemText>
167 |         </Ww>
168 |         <Ww>
169 |           <count>3</count>
170 |           <WinNumber>1</WinNumber>
171 |           <ItemText>PI_Iq,0x0A</ItemText>
172 |         </Ww>
173 |         <Ww>
174 |           <count>4</count>
175 |           <WinNumber>1</WinNumber>
176 |           <ItemText>SVPWM16_7</ItemText>
177 |         </Ww>
178 |         <Ww>
179 |           <count>5</count>
180 |           <WinNumber>1</WinNumber>
181 |           <ItemText>SVPWM16,0x0A</ItemText>
182 |         </Ww>
183 |         <Ww>
184 |           <count>6</count>
185 |           <WinNumber>1</WinNumber>
186 |           <ItemText>GPIO_Init</ItemText>
187 |         </Ww>
188 |         <Ww>
189 |           <count>7</count>
190 |           <WinNumber>1</WinNumber>
191 |           <ItemText>speed_time</ItemText>
192 |         </Ww>
193 |         <Ww>
194 |           <count>8</count>
195 |           <WinNumber>1</WinNumber>
196 |           <ItemText>((CCU4_CC4_TypeDef *) 0x4000C400UL)-&gt;CV[0]&amp;0x0000FFFF,0x0A</ItemText>
197 |         </Ww>
198 |         <Ww>
199 |           <count>9</count>
200 |           <WinNumber>1</WinNumber>
201 |           <ItemText>Uart_Send_Flag</ItemText>
202 |         </Ww>
203 |         <Ww>
204 |           <count>10</count>
205 |           <WinNumber>1</WinNumber>
206 |           <ItemText>uart_state_flag</ItemText>
207 |         </Ww>
208 |         <Ww>
209 |           <count>11</count>
210 |           <WinNumber>1</WinNumber>
211 |           <ItemText>d_sum,0x0A</ItemText>
212 |         </Ww>
213 |         <Ww>
214 |           <count>12</count>
215 |           <WinNumber>1</WinNumber>
216 |           <ItemText>d_count,0x0A</ItemText>
217 |         </Ww>
218 |         <Ww>
219 |           <count>13</count>
220 |           <WinNumber>1</WinNumber>
221 |           <ItemText>__disable_irq</ItemText>
222 |         </Ww>
223 |         <Ww>
224 |           <count>14</count>
225 |           <WinNumber>1</WinNumber>
226 |           <ItemText>CCU80_Init</ItemText>
227 |         </Ww>
228 |         <Ww>
229 |           <count>15</count>
230 |           <WinNumber>1</WinNumber>
231 |           <ItemText>SMO,0x0A</ItemText>
232 |         </Ww>
233 |         <Ww>
234 |           <count>16</count>
235 |           <WinNumber>1</WinNumber>
236 |           <ItemText>Cur_Calibration_Iu_sum,0x0A</ItemText>
237 |         </Ww>
238 |         <Ww>
239 |           <count>17</count>
240 |           <WinNumber>1</WinNumber>
241 |           <ItemText>Cur_Calibration_Iv_sum,0x0A</ItemText>
242 |         </Ww>
243 |         <Ww>
244 |           <count>18</count>
245 |           <WinNumber>1</WinNumber>
246 |           <ItemText>Cur_Calibration_Iw_sum,0x0A</ItemText>
247 |         </Ww>
248 |         <Ww>
249 |           <count>19</count>
250 |           <WinNumber>1</WinNumber>
251 |           <ItemText>PI_Speed.flo_kp,0x0A</ItemText>
252 |         </Ww>
253 |         <Ww>
254 |           <count>20</count>
255 |           <WinNumber>1</WinNumber>
256 |           <ItemText>PI_Speed.flo_ki,0x0A</ItemText>
257 |         </Ww>
258 |         <Ww>
259 |           <count>21</count>
260 |           <WinNumber>1</WinNumber>
261 |           <ItemText>I_Sum,0x0A</ItemText>
262 |         </Ww>
263 |         <Ww>
264 |           <count>22</count>
265 |           <WinNumber>1</WinNumber>
266 |           <ItemText>PI_Speed,0x0A</ItemText>
267 |         </Ww>
268 |         <Ww>
269 |           <count>23</count>
270 |           <WinNumber>1</WinNumber>
271 |           <ItemText>P_output_pos,0x10</ItemText>
272 |         </Ww>
273 |         <Ww>
274 |           <count>24</count>
275 |           <WinNumber>1</WinNumber>
276 |           <ItemText>I_output_pos,0x10</ItemText>
277 |         </Ww>
278 |         <Ww>
279 |           <count>25</count>
280 |           <WinNumber>1</WinNumber>
281 |           <ItemText>I_Max,0x10</ItemText>
282 |         </Ww>
283 |         <Ww>
284 |           <count>26</count>
285 |           <WinNumber>1</WinNumber>
286 |           <ItemText>Motor.cmd.i16_Iq,0x0A</ItemText>
287 |         </Ww>
288 |         <Ww>
289 |           <count>27</count>
290 |           <WinNumber>1</WinNumber>
291 |           <ItemText>output</ItemText>
292 |         </Ww>
293 |         <Ww>
294 |           <count>28</count>
295 |           <WinNumber>1</WinNumber>
296 |           <ItemText>GPIO_Init</ItemText>
297 |         </Ww>
298 |         <Ww>
299 |           <count>29</count>
300 |           <WinNumber>1</WinNumber>
301 |           <ItemText>PI_SMO,0x0A</ItemText>
302 |         </Ww>
303 |       </WatchWindow1>
304 |       <Tracepoint>
305 |         <THDelay>0</THDelay>
306 |       </Tracepoint>
307 |       <DebugFlag>
308 |         <trace>0</trace>
309 |         <periodic>1</periodic>
310 |         <aLwin>1</aLwin>
311 |         <aCover>0</aCover>
312 |         <aSer1>0</aSer1>
313 |         <aSer2>0</aSer2>
314 |         <aPa>0</aPa>
315 |         <viewmode>1</viewmode>
316 |         <vrSel>0</vrSel>
317 |         <aSym>0</aSym>
318 |         <aTbox>0</aTbox>
319 |         <AscS1>0</AscS1>
320 |         <AscS2>0</AscS2>
321 |         <AscS3>0</AscS3>
322 |         <aSer3>0</aSer3>
323 |         <eProf>0</eProf>
324 |         <aLa>0</aLa>
325 |         <aPa1>0</aPa1>
326 |         <AscS4>0</AscS4>
327 |         <aSer4>0</aSer4>
328 |         <StkLoc>1</StkLoc>
329 |         <TrcWin>0</TrcWin>
330 |         <newCpu>0</newCpu>
331 |         <uProt>0</uProt>
332 |       </DebugFlag>
333 |       <LintExecutable></LintExecutable>
334 |       <LintConfigFile></LintConfigFile>
335 |       <bLintAuto>0</bLintAuto>
336 |       <bAutoGenD>0</bAutoGenD>
337 |       <LntExFlags>0</LntExFlags>
338 |       <pMisraName></pMisraName>
339 |       <pszMrule></pszMrule>
340 |       <pSingCmds></pSingCmds>
341 |       <pMultCmds></pMultCmds>
342 |       <pMisraNamep></pMisraNamep>
343 |       <pszMrulep></pszMrulep>
344 |       <pSingCmdsp></pSingCmdsp>
345 |       <pMultCmdsp></pMultCmdsp>
346 |     </TargetOption>
347 |   </Target>
348 | 
349 |   <Group>
350 |     <GroupName>MAIN</GroupName>
351 |     <tvExp>1</tvExp>
352 |     <tvExpOptDlg>0</tvExpOptDlg>
353 |     <cbSel>0</cbSel>
354 |     <RteFlg>0</RteFlg>
355 |     <File>
356 |       <GroupNumber>1</GroupNumber>
357 |       <FileNumber>1</FileNumber>
358 |       <FileType>1</FileType>
359 |       <tvExp>0</tvExp>
360 |       <tvExpOptDlg>0</tvExpOptDlg>
361 |       <bDave2>0</bDave2>
362 |       <PathWithFileName>.\Main\main.c</PathWithFileName>
363 |       <FilenameWithoutPath>main.c</FilenameWithoutPath>
364 |       <RteFlg>0</RteFlg>
365 |       <bShared>0</bShared>
366 |     </File>
367 |   </Group>
368 | 
369 |   <Group>
370 |     <GroupName>SYS_Init</GroupName>
371 |     <tvExp>1</tvExp>
372 |     <tvExpOptDlg>0</tvExpOptDlg>
373 |     <cbSel>0</cbSel>
374 |     <RteFlg>0</RteFlg>
375 |     <File>
376 |       <GroupNumber>2</GroupNumber>
377 |       <FileNumber>2</FileNumber>
378 |       <FileType>1</FileType>
379 |       <tvExp>0</tvExp>
380 |       <tvExpOptDlg>0</tvExpOptDlg>
381 |       <bDave2>0</bDave2>
382 |       <PathWithFileName>.\SYS_Init\MCU_Initialize.c</PathWithFileName>
383 |       <FilenameWithoutPath>MCU_Initialize.c</FilenameWithoutPath>
384 |       <RteFlg>0</RteFlg>
385 |       <bShared>0</bShared>
386 |     </File>
387 |     <File>
388 |       <GroupNumber>2</GroupNumber>
389 |       <FileNumber>3</FileNumber>
390 |       <FileType>1</FileType>
391 |       <tvExp>0</tvExp>
392 |       <tvExpOptDlg>0</tvExpOptDlg>
393 |       <bDave2>0</bDave2>
394 |       <PathWithFileName>.\SYS_Init\VAR_Initialize.c</PathWithFileName>
395 |       <FilenameWithoutPath>VAR_Initialize.c</FilenameWithoutPath>
396 |       <RteFlg>0</RteFlg>
397 |       <bShared>0</bShared>
398 |     </File>
399 |   </Group>
400 | 
401 |   <Group>
402 |     <GroupName>FOC_Control</GroupName>
403 |     <tvExp>1</tvExp>
404 |     <tvExpOptDlg>0</tvExpOptDlg>
405 |     <cbSel>0</cbSel>
406 |     <RteFlg>0</RteFlg>
407 |     <File>
408 |       <GroupNumber>3</GroupNumber>
409 |       <FileNumber>4</FileNumber>
410 |       <FileType>1</FileType>
411 |       <tvExp>0</tvExp>
412 |       <tvExpOptDlg>0</tvExpOptDlg>
413 |       <bDave2>0</bDave2>
414 |       <PathWithFileName>.\FOC_Control\Call_Functions.c</PathWithFileName>
415 |       <FilenameWithoutPath>Call_Functions.c</FilenameWithoutPath>
416 |       <RteFlg>0</RteFlg>
417 |       <bShared>0</bShared>
418 |     </File>
419 |     <File>
420 |       <GroupNumber>3</GroupNumber>
421 |       <FileNumber>5</FileNumber>
422 |       <FileType>1</FileType>
423 |       <tvExp>0</tvExp>
424 |       <tvExpOptDlg>0</tvExpOptDlg>
425 |       <bDave2>0</bDave2>
426 |       <PathWithFileName>.\FOC_Control\INT_ISR.c</PathWithFileName>
427 |       <FilenameWithoutPath>INT_ISR.c</FilenameWithoutPath>
428 |       <RteFlg>0</RteFlg>
429 |       <bShared>0</bShared>
430 |     </File>
431 |     <File>
432 |       <GroupNumber>3</GroupNumber>
433 |       <FileNumber>6</FileNumber>
434 |       <FileType>1</FileType>
435 |       <tvExp>0</tvExp>
436 |       <tvExpOptDlg>0</tvExpOptDlg>
437 |       <bDave2>0</bDave2>
438 |       <PathWithFileName>.\FOC_Control\PI_Control.c</PathWithFileName>
439 |       <FilenameWithoutPath>PI_Control.c</FilenameWithoutPath>
440 |       <RteFlg>0</RteFlg>
441 |       <bShared>0</bShared>
442 |     </File>
443 |     <File>
444 |       <GroupNumber>3</GroupNumber>
445 |       <FileNumber>7</FileNumber>
446 |       <FileType>5</FileType>
447 |       <tvExp>0</tvExp>
448 |       <tvExpOptDlg>0</tvExpOptDlg>
449 |       <bDave2>0</bDave2>
450 |       <PathWithFileName>.\FOC_Control\Motor_Functions.h</PathWithFileName>
451 |       <FilenameWithoutPath>Motor_Functions.h</FilenameWithoutPath>
452 |       <RteFlg>0</RteFlg>
453 |       <bShared>0</bShared>
454 |     </File>
455 |     <File>
456 |       <GroupNumber>3</GroupNumber>
457 |       <FileNumber>8</FileNumber>
458 |       <FileType>5</FileType>
459 |       <tvExp>0</tvExp>
460 |       <tvExpOptDlg>0</tvExpOptDlg>
461 |       <bDave2>0</bDave2>
462 |       <PathWithFileName>.\FOC_Control\SVPWM.h</PathWithFileName>
463 |       <FilenameWithoutPath>SVPWM.h</FilenameWithoutPath>
464 |       <RteFlg>0</RteFlg>
465 |       <bShared>0</bShared>
466 |     </File>
467 |     <File>
468 |       <GroupNumber>3</GroupNumber>
469 |       <FileNumber>9</FileNumber>
470 |       <FileType>4</FileType>
471 |       <tvExp>0</tvExp>
472 |       <tvExpOptDlg>0</tvExpOptDlg>
473 |       <bDave2>0</bDave2>
474 |       <PathWithFileName>.\Sensorless_Lib\PMSM_FOC.lib</PathWithFileName>
475 |       <FilenameWithoutPath>PMSM_FOC.lib</FilenameWithoutPath>
476 |       <RteFlg>0</RteFlg>
477 |       <bShared>0</bShared>
478 |     </File>
479 |     <File>
480 |       <GroupNumber>3</GroupNumber>
481 |       <FileNumber>10</FileNumber>
482 |       <FileType>4</FileType>
483 |       <tvExp>0</tvExp>
484 |       <tvExpOptDlg>0</tvExpOptDlg>
485 |       <bDave2>0</bDave2>
486 |       <PathWithFileName>$TC_ROOT$\..\..\study\XHY\Github\GITHUB\Sensorless_FOC\Sensorless_Lib\SVPWM.lib</PathWithFileName>
487 |       <FilenameWithoutPath>..\..\study\XHY\Github\GITHUB\Sensorless_FOC\Sensorless_Lib\SVPWM.lib</FilenameWithoutPath>
488 |       <RteFlg>0</RteFlg>
489 |       <bShared>0</bShared>
490 |     </File>
491 |   </Group>
492 | 
493 |   <Group>
494 |     <GroupName>DEBUG</GroupName>
495 |     <tvExp>1</tvExp>
496 |     <tvExpOptDlg>0</tvExpOptDlg>
497 |     <cbSel>0</cbSel>
498 |     <RteFlg>0</RteFlg>
499 |     <File>
500 |       <GroupNumber>4</GroupNumber>
501 |       <FileNumber>11</FileNumber>
502 |       <FileType>1</FileType>
503 |       <tvExp>0</tvExp>
504 |       <tvExpOptDlg>0</tvExpOptDlg>
505 |       <bDave2>0</bDave2>
506 |       <PathWithFileName>.\DEBUG\Agreement.c</PathWithFileName>
507 |       <FilenameWithoutPath>Agreement.c</FilenameWithoutPath>
508 |       <RteFlg>0</RteFlg>
509 |       <bShared>0</bShared>
510 |     </File>
511 |     <File>
512 |       <GroupNumber>4</GroupNumber>
513 |       <FileNumber>12</FileNumber>
514 |       <FileType>1</FileType>
515 |       <tvExp>0</tvExp>
516 |       <tvExpOptDlg>0</tvExpOptDlg>
517 |       <bDave2>0</bDave2>
518 |       <PathWithFileName>.\DEBUG\DAC.c</PathWithFileName>
519 |       <FilenameWithoutPath>DAC.c</FilenameWithoutPath>
520 |       <RteFlg>0</RteFlg>
521 |       <bShared>0</bShared>
522 |     </File>
523 |     <File>
524 |       <GroupNumber>4</GroupNumber>
525 |       <FileNumber>13</FileNumber>
526 |       <FileType>1</FileType>
527 |       <tvExp>0</tvExp>
528 |       <tvExpOptDlg>0</tvExpOptDlg>
529 |       <bDave2>0</bDave2>
530 |       <PathWithFileName>.\DEBUG\UART.c</PathWithFileName>
531 |       <FilenameWithoutPath>UART.c</FilenameWithoutPath>
532 |       <RteFlg>0</RteFlg>
533 |       <bShared>0</bShared>
534 |     </File>
535 |   </Group>
536 | 
537 |   <Group>
538 |     <GroupName>Readme</GroupName>
539 |     <tvExp>1</tvExp>
540 |     <tvExpOptDlg>0</tvExpOptDlg>
541 |     <cbSel>0</cbSel>
542 |     <RteFlg>0</RteFlg>
543 |     <File>
544 |       <GroupNumber>5</GroupNumber>
545 |       <FileNumber>14</FileNumber>
546 |       <FileType>5</FileType>
547 |       <tvExp>0</tvExp>
548 |       <tvExpOptDlg>0</tvExpOptDlg>
549 |       <bDave2>0</bDave2>
550 |       <PathWithFileName>.\Readme\README.txt</PathWithFileName>
551 |       <FilenameWithoutPath>README.txt</FilenameWithoutPath>
552 |       <RteFlg>0</RteFlg>
553 |       <bShared>0</bShared>
554 |     </File>
555 |   </Group>
556 | 
557 |   <Group>
558 |     <GroupName>::CMSIS</GroupName>
559 |     <tvExp>0</tvExp>
560 |     <tvExpOptDlg>0</tvExpOptDlg>
561 |     <cbSel>0</cbSel>
562 |     <RteFlg>1</RteFlg>
563 |   </Group>
564 | 
565 |   <Group>
566 |     <GroupName>::Device</GroupName>
567 |     <tvExp>0</tvExp>
568 |     <tvExpOptDlg>0</tvExpOptDlg>
569 |     <cbSel>0</cbSel>
570 |     <RteFlg>1</RteFlg>
571 |   </Group>
572 | 
573 | </ProjectOpt>
574 | 


--------------------------------------------------------------------------------
/PMSM_FOC.uvprojx:
--------------------------------------------------------------------------------
  1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
  2 | <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
  3 | 
  4 |   <SchemaVersion>2.1</SchemaVersion>
  5 | 
  6 |   <Header>### uVision Project, (C) Keil Software</Header>
  7 | 
  8 |   <Targets>
  9 |     <Target>
 10 |       <TargetName>Target 1</TargetName>
 11 |       <ToolsetNumber>0x4</ToolsetNumber>
 12 |       <ToolsetName>ARM-ADS</ToolsetName>
 13 |       <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
 14 |       <uAC6>0</uAC6>
 15 |       <TargetOption>
 16 |         <TargetCommonOption>
 17 |           <Device>XMC4400-F100x512</Device>
 18 |           <Vendor>Infineon</Vendor>
 19 |           <PackID>Infineon.XMC4000_DFP.2.11.0</PackID>
 20 |           <PackURL>http://dave.infineon.com/Libraries/CMSIS_PACK/</PackURL>
 21 |           <Cpu>IRAM(0x20000000,0xFFC0) IRAM2(0x1FFFC000,0x4000) IROM(0x08000000,0x80000) IROM2(0x0C000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
 22 |           <FlashUtilSpec></FlashUtilSpec>
 23 |           <StartupFile></StartupFile>
 24 |           <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0XMC4400_512 -FS0C000000 -FL080000 -FF1XMC4400c_512 -FS18000000 -FL180000 -FP0($$Device:XMC4400-F100x512$Flash\XMC4400_512.FLM) -FP1($$Device:XMC4400-F100x512$Flash\XMC4400c_512.FLM))</FlashDriverDll>
 25 |           <DeviceId>0</DeviceId>
 26 |           <RegisterFile>$$Device:XMC4400-F100x512$Device\XMC4400_series\Include\XMC4400.h</RegisterFile>
 27 |           <MemoryEnv></MemoryEnv>
 28 |           <Cmp></Cmp>
 29 |           <Asm></Asm>
 30 |           <Linker></Linker>
 31 |           <OHString></OHString>
 32 |           <InfinionOptionDll></InfinionOptionDll>
 33 |           <SLE66CMisc></SLE66CMisc>
 34 |           <SLE66AMisc></SLE66AMisc>
 35 |           <SLE66LinkerMisc></SLE66LinkerMisc>
 36 |           <SFDFile>$$Device:XMC4400-F100x512$SVD\XMC4400.svd</SFDFile>
 37 |           <bCustSvd>0</bCustSvd>
 38 |           <UseEnv>0</UseEnv>
 39 |           <BinPath></BinPath>
 40 |           <IncludePath></IncludePath>
 41 |           <LibPath></LibPath>
 42 |           <RegisterFilePath></RegisterFilePath>
 43 |           <DBRegisterFilePath></DBRegisterFilePath>
 44 |           <TargetStatus>
 45 |             <Error>0</Error>
 46 |             <ExitCodeStop>0</ExitCodeStop>
 47 |             <ButtonStop>0</ButtonStop>
 48 |             <NotGenerated>0</NotGenerated>
 49 |             <InvalidFlash>1</InvalidFlash>
 50 |           </TargetStatus>
 51 |           <OutputDirectory>.\Objects\</OutputDirectory>
 52 |           <OutputName>PMSM_FOC</OutputName>
 53 |           <CreateExecutable>1</CreateExecutable>
 54 |           <CreateLib>0</CreateLib>
 55 |           <CreateHexFile>1</CreateHexFile>
 56 |           <DebugInformation>1</DebugInformation>
 57 |           <BrowseInformation>1</BrowseInformation>
 58 |           <ListingPath>.\Listings\</ListingPath>
 59 |           <HexFormatSelection>1</HexFormatSelection>
 60 |           <Merge32K>0</Merge32K>
 61 |           <CreateBatchFile>0</CreateBatchFile>
 62 |           <BeforeCompile>
 63 |             <RunUserProg1>0</RunUserProg1>
 64 |             <RunUserProg2>0</RunUserProg2>
 65 |             <UserProg1Name></UserProg1Name>
 66 |             <UserProg2Name></UserProg2Name>
 67 |             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
 68 |             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
 69 |             <nStopU1X>0</nStopU1X>
 70 |             <nStopU2X>0</nStopU2X>
 71 |           </BeforeCompile>
 72 |           <BeforeMake>
 73 |             <RunUserProg1>0</RunUserProg1>
 74 |             <RunUserProg2>0</RunUserProg2>
 75 |             <UserProg1Name></UserProg1Name>
 76 |             <UserProg2Name></UserProg2Name>
 77 |             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
 78 |             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
 79 |             <nStopB1X>0</nStopB1X>
 80 |             <nStopB2X>0</nStopB2X>
 81 |           </BeforeMake>
 82 |           <AfterMake>
 83 |             <RunUserProg1>0</RunUserProg1>
 84 |             <RunUserProg2>0</RunUserProg2>
 85 |             <UserProg1Name></UserProg1Name>
 86 |             <UserProg2Name></UserProg2Name>
 87 |             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
 88 |             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
 89 |             <nStopA1X>0</nStopA1X>
 90 |             <nStopA2X>0</nStopA2X>
 91 |           </AfterMake>
 92 |           <SelectedForBatchBuild>0</SelectedForBatchBuild>
 93 |           <SVCSIdString></SVCSIdString>
 94 |         </TargetCommonOption>
 95 |         <CommonProperty>
 96 |           <UseCPPCompiler>0</UseCPPCompiler>
 97 |           <RVCTCodeConst>0</RVCTCodeConst>
 98 |           <RVCTZI>0</RVCTZI>
 99 |           <RVCTOtherData>0</RVCTOtherData>
100 |           <ModuleSelection>0</ModuleSelection>
101 |           <IncludeInBuild>1</IncludeInBuild>
102 |           <AlwaysBuild>0</AlwaysBuild>
103 |           <GenerateAssemblyFile>0</GenerateAssemblyFile>
104 |           <AssembleAssemblyFile>0</AssembleAssemblyFile>
105 |           <PublicsOnly>0</PublicsOnly>
106 |           <StopOnExitCode>3</StopOnExitCode>
107 |           <CustomArgument></CustomArgument>
108 |           <IncludeLibraryModules></IncludeLibraryModules>
109 |           <ComprImg>1</ComprImg>
110 |         </CommonProperty>
111 |         <DllOption>
112 |           <SimDllName>SARMCM3.DLL</SimDllName>
113 |           <SimDllArguments> -REMAP -MPU</SimDllArguments>
114 |           <SimDlgDll>DCM.DLL</SimDlgDll>
115 |           <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
116 |           <TargetDllName>SARMCM3.DLL</TargetDllName>
117 |           <TargetDllArguments> -MPU</TargetDllArguments>
118 |           <TargetDlgDll>TCM.DLL</TargetDlgDll>
119 |           <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
120 |         </DllOption>
121 |         <DebugOption>
122 |           <OPTHX>
123 |             <HexSelection>1</HexSelection>
124 |             <HexRangeLowAddress>0</HexRangeLowAddress>
125 |             <HexRangeHighAddress>0</HexRangeHighAddress>
126 |             <HexOffset>0</HexOffset>
127 |             <Oh166RecLen>16</Oh166RecLen>
128 |           </OPTHX>
129 |         </DebugOption>
130 |         <Utilities>
131 |           <Flash1>
132 |             <UseTargetDll>1</UseTargetDll>
133 |             <UseExternalTool>0</UseExternalTool>
134 |             <RunIndependent>0</RunIndependent>
135 |             <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
136 |             <Capability>1</Capability>
137 |             <DriverSelection>4096</DriverSelection>
138 |           </Flash1>
139 |           <bUseTDR>1</bUseTDR>
140 |           <Flash2>BIN\UL2CM3.DLL</Flash2>
141 |           <Flash3>"" ()</Flash3>
142 |           <Flash4></Flash4>
143 |           <pFcarmOut></pFcarmOut>
144 |           <pFcarmGrp></pFcarmGrp>
145 |           <pFcArmRoot></pFcArmRoot>
146 |           <FcArmLst>0</FcArmLst>
147 |         </Utilities>
148 |         <TargetArmAds>
149 |           <ArmAdsMisc>
150 |             <GenerateListings>0</GenerateListings>
151 |             <asHll>1</asHll>
152 |             <asAsm>1</asAsm>
153 |             <asMacX>1</asMacX>
154 |             <asSyms>1</asSyms>
155 |             <asFals>1</asFals>
156 |             <asDbgD>1</asDbgD>
157 |             <asForm>1</asForm>
158 |             <ldLst>0</ldLst>
159 |             <ldmm>1</ldmm>
160 |             <ldXref>1</ldXref>
161 |             <BigEnd>0</BigEnd>
162 |             <AdsALst>1</AdsALst>
163 |             <AdsACrf>1</AdsACrf>
164 |             <AdsANop>0</AdsANop>
165 |             <AdsANot>0</AdsANot>
166 |             <AdsLLst>1</AdsLLst>
167 |             <AdsLmap>1</AdsLmap>
168 |             <AdsLcgr>1</AdsLcgr>
169 |             <AdsLsym>1</AdsLsym>
170 |             <AdsLszi>1</AdsLszi>
171 |             <AdsLtoi>1</AdsLtoi>
172 |             <AdsLsun>1</AdsLsun>
173 |             <AdsLven>1</AdsLven>
174 |             <AdsLsxf>1</AdsLsxf>
175 |             <RvctClst>0</RvctClst>
176 |             <GenPPlst>0</GenPPlst>
177 |             <AdsCpuType>"Cortex-M4"</AdsCpuType>
178 |             <RvctDeviceName></RvctDeviceName>
179 |             <mOS>0</mOS>
180 |             <uocRom>0</uocRom>
181 |             <uocRam>0</uocRam>
182 |             <hadIROM>1</hadIROM>
183 |             <hadIRAM>1</hadIRAM>
184 |             <hadXRAM>0</hadXRAM>
185 |             <uocXRam>0</uocXRam>
186 |             <RvdsVP>2</RvdsVP>
187 |             <RvdsMve>0</RvdsMve>
188 |             <hadIRAM2>1</hadIRAM2>
189 |             <hadIROM2>1</hadIROM2>
190 |             <StupSel>8</StupSel>
191 |             <useUlib>0</useUlib>
192 |             <EndSel>0</EndSel>
193 |             <uLtcg>0</uLtcg>
194 |             <nSecure>0</nSecure>
195 |             <RoSelD>3</RoSelD>
196 |             <RwSelD>4</RwSelD>
197 |             <CodeSel>0</CodeSel>
198 |             <OptFeed>0</OptFeed>
199 |             <NoZi1>0</NoZi1>
200 |             <NoZi2>0</NoZi2>
201 |             <NoZi3>0</NoZi3>
202 |             <NoZi4>0</NoZi4>
203 |             <NoZi5>0</NoZi5>
204 |             <Ro1Chk>0</Ro1Chk>
205 |             <Ro2Chk>0</Ro2Chk>
206 |             <Ro3Chk>0</Ro3Chk>
207 |             <Ir1Chk>1</Ir1Chk>
208 |             <Ir2Chk>0</Ir2Chk>
209 |             <Ra1Chk>0</Ra1Chk>
210 |             <Ra2Chk>0</Ra2Chk>
211 |             <Ra3Chk>0</Ra3Chk>
212 |             <Im1Chk>1</Im1Chk>
213 |             <Im2Chk>1</Im2Chk>
214 |             <OnChipMemories>
215 |               <Ocm1>
216 |                 <Type>0</Type>
217 |                 <StartAddress>0x0</StartAddress>
218 |                 <Size>0x0</Size>
219 |               </Ocm1>
220 |               <Ocm2>
221 |                 <Type>0</Type>
222 |                 <StartAddress>0x0</StartAddress>
223 |                 <Size>0x0</Size>
224 |               </Ocm2>
225 |               <Ocm3>
226 |                 <Type>0</Type>
227 |                 <StartAddress>0x0</StartAddress>
228 |                 <Size>0x0</Size>
229 |               </Ocm3>
230 |               <Ocm4>
231 |                 <Type>0</Type>
232 |                 <StartAddress>0x0</StartAddress>
233 |                 <Size>0x0</Size>
234 |               </Ocm4>
235 |               <Ocm5>
236 |                 <Type>0</Type>
237 |                 <StartAddress>0x0</StartAddress>
238 |                 <Size>0x0</Size>
239 |               </Ocm5>
240 |               <Ocm6>
241 |                 <Type>0</Type>
242 |                 <StartAddress>0x0</StartAddress>
243 |                 <Size>0x0</Size>
244 |               </Ocm6>
245 |               <IRAM>
246 |                 <Type>0</Type>
247 |                 <StartAddress>0x20000000</StartAddress>
248 |                 <Size>0xffc0</Size>
249 |               </IRAM>
250 |               <IROM>
251 |                 <Type>1</Type>
252 |                 <StartAddress>0x8000000</StartAddress>
253 |                 <Size>0x80000</Size>
254 |               </IROM>
255 |               <XRAM>
256 |                 <Type>0</Type>
257 |                 <StartAddress>0x0</StartAddress>
258 |                 <Size>0x0</Size>
259 |               </XRAM>
260 |               <OCR_RVCT1>
261 |                 <Type>1</Type>
262 |                 <StartAddress>0x0</StartAddress>
263 |                 <Size>0x0</Size>
264 |               </OCR_RVCT1>
265 |               <OCR_RVCT2>
266 |                 <Type>1</Type>
267 |                 <StartAddress>0x0</StartAddress>
268 |                 <Size>0x0</Size>
269 |               </OCR_RVCT2>
270 |               <OCR_RVCT3>
271 |                 <Type>1</Type>
272 |                 <StartAddress>0x0</StartAddress>
273 |                 <Size>0x0</Size>
274 |               </OCR_RVCT3>
275 |               <OCR_RVCT4>
276 |                 <Type>1</Type>
277 |                 <StartAddress>0x8000000</StartAddress>
278 |                 <Size>0x80000</Size>
279 |               </OCR_RVCT4>
280 |               <OCR_RVCT5>
281 |                 <Type>1</Type>
282 |                 <StartAddress>0xc000000</StartAddress>
283 |                 <Size>0x80000</Size>
284 |               </OCR_RVCT5>
285 |               <OCR_RVCT6>
286 |                 <Type>0</Type>
287 |                 <StartAddress>0x0</StartAddress>
288 |                 <Size>0x0</Size>
289 |               </OCR_RVCT6>
290 |               <OCR_RVCT7>
291 |                 <Type>0</Type>
292 |                 <StartAddress>0x0</StartAddress>
293 |                 <Size>0x0</Size>
294 |               </OCR_RVCT7>
295 |               <OCR_RVCT8>
296 |                 <Type>0</Type>
297 |                 <StartAddress>0x0</StartAddress>
298 |                 <Size>0x0</Size>
299 |               </OCR_RVCT8>
300 |               <OCR_RVCT9>
301 |                 <Type>0</Type>
302 |                 <StartAddress>0x20000000</StartAddress>
303 |                 <Size>0xffc0</Size>
304 |               </OCR_RVCT9>
305 |               <OCR_RVCT10>
306 |                 <Type>0</Type>
307 |                 <StartAddress>0x1fffc000</StartAddress>
308 |                 <Size>0x4000</Size>
309 |               </OCR_RVCT10>
310 |             </OnChipMemories>
311 |             <RvctStartVector></RvctStartVector>
312 |           </ArmAdsMisc>
313 |           <Cads>
314 |             <interw>1</interw>
315 |             <Optim>1</Optim>
316 |             <oTime>0</oTime>
317 |             <SplitLS>0</SplitLS>
318 |             <OneElfS>1</OneElfS>
319 |             <Strict>0</Strict>
320 |             <EnumInt>0</EnumInt>
321 |             <PlainCh>0</PlainCh>
322 |             <Ropi>0</Ropi>
323 |             <Rwpi>0</Rwpi>
324 |             <wLevel>2</wLevel>
325 |             <uThumb>0</uThumb>
326 |             <uSurpInc>0</uSurpInc>
327 |             <uC99>1</uC99>
328 |             <uGnu>1</uGnu>
329 |             <useXO>0</useXO>
330 |             <v6Lang>1</v6Lang>
331 |             <v6LangP>1</v6LangP>
332 |             <vShortEn>1</vShortEn>
333 |             <vShortWch>1</vShortWch>
334 |             <v6Lto>0</v6Lto>
335 |             <v6WtE>0</v6WtE>
336 |             <v6Rtti>0</v6Rtti>
337 |             <VariousControls>
338 |               <MiscControls></MiscControls>
339 |               <Define></Define>
340 |               <Undefine></Undefine>
341 |               <IncludePath>.\FOC;.\PMSM;.\SYS_Init;.\FOC_Control;.\DEBUG</IncludePath>
342 |             </VariousControls>
343 |           </Cads>
344 |           <Aads>
345 |             <interw>1</interw>
346 |             <Ropi>0</Ropi>
347 |             <Rwpi>0</Rwpi>
348 |             <thumb>0</thumb>
349 |             <SplitLS>0</SplitLS>
350 |             <SwStkChk>0</SwStkChk>
351 |             <NoWarn>0</NoWarn>
352 |             <uSurpInc>0</uSurpInc>
353 |             <useXO>0</useXO>
354 |             <uClangAs>0</uClangAs>
355 |             <VariousControls>
356 |               <MiscControls></MiscControls>
357 |               <Define></Define>
358 |               <Undefine></Undefine>
359 |               <IncludePath></IncludePath>
360 |             </VariousControls>
361 |           </Aads>
362 |           <LDads>
363 |             <umfTarg>1</umfTarg>
364 |             <Ropi>0</Ropi>
365 |             <Rwpi>0</Rwpi>
366 |             <noStLib>0</noStLib>
367 |             <RepFail>1</RepFail>
368 |             <useFile>0</useFile>
369 |             <TextAddressRange>0x08000000</TextAddressRange>
370 |             <DataAddressRange>0x20000000</DataAddressRange>
371 |             <pXoBase></pXoBase>
372 |             <ScatterFile></ScatterFile>
373 |             <IncludeLibs></IncludeLibs>
374 |             <IncludeLibsPath></IncludeLibsPath>
375 |             <Misc></Misc>
376 |             <LinkerInputFile></LinkerInputFile>
377 |             <DisabledWarnings></DisabledWarnings>
378 |           </LDads>
379 |         </TargetArmAds>
380 |       </TargetOption>
381 |       <Groups>
382 |         <Group>
383 |           <GroupName>MAIN</GroupName>
384 |           <Files>
385 |             <File>
386 |               <FileName>main.c</FileName>
387 |               <FileType>1</FileType>
388 |               <FilePath>.\Main\main.c</FilePath>
389 |             </File>
390 |           </Files>
391 |         </Group>
392 |         <Group>
393 |           <GroupName>SYS_Init</GroupName>
394 |           <Files>
395 |             <File>
396 |               <FileName>MCU_Initialize.c</FileName>
397 |               <FileType>1</FileType>
398 |               <FilePath>.\SYS_Init\MCU_Initialize.c</FilePath>
399 |             </File>
400 |             <File>
401 |               <FileName>VAR_Initialize.c</FileName>
402 |               <FileType>1</FileType>
403 |               <FilePath>.\SYS_Init\VAR_Initialize.c</FilePath>
404 |             </File>
405 |           </Files>
406 |         </Group>
407 |         <Group>
408 |           <GroupName>FOC_Control</GroupName>
409 |           <Files>
410 |             <File>
411 |               <FileName>Call_Functions.c</FileName>
412 |               <FileType>1</FileType>
413 |               <FilePath>.\FOC_Control\Call_Functions.c</FilePath>
414 |             </File>
415 |             <File>
416 |               <FileName>INT_ISR.c</FileName>
417 |               <FileType>1</FileType>
418 |               <FilePath>.\FOC_Control\INT_ISR.c</FilePath>
419 |             </File>
420 |             <File>
421 |               <FileName>PI_Control.c</FileName>
422 |               <FileType>1</FileType>
423 |               <FilePath>.\FOC_Control\PI_Control.c</FilePath>
424 |             </File>
425 |             <File>
426 |               <FileName>Motor_Functions.h</FileName>
427 |               <FileType>5</FileType>
428 |               <FilePath>.\FOC_Control\Motor_Functions.h</FilePath>
429 |             </File>
430 |             <File>
431 |               <FileName>SVPWM.h</FileName>
432 |               <FileType>5</FileType>
433 |               <FilePath>.\FOC_Control\SVPWM.h</FilePath>
434 |             </File>
435 |             <File>
436 |               <FileName>PMSM_FOC.lib</FileName>
437 |               <FileType>4</FileType>
438 |               <FilePath>.\Sensorless_Lib\PMSM_FOC.lib</FilePath>
439 |             </File>
440 |             <File>
441 |               <FileName>..\..\study\XHY\Github\GITHUB\Sensorless_FOC\Sensorless_Lib\SVPWM.lib</FileName>
442 |               <FileType>4</FileType>
443 |               <FilePath>$TC_ROOT$\..\..\study\XHY\Github\GITHUB\Sensorless_FOC\Sensorless_Lib\SVPWM.lib</FilePath>
444 |             </File>
445 |           </Files>
446 |         </Group>
447 |         <Group>
448 |           <GroupName>DEBUG</GroupName>
449 |           <Files>
450 |             <File>
451 |               <FileName>Agreement.c</FileName>
452 |               <FileType>1</FileType>
453 |               <FilePath>.\DEBUG\Agreement.c</FilePath>
454 |             </File>
455 |             <File>
456 |               <FileName>DAC.c</FileName>
457 |               <FileType>1</FileType>
458 |               <FilePath>.\DEBUG\DAC.c</FilePath>
459 |             </File>
460 |             <File>
461 |               <FileName>UART.c</FileName>
462 |               <FileType>1</FileType>
463 |               <FilePath>.\DEBUG\UART.c</FilePath>
464 |             </File>
465 |           </Files>
466 |         </Group>
467 |         <Group>
468 |           <GroupName>Readme</GroupName>
469 |           <Files>
470 |             <File>
471 |               <FileName>README.txt</FileName>
472 |               <FileType>5</FileType>
473 |               <FilePath>.\Readme\README.txt</FilePath>
474 |             </File>
475 |           </Files>
476 |         </Group>
477 |         <Group>
478 |           <GroupName>::CMSIS</GroupName>
479 |         </Group>
480 |         <Group>
481 |           <GroupName>::Device</GroupName>
482 |         </Group>
483 |       </Groups>
484 |     </Target>
485 |   </Targets>
486 | 
487 |   <RTE>
488 |     <apis/>
489 |     <components>
490 |       <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.1.2" condition="ARMv6_7_8-M Device">
491 |         <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.4.0"/>
492 |         <targetInfos>
493 |           <targetInfo name="Target 1"/>
494 |         </targetInfos>
495 |       </component>
496 |       <component Cclass="Device" Cgroup="RTE_Device" Cvendor="Infineon" Cversion="1.1.0" condition="XMC4 CMSIS">
497 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
498 |         <targetInfos>
499 |           <targetInfo name="Target 1"/>
500 |         </targetInfos>
501 |       </component>
502 |       <component Cclass="Device" Cgroup="Startup" Cvendor="Infineon" Cversion="2.2.0" condition="XMC4 CMSIS">
503 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
504 |         <targetInfos>
505 |           <targetInfo name="Target 1"/>
506 |         </targetInfos>
507 |       </component>
508 |       <component Cclass="Device" Cgroup="XMClib" Csub="DAC" Cvendor="Infineon" Cversion="2.1.18" condition="XMC4 CMSIS SCU">
509 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
510 |         <targetInfos>
511 |           <targetInfo name="Target 1"/>
512 |         </targetInfos>
513 |       </component>
514 |       <component Cclass="Device" Cgroup="XMClib" Csub="GPIO" Cvendor="Infineon" Cversion="2.1.18" condition="XMC4 CMSIS">
515 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
516 |         <targetInfos>
517 |           <targetInfo name="Target 1"/>
518 |         </targetInfos>
519 |       </component>
520 |       <component Cclass="Device" Cgroup="XMClib" Csub="SCU" Cvendor="Infineon" Cversion="2.1.18" condition="XMC4 CMSIS">
521 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
522 |         <targetInfos>
523 |           <targetInfo name="Target 1"/>
524 |         </targetInfos>
525 |       </component>
526 |       <component Cclass="Device" Cgroup="XMClib" Csub="UART" Cvendor="Infineon" Cversion="2.1.18" condition="XMC4 CMSIS SCU">
527 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
528 |         <targetInfos>
529 |           <targetInfo name="Target 1"/>
530 |         </targetInfos>
531 |       </component>
532 |     </components>
533 |     <files>
534 |       <file attr="config" category="header" condition="XMC4400_F100" name="RTE_Driver\Config\XMC4400_F100\RTE_Device.h" version="1.1.0">
535 |         <instance index="0">RTE\Device\XMC4400-F100x512\RTE_Device.h</instance>
536 |         <component Cclass="Device" Cgroup="RTE_Device" Cvendor="Infineon" Cversion="1.1.0" condition="XMC4 CMSIS"/>
537 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
538 |         <targetInfos>
539 |           <targetInfo name="Target 1"/>
540 |         </targetInfos>
541 |       </file>
542 |       <file attr="config" category="source" condition="XMC4400_ARMCC" name="Device\XMC4400_series\Source\ARM\startup_XMC4400.s" version="1.5.0">
543 |         <instance index="0">RTE\Device\XMC4400-F100x512\startup_XMC4400.s</instance>
544 |         <component Cclass="Device" Cgroup="Startup" Cvendor="Infineon" Cversion="2.2.0" condition="XMC4 CMSIS"/>
545 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
546 |         <targetInfos>
547 |           <targetInfo name="Target 1"/>
548 |         </targetInfos>
549 |       </file>
550 |       <file attr="config" category="source" condition="XMC44xx" name="Device\XMC4400_series\Source\system_XMC4400.c" version="3.1.3">
551 |         <instance index="0">RTE\Device\XMC4400-F100x512\system_XMC4400.c</instance>
552 |         <component Cclass="Device" Cgroup="Startup" Cvendor="Infineon" Cversion="2.2.0" condition="XMC4 CMSIS"/>
553 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
554 |         <targetInfos>
555 |           <targetInfo name="Target 1"/>
556 |         </targetInfos>
557 |       </file>
558 |       <file attr="config" category="header" condition="XMC4400_F64" name="RTE_Driver\Config\XMC4400_F64\RTE_Device.h" version="1.1.0">
559 |         <instance index="0" removed="1">RTE\Device\XMC4400-F64x512\RTE_Device.h</instance>
560 |         <component Cclass="Device" Cgroup="RTE_Device" Cvendor="Infineon" Cversion="1.1.0" condition="XMC4 CMSIS"/>
561 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
562 |         <targetInfos/>
563 |       </file>
564 |       <file attr="config" category="source" condition="XMC4400_ARMCC" name="Device\XMC4400_series\Source\ARM\startup_XMC4400.s" version="1.5.0">
565 |         <instance index="0" removed="1">RTE\Device\XMC4400-F64x512\startup_XMC4400.s</instance>
566 |         <component Cclass="Device" Cgroup="Startup" Cvendor="Infineon" Cversion="2.2.0" condition="XMC4 CMSIS"/>
567 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
568 |         <targetInfos/>
569 |       </file>
570 |       <file attr="config" category="source" condition="XMC44xx" name="Device\XMC4400_series\Source\system_XMC4400.c" version="3.1.4">
571 |         <instance index="0" removed="1">RTE\Device\XMC4400-F64x512\system_XMC4400.c</instance>
572 |         <component Cclass="Device" Cgroup="Startup" Cvendor="Infineon" Cversion="2.2.0" condition="XMC4 CMSIS"/>
573 |         <package license="License/CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://dave.infineon.com/Libraries/CMSIS_PACK/" vendor="Infineon" version="2.11.0"/>
574 |         <targetInfos/>
575 |       </file>
576 |     </files>
577 |   </RTE>
578 | 
579 | </Project>
580 | 


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
 1 | - [ SensorlessFOC](#head1)
 2 | 	- [ 一、介绍 ](#head2)
 3 | 	- [ 二、引脚定义](#head3)
 4 | 	- [ 三、软件设计](#head4)
 5 | # <span id="head1"> SensorlessFOC</span>
 6 | 感谢陆兵同学 @gitee.com/robbinlu 编写的上位机MotorTest
 7 | ## <span id="head2"> 一、介绍 </span>
 8 | 基于 XMC4400F100K512 的PMSM无位置传感器驱动控制程序  
 9 | ## <span id="head3"> 二、引脚定义</span>
10 | 注：Sensorless FOC 不需要使用位置传感器接口
11 | + #### A/D采样输入： 
12 | 
13 | | Iu    | Iv    | Iw     | RP    | 
14 | | :----:| :----: | :----: |:----: | 
15 | | P14.2  | P15.2  | P14.8   | P14.1  | 
16 | 
17 | + #### 六路PWM脉冲输出：  
18 | 
19 | | UH    | UL    | VH     | VL    | WH    | WL     |
20 | | :----:| :----: | :----: |:----: | :----: | :----: |
21 | | P0.5  | P0.2  | P0.4   | P0.1  | P0.3  | P0.0   |
22 | 
23 | + #### D/A输出： 
24 | 
25 | | DAC1    |  
26 | | :----:| 
27 | | P14.9  | 
28 | 
29 | + #### 通讯接口 (UART)： 
30 | 
31 | | RX    | TX    |  
32 | | :----:| :----: | 
33 | | P2.2  | P2.5  | 
34 | 
35 | ## <span id="head4"> 三、软件设计</span>
36 | * #### 底层驱动 ：  
37 | 1. **CCU8** :  
38 |      - 生成3路带死区的互补的PWM信号  
39 |      - 一路专用的PWM用于触发采样和PWM占空比更新
40 | 2. **VADC** :   
41 |    -  VADC0 G0、G2、G3三组同步采样（G0主 G2,G3从）
42 | 3. **POSIF** :  
43 |    - 独立多通道模式用于保护封波
44 | 4. **USIC** :  
45 |    - ASC协议UART模式，用于和上位机通信
46 | 5. **DAC**：  
47 |     - DAC1输出用于观测器和角度的实时Debug  
48 | 
49 | * #### 主要中断：
50 |  1. **CCU80_0_IRQHandler**:  
51 |      - 更新下一个62.5us内的PWM信号占空比  
52 |      - 处理初始定位和闭环I/F启动相关流程
53 | 2. **VADC0_G0_0_IRQHandler**:   
54 |    - 三相电流重构  
55 |    - 观测器反电势估计
56 |    - 锁相环角度估计与转速估计 
57 |    - I/F-FOC切换相关流程
58 |    - dq轴电流环运算
59 |    - 虚拟示波器Flash存储
60 | 1. **SysTick_Handler**:   
61 |    - 转速环运算 
62 |    - 上位机显示
63 |    - 虚拟示波器Flash数据显示
64 | 
65 | Control_Loop_Mode  1：电流单闭环  2：转速电流双闭环   
66 | 


--------------------------------------------------------------------------------
/RTE/Device/XMC4400-F100x512/startup_XMC4400.s:
--------------------------------------------------------------------------------
  1 | ;*******************************************************************************
  2 | ;* @file     startup_XMC4400.s
  3 | ;* @brief    CMSIS Core Device Startup File for
  4 | ;*           Infineon XMC4400 Device Series
  5 | ;* @version  V1.5
  6 | ;* @date     June 2016
  7 | ;*
  8 | ;* @cond
  9 | ;*********************************************************************************************************************
 10 | ;* Copyright (c) 2012-2016, Infineon Technologies AG
 11 | ;* All rights reserved.                        
 12 | ;*                                             
 13 | ;* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
 14 | ;* following conditions are met:   
 15 | ;*                                                                              
 16 | ;* Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
 17 | ;* disclaimer.                        
 18 | ;* 
 19 | ;* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
 20 | ;* disclaimer in the documentation and/or other materials provided with the distribution.                       
 21 | ;* 
 22 | ;* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
 23 | ;* products derived from this software without specific prior written permission.                                           
 24 | ;*                                                                              
 25 | ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
 26 | ;* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
 27 | ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 28 | ;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
 29 | ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
 30 | ;* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 31 | ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
 32 | ;*                                                                              
 33 | ;* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
 34 | ;* Infineon Technologies AG dave@infineon.com).                                                          
 35 | ;*********************************************************************************************************************
 36 | ;*
 37 | ;************************** Version History ************************************
 38 | ; V0.2, August 2012, First version
 39 | ; V1.0, February 2013, FIX for CPU prefetch bug implemented
 40 | ; V1.1, August 2013, Fix the bug of stack pointer alignment to a 8 byte boundary
 41 | ; V1.2, November 2014, Disable CPU workaround. Increased stack size.
 42 | ;                       Removed DAVE3 dependency
 43 | ; V1.3, November 2015, Remove peripherals not included in device.
 44 | ; V1.4, March    2016, Fix weak definition of Veneers.
 45 | ;                       Only relevant for AA, which needs ENABLE_PMU_CM_001_WORKAROUND 
 46 | ; V1.5, June     2016, Rename ENABLE_CPU_CM_001_WORKAROUND to ENABLE_PMU_CM_001_WORKAROUND
 47 | ;                      Action required: If using AA step, use ENABLE_PMU_CM_001_WORKAROUND instead of ENABLE_CPU_CM_001_WORKAROUND
 48 | ;*******************************************************************************
 49 | ;* @endcond
 50 | 
 51 | ; ------------------ <<< Use Configuration Wizard in Context Menu >>> ------------------
 52 |            
 53 | ; <h> Stack Configuration
 54 | ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 55 | ; </h>
 56 | 
 57 | Stack_Size      EQU     0x00000800
 58 | 
 59 |                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 60 | Stack_Mem       SPACE   Stack_Size
 61 | __initial_sp
 62 | 
 63 | 
 64 | ; <h> Heap Configuration
 65 | ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 66 | ; </h>
 67 | 
 68 | Heap_Size       EQU     0x00000200
 69 | 
 70 |                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 71 | __heap_base
 72 | Heap_Mem        SPACE   Heap_Size
 73 | __heap_limit
 74 | 
 75 |                 PRESERVE8
 76 |                 THUMB
 77 | 
 78 |                 IF    :DEF:ENABLE_PMU_CM_001_WORKAROUND
 79 |                     MACRO
 80 |                     Entry $Handler
 81 |                     DCD   $Handler._Veneer
 82 |                     MEND
 83 |                 ELSE
 84 |                     MACRO
 85 |                     Entry $Handler
 86 |                     DCD   $Handler
 87 |                     MEND
 88 |                 ENDIF
 89 | 
 90 | ; Vector Table Mapped to Address 0 at Reset
 91 | 
 92 |                 AREA    RESET, DATA, READONLY
 93 |                 EXPORT  __Vectors
 94 |                 EXPORT  __Vectors_End
 95 |                 EXPORT  __Vectors_Size
 96 |                
 97 | __Vectors       DCD     __initial_sp              ; 0 Top of Stack
 98 |                 DCD     Reset_Handler             ; 1 Reset Handler
 99 |                 Entry   NMI_Handler               ; 2 NMI Handler
100 |                 Entry   HardFault_Handler         ; 3 Hard Fault Handler
101 |                 Entry   MemManage_Handler         ; 4 MPU Fault Handler
102 |                 Entry   BusFault_Handler          ; 5 Bus Fault Handler
103 |                 Entry   UsageFault_Handler        ; 6 Usage Fault Handler
104 |                 DCD     0                         ; 7 Reserved
105 |                 DCD     0                         ; 8 Reserved
106 |                 DCD     0                         ; 9 Reserved
107 |                 DCD     0                         ; 10 Reserved
108 |                 Entry   SVC_Handler               ; 11 SVCall Handler
109 |                 Entry   DebugMon_Handler          ; 12 Debug Monitor Handler
110 |                 DCD     0                         ; 13 Reserved
111 |                 Entry   PendSV_Handler            ; 14 PendSV Handler
112 |                 Entry   SysTick_Handler           ; 15 SysTick Handler
113 | 
114 | ; Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals */
115 |                 Entry   SCU_0_IRQHandler          ; Handler name for SR SCU_0     
116 |                 Entry   ERU0_0_IRQHandler         ; Handler name for SR ERU0_0    
117 |                 Entry   ERU0_1_IRQHandler         ; Handler name for SR ERU0_1    
118 |                 Entry   ERU0_2_IRQHandler         ; Handler name for SR ERU0_2    
119 |                 Entry   ERU0_3_IRQHandler         ; Handler name for SR ERU0_3     
120 |                 Entry   ERU1_0_IRQHandler         ; Handler name for SR ERU1_0    
121 |                 Entry   ERU1_1_IRQHandler         ; Handler name for SR ERU1_1    
122 |                 Entry   ERU1_2_IRQHandler         ; Handler name for SR ERU1_2    
123 |                 Entry   ERU1_3_IRQHandler         ; Handler name for SR ERU1_3    
124 |                 DCD     0                         ; Not Available                 
125 |                 DCD     0                         ; Not Available                 
126 |                 DCD     0                         ; Not Available                 
127 |                 Entry   PMU0_0_IRQHandler         ; Handler name for SR PMU0_0    
128 |                 DCD     0                         ; Not Available                 
129 |                 Entry   VADC0_C0_0_IRQHandler     ; Handler name for SR VADC0_C0_0  
130 |                 Entry   VADC0_C0_1_IRQHandler     ; Handler name for SR VADC0_C0_1  
131 |                 Entry   VADC0_C0_2_IRQHandler     ; Handler name for SR VADC0_C0_1  
132 |                 Entry   VADC0_C0_3_IRQHandler     ; Handler name for SR VADC0_C0_3  
133 |                 Entry   VADC0_G0_0_IRQHandler     ; Handler name for SR VADC0_G0_0  
134 |                 Entry   VADC0_G0_1_IRQHandler     ; Handler name for SR VADC0_G0_1  
135 |                 Entry   VADC0_G0_2_IRQHandler     ; Handler name for SR VADC0_G0_2  
136 |                 Entry   VADC0_G0_3_IRQHandler     ; Handler name for SR VADC0_G0_3  
137 |                 Entry   VADC0_G1_0_IRQHandler     ; Handler name for SR VADC0_G1_0  
138 |                 Entry   VADC0_G1_1_IRQHandler     ; Handler name for SR VADC0_G1_1  
139 |                 Entry   VADC0_G1_2_IRQHandler     ; Handler name for SR VADC0_G1_2  
140 |                 Entry   VADC0_G1_3_IRQHandler     ; Handler name for SR VADC0_G1_3  
141 |                 Entry   VADC0_G2_0_IRQHandler     ; Handler name for SR VADC0_G2_0  
142 |                 Entry   VADC0_G2_1_IRQHandler     ; Handler name for SR VADC0_G2_1  
143 |                 Entry   VADC0_G2_2_IRQHandler     ; Handler name for SR VADC0_G2_2  
144 |                 Entry   VADC0_G2_3_IRQHandler     ; Handler name for SR VADC0_G2_3  
145 |                 Entry   VADC0_G3_0_IRQHandler     ; Handler name for SR VADC0_G3_0  
146 |                 Entry   VADC0_G3_1_IRQHandler     ; Handler name for SR VADC0_G3_1  
147 |                 Entry   VADC0_G3_2_IRQHandler     ; Handler name for SR VADC0_G3_2  
148 |                 Entry   VADC0_G3_3_IRQHandler     ; Handler name for SR VADC0_G3_3  
149 |                 Entry   DSD0_0_IRQHandler         ; Handler name for SR DSD_SRM_0 
150 |                 Entry   DSD0_1_IRQHandler         ; Handler name for SR DSD_SRM_1 
151 |                 Entry   DSD0_2_IRQHandler         ; Handler name for SR DSD_SRM_2 
152 |                 Entry   DSD0_3_IRQHandler         ; Handler name for SR DSD_SRM_3 
153 |                 Entry   DSD0_4_IRQHandler         ; Handler name for SR DSD_SRA_0 
154 |                 Entry   DSD0_5_IRQHandler         ; Handler name for SR DSD_SRA_1 
155 |                 Entry   DSD0_6_IRQHandler         ; Handler name for SR DSD_SRA_2 
156 |                 Entry   DSD0_7_IRQHandler         ; Handler name for SR DSD_SRA_3 
157 |                 Entry   DAC0_0_IRQHandler         ; Handler name for SR DAC0_0    
158 |                 Entry   DAC0_1_IRQHandler         ; Handler name for SR DAC0_1    
159 |                 Entry   CCU40_0_IRQHandler        ; Handler name for SR CCU40_0   
160 |                 Entry   CCU40_1_IRQHandler        ; Handler name for SR CCU40_1   
161 |                 Entry   CCU40_2_IRQHandler        ; Handler name for SR CCU40_2   
162 |                 Entry   CCU40_3_IRQHandler        ; Handler name for SR CCU40_3   
163 |                 Entry   CCU41_0_IRQHandler        ; Handler name for SR CCU41_0   
164 |                 Entry   CCU41_1_IRQHandler        ; Handler name for SR CCU41_1   
165 |                 Entry   CCU41_2_IRQHandler        ; Handler name for SR CCU41_2   
166 |                 Entry   CCU41_3_IRQHandler        ; Handler name for SR CCU41_3   
167 |                 Entry   CCU42_0_IRQHandler        ; Handler name for SR CCU42_0   
168 |                 Entry   CCU42_1_IRQHandler        ; Handler name for SR CCU42_1   
169 |                 Entry   CCU42_2_IRQHandler        ; Handler name for SR CCU42_2   
170 |                 Entry   CCU42_3_IRQHandler        ; Handler name for SR CCU42_3   
171 |                 Entry   CCU43_0_IRQHandler        ; Handler name for SR CCU43_0   
172 |                 Entry   CCU43_1_IRQHandler        ; Handler name for SR CCU43_1   
173 |                 Entry   CCU43_2_IRQHandler        ; Handler name for SR CCU43_2   
174 |                 Entry   CCU43_3_IRQHandler        ; Handler name for SR CCU43_3   
175 |                 Entry   CCU80_0_IRQHandler        ; Handler name for SR CCU80_0   
176 |                 Entry   CCU80_1_IRQHandler        ; Handler name for SR CCU80_1   
177 |                 Entry   CCU80_2_IRQHandler        ; Handler name for SR CCU80_2   
178 |                 Entry   CCU80_3_IRQHandler        ; Handler name for SR CCU80_3   
179 |                 Entry   CCU81_0_IRQHandler        ; Handler name for SR CCU81_0   
180 |                 Entry   CCU81_1_IRQHandler        ; Handler name for SR CCU81_1   
181 |                 Entry   CCU81_2_IRQHandler        ; Handler name for SR CCU81_2   
182 |                 Entry   CCU81_3_IRQHandler        ; Handler name for SR CCU81_3   
183 |                 Entry   POSIF0_0_IRQHandler       ; Handler name for SR POSIF0_0  
184 |                 Entry   POSIF0_1_IRQHandler       ; Handler name for SR POSIF0_1  
185 |                 Entry   POSIF1_0_IRQHandler       ; Handler name for SR POSIF1_0  
186 |                 Entry   POSIF1_1_IRQHandler       ; Handler name for SR POSIF1_1  
187 |                 Entry   HRPWM_0_IRQHandler        ; Handler name for SR HRPWM_0   
188 |                 Entry   HRPWM_1_IRQHandler        ; Handler name for SR HRPWM_1   
189 |                 Entry   HRPWM_2_IRQHandler        ; Handler name for SR HRPWM_2   
190 |                 Entry   HRPWM_3_IRQHandler        ; Handler name for SR HRPWM_3   
191 |                 Entry   CAN0_0_IRQHandler         ; Handler name for SR CAN0_0    
192 |                 Entry   CAN0_1_IRQHandler         ; Handler name for SR CAN0_1    
193 |                 Entry   CAN0_2_IRQHandler         ; Handler name for SR CAN0_2    
194 |                 Entry   CAN0_3_IRQHandler         ; Handler name for SR CAN0_3    
195 |                 Entry   CAN0_4_IRQHandler         ; Handler name for SR CAN0_4    
196 |                 Entry   CAN0_5_IRQHandler         ; Handler name for SR CAN0_5    
197 |                 Entry   CAN0_6_IRQHandler         ; Handler name for SR CAN0_6    
198 |                 Entry   CAN0_7_IRQHandler         ; Handler name for SR CAN0_7    
199 |                 Entry   USIC0_0_IRQHandler        ; Handler name for SR USIC0_0   
200 |                 Entry   USIC0_1_IRQHandler        ; Handler name for SR USIC0_1   
201 |                 Entry   USIC0_2_IRQHandler        ; Handler name for SR USIC0_2   
202 |                 Entry   USIC0_3_IRQHandler        ; Handler name for SR USIC0_3   
203 |                 Entry   USIC0_4_IRQHandler        ; Handler name for SR USIC0_4   
204 |                 Entry   USIC0_5_IRQHandler        ; Handler name for SR USIC0_5   
205 |                 Entry   USIC1_0_IRQHandler        ; Handler name for SR USIC1_0   
206 |                 Entry   USIC1_1_IRQHandler        ; Handler name for SR USIC1_1   
207 |                 Entry   USIC1_2_IRQHandler        ; Handler name for SR USIC1_2   
208 |                 Entry   USIC1_3_IRQHandler        ; Handler name for SR USIC1_3   
209 |                 Entry   USIC1_4_IRQHandler        ; Handler name for SR USIC1_4   
210 |                 Entry   USIC1_5_IRQHandler        ; Handler name for SR USIC1_5   
211 |                 DCD     0                         ; Not Available                 
212 |                 DCD     0                         ; Not Available                 
213 |                 DCD     0                         ; Not Available                 
214 |                 DCD     0                         ; Not Available                 
215 |                 DCD     0                         ; Not Available                 
216 |                 DCD     0                         ; Not Available                 
217 |                 Entry   LEDTS0_0_IRQHandler       ; Handler name for SR LEDTS0_0  
218 |                 DCD     0                         ; Not Available                 
219 |                 Entry   FCE0_0_IRQHandler         ; Handler name for SR FCE0_0    
220 |                 Entry   GPDMA0_0_IRQHandler       ; Handler name for SR GPDMA0_0  
221 |                 DCD     0                         ; Not Available                 
222 |                 Entry   USB0_0_IRQHandler         ; Handler name for SR USB0_0    
223 |                 Entry   ETH0_0_IRQHandler         ; Handler name for SR ETH0_0    
224 |                 DCD     0                         ; Not Available                 
225 |                 DCD     0                         ; Not Available                 
226 |                 DCD     0                         ; Not Available                 
227 | __Vectors_End
228 | 
229 | __Vectors_Size  EQU     __Vectors_End - __Vectors
230 | 
231 |                 AREA    |.text|, CODE, READONLY
232 | 
233 | ; Reset Handler
234 | 
235 | Reset_Handler   PROC
236 |                 EXPORT  Reset_Handler           [WEAK]
237 |                 IMPORT  SystemInit
238 |                 IMPORT  __main
239 |                 LDR     SP, =__initial_sp                                
240 |                 LDR     R0, =SystemInit
241 |                 BLX     R0
242 |                 LDR     R0, =__main
243 |                 BX      R0
244 |                 ENDP
245 | 
246 | ; Dummy Exception Handlers (infinite loops which can be modified)
247 |              
248 | Default_Handler PROC
249 |                 EXPORT  NMI_Handler             [WEAK]
250 |                 EXPORT  HardFault_Handler       [WEAK]
251 |                 EXPORT  MemManage_Handler       [WEAK]
252 |                 EXPORT  BusFault_Handler        [WEAK]
253 |                 EXPORT  UsageFault_Handler      [WEAK]
254 |                 EXPORT  SVC_Handler             [WEAK]
255 |                 EXPORT  DebugMon_Handler        [WEAK]
256 |                 EXPORT  PendSV_Handler          [WEAK]
257 |                 EXPORT  SysTick_Handler         [WEAK]
258 |                 
259 |                 EXPORT  SCU_0_IRQHandler        [WEAK]
260 |                 EXPORT  ERU0_0_IRQHandler       [WEAK]
261 |                 EXPORT  ERU0_1_IRQHandler       [WEAK]
262 |                 EXPORT  ERU0_2_IRQHandler       [WEAK]
263 |                 EXPORT  ERU0_3_IRQHandler       [WEAK]
264 |                 EXPORT  ERU1_0_IRQHandler       [WEAK]
265 |                 EXPORT  ERU1_1_IRQHandler       [WEAK]
266 |                 EXPORT  ERU1_2_IRQHandler       [WEAK]
267 |                 EXPORT  ERU1_3_IRQHandler       [WEAK]
268 |                 EXPORT  PMU0_0_IRQHandler       [WEAK]
269 |                 EXPORT  VADC0_C0_0_IRQHandler   [WEAK]
270 |                 EXPORT  VADC0_C0_1_IRQHandler   [WEAK]
271 |                 EXPORT  VADC0_C0_2_IRQHandler   [WEAK]
272 |                 EXPORT  VADC0_C0_3_IRQHandler   [WEAK]
273 |                 EXPORT  VADC0_G0_0_IRQHandler   [WEAK]
274 |                 EXPORT  VADC0_G0_1_IRQHandler   [WEAK]
275 |                 EXPORT  VADC0_G0_2_IRQHandler   [WEAK]
276 |                 EXPORT  VADC0_G0_3_IRQHandler   [WEAK]
277 |                 EXPORT  VADC0_G1_0_IRQHandler   [WEAK]
278 |                 EXPORT  VADC0_G1_1_IRQHandler   [WEAK]
279 |                 EXPORT  VADC0_G1_2_IRQHandler   [WEAK]
280 |                 EXPORT  VADC0_G1_3_IRQHandler   [WEAK]
281 |                 EXPORT  VADC0_G2_0_IRQHandler   [WEAK]
282 |                 EXPORT  VADC0_G2_1_IRQHandler   [WEAK]
283 |                 EXPORT  VADC0_G2_2_IRQHandler   [WEAK]
284 |                 EXPORT  VADC0_G2_3_IRQHandler   [WEAK]
285 |                 EXPORT  VADC0_G3_0_IRQHandler   [WEAK]
286 |                 EXPORT  VADC0_G3_1_IRQHandler   [WEAK]
287 |                 EXPORT  VADC0_G3_2_IRQHandler   [WEAK]
288 |                 EXPORT  VADC0_G3_3_IRQHandler   [WEAK]
289 |                 EXPORT  DSD0_0_IRQHandler       [WEAK]
290 |                 EXPORT  DSD0_1_IRQHandler       [WEAK]
291 |                 EXPORT  DSD0_2_IRQHandler       [WEAK]
292 |                 EXPORT  DSD0_3_IRQHandler       [WEAK]
293 |                 EXPORT  DSD0_4_IRQHandler       [WEAK]
294 |                 EXPORT  DSD0_5_IRQHandler       [WEAK]
295 |                 EXPORT  DSD0_6_IRQHandler       [WEAK]
296 |                 EXPORT  DSD0_7_IRQHandler       [WEAK]
297 |                 EXPORT  DAC0_0_IRQHandler       [WEAK]
298 |                 EXPORT  DAC0_1_IRQHandler       [WEAK]
299 |                 EXPORT  CCU40_0_IRQHandler      [WEAK]
300 |                 EXPORT  CCU40_1_IRQHandler      [WEAK]
301 |                 EXPORT  CCU40_2_IRQHandler      [WEAK]
302 |                 EXPORT  CCU40_3_IRQHandler      [WEAK]
303 |                 EXPORT  CCU41_0_IRQHandler      [WEAK]
304 |                 EXPORT  CCU41_1_IRQHandler      [WEAK]
305 |                 EXPORT  CCU41_2_IRQHandler      [WEAK]
306 |                 EXPORT  CCU41_3_IRQHandler      [WEAK]
307 |                 EXPORT  CCU42_0_IRQHandler      [WEAK]
308 |                 EXPORT  CCU42_1_IRQHandler      [WEAK]
309 |                 EXPORT  CCU42_2_IRQHandler      [WEAK]
310 |                 EXPORT  CCU42_3_IRQHandler      [WEAK]
311 |                 EXPORT  CCU43_0_IRQHandler      [WEAK]
312 |                 EXPORT  CCU43_1_IRQHandler      [WEAK]
313 |                 EXPORT  CCU43_2_IRQHandler      [WEAK]
314 |                 EXPORT  CCU43_3_IRQHandler      [WEAK]
315 |                 EXPORT  CCU80_0_IRQHandler      [WEAK]
316 |                 EXPORT  CCU80_1_IRQHandler      [WEAK]
317 |                 EXPORT  CCU80_2_IRQHandler      [WEAK]
318 |                 EXPORT  CCU80_3_IRQHandler      [WEAK]
319 |                 EXPORT  CCU81_0_IRQHandler      [WEAK]
320 |                 EXPORT  CCU81_1_IRQHandler      [WEAK]
321 |                 EXPORT  CCU81_2_IRQHandler      [WEAK]
322 |                 EXPORT  CCU81_3_IRQHandler      [WEAK]
323 |                 EXPORT  POSIF0_0_IRQHandler     [WEAK]
324 |                 EXPORT  POSIF0_1_IRQHandler     [WEAK]
325 |                 EXPORT  POSIF1_0_IRQHandler     [WEAK]
326 |                 EXPORT  POSIF1_1_IRQHandler     [WEAK]
327 |                 EXPORT  HRPWM_0_IRQHandler      [WEAK]
328 |                 EXPORT  HRPWM_1_IRQHandler      [WEAK]
329 |                 EXPORT  HRPWM_2_IRQHandler      [WEAK]
330 |                 EXPORT  HRPWM_3_IRQHandler      [WEAK]
331 |                 EXPORT  CAN0_0_IRQHandler       [WEAK]
332 |                 EXPORT  CAN0_1_IRQHandler       [WEAK]
333 |                 EXPORT  CAN0_2_IRQHandler       [WEAK]
334 |                 EXPORT  CAN0_3_IRQHandler       [WEAK]
335 |                 EXPORT  CAN0_4_IRQHandler       [WEAK]
336 |                 EXPORT  CAN0_5_IRQHandler       [WEAK]
337 |                 EXPORT  CAN0_6_IRQHandler       [WEAK]
338 |                 EXPORT  CAN0_7_IRQHandler       [WEAK]
339 |                 EXPORT  USIC0_0_IRQHandler      [WEAK]
340 |                 EXPORT  USIC0_1_IRQHandler      [WEAK]
341 |                 EXPORT  USIC0_2_IRQHandler      [WEAK]
342 |                 EXPORT  USIC0_3_IRQHandler      [WEAK]
343 |                 EXPORT  USIC0_4_IRQHandler      [WEAK]
344 |                 EXPORT  USIC0_5_IRQHandler      [WEAK]
345 |                 EXPORT  USIC1_0_IRQHandler      [WEAK]
346 |                 EXPORT  USIC1_1_IRQHandler      [WEAK]
347 |                 EXPORT  USIC1_2_IRQHandler      [WEAK]
348 |                 EXPORT  USIC1_3_IRQHandler      [WEAK]
349 |                 EXPORT  USIC1_4_IRQHandler      [WEAK]
350 |                 EXPORT  USIC1_5_IRQHandler      [WEAK]
351 |                 EXPORT  LEDTS0_0_IRQHandler     [WEAK]
352 |                 EXPORT  FCE0_0_IRQHandler       [WEAK]
353 |                 EXPORT  GPDMA0_0_IRQHandler     [WEAK]
354 |                 EXPORT  USB0_0_IRQHandler       [WEAK]
355 |                 EXPORT  ETH0_0_IRQHandler       [WEAK]
356 | 
357 | NMI_Handler
358 | HardFault_Handler
359 | MemManage_Handler
360 | BusFault_Handler
361 | UsageFault_Handler
362 | SVC_Handler
363 | DebugMon_Handler
364 | PendSV_Handler
365 | SysTick_Handler                
366 | SCU_0_IRQHandler
367 | ERU0_0_IRQHandler 
368 | ERU0_1_IRQHandler 
369 | ERU0_2_IRQHandler 
370 | ERU0_3_IRQHandler 
371 | ERU1_0_IRQHandler 
372 | ERU1_1_IRQHandler 
373 | ERU1_2_IRQHandler 
374 | ERU1_3_IRQHandler 
375 | PMU0_0_IRQHandler 
376 | VADC0_C0_0_IRQHandler 
377 | VADC0_C0_1_IRQHandler 
378 | VADC0_C0_2_IRQHandler 
379 | VADC0_C0_3_IRQHandler 
380 | VADC0_G0_0_IRQHandler 
381 | VADC0_G0_1_IRQHandler 
382 | VADC0_G0_2_IRQHandler 
383 | VADC0_G0_3_IRQHandler 
384 | VADC0_G1_0_IRQHandler 
385 | VADC0_G1_1_IRQHandler 
386 | VADC0_G1_2_IRQHandler 
387 | VADC0_G1_3_IRQHandler 
388 | VADC0_G2_0_IRQHandler 
389 | VADC0_G2_1_IRQHandler 
390 | VADC0_G2_2_IRQHandler 
391 | VADC0_G2_3_IRQHandler 
392 | VADC0_G3_0_IRQHandler 
393 | VADC0_G3_1_IRQHandler 
394 | VADC0_G3_2_IRQHandler 
395 | VADC0_G3_3_IRQHandler 
396 | DSD0_0_IRQHandler 
397 | DSD0_1_IRQHandler 
398 | DSD0_2_IRQHandler 
399 | DSD0_3_IRQHandler 
400 | DSD0_4_IRQHandler 
401 | DSD0_5_IRQHandler 
402 | DSD0_6_IRQHandler 
403 | DSD0_7_IRQHandler 
404 | DAC0_0_IRQHandler 
405 | DAC0_1_IRQHandler 
406 | CCU40_0_IRQHandler
407 | CCU40_1_IRQHandler
408 | CCU40_2_IRQHandler
409 | CCU40_3_IRQHandler
410 | CCU41_0_IRQHandler
411 | CCU41_1_IRQHandler
412 | CCU41_2_IRQHandler
413 | CCU41_3_IRQHandler
414 | CCU42_0_IRQHandler
415 | CCU42_1_IRQHandler
416 | CCU42_2_IRQHandler
417 | CCU42_3_IRQHandler
418 | CCU43_0_IRQHandler
419 | CCU43_1_IRQHandler
420 | CCU43_2_IRQHandler
421 | CCU43_3_IRQHandler
422 | CCU80_0_IRQHandler
423 | CCU80_1_IRQHandler
424 | CCU80_2_IRQHandler
425 | CCU80_3_IRQHandler
426 | CCU81_0_IRQHandler
427 | CCU81_1_IRQHandler
428 | CCU81_2_IRQHandler
429 | CCU81_3_IRQHandler
430 | POSIF0_0_IRQHandler 
431 | POSIF0_1_IRQHandler 
432 | POSIF1_0_IRQHandler 
433 | POSIF1_1_IRQHandler 
434 | HRPWM_0_IRQHandler
435 | HRPWM_1_IRQHandler
436 | HRPWM_2_IRQHandler
437 | HRPWM_3_IRQHandler
438 | CAN0_0_IRQHandler 
439 | CAN0_1_IRQHandler 
440 | CAN0_2_IRQHandler 
441 | CAN0_3_IRQHandler 
442 | CAN0_4_IRQHandler 
443 | CAN0_5_IRQHandler 
444 | CAN0_6_IRQHandler 
445 | CAN0_7_IRQHandler 
446 | USIC0_0_IRQHandler
447 | USIC0_1_IRQHandler
448 | USIC0_2_IRQHandler
449 | USIC0_3_IRQHandler
450 | USIC0_4_IRQHandler
451 | USIC0_5_IRQHandler
452 | USIC1_0_IRQHandler
453 | USIC1_1_IRQHandler
454 | USIC1_2_IRQHandler
455 | USIC1_3_IRQHandler
456 | USIC1_4_IRQHandler
457 | USIC1_5_IRQHandler
458 | LEDTS0_0_IRQHandler 
459 | FCE0_0_IRQHandler 
460 | GPDMA0_0_IRQHandler 
461 | USB0_0_IRQHandler 
462 | ETH0_0_IRQHandler 
463 | 
464 |                 B       .
465 | 
466 |                 ENDP
467 | 
468 |                 IF     :DEF:ENABLE_PMU_CM_001_WORKAROUND
469 | 
470 |                 MACRO
471 |                 Insert_ExceptionHandlerVeneer $Handler_Func                    
472 | $Handler_Func._Veneer\
473 |                     PROC
474 |                     EXPORT  $Handler_Func._Veneer [WEAK]
475 |                     LDR     R0, =$Handler_Func
476 |                     PUSH    {LR}  ;/* Breaks AAPCS */
477 |                     SUB     SP,#4     ;/* Restores AAPCS */
478 |                     BLX     R0
479 |                     ADD     SP,#4
480 |                     POP     {PC}
481 |                     ALIGN
482 |                     LTORG
483 |                     ENDP
484 |                 MEND
485 |                 
486 |                 Insert_ExceptionHandlerVeneer  NMI_Handler
487 |                 Insert_ExceptionHandlerVeneer  HardFault_Handler
488 |                 Insert_ExceptionHandlerVeneer  MemManage_Handler
489 |                 Insert_ExceptionHandlerVeneer  BusFault_Handler 
490 |                 Insert_ExceptionHandlerVeneer  UsageFault_Handler
491 |                 Insert_ExceptionHandlerVeneer  SVC_Handler
492 |                 Insert_ExceptionHandlerVeneer  DebugMon_Handler
493 |                 Insert_ExceptionHandlerVeneer  PendSV_Handler
494 |                 Insert_ExceptionHandlerVeneer SysTick_Handler
495 | 
496 |                 Insert_ExceptionHandlerVeneer  SCU_0_IRQHandler
497 |                 Insert_ExceptionHandlerVeneer  ERU0_0_IRQHandler
498 |                 Insert_ExceptionHandlerVeneer  ERU0_1_IRQHandler
499 |                 Insert_ExceptionHandlerVeneer  ERU0_2_IRQHandler
500 |                 Insert_ExceptionHandlerVeneer  ERU0_3_IRQHandler
501 |                 Insert_ExceptionHandlerVeneer  ERU1_0_IRQHandler
502 |                 Insert_ExceptionHandlerVeneer  ERU1_1_IRQHandler
503 |                 Insert_ExceptionHandlerVeneer  ERU1_2_IRQHandler
504 |                 Insert_ExceptionHandlerVeneer  ERU1_3_IRQHandler
505 |                 Insert_ExceptionHandlerVeneer  PMU0_0_IRQHandler
506 |                 Insert_ExceptionHandlerVeneer  VADC0_C0_0_IRQHandler   
507 |                 Insert_ExceptionHandlerVeneer  VADC0_C0_1_IRQHandler   
508 |                 Insert_ExceptionHandlerVeneer  VADC0_C0_2_IRQHandler   
509 |                 Insert_ExceptionHandlerVeneer  VADC0_C0_3_IRQHandler   
510 |                 Insert_ExceptionHandlerVeneer  VADC0_G0_0_IRQHandler   
511 |                 Insert_ExceptionHandlerVeneer  VADC0_G0_1_IRQHandler   
512 |                 Insert_ExceptionHandlerVeneer  VADC0_G0_2_IRQHandler   
513 |                 Insert_ExceptionHandlerVeneer  VADC0_G0_3_IRQHandler   
514 |                 Insert_ExceptionHandlerVeneer  VADC0_G1_0_IRQHandler   
515 |                 Insert_ExceptionHandlerVeneer  VADC0_G1_1_IRQHandler   
516 |                 Insert_ExceptionHandlerVeneer  VADC0_G1_2_IRQHandler   
517 |                 Insert_ExceptionHandlerVeneer  VADC0_G1_3_IRQHandler   
518 |                 Insert_ExceptionHandlerVeneer  VADC0_G2_0_IRQHandler   
519 |                 Insert_ExceptionHandlerVeneer  VADC0_G2_1_IRQHandler   
520 |                 Insert_ExceptionHandlerVeneer  VADC0_G2_2_IRQHandler   
521 |                 Insert_ExceptionHandlerVeneer  VADC0_G2_3_IRQHandler   
522 |                 Insert_ExceptionHandlerVeneer  VADC0_G3_0_IRQHandler   
523 |                 Insert_ExceptionHandlerVeneer  VADC0_G3_1_IRQHandler   
524 |                 Insert_ExceptionHandlerVeneer  VADC0_G3_2_IRQHandler   
525 |                 Insert_ExceptionHandlerVeneer  VADC0_G3_3_IRQHandler   
526 |                 Insert_ExceptionHandlerVeneer  DSD0_0_IRQHandler       
527 |                 Insert_ExceptionHandlerVeneer  DSD0_1_IRQHandler       
528 |                 Insert_ExceptionHandlerVeneer  DSD0_2_IRQHandler       
529 |                 Insert_ExceptionHandlerVeneer  DSD0_3_IRQHandler       
530 |                 Insert_ExceptionHandlerVeneer  DSD0_4_IRQHandler       
531 |                 Insert_ExceptionHandlerVeneer  DSD0_5_IRQHandler       
532 |                 Insert_ExceptionHandlerVeneer  DSD0_6_IRQHandler       
533 |                 Insert_ExceptionHandlerVeneer  DSD0_7_IRQHandler       
534 |                 Insert_ExceptionHandlerVeneer  DAC0_0_IRQHandler       
535 |                 Insert_ExceptionHandlerVeneer  DAC0_1_IRQHandler       
536 |                 Insert_ExceptionHandlerVeneer  CCU40_0_IRQHandler      
537 |                 Insert_ExceptionHandlerVeneer  CCU40_1_IRQHandler      
538 |                 Insert_ExceptionHandlerVeneer  CCU40_2_IRQHandler      
539 |                 Insert_ExceptionHandlerVeneer  CCU40_3_IRQHandler      
540 |                 Insert_ExceptionHandlerVeneer  CCU41_0_IRQHandler      
541 |                 Insert_ExceptionHandlerVeneer  CCU41_1_IRQHandler      
542 |                 Insert_ExceptionHandlerVeneer  CCU41_2_IRQHandler      
543 |                 Insert_ExceptionHandlerVeneer  CCU41_3_IRQHandler      
544 |                 Insert_ExceptionHandlerVeneer  CCU42_0_IRQHandler      
545 |                 Insert_ExceptionHandlerVeneer  CCU42_1_IRQHandler      
546 |                 Insert_ExceptionHandlerVeneer  CCU42_2_IRQHandler      
547 |                 Insert_ExceptionHandlerVeneer  CCU42_3_IRQHandler      
548 |                 Insert_ExceptionHandlerVeneer  CCU43_0_IRQHandler      
549 |                 Insert_ExceptionHandlerVeneer  CCU43_1_IRQHandler      
550 |                 Insert_ExceptionHandlerVeneer  CCU43_2_IRQHandler      
551 |                 Insert_ExceptionHandlerVeneer  CCU43_3_IRQHandler      
552 |                 Insert_ExceptionHandlerVeneer  CCU80_0_IRQHandler      
553 |                 Insert_ExceptionHandlerVeneer  CCU80_1_IRQHandler      
554 |                 Insert_ExceptionHandlerVeneer  CCU80_2_IRQHandler      
555 |                 Insert_ExceptionHandlerVeneer  CCU80_3_IRQHandler      
556 |                 Insert_ExceptionHandlerVeneer  CCU81_0_IRQHandler      
557 |                 Insert_ExceptionHandlerVeneer  CCU81_1_IRQHandler      
558 |                 Insert_ExceptionHandlerVeneer  CCU81_2_IRQHandler      
559 |                 Insert_ExceptionHandlerVeneer  CCU81_3_IRQHandler      
560 |                 Insert_ExceptionHandlerVeneer  POSIF0_0_IRQHandler     
561 |                 Insert_ExceptionHandlerVeneer  POSIF0_1_IRQHandler     
562 |                 Insert_ExceptionHandlerVeneer  POSIF1_0_IRQHandler     
563 |                 Insert_ExceptionHandlerVeneer  POSIF1_1_IRQHandler     
564 |                 Insert_ExceptionHandlerVeneer  HRPWM_0_IRQHandler      
565 |                 Insert_ExceptionHandlerVeneer  HRPWM_1_IRQHandler      
566 |                 Insert_ExceptionHandlerVeneer  HRPWM_2_IRQHandler      
567 |                 Insert_ExceptionHandlerVeneer  HRPWM_3_IRQHandler      
568 |                 Insert_ExceptionHandlerVeneer  CAN0_0_IRQHandler       
569 |                 Insert_ExceptionHandlerVeneer  CAN0_1_IRQHandler       
570 |                 Insert_ExceptionHandlerVeneer  CAN0_2_IRQHandler       
571 |                 Insert_ExceptionHandlerVeneer  CAN0_3_IRQHandler       
572 |                 Insert_ExceptionHandlerVeneer  CAN0_4_IRQHandler       
573 |                 Insert_ExceptionHandlerVeneer  CAN0_5_IRQHandler       
574 |                 Insert_ExceptionHandlerVeneer  CAN0_6_IRQHandler       
575 |                 Insert_ExceptionHandlerVeneer  CAN0_7_IRQHandler       
576 |                 Insert_ExceptionHandlerVeneer  USIC0_0_IRQHandler      
577 |                 Insert_ExceptionHandlerVeneer  USIC0_1_IRQHandler      
578 |                 Insert_ExceptionHandlerVeneer  USIC0_2_IRQHandler      
579 |                 Insert_ExceptionHandlerVeneer  USIC0_3_IRQHandler      
580 |                 Insert_ExceptionHandlerVeneer  USIC0_4_IRQHandler      
581 |                 Insert_ExceptionHandlerVeneer  USIC0_5_IRQHandler      
582 |                 Insert_ExceptionHandlerVeneer  USIC1_0_IRQHandler      
583 |                 Insert_ExceptionHandlerVeneer  USIC1_1_IRQHandler      
584 |                 Insert_ExceptionHandlerVeneer  USIC1_2_IRQHandler      
585 |                 Insert_ExceptionHandlerVeneer  USIC1_3_IRQHandler      
586 |                 Insert_ExceptionHandlerVeneer  USIC1_4_IRQHandler      
587 |                 Insert_ExceptionHandlerVeneer  USIC1_5_IRQHandler      
588 |                 Insert_ExceptionHandlerVeneer  LEDTS0_0_IRQHandler     
589 |                 Insert_ExceptionHandlerVeneer  FCE0_0_IRQHandler       
590 |                 Insert_ExceptionHandlerVeneer  GPDMA0_0_IRQHandler     
591 |                 Insert_ExceptionHandlerVeneer  USB0_0_IRQHandler       
592 |                 Insert_ExceptionHandlerVeneer  ETH0_0_IRQHandler       
593 |                 ENDIF
594 |                 
595 |                 ALIGN
596 | 
597 | ; User Initial Stack & Heap
598 | 
599 |                 IF      :DEF:__MICROLIB
600 | 
601 |                 EXPORT  __initial_sp
602 |                 EXPORT  __heap_base
603 |                 EXPORT  __heap_limit
604 | 
605 |                 ELSE
606 | 
607 |                 IMPORT  __use_two_region_memory
608 |                 EXPORT  __user_initial_stackheap
609 | __user_initial_stackheap
610 | 
611 |                 LDR     R0, =  Heap_Mem
612 |                 LDR     R1, =(Stack_Mem + Stack_Size)
613 |                 LDR     R2, = (Heap_Mem +  Heap_Size)
614 |                 LDR     R3, = Stack_Mem
615 |                 BX      LR
616 | 
617 |                 ALIGN
618 | 
619 |                 ENDIF
620 | 
621 | 
622 |                 END
623 | 


--------------------------------------------------------------------------------
/RTE/Device/XMC4400-F100x512/system_XMC4400.c:
--------------------------------------------------------------------------------
  1 | /*********************************************************************************************************************
  2 |  * @file     system_XMC4400.c
  3 |  * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4400 Device Series
  4 |  * @version  V3.1.3
  5 |  * @date     26. Sep 2017
  6 |  *
  7 |  * @cond
  8 |  *********************************************************************************************************************
  9 |  * Copyright (c) 2014-2017, Infineon Technologies AG
 10 |  * All rights reserved.
 11 |  *
 12 |  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
 13 |  * following conditions are met:
 14 |  *
 15 |  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
 16 |  * disclaimer.
 17 |  *
 18 |  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
 19 |  * disclaimer in the documentation and/or other materials provided with the distribution.
 20 |  *
 21 |  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
 22 |  * products derived from this software without specific prior written permission.
 23 |  *
 24 |  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 25 |  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 26 |  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 27 |  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 28 |  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 29 |  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 30 |  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 31 |  *
 32 |  * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
 33 |  * Infineon Technologies AG dave@infineon.com).
 34 |  *********************************************************************************************************************
 35 |  *
 36 |  ********************** Version History ***************************************
 37 |  * V3.1.0, Dec 2014, Added options to configure clock settings
 38 |  * V3.1.1, 01. Jun 2016, Fix masking of OSCHPCTRL value 
 39 |  * V3.1.2, 19. Jun 2017, Rely on cmsis_compiler.h instead of defining __WEAK 
 40 |  *                       Added support for ARM Compiler 6 (armclang) 
 41 |  * V3.1.3, 26. Sep 2017, Disable FPU if FPU_USED is zero  
 42 |  ******************************************************************************
 43 |  * @endcond
 44 |  */
 45 | 
 46 | /*******************************************************************************
 47 |  * HEADER FILES
 48 |  *******************************************************************************/
 49 | #include <string.h>
 50 | 
 51 | #include <XMC4400.h>
 52 | #include "system_XMC4400.h"
 53 | 
 54 | /*******************************************************************************
 55 |  * MACROS
 56 |  *******************************************************************************/
 57 | #define CHIPID_LOC ((uint8_t *)0x20000000UL)
 58 | #define HRPWM_CHARDATA_LOC ((uint8_t *)0x20000084UL)
 59 | 
 60 | #define PMU_FLASH_WS          (0x3U)
 61 | 
 62 | #define FPLL_FREQUENCY        (120000000U)
 63 | #define FOSCREF               (2500000U)
 64 | #define DELAY_CNT_50US_50MHZ  (2500UL)
 65 | #define DELAY_CNT_150US_50MHZ (7500UL)
 66 | #define DELAY_CNT_50US_60MHZ  (3000UL)
 67 | #define DELAY_CNT_50US_90MHZ  (4500UL)
 68 | #define DELAY_CNT_50US_120MHZ (6000UL)
 69 | 
 70 | #define SCU_PLL_PLLSTAT_OSC_USABLE  (SCU_PLL_PLLSTAT_PLLHV_Msk | \
 71 |                                      SCU_PLL_PLLSTAT_PLLLV_Msk | \
 72 |                                      SCU_PLL_PLLSTAT_PLLSP_Msk)
 73 | 
 74 | /*
 75 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
 76 | */
 77 | 
 78 | /*
 79 | // <h> Clock configuration
 80 | */
 81 | 
 82 | /*
 83 | //    <o> External crystal frequency [Hz]
 84 | //       <8000000=> 8MHz
 85 | //       <12000000=> 12MHz
 86 | //       <16000000=> 16MHz
 87 | //    <i> Defines external crystal frequency
 88 | //    <i> Default: 8MHz
 89 | */
 90 | #define OSCHP_FREQUENCY (12000000U)
 91 | 
 92 | #if OSCHP_FREQUENCY == 8000000U
 93 | #define USB_PDIV (1U)
 94 | #define USB_NDIV (95U)
 95 | #define USB_DIV (3U)
 96 | 
 97 | #elif OSCHP_FREQUENCY == 12000000U
 98 | #define USB_PDIV (1U)
 99 | #define USB_NDIV (63U)
100 | #define USB_DIV (3U)
101 | 
102 | #elif OSCHP_FREQUENCY == 16000000U
103 | #define USB_PDIV (1U)
104 | #define USB_NDIV (47U)
105 | #define USB_DIV (3U)
106 | 
107 | #else
108 | #error "External crystal frequency not supported"
109 | 
110 | #endif
111 | 
112 | /*
113 | //    <o> System clock (fSYS) source selection
114 | //       <0=> Backup clock (24MHz)
115 | //       <1=> Maximum clock frequency using PLL (120MHz)
116 | //    <i> Default: Maximum clock frequency using PLL (120MHz)
117 | */
118 | #define SYS_CLOCK_SRC 1
119 | #define SYS_CLOCK_SRC_OFI 0
120 | #define SYS_CLOCK_SRC_PLL 1
121 | 
122 | /*
123 | //    <o> Backup clock calibration mode
124 | //       <0=> Factory calibration
125 | //       <1=> Automatic calibration
126 | //    <i> Default: Automatic calibration
127 | */
128 | #define FOFI_CALIBRATION_MODE 1
129 | #define FOFI_CALIBRATION_MODE_FACTORY 0
130 | #define FOFI_CALIBRATION_MODE_AUTOMATIC 1
131 | 
132 | /*
133 | //    <o> Standby clock (fSTDBY) source selection
134 | //       <0=> Internal slow oscillator (32768Hz)
135 | //       <1=> External crystal (32768Hz)
136 | //    <i> Default: Internal slow oscillator (32768Hz)
137 | */
138 | #define STDBY_CLOCK_SRC 0
139 | #define STDBY_CLOCK_SRC_OSI 0
140 | #define STDBY_CLOCK_SRC_OSCULP 1
141 | 
142 | /*
143 | //    <o> PLL clock source selection
144 | //       <0=> External crystal
145 | //       <1=> External direct input
146 | //       <2=> Internal fast oscillator
147 | //    <i> Default: External crystal
148 | */
149 | #define PLL_CLOCK_SRC 0
150 | #define PLL_CLOCK_SRC_EXT_XTAL 0
151 | #define PLL_CLOCK_SRC_EXT_DIRECT 1
152 | #define PLL_CLOCK_SRC_OFI 2
153 | 
154 | #if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL
155 | #if OSCHP_FREQUENCY == 8000000U
156 | #define PLL_PDIV (1U)
157 | #define PLL_NDIV (89U)
158 | #define PLL_K2DIV (2U)
159 | 
160 | #elif OSCHP_FREQUENCY == 12000000U
161 | #define PLL_PDIV (1U)
162 | #define PLL_NDIV (79U)
163 | #define PLL_K2DIV (3U)
164 | 
165 | #elif OSCHP_FREQUENCY == 16000000U
166 | #define PLL_PDIV (1U)
167 | #define PLL_NDIV (59U)
168 | #define PLL_K2DIV (3U)
169 | 
170 | #else
171 | #error "External crystal frequency not supported"
172 | 
173 | #endif
174 | 
175 | #define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
176 | 
177 | #else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */
178 | 
179 | #define PLL_PDIV (1U)
180 | #define PLL_NDIV (39U)
181 | #define PLL_K2DIV (3U)
182 | 
183 | #define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
184 | 
185 | #endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */
186 | 
187 | #define PLL_K2DIV_0 ((VCO / OFI_FREQUENCY) - 1UL)
188 | #define PLL_K2DIV_1 ((VCO / 60000000U) - 1UL)
189 | #define PLL_K2DIV_2 ((VCO / 90000000U) - 1UL)
190 | 
191 | #define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk
192 | #define SCU_CLK_CLKCLR_ENABLE_ETHCLK SCU_CLK_CLKCLR_ETH0CDI_Msk
193 | #define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk
194 | #define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk
195 | 
196 | #define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos)
197 | #define SCU_CLK_USBCLKCR_USBSEL_PLL    (1U << SCU_CLK_USBCLKCR_USBSEL_Pos)
198 | 
199 | #define SCU_CLK_WDTCLKCR_WDTSEL_OFI      (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
200 | #define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY  (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
201 | #define SCU_CLK_WDTCLKCR_WDTSEL_PLL      (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
202 | 
203 | #define SCU_CLK_EXTCLKCR_ECKSEL_SYS      (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
204 | #define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL   (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
205 | #define SCU_CLK_EXTCLKCR_ECKSEL_PLL      (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
206 | #define SCU_CLK_EXTCLKCR_ECKSEL_STANDBY  (4U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
207 | 
208 | #define EXTCLK_PIN_P0_8  (0)
209 | #define EXTCLK_PIN_P1_15 (1)
210 | 
211 | /*
212 | //    <h> Clock tree
213 | //        <o1.0> CPU clock divider
214 | //                   <0=> fCPU = fSYS
215 | //                   <1=> fCPU = fSYS / 2
216 | //        <o2.0>  Peripheral clock divider
217 | //                     <0=> fPB	= fCPU
218 | //                     <1=> fPB	= fCPU / 2
219 | //        <e.4> Enable CCU clock
220 | //             <o3.0>  CCU clock divider
221 | //                     <0=> fCCU = fCPU
222 | //                     <1=> fCCU = fCPU / 2
223 | //        </e>
224 | //        <e.5> Enable WDT clock
225 | //             <o4.0..7>  WDT clock divider <1-256><#-1>
226 | //             <o4.16..17> WDT clock source <0=> fOFI
227 | //                                          <1=> fSTDBY
228 | //                                          <2=> fPLL
229 | //        </e>
230 | //        <e.2> Enable ETH clock
231 | //        </e>
232 | //        <e.0> Enable USB clock
233 | //             <o5.16> USB clock source <0=> USBPLL
234 | //                                      <1=> PLL
235 | //        </e>
236 | //        <e6> External Clock configuration
237 | //            <o7.0..2> External clock source selection
238 | //                  <0=> System clock
239 | //                  <2=> USB PLL clock
240 | //                  <3=> PLL clock
241 | //                  <4=> Standby clock
242 | //            <o7.16..24> External clock divider <1-512><#-1>
243 | //            <i> Only valid for USB PLL and PLL clocks
244 | //            <o8.0> External Pin Selection
245 | //                  <0=> P0.8
246 | //                  <1=> P1.15
247 | //        </e>
248 | //    </h>
249 | */
250 | #define ENABLE_SCUCLK (0U)
251 | #define CPUCLKDIV (0U)
252 | #define PBCLKDIV (0U)
253 | #define CCUCLKDIV (0U)
254 | #define WDTCLKDIV (0U | SCU_CLK_WDTCLKCR_WDTSEL_OFI)
255 | #define USBCLKDIV (0U | SCU_CLK_USBCLKCR_USBSEL_USBPLL | USB_DIV)
256 | 
257 | #define ENABLE_EXTCLK (0U)
258 | #define EXTCLKDIV (0U | SCU_CLK_EXTCLKCR_ECKSEL_SYS)
259 | #define EXTCLK_PIN (0U)
260 | 
261 | #define ENABLE_PLL \
262 |     (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) || \
263 |     (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \
264 |     (((ENABLE_SCUCLK & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((WDTCLKDIV & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL))
265 | 
266 | /*
267 | // </h>
268 | */
269 | 
270 | /*
271 | //-------- <<< end of configuration section >>> ------------------
272 | */
273 | 
274 | /*******************************************************************************
275 |  * GLOBAL VARIABLES
276 |  *******************************************************************************/
277 | #if defined ( __CC_ARM )
278 | uint32_t SystemCoreClock __attribute__((at(0x2000FFC0)));
279 | uint8_t g_chipid[16] __attribute__((at(0x2000FFC4)));
280 | uint32_t g_hrpwm_char_data[3] __attribute__((at(0x2000FFD4)));
281 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
282 | uint32_t SystemCoreClock __attribute__((section(".ARM.__at_0x2000FFC0")));
283 | uint8_t g_chipid[16] __attribute__((section(".ARM.__at_0x2000FFC4")));
284 | uint32_t g_hrpwm_char_data[3] __attribute__((section(".ARM.__at_0x2000FFD4")));
285 | #elif defined ( __ICCARM__ )
286 | __no_init uint32_t SystemCoreClock;
287 | __no_init uint8_t g_chipid[16];
288 | __no_init uint32_t g_hrpwm_char_data[3];
289 | #elif defined ( __GNUC__ )
290 | uint32_t SystemCoreClock __attribute__((section(".no_init")));
291 | uint8_t g_chipid[16] __attribute__((section(".no_init")));
292 | uint32_t g_hrpwm_char_data[3] __attribute__((section(".no_init")));
293 | #elif defined ( __TASKING__ )
294 | uint32_t SystemCoreClock __at( 0x2000FFC0 );
295 | uint8_t g_chipid[16] __at( 0x2000FFC4 );
296 | uint32_t g_hrpwm_char_data[3] __at( 0x2000FFD4 );
297 | #endif
298 | 
299 | extern uint32_t __Vectors;
300 | 
301 | /*******************************************************************************
302 |  * LOCAL FUNCTIONS
303 |  *******************************************************************************/
304 | static void delay(uint32_t cycles)
305 | {
306 |   volatile uint32_t i;
307 | 
308 |   for(i = 0UL; i < cycles ;++i)
309 |   {
310 |     __NOP();
311 |   }
312 | }
313 | 
314 | /*******************************************************************************
315 |  * API IMPLEMENTATION
316 |  *******************************************************************************/
317 | 
318 | __WEAK void SystemInit(void)
319 | {
320 |   memcpy(g_chipid, CHIPID_LOC, 16);
321 |   memcpy(g_hrpwm_char_data, HRPWM_CHARDATA_LOC, 12);
322 | 
323 |   SystemCoreSetup();
324 |   SystemCoreClockSetup(); 
325 | }
326 | 
327 | __WEAK void SystemCoreSetup(void)
328 | {
329 |   uint32_t temp;
330 | 	
331 |   /* relocate vector table */
332 |   __disable_irq();
333 |   SCB->VTOR = (uint32_t)(&__Vectors);
334 |   __DSB();
335 |   __enable_irq();
336 |     
337 |   /* __FPU_PRESENT = 1 defined in device header file */
338 |   /* __FPU_USED value depends on compiler/linker options. */
339 |   /* __FPU_USED = 0 if -mfloat-abi=soft is selected */
340 |   /* __FPU_USED = 1 if -mfloat-abi=softfp or –mfloat-abi=hard */
341 | 
342 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
343 |   SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
344 |                  (3UL << 11*2)  );               /* set CP11 Full Access */
345 | #else
346 |   SCB->CPACR = 0;
347 | #endif
348 | 
349 |   /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
350 |   SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
351 | 
352 |   temp = FLASH0->FCON;
353 |   temp &= ~FLASH_FCON_WSPFLASH_Msk;
354 |   temp |= PMU_FLASH_WS;
355 |   FLASH0->FCON = temp;
356 | }
357 | 
358 | __WEAK void SystemCoreClockSetup(void)
359 | {
360 | #if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY
361 |   /* Enable factory calibration */
362 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk;
363 | #else
364 |   /* Automatic calibration uses the fSTDBY */
365 | 
366 |   /* Enable HIB domain */
367 |   /* Power up HIB domain if and only if it is currently powered down */
368 |   if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
369 |   {
370 |     SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk;
371 | 
372 |     while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
373 |     {
374 |       /* wait until HIB domain is enabled */
375 |     }
376 |   }
377 | 
378 |   /* Remove the reset only if HIB domain were in a state of reset */
379 |   if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk)
380 |   {
381 |     SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk;
382 |     delay(DELAY_CNT_150US_50MHZ);
383 |   }
384 |   
385 | #if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP
386 |   /* Enable OSC_ULP */
387 |   if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL)
388 |   {
389 |     /*enable OSC_ULP*/
390 |     while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk)
391 |     {
392 |       /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
393 |     }
394 |     SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk;
395 | 
396 |     /* Check if the clock is OK using OSCULP Oscillator Watchdog*/
397 |     while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
398 |     {
399 |       /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
400 |     }
401 |     SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
402 | 
403 |     /* wait till clock is stable */
404 |     do
405 |     {
406 |       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk)
407 |       {
408 |         /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
409 |       }
410 |       SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
411 | 
412 |       delay(DELAY_CNT_50US_50MHZ);
413 | 
414 |     } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL);
415 | 
416 |   }
417 | 
418 |   /* now OSC_ULP is running and can be used*/
419 |   /* Select OSC_ULP as the clock source for RTC and STDBY*/
420 |   while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
421 |   {
422 |     /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
423 |   }
424 |   SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
425 | 
426 | #endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */
427 | 
428 |   /* Enable automatic calibration of internal fast oscillator */
429 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
430 | #endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */
431 | 
432 |   delay(DELAY_CNT_50US_50MHZ);
433 | 
434 | #if ENABLE_PLL
435 | 
436 |   /* enable PLL */
437 |   SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
438 | 
439 | #if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI
440 |   /* enable OSC_HP */
441 |   if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
442 |   {
443 |     SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
444 |     SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
445 | 
446 |     /* select OSC_HP clock as PLL input */
447 |     SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
448 | 
449 |     /* restart OSC Watchdog */
450 |     SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
451 | 
452 |     while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
453 |     {
454 |       /* wait till OSC_HP output frequency is usable */
455 |     }
456 |   }
457 | #else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */
458 | 
459 |   /* select backup clock as PLL input */
460 |   SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
461 | #endif
462 | 
463 |   /* Go to bypass the Main PLL */
464 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
465 | 
466 |   /* disconnect Oscillator from PLL */
467 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
468 | 
469 |   /* Setup divider settings for main PLL */
470 |   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
471 |                       (PLL_K2DIV_0 << SCU_PLL_PLLCON1_K2DIV_Pos) |
472 |                       (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
473 | 
474 |   /* Set OSCDISCDIS */
475 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
476 | 
477 |   /* connect Oscillator to PLL */
478 |   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
479 | 
480 |   /* restart PLL Lock detection */
481 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
482 | 
483 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
484 |   {
485 |     /* wait for PLL Lock */
486 |   }
487 | 
488 |   /* Disable bypass- put PLL clock back */
489 |   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
490 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U)
491 |   {
492 |     /* wait for normal mode */
493 |   }
494 | #endif /* ENABLE_PLL */
495 | 
496 | #if (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL)
497 |   /* Switch system clock to PLL */
498 |   SCU_CLK->SYSCLKCR |= SCU_CLK_SYSCLKCR_SYSSEL_Msk;
499 | #else
500 |   /* Switch system clock to backup clock */
501 |   SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk;
502 | #endif
503 | 
504 |   /* Before scaling to final frequency we need to setup the clock dividers */
505 |   SCU_CLK->PBCLKCR = PBCLKDIV;
506 |   SCU_CLK->CPUCLKCR = CPUCLKDIV;
507 |   SCU_CLK->CCUCLKCR = CCUCLKDIV;
508 |   SCU_CLK->WDTCLKCR = WDTCLKDIV;
509 |   SCU_CLK->USBCLKCR = USBCLKDIV;
510 | 
511 | #if ENABLE_PLL
512 |   /* PLL frequency stepping...*/
513 |   /* Reset OSCDISCDIS */
514 |   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
515 | 
516 |   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
517 | 	                    (PLL_K2DIV_1 << SCU_PLL_PLLCON1_K2DIV_Pos) |
518 | 	                    (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
519 | 
520 | 
521 |   delay(DELAY_CNT_50US_60MHZ);
522 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
523 |   {
524 |     /* wait for PLL Lock */
525 |   }
526 | 
527 |   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
528 | 	                    (PLL_K2DIV_2 << SCU_PLL_PLLCON1_K2DIV_Pos) |
529 | 	                    (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
530 | 
531 | 
532 |   delay(DELAY_CNT_50US_90MHZ);
533 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
534 |   {
535 |     /* wait for PLL Lock */
536 |   }
537 | 
538 |   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
539 | 	                    (PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) |
540 | 	                    (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
541 | 
542 | 
543 |   delay(DELAY_CNT_50US_120MHZ);
544 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
545 |   {
546 |     /* wait for PLL Lock */
547 |   }
548 | 
549 |   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
550 | #endif /* ENABLE_PLL */
551 | 
552 | #if (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL))
553 |   /* enable USB PLL first */
554 |   SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
555 | 
556 |   /* USB PLL uses as clock input the OSC_HP */
557 |   /* check and if not already running enable OSC_HP */
558 |   if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
559 |   {
560 |     /* check if Main PLL is switched on for OSC WDG*/
561 |     if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL)
562 |     {
563 |       /* enable PLL first */
564 |       SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
565 |     }
566 | 
567 |     SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
568 |     SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
569 | 
570 |     /* restart OSC Watchdog */
571 |     SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
572 | 
573 |     while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
574 |     {
575 |       /* wait till OSC_HP output frequency is usable */
576 |     }
577 |   }
578 | 
579 |   /* Setup USB PLL */
580 |   /* Go to bypass the USB PLL */
581 |   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
582 | 
583 |   /* disconnect Oscillator from USB PLL */
584 |   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
585 | 
586 |   /* Setup Divider settings for USB PLL */
587 |   SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) |
588 |                         (USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos));
589 | 
590 |   /* Set OSCDISCDIS */
591 |   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
592 | 
593 |   /* connect Oscillator to USB PLL */
594 |   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
595 | 
596 |   /* restart PLL Lock detection */
597 |   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
598 | 
599 |   while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U)
600 |   {
601 |     /* wait for PLL Lock */
602 |   }
603 | #endif /* (USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) */
604 | 
605 |   /* Enable selected clocks */
606 |   SCU_CLK->CLKSET = ENABLE_SCUCLK;
607 | 
608 | #if ENABLE_EXTCLK == 1
609 |   /* Configure external clock */
610 |   SCU_CLK->EXTCLKCR = EXTCLKDIV;
611 | 
612 | #if EXTCLK_PIN == EXTCLK_PIN_P1_15
613 |   /* P1.15 */
614 |   PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk;
615 |   PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos);
616 | #else
617 |   /* P0.8 */
618 |   PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk;
619 |   PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk;
620 |   PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos);
621 | #endif
622 | 
623 | #endif  /* ENABLE_EXTCLK == 1  */
624 | 
625 |   SystemCoreClockUpdate();
626 | }
627 | 
628 | __WEAK void SystemCoreClockUpdate(void)
629 | {
630 |   uint32_t pdiv;
631 |   uint32_t ndiv;
632 |   uint32_t kdiv;
633 |   uint32_t temp;
634 | 
635 |   if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk)
636 |   {
637 |     /* fPLL is clock source for fSYS */
638 |     if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk)
639 |     {
640 |       /* PLL input clock is the backup clock (fOFI) */
641 |       temp = OFI_FREQUENCY;
642 |     }
643 |     else
644 |     {
645 |       /* PLL input clock is the high performance osicllator (fOSCHP) */
646 |       temp = OSCHP_GetFrequency();
647 |     }
648 | 
649 |     /* check if PLL is locked */
650 |     if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)
651 |     {
652 |       /* PLL normal mode */
653 |       /* read back divider settings */
654 |       pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1;
655 |       ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1;
656 |       kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1;
657 | 
658 |       temp = (temp / (pdiv * kdiv)) * ndiv;
659 |     }
660 |     else
661 |     {
662 |       /* PLL prescalar mode */
663 |       /* read back divider settings */
664 |       kdiv  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1;
665 |       
666 |       temp = (temp / kdiv);
667 |     }
668 |   }
669 |   else
670 |   {
671 |     /* fOFI is clock source for fSYS */    
672 |     temp = OFI_FREQUENCY;
673 |   }
674 | 
675 |   temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1);
676 |   temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1);
677 | 
678 |   SystemCoreClock = temp;
679 | }
680 | 
681 | __WEAK uint32_t OSCHP_GetFrequency(void)
682 | {
683 |   return OSCHP_FREQUENCY;
684 | }
685 | 


--------------------------------------------------------------------------------
/RTE/Device/XMC4400-F64x512/startup_XMC4400.s:
--------------------------------------------------------------------------------
  1 | ;*******************************************************************************
  2 | ;* @file     startup_XMC4400.s
  3 | ;* @brief    CMSIS Core Device Startup File for
  4 | ;*           Infineon XMC4400 Device Series
  5 | ;* @version  V1.5
  6 | ;* @date     June 2016
  7 | ;*
  8 | ;* @cond
  9 | ;*********************************************************************************************************************
 10 | ;* Copyright (c) 2012-2016, Infineon Technologies AG
 11 | ;* All rights reserved.                        
 12 | ;*                                             
 13 | ;* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
 14 | ;* following conditions are met:   
 15 | ;*                                                                              
 16 | ;* Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
 17 | ;* disclaimer.                        
 18 | ;* 
 19 | ;* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
 20 | ;* disclaimer in the documentation and/or other materials provided with the distribution.                       
 21 | ;* 
 22 | ;* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
 23 | ;* products derived from this software without specific prior written permission.                                           
 24 | ;*                                                                              
 25 | ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
 26 | ;* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
 27 | ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 28 | ;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
 29 | ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
 30 | ;* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 31 | ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
 32 | ;*                                                                              
 33 | ;* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
 34 | ;* Infineon Technologies AG dave@infineon.com).                                                          
 35 | ;*********************************************************************************************************************
 36 | ;*
 37 | ;************************** Version History ************************************
 38 | ; V0.2, August 2012, First version
 39 | ; V1.0, February 2013, FIX for CPU prefetch bug implemented
 40 | ; V1.1, August 2013, Fix the bug of stack pointer alignment to a 8 byte boundary
 41 | ; V1.2, November 2014, Disable CPU workaround. Increased stack size.
 42 | ;                       Removed DAVE3 dependency
 43 | ; V1.3, November 2015, Remove peripherals not included in device.
 44 | ; V1.4, March    2016, Fix weak definition of Veneers.
 45 | ;                       Only relevant for AA, which needs ENABLE_PMU_CM_001_WORKAROUND 
 46 | ; V1.5, June     2016, Rename ENABLE_CPU_CM_001_WORKAROUND to ENABLE_PMU_CM_001_WORKAROUND
 47 | ;                      Action required: If using AA step, use ENABLE_PMU_CM_001_WORKAROUND instead of ENABLE_CPU_CM_001_WORKAROUND
 48 | ;*******************************************************************************
 49 | ;* @endcond
 50 | 
 51 | ; ------------------ <<< Use Configuration Wizard in Context Menu >>> ------------------
 52 |            
 53 | ; <h> Stack Configuration
 54 | ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 55 | ; </h>
 56 | 
 57 | Stack_Size      EQU     0x00000800
 58 | 
 59 |                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 60 | Stack_Mem       SPACE   Stack_Size
 61 | __initial_sp
 62 | 
 63 | 
 64 | ; <h> Heap Configuration
 65 | ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 66 | ; </h>
 67 | 
 68 | Heap_Size       EQU     0x00000200
 69 | 
 70 |                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 71 | __heap_base
 72 | Heap_Mem        SPACE   Heap_Size
 73 | __heap_limit
 74 | 
 75 |                 PRESERVE8
 76 |                 THUMB
 77 | 
 78 |                 IF    :DEF:ENABLE_PMU_CM_001_WORKAROUND
 79 |                     MACRO
 80 |                     Entry $Handler
 81 |                     DCD   $Handler._Veneer
 82 |                     MEND
 83 |                 ELSE
 84 |                     MACRO
 85 |                     Entry $Handler
 86 |                     DCD   $Handler
 87 |                     MEND
 88 |                 ENDIF
 89 | 
 90 | ; Vector Table Mapped to Address 0 at Reset
 91 | 
 92 |                 AREA    RESET, DATA, READONLY
 93 |                 EXPORT  __Vectors
 94 |                 EXPORT  __Vectors_End
 95 |                 EXPORT  __Vectors_Size
 96 |                
 97 | __Vectors       DCD     __initial_sp              ; 0 Top of Stack
 98 |                 DCD     Reset_Handler             ; 1 Reset Handler
 99 |                 Entry   NMI_Handler               ; 2 NMI Handler
100 |                 Entry   HardFault_Handler         ; 3 Hard Fault Handler
101 |                 Entry   MemManage_Handler         ; 4 MPU Fault Handler
102 |                 Entry   BusFault_Handler          ; 5 Bus Fault Handler
103 |                 Entry   UsageFault_Handler        ; 6 Usage Fault Handler
104 |                 DCD     0                         ; 7 Reserved
105 |                 DCD     0                         ; 8 Reserved
106 |                 DCD     0                         ; 9 Reserved
107 |                 DCD     0                         ; 10 Reserved
108 |                 Entry   SVC_Handler               ; 11 SVCall Handler
109 |                 Entry   DebugMon_Handler          ; 12 Debug Monitor Handler
110 |                 DCD     0                         ; 13 Reserved
111 |                 Entry   PendSV_Handler            ; 14 PendSV Handler
112 |                 Entry   SysTick_Handler           ; 15 SysTick Handler
113 | 
114 | ; Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals */
115 |                 Entry   SCU_0_IRQHandler          ; Handler name for SR SCU_0     
116 |                 Entry   ERU0_0_IRQHandler         ; Handler name for SR ERU0_0    
117 |                 Entry   ERU0_1_IRQHandler         ; Handler name for SR ERU0_1    
118 |                 Entry   ERU0_2_IRQHandler         ; Handler name for SR ERU0_2    
119 |                 Entry   ERU0_3_IRQHandler         ; Handler name for SR ERU0_3     
120 |                 Entry   ERU1_0_IRQHandler         ; Handler name for SR ERU1_0    
121 |                 Entry   ERU1_1_IRQHandler         ; Handler name for SR ERU1_1    
122 |                 Entry   ERU1_2_IRQHandler         ; Handler name for SR ERU1_2    
123 |                 Entry   ERU1_3_IRQHandler         ; Handler name for SR ERU1_3    
124 |                 DCD     0                         ; Not Available                 
125 |                 DCD     0                         ; Not Available                 
126 |                 DCD     0                         ; Not Available                 
127 |                 Entry   PMU0_0_IRQHandler         ; Handler name for SR PMU0_0    
128 |                 DCD     0                         ; Not Available                 
129 |                 Entry   VADC0_C0_0_IRQHandler     ; Handler name for SR VADC0_C0_0  
130 |                 Entry   VADC0_C0_1_IRQHandler     ; Handler name for SR VADC0_C0_1  
131 |                 Entry   VADC0_C0_2_IRQHandler     ; Handler name for SR VADC0_C0_1  
132 |                 Entry   VADC0_C0_3_IRQHandler     ; Handler name for SR VADC0_C0_3  
133 |                 Entry   VADC0_G0_0_IRQHandler     ; Handler name for SR VADC0_G0_0  
134 |                 Entry   VADC0_G0_1_IRQHandler     ; Handler name for SR VADC0_G0_1  
135 |                 Entry   VADC0_G0_2_IRQHandler     ; Handler name for SR VADC0_G0_2  
136 |                 Entry   VADC0_G0_3_IRQHandler     ; Handler name for SR VADC0_G0_3  
137 |                 Entry   VADC0_G1_0_IRQHandler     ; Handler name for SR VADC0_G1_0  
138 |                 Entry   VADC0_G1_1_IRQHandler     ; Handler name for SR VADC0_G1_1  
139 |                 Entry   VADC0_G1_2_IRQHandler     ; Handler name for SR VADC0_G1_2  
140 |                 Entry   VADC0_G1_3_IRQHandler     ; Handler name for SR VADC0_G1_3  
141 |                 Entry   VADC0_G2_0_IRQHandler     ; Handler name for SR VADC0_G2_0  
142 |                 Entry   VADC0_G2_1_IRQHandler     ; Handler name for SR VADC0_G2_1  
143 |                 Entry   VADC0_G2_2_IRQHandler     ; Handler name for SR VADC0_G2_2  
144 |                 Entry   VADC0_G2_3_IRQHandler     ; Handler name for SR VADC0_G2_3  
145 |                 Entry   VADC0_G3_0_IRQHandler     ; Handler name for SR VADC0_G3_0  
146 |                 Entry   VADC0_G3_1_IRQHandler     ; Handler name for SR VADC0_G3_1  
147 |                 Entry   VADC0_G3_2_IRQHandler     ; Handler name for SR VADC0_G3_2  
148 |                 Entry   VADC0_G3_3_IRQHandler     ; Handler name for SR VADC0_G3_3  
149 |                 Entry   DSD0_0_IRQHandler         ; Handler name for SR DSD_SRM_0 
150 |                 Entry   DSD0_1_IRQHandler         ; Handler name for SR DSD_SRM_1 
151 |                 Entry   DSD0_2_IRQHandler         ; Handler name for SR DSD_SRM_2 
152 |                 Entry   DSD0_3_IRQHandler         ; Handler name for SR DSD_SRM_3 
153 |                 Entry   DSD0_4_IRQHandler         ; Handler name for SR DSD_SRA_0 
154 |                 Entry   DSD0_5_IRQHandler         ; Handler name for SR DSD_SRA_1 
155 |                 Entry   DSD0_6_IRQHandler         ; Handler name for SR DSD_SRA_2 
156 |                 Entry   DSD0_7_IRQHandler         ; Handler name for SR DSD_SRA_3 
157 |                 Entry   DAC0_0_IRQHandler         ; Handler name for SR DAC0_0    
158 |                 Entry   DAC0_1_IRQHandler         ; Handler name for SR DAC0_1    
159 |                 Entry   CCU40_0_IRQHandler        ; Handler name for SR CCU40_0   
160 |                 Entry   CCU40_1_IRQHandler        ; Handler name for SR CCU40_1   
161 |                 Entry   CCU40_2_IRQHandler        ; Handler name for SR CCU40_2   
162 |                 Entry   CCU40_3_IRQHandler        ; Handler name for SR CCU40_3   
163 |                 Entry   CCU41_0_IRQHandler        ; Handler name for SR CCU41_0   
164 |                 Entry   CCU41_1_IRQHandler        ; Handler name for SR CCU41_1   
165 |                 Entry   CCU41_2_IRQHandler        ; Handler name for SR CCU41_2   
166 |                 Entry   CCU41_3_IRQHandler        ; Handler name for SR CCU41_3   
167 |                 Entry   CCU42_0_IRQHandler        ; Handler name for SR CCU42_0   
168 |                 Entry   CCU42_1_IRQHandler        ; Handler name for SR CCU42_1   
169 |                 Entry   CCU42_2_IRQHandler        ; Handler name for SR CCU42_2   
170 |                 Entry   CCU42_3_IRQHandler        ; Handler name for SR CCU42_3   
171 |                 Entry   CCU43_0_IRQHandler        ; Handler name for SR CCU43_0   
172 |                 Entry   CCU43_1_IRQHandler        ; Handler name for SR CCU43_1   
173 |                 Entry   CCU43_2_IRQHandler        ; Handler name for SR CCU43_2   
174 |                 Entry   CCU43_3_IRQHandler        ; Handler name for SR CCU43_3   
175 |                 Entry   CCU80_0_IRQHandler        ; Handler name for SR CCU80_0   
176 |                 Entry   CCU80_1_IRQHandler        ; Handler name for SR CCU80_1   
177 |                 Entry   CCU80_2_IRQHandler        ; Handler name for SR CCU80_2   
178 |                 Entry   CCU80_3_IRQHandler        ; Handler name for SR CCU80_3   
179 |                 Entry   CCU81_0_IRQHandler        ; Handler name for SR CCU81_0   
180 |                 Entry   CCU81_1_IRQHandler        ; Handler name for SR CCU81_1   
181 |                 Entry   CCU81_2_IRQHandler        ; Handler name for SR CCU81_2   
182 |                 Entry   CCU81_3_IRQHandler        ; Handler name for SR CCU81_3   
183 |                 Entry   POSIF0_0_IRQHandler       ; Handler name for SR POSIF0_0  
184 |                 Entry   POSIF0_1_IRQHandler       ; Handler name for SR POSIF0_1  
185 |                 Entry   POSIF1_0_IRQHandler       ; Handler name for SR POSIF1_0  
186 |                 Entry   POSIF1_1_IRQHandler       ; Handler name for SR POSIF1_1  
187 |                 Entry   HRPWM_0_IRQHandler        ; Handler name for SR HRPWM_0   
188 |                 Entry   HRPWM_1_IRQHandler        ; Handler name for SR HRPWM_1   
189 |                 Entry   HRPWM_2_IRQHandler        ; Handler name for SR HRPWM_2   
190 |                 Entry   HRPWM_3_IRQHandler        ; Handler name for SR HRPWM_3   
191 |                 Entry   CAN0_0_IRQHandler         ; Handler name for SR CAN0_0    
192 |                 Entry   CAN0_1_IRQHandler         ; Handler name for SR CAN0_1    
193 |                 Entry   CAN0_2_IRQHandler         ; Handler name for SR CAN0_2    
194 |                 Entry   CAN0_3_IRQHandler         ; Handler name for SR CAN0_3    
195 |                 Entry   CAN0_4_IRQHandler         ; Handler name for SR CAN0_4    
196 |                 Entry   CAN0_5_IRQHandler         ; Handler name for SR CAN0_5    
197 |                 Entry   CAN0_6_IRQHandler         ; Handler name for SR CAN0_6    
198 |                 Entry   CAN0_7_IRQHandler         ; Handler name for SR CAN0_7    
199 |                 Entry   USIC0_0_IRQHandler        ; Handler name for SR USIC0_0   
200 |                 Entry   USIC0_1_IRQHandler        ; Handler name for SR USIC0_1   
201 |                 Entry   USIC0_2_IRQHandler        ; Handler name for SR USIC0_2   
202 |                 Entry   USIC0_3_IRQHandler        ; Handler name for SR USIC0_3   
203 |                 Entry   USIC0_4_IRQHandler        ; Handler name for SR USIC0_4   
204 |                 Entry   USIC0_5_IRQHandler        ; Handler name for SR USIC0_5   
205 |                 Entry   USIC1_0_IRQHandler        ; Handler name for SR USIC1_0   
206 |                 Entry   USIC1_1_IRQHandler        ; Handler name for SR USIC1_1   
207 |                 Entry   USIC1_2_IRQHandler        ; Handler name for SR USIC1_2   
208 |                 Entry   USIC1_3_IRQHandler        ; Handler name for SR USIC1_3   
209 |                 Entry   USIC1_4_IRQHandler        ; Handler name for SR USIC1_4   
210 |                 Entry   USIC1_5_IRQHandler        ; Handler name for SR USIC1_5   
211 |                 DCD     0                         ; Not Available                 
212 |                 DCD     0                         ; Not Available                 
213 |                 DCD     0                         ; Not Available                 
214 |                 DCD     0                         ; Not Available                 
215 |                 DCD     0                         ; Not Available                 
216 |                 DCD     0                         ; Not Available                 
217 |                 Entry   LEDTS0_0_IRQHandler       ; Handler name for SR LEDTS0_0  
218 |                 DCD     0                         ; Not Available                 
219 |                 Entry   FCE0_0_IRQHandler         ; Handler name for SR FCE0_0    
220 |                 Entry   GPDMA0_0_IRQHandler       ; Handler name for SR GPDMA0_0  
221 |                 DCD     0                         ; Not Available                 
222 |                 Entry   USB0_0_IRQHandler         ; Handler name for SR USB0_0    
223 |                 Entry   ETH0_0_IRQHandler         ; Handler name for SR ETH0_0    
224 |                 DCD     0                         ; Not Available                 
225 |                 DCD     0                         ; Not Available                 
226 |                 DCD     0                         ; Not Available                 
227 | __Vectors_End
228 | 
229 | __Vectors_Size  EQU     __Vectors_End - __Vectors
230 | 
231 |                 AREA    |.text|, CODE, READONLY
232 | 
233 | ; Reset Handler
234 | 
235 | Reset_Handler   PROC
236 |                 EXPORT  Reset_Handler           [WEAK]
237 |                 IMPORT  SystemInit
238 |                 IMPORT  __main
239 |                 LDR     SP, =__initial_sp                                
240 |                 LDR     R0, =SystemInit
241 |                 BLX     R0
242 |                 LDR     R0, =__main
243 |                 BX      R0
244 |                 ENDP
245 | 
246 | ; Dummy Exception Handlers (infinite loops which can be modified)
247 |              
248 | Default_Handler PROC
249 |                 EXPORT  NMI_Handler             [WEAK]
250 |                 EXPORT  HardFault_Handler       [WEAK]
251 |                 EXPORT  MemManage_Handler       [WEAK]
252 |                 EXPORT  BusFault_Handler        [WEAK]
253 |                 EXPORT  UsageFault_Handler      [WEAK]
254 |                 EXPORT  SVC_Handler             [WEAK]
255 |                 EXPORT  DebugMon_Handler        [WEAK]
256 |                 EXPORT  PendSV_Handler          [WEAK]
257 |                 EXPORT  SysTick_Handler         [WEAK]
258 |                 
259 |                 EXPORT  SCU_0_IRQHandler        [WEAK]
260 |                 EXPORT  ERU0_0_IRQHandler       [WEAK]
261 |                 EXPORT  ERU0_1_IRQHandler       [WEAK]
262 |                 EXPORT  ERU0_2_IRQHandler       [WEAK]
263 |                 EXPORT  ERU0_3_IRQHandler       [WEAK]
264 |                 EXPORT  ERU1_0_IRQHandler       [WEAK]
265 |                 EXPORT  ERU1_1_IRQHandler       [WEAK]
266 |                 EXPORT  ERU1_2_IRQHandler       [WEAK]
267 |                 EXPORT  ERU1_3_IRQHandler       [WEAK]
268 |                 EXPORT  PMU0_0_IRQHandler       [WEAK]
269 |                 EXPORT  VADC0_C0_0_IRQHandler   [WEAK]
270 |                 EXPORT  VADC0_C0_1_IRQHandler   [WEAK]
271 |                 EXPORT  VADC0_C0_2_IRQHandler   [WEAK]
272 |                 EXPORT  VADC0_C0_3_IRQHandler   [WEAK]
273 |                 EXPORT  VADC0_G0_0_IRQHandler   [WEAK]
274 |                 EXPORT  VADC0_G0_1_IRQHandler   [WEAK]
275 |                 EXPORT  VADC0_G0_2_IRQHandler   [WEAK]
276 |                 EXPORT  VADC0_G0_3_IRQHandler   [WEAK]
277 |                 EXPORT  VADC0_G1_0_IRQHandler   [WEAK]
278 |                 EXPORT  VADC0_G1_1_IRQHandler   [WEAK]
279 |                 EXPORT  VADC0_G1_2_IRQHandler   [WEAK]
280 |                 EXPORT  VADC0_G1_3_IRQHandler   [WEAK]
281 |                 EXPORT  VADC0_G2_0_IRQHandler   [WEAK]
282 |                 EXPORT  VADC0_G2_1_IRQHandler   [WEAK]
283 |                 EXPORT  VADC0_G2_2_IRQHandler   [WEAK]
284 |                 EXPORT  VADC0_G2_3_IRQHandler   [WEAK]
285 |                 EXPORT  VADC0_G3_0_IRQHandler   [WEAK]
286 |                 EXPORT  VADC0_G3_1_IRQHandler   [WEAK]
287 |                 EXPORT  VADC0_G3_2_IRQHandler   [WEAK]
288 |                 EXPORT  VADC0_G3_3_IRQHandler   [WEAK]
289 |                 EXPORT  DSD0_0_IRQHandler       [WEAK]
290 |                 EXPORT  DSD0_1_IRQHandler       [WEAK]
291 |                 EXPORT  DSD0_2_IRQHandler       [WEAK]
292 |                 EXPORT  DSD0_3_IRQHandler       [WEAK]
293 |                 EXPORT  DSD0_4_IRQHandler       [WEAK]
294 |                 EXPORT  DSD0_5_IRQHandler       [WEAK]
295 |                 EXPORT  DSD0_6_IRQHandler       [WEAK]
296 |                 EXPORT  DSD0_7_IRQHandler       [WEAK]
297 |                 EXPORT  DAC0_0_IRQHandler       [WEAK]
298 |                 EXPORT  DAC0_1_IRQHandler       [WEAK]
299 |                 EXPORT  CCU40_0_IRQHandler      [WEAK]
300 |                 EXPORT  CCU40_1_IRQHandler      [WEAK]
301 |                 EXPORT  CCU40_2_IRQHandler      [WEAK]
302 |                 EXPORT  CCU40_3_IRQHandler      [WEAK]
303 |                 EXPORT  CCU41_0_IRQHandler      [WEAK]
304 |                 EXPORT  CCU41_1_IRQHandler      [WEAK]
305 |                 EXPORT  CCU41_2_IRQHandler      [WEAK]
306 |                 EXPORT  CCU41_3_IRQHandler      [WEAK]
307 |                 EXPORT  CCU42_0_IRQHandler      [WEAK]
308 |                 EXPORT  CCU42_1_IRQHandler      [WEAK]
309 |                 EXPORT  CCU42_2_IRQHandler      [WEAK]
310 |                 EXPORT  CCU42_3_IRQHandler      [WEAK]
311 |                 EXPORT  CCU43_0_IRQHandler      [WEAK]
312 |                 EXPORT  CCU43_1_IRQHandler      [WEAK]
313 |                 EXPORT  CCU43_2_IRQHandler      [WEAK]
314 |                 EXPORT  CCU43_3_IRQHandler      [WEAK]
315 |                 EXPORT  CCU80_0_IRQHandler      [WEAK]
316 |                 EXPORT  CCU80_1_IRQHandler      [WEAK]
317 |                 EXPORT  CCU80_2_IRQHandler      [WEAK]
318 |                 EXPORT  CCU80_3_IRQHandler      [WEAK]
319 |                 EXPORT  CCU81_0_IRQHandler      [WEAK]
320 |                 EXPORT  CCU81_1_IRQHandler      [WEAK]
321 |                 EXPORT  CCU81_2_IRQHandler      [WEAK]
322 |                 EXPORT  CCU81_3_IRQHandler      [WEAK]
323 |                 EXPORT  POSIF0_0_IRQHandler     [WEAK]
324 |                 EXPORT  POSIF0_1_IRQHandler     [WEAK]
325 |                 EXPORT  POSIF1_0_IRQHandler     [WEAK]
326 |                 EXPORT  POSIF1_1_IRQHandler     [WEAK]
327 |                 EXPORT  HRPWM_0_IRQHandler      [WEAK]
328 |                 EXPORT  HRPWM_1_IRQHandler      [WEAK]
329 |                 EXPORT  HRPWM_2_IRQHandler      [WEAK]
330 |                 EXPORT  HRPWM_3_IRQHandler      [WEAK]
331 |                 EXPORT  CAN0_0_IRQHandler       [WEAK]
332 |                 EXPORT  CAN0_1_IRQHandler       [WEAK]
333 |                 EXPORT  CAN0_2_IRQHandler       [WEAK]
334 |                 EXPORT  CAN0_3_IRQHandler       [WEAK]
335 |                 EXPORT  CAN0_4_IRQHandler       [WEAK]
336 |                 EXPORT  CAN0_5_IRQHandler       [WEAK]
337 |                 EXPORT  CAN0_6_IRQHandler       [WEAK]
338 |                 EXPORT  CAN0_7_IRQHandler       [WEAK]
339 |                 EXPORT  USIC0_0_IRQHandler      [WEAK]
340 |                 EXPORT  USIC0_1_IRQHandler      [WEAK]
341 |                 EXPORT  USIC0_2_IRQHandler      [WEAK]
342 |                 EXPORT  USIC0_3_IRQHandler      [WEAK]
343 |                 EXPORT  USIC0_4_IRQHandler      [WEAK]
344 |                 EXPORT  USIC0_5_IRQHandler      [WEAK]
345 |                 EXPORT  USIC1_0_IRQHandler      [WEAK]
346 |                 EXPORT  USIC1_1_IRQHandler      [WEAK]
347 |                 EXPORT  USIC1_2_IRQHandler      [WEAK]
348 |                 EXPORT  USIC1_3_IRQHandler      [WEAK]
349 |                 EXPORT  USIC1_4_IRQHandler      [WEAK]
350 |                 EXPORT  USIC1_5_IRQHandler      [WEAK]
351 |                 EXPORT  LEDTS0_0_IRQHandler     [WEAK]
352 |                 EXPORT  FCE0_0_IRQHandler       [WEAK]
353 |                 EXPORT  GPDMA0_0_IRQHandler     [WEAK]
354 |                 EXPORT  USB0_0_IRQHandler       [WEAK]
355 |                 EXPORT  ETH0_0_IRQHandler       [WEAK]
356 | 
357 | NMI_Handler
358 | HardFault_Handler
359 | MemManage_Handler
360 | BusFault_Handler
361 | UsageFault_Handler
362 | SVC_Handler
363 | DebugMon_Handler
364 | PendSV_Handler
365 | SysTick_Handler                
366 | SCU_0_IRQHandler
367 | ERU0_0_IRQHandler 
368 | ERU0_1_IRQHandler 
369 | ERU0_2_IRQHandler 
370 | ERU0_3_IRQHandler 
371 | ERU1_0_IRQHandler 
372 | ERU1_1_IRQHandler 
373 | ERU1_2_IRQHandler 
374 | ERU1_3_IRQHandler 
375 | PMU0_0_IRQHandler 
376 | VADC0_C0_0_IRQHandler 
377 | VADC0_C0_1_IRQHandler 
378 | VADC0_C0_2_IRQHandler 
379 | VADC0_C0_3_IRQHandler 
380 | VADC0_G0_0_IRQHandler 
381 | VADC0_G0_1_IRQHandler 
382 | VADC0_G0_2_IRQHandler 
383 | VADC0_G0_3_IRQHandler 
384 | VADC0_G1_0_IRQHandler 
385 | VADC0_G1_1_IRQHandler 
386 | VADC0_G1_2_IRQHandler 
387 | VADC0_G1_3_IRQHandler 
388 | VADC0_G2_0_IRQHandler 
389 | VADC0_G2_1_IRQHandler 
390 | VADC0_G2_2_IRQHandler 
391 | VADC0_G2_3_IRQHandler 
392 | VADC0_G3_0_IRQHandler 
393 | VADC0_G3_1_IRQHandler 
394 | VADC0_G3_2_IRQHandler 
395 | VADC0_G3_3_IRQHandler 
396 | DSD0_0_IRQHandler 
397 | DSD0_1_IRQHandler 
398 | DSD0_2_IRQHandler 
399 | DSD0_3_IRQHandler 
400 | DSD0_4_IRQHandler 
401 | DSD0_5_IRQHandler 
402 | DSD0_6_IRQHandler 
403 | DSD0_7_IRQHandler 
404 | DAC0_0_IRQHandler 
405 | DAC0_1_IRQHandler 
406 | CCU40_0_IRQHandler
407 | CCU40_1_IRQHandler
408 | CCU40_2_IRQHandler
409 | CCU40_3_IRQHandler
410 | CCU41_0_IRQHandler
411 | CCU41_1_IRQHandler
412 | CCU41_2_IRQHandler
413 | CCU41_3_IRQHandler
414 | CCU42_0_IRQHandler
415 | CCU42_1_IRQHandler
416 | CCU42_2_IRQHandler
417 | CCU42_3_IRQHandler
418 | CCU43_0_IRQHandler
419 | CCU43_1_IRQHandler
420 | CCU43_2_IRQHandler
421 | CCU43_3_IRQHandler
422 | CCU80_0_IRQHandler
423 | CCU80_1_IRQHandler
424 | CCU80_2_IRQHandler
425 | CCU80_3_IRQHandler
426 | CCU81_0_IRQHandler
427 | CCU81_1_IRQHandler
428 | CCU81_2_IRQHandler
429 | CCU81_3_IRQHandler
430 | POSIF0_0_IRQHandler 
431 | POSIF0_1_IRQHandler 
432 | POSIF1_0_IRQHandler 
433 | POSIF1_1_IRQHandler 
434 | HRPWM_0_IRQHandler
435 | HRPWM_1_IRQHandler
436 | HRPWM_2_IRQHandler
437 | HRPWM_3_IRQHandler
438 | CAN0_0_IRQHandler 
439 | CAN0_1_IRQHandler 
440 | CAN0_2_IRQHandler 
441 | CAN0_3_IRQHandler 
442 | CAN0_4_IRQHandler 
443 | CAN0_5_IRQHandler 
444 | CAN0_6_IRQHandler 
445 | CAN0_7_IRQHandler 
446 | USIC0_0_IRQHandler
447 | USIC0_1_IRQHandler
448 | USIC0_2_IRQHandler
449 | USIC0_3_IRQHandler
450 | USIC0_4_IRQHandler
451 | USIC0_5_IRQHandler
452 | USIC1_0_IRQHandler
453 | USIC1_1_IRQHandler
454 | USIC1_2_IRQHandler
455 | USIC1_3_IRQHandler
456 | USIC1_4_IRQHandler
457 | USIC1_5_IRQHandler
458 | LEDTS0_0_IRQHandler 
459 | FCE0_0_IRQHandler 
460 | GPDMA0_0_IRQHandler 
461 | USB0_0_IRQHandler 
462 | ETH0_0_IRQHandler 
463 | 
464 |                 B       .
465 | 
466 |                 ENDP
467 | 
468 |                 IF     :DEF:ENABLE_PMU_CM_001_WORKAROUND
469 | 
470 |                 MACRO
471 |                 Insert_ExceptionHandlerVeneer $Handler_Func                    
472 | $Handler_Func._Veneer\
473 |                     PROC
474 |                     EXPORT  $Handler_Func._Veneer [WEAK]
475 |                     LDR     R0, =$Handler_Func
476 |                     PUSH    {LR}  ;/* Breaks AAPCS */
477 |                     SUB     SP,#4     ;/* Restores AAPCS */
478 |                     BLX     R0
479 |                     ADD     SP,#4
480 |                     POP     {PC}
481 |                     ALIGN
482 |                     LTORG
483 |                     ENDP
484 |                 MEND
485 |                 
486 |                 Insert_ExceptionHandlerVeneer  NMI_Handler
487 |                 Insert_ExceptionHandlerVeneer  HardFault_Handler
488 |                 Insert_ExceptionHandlerVeneer  MemManage_Handler
489 |                 Insert_ExceptionHandlerVeneer  BusFault_Handler 
490 |                 Insert_ExceptionHandlerVeneer  UsageFault_Handler
491 |                 Insert_ExceptionHandlerVeneer  SVC_Handler
492 |                 Insert_ExceptionHandlerVeneer  DebugMon_Handler
493 |                 Insert_ExceptionHandlerVeneer  PendSV_Handler
494 |                 Insert_ExceptionHandlerVeneer SysTick_Handler
495 | 
496 |                 Insert_ExceptionHandlerVeneer  SCU_0_IRQHandler
497 |                 Insert_ExceptionHandlerVeneer  ERU0_0_IRQHandler
498 |                 Insert_ExceptionHandlerVeneer  ERU0_1_IRQHandler
499 |                 Insert_ExceptionHandlerVeneer  ERU0_2_IRQHandler
500 |                 Insert_ExceptionHandlerVeneer  ERU0_3_IRQHandler
501 |                 Insert_ExceptionHandlerVeneer  ERU1_0_IRQHandler
502 |                 Insert_ExceptionHandlerVeneer  ERU1_1_IRQHandler
503 |                 Insert_ExceptionHandlerVeneer  ERU1_2_IRQHandler
504 |                 Insert_ExceptionHandlerVeneer  ERU1_3_IRQHandler
505 |                 Insert_ExceptionHandlerVeneer  PMU0_0_IRQHandler
506 |                 Insert_ExceptionHandlerVeneer  VADC0_C0_0_IRQHandler   
507 |                 Insert_ExceptionHandlerVeneer  VADC0_C0_1_IRQHandler   
508 |                 Insert_ExceptionHandlerVeneer  VADC0_C0_2_IRQHandler   
509 |                 Insert_ExceptionHandlerVeneer  VADC0_C0_3_IRQHandler   
510 |                 Insert_ExceptionHandlerVeneer  VADC0_G0_0_IRQHandler   
511 |                 Insert_ExceptionHandlerVeneer  VADC0_G0_1_IRQHandler   
512 |                 Insert_ExceptionHandlerVeneer  VADC0_G0_2_IRQHandler   
513 |                 Insert_ExceptionHandlerVeneer  VADC0_G0_3_IRQHandler   
514 |                 Insert_ExceptionHandlerVeneer  VADC0_G1_0_IRQHandler   
515 |                 Insert_ExceptionHandlerVeneer  VADC0_G1_1_IRQHandler   
516 |                 Insert_ExceptionHandlerVeneer  VADC0_G1_2_IRQHandler   
517 |                 Insert_ExceptionHandlerVeneer  VADC0_G1_3_IRQHandler   
518 |                 Insert_ExceptionHandlerVeneer  VADC0_G2_0_IRQHandler   
519 |                 Insert_ExceptionHandlerVeneer  VADC0_G2_1_IRQHandler   
520 |                 Insert_ExceptionHandlerVeneer  VADC0_G2_2_IRQHandler   
521 |                 Insert_ExceptionHandlerVeneer  VADC0_G2_3_IRQHandler   
522 |                 Insert_ExceptionHandlerVeneer  VADC0_G3_0_IRQHandler   
523 |                 Insert_ExceptionHandlerVeneer  VADC0_G3_1_IRQHandler   
524 |                 Insert_ExceptionHandlerVeneer  VADC0_G3_2_IRQHandler   
525 |                 Insert_ExceptionHandlerVeneer  VADC0_G3_3_IRQHandler   
526 |                 Insert_ExceptionHandlerVeneer  DSD0_0_IRQHandler       
527 |                 Insert_ExceptionHandlerVeneer  DSD0_1_IRQHandler       
528 |                 Insert_ExceptionHandlerVeneer  DSD0_2_IRQHandler       
529 |                 Insert_ExceptionHandlerVeneer  DSD0_3_IRQHandler       
530 |                 Insert_ExceptionHandlerVeneer  DSD0_4_IRQHandler       
531 |                 Insert_ExceptionHandlerVeneer  DSD0_5_IRQHandler       
532 |                 Insert_ExceptionHandlerVeneer  DSD0_6_IRQHandler       
533 |                 Insert_ExceptionHandlerVeneer  DSD0_7_IRQHandler       
534 |                 Insert_ExceptionHandlerVeneer  DAC0_0_IRQHandler       
535 |                 Insert_ExceptionHandlerVeneer  DAC0_1_IRQHandler       
536 |                 Insert_ExceptionHandlerVeneer  CCU40_0_IRQHandler      
537 |                 Insert_ExceptionHandlerVeneer  CCU40_1_IRQHandler      
538 |                 Insert_ExceptionHandlerVeneer  CCU40_2_IRQHandler      
539 |                 Insert_ExceptionHandlerVeneer  CCU40_3_IRQHandler      
540 |                 Insert_ExceptionHandlerVeneer  CCU41_0_IRQHandler      
541 |                 Insert_ExceptionHandlerVeneer  CCU41_1_IRQHandler      
542 |                 Insert_ExceptionHandlerVeneer  CCU41_2_IRQHandler      
543 |                 Insert_ExceptionHandlerVeneer  CCU41_3_IRQHandler      
544 |                 Insert_ExceptionHandlerVeneer  CCU42_0_IRQHandler      
545 |                 Insert_ExceptionHandlerVeneer  CCU42_1_IRQHandler      
546 |                 Insert_ExceptionHandlerVeneer  CCU42_2_IRQHandler      
547 |                 Insert_ExceptionHandlerVeneer  CCU42_3_IRQHandler      
548 |                 Insert_ExceptionHandlerVeneer  CCU43_0_IRQHandler      
549 |                 Insert_ExceptionHandlerVeneer  CCU43_1_IRQHandler      
550 |                 Insert_ExceptionHandlerVeneer  CCU43_2_IRQHandler      
551 |                 Insert_ExceptionHandlerVeneer  CCU43_3_IRQHandler      
552 |                 Insert_ExceptionHandlerVeneer  CCU80_0_IRQHandler      
553 |                 Insert_ExceptionHandlerVeneer  CCU80_1_IRQHandler      
554 |                 Insert_ExceptionHandlerVeneer  CCU80_2_IRQHandler      
555 |                 Insert_ExceptionHandlerVeneer  CCU80_3_IRQHandler      
556 |                 Insert_ExceptionHandlerVeneer  CCU81_0_IRQHandler      
557 |                 Insert_ExceptionHandlerVeneer  CCU81_1_IRQHandler      
558 |                 Insert_ExceptionHandlerVeneer  CCU81_2_IRQHandler      
559 |                 Insert_ExceptionHandlerVeneer  CCU81_3_IRQHandler      
560 |                 Insert_ExceptionHandlerVeneer  POSIF0_0_IRQHandler     
561 |                 Insert_ExceptionHandlerVeneer  POSIF0_1_IRQHandler     
562 |                 Insert_ExceptionHandlerVeneer  POSIF1_0_IRQHandler     
563 |                 Insert_ExceptionHandlerVeneer  POSIF1_1_IRQHandler     
564 |                 Insert_ExceptionHandlerVeneer  HRPWM_0_IRQHandler      
565 |                 Insert_ExceptionHandlerVeneer  HRPWM_1_IRQHandler      
566 |                 Insert_ExceptionHandlerVeneer  HRPWM_2_IRQHandler      
567 |                 Insert_ExceptionHandlerVeneer  HRPWM_3_IRQHandler      
568 |                 Insert_ExceptionHandlerVeneer  CAN0_0_IRQHandler       
569 |                 Insert_ExceptionHandlerVeneer  CAN0_1_IRQHandler       
570 |                 Insert_ExceptionHandlerVeneer  CAN0_2_IRQHandler       
571 |                 Insert_ExceptionHandlerVeneer  CAN0_3_IRQHandler       
572 |                 Insert_ExceptionHandlerVeneer  CAN0_4_IRQHandler       
573 |                 Insert_ExceptionHandlerVeneer  CAN0_5_IRQHandler       
574 |                 Insert_ExceptionHandlerVeneer  CAN0_6_IRQHandler       
575 |                 Insert_ExceptionHandlerVeneer  CAN0_7_IRQHandler       
576 |                 Insert_ExceptionHandlerVeneer  USIC0_0_IRQHandler      
577 |                 Insert_ExceptionHandlerVeneer  USIC0_1_IRQHandler      
578 |                 Insert_ExceptionHandlerVeneer  USIC0_2_IRQHandler      
579 |                 Insert_ExceptionHandlerVeneer  USIC0_3_IRQHandler      
580 |                 Insert_ExceptionHandlerVeneer  USIC0_4_IRQHandler      
581 |                 Insert_ExceptionHandlerVeneer  USIC0_5_IRQHandler      
582 |                 Insert_ExceptionHandlerVeneer  USIC1_0_IRQHandler      
583 |                 Insert_ExceptionHandlerVeneer  USIC1_1_IRQHandler      
584 |                 Insert_ExceptionHandlerVeneer  USIC1_2_IRQHandler      
585 |                 Insert_ExceptionHandlerVeneer  USIC1_3_IRQHandler      
586 |                 Insert_ExceptionHandlerVeneer  USIC1_4_IRQHandler      
587 |                 Insert_ExceptionHandlerVeneer  USIC1_5_IRQHandler      
588 |                 Insert_ExceptionHandlerVeneer  LEDTS0_0_IRQHandler     
589 |                 Insert_ExceptionHandlerVeneer  FCE0_0_IRQHandler       
590 |                 Insert_ExceptionHandlerVeneer  GPDMA0_0_IRQHandler     
591 |                 Insert_ExceptionHandlerVeneer  USB0_0_IRQHandler       
592 |                 Insert_ExceptionHandlerVeneer  ETH0_0_IRQHandler       
593 |                 ENDIF
594 |                 
595 |                 ALIGN
596 | 
597 | ; User Initial Stack & Heap
598 | 
599 |                 IF      :DEF:__MICROLIB
600 | 
601 |                 EXPORT  __initial_sp
602 |                 EXPORT  __heap_base
603 |                 EXPORT  __heap_limit
604 | 
605 |                 ELSE
606 | 
607 |                 IMPORT  __use_two_region_memory
608 |                 EXPORT  __user_initial_stackheap
609 | __user_initial_stackheap
610 | 
611 |                 LDR     R0, =  Heap_Mem
612 |                 LDR     R1, =(Stack_Mem + Stack_Size)
613 |                 LDR     R2, = (Heap_Mem +  Heap_Size)
614 |                 LDR     R3, = Stack_Mem
615 |                 BX      LR
616 | 
617 |                 ALIGN
618 | 
619 |                 ENDIF
620 | 
621 | 
622 |                 END
623 | 


--------------------------------------------------------------------------------
/RTE/Device/XMC4400-F64x512/system_XMC4400.c:
--------------------------------------------------------------------------------
  1 | /*********************************************************************************************************************
  2 |  * @file     system_XMC4400.c
  3 |  * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4400 Device Series
  4 |  * @version  V3.1.4
  5 |  * @date     29. Oct 2018
  6 |  *
  7 |  * @cond
  8 |  *********************************************************************************************************************
  9 |  * Copyright (c) 2014-2018, Infineon Technologies AG
 10 |  * All rights reserved.
 11 |  *
 12 |  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
 13 |  * following conditions are met:
 14 |  *
 15 |  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
 16 |  * disclaimer.
 17 |  *
 18 |  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
 19 |  * disclaimer in the documentation and/or other materials provided with the distribution.
 20 |  *
 21 |  * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
 22 |  * products derived from this software without specific prior written permission.
 23 |  *
 24 |  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 25 |  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 26 |  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 27 |  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 28 |  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 29 |  * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 30 |  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 31 |  *
 32 |  * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
 33 |  * Infineon Technologies AG dave@infineon.com).
 34 |  *********************************************************************************************************************
 35 |  *
 36 |  ********************** Version History ***************************************
 37 |  * V3.1.0, Dec 2014, Added options to configure clock settings
 38 |  * V3.1.1, 01. Jun 2016, Fix masking of OSCHPCTRL value 
 39 |  * V3.1.2, 19. Jun 2017, Rely on cmsis_compiler.h instead of defining __WEAK 
 40 |  *                       Added support for ARM Compiler 6 (armclang) 
 41 |  * V3.1.3, 26. Sep 2017, Disable FPU if FPU_USED is zero  
 42 |  * V3.1.4, 29. Oct 2018, Fix variable location of SystemCoreClock, g_hrpwm_char_data and g_chipid for ARMCC compiler
 43 |  ******************************************************************************
 44 |  * @endcond
 45 |  */
 46 | 
 47 | /*******************************************************************************
 48 |  * HEADER FILES
 49 |  *******************************************************************************/
 50 | #include <string.h>
 51 | 
 52 | #include <XMC4400.h>
 53 | #include "system_XMC4400.h"
 54 | 
 55 | /*******************************************************************************
 56 |  * MACROS
 57 |  *******************************************************************************/
 58 | #define CHIPID_LOC ((uint8_t *)0x20000000UL)
 59 | #define HRPWM_CHARDATA_LOC ((uint8_t *)0x20000084UL)
 60 | 
 61 | #define PMU_FLASH_WS          (0x3U)
 62 | 
 63 | #define FPLL_FREQUENCY        (120000000U)
 64 | #define FOSCREF               (2500000U)
 65 | #define DELAY_CNT_50US_50MHZ  (2500UL)
 66 | #define DELAY_CNT_150US_50MHZ (7500UL)
 67 | #define DELAY_CNT_50US_60MHZ  (3000UL)
 68 | #define DELAY_CNT_50US_90MHZ  (4500UL)
 69 | #define DELAY_CNT_50US_120MHZ (6000UL)
 70 | 
 71 | #define SCU_PLL_PLLSTAT_OSC_USABLE  (SCU_PLL_PLLSTAT_PLLHV_Msk | \
 72 |                                      SCU_PLL_PLLSTAT_PLLLV_Msk | \
 73 |                                      SCU_PLL_PLLSTAT_PLLSP_Msk)
 74 | 
 75 | /*
 76 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
 77 | */
 78 | 
 79 | /*
 80 | // <h> Clock configuration
 81 | */
 82 | 
 83 | /*
 84 | //    <o> External crystal frequency [Hz]
 85 | //       <8000000=> 8MHz
 86 | //       <12000000=> 12MHz
 87 | //       <16000000=> 16MHz
 88 | //    <i> Defines external crystal frequency
 89 | //    <i> Default: 8MHz
 90 | */
 91 | #define OSCHP_FREQUENCY (12000000U)
 92 | 
 93 | #if OSCHP_FREQUENCY == 8000000U
 94 | #define USB_PDIV (1U)
 95 | #define USB_NDIV (95U)
 96 | #define USB_DIV (3U)
 97 | 
 98 | #elif OSCHP_FREQUENCY == 12000000U
 99 | #define USB_PDIV (1U)
100 | #define USB_NDIV (63U)
101 | #define USB_DIV (3U)
102 | 
103 | #elif OSCHP_FREQUENCY == 16000000U
104 | #define USB_PDIV (1U)
105 | #define USB_NDIV (47U)
106 | #define USB_DIV (3U)
107 | 
108 | #else
109 | #error "External crystal frequency not supported"
110 | 
111 | #endif
112 | 
113 | /*
114 | //    <o> System clock (fSYS) source selection
115 | //       <0=> Backup clock (24MHz)
116 | //       <1=> Maximum clock frequency using PLL (120MHz)
117 | //    <i> Default: Maximum clock frequency using PLL (120MHz)
118 | */
119 | #define SYS_CLOCK_SRC 1
120 | #define SYS_CLOCK_SRC_OFI 0
121 | #define SYS_CLOCK_SRC_PLL 1
122 | 
123 | /*
124 | //    <o> Backup clock calibration mode
125 | //       <0=> Factory calibration
126 | //       <1=> Automatic calibration
127 | //    <i> Default: Automatic calibration
128 | */
129 | #define FOFI_CALIBRATION_MODE 1
130 | #define FOFI_CALIBRATION_MODE_FACTORY 0
131 | #define FOFI_CALIBRATION_MODE_AUTOMATIC 1
132 | 
133 | /*
134 | //    <o> Standby clock (fSTDBY) source selection
135 | //       <0=> Internal slow oscillator (32768Hz)
136 | //       <1=> External crystal (32768Hz)
137 | //    <i> Default: Internal slow oscillator (32768Hz)
138 | */
139 | #define STDBY_CLOCK_SRC 0
140 | #define STDBY_CLOCK_SRC_OSI 0
141 | #define STDBY_CLOCK_SRC_OSCULP 1
142 | 
143 | /*
144 | //    <o> PLL clock source selection
145 | //       <0=> External crystal
146 | //       <1=> External direct input
147 | //       <2=> Internal fast oscillator
148 | //    <i> Default: External crystal
149 | */
150 | #define PLL_CLOCK_SRC 2
151 | #define PLL_CLOCK_SRC_EXT_XTAL 0
152 | #define PLL_CLOCK_SRC_EXT_DIRECT 1
153 | #define PLL_CLOCK_SRC_OFI 2
154 | 
155 | #if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL
156 | #if OSCHP_FREQUENCY == 8000000U
157 | #define PLL_PDIV (1U)
158 | #define PLL_NDIV (89U)
159 | #define PLL_K2DIV (2U)
160 | 
161 | #elif OSCHP_FREQUENCY == 12000000U
162 | #define PLL_PDIV (1U)
163 | #define PLL_NDIV (79U)
164 | #define PLL_K2DIV (3U)
165 | 
166 | #elif OSCHP_FREQUENCY == 16000000U
167 | #define PLL_PDIV (1U)
168 | #define PLL_NDIV (59U)
169 | #define PLL_K2DIV (3U)
170 | 
171 | #else
172 | #error "External crystal frequency not supported"
173 | 
174 | #endif
175 | 
176 | #define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
177 | 
178 | #else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */
179 | 
180 | #define PLL_PDIV (1U)
181 | #define PLL_NDIV (39U)
182 | #define PLL_K2DIV (3U)
183 | 
184 | #define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
185 | 
186 | #endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */
187 | 
188 | #define PLL_K2DIV_0 ((VCO / OFI_FREQUENCY) - 1UL)
189 | #define PLL_K2DIV_1 ((VCO / 60000000U) - 1UL)
190 | #define PLL_K2DIV_2 ((VCO / 90000000U) - 1UL)
191 | 
192 | #define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk
193 | #define SCU_CLK_CLKCLR_ENABLE_ETHCLK SCU_CLK_CLKCLR_ETH0CDI_Msk
194 | #define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk
195 | #define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk
196 | 
197 | #define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos)
198 | #define SCU_CLK_USBCLKCR_USBSEL_PLL    (1U << SCU_CLK_USBCLKCR_USBSEL_Pos)
199 | 
200 | #define SCU_CLK_WDTCLKCR_WDTSEL_OFI      (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
201 | #define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY  (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
202 | #define SCU_CLK_WDTCLKCR_WDTSEL_PLL      (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
203 | 
204 | #define SCU_CLK_EXTCLKCR_ECKSEL_SYS      (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
205 | #define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL   (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
206 | #define SCU_CLK_EXTCLKCR_ECKSEL_PLL      (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
207 | #define SCU_CLK_EXTCLKCR_ECKSEL_STANDBY  (4U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
208 | 
209 | #define EXTCLK_PIN_P0_8  (0)
210 | #define EXTCLK_PIN_P1_15 (1)
211 | 
212 | /*
213 | //    <h> Clock tree
214 | //        <o1.0> CPU clock divider
215 | //                   <0=> fCPU = fSYS
216 | //                   <1=> fCPU = fSYS / 2
217 | //        <o2.0>  Peripheral clock divider
218 | //                     <0=> fPB	= fCPU
219 | //                     <1=> fPB	= fCPU / 2
220 | //        <e.4> Enable CCU clock
221 | //             <o3.0>  CCU clock divider
222 | //                     <0=> fCCU = fCPU
223 | //                     <1=> fCCU = fCPU / 2
224 | //        </e>
225 | //        <e.5> Enable WDT clock
226 | //             <o4.0..7>  WDT clock divider <1-256><#-1>
227 | //             <o4.16..17> WDT clock source <0=> fOFI
228 | //                                          <1=> fSTDBY
229 | //                                          <2=> fPLL
230 | //        </e>
231 | //        <e.2> Enable ETH clock
232 | //        </e>
233 | //        <e.0> Enable USB clock
234 | //             <o5.16> USB clock source <0=> USBPLL
235 | //                                      <1=> PLL
236 | //        </e>
237 | //        <e6> External Clock configuration
238 | //            <o7.0..2> External clock source selection
239 | //                  <0=> System clock
240 | //                  <2=> USB PLL clock
241 | //                  <3=> PLL clock
242 | //                  <4=> Standby clock
243 | //            <o7.16..24> External clock divider <1-512><#-1>
244 | //            <i> Only valid for USB PLL and PLL clocks
245 | //            <o8.0> External Pin Selection
246 | //                  <0=> P0.8
247 | //                  <1=> P1.15
248 | //        </e>
249 | //    </h>
250 | */
251 | #define ENABLE_SCUCLK (0U)
252 | #define CPUCLKDIV (0U)
253 | #define PBCLKDIV (0U)
254 | #define CCUCLKDIV (0U)
255 | #define WDTCLKDIV (0U | SCU_CLK_WDTCLKCR_WDTSEL_OFI)
256 | #define USBCLKDIV (0U | SCU_CLK_USBCLKCR_USBSEL_USBPLL | USB_DIV)
257 | 
258 | #define ENABLE_EXTCLK (0U)
259 | #define EXTCLKDIV (0U | SCU_CLK_EXTCLKCR_ECKSEL_SYS)
260 | #define EXTCLK_PIN (0U)
261 | 
262 | #define ENABLE_PLL \
263 |     (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) || \
264 |     (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \
265 |     (((ENABLE_SCUCLK & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((WDTCLKDIV & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL))
266 | 
267 | /*
268 | // </h>
269 | */
270 | 
271 | /*
272 | //-------- <<< end of configuration section >>> ------------------
273 | */
274 | 
275 | /*******************************************************************************
276 |  * GLOBAL VARIABLES
277 |  *******************************************************************************/
278 | #if defined ( __CC_ARM )
279 | uint32_t SystemCoreClock __attribute__((at(0x2000FFC0)));
280 | uint8_t g_chipid[16] __attribute__((at(0x2000FFC4)));
281 | uint32_t g_hrpwm_char_data[3] __attribute__((at(0x2000FFD4)));
282 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
283 | uint32_t SystemCoreClock __attribute__((section(".bss.ARM.__at_0x2000FFC0")));
284 | uint8_t g_chipid[16] __attribute__((section(".bss.ARM.__at_0x2000FFC4")));
285 | uint32_t g_hrpwm_char_data[3] __attribute__((section(".bss.ARM.__at_0x2000FFD4")));
286 | #elif defined ( __ICCARM__ )
287 | __no_init uint32_t SystemCoreClock;
288 | __no_init uint8_t g_chipid[16];
289 | __no_init uint32_t g_hrpwm_char_data[3];
290 | #elif defined ( __GNUC__ )
291 | uint32_t SystemCoreClock __attribute__((section(".no_init")));
292 | uint8_t g_chipid[16] __attribute__((section(".no_init")));
293 | uint32_t g_hrpwm_char_data[3] __attribute__((section(".no_init")));
294 | #elif defined ( __TASKING__ )
295 | uint32_t SystemCoreClock __at( 0x2000FFC0 );
296 | uint8_t g_chipid[16] __at( 0x2000FFC4 );
297 | uint32_t g_hrpwm_char_data[3] __at( 0x2000FFD4 );
298 | #endif
299 | 
300 | extern uint32_t __Vectors;
301 | 
302 | /*******************************************************************************
303 |  * LOCAL FUNCTIONS
304 |  *******************************************************************************/
305 | static void delay(uint32_t cycles)
306 | {
307 |   volatile uint32_t i;
308 | 
309 |   for(i = 0UL; i < cycles ;++i)
310 |   {
311 |     __NOP();
312 |   }
313 | }
314 | 
315 | /*******************************************************************************
316 |  * API IMPLEMENTATION
317 |  *******************************************************************************/
318 | 
319 | __WEAK void SystemInit(void)
320 | {
321 |   memcpy(g_chipid, CHIPID_LOC, 16);
322 |   memcpy(g_hrpwm_char_data, HRPWM_CHARDATA_LOC, 12);
323 | 
324 |   SystemCoreSetup();
325 |   SystemCoreClockSetup(); 
326 | }
327 | 
328 | __WEAK void SystemCoreSetup(void)
329 | {
330 |   uint32_t temp;
331 | 	
332 |   /* relocate vector table */
333 |   __disable_irq();
334 |   SCB->VTOR = (uint32_t)(&__Vectors);
335 |   __DSB();
336 |   __enable_irq();
337 |     
338 |   /* __FPU_PRESENT = 1 defined in device header file */
339 |   /* __FPU_USED value depends on compiler/linker options. */
340 |   /* __FPU_USED = 0 if -mfloat-abi=soft is selected */
341 |   /* __FPU_USED = 1 if -mfloat-abi=softfp or –mfloat-abi=hard */
342 | 
343 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
344 |   SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
345 |                  (3UL << 11*2)  );               /* set CP11 Full Access */
346 | #else
347 |   SCB->CPACR = 0;
348 | #endif
349 | 
350 |   /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
351 |   SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
352 | 
353 |   temp = FLASH0->FCON;
354 |   temp &= ~FLASH_FCON_WSPFLASH_Msk;
355 |   temp |= PMU_FLASH_WS;
356 |   FLASH0->FCON = temp;
357 | }
358 | 
359 | __WEAK void SystemCoreClockSetup(void)
360 | {
361 | #if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY
362 |   /* Enable factory calibration */
363 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk;
364 | #else
365 |   /* Automatic calibration uses the fSTDBY */
366 | 
367 |   /* Enable HIB domain */
368 |   /* Power up HIB domain if and only if it is currently powered down */
369 |   if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
370 |   {
371 |     SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk;
372 | 
373 |     while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
374 |     {
375 |       /* wait until HIB domain is enabled */
376 |     }
377 |   }
378 | 
379 |   /* Remove the reset only if HIB domain were in a state of reset */
380 |   if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk)
381 |   {
382 |     SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk;
383 |     delay(DELAY_CNT_150US_50MHZ);
384 |   }
385 |   
386 | #if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP
387 |   /* Enable OSC_ULP */
388 |   if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL)
389 |   {
390 |     /*enable OSC_ULP*/
391 |     while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk)
392 |     {
393 |       /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
394 |     }
395 |     SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk;
396 | 
397 |     /* Check if the clock is OK using OSCULP Oscillator Watchdog*/
398 |     while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
399 |     {
400 |       /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
401 |     }
402 |     SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
403 | 
404 |     /* wait till clock is stable */
405 |     do
406 |     {
407 |       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk)
408 |       {
409 |         /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
410 |       }
411 |       SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
412 | 
413 |       delay(DELAY_CNT_50US_50MHZ);
414 | 
415 |     } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL);
416 | 
417 |   }
418 | 
419 |   /* now OSC_ULP is running and can be used*/
420 |   /* Select OSC_ULP as the clock source for RTC and STDBY*/
421 |   while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
422 |   {
423 |     /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
424 |   }
425 |   SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
426 | 
427 | #endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */
428 | 
429 |   /* Enable automatic calibration of internal fast oscillator */
430 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
431 | #endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */
432 | 
433 |   delay(DELAY_CNT_150US_50MHZ);
434 | 
435 | #if ENABLE_PLL
436 | 
437 |   /* enable PLL */
438 |   SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
439 | 
440 | #if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI
441 |   /* enable OSC_HP */
442 |   if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
443 |   {
444 |     SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
445 |     SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
446 | 
447 |     /* select OSC_HP clock as PLL input */
448 |     SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
449 | 
450 |     /* restart OSC Watchdog */
451 |     SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
452 | 
453 |     while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
454 |     {
455 |       /* wait till OSC_HP output frequency is usable */
456 |     }
457 |   }
458 | #else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */
459 | 
460 |   /* select backup clock as PLL input */
461 |   SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
462 | #endif
463 | 
464 |   /* Go to bypass the Main PLL */
465 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
466 | 
467 |   /* disconnect Oscillator from PLL */
468 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
469 | 
470 |   /* Setup divider settings for main PLL */
471 |   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
472 |                       (PLL_K2DIV_0 << SCU_PLL_PLLCON1_K2DIV_Pos) |
473 |                       (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
474 | 
475 |   /* Set OSCDISCDIS */
476 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
477 | 
478 |   /* connect Oscillator to PLL */
479 |   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
480 | 
481 |   /* restart PLL Lock detection */
482 |   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
483 | 
484 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
485 |   {
486 |     /* wait for PLL Lock */
487 |   }
488 | 
489 |   /* Disable bypass- put PLL clock back */
490 |   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
491 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U)
492 |   {
493 |     /* wait for normal mode */
494 |   }
495 | #endif /* ENABLE_PLL */
496 | 
497 | #if (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL)
498 |   /* Switch system clock to PLL */
499 |   SCU_CLK->SYSCLKCR |= SCU_CLK_SYSCLKCR_SYSSEL_Msk;
500 | #else
501 |   /* Switch system clock to backup clock */
502 |   SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk;
503 | #endif
504 | 
505 |   /* Before scaling to final frequency we need to setup the clock dividers */
506 |   SCU_CLK->PBCLKCR = PBCLKDIV;
507 |   SCU_CLK->CPUCLKCR = CPUCLKDIV;
508 |   SCU_CLK->CCUCLKCR = CCUCLKDIV;
509 |   SCU_CLK->WDTCLKCR = WDTCLKDIV;
510 |   SCU_CLK->USBCLKCR = USBCLKDIV;
511 | 
512 | #if ENABLE_PLL
513 |   /* PLL frequency stepping...*/
514 |   /* Reset OSCDISCDIS */
515 |   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
516 | 
517 |   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
518 | 	                    (PLL_K2DIV_1 << SCU_PLL_PLLCON1_K2DIV_Pos) |
519 | 	                    (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
520 | 
521 | 
522 |   delay(DELAY_CNT_50US_60MHZ);
523 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
524 |   {
525 |     /* wait for PLL Lock */
526 |   }
527 | 
528 |   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
529 | 	                    (PLL_K2DIV_2 << SCU_PLL_PLLCON1_K2DIV_Pos) |
530 | 	                    (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
531 | 
532 | 
533 |   delay(DELAY_CNT_50US_90MHZ);
534 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
535 |   {
536 |     /* wait for PLL Lock */
537 |   }
538 | 
539 |   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
540 | 	                    (PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) |
541 | 	                    (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
542 | 
543 | 
544 |   delay(DELAY_CNT_50US_120MHZ);
545 |   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
546 |   {
547 |     /* wait for PLL Lock */
548 |   }
549 | 
550 |   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
551 | #endif /* ENABLE_PLL */
552 | 
553 | #if (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL))
554 |   /* enable USB PLL first */
555 |   SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
556 | 
557 |   /* USB PLL uses as clock input the OSC_HP */
558 |   /* check and if not already running enable OSC_HP */
559 |   if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
560 |   {
561 |     /* check if Main PLL is switched on for OSC WDG*/
562 |     if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL)
563 |     {
564 |       /* enable PLL first */
565 |       SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
566 |     }
567 | 
568 |     SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
569 |     SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
570 | 
571 |     /* restart OSC Watchdog */
572 |     SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
573 | 
574 |     while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
575 |     {
576 |       /* wait till OSC_HP output frequency is usable */
577 |     }
578 |   }
579 | 
580 |   /* Setup USB PLL */
581 |   /* Go to bypass the USB PLL */
582 |   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
583 | 
584 |   /* disconnect Oscillator from USB PLL */
585 |   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
586 | 
587 |   /* Setup Divider settings for USB PLL */
588 |   SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) |
589 |                         (USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos));
590 | 
591 |   /* Set OSCDISCDIS */
592 |   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
593 | 
594 |   /* connect Oscillator to USB PLL */
595 |   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
596 | 
597 |   /* restart PLL Lock detection */
598 |   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
599 | 
600 |   while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U)
601 |   {
602 |     /* wait for PLL Lock */
603 |   }
604 | #endif /* (USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) */
605 | 
606 |   /* Enable selected clocks */
607 |   SCU_CLK->CLKSET = ENABLE_SCUCLK;
608 | 
609 | #if ENABLE_EXTCLK == 1
610 |   /* Configure external clock */
611 |   SCU_CLK->EXTCLKCR = EXTCLKDIV;
612 | 
613 | #if EXTCLK_PIN == EXTCLK_PIN_P1_15
614 |   /* P1.15 */
615 |   PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk;
616 |   PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos);
617 | #else
618 |   /* P0.8 */
619 |   PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk;
620 |   PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk;
621 |   PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos);
622 | #endif
623 | 
624 | #endif  /* ENABLE_EXTCLK == 1  */
625 | 
626 |   SystemCoreClockUpdate();
627 | }
628 | 
629 | __WEAK void SystemCoreClockUpdate(void)
630 | {
631 |   uint32_t pdiv;
632 |   uint32_t ndiv;
633 |   uint32_t kdiv;
634 |   uint32_t temp;
635 | 
636 |   if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk)
637 |   {
638 |     /* fPLL is clock source for fSYS */
639 |     if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk)
640 |     {
641 |       /* PLL input clock is the backup clock (fOFI) */
642 |       temp = OFI_FREQUENCY;
643 |     }
644 |     else
645 |     {
646 |       /* PLL input clock is the high performance osicllator (fOSCHP) */
647 |       temp = OSCHP_GetFrequency();
648 |     }
649 | 
650 |     /* check if PLL is locked */
651 |     if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)
652 |     {
653 |       /* PLL normal mode */
654 |       /* read back divider settings */
655 |       pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1;
656 |       ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1;
657 |       kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1;
658 | 
659 |       temp = (temp / (pdiv * kdiv)) * ndiv;
660 |     }
661 |     else
662 |     {
663 |       /* PLL prescalar mode */
664 |       /* read back divider settings */
665 |       kdiv  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1;
666 |       
667 |       temp = (temp / kdiv);
668 |     }
669 |   }
670 |   else
671 |   {
672 |     /* fOFI is clock source for fSYS */    
673 |     temp = OFI_FREQUENCY;
674 |   }
675 | 
676 |   temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1);
677 |   temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1);
678 | 
679 |   SystemCoreClock = temp;
680 | }
681 | 
682 | __WEAK uint32_t OSCHP_GetFrequency(void)
683 | {
684 |   return OSCHP_FREQUENCY;
685 | }
686 | 


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/RTE/_Target_1/RTE_Components.h:
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 1 | 
 2 | /*
 3 |  * Auto generated Run-Time-Environment Component Configuration File
 4 |  *      *** Do not modify ! ***
 5 |  *
 6 |  * Project: 'PMSM_FOC' 
 7 |  * Target:  'Target 1' 
 8 |  */
 9 | 
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 | 
13 | 
14 | /*
15 |  * Define the Device Header File: 
16 |  */
17 | #define CMSIS_device_header "XMC4400.h"
18 | 
19 | #define RTE_DEVICE
20 | #define RTE_DEVICE_STARTUP
21 | #define RTE_DEVICE_XMCLIB_DAC
22 | #define RTE_DEVICE_XMCLIB_GPIO
23 | #define RTE_DEVICE_XMCLIB_SCU
24 | #define RTE_DEVICE_XMCLIB_UART
25 | 
26 | #endif /* RTE_COMPONENTS_H */
27 | 


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/SYS_Init/MCU_Initialize.h:
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/SYS_Init/VAR_Initialize.c:
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/Sensorless_Lib/PMSM_FOC.lib:
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/Sensorless_Lib/SVPWM.lib:
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