├── .gitignore ├── README.md ├── examples ├── ex-data │ └── data.csv ├── ex-json │ ├── ic_algo.json │ └── rsi.json └── gen-verilog │ ├── ic_algo.v │ ├── rsi.v │ └── rsi_tb.v ├── schematics ├── fp_gt_schematic.png ├── ichimoku_schematic.png └── rsi_schematic.png └── src ├── analysis └── profit_analyzer.py ├── fpu ├── fp_gt.v ├── skeleton_files │ └── fp_txt_in.v └── tests │ ├── ex │ ├── fp_gt │ └── fp_txt_in │ ├── fp_gt_tb.v │ └── vcd │ ├── fp_gt.vcd │ ├── fp_txt_in.vcd │ └── rsi_txt_in.vcd └── generator ├── gen_testbench.py └── gen_verilog.py /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NaregAmirianMegan/hft-verilog-generator/HEAD/README.md -------------------------------------------------------------------------------- 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