├── .gitignore ├── .gitmodules ├── APACHE-LICENSE-2.0.txt ├── Makefile ├── NetFPGA-CIC-LICENSE.md ├── README ├── RELEASE_NOTES ├── hw ├── contrib-projects │ └── .keep ├── lib │ ├── common │ │ ├── constraints │ │ │ ├── au200_general.xdc │ │ │ ├── au200_vcu1525_timing.tcl │ │ │ ├── au250_general.xdc │ │ │ ├── au250_timing.tcl │ │ │ ├── au280_general.xdc │ │ │ ├── au280_timing.tcl │ │ │ ├── nf_timing.tcl │ │ │ └── vcu1525_general.xdc │ │ └── hdl │ │ │ ├── nf_attachment.sv │ │ │ ├── top.v │ │ │ └── top_wrapper.sv │ ├── contrib │ │ └── nf_endianess_manager_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── hdl │ │ │ ├── bridge.v │ │ │ └── nf_endianess_manager.v │ │ │ └── nf_endianess_manager.tcl │ ├── std │ │ ├── axi_sim_transactor_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── axi_sim_transactor.tcl │ │ │ └── hdl │ │ │ │ ├── axi_sim_transactor.vhd │ │ │ │ └── transactor_fifos.vhd │ │ ├── axis_fifo_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── axis_fifo.tcl │ │ │ └── hdl │ │ │ │ └── axis_fifo.v │ │ ├── axis_sim_pkg_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── axis_sim_pkg.tcl │ │ │ └── hdl │ │ │ │ └── axis_sim_pkg.vhd │ │ ├── axis_sim_record_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── axis_sim_record.tcl │ │ │ └── hdl │ │ │ │ └── axis_sim_record.v │ │ ├── axis_sim_stim_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── axis_sim_stim.tcl │ │ │ └── hdl │ │ │ │ └── axis_sim_stim.vhd │ │ ├── barrier_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── barrier.tcl │ │ │ └── hdl │ │ │ │ └── barrier.v │ │ ├── fallthrough_small_fifo_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── fallthrough_small_fifo.tcl │ │ │ └── hdl │ │ │ │ ├── fallthrough_small_fifo.v │ │ │ │ └── small_fifo.v │ │ ├── input_arbiter_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── data │ │ │ │ ├── input_arbiter_regs_defines.h │ │ │ │ ├── input_arbiter_regs_defines.tcl │ │ │ │ ├── input_arbiter_regs_defines.txt │ │ │ │ └── module_generation_Input_arbiter.xlsm │ │ │ ├── hdl │ │ │ │ ├── input_arbiter.v │ │ │ │ ├── input_arbiter_cpu_regs.v │ │ │ │ └── input_arbiter_cpu_regs_defines.v │ │ │ └── input_arbiter.tcl │ │ ├── nf_axis_converter_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── hdl │ │ │ │ ├── nf_axis_converter.v │ │ │ │ └── nf_axis_converter_main.v │ │ │ └── nf_axis_converter.tcl │ │ ├── nf_mac_attachment_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── hdl │ │ │ │ ├── data_synch.v │ │ │ │ ├── nf_mac_attachment.v │ │ │ │ ├── nf_mac_attachment_cpu_regs.v │ │ │ │ ├── nf_mac_attachment_cpu_regs_defines.v │ │ │ │ ├── rx_queue.v │ │ │ │ └── tx_queue.v │ │ │ └── nf_mac_attachment_tcl.tcl │ │ ├── nic_output_port_lookup_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── data │ │ │ │ ├── module_generation_nic_opl.xlsm │ │ │ │ ├── output_port_lookup_regs_defines.h │ │ │ │ ├── output_port_lookup_regs_defines.tcl │ │ │ │ └── output_port_lookup_regs_defines.txt │ │ │ ├── hdl │ │ │ │ ├── nic_output_port_lookup.v │ │ │ │ ├── output_port_lookup_cpu_regs.v │ │ │ │ └── output_port_lookup_cpu_regs_defines.v │ │ │ └── nic_output_port_lookup.tcl │ │ ├── output_queues_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── data │ │ │ │ ├── module_generation_output_queues.xlsm │ │ │ │ ├── output_queues_regs_defines.h │ │ │ │ ├── output_queues_regs_defines.tcl │ │ │ │ └── output_queues_regs_defines.txt │ │ │ ├── hdl │ │ │ │ ├── output_queues.v │ │ │ │ ├── output_queues_cpu_regs.v │ │ │ │ └── output_queues_cpu_regs_defines.v │ │ │ └── output_queues.tcl │ │ ├── router_output_port_lookup_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── data │ │ │ │ ├── output_port_lookup_regs_defines.h │ │ │ │ ├── output_port_lookup_regs_defines.tcl │ │ │ │ └── output_port_lookup_regs_defines.txt │ │ │ ├── hdl │ │ │ │ ├── dest_ip_filter.v │ │ │ │ ├── eth_parser.v │ │ │ │ ├── ip_arp.v │ │ │ │ ├── ip_checksum_ttl.v │ │ │ │ ├── ip_lpm.v │ │ │ │ ├── op_lut_hdr_parser.v │ │ │ │ ├── op_lut_process_sm.v │ │ │ │ ├── output_port_lookup.v │ │ │ │ ├── output_port_lookup_cpu_regs.v │ │ │ │ ├── output_port_lookup_cpu_regs_defines.v │ │ │ │ ├── preprocess_control.v │ │ │ │ ├── router_output_port_lookup.v │ │ │ │ └── unencoded_cam_lut_sm.v │ │ │ └── router_output_port_lookup.tcl │ │ ├── switch_lite_output_port_lookup_v1_0_0 │ │ │ ├── Makefile │ │ │ ├── data │ │ │ │ ├── module_generation_switch_opl.xlsm │ │ │ │ ├── output_port_lookup_regs_defines.h │ │ │ │ ├── output_port_lookup_regs_defines.tcl │ │ │ │ └── output_port_lookup_regs_defines.txt │ │ │ ├── hdl │ │ │ │ ├── eth_parser.v │ │ │ │ ├── mac_cam_lut.v │ │ │ │ ├── output_port_lookup_cpu_regs.v │ │ │ │ ├── output_port_lookup_cpu_regs_defines.v │ │ │ │ └── switch_lite_output_port_lookup.v │ │ │ └── switch_lite_output_port_lookup.tcl │ │ └── switch_output_port_lookup_v1_0_1 │ │ │ ├── Makefile │ │ │ ├── data │ │ │ ├── module_generation_switch_opl.xlsm │ │ │ ├── output_port_lookup_regs_defines.h │ │ │ ├── output_port_lookup_regs_defines.tcl │ │ │ └── output_port_lookup_regs_defines.txt │ │ │ ├── hdl │ │ │ ├── eth_parser.v │ │ │ ├── mac_cam_lut.v │ │ │ ├── output_port_lookup_cpu_regs.v │ │ │ ├── output_port_lookup_cpu_regs_defines.v │ │ │ └── switch_output_port_lookup.v │ │ │ └── switch_output_port_lookup.tcl │ └── xilinx │ │ ├── cam_v1_1_0 │ │ ├── Makefile │ │ ├── README │ │ ├── cam.tcl │ │ ├── hdl │ │ │ ├── verilog │ │ │ │ ├── cam.v │ │ │ │ └── cam_wrapper.v │ │ │ └── vhdl │ │ │ │ └── cam │ │ │ │ └── .keep │ │ └── scripts │ │ │ └── run_update_lib.sh │ │ ├── tcam_v1_1_0 │ │ ├── Makefile │ │ ├── README │ │ ├── hdl │ │ │ ├── verilog │ │ │ │ ├── tcam.v │ │ │ │ └── tcam_wrapper.v │ │ │ └── vhdl │ │ │ │ └── tcam │ │ │ │ └── .keep │ │ ├── scripts │ │ │ └── run_update_lib.sh │ │ ├── sim │ │ │ ├── run_sim.tcl │ │ │ ├── run_tcam_sim.sh │ │ │ └── testbench.v │ │ └── tcam.tcl │ │ └── xilinx_shell_v1_0_0 │ │ ├── Makefile │ │ ├── hdl │ │ └── open_nic_shell.sv │ │ ├── update.sh │ │ ├── vivado_ip │ │ ├── .keep │ │ ├── qdma_subsystem_axi_cdc.tcl │ │ └── qdma_subsystem_clk_div.tcl │ │ └── xilinx_shell.tcl └── projects │ ├── reference_nic │ ├── bitfiles │ │ └── README │ ├── hw │ │ ├── Makefile │ │ ├── constraints │ │ │ └── au200_vcu1525_user_timing.tcl │ │ ├── hdl │ │ │ ├── nf_datapath.v │ │ │ ├── top_sim.v │ │ │ └── top_tb.v │ │ └── tcl │ │ │ ├── export_registers.tcl │ │ │ ├── reference_nic.tcl │ │ │ ├── reference_nic_defines.tcl │ │ │ └── reference_nic_sim.tcl │ └── test │ │ ├── both_inc_size │ │ └── run.py │ │ ├── both_loopback_maxsize │ │ └── run.py │ │ ├── both_loopback_minsize │ │ └── run.py │ │ ├── both_loopback_random │ │ └── run.py │ │ ├── connections │ │ └── conn │ │ └── global │ │ └── setup │ ├── reference_router │ ├── bitfiles │ │ └── README │ ├── hw │ │ ├── Makefile │ │ ├── constraints │ │ │ └── au200_vcu1525_user_timing.tcl │ │ ├── hdl │ │ │ ├── nf_datapath.v │ │ │ ├── top_sim.v │ │ │ └── top_tb.v │ │ └── tcl │ │ │ ├── export_registers.tcl │ │ │ ├── reference_router.tcl │ │ │ ├── reference_router_defines.tcl │ │ │ └── reference_router_sim.tcl │ ├── lib │ │ └── Python │ │ │ ├── RegressRouterLib.py │ │ │ └── RouterLib.py │ ├── sw │ │ ├── apps │ │ │ ├── Makefile │ │ │ ├── register_read.sh │ │ │ ├── register_write.sh │ │ │ └── rwaxi.c │ │ ├── cli │ │ │ ├── Makefile │ │ │ ├── arp │ │ │ ├── cli.c │ │ │ ├── ip │ │ │ └── mac │ │ ├── common │ │ │ ├── Makefile │ │ │ ├── nf_sume.h │ │ │ ├── nf_util.c │ │ │ ├── nf_util.h │ │ │ ├── nfplus_util.c │ │ │ └── nfplus_util.h │ │ ├── router_kit │ │ │ ├── Makefile │ │ │ ├── arptable.hh │ │ │ ├── iflist.hh │ │ │ ├── linux_proc_net.cc │ │ │ ├── linux_proc_net.hh │ │ │ ├── netinet++ │ │ │ │ ├── ethernetaddr.hh │ │ │ │ └── ipaddr.hh │ │ │ ├── rkd.cc │ │ │ ├── rtable.hh │ │ │ ├── sume_mon.cc │ │ │ └── sume_mon.hh │ │ └── scone │ │ │ ├── Makefile │ │ │ ├── README │ │ │ ├── TODO.txt │ │ │ ├── cpuhw │ │ │ ├── design_doc.pdf │ │ │ ├── getarg.c │ │ │ ├── lwtcp │ │ │ ├── api_lib.c │ │ │ ├── api_msg.c │ │ │ ├── err.c │ │ │ ├── icmp.c │ │ │ ├── inet.c │ │ │ ├── ip_addr.c │ │ │ ├── lwtcp_sr_integration.h │ │ │ ├── main.c │ │ │ ├── mem.c │ │ │ ├── memp.c │ │ │ ├── pbuf.c │ │ │ ├── sockets.c │ │ │ ├── stats.c │ │ │ ├── sys.c │ │ │ ├── sys_arch.c │ │ │ ├── tcp.c │ │ │ ├── tcp_input.c │ │ │ ├── tcp_output.c │ │ │ ├── tcpip.c │ │ │ ├── transport_subsys.c │ │ │ └── udp.c │ │ │ ├── or_arp.c │ │ │ ├── or_arp.h │ │ │ ├── or_cli.c │ │ │ ├── or_cli.h │ │ │ ├── or_data_types.h │ │ │ ├── or_dijkstra.c │ │ │ ├── or_dijkstra.h │ │ │ ├── or_dijkstra_test.c │ │ │ ├── or_icmp.c │ │ │ ├── or_icmp.h │ │ │ ├── or_iface.c │ │ │ ├── or_iface.h │ │ │ ├── or_ip.c │ │ │ ├── or_ip.h │ │ │ ├── or_main.c │ │ │ ├── or_main.h │ │ │ ├── or_nat.c │ │ │ ├── or_nat.h │ │ │ ├── or_netfpga.c │ │ │ ├── or_netfpga.h │ │ │ ├── or_output.c │ │ │ ├── or_output.h │ │ │ ├── or_pwospf.c │ │ │ ├── or_pwospf.h │ │ │ ├── or_rtable.c │ │ │ ├── or_rtable.h │ │ │ ├── or_sping.c │ │ │ ├── or_sping.h │ │ │ ├── or_utils.c │ │ │ ├── or_utils.h │ │ │ ├── or_vns.c │ │ │ ├── or_vns.h │ │ │ ├── or_www.c │ │ │ ├── or_www.h │ │ │ ├── rawsock.c │ │ │ ├── rtables │ │ │ ├── rtable │ │ │ ├── rtable.netfpga │ │ │ ├── rtable.regress1 │ │ │ ├── rtable.vhost1 │ │ │ ├── rtable.vhost1.pwospf │ │ │ ├── rtable.vhost2 │ │ │ ├── rtable.vhost2.pwospf │ │ │ ├── rtable.vhost3 │ │ │ ├── rtable.vhost3.pwospf │ │ │ ├── rtable2.vhost1.pwospf │ │ │ ├── rtable2.vhost2.pwospf │ │ │ └── rtable2.vhost3.pwospf │ │ │ ├── sr_base.c │ │ │ ├── sr_base.h │ │ │ ├── sr_base_internal.h │ │ │ ├── sr_cpu_extension_nf.c │ │ │ ├── sr_cpu_extension_nf.h │ │ │ ├── sr_dumper.c │ │ │ ├── sr_dumper.h │ │ │ ├── sr_integration.c │ │ │ ├── sr_lwtcp_glue.c │ │ │ ├── sr_lwtcp_glue.h │ │ │ ├── sr_main.c │ │ │ ├── sr_vns.c │ │ │ ├── sr_vns.h │ │ │ ├── vnscommand.h │ │ │ └── www │ │ │ ├── content.html │ │ │ ├── footer.html │ │ │ ├── gradient_1.gif │ │ │ ├── header.html │ │ │ ├── index.html │ │ │ ├── left.html │ │ │ ├── main.css │ │ │ ├── our_router.js │ │ │ ├── prototype.js │ │ │ ├── refresh.png │ │ │ └── router.png │ └── test │ │ ├── both_arp_misses │ │ └── run.py │ │ ├── both_badipchksum_packet │ │ └── run.py │ │ ├── both_invalidttl_packet │ │ └── run.py │ │ ├── both_ipdestfilter_hit │ │ └── run.py │ │ ├── both_lpm_generic │ │ └── run.py │ │ ├── both_lpm_misses │ │ └── run.py │ │ ├── both_lpm_nexthop │ │ └── run.py │ │ ├── both_nonip_packet │ │ └── run.py │ │ ├── both_nonipv4_packet │ │ └── run.py │ │ ├── both_packet_forwarding │ │ └── run.py │ │ ├── both_router_table │ │ └── run.py │ │ ├── both_wrong_destMAC │ │ └── run.py │ │ ├── connections │ │ └── conn │ │ └── global │ │ └── setup │ ├── reference_switch │ ├── bitfiles │ │ └── README │ ├── hw │ │ ├── Makefile │ │ ├── constraints │ │ │ └── au250_au200_vcu1525_user_timing.tcl │ │ ├── hdl │ │ │ ├── nf_datapath.v │ │ │ ├── top_sim.v │ │ │ └── top_tb.v │ │ └── tcl │ │ │ ├── export_registers.tcl │ │ │ ├── reference_switch.tcl │ │ │ ├── reference_switch_defines.tcl │ │ │ └── reference_switch_sim.tcl │ └── test │ │ ├── both_learning_sw │ │ └── run.py │ │ ├── both_simple_broadcast │ │ └── run.py │ │ ├── connections │ │ └── conn │ │ └── global │ │ └── setup │ └── reference_switch_lite │ ├── bitfiles │ └── README │ ├── hw │ ├── Makefile │ ├── constraints │ │ └── au200_vcu1525_user_timing.tcl │ ├── hdl │ │ ├── nf_datapath.v │ │ ├── top_sim.v │ │ └── top_tb.v │ └── tcl │ │ ├── export_registers.tcl │ │ ├── reference_switch_lite.tcl │ │ ├── reference_switch_lite_defines.tcl │ │ └── reference_switch_lite_sim.tcl │ └── test │ ├── both_learning_sw │ └── run.py │ ├── both_simple_broadcast │ └── run.py │ ├── connections │ └── conn │ └── global │ └── setup ├── sw ├── app │ ├── Makefile │ └── main.c ├── driver │ ├── Makefile │ └── opennic-driver.patch └── hwtestlib │ ├── Makefile │ └── sume_reg.c └── tools ├── scripts ├── NFTest │ ├── NFTest │ │ ├── Makefile │ │ ├── NFTestHeader.py │ │ ├── NFTestLib.py │ │ ├── PacketLib.py │ │ ├── __init__.py │ │ ├── hwPkt.py │ │ ├── hwPktLib.py │ │ ├── hwReg.py │ │ ├── hwRegLib.py │ │ ├── scapy_sniff_patch.py │ │ ├── simLib.py │ │ ├── simPkt.py │ │ └── simReg.py │ └── testcheck.py ├── axitools.py ├── nf_sim_reconcile_axi_logs.py ├── nf_sim_registers_axi_logs.py ├── nf_test.py ├── pci_rescan_run.sh ├── python_parser.py └── xparam2regdefines.py └── settings.sh /.gitignore: -------------------------------------------------------------------------------- 1 | *.bit 2 | *.ltx 3 | *.zip 4 | *.log 5 | *.o 6 | *.ko 7 | *.cmd 8 | *.mod 9 | *.mod.c 10 | *.axi 11 | *.so 12 | *.sim 13 | *.d 14 | *.a 15 | *.backup.jou 16 | vivado.log 17 | vivado.jou 18 | xvlog.pb 19 | xvlog.log 20 | xsim.dir 21 | seed 22 | __pycache__ 23 | usage_statistics_webtalk.html 24 | usage_statistics_webtalk.xml 25 | nf_register_defines.h 26 | reg_defines.h 27 | lib_pkg_v1_0_rfs.vhd 28 | lib_srl_fifo_v1_0_rfs.vhd 29 | rwaxi 30 | rkd 31 | xgui 32 | ip_repo 33 | ip_proj 34 | proj 35 | project 36 | component.xml 37 | Module.symvers 38 | modules.order 39 | xapp1151_cam_v1_1 40 | sw/driver/.updated.txt 41 | hw/lib/std/axi_sim_transactor_v1_0_0/hdl/axis_sim_pkg/ 42 | hw/lib/xilinx/cam_v1_1_0/hdl/vhdl/cam/*.vhd 43 | hw/lib/xilinx/tcam_v1_1_0/hdl/vhdl/tcam/*.vhd 44 | hw/projects/*/test/Makefile 45 | reg_defines_*.py 46 | hw/projects/reference_nic/sw/ 47 | hw/projects/reference_switch/sw/ 48 | hw/projects/reference_switch_lite/sw/ 49 | tools/scripts/NFTest/testcheck.pyc 50 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "sw/driver/open-nic-driver"] 2 | path = sw/driver/open-nic-driver 3 | url = https://github.com/Xilinx/open-nic-driver.git 4 | [submodule "hw/lib/xilinx/xilinx_shell_v1_0_0/open-nic-shell"] 5 | path = hw/lib/xilinx/xilinx_shell_v1_0_0/open-nic-shell 6 | url = https://github.com/Xilinx/open-nic-shell.git 7 | -------------------------------------------------------------------------------- /NetFPGA-CIC-LICENSE.md: -------------------------------------------------------------------------------- 1 | [![](https://github.com/NetFPGA/NetFPGA-public/blob/master/netfpga.png)](http://www.netfpga.org) 2 | 3 | 4 | 5 | 6 | [NetFPGA license and agreements](http://netfpga-cic.org/) 7 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2021 Yuta Tokusashi 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC EARL Project EP/P025374/1 alongside support 7 | # from Xilinx Inc. 8 | # 9 | # @NETFPGA_LICENSE_HEADER_START@ 10 | # 11 | # Licensed under the Apache License, Version 2.0 (the "License"); 12 | # you may not use this file except in compliance with the License. 13 | # You may obtain a copy of the License at 14 | # 15 | # http://www.apache.org/licenses/LICENSE-2.0 16 | # 17 | # Unless required by applicable law or agreed to in writing, software 18 | # distributed under the License is distributed on an "AS IS" BASIS, 19 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | # See the License for the specific language governing permissions and 21 | # limitations under the License. 22 | # 23 | # @NETFPGA_LICENSE_HEADER_END@ 24 | # 25 | 26 | Welcome to the NetFPGA-PLUS base package. 27 | 28 | For documentation on its content and use, as well as general 29 | information on the NetFPGA-SUME platform, please visit the 30 | documentation wiki: 31 | 32 | https://github.com/NetFPGA/NetFPGA-PLUS/wiki 33 | 34 | The wiki additionally contains a useful "Getting Started Guide" 35 | for new users, which can be found here: 36 | 37 | https://github.com/NetFPGA/NetFPGA-PLUS/wiki/Getting-Started-Guide 38 | 39 | Have fun! 40 | -------------------------------------------------------------------------------- /RELEASE_NOTES: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2021 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by Stanford University and the University of Cambridge Computer Laboratory 6 | # under National Science Foundation under Grant No. CNS-0855268, 7 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 8 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 9 | # as part of the DARPA MRC research programme, 10 | # and by the University of Cambridge Computer Laboratory under EPSRC EARL Project 11 | # EP/P025374/1 alongside support from Xilinx Inc. 12 | # 13 | # @NETFPGA_LICENSE_HEADER_START@ 14 | # 15 | # Licensed under the Apache License, Version 2.0 (the "License"); 16 | # you may not use this file except in compliance with the License. 17 | # You may obtain a copy of the License at 18 | # 19 | # http://www.apache.org/licenses/LICENSE-2.0 20 | # 21 | # Unless required by applicable law or agreed to in writing, software 22 | # distributed under the License is distributed on an "AS IS" BASIS, 23 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | # See the License for the specific language governing permissions and 25 | # limitations under the License. 26 | # 27 | # @NETFPGA_LICENSE_HEADER_END@ 28 | # 29 | GIT VERSION 1.1.0 30 | 31 | This release contains: 32 | 1. Designs 33 | - support Vivado 2023.2 34 | - support OpenNIC Shell open-nic-shell (commit: 8077751) 35 | - support OpenNIC Driver open-nic-driver (commit: cbac3b9) 36 | 37 | 38 | -------------------------------------------------------------------------------- /hw/contrib-projects/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/contrib-projects/.keep -------------------------------------------------------------------------------- /hw/lib/common/constraints/au200_vcu1525_timing.tcl: -------------------------------------------------------------------------------- 1 | # ************************************************************************* 2 | # 3 | # Copyright 2020 Xilinx, Inc. 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # ************************************************************************* 18 | create_clock -period 4.000 -name axis_aclk [get_nets u_top_wrapper/axis_aclk] 19 | set_false_path -through [get_ports pci_rst_n] 20 | 21 | set axis_aclk [get_clocks -of_object [get_nets u_top_wrapper/axis_aclk]] 22 | foreach cmac_clk [get_clocks -of_object [get_nets u_top_wrapper/cmac_clk*]] { 23 | set_max_delay -datapath_only -from $axis_aclk -to $cmac_clk 4.000 24 | set_max_delay -datapath_only -from $cmac_clk -to $axis_aclk 3.103 25 | } 26 | -------------------------------------------------------------------------------- /hw/lib/common/constraints/au250_timing.tcl: -------------------------------------------------------------------------------- 1 | # ************************************************************************* 2 | # 3 | # Copyright 2020 Xilinx, Inc. 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # ************************************************************************* 18 | # QDMA clock 19 | set_false_path -through [get_ports pci_rst_n] 20 | 21 | set axis_aclk [get_clocks -of_object [get_nets u_top_wrapper/axis_aclk]] 22 | foreach cmac_clk [get_clocks -of_object [get_nets u_top_wrapper/cmac_clk*]] { 23 | set_max_delay -datapath_only -from $axis_aclk -to $cmac_clk 4.000 24 | set_max_delay -datapath_only -from $cmac_clk -to $axis_aclk 3.103 25 | } 26 | 27 | create_pblock pblock_qdma_subsystem 28 | add_cells_to_pblock [get_pblocks pblock_qdma_subsystem] [get_cells -quiet [list u_top_wrapper/xilinx_nic_shell/inst/qdma_subsystem_inst]] 29 | resize_pblock [get_pblocks pblock_qdma_subsystem] -add {SLR1} 30 | -------------------------------------------------------------------------------- /hw/lib/common/constraints/au280_timing.tcl: -------------------------------------------------------------------------------- 1 | # ************************************************************************* 2 | # 3 | # Copyright 2020 Xilinx, Inc. 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # ************************************************************************* 18 | create_clock -period 4.000 -name axis_aclk [get_nets u_top_wrapper/axis_aclk] 19 | set_false_path -through [get_ports pci_rst_n] 20 | 21 | set axis_aclk [get_clocks -of_object [get_nets u_top_wrapper/axis_aclk]] 22 | foreach cmac_clk [get_clocks -of_object [get_nets u_top_wrapper/cmac_clk*]] { 23 | set_max_delay -datapath_only -from $axis_aclk -to $cmac_clk 4.000 24 | set_max_delay -datapath_only -from $cmac_clk -to $axis_aclk 3.103 25 | } 26 | 27 | create_pblock pblock_qdma_subsystem 28 | add_cells_to_pblock [get_pblocks pblock_qdma_subsystem] [get_cells -quiet [list u_top_wrapper/xilinx_nic_shell/inst/qdma_subsystem_inst]] 29 | resize_pblock [get_pblocks pblock_qdma_subsystem] -add {SLR0} 30 | 31 | create_pblock pblock_cmac_subsystem 32 | add_cells_to_pblock [get_pblocks pblock_cmac_subsystem] [get_cells -quiet {u_top_wrapper/xilinx_nic_shell/inst/cmac_port*.cmac_subsystem_inst}] 33 | resize_pblock [get_pblocks pblock_cmac_subsystem] -add {SLR2} 34 | 35 | create_pblock pblock_nf_datapath 36 | add_cells_to_pblock [get_pblocks pblock_nf_datapath] [get_cells -quiet [list nf_datapath_0]] 37 | add_cells_to_pblock [get_pblocks pblock_nf_datapath] [get_cells -quiet [list u_top_wrapper/u_nf_attachment]] 38 | resize_pblock [get_pblocks pblock_nf_datapath] -add {SLR1} 39 | 40 | # This false paths should be removed (ToDo) 41 | set_false_path -from [get_cells u_top_wrapper/u_nf_attachment/u_nf_attachment_0/inst/tx_fifo_rst/sync1_r_reg[5]] 42 | set_false_path -from [get_cells u_top_wrapper/u_nf_attachment/u_nf_attachment_1/inst/tx_fifo_rst/sync1_r_reg[5]] 43 | set_false_path -from [get_cells u_top_wrapper/u_nf_attachment/u_nf_attachment_0/inst/rx_fifo_rst/sync1_r_reg[5]] 44 | set_false_path -from [get_cells u_top_wrapper/u_nf_attachment/u_nf_attachment_1/inst/rx_fifo_rst/sync1_r_reg[5]] 45 | -------------------------------------------------------------------------------- /hw/lib/common/constraints/nf_timing.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2021 Yuta Tokusashi 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC EARL Project EP/P025374/1 alongside support 7 | # from Xilinx Inc. 8 | # 9 | # @NETFPGA_LICENSE_HEADER_START@ 10 | # 11 | # Licensed under the Apache License, Version 2.0 (the "License"); 12 | # you may not use this file except in compliance with the License. 13 | # You may obtain a copy of the License at 14 | # 15 | # http://www.apache.org/licenses/LICENSE-2.0 16 | # 17 | # Unless required by applicable law or agreed to in writing, software 18 | # distributed under the License is distributed on an "AS IS" BASIS, 19 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | # See the License for the specific language governing permissions and 21 | # limitations under the License. 22 | # 23 | # @NETFPGA_LICENSE_HEADER_END@ 24 | # 25 | 26 | create_pblock pblock_nf_datapath 27 | add_cells_to_pblock [get_pblocks pblock_nf_datapath] [get_cells -quiet [list nf_datapath_0]] 28 | add_cells_to_pblock [get_pblocks pblock_nf_datapath] [get_cells -quiet [list u_top_wrapper/u_nf_attachment]] 29 | resize_pblock [get_pblocks pblock_nf_datapath] -add {SLR1} 30 | -------------------------------------------------------------------------------- /hw/lib/contrib/nf_endianess_manager_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | all: clean 29 | vivado -mode batch -source nf_endianess_manager.tcl 30 | 31 | clean: 32 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 33 | -------------------------------------------------------------------------------- /hw/lib/std/axi_sim_transactor_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Georgina Kalogeridou 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | all: clean 30 | vivado -mode batch -source axi_sim_transactor.tcl 31 | 32 | clean: 33 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* ip_pro* *.*~ *.zip hdl/axis_sim_pkg/ hdl/lib_srl_fifo hdl/lib_srl_fifo_v1_0 hdl/lib_pkg hdl/lib_pkg_v1_0 34 | -------------------------------------------------------------------------------- /hw/lib/std/axis_fifo_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | all: clean 29 | vivado -mode batch -source axis_fifo.tcl 30 | 31 | clean: 32 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 33 | -------------------------------------------------------------------------------- /hw/lib/std/axis_sim_pkg_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Georgina Kalogeridou 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | 30 | all: clean 31 | vivado -mode batch -source axis_sim_pkg.tcl 32 | 33 | clean: 34 | rm -rf vivado*.* *.xml xgui/ .Xil* ip_pro* 35 | -------------------------------------------------------------------------------- /hw/lib/std/axis_sim_pkg_v1_0_0/axis_sim_pkg.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Georgina Kalogeridou 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | 30 | # Set variables. 31 | set design axis_sim_pkg 32 | set device $::env(DEVICE) 33 | set proj_dir ./ip_proj 34 | set ip_version 1.0 35 | set lib_name NetFPGA 36 | 37 | # Project setting. 38 | create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} -ip 39 | set_property source_mgmt_mode All [current_project] 40 | set_property top ${design} [current_fileset] 41 | set_property ip_repo_paths $::env(NFPLUS_FOLDER)/hw/lib/ [current_fileset] 42 | update_ip_catalog 43 | 44 | # IP build. 45 | read_vhdl "./hdl/axis_sim_pkg.vhd" 46 | update_compile_order -fileset sources_1 47 | update_compile_order -fileset sim_1 48 | ipx::package_project 49 | 50 | set_property name ${design} [ipx::current_core] 51 | set_property library ${lib_name} [ipx::current_core] 52 | set_property vendor_display_name {NetFPGA} [ipx::current_core] 53 | set_property company_url {http://www.netfpga.org} [ipx::current_core] 54 | set_property vendor {NetFPGA} [ipx::current_core] 55 | set_property supported_families {{virtexuplus} {Production} {virtexuplushbm} {Production}} [ipx::current_core] 56 | set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core] 57 | set_property version ${ip_version} [ipx::current_core] 58 | set_property display_name ${design} [ipx::current_core] 59 | set_property description ${design} [ipx::current_core] 60 | 61 | update_ip_catalog -rebuild 62 | ipx::infer_user_parameters [ipx::current_core] 63 | ipx::check_integrity [ipx::current_core] 64 | ipx::save_core [ipx::current_core] 65 | update_ip_catalog 66 | close_project 67 | 68 | 69 | 70 | 71 | -------------------------------------------------------------------------------- /hw/lib/std/axis_sim_record_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Georgina Kalogeridou 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | all: clean 30 | vivado -mode batch -source axis_sim_record.tcl 31 | 32 | clean: 33 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* ip_pro* *.*~ *.zip 34 | -------------------------------------------------------------------------------- /hw/lib/std/axis_sim_stim_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Georgina Kalogeridou 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | all: clean 30 | vivado -mode batch -source axis_sim_stim.tcl 31 | 32 | clean: 33 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* ip_pro* *.*~ *.zip hdl/axis_sim_pkg/ 34 | -------------------------------------------------------------------------------- /hw/lib/std/axis_sim_stim_v1_0_0/axis_sim_stim.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Georgina Kalogeridou 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | # Set variables. 30 | set design axis_sim_stim 31 | set device $::env(DEVICE) 32 | set proj_dir ./ip_proj 33 | set ip_version 1.0 34 | set lib_name NetFPGA 35 | 36 | set axis_sim_pkg_path ../axis_sim_pkg_v1_0_0/hdl/ 37 | 38 | # Project setting. 39 | create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} -ip 40 | set_property source_mgmt_mode All [current_project] 41 | set_property top ${design} [current_fileset] 42 | set_property ip_repo_paths $::env(NFPLUS_FOLDER)/hw/lib/ [current_fileset] 43 | 44 | # IP build. 45 | file copy -force ${axis_sim_pkg_path}/ "./hdl/axis_sim_pkg/" 46 | read_vhdl "./hdl/axis_sim_pkg/axis_sim_pkg.vhd" 47 | update_ip_catalog 48 | read_vhdl "./hdl/axis_sim_stim.vhd" 49 | update_compile_order -fileset sources_1 50 | update_compile_order -fileset sim_1 51 | ipx::package_project 52 | 53 | set_property name ${design} [ipx::current_core] 54 | set_property library ${lib_name} [ipx::current_core] 55 | set_property vendor_display_name {NetFPGA} [ipx::current_core] 56 | set_property company_url {http://www.netfpga.org} [ipx::current_core] 57 | set_property vendor {NetFPGA} [ipx::current_core] 58 | set_property supported_families {{virtexuplus} {Production} {virtexuplushbm} {Production}} [ipx::current_core] 59 | set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core] 60 | set_property version ${ip_version} [ipx::current_core] 61 | set_property display_name ${design} [ipx::current_core] 62 | set_property description ${design} [ipx::current_core] 63 | 64 | update_ip_catalog -rebuild 65 | ipx::infer_user_parameters [ipx::current_core] 66 | 67 | ipx::check_integrity [ipx::current_core] 68 | ipx::save_core [ipx::current_core] 69 | update_ip_catalog 70 | close_project 71 | -------------------------------------------------------------------------------- /hw/lib/std/barrier_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Georgina Kalogeridou 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | all: clean 30 | vivado -mode batch -source barrier.tcl 31 | 32 | clean: 33 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* ip_pro* *.*~ *.zip 34 | -------------------------------------------------------------------------------- /hw/lib/std/barrier_v1_0_0/barrier.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Georgina Kalogeridou 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | # Set variables. 30 | set design barrier 31 | set device $::env(DEVICE) 32 | set proj_dir ./ip_proj 33 | set ip_version 1.0 34 | set lib_name NetFPGA 35 | 36 | # Project setting. 37 | create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} -ip 38 | set_property source_mgmt_mode All [current_project] 39 | set_property top ${design} [current_fileset] 40 | set_property ip_repo_paths $::env(NFPLUS_FOLDER)/hw/lib/ [current_fileset] 41 | update_ip_catalog 42 | # IP build. 43 | read_verilog "./hdl/barrier.v" 44 | update_compile_order -fileset sources_1 45 | update_compile_order -fileset sim_1 46 | ipx::package_project 47 | 48 | set_property name ${design} [ipx::current_core] 49 | set_property library ${lib_name} [ipx::current_core] 50 | set_property vendor_display_name {NetFPGA} [ipx::current_core] 51 | set_property company_url {http://www.netfpga.org} [ipx::current_core] 52 | set_property vendor {NetFPGA} [ipx::current_core] 53 | set_property supported_families {{virtexuplus} {Production} {virtexuplushbm} {Production}} [ipx::current_core] 54 | set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core] 55 | set_property version ${ip_version} [ipx::current_core] 56 | set_property display_name ${design} [ipx::current_core] 57 | set_property description ${design} [ipx::current_core] 58 | 59 | update_ip_catalog -rebuild 60 | ipx::infer_user_parameters [ipx::current_core] 61 | 62 | ipx::check_integrity [ipx::current_core] 63 | ipx::save_core [ipx::current_core] 64 | update_ip_catalog 65 | close_project 66 | -------------------------------------------------------------------------------- /hw/lib/std/fallthrough_small_fifo_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | all: clean 29 | vivado -mode batch -source fallthrough_small_fifo.tcl 30 | 31 | clean: 32 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 33 | -------------------------------------------------------------------------------- /hw/lib/std/input_arbiter_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # Modified by Salvator Galea 4 | # All rights reserved. 5 | # 6 | # This software was developed by 7 | # Stanford University and the University of Cambridge Computer Laboratory 8 | # under National Science Foundation under Grant No. CNS-0855268, 9 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 10 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 11 | # as part of the DARPA MRC research programme. 12 | # 13 | # @NETFPGA_LICENSE_HEADER_START@ 14 | # 15 | # Licensed under the Apache License, Version 2.0 (the "License"); 16 | # you may not use this file except in compliance with the License. 17 | # You may obtain a copy of the License at 18 | # 19 | # http://www.apache.org/licenses/LICENSE-2.0 20 | # 21 | # Unless required by applicable law or agreed to in writing, software 22 | # distributed under the License is distributed on an "AS IS" BASIS, 23 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | # See the License for the specific language governing permissions and 25 | # limitations under the License. 26 | # 27 | # @NETFPGA_LICENSE_HEADER_END@ 28 | 29 | all: clean 30 | vivado -mode batch -source input_arbiter.tcl 31 | 32 | clean: 33 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 34 | -------------------------------------------------------------------------------- /hw/lib/std/input_arbiter_v1_0_0/data/input_arbiter_regs_defines.h: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // 6 | // File: 7 | // input_arbiter_regs_defines.h 8 | // 9 | // Description: 10 | // This file is automatically generated with header defines for the software 11 | // 12 | // This software was developed by 13 | // Stanford University and the University of Cambridge Computer Laboratory 14 | // under National Science Foundation under Grant No. CNS-0855268, 15 | // the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | // by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | // as part of the DARPA MRC research programme. 18 | // 19 | // @NETFPGA_LICENSE_HEADER_START@ 20 | // 21 | // Licensed under the Apache License, Version 2.0 (the "License"); 22 | // you may not use this file except in compliance with the License. 23 | // You may obtain a copy of the License at 24 | // 25 | // http://www.apache.org/licenses/LICENSE-2.0 26 | // 27 | // Unless required by applicable law or agreed to in writing, software 28 | // distributed under the License is distributed on an "AS IS" BASIS, 29 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | // See the License for the specific language governing permissions and 31 | // limitations under the License. 32 | // 33 | // @NETFPGA_LICENSE_HEADER_END@ 34 | // 35 | 36 | ##########This text should be copied to the head file ############# 37 | #Registers offset definitions 38 | 39 | #define NFPLUS_INPUT_ARBITER_ID_0_OFFSET 0x0 40 | #define NFPLUS_INPUT_ARBITER_ID_0_DEFAULT 0x0000DA01 41 | #define NFPLUS_INPUT_ARBITER_ID_0_WIDTH 32 42 | #define NFPLUS_INPUT_ARBITER_VERSION_0_OFFSET 0x4 43 | #define NFPLUS_INPUT_ARBITER_VERSION_0_DEFAULT 0x1 44 | #define NFPLUS_INPUT_ARBITER_VERSION_0_WIDTH 32 45 | #define NFPLUS_INPUT_ARBITER_RESET_0_OFFSET 0x8 46 | #define NFPLUS_INPUT_ARBITER_RESET_0_DEFAULT 0x0 47 | #define NFPLUS_INPUT_ARBITER_RESET_0_WIDTH 16 48 | #define NFPLUS_INPUT_ARBITER_FLIP_0_OFFSET 0xC 49 | #define NFPLUS_INPUT_ARBITER_FLIP_0_DEFAULT 0x0 50 | #define NFPLUS_INPUT_ARBITER_FLIP_0_WIDTH 32 51 | #define NFPLUS_INPUT_ARBITER_DEBUG_0_OFFSET 0x10 52 | #define NFPLUS_INPUT_ARBITER_DEBUG_0_DEFAULT 0x0 53 | #define NFPLUS_INPUT_ARBITER_DEBUG_0_WIDTH 32 54 | #define NFPLUS_INPUT_ARBITER_PKTIN_0_OFFSET 0x14 55 | #define NFPLUS_INPUT_ARBITER_PKTIN_0_DEFAULT 0x0 56 | #define NFPLUS_INPUT_ARBITER_PKTIN_0_WIDTH 32 57 | #define NFPLUS_INPUT_ARBITER_PKTOUT_0_OFFSET 0x18 58 | #define NFPLUS_INPUT_ARBITER_PKTOUT_0_DEFAULT 0x0 59 | #define NFPLUS_INPUT_ARBITER_PKTOUT_0_WIDTH 32 60 | -------------------------------------------------------------------------------- /hw/lib/std/input_arbiter_v1_0_0/data/input_arbiter_regs_defines.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # 6 | # File: 7 | # input_arbiter_regs_defines.tcl 8 | # 9 | # Description: 10 | # This file is automatically generated with tcl defines for the software 11 | # 12 | # This software was developed by 13 | # Stanford University and the University of Cambridge Computer Laboratory 14 | # under National Science Foundation under Grant No. CNS-0855268, 15 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | # as part of the DARPA MRC research programme. 18 | # 19 | # @NETFPGA_LICENSE_HEADER_START@ 20 | # 21 | # Licensed under the Apache License, Version 2.0 (the "License"); 22 | # you may not use this file except in compliance with the License. 23 | # You may obtain a copy of the License at 24 | # 25 | # http://www.apache.org/licenses/LICENSE-2.0 26 | # 27 | # Unless required by applicable law or agreed to in writing, software 28 | # distributed under the License is distributed on an "AS IS" BASIS, 29 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | # See the License for the specific language governing permissions and 31 | # limitations under the License. 32 | # 33 | # @NETFPGA_LICENSE_HEADER_END@ 34 | # 35 | 36 | set INPUT_ARBITER_REGS_ID_0_OFFSET 0x0 37 | set INPUT_ARBITER_REGS_ID_0_DEFAULT 0x0000DA01 38 | set INPUT_ARBITER_REGS_ID_0_WIDTH 32 39 | set INPUT_ARBITER_REGS_VERSION_0_OFFSET 0x4 40 | set INPUT_ARBITER_REGS_VERSION_0_DEFAULT 0x1 41 | set INPUT_ARBITER_REGS_VERSION_0_WIDTH 32 42 | set INPUT_ARBITER_REGS_RESET_0_OFFSET 0x8 43 | set INPUT_ARBITER_REGS_RESET_0_DEFAULT 0x0 44 | set INPUT_ARBITER_REGS_RESET_0_WIDTH 16 45 | set INPUT_ARBITER_REGS_FLIP_0_OFFSET 0xC 46 | set INPUT_ARBITER_REGS_FLIP_0_DEFAULT 0x0 47 | set INPUT_ARBITER_REGS_FLIP_0_WIDTH 32 48 | set INPUT_ARBITER_REGS_DEBUG_0_OFFSET 0x10 49 | set INPUT_ARBITER_REGS_DEBUG_0_DEFAULT 0x0 50 | set INPUT_ARBITER_REGS_DEBUG_0_WIDTH 32 51 | set INPUT_ARBITER_REGS_PKTIN_0_OFFSET 0x14 52 | set INPUT_ARBITER_REGS_PKTIN_0_DEFAULT 0x0 53 | set INPUT_ARBITER_REGS_PKTIN_0_WIDTH 32 54 | set INPUT_ARBITER_REGS_PKTOUT_0_OFFSET 0x18 55 | set INPUT_ARBITER_REGS_PKTOUT_0_DEFAULT 0x0 56 | set INPUT_ARBITER_REGS_PKTOUT_0_WIDTH 32 57 | -------------------------------------------------------------------------------- /hw/lib/std/input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // 6 | // File: 7 | // input_arbiter_regs_defines.txt 8 | // 9 | // Description: 10 | // This file is automatically generated with header defines for the software 11 | // 12 | // This software was developed by 13 | // Stanford University and the University of Cambridge Computer Laboratory 14 | // under National Science Foundation under Grant No. CNS-0855268, 15 | // the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | // by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | // as part of the DARPA MRC research programme. 18 | // 19 | // @NETFPGA_LICENSE_HEADER_START@ 20 | // 21 | // Licensed under the Apache License, Version 2.0 (the "License"); 22 | // you may not use this file except in compliance with the License. 23 | // You may obtain a copy of the License at 24 | // 25 | // http://www.apache.org/licenses/LICENSE-2.0 26 | // 27 | // Unless required by applicable law or agreed to in writing, software 28 | // distributed under the License is distributed on an "AS IS" BASIS, 29 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | // See the License for the specific language governing permissions and 31 | // limitations under the License. 32 | // 33 | // @NETFPGA_LICENSE_HEADER_END@ 34 | // 35 | 36 | #define NFPLUS INPUT_ARBITER ID OFFSET 0x0 37 | #define NFPLUS INPUT_ARBITER ID DEFAULT 0x0000DA01 38 | #define NFPLUS INPUT_ARBITER ID WIDTH 32 39 | #define NFPLUS INPUT_ARBITER VERSION OFFSET 0x4 40 | #define NFPLUS INPUT_ARBITER VERSION DEFAULT 0x1 41 | #define NFPLUS INPUT_ARBITER VERSION WIDTH 32 42 | #define NFPLUS INPUT_ARBITER RESET OFFSET 0x8 43 | #define NFPLUS INPUT_ARBITER RESET DEFAULT 0x0 44 | #define NFPLUS INPUT_ARBITER RESET WIDTH 16 45 | #define NFPLUS INPUT_ARBITER FLIP OFFSET 0xC 46 | #define NFPLUS INPUT_ARBITER FLIP DEFAULT 0x0 47 | #define NFPLUS INPUT_ARBITER FLIP WIDTH 32 48 | #define NFPLUS INPUT_ARBITER DEBUG OFFSET 0x10 49 | #define NFPLUS INPUT_ARBITER DEBUG DEFAULT 0x0 50 | #define NFPLUS INPUT_ARBITER DEBUG WIDTH 32 51 | #define NFPLUS INPUT_ARBITER PKTIN OFFSET 0x14 52 | #define NFPLUS INPUT_ARBITER PKTIN DEFAULT 0x0 53 | #define NFPLUS INPUT_ARBITER PKTIN WIDTH 32 54 | #define NFPLUS INPUT_ARBITER PKTOUT OFFSET 0x18 55 | #define NFPLUS INPUT_ARBITER PKTOUT DEFAULT 0x0 56 | #define NFPLUS INPUT_ARBITER PKTOUT WIDTH 32 57 | -------------------------------------------------------------------------------- /hw/lib/std/input_arbiter_v1_0_0/data/module_generation_Input_arbiter.xlsm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/lib/std/input_arbiter_v1_0_0/data/module_generation_Input_arbiter.xlsm -------------------------------------------------------------------------------- /hw/lib/std/input_arbiter_v1_0_0/hdl/input_arbiter_cpu_regs_defines.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // 6 | // File: 7 | // input_arbiter_cpu_regs_defines.v 8 | // 9 | // Module: 10 | // input_arbiter_cpu_regs_defines 11 | // 12 | // Description: 13 | // This file is automatically generated with the registers defintions towards the CPU/Software 14 | // 15 | // This software was developed by 16 | // Stanford University and the University of Cambridge Computer Laboratory 17 | // under National Science Foundation under Grant No. CNS-0855268, 18 | // the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 19 | // by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 20 | // as part of the DARPA MRC research programme. 21 | // 22 | // @NETFPGA_LICENSE_HEADER_START@ 23 | // 24 | // Licensed under the Apache License, Version 2.0 (the "License"); 25 | // you may not use this file except in compliance with the License. 26 | // You may obtain a copy of the License at 27 | // 28 | // http://www.apache.org/licenses/LICENSE-2.0 29 | // 30 | // Unless required by applicable law or agreed to in writing, software 31 | // distributed under the License is distributed on an "AS IS" BASIS, 32 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 33 | // See the License for the specific language governing permissions and 34 | // limitations under the License. 35 | // 36 | // @NETFPGA_LICENSE_HEADER_END@ 37 | // 38 | 39 | `define REG_ID_BITS 31:0 40 | `define REG_ID_WIDTH 32 41 | `define REG_ID_DEFAULT 32'h0000DA01 42 | `define REG_ID_ADDR 32'h0 43 | 44 | `define REG_VERSION_BITS 31:0 45 | `define REG_VERSION_WIDTH 32 46 | `define REG_VERSION_DEFAULT 32'h1 47 | `define REG_VERSION_ADDR 32'h4 48 | 49 | `define REG_RESET_BITS 15:0 50 | `define REG_RESET_WIDTH 16 51 | `define REG_RESET_DEFAULT 16'h0 52 | `define REG_RESET_ADDR 32'h8 53 | 54 | `define REG_FLIP_BITS 31:0 55 | `define REG_FLIP_WIDTH 32 56 | `define REG_FLIP_DEFAULT 32'h0 57 | `define REG_FLIP_ADDR 32'hC 58 | 59 | `define REG_DEBUG_BITS 31:0 60 | `define REG_DEBUG_WIDTH 32 61 | `define REG_DEBUG_DEFAULT 32'h0 62 | `define REG_DEBUG_ADDR 32'h10 63 | 64 | `define REG_PKTIN_BITS 31:0 65 | `define REG_PKTIN_WIDTH 32 66 | `define REG_PKTIN_DEFAULT 32'h0 67 | `define REG_PKTIN_ADDR 32'h14 68 | 69 | `define REG_PKTOUT_BITS 31:0 70 | `define REG_PKTOUT_WIDTH 32 71 | `define REG_PKTOUT_DEFAULT 32'h0 72 | `define REG_PKTOUT_ADDR 32'h18 73 | -------------------------------------------------------------------------------- /hw/lib/std/nf_axis_converter_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | all: clean 29 | vivado -mode batch -source nf_axis_converter.tcl 30 | 31 | clean: 32 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 33 | -------------------------------------------------------------------------------- /hw/lib/std/nf_mac_attachment_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2021 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC EARL Project EP/P025374/1 alongside support 7 | # from Xilinx Inc. 8 | # 9 | # @NETFPGA_LICENSE_HEADER_START@ 10 | # 11 | # Licensed under the Apache License, Version 2.0 (the "License"); 12 | # you may not use this file except in compliance with the License. 13 | # You may obtain a copy of the License at 14 | # 15 | # http://www.apache.org/licenses/LICENSE-2.0 16 | # 17 | # Unless required by applicable law or agreed to in writing, software 18 | # distributed under the License is distributed on an "AS IS" BASIS, 19 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | # See the License for the specific language governing permissions and 21 | # limitations under the License. 22 | # 23 | # @NETFPGA_LICENSE_HEADER_END@ 24 | # 25 | 26 | all: clean 27 | vivado -mode batch -source nf_mac_attachment_tcl.tcl 28 | 29 | clean: 30 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 31 | -------------------------------------------------------------------------------- /hw/lib/std/nf_mac_attachment_v1_0_0/hdl/data_synch.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // This software was developed by 6 | // Stanford University and the University of Cambridge Computer Laboratory 7 | // under National Science Foundation under Grant No. CNS-0855268, 8 | // the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | // by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | // as part of the DARPA MRC research programme. 11 | // 12 | // @NETFPGA_LICENSE_HEADER_START@ 13 | // 14 | // Licensed under the Apache License, Version 2.0 (the "License"); 15 | // you may not use this file except in compliance with the License. 16 | // You may obtain a copy of the License at 17 | // 18 | // http://www.apache.org/licenses/LICENSE-2.0 19 | // 20 | // Unless required by applicable law or agreed to in writing, software 21 | // distributed under the License is distributed on an "AS IS" BASIS, 22 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | // See the License for the specific language governing permissions and 24 | // limitations under the License. 25 | // 26 | // @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | `timescale 1ps / 1ps 29 | 30 | (* dont_touch = "yes" *) 31 | module data_sync_block #( 32 | parameter C_NUM_SYNC_REGS = 5 33 | ) 34 | ( 35 | input wire clk, 36 | input wire data_in, 37 | output wire data_out 38 | ); 39 | 40 | (* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{1'b1}}; 41 | 42 | //---------------------------------------------------------------------------- 43 | // Synchronizer 44 | //---------------------------------------------------------------------------- 45 | always @(posedge clk) begin 46 | sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in}; 47 | end 48 | 49 | assign data_out = sync1_r[C_NUM_SYNC_REGS-1]; 50 | endmodule 51 | -------------------------------------------------------------------------------- /hw/lib/std/nic_output_port_lookup_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | all: clean 29 | vivado -mode batch -source nic_output_port_lookup.tcl 30 | 31 | clean: 32 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip hdl/axi_lite_ipif/ 33 | -------------------------------------------------------------------------------- /hw/lib/std/nic_output_port_lookup_v1_0_0/data/module_generation_nic_opl.xlsm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/lib/std/nic_output_port_lookup_v1_0_0/data/module_generation_nic_opl.xlsm -------------------------------------------------------------------------------- /hw/lib/std/nic_output_port_lookup_v1_0_0/data/output_port_lookup_regs_defines.h: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // 6 | // File: 7 | // output_port_lookup_regs_defines.h 8 | // 9 | // Description: 10 | // This file is automatically generated with header defines for the software 11 | // 12 | // This software was developed by 13 | // Stanford University and the University of Cambridge Computer Laboratory 14 | // under National Science Foundation under Grant No. CNS-0855268, 15 | // the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | // by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | // as part of the DARPA MRC research programme. 18 | // 19 | // @NETFPGA_LICENSE_HEADER_START@ 20 | // 21 | // Licensed under the Apache License, Version 2.0 (the "License"); 22 | // you may not use this file except in compliance with the License. 23 | // You may obtain a copy of the License at 24 | // 25 | // http://www.apache.org/licenses/LICENSE-2.0 26 | // 27 | // Unless required by applicable law or agreed to in writing, software 28 | // distributed under the License is distributed on an "AS IS" BASIS, 29 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | // See the License for the specific language governing permissions and 31 | // limitations under the License. 32 | // 33 | // @NETFPGA_LICENSE_HEADER_END@ 34 | // 35 | 36 | ##########This text should be copied to the head file ############# 37 | #Registers offset definitions 38 | 39 | #define NFPLUS_OUTPUT_PORT_LOOKUP_ID_0_OFFSET 0x0 40 | #define NFPLUS_OUTPUT_PORT_LOOKUP_ID_0_DEFAULT 0x0000DA02 41 | #define NFPLUS_OUTPUT_PORT_LOOKUP_ID_0_WIDTH 32 42 | #define NFPLUS_OUTPUT_PORT_LOOKUP_VERSION_0_OFFSET 0x4 43 | #define NFPLUS_OUTPUT_PORT_LOOKUP_VERSION_0_DEFAULT 0x1 44 | #define NFPLUS_OUTPUT_PORT_LOOKUP_VERSION_0_WIDTH 32 45 | #define NFPLUS_OUTPUT_PORT_LOOKUP_RESET_0_OFFSET 0x8 46 | #define NFPLUS_OUTPUT_PORT_LOOKUP_RESET_0_DEFAULT 0x0 47 | #define NFPLUS_OUTPUT_PORT_LOOKUP_RESET_0_WIDTH 16 48 | #define NFPLUS_OUTPUT_PORT_LOOKUP_FLIP_0_OFFSET 0xC 49 | #define NFPLUS_OUTPUT_PORT_LOOKUP_FLIP_0_DEFAULT 0x0 50 | #define NFPLUS_OUTPUT_PORT_LOOKUP_FLIP_0_WIDTH 32 51 | #define NFPLUS_OUTPUT_PORT_LOOKUP_DEBUG_0_OFFSET 0x10 52 | #define NFPLUS_OUTPUT_PORT_LOOKUP_DEBUG_0_DEFAULT 0x0 53 | #define NFPLUS_OUTPUT_PORT_LOOKUP_DEBUG_0_WIDTH 32 54 | #define NFPLUS_OUTPUT_PORT_LOOKUP_PKTIN_0_OFFSET 0x14 55 | #define NFPLUS_OUTPUT_PORT_LOOKUP_PKTIN_0_DEFAULT 0x0 56 | #define NFPLUS_OUTPUT_PORT_LOOKUP_PKTIN_0_WIDTH 32 57 | #define NFPLUS_OUTPUT_PORT_LOOKUP_PKTOUT_0_OFFSET 0x18 58 | #define NFPLUS_OUTPUT_PORT_LOOKUP_PKTOUT_0_DEFAULT 0x0 59 | #define NFPLUS_OUTPUT_PORT_LOOKUP_PKTOUT_0_WIDTH 32 60 | -------------------------------------------------------------------------------- /hw/lib/std/nic_output_port_lookup_v1_0_0/data/output_port_lookup_regs_defines.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # 6 | # File: 7 | # output_port_lookup_regs_defines.tcl 8 | # 9 | # Description: 10 | # This file is automatically generated with tcl defines for the software 11 | # 12 | # This software was developed by 13 | # Stanford University and the University of Cambridge Computer Laboratory 14 | # under National Science Foundation under Grant No. CNS-0855268, 15 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | # as part of the DARPA MRC research programme. 18 | # 19 | # @NETFPGA_LICENSE_HEADER_START@ 20 | # 21 | # Licensed under the Apache License, Version 2.0 (the "License"); 22 | # you may not use this file except in compliance with the License. 23 | # You may obtain a copy of the License at 24 | # 25 | # http://www.apache.org/licenses/LICENSE-2.0 26 | # 27 | # Unless required by applicable law or agreed to in writing, software 28 | # distributed under the License is distributed on an "AS IS" BASIS, 29 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | # See the License for the specific language governing permissions and 31 | # limitations under the License. 32 | # 33 | # @NETFPGA_LICENSE_HEADER_END@ 34 | # 35 | 36 | set OUTPUT_PORT_LOOKUP_REGS_ID_0_OFFSET 0x0 37 | set OUTPUT_PORT_LOOKUP_REGS_ID_0_DEFAULT 0x0000DA02 38 | set OUTPUT_PORT_LOOKUP_REGS_ID_0_WIDTH 32 39 | set OUTPUT_PORT_LOOKUP_REGS_VERSION_0_OFFSET 0x4 40 | set OUTPUT_PORT_LOOKUP_REGS_VERSION_0_DEFAULT 0x1 41 | set OUTPUT_PORT_LOOKUP_REGS_VERSION_0_WIDTH 32 42 | set OUTPUT_PORT_LOOKUP_REGS_RESET_0_OFFSET 0x8 43 | set OUTPUT_PORT_LOOKUP_REGS_RESET_0_DEFAULT 0x0 44 | set OUTPUT_PORT_LOOKUP_REGS_RESET_0_WIDTH 16 45 | set OUTPUT_PORT_LOOKUP_REGS_FLIP_0_OFFSET 0xC 46 | set OUTPUT_PORT_LOOKUP_REGS_FLIP_0_DEFAULT 0x0 47 | set OUTPUT_PORT_LOOKUP_REGS_FLIP_0_WIDTH 32 48 | set OUTPUT_PORT_LOOKUP_REGS_DEBUG_0_OFFSET 0x10 49 | set OUTPUT_PORT_LOOKUP_REGS_DEBUG_0_DEFAULT 0x0 50 | set OUTPUT_PORT_LOOKUP_REGS_DEBUG_0_WIDTH 32 51 | set OUTPUT_PORT_LOOKUP_REGS_PKTIN_0_OFFSET 0x14 52 | set OUTPUT_PORT_LOOKUP_REGS_PKTIN_0_DEFAULT 0x0 53 | set OUTPUT_PORT_LOOKUP_REGS_PKTIN_0_WIDTH 32 54 | set OUTPUT_PORT_LOOKUP_REGS_PKTOUT_0_OFFSET 0x18 55 | set OUTPUT_PORT_LOOKUP_REGS_PKTOUT_0_DEFAULT 0x0 56 | set OUTPUT_PORT_LOOKUP_REGS_PKTOUT_0_WIDTH 32 57 | -------------------------------------------------------------------------------- /hw/lib/std/nic_output_port_lookup_v1_0_0/data/output_port_lookup_regs_defines.txt: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // 6 | // File: 7 | // output_port_lookup_regs_defines.txt 8 | // 9 | // Description: 10 | // This file is automatically generated with header defines for the software 11 | // 12 | // This software was developed by 13 | // Stanford University and the University of Cambridge Computer Laboratory 14 | // under National Science Foundation under Grant No. CNS-0855268, 15 | // the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | // by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | // as part of the DARPA MRC research programme. 18 | // 19 | // @NETFPGA_LICENSE_HEADER_START@ 20 | // 21 | // Licensed under the Apache License, Version 2.0 (the "License"); 22 | // you may not use this file except in compliance with the License. 23 | // You may obtain a copy of the License at 24 | // 25 | // http://www.apache.org/licenses/LICENSE-2.0 26 | // 27 | // Unless required by applicable law or agreed to in writing, software 28 | // distributed under the License is distributed on an "AS IS" BASIS, 29 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | // See the License for the specific language governing permissions and 31 | // limitations under the License. 32 | // 33 | // @NETFPGA_LICENSE_HEADER_END@ 34 | // 35 | 36 | #define NFPLUS OUTPUT_PORT_LOOKUP ID OFFSET 0x0 37 | #define NFPLUS OUTPUT_PORT_LOOKUP ID DEFAULT 0x0000DA02 38 | #define NFPLUS OUTPUT_PORT_LOOKUP ID WIDTH 32 39 | #define NFPLUS OUTPUT_PORT_LOOKUP VERSION OFFSET 0x4 40 | #define NFPLUS OUTPUT_PORT_LOOKUP VERSION DEFAULT 0x1 41 | #define NFPLUS OUTPUT_PORT_LOOKUP VERSION WIDTH 32 42 | #define NFPLUS OUTPUT_PORT_LOOKUP RESET OFFSET 0x8 43 | #define NFPLUS OUTPUT_PORT_LOOKUP RESET DEFAULT 0x0 44 | #define NFPLUS OUTPUT_PORT_LOOKUP RESET WIDTH 16 45 | #define NFPLUS OUTPUT_PORT_LOOKUP FLIP OFFSET 0xC 46 | #define NFPLUS OUTPUT_PORT_LOOKUP FLIP DEFAULT 0x0 47 | #define NFPLUS OUTPUT_PORT_LOOKUP FLIP WIDTH 32 48 | #define NFPLUS OUTPUT_PORT_LOOKUP DEBUG OFFSET 0x10 49 | #define NFPLUS OUTPUT_PORT_LOOKUP DEBUG DEFAULT 0x0 50 | #define NFPLUS OUTPUT_PORT_LOOKUP DEBUG WIDTH 32 51 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTIN OFFSET 0x14 52 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTIN DEFAULT 0x0 53 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTIN WIDTH 32 54 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTOUT OFFSET 0x18 55 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTOUT DEFAULT 0x0 56 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTOUT WIDTH 32 57 | -------------------------------------------------------------------------------- /hw/lib/std/nic_output_port_lookup_v1_0_0/hdl/output_port_lookup_cpu_regs_defines.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // 6 | // File: 7 | // output_port_lookup_cpu_regs_defines.v 8 | // 9 | // Module: 10 | // output_port_lookup_cpu_regs_defines 11 | // 12 | // Description: 13 | // This file is automatically generated with the registers defintions towards the CPU/Software 14 | // 15 | // This software was developed by 16 | // Stanford University and the University of Cambridge Computer Laboratory 17 | // under National Science Foundation under Grant No. CNS-0855268, 18 | // the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 19 | // by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 20 | // as part of the DARPA MRC research programme. 21 | // 22 | // @NETFPGA_LICENSE_HEADER_START@ 23 | // 24 | // Licensed under the Apache License, Version 2.0 (the "License"); 25 | // you may not use this file except in compliance with the License. 26 | // You may obtain a copy of the License at 27 | // 28 | // http://www.apache.org/licenses/LICENSE-2.0 29 | // 30 | // Unless required by applicable law or agreed to in writing, software 31 | // distributed under the License is distributed on an "AS IS" BASIS, 32 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 33 | // See the License for the specific language governing permissions and 34 | // limitations under the License. 35 | // 36 | // @NETFPGA_LICENSE_HEADER_END@ 37 | // 38 | 39 | 40 | `define REG_ID_BITS 31:0 41 | `define REG_ID_WIDTH 32 42 | `define REG_ID_DEFAULT 32'h0000DA02 43 | `define REG_ID_ADDR 32'h0 44 | 45 | `define REG_VERSION_BITS 31:0 46 | `define REG_VERSION_WIDTH 32 47 | `define REG_VERSION_DEFAULT 32'h1 48 | `define REG_VERSION_ADDR 32'h4 49 | 50 | `define REG_RESET_BITS 15:0 51 | `define REG_RESET_WIDTH 16 52 | `define REG_RESET_DEFAULT 16'h0 53 | `define REG_RESET_ADDR 32'h8 54 | 55 | `define REG_FLIP_BITS 31:0 56 | `define REG_FLIP_WIDTH 32 57 | `define REG_FLIP_DEFAULT 32'h0 58 | `define REG_FLIP_ADDR 32'hC 59 | 60 | `define REG_DEBUG_BITS 31:0 61 | `define REG_DEBUG_WIDTH 32 62 | `define REG_DEBUG_DEFAULT 32'h0 63 | `define REG_DEBUG_ADDR 32'h10 64 | 65 | `define REG_PKTIN_BITS 31:0 66 | `define REG_PKTIN_WIDTH 32 67 | `define REG_PKTIN_DEFAULT 32'h0 68 | `define REG_PKTIN_ADDR 32'h14 69 | 70 | `define REG_PKTOUT_BITS 31:0 71 | `define REG_PKTOUT_WIDTH 32 72 | `define REG_PKTOUT_DEFAULT 32'h0 73 | `define REG_PKTOUT_ADDR 32'h18 74 | -------------------------------------------------------------------------------- /hw/lib/std/output_queues_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # Modified by Salvator Galea 4 | # All rights reserved. 5 | # 6 | # This software was developed by 7 | # Stanford University and the University of Cambridge Computer Laboratory 8 | # under National Science Foundation under Grant No. CNS-0855268, 9 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 10 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 11 | # as part of the DARPA MRC research programme. 12 | # 13 | # @NETFPGA_LICENSE_HEADER_START@ 14 | # 15 | # Licensed under the Apache License, Version 2.0 (the "License"); 16 | # you may not use this file except in compliance with the License. 17 | # You may obtain a copy of the License at 18 | # 19 | # http://www.apache.org/licenses/LICENSE-2.0 20 | # 21 | # Unless required by applicable law or agreed to in writing, software 22 | # distributed under the License is distributed on an "AS IS" BASIS, 23 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | # See the License for the specific language governing permissions and 25 | # limitations under the License. 26 | # 27 | # @NETFPGA_LICENSE_HEADER_END@ 28 | 29 | all: clean 30 | vivado -mode batch -source output_queues.tcl 31 | 32 | clean: 33 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 34 | -------------------------------------------------------------------------------- /hw/lib/std/output_queues_v1_0_0/data/module_generation_output_queues.xlsm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/lib/std/output_queues_v1_0_0/data/module_generation_output_queues.xlsm -------------------------------------------------------------------------------- /hw/lib/std/router_output_port_lookup_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | all: clean 29 | vivado -mode batch -source router_output_port_lookup.tcl 30 | 31 | clean: 32 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip hdl/axi_lite_ipif/ 33 | -------------------------------------------------------------------------------- /hw/lib/std/switch_lite_output_port_lookup_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # Modified by Salvator Galea 4 | # All rights reserved. 5 | # 6 | # This software was developed by 7 | # Stanford University and the University of Cambridge Computer Laboratory 8 | # under National Science Foundation under Grant No. CNS-0855268, 9 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 10 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 11 | # as part of the DARPA MRC research programme. 12 | # 13 | # @NETFPGA_LICENSE_HEADER_START@ 14 | # 15 | # Licensed under the Apache License, Version 2.0 (the "License"); 16 | # you may not use this file except in compliance with the License. 17 | # You may obtain a copy of the License at 18 | # 19 | # http://www.apache.org/licenses/LICENSE-2.0 20 | # 21 | # Unless required by applicable law or agreed to in writing, software 22 | # distributed under the License is distributed on an "AS IS" BASIS, 23 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | # See the License for the specific language governing permissions and 25 | # limitations under the License. 26 | # 27 | # @NETFPGA_LICENSE_HEADER_END@ 28 | 29 | all: clean 30 | vivado -mode batch -source switch_lite_output_port_lookup.tcl 31 | 32 | clean: 33 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 34 | -------------------------------------------------------------------------------- /hw/lib/std/switch_lite_output_port_lookup_v1_0_0/data/module_generation_switch_opl.xlsm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/lib/std/switch_lite_output_port_lookup_v1_0_0/data/module_generation_switch_opl.xlsm -------------------------------------------------------------------------------- /hw/lib/std/switch_lite_output_port_lookup_v1_0_0/data/output_port_lookup_regs_defines.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # 6 | # File: 7 | # output_port_lookup_regs_defines.tcl 8 | # 9 | # Description: 10 | # This file is automatically generated with tcl defines for the software 11 | # 12 | # This software was developed by 13 | # Stanford University and the University of Cambridge Computer Laboratory 14 | # under National Science Foundation under Grant No. CNS-0855268, 15 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | # as part of the DARPA MRC research programme. 18 | # 19 | # @NETFPGA_LICENSE_HEADER_START@ 20 | # 21 | # Licensed under the Apache License, Version 2.0 (the "License"); 22 | # you may not use this file except in compliance with the License. 23 | # You may obtain a copy of the License at 24 | # 25 | # http://www.apache.org/licenses/LICENSE-2.0 26 | # 27 | # Unless required by applicable law or agreed to in writing, software 28 | # distributed under the License is distributed on an "AS IS" BASIS, 29 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | # See the License for the specific language governing permissions and 31 | # limitations under the License. 32 | # 33 | # @NETFPGA_LICENSE_HEADER_END@ 34 | # 35 | 36 | set OUTPUT_PORT_LOOKUP_REGS_ID_0_OFFSET 0x0 37 | set OUTPUT_PORT_LOOKUP_REGS_ID_0_DEFAULT 0x0001DA02 38 | set OUTPUT_PORT_LOOKUP_REGS_ID_0_WIDTH 32 39 | set OUTPUT_PORT_LOOKUP_REGS_VERSION_0_OFFSET 0x4 40 | set OUTPUT_PORT_LOOKUP_REGS_VERSION_0_DEFAULT 0x1 41 | set OUTPUT_PORT_LOOKUP_REGS_VERSION_0_WIDTH 32 42 | set OUTPUT_PORT_LOOKUP_REGS_RESET_0_OFFSET 0x8 43 | set OUTPUT_PORT_LOOKUP_REGS_RESET_0_DEFAULT 0x0 44 | set OUTPUT_PORT_LOOKUP_REGS_RESET_0_WIDTH 16 45 | set OUTPUT_PORT_LOOKUP_REGS_FLIP_0_OFFSET 0xC 46 | set OUTPUT_PORT_LOOKUP_REGS_FLIP_0_DEFAULT 0x0 47 | set OUTPUT_PORT_LOOKUP_REGS_FLIP_0_WIDTH 32 48 | set OUTPUT_PORT_LOOKUP_REGS_DEBUG_0_OFFSET 0x10 49 | set OUTPUT_PORT_LOOKUP_REGS_DEBUG_0_DEFAULT 0x0 50 | set OUTPUT_PORT_LOOKUP_REGS_DEBUG_0_WIDTH 32 51 | set OUTPUT_PORT_LOOKUP_REGS_PKTIN_0_OFFSET 0x14 52 | set OUTPUT_PORT_LOOKUP_REGS_PKTIN_0_DEFAULT 0x0 53 | set OUTPUT_PORT_LOOKUP_REGS_PKTIN_0_WIDTH 32 54 | set OUTPUT_PORT_LOOKUP_REGS_PKTOUT_0_OFFSET 0x18 55 | set OUTPUT_PORT_LOOKUP_REGS_PKTOUT_0_DEFAULT 0x0 56 | set OUTPUT_PORT_LOOKUP_REGS_PKTOUT_0_WIDTH 32 57 | set OUTPUT_PORT_LOOKUP_REGS_LUTHIT_0_OFFSET 0x1C 58 | set OUTPUT_PORT_LOOKUP_REGS_LUTHIT_0_DEFAULT 0x0 59 | set OUTPUT_PORT_LOOKUP_REGS_LUTHIT_0_WIDTH 32 60 | set OUTPUT_PORT_LOOKUP_REGS_LUTMISS_0_OFFSET 0x20 61 | set OUTPUT_PORT_LOOKUP_REGS_LUTMISS_0_DEFAULT 0x0 62 | set OUTPUT_PORT_LOOKUP_REGS_LUTMISS_0_WIDTH 32 63 | -------------------------------------------------------------------------------- /hw/lib/std/switch_lite_output_port_lookup_v1_0_0/data/output_port_lookup_regs_defines.txt: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // 6 | // File: 7 | // output_port_lookup_regs_defines.txt 8 | // 9 | // Description: 10 | // This file is automatically generated with header defines for the software 11 | // 12 | // This software was developed by 13 | // Stanford University and the University of Cambridge Computer Laboratory 14 | // under National Science Foundation under Grant No. CNS-0855268, 15 | // the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | // by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | // as part of the DARPA MRC research programme. 18 | // 19 | // @NETFPGA_LICENSE_HEADER_START@ 20 | // 21 | // Licensed under the Apache License, Version 2.0 (the "License"); 22 | // you may not use this file except in compliance with the License. 23 | // You may obtain a copy of the License at 24 | // 25 | // http://www.apache.org/licenses/LICENSE-2.0 26 | // 27 | // Unless required by applicable law or agreed to in writing, software 28 | // distributed under the License is distributed on an "AS IS" BASIS, 29 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | // See the License for the specific language governing permissions and 31 | // limitations under the License. 32 | // 33 | // @NETFPGA_LICENSE_HEADER_END@ 34 | // 35 | 36 | #define NFPLUS OUTPUT_PORT_LOOKUP ID OFFSET 0x0 37 | #define NFPLUS OUTPUT_PORT_LOOKUP ID DEFAULT 0x0001DA02 38 | #define NFPLUS OUTPUT_PORT_LOOKUP ID WIDTH 32 39 | #define NFPLUS OUTPUT_PORT_LOOKUP VERSION OFFSET 0x4 40 | #define NFPLUS OUTPUT_PORT_LOOKUP VERSION DEFAULT 0x1 41 | #define NFPLUS OUTPUT_PORT_LOOKUP VERSION WIDTH 32 42 | #define NFPLUS OUTPUT_PORT_LOOKUP RESET OFFSET 0x8 43 | #define NFPLUS OUTPUT_PORT_LOOKUP RESET DEFAULT 0x0 44 | #define NFPLUS OUTPUT_PORT_LOOKUP RESET WIDTH 16 45 | #define NFPLUS OUTPUT_PORT_LOOKUP FLIP OFFSET 0xC 46 | #define NFPLUS OUTPUT_PORT_LOOKUP FLIP DEFAULT 0x0 47 | #define NFPLUS OUTPUT_PORT_LOOKUP FLIP WIDTH 32 48 | #define NFPLUS OUTPUT_PORT_LOOKUP DEBUG OFFSET 0x10 49 | #define NFPLUS OUTPUT_PORT_LOOKUP DEBUG DEFAULT 0x0 50 | #define NFPLUS OUTPUT_PORT_LOOKUP DEBUG WIDTH 32 51 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTIN OFFSET 0x14 52 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTIN DEFAULT 0x0 53 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTIN WIDTH 32 54 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTOUT OFFSET 0x18 55 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTOUT DEFAULT 0x0 56 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTOUT WIDTH 32 57 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTHIT OFFSET 0x1C 58 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTHIT DEFAULT 0x0 59 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTHIT WIDTH 32 60 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTMISS OFFSET 0x20 61 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTMISS DEFAULT 0x0 62 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTMISS WIDTH 32 63 | -------------------------------------------------------------------------------- /hw/lib/std/switch_output_port_lookup_v1_0_1/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by 6 | # Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | all: clean 29 | vivado -mode batch -source switch_output_port_lookup.tcl 30 | 31 | clean: 32 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip 33 | -------------------------------------------------------------------------------- /hw/lib/std/switch_output_port_lookup_v1_0_1/data/module_generation_switch_opl.xlsm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/lib/std/switch_output_port_lookup_v1_0_1/data/module_generation_switch_opl.xlsm -------------------------------------------------------------------------------- /hw/lib/std/switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # 6 | # File: 7 | # output_port_lookup_regs_defines.tcl 8 | # 9 | # Description: 10 | # This file is automatically generated with tcl defines for the software 11 | # 12 | # This software was developed by 13 | # Stanford University and the University of Cambridge Computer Laboratory 14 | # under National Science Foundation under Grant No. CNS-0855268, 15 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | # as part of the DARPA MRC research programme. 18 | # 19 | # @NETFPGA_LICENSE_HEADER_START@ 20 | # 21 | # Licensed under the Apache License, Version 2.0 (the "License"); 22 | # you may not use this file except in compliance with the License. 23 | # You may obtain a copy of the License at 24 | # 25 | # http://www.apache.org/licenses/LICENSE-2.0 26 | # 27 | # Unless required by applicable law or agreed to in writing, software 28 | # distributed under the License is distributed on an "AS IS" BASIS, 29 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | # See the License for the specific language governing permissions and 31 | # limitations under the License. 32 | # 33 | # @NETFPGA_LICENSE_HEADER_END@ 34 | # 35 | 36 | set OUTPUT_PORT_LOOKUP_REGS_ID_0_OFFSET 0x0 37 | set OUTPUT_PORT_LOOKUP_REGS_ID_0_DEFAULT 0x0001DA02 38 | set OUTPUT_PORT_LOOKUP_REGS_ID_0_WIDTH 32 39 | set OUTPUT_PORT_LOOKUP_REGS_VERSION_0_OFFSET 0x4 40 | set OUTPUT_PORT_LOOKUP_REGS_VERSION_0_DEFAULT 0x1 41 | set OUTPUT_PORT_LOOKUP_REGS_VERSION_0_WIDTH 32 42 | set OUTPUT_PORT_LOOKUP_REGS_RESET_0_OFFSET 0x8 43 | set OUTPUT_PORT_LOOKUP_REGS_RESET_0_DEFAULT 0x0 44 | set OUTPUT_PORT_LOOKUP_REGS_RESET_0_WIDTH 16 45 | set OUTPUT_PORT_LOOKUP_REGS_FLIP_0_OFFSET 0xC 46 | set OUTPUT_PORT_LOOKUP_REGS_FLIP_0_DEFAULT 0x0 47 | set OUTPUT_PORT_LOOKUP_REGS_FLIP_0_WIDTH 32 48 | set OUTPUT_PORT_LOOKUP_REGS_DEBUG_0_OFFSET 0x10 49 | set OUTPUT_PORT_LOOKUP_REGS_DEBUG_0_DEFAULT 0x0 50 | set OUTPUT_PORT_LOOKUP_REGS_DEBUG_0_WIDTH 32 51 | set OUTPUT_PORT_LOOKUP_REGS_PKTIN_0_OFFSET 0x14 52 | set OUTPUT_PORT_LOOKUP_REGS_PKTIN_0_DEFAULT 0x0 53 | set OUTPUT_PORT_LOOKUP_REGS_PKTIN_0_WIDTH 32 54 | set OUTPUT_PORT_LOOKUP_REGS_PKTOUT_0_OFFSET 0x18 55 | set OUTPUT_PORT_LOOKUP_REGS_PKTOUT_0_DEFAULT 0x0 56 | set OUTPUT_PORT_LOOKUP_REGS_PKTOUT_0_WIDTH 32 57 | set OUTPUT_PORT_LOOKUP_REGS_LUTHIT_0_OFFSET 0x1C 58 | set OUTPUT_PORT_LOOKUP_REGS_LUTHIT_0_DEFAULT 0x0 59 | set OUTPUT_PORT_LOOKUP_REGS_LUTHIT_0_WIDTH 32 60 | set OUTPUT_PORT_LOOKUP_REGS_LUTMISS_0_OFFSET 0x20 61 | set OUTPUT_PORT_LOOKUP_REGS_LUTMISS_0_DEFAULT 0x0 62 | set OUTPUT_PORT_LOOKUP_REGS_LUTMISS_0_WIDTH 32 63 | -------------------------------------------------------------------------------- /hw/lib/std/switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // 6 | // File: 7 | // output_port_lookup_regs_defines.txt 8 | // 9 | // Description: 10 | // This file is automatically generated with header defines for the software 11 | // 12 | // This software was developed by 13 | // Stanford University and the University of Cambridge Computer Laboratory 14 | // under National Science Foundation under Grant No. CNS-0855268, 15 | // the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 16 | // by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 17 | // as part of the DARPA MRC research programme. 18 | // 19 | // @NETFPGA_LICENSE_HEADER_START@ 20 | // 21 | // Licensed under the Apache License, Version 2.0 (the "License"); 22 | // you may not use this file except in compliance with the License. 23 | // You may obtain a copy of the License at 24 | // 25 | // http://www.apache.org/licenses/LICENSE-2.0 26 | // 27 | // Unless required by applicable law or agreed to in writing, software 28 | // distributed under the License is distributed on an "AS IS" BASIS, 29 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | // See the License for the specific language governing permissions and 31 | // limitations under the License. 32 | // 33 | // @NETFPGA_LICENSE_HEADER_END@ 34 | // 35 | 36 | #define NFPLUS OUTPUT_PORT_LOOKUP ID OFFSET 0x0 37 | #define NFPLUS OUTPUT_PORT_LOOKUP ID DEFAULT 0x0001DA02 38 | #define NFPLUS OUTPUT_PORT_LOOKUP ID WIDTH 32 39 | #define NFPLUS OUTPUT_PORT_LOOKUP VERSION OFFSET 0x4 40 | #define NFPLUS OUTPUT_PORT_LOOKUP VERSION DEFAULT 0x1 41 | #define NFPLUS OUTPUT_PORT_LOOKUP VERSION WIDTH 32 42 | #define NFPLUS OUTPUT_PORT_LOOKUP RESET OFFSET 0x8 43 | #define NFPLUS OUTPUT_PORT_LOOKUP RESET DEFAULT 0x0 44 | #define NFPLUS OUTPUT_PORT_LOOKUP RESET WIDTH 16 45 | #define NFPLUS OUTPUT_PORT_LOOKUP FLIP OFFSET 0xC 46 | #define NFPLUS OUTPUT_PORT_LOOKUP FLIP DEFAULT 0x0 47 | #define NFPLUS OUTPUT_PORT_LOOKUP FLIP WIDTH 32 48 | #define NFPLUS OUTPUT_PORT_LOOKUP DEBUG OFFSET 0x10 49 | #define NFPLUS OUTPUT_PORT_LOOKUP DEBUG DEFAULT 0x0 50 | #define NFPLUS OUTPUT_PORT_LOOKUP DEBUG WIDTH 32 51 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTIN OFFSET 0x14 52 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTIN DEFAULT 0x0 53 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTIN WIDTH 32 54 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTOUT OFFSET 0x18 55 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTOUT DEFAULT 0x0 56 | #define NFPLUS OUTPUT_PORT_LOOKUP PKTOUT WIDTH 32 57 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTHIT OFFSET 0x1C 58 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTHIT DEFAULT 0x0 59 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTHIT WIDTH 32 60 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTMISS OFFSET 0x20 61 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTMISS DEFAULT 0x0 62 | #define NFPLUS OUTPUT_PORT_LOOKUP LUTMISS WIDTH 32 63 | -------------------------------------------------------------------------------- /hw/lib/xilinx/cam_v1_1_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC INTERNET Project EP/H040536/1, National Science 7 | # Foundation under Grant No. CNS-0855268, and Defense Advanced Research 8 | # Projects Agency (DARPA) and Air Force Research Laboratory (AFRL), under 9 | # contract FA8750-11-C-0249. 10 | # 11 | # @NETFPGA_LICENSE_HEADER_START@ 12 | 13 | # Licensed under the Apache License, Version 2.0 (the "License"); 14 | # you may not use this file except in compliance with the License. 15 | # You may obtain a copy of the License at 16 | # 17 | # http://www.apache.org/licenses/LICENSE-2.0 18 | # 19 | # Unless required by applicable law or agreed to in writing, software 20 | # distributed under the License is distributed on an "AS IS" BASIS, 21 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | # See the License for the specific language governing permissions and 23 | # limitations under the License. 24 | # 25 | # @NETFPGA_LICENSE_HEADER_END@ 26 | # 27 | 28 | .PHONY: all 29 | .PHONY: update 30 | .PHONY: sim 31 | 32 | all: clean 33 | vivado -mode tcl -source cam.tcl 34 | 35 | update: 36 | unzip xapp1151_Param_CAM.zip 37 | bash ./scripts/run_update_lib.sh 38 | cp -f ./xapp1151_cam_v1_1/src/vhdl/*.vhd ./hdl/vhdl/cam/ 39 | 40 | sim: 41 | bash ./sim/run_cam_sim.sh 42 | 43 | clean: 44 | rm -rf vivado*.* *.xml xgui/ .Xil* ip_pro* xv* *.wdb xsim* xe* we* 45 | -------------------------------------------------------------------------------- /hw/lib/xilinx/cam_v1_1_0/README: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by Stanford University and the University of Cambridge Computer Laboratory 6 | # under National Science Foundation under Grant No. CNS-0855268, 7 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 8 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 9 | # as part of the DARPA MRC research programme. 10 | # 11 | # @NETFPGA_LICENSE_HEADER_START@ 12 | # 13 | # Licensed under the Apache License, Version 2.0 (the "License"); 14 | # you may not use this file except in compliance with the License. 15 | # You may obtain a copy of the License at 16 | # 17 | # http://www.apache.org/licenses/LICENSE-2.0 18 | # 19 | # Unless required by applicable law or agreed to in writing, software 20 | # distributed under the License is distributed on an "AS IS" BASIS, 21 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | # See the License for the specific language governing permissions and 23 | # limitations under the License. 24 | # 25 | # @NETFPGA_LICENSE_HEADER_END@ 26 | # 27 | 28 | Follow the instruction below to create a TCAM IP for NetFPGA NFPLUS platform step by step. The TCAM IPs created by the instruction is based on SRL only to support Ternary mode. More detailed information of the TCAM can be found on xapp1151_Param_CAM.pdf in Xilinx web site. TCAM IPs on NFPLUS platform are separated into TCAM and CAM, but they are almost the same and share the same libraries. 29 | 30 | 1) At first, users need to find and download xapp1151 module on Xilinx web site. After searching 'xapp1151', xapp1151_Param_CAM.zip and related documents can be downloaded from the web site. 31 | 32 | 2) Copy xapp1151_Param_CAM.zip into the NetFPGA-NFPLUS-live/lib/hw/xilinx/cores/cam_v*_*_*/ and go to the 'cam_v*_*_*' directory. 33 | 34 | 3) Run 'make update' to decompress and update the xapp1151 libraries. 35 | 36 | 4) Run 'make sim' and find what is the simulation result. Before run 'make sim', source Vivado license to run the tool commands. 37 | 38 | 5) Run 'make' to create IP. 39 | 40 | 41 | If it is succeeded, now users can call the TCAM IP in the project for block design and ip creation. 42 | 43 | (Note: Whenever you run 'make clean' in the $NFPLUS_FOLDER, you need to run again 'make' into cam_v*_*_* folder, to create the IP.) 44 | -------------------------------------------------------------------------------- /hw/lib/xilinx/cam_v1_1_0/hdl/verilog/cam.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // This software was developed by SRI International and the University of 6 | // Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1, 7 | // National Science Foundation under Grant No. CNS-0855268, and Defense 8 | // Advanced Research Projects Agency (DARPA) and Air Force Research Laboratory 9 | // (AFRL), under contract FA8750-11-C-0249. 10 | // 11 | // @NETFPGA_LICENSE_HEADER_START@ 12 | // 13 | // Licensed under the Apache License, Version 2.0 (the "License"); 14 | // you may not use this file except in compliance with the License. 15 | // You may obtain a copy of the License at 16 | // 17 | // http://www.apache.org/licenses/LICENSE-2.0 18 | // 19 | // Unless required by applicable law or agreed to in writing, software 20 | // distributed under the License is distributed on an "AS IS" BASIS, 21 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | // See the License for the specific language governing permissions and 23 | // limitations under the License. 24 | // 25 | // @NETFPGA_LICENSE_HEADER_END@ 26 | // 27 | `timescale 1ns/1ps 28 | 29 | module cam 30 | #( 31 | parameter C_TCAM_ADDR_WIDTH = 5, 32 | parameter C_TCAM_DATA_WIDTH = 32, 33 | parameter C_TCAM_ADDR_TYPE = 0, 34 | parameter C_TCAM_MATCH_ADDR_WIDTH = 5 35 | ) 36 | ( 37 | input CLK, 38 | input WE, 39 | input [C_TCAM_ADDR_WIDTH-1:0] ADDR_WR, 40 | input [C_TCAM_DATA_WIDTH-1:0] DIN, 41 | output BUSY, 42 | 43 | input [C_TCAM_DATA_WIDTH-1:0] CMP_DIN, 44 | output MATCH, 45 | output [C_TCAM_MATCH_ADDR_WIDTH-1:0] MATCH_ADDR 46 | ); 47 | 48 | localparam C_TCAM_DATA_DEPTH = 2**C_TCAM_ADDR_WIDTH; 49 | 50 | cam_wrapper 51 | #( 52 | .C_TCAM_ADDR_WIDTH ( C_TCAM_ADDR_WIDTH ), 53 | .C_TCAM_DATA_WIDTH ( C_TCAM_DATA_WIDTH ), 54 | .C_TCAM_ADDR_TYPE ( C_TCAM_ADDR_TYPE ), 55 | .C_TCAM_MATCH_ADDR_WIDTH ( C_TCAM_MATCH_ADDR_WIDTH ) 56 | ) 57 | cam_wrapper 58 | ( 59 | .CLK ( CLK ), 60 | .WE ( WE ), 61 | .WR_ADDR ( ADDR_WR ), 62 | .DIN ( DIN ), 63 | .BUSY ( BUSY ), 64 | 65 | .MATCH ( MATCH ), 66 | .MATCH_ADDR ( MATCH_ADDR ), 67 | .CMP_DIN ( CMP_DIN ) 68 | ); 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /hw/lib/xilinx/cam_v1_1_0/hdl/vhdl/cam/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/lib/xilinx/cam_v1_1_0/hdl/vhdl/cam/.keep -------------------------------------------------------------------------------- /hw/lib/xilinx/cam_v1_1_0/scripts/run_update_lib.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | # Copyright (c) 2015 University of Cambridge 4 | # All rights reserved. 5 | # 6 | # This software was developed by the University of Cambridge Computer 7 | # Laboratory under EPSRC INTERNET Project EP/H040536/1, National Science 8 | # Foundation under Grant No. CNS-0855268, and Defense Advanced Research 9 | # Projects Agency (DARPA) and Air Force Research Laboratory (AFRL), under 10 | # contract FA8750-11-C-0249. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | cam_dir=./xapp1151_cam_v1_1/src 30 | 31 | file_list=`find $cam_dir -name *.vhd` 32 | 33 | for in_file in $file_list; do 34 | 35 | sed -i -e 's/LIBRARY cam/LIBRARY xil_defaultlib/' $in_file 36 | sed -i -e 's/ENTITY cam\./ENTITY xil_defaultlib\./' $in_file 37 | sed -i -e 's/USE cam\./USE xil_defaultlib\./' $in_file 38 | done 39 | 40 | sed -i '/virtex6l/a CONSTANT VIRTEX7 : STRING := "virtex7";' $cam_dir/vhdl/cam_pkg.vhd 41 | sed -i -e 's/spartan6)/spartan6) OR (C_FAMILY = virtex7)/' $cam_dir/vhdl/cam_rtl.vhd 42 | sed -i -e 's/or spartan6/spartan6, or virtex7/' $cam_dir/vhdl/cam_rtl.vhd 43 | -------------------------------------------------------------------------------- /hw/lib/xilinx/tcam_v1_1_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC INTERNET Project EP/H040536/1, National Science 7 | # Foundation under Grant No. CNS-0855268, and Defense Advanced Research 8 | # Projects Agency (DARPA) and Air Force Research Laboratory (AFRL), under 9 | # contract FA8750-11-C-0249. 10 | # 11 | # @NETFPGA_LICENSE_HEADER_START@ 12 | # 13 | # Licensed under the Apache License, Version 2.0 (the "License"); 14 | # you may not use this file except in compliance with the License. 15 | # You may obtain a copy of the License at 16 | # 17 | # http://www.apache.org/licenses/LICENSE-2.0 18 | # 19 | # Unless required by applicable law or agreed to in writing, software 20 | # distributed under the License is distributed on an "AS IS" BASIS, 21 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | # See the License for the specific language governing permissions and 23 | # limitations under the License. 24 | # 25 | # @NETFPGA_LICENSE_HEADER_END@ 26 | # 27 | .PHONY: all 28 | .PHONY: update 29 | .PHONY: sim 30 | 31 | all: clean 32 | vivado -mode tcl -source tcam.tcl 33 | 34 | update: 35 | unzip xapp1151_Param_CAM.zip 36 | bash ./scripts/run_update_lib.sh 37 | cp -f ./xapp1151_cam_v1_1/src/vhdl/*.vhd ./hdl/vhdl/tcam/ 38 | 39 | sim: 40 | bash ./sim/run_tcam_sim.sh 41 | 42 | clean: 43 | rm -rf vivado*.* *.xml xgui/ .Xil* ip_pro* xv* *.wdb xsim* xe* we* 44 | -------------------------------------------------------------------------------- /hw/lib/xilinx/tcam_v1_1_0/README: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by Stanford University and the University of Cambridge Computer Laboratory 6 | # under National Science Foundation under Grant No. CNS-0855268, 7 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 8 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 9 | # as part of the DARPA MRC research programme. 10 | # 11 | # @NETFPGA_LICENSE_HEADER_START@ 12 | # 13 | # Licensed under the Apache License, Version 2.0 (the "License"); 14 | # you may not use this file except in compliance with the License. 15 | # You may obtain a copy of the License at 16 | # 17 | # http://www.apache.org/licenses/LICENSE-2.0 18 | # 19 | # Unless required by applicable law or agreed to in writing, software 20 | # distributed under the License is distributed on an "AS IS" BASIS, 21 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | # See the License for the specific language governing permissions and 23 | # limitations under the License. 24 | # 25 | # @NETFPGA_LICENSE_HEADER_END@ 26 | # 27 | 28 | Follow the instruction below to create a TCAM IP for NetFPGA NFPLUS platform step by step. The TCAM IPs created by the instruction is based on SRL only to support Ternary mode. More detailed information of the TCAM can be found on xapp1151_Param_CAM.pdf in Xilinx web site. TCAM IPs on NFPLUS platform are separated into TCAM and CAM, but they are almost the same and share the same libraries. 29 | 30 | 1) At first, users need to find and download xapp1151 module on Xilinx web site. After searching 'xapp1151', xapp1151_Param_CAM.zip and related documents can be downloaded from the web site. 31 | 32 | 2) Copy xapp1151_Param_CAM.zip into the NetFPGA-NFPLUS-live/lib/hw/xilinx/cores/tcam_v*_*_*/ and go to the 'tcam_v*_*_*' directory. 33 | 34 | 3) Run 'make update' to decompress and update the xapp1151 libraries. 35 | 36 | 4) Run 'make sim' and find what is the simulation result. Before run 'make sim', source Vivado license to run the tool commands. 37 | 38 | 5) Run 'make' to create IP. 39 | 40 | 41 | If it is succeeded, now users can call the TCAM IP in the project for block design and ip creation. 42 | 43 | (Note: Whenever you run 'make clean' in the $NFPLUS_FOLDER, you need to run again 'make' into tcam_v*_*_* folder, to create the IP.) 44 | -------------------------------------------------------------------------------- /hw/lib/xilinx/tcam_v1_1_0/hdl/verilog/tcam.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2015 University of Cambridge 3 | // All rights reserved. 4 | // 5 | // This software was developed by SRI International and the University of 6 | // Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1, 7 | // National Science Foundation under Grant No. CNS-0855268, and Defense 8 | // Advanced Research Projects Agency (DARPA) and Air Force Research Laboratory 9 | // (AFRL), under contract FA8750-11-C-0249. 10 | // 11 | // @NETFPGA_LICENSE_HEADER_START@ 12 | // 13 | // Licensed under the Apache License, Version 2.0 (the "License"); 14 | // you may not use this file except in compliance with the License. 15 | // You may obtain a copy of the License at 16 | // 17 | // http://www.apache.org/licenses/LICENSE-2.0 18 | // 19 | // Unless required by applicable law or agreed to in writing, software 20 | // distributed under the License is distributed on an "AS IS" BASIS, 21 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | // See the License for the specific language governing permissions and 23 | // limitations under the License. 24 | // 25 | // @NETFPGA_LICENSE_HEADER_END@ 26 | 27 | `timescale 1ns/1ps 28 | 29 | module tcam 30 | #( 31 | parameter C_TCAM_ADDR_WIDTH = 5, 32 | parameter C_TCAM_DATA_WIDTH = 32, 33 | parameter C_TCAM_ADDR_TYPE = 0, 34 | parameter C_TCAM_MATCH_ADDR_WIDTH = 5 35 | ) 36 | ( 37 | input CLK, 38 | input WE, 39 | input [C_TCAM_ADDR_WIDTH-1:0] ADDR_WR, 40 | input [C_TCAM_DATA_WIDTH-1:0] DIN, 41 | input [C_TCAM_DATA_WIDTH-1:0] DATA_MASK, 42 | output BUSY, 43 | 44 | input [C_TCAM_DATA_WIDTH-1:0] CMP_DIN, 45 | input [C_TCAM_DATA_WIDTH-1:0] CMP_DATA_MASK, 46 | output MATCH, 47 | output [C_TCAM_MATCH_ADDR_WIDTH-1:0] MATCH_ADDR 48 | ); 49 | 50 | 51 | tcam_wrapper 52 | #( 53 | .C_TCAM_ADDR_WIDTH ( C_TCAM_ADDR_WIDTH ), 54 | .C_TCAM_DATA_WIDTH ( C_TCAM_DATA_WIDTH ), 55 | .C_TCAM_ADDR_TYPE ( C_TCAM_ADDR_TYPE ), 56 | .C_TCAM_MATCH_ADDR_WIDTH ( C_TCAM_MATCH_ADDR_WIDTH ) 57 | ) 58 | tcam_wrapper 59 | ( 60 | .CLK ( CLK ), 61 | .WE ( WE ), 62 | .WR_ADDR ( ADDR_WR ), 63 | .DIN ( DIN ), 64 | .DATA_MASK ( DATA_MASK ), 65 | .BUSY ( BUSY ), 66 | 67 | .MATCH ( MATCH ), 68 | .MATCH_ADDR ( MATCH_ADDR ), 69 | .CMP_DIN ( CMP_DIN ), 70 | .CMP_DATA_MASK ( CMP_DATA_MASK ) 71 | ); 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /hw/lib/xilinx/tcam_v1_1_0/hdl/vhdl/tcam/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/lib/xilinx/tcam_v1_1_0/hdl/vhdl/tcam/.keep -------------------------------------------------------------------------------- /hw/lib/xilinx/tcam_v1_1_0/scripts/run_update_lib.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | # Copyright (c) 2015 University of Cambridge 4 | # All rights reserved. 5 | # 6 | # This software was developed by the University of Cambridge Computer 7 | # Laboratory under EPSRC INTERNET Project EP/H040536/1, National Science 8 | # Foundation under Grant No. CNS-0855268, and Defense Advanced Research 9 | # Projects Agency (DARPA) and Air Force Research Laboratory (AFRL), under 10 | # contract FA8750-11-C-0249. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | cam_dir=./xapp1151_cam_v1_1/src 29 | 30 | file_list=`find $cam_dir -name *.vhd` 31 | 32 | for in_file in $file_list; do 33 | 34 | sed -i -e 's/LIBRARY cam/LIBRARY xil_defaultlib/' $in_file 35 | sed -i -e 's/ENTITY cam\./ENTITY xil_defaultlib\./' $in_file 36 | sed -i -e 's/USE cam\./USE xil_defaultlib\./' $in_file 37 | done 38 | 39 | sed -i '/virtex6l/a CONSTANT VIRTEX7 : STRING := "virtex7";' $cam_dir/vhdl/cam_pkg.vhd 40 | sed -i -e 's/spartan6)/spartan6) OR (C_FAMILY = virtex7)/' $cam_dir/vhdl/cam_rtl.vhd 41 | sed -i -e 's/or spartan6/spartan6, or virtex7/' $cam_dir/vhdl/cam_rtl.vhd 42 | -------------------------------------------------------------------------------- /hw/lib/xilinx/tcam_v1_1_0/sim/run_sim.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge All rights reserved. 3 | # 4 | # This software was developed by the University of Cambridge Computer 5 | # Laboratory under EPSRC INTERNET Project EP/H040536/1, National Science 6 | # Foundation under Grant No. CNS-0855268, and Defense Advanced Research 7 | # Projects Agency (DARPA) and Air Force Research Laboratory (AFRL), under 8 | # contract FA8750-11-C-0249. 9 | # 10 | # @NETFPGA_LICENSE_HEADER_START@ 11 | # 12 | # Licensed to NetFPGA Open Systems C.I.C. (NetFPGA) under one or more 13 | # contributor license agreements. See the NOTICE file distributed with this 14 | # work for additional information regarding copyright ownership. NetFPGA 15 | # licenses this file to you under the NetFPGA Hardware-Software License, 16 | # Version 1.0 (the "License"); you may not use this file except in compliance 17 | # with the License. You may obtain a copy of the License at: 18 | # 19 | # http://www.netfpga-cic.org 20 | # 21 | # Unless required by applicable law or agreed to in writing, Work distributed 22 | # under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 23 | # CONDITIONS OF ANY KIND, either express or implied. See the License for the 24 | # specific language governing permissions and limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | add_wave /testbench/sume_tcam/* 29 | run 20us 30 | exit 31 | 32 | -------------------------------------------------------------------------------- /hw/lib/xilinx/xilinx_shell_v1_0_0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2021 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC EARL Project EP/P025374/1 alongside support 7 | # from Xilinx Inc. 8 | # 9 | # @NETFPGA_LICENSE_HEADER_START@ 10 | # 11 | # Licensed under the Apache License, Version 2.0 (the "License"); 12 | # you may not use this file except in compliance with the License. 13 | # You may obtain a copy of the License at 14 | # 15 | # http://www.apache.org/licenses/LICENSE-2.0 16 | # 17 | # Unless required by applicable law or agreed to in writing, software 18 | # distributed under the License is distributed on an "AS IS" BASIS, 19 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | # See the License for the specific language governing permissions and 21 | # limitations under the License. 22 | # 23 | # @NETFPGA_LICENSE_HEADER_END@ 24 | 25 | all: update clean 26 | sed -i -e "s/parameter int NUM_PHYS_FUNC = 1/parameter int NUM_PHYS_FUNC = 2/g" hdl/open_nic_shell.sv 27 | sed -i -e "s/parameter int NUM_CMAC_PORT = 1/parameter int NUM_CMAC_PORT = 2/g" hdl/open_nic_shell.sv 28 | vivado -mode batch -source xilinx_shell.tcl 29 | 30 | update: 31 | bash update.sh 32 | 33 | clean: 34 | rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip proj 35 | 36 | -------------------------------------------------------------------------------- /hw/lib/xilinx/xilinx_shell_v1_0_0/vivado_ip/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/lib/xilinx/xilinx_shell_v1_0_0/vivado_ip/.keep -------------------------------------------------------------------------------- /hw/lib/xilinx/xilinx_shell_v1_0_0/vivado_ip/qdma_subsystem_axi_cdc.tcl: -------------------------------------------------------------------------------- 1 | set axi_clock_converter qdma_subsystem_axi_cdc 2 | create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $axi_clock_converter -dir ${ip_build_dir} 3 | set_property -dict { 4 | CONFIG.PROTOCOL {AXI4LITE} 5 | CONFIG.DATA_WIDTH {32} 6 | CONFIG.ID_WIDTH {0} 7 | CONFIG.AWUSER_WIDTH {0} 8 | CONFIG.ARUSER_WIDTH {0} 9 | CONFIG.RUSER_WIDTH {0} 10 | CONFIG.WUSER_WIDTH {0} 11 | CONFIG.BUSER_WIDTH {0} 12 | CONFIG.SI_CLK.FREQ_HZ {250000000} 13 | CONFIG.MI_CLK.FREQ_HZ {250000000} 14 | CONFIG.ACLK_ASYNC {1} 15 | CONFIG.SYNCHRONIZATION_STAGES {2} 16 | } [get_ips $axi_clock_converter] 17 | -------------------------------------------------------------------------------- /hw/lib/xilinx/xilinx_shell_v1_0_0/vivado_ip/qdma_subsystem_clk_div.tcl: -------------------------------------------------------------------------------- 1 | set clk_wiz qdma_subsystem_clk_div 2 | create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $clk_wiz -dir ${ip_build_dir} 3 | set_property -dict { 4 | CONFIG.PRIMITIVE {Auto} 5 | CONFIG.USE_PHASE_ALIGNMENT {true} 6 | CONFIG.PRIM_IN_FREQ {250} 7 | CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} 8 | CONFIG.CLKIN1_JITTER_PS {40.0} 9 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {250.000} 10 | CONFIG.CLKOUT1_DRIVES {Buffer} 11 | CONFIG.CLKOUT2_DRIVES {Buffer} 12 | CONFIG.CLKOUT3_DRIVES {Buffer} 13 | CONFIG.CLKOUT4_DRIVES {Buffer} 14 | CONFIG.CLKOUT5_DRIVES {Buffer} 15 | CONFIG.CLKOUT6_DRIVES {Buffer} 16 | CONFIG.CLKOUT7_DRIVES {Buffer} 17 | CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} 18 | CONFIG.USE_LOCKED {true} 19 | CONFIG.USE_RESET {false} 20 | CONFIG.MMCM_BANDWIDTH {OPTIMIZED} 21 | CONFIG.MMCM_CLKIN1_PERIOD {4.000} 22 | CONFIG.MMCM_CLKIN2_PERIOD {10.0} 23 | CONFIG.MMCM_COMPENSATION {AUTO} 24 | CONFIG.AUTO_PRIMITIVE {MMCM} 25 | CONFIG.MMCM_DIVCLK_DIVIDE {1} 26 | CONFIG.MMCM_CLKFBOUT_MULT_F {4.750} 27 | CONFIG.MMCM_CLKIN1_PERIOD {4.000} 28 | CONFIG.MMCM_CLKIN2_PERIOD {10.0} 29 | CONFIG.MMCM_CLKOUT0_DIVIDE_F {4.750} 30 | CONFIG.CLKOUT1_JITTER {85.152} 31 | CONFIG.CLKOUT1_PHASE_ERROR {78.266} 32 | } [get_ips $clk_wiz] 33 | -------------------------------------------------------------------------------- /hw/projects/reference_nic/bitfiles/README: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2021 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC EARL Project EP/P025374/1 alongside support 7 | # from Xilinx Inc. 8 | # 9 | # @NETFPGA_LICENSE_HEADER_START@ 10 | # 11 | # Licensed under the Apache License, Version 2.0 (the "License"); 12 | # you may not use this file except in compliance with the License. 13 | # You may obtain a copy of the License at 14 | # 15 | # http://www.apache.org/licenses/LICENSE-2.0 16 | # 17 | # Unless required by applicable law or agreed to in writing, software 18 | # distributed under the License is distributed on an "AS IS" BASIS, 19 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | # See the License for the specific language governing permissions and 21 | # limitations under the License. 22 | # 23 | # @NETFPGA_LICENSE_HEADER_END@ 24 | # 25 | 26 | Reference NIC bitfile is available for a direct download from the University of Cambridge servers: 27 | 28 | 1. Reference NIC (VCU1525) 29 | url: http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/bitfiles/NetFPGA-PLUS/1.0.0/reference_nic/reference_nic_vcu1525.bit 30 | md5 checksum: f689c1da8d1d02e31933fc50c6295431 31 | 32 | 2. Reference NIC (U200) 33 | url: http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/bitfiles/NetFPGA-PLUS/1.0.0/reference_nic/reference_nic_au200.bit 34 | md5 checksum: d7554958f440634a2dbd349e91cb9831 35 | 36 | 3. Reference NIC (U250) 37 | url: http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/bitfiles/NetFPGA-PLUS/1.0.0/reference_nic/reference_nic_au250.bit 38 | md5 checksum: d540af93f4eaf4b8e69f073086134922 39 | 40 | 4. Reference NIC (U280) 41 | url: http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/bitfiles/NetFPGA-PLUS/1.0.0/reference_nic/reference_nic_au280.bit 42 | md5 checksum: c3715ab5bc82a0beb84be00a29a32da7 43 | -------------------------------------------------------------------------------- /hw/projects/reference_nic/hw/constraints/au200_vcu1525_user_timing.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2021 Yuta Tokusashi 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC EARL Project EP/P025374/1 alongside support 7 | # from Xilinx Inc. 8 | # 9 | # @NETFPGA_LICENSE_HEADER_START@ 10 | # 11 | # Licensed under the Apache License, Version 2.0 (the "License"); 12 | # you may not use this file except in compliance with the License. 13 | # You may obtain a copy of the License at 14 | # 15 | # http://www.apache.org/licenses/LICENSE-2.0 16 | # 17 | # Unless required by applicable law or agreed to in writing, software 18 | # distributed under the License is distributed on an "AS IS" BASIS, 19 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | # See the License for the specific language governing permissions and 21 | # limitations under the License. 22 | # 23 | # @NETFPGA_LICENSE_HEADER_END@ 24 | # 25 | 26 | create_pblock pblock_nf_datapath 27 | add_cells_to_pblock [get_pblocks pblock_nf_datapath] [get_cells -quiet [list nf_datapath_0]] 28 | add_cells_to_pblock [get_pblocks pblock_nf_datapath] [get_cells -quiet [list u_top_wrapper/u_nf_attachment]] 29 | resize_pblock [get_pblocks pblock_nf_datapath] -add {SLR2} 30 | 31 | -------------------------------------------------------------------------------- /hw/projects/reference_nic/hw/tcl/reference_nic_defines.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Noa Zilberman 3 | # Copyright (c) 2021 Yuta Tokusashi 4 | # All rights reserved. 5 | # 6 | # This software was developed by Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme, 11 | # and by the University of Cambridge Computer Laboratory under EPSRC EARL Project 12 | # EP/P025374/1 alongside support from Xilinx Inc. 13 | # 14 | # @NETFPGA_LICENSE_HEADER_START@ 15 | # 16 | # Licensed under the Apache License, Version 2.0 (the "License"); 17 | # you may not use this file except in compliance with the License. 18 | # You may obtain a copy of the License at 19 | # 20 | # http://www.apache.org/licenses/LICENSE-2.0 21 | # 22 | # Unless required by applicable law or agreed to in writing, software 23 | # distributed under the License is distributed on an "AS IS" BASIS, 24 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | # See the License for the specific language governing permissions and 26 | # limitations under the License. 27 | # 28 | # @NETFPGA_LICENSE_HEADER_END@ 29 | # 30 | 31 | ####################### 32 | # Segments Assignment # 33 | ####################### 34 | #M00 35 | set M00_BASEADDR 0x00010000 36 | set M00_HIGHADDR 0x00010FFF 37 | set M00_SIZEADDR 0x1000 38 | 39 | #M01 40 | set M01_BASEADDR 0x00020000 41 | set M01_HIGHADDR 0x00020FFF 42 | set M01_SIZEADDR 0x1000 43 | 44 | #M02 45 | set M02_BASEADDR 0x00030000 46 | set M02_HIGHADDR 0x00030FFF 47 | set M02_SIZEADDR 0x1000 48 | 49 | ##M03 50 | #set M03_BASEADDR 0x44030000 51 | #set M03_HIGHADDR 0x44030FFF 52 | #set M03_SIZEADDR 0x1000 53 | # 54 | 55 | ####################### 56 | # IP_ASSIGNMENT # 57 | ####################### 58 | # Note that physical connectivity must match this mapping 59 | 60 | ##IDENTIFIER base address and size 61 | #set IDENTIFIER_BASEADDR $M00_BASEADDR 62 | #set IDENTIFIER_HIGHADDR $M00_HIGHADDR 63 | #set IDENTIFIER_SIZEADDR $M00_SIZEADDR 64 | 65 | 66 | #INPUT ARBITER base address and size 67 | set INPUT_ARBITER_BASEADDR $M00_BASEADDR 68 | set INPUT_ARBITER_HIGHADDR $M00_HIGHADDR 69 | set INPUT_ARBITER_SIZEADDR $M00_SIZEADDR 70 | 71 | #OUTPUT_QUEUES base address and size 72 | set OUTPUT_QUEUES_BASEADDR $M02_BASEADDR 73 | set OUTPUT_QUEUES_HIGHADDR $M02_HIGHADDR 74 | set OUTPUT_QUEUES_SIZEADDR $M02_SIZEADDR 75 | 76 | #OUPUT_PORT_LOOKUP base address and size 77 | set OUTPUT_PORT_LOOKUP_BASEADDR $M01_BASEADDR 78 | set OUTPUT_PORT_LOOKUP_HIGHADDR $M01_HIGHADDR 79 | set OUTPUT_PORT_LOOKUP_SIZEADDR $M01_SIZEADDR 80 | -------------------------------------------------------------------------------- /hw/projects/reference_nic/test/connections/conn: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by Stanford University and the University of Cambridge Computer Laboratory 6 | # under National Science Foundation under Grant No. CNS-0855268, 7 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 8 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 9 | # as part of the DARPA MRC research programme. 10 | # 11 | # @NETFPGA_LICENSE_HEADER_START@ 12 | # 13 | # Licensed under the Apache License, Version 2.0 (the "License"); 14 | # you may not use this file except in compliance with the License. 15 | # You may obtain a copy of the License at 16 | # 17 | # http://www.apache.org/licenses/LICENSE-2.0 18 | # 19 | # Unless required by applicable law or agreed to in writing, software 20 | # distributed under the License is distributed on an "AS IS" BASIS, 21 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | # See the License for the specific language governing permissions and 23 | # limitations under the License. 24 | # 25 | # @NETFPGA_LICENSE_HEADER_END@ 26 | # 27 | 28 | 29 | nf0:nf0 30 | nf1:nf1 31 | -------------------------------------------------------------------------------- /hw/projects/reference_nic/test/global/setup: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # 4 | # Copyright (c) 2015 University of Cambridge 5 | # All rights reserved. 6 | # 7 | # This software was developed by Stanford University and the University of Cambridge Computer Laboratory 8 | # under National Science Foundation under Grant No. CNS-0855268, 9 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 10 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 11 | # as part of the DARPA MRC research programme. 12 | # 13 | # @NETFPGA_LICENSE_HEADER_START@ 14 | # 15 | # Licensed under the Apache License, Version 2.0 (the "License"); 16 | # you may not use this file except in compliance with the License. 17 | # You may obtain a copy of the License at 18 | # 19 | # http://www.apache.org/licenses/LICENSE-2.0 20 | # 21 | # Unless required by applicable law or agreed to in writing, software 22 | # distributed under the License is distributed on an "AS IS" BASIS, 23 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | # See the License for the specific language governing permissions and 25 | # limitations under the License. 26 | # 27 | # @NETFPGA_LICENSE_HEADER_END@ 28 | # 29 | 30 | from subprocess import Popen, PIPE 31 | 32 | proc = Popen(["ifconfig","eth1","192.168.100.1"], stdout=PIPE) 33 | proc = Popen(["ifconfig","eth2","192.168.101.1"], stdout=PIPE) 34 | proc = Popen(["ifconfig","nf0","192.168.200.1"], stdout=PIPE) 35 | proc = Popen(["ifconfig","nf1","192.168.201.1"], stdout=PIPE) 36 | -------------------------------------------------------------------------------- /hw/projects/reference_router/bitfiles/README: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2021 University of Cambridge 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC EARL Project EP/P025374/1 alongside support 7 | # from Xilinx Inc. 8 | # 9 | # @NETFPGA_LICENSE_HEADER_START@ 10 | # 11 | # Licensed under the Apache License, Version 2.0 (the "License"); 12 | # you may not use this file except in compliance with the License. 13 | # You may obtain a copy of the License at 14 | # 15 | # http://www.apache.org/licenses/LICENSE-2.0 16 | # 17 | # Unless required by applicable law or agreed to in writing, software 18 | # distributed under the License is distributed on an "AS IS" BASIS, 19 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | # See the License for the specific language governing permissions and 21 | # limitations under the License. 22 | # 23 | # @NETFPGA_LICENSE_HEADER_END@ 24 | # 25 | 26 | Reference Router bitfile is available for a direct download from the University of Cambridge servers: 27 | 28 | 1. Reference Router (VCU1525) 29 | url: http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/bitfiles/NetFPGA-PLUS/1.0.0/reference_router/reference_router_vcu1525.bit 30 | md5 checksum: 2ec97cfedcd09d716e62c8e7ec041878 31 | 32 | 2. Reference Router (U200) 33 | url: http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/bitfiles/NetFPGA-PLUS/1.0.0/reference_router/reference_router_au200.bit 34 | md5 checksum: 09cbb497a50def6263525e23dec5b8be 35 | 36 | 3. Reference Router (U250) 37 | url: http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/bitfiles/NetFPGA-PLUS/1.0.0/reference_router/reference_router_au250.bit 38 | md5 checksum: caf3ff3d42f7aeaa2fde6a1e1afc89bd 39 | 40 | 4. Reference Router (U280) 41 | url: http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/bitfiles/NetFPGA-PLUS/1.0.0/reference_router/reference_router_au280.bit 42 | md5 checksum: d8c6cb97505dd22edc30ed7e0af416d7 43 | -------------------------------------------------------------------------------- /hw/projects/reference_router/hw/constraints/au200_vcu1525_user_timing.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2021 Yuta Tokusashi 3 | # All rights reserved. 4 | # 5 | # This software was developed by the University of Cambridge Computer 6 | # Laboratory under EPSRC EARL Project EP/P025374/1 alongside support 7 | # from Xilinx Inc. 8 | # 9 | # @NETFPGA_LICENSE_HEADER_START@ 10 | # 11 | # Licensed under the Apache License, Version 2.0 (the "License"); 12 | # you may not use this file except in compliance with the License. 13 | # You may obtain a copy of the License at 14 | # 15 | # http://www.apache.org/licenses/LICENSE-2.0 16 | # 17 | # Unless required by applicable law or agreed to in writing, software 18 | # distributed under the License is distributed on an "AS IS" BASIS, 19 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | # See the License for the specific language governing permissions and 21 | # limitations under the License. 22 | # 23 | # @NETFPGA_LICENSE_HEADER_END@ 24 | # 25 | 26 | create_pblock pblock_nf_datapath 27 | add_cells_to_pblock [get_pblocks pblock_nf_datapath] [get_cells -quiet [list nf_datapath_0]] 28 | add_cells_to_pblock [get_pblocks pblock_nf_datapath] [get_cells -quiet [list u_top_wrapper/u_nf_attachment]] 29 | resize_pblock [get_pblocks pblock_nf_datapath] -add {SLR2} 30 | 31 | set_false_path -from [get_cells u_top_wrapper/u_nf_attachment/u_nf_attachment_1/inst/tx_fifo_rst/sync1_r_reg[5]] 32 | -------------------------------------------------------------------------------- /hw/projects/reference_router/hw/tcl/reference_router_defines.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Noa Zilberman 3 | # Copyright (c) 2021 Yuta Tokusashi 4 | # All rights reserved. 5 | # 6 | # This software was developed by Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme, 11 | # and by the University of Cambridge Computer Laboratory under EPSRC EARL Project 12 | # EP/P025374/1 alongside support from Xilinx Inc. 13 | # 14 | # @NETFPGA_LICENSE_HEADER_START@ 15 | # 16 | # Licensed under the Apache License, Version 2.0 (the "License"); 17 | # you may not use this file except in compliance with the License. 18 | # You may obtain a copy of the License at 19 | # 20 | # http://www.apache.org/licenses/LICENSE-2.0 21 | # 22 | # Unless required by applicable law or agreed to in writing, software 23 | # distributed under the License is distributed on an "AS IS" BASIS, 24 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | # See the License for the specific language governing permissions and 26 | # limitations under the License. 27 | # 28 | # @NETFPGA_LICENSE_HEADER_END@ 29 | # 30 | 31 | 32 | 33 | ####################### 34 | # Segments Assignment # 35 | ####################### 36 | #M00 37 | set M00_BASEADDR 0x00010000 38 | set M00_HIGHADDR 0x00010FFF 39 | set M00_SIZEADDR 0x1000 40 | 41 | #M01 42 | set M01_BASEADDR 0x00020000 43 | set M01_HIGHADDR 0x00020FFF 44 | set M01_SIZEADDR 0x1000 45 | 46 | #M02 47 | set M02_BASEADDR 0x00030000 48 | set M02_HIGHADDR 0x00030FFF 49 | set M02_SIZEADDR 0x1000 50 | 51 | ##M03 52 | #set M03_BASEADDR 0x44030000 53 | #set M03_HIGHADDR 0x44030FFF 54 | #set M03_SIZEADDR 0x1000 55 | # 56 | 57 | ####################### 58 | # IP_ASSIGNMENT # 59 | ####################### 60 | # Note that physical connectivity must match this mapping 61 | 62 | ##IDENTIFIER base address and size 63 | #set IDENTIFIER_BASEADDR $M00_BASEADDR 64 | #set IDENTIFIER_HIGHADDR $M00_HIGHADDR 65 | #set IDENTIFIER_SIZEADDR $M00_SIZEADDR 66 | 67 | 68 | #INPUT ARBITER base address and size 69 | set INPUT_ARBITER_BASEADDR $M00_BASEADDR 70 | set INPUT_ARBITER_HIGHADDR $M00_HIGHADDR 71 | set INPUT_ARBITER_SIZEADDR $M00_SIZEADDR 72 | 73 | #OUTPUT_QUEUES base address and size 74 | set OUTPUT_QUEUES_BASEADDR $M02_BASEADDR 75 | set OUTPUT_QUEUES_HIGHADDR $M02_HIGHADDR 76 | set OUTPUT_QUEUES_SIZEADDR $M02_SIZEADDR 77 | 78 | #OUPUT_PORT_LOOKUP base address and size 79 | set OUTPUT_PORT_LOOKUP_BASEADDR $M01_BASEADDR 80 | set OUTPUT_PORT_LOOKUP_HIGHADDR $M01_HIGHADDR 81 | set OUTPUT_PORT_LOOKUP_SIZEADDR $M01_SIZEADDR 82 | 83 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/apps/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2015 Bjoern A. Zeeb 3 | # All rights reserved. 4 | # 5 | # File: 6 | # Makefile 7 | # 8 | # This software was developed by Stanford University and the University of Cambridge Computer Laboratory 9 | # under National Science Foundation under Grant No. CNS-0855268, 10 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 11 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 12 | # as part of the DARPA MRC research programme. 13 | # 14 | # @NETFPGA_LICENSE_HEADER_START@ 15 | # 16 | # Licensed under the Apache License, Version 2.0 (the "License"); 17 | # you may not use this file except in compliance with the License. 18 | # You may obtain a copy of the License at 19 | # 20 | # http://www.apache.org/licenses/LICENSE-2.0 21 | # 22 | # Unless required by applicable law or agreed to in writing, software 23 | # distributed under the License is distributed on an "AS IS" BASIS, 24 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | # See the License for the specific language governing permissions and 26 | # limitations under the License. 27 | # 28 | # @NETFPGA_LICENSE_HEADER_END@ 29 | # 30 | 31 | all: rwaxi 32 | 33 | rwaxi: 34 | cc -Wall -Werror -o rwaxi rwaxi.c -I../common 35 | 36 | clean: 37 | rm -f rwaxi 38 | 39 | # end 40 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/apps/register_write.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | # Copyright (c) 2015 University of Cambridge 4 | # All rights reserved. 5 | # 6 | # This software was developed by Stanford University and the University of Cambridge Computer Laboratory 7 | # under National Science Foundation under Grant No. CNS-0855268, 8 | # the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 9 | # by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 10 | # as part of the DARPA MRC research programme. 11 | # 12 | # @NETFPGA_LICENSE_HEADER_START@ 13 | # 14 | # Licensed under the Apache License, Version 2.0 (the "License"); 15 | # you may not use this file except in compliance with the License. 16 | # You may obtain a copy of the License at 17 | # 18 | # http://www.apache.org/licenses/LICENSE-2.0 19 | # 20 | # Unless required by applicable law or agreed to in writing, software 21 | # distributed under the License is distributed on an "AS IS" BASIS, 22 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | # See the License for the specific language governing permissions and 24 | # limitations under the License. 25 | # 26 | # @NETFPGA_LICENSE_HEADER_END@ 27 | # 28 | 29 | 30 | 31 | echo "===> NFPLUS_INPUT_ARBITER_BASEADDR (0x00010000)" 32 | 33 | echo "===> NFPLUS_OUTPUT_QUEUES_BASEADDR (0x00030000)" 34 | 35 | echo "===> NFPLUS_OUTPUT_PORT_LOOKUP_BASEADDR (0x00020000)" 36 | 37 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/cli/Makefile: -------------------------------------------------------------------------------- 1 | #/******************************************************************************* 2 | #* 3 | #* Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | #* Junior University 5 | #* All rights reserved. 6 | #* 7 | #* This software was developed by 8 | #* Stanford University and the University of Cambridge Computer Laboratory 9 | #* under National Science Foundation under Grant No. CNS-0855268, 10 | #* the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 11 | #* by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 12 | #* as part of the DARPA MRC research programme. 13 | #* 14 | #* @NETFPGA_LICENSE_HEADER_START@ 15 | #* 16 | #* Licensed under the Apache License, Version 2.0 (the "License"); 17 | #* you may not use this file except in compliance with the License. 18 | #* You may obtain a copy of the License at 19 | #* 20 | #* http://www.apache.org/licenses/LICENSE-2.0 21 | #* 22 | #* Unless required by applicable law or agreed to in writing, software 23 | #* distributed under the License is distributed on an "AS IS" BASIS, 24 | #* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | #* See the License for the specific language governing permissions and 26 | #* limitations under the License. 27 | #* 28 | #* @NETFPGA_LICENSE_HEADER_END@ 29 | #* 30 | #* 31 | #******************************************************************************/ 32 | 33 | CFLAGS = -g -Wall 34 | CC = gcc 35 | 36 | # Location of binary files 37 | BINDIR ?= /usr/local/bin 38 | 39 | INSTALL_PREFIX ?= /usr/local 40 | 41 | # Location of common files 42 | COMMON = ../common 43 | 44 | all : common cli 45 | 46 | common : 47 | $(MAKE) -C $(COMMON) 48 | 49 | cli : cli.o ../common/nfplus_util.o 50 | 51 | clean : 52 | rm -f cli *.o 53 | 54 | install: 55 | 56 | .PHONY: all clean install 57 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/cli/arp: -------------------------------------------------------------------------------- 1 | 0 192.168.2.1 00:00:00:00:00:01 2 | 1 192.168.1.1 00:00:00:00:00:02 3 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/cli/ip: -------------------------------------------------------------------------------- 1 | 0 192.168.1.1 255.255.255.255 192.168.1.1 0x10 2 | 1 192.168.2.1 255.255.255.255 192.168.2.1 0x4 3 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/cli/mac: -------------------------------------------------------------------------------- 1 | 1 00:4E:46:31:30:00 2 | 2 00:4E:46:31:30:01 3 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/common/Makefile: -------------------------------------------------------------------------------- 1 | #/******************************************************************************* 2 | #* 3 | #* Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | #* Junior University 5 | #* All rights reserved. 6 | #* 7 | #* This software was developed by 8 | #* Stanford University and the University of Cambridge Computer Laboratory 9 | #* under National Science Foundation under Grant No. CNS-0855268, 10 | #* the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 11 | #* by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 12 | #* as part of the DARPA MRC research programme. 13 | #* 14 | #* @NETFPGA_LICENSE_HEADER_START@ 15 | #* 16 | #* Licensed under the Apache License, Version 2.0 (the "License"); 17 | #* you may not use this file except in compliance with the License. 18 | #* You may obtain a copy of the License at 19 | #* 20 | #* http://www.apache.org/licenses/LICENSE-2.0 21 | #* 22 | #* Unless required by applicable law or agreed to in writing, software 23 | #* distributed under the License is distributed on an "AS IS" BASIS, 24 | #* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | #* See the License for the specific language governing permissions and 26 | #* limitations under the License. 27 | #* 28 | #* @NETFPGA_LICENSE_HEADER_END@ 29 | #* 30 | #* 31 | #******************************************************************************/ 32 | 33 | all : nfplus_util.o libnfplus.so 34 | 35 | libnfplus.so: nfplus_util.c nfplus_util.h nf_util.c nf_util.h 36 | gcc -fpic -c nfplus_util.c nf_util.c 37 | gcc -shared nfplus_util.o nf_util.o -o $@ 38 | 39 | clean : 40 | rm -rf nfplus_util.o nf_util.o libnfplus.so 41 | 42 | install: libnfplus.so 43 | install -d /usr/local/lib 44 | install -m 644 libnfplus.so /usr/local/lib 45 | ln -s -f /usr/local/lib/libnfplus.so /usr/local/lib/libnfplusregs.so 46 | ldconfig 47 | 48 | .PHONY: clean 49 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/common/nf_util.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * All rights reserved. 6 | * 7 | * This software was developed by 8 | * Stanford University and the University of Cambridge Computer Laboratory 9 | * under National Science Foundation under Grant No. CNS-0855268, 10 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 11 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 12 | * as part of the DARPA MRC research programme. 13 | * 14 | * @NETFPGA_LICENSE_HEADER_START@ 15 | * 16 | * Licensed under the Apache License, Version 2.0 (the "License"); 17 | * you may not use this file except in compliance with the License. 18 | * You may obtain a copy of the License at 19 | * 20 | * http://www.apache.org/licenses/LICENSE-2.0 21 | * 22 | * Unless required by applicable law or agreed to in writing, software 23 | * distributed under the License is distributed on an "AS IS" BASIS, 24 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | * See the License for the specific language governing permissions and 26 | * limitations under the License. 27 | * 28 | * @NETFPGA_LICENSE_HEADER_END@ 29 | * 30 | * 31 | ******************************************************************************/ 32 | 33 | 34 | #ifndef _NF_UTIL_H 35 | #define _NF_UTIL_H 1 36 | 37 | /* Include for socket IOCTLs */ 38 | #include 39 | 40 | #define PATHLEN 80 41 | #define DEVICE_STR_LEN 120 42 | 43 | 44 | /* 45 | * Structure to represent an nf device to a user mode programs 46 | */ 47 | struct nf_device { 48 | char *device_name; 49 | int fd; 50 | int net_iface; 51 | }; 52 | typedef struct nf_device nf_device; 53 | 54 | /* 55 | * IOCTLs 56 | */ 57 | #define SIOCREGSTAT (SIODEVPRIVATE+0) 58 | #define SIOCREGREAD (SIOCDEVPRIVATE+2) 59 | #define SIOCREGWRITE (SIOCDEVPRIVATE+1) 60 | 61 | 62 | /* 63 | * Structure for transferring register data via an IOCTL 64 | */ 65 | struct nf_reg { 66 | unsigned int reg; 67 | unsigned int val; 68 | }; 69 | 70 | 71 | /* Function declarations */ 72 | 73 | int check_iface(struct nf_device *nf); 74 | int openDescriptor(struct nf_device *nf); 75 | int closeDescriptor(struct nf_device *nf); 76 | 77 | extern char nf_device_str[DEVICE_STR_LEN]; 78 | 79 | #endif 80 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/common/nfplus_util.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) 2015 Gianni Antichi 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | 35 | int readReg(int f, uint32_t addr, uint32_t *val); 36 | int writeReg(int f, uint32_t addr, uint32_t val); 37 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/router_kit/Makefile: -------------------------------------------------------------------------------- 1 | #/******************************************************************************* 2 | #* 3 | #* Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | #* Junior University 5 | #* Copyright (C) Martin Casado 6 | #* All rights reserved. 7 | #* 8 | #* This software was developed by 9 | #* Stanford University and the University of Cambridge Computer Laboratory 10 | #* under National Science Foundation under Grant No. CNS-0855268, 11 | #* the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | #* by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | #* as part of the DARPA MRC research programme. 14 | #* 15 | #* @NETFPGA_LICENSE_HEADER_START@ 16 | #* 17 | #* Licensed under the Apache License, Version 2.0 (the "License"); 18 | #* you may not use this file except in compliance with the License. 19 | #* You may obtain a copy of the License at 20 | #* 21 | #* http://www.apache.org/licenses/LICENSE-2.0 22 | #* 23 | #* Unless required by applicable law or agreed to in writing, software 24 | #* distributed under the License is distributed on an "AS IS" BASIS, 25 | #* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | #* See the License for the specific language governing permissions and 27 | #* limitations under the License. 28 | #* 29 | #* @NETFPGA_LICENSE_HEADER_END@ 30 | #* 31 | #* 32 | #******************************************************************************/ 33 | 34 | 35 | all: rkd 36 | 37 | HEADERS = rtable.hh arptable.hh sume_mon.hh iflist.hh 38 | CXXFLAGS = -g -Wall -ansi 39 | 40 | rkd : rkd.cc linux_proc_net.o sume_mon.o ../common/nfplus_util.o $(HEADERS) 41 | g++ -g -Wall -o rkd rkd.cc sume_mon.o ../common/nfplus_util.o linux_proc_net.o 42 | 43 | clean: 44 | rm -f *.o rkd 45 | 46 | install: 47 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/router_kit/linux_proc_net.hh: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) Martin Casado 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | 35 | #ifndef LINUX_PROC_NET_HH__ 36 | #define LINUX_PROC_NET_HH__ 37 | 38 | #include "rtable.hh" 39 | #include "arptable.hh" 40 | 41 | namespace rk 42 | { 43 | 44 | static const char PROC_ROUTE_FILE[] = "/proc/net/route"; 45 | static const char PROC_ARP_FILE[] = "/proc/net/arp"; 46 | static const char PROC_DEV_FILE[] = "/proc/net/dev"; 47 | 48 | void 49 | linux_proc_net_load_rtable(rtable& rt); 50 | 51 | void 52 | linux_proc_net_load_arptable(arptable& rt); 53 | 54 | } // -- namespace rk 55 | 56 | 57 | #endif // -- LINUX_PROC_NET_HH__ 58 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/README: -------------------------------------------------------------------------------- 1 | 2 | /******************************************************************************* 3 | * 4 | * @NETFPGA_LICENSE_HEADER_START@ 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the "License"); 7 | * you may not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * http://www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an "AS IS" BASIS, 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * @NETFPGA_LICENSE_HEADER_END@ 19 | * 20 | * 21 | ******************************************************************************/ 22 | 23 | 24 | File: README 25 | Date: Tue Feb 03 15:57:46 PST 2004 26 | Last Modified: Wed Apr 04 06:18:07 PDT 2007 27 | Author: Martin Casado 28 | 29 | This directory contains the code base for developing a functional 30 | internet router that supports TCP and user level programs. 31 | 32 | Decsription of Files: 33 | 34 | - sr_main.c : The entry point to the full system. This starts the 35 | lower level routing functionality in a seperate thread 36 | and then idles in a sleep(..) loop. 'User level' network 37 | code that use the standard bsd sockets can be run from main, 38 | and if linked correctly will use the sr network underlayer. 39 | 40 | - sr_base.c : Entry point to the full low level networking code. sr_base 41 | is responsible for housing the "global" instance of the 42 | router, starting the transport subsystem, and managing the 43 | connection to the VNS. 44 | 45 | - sr_integration.c : Contains all the methods which need to be 46 | extended to support a full running router. This 47 | includes callback methods for each packet, methods 48 | to send packets, methods which pass in hardware 49 | information etc. 50 | 51 | - sr_vns.c : handles communication with the VNS server 52 | 53 | - sr_dumper.c : Methods supporting writing packets in pcap format 54 | 55 | - sr_lwtcp_glue.c : compatibility methods for integrating with lwip 56 | 57 | - sr_cpu_extension_nf2.c : Contains code for interfacing with the hardware. 58 | This file contains two methods that have to be 59 | completed by the students and should be extended to 60 | add support for register reads/writes. 61 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/TODO.txt: -------------------------------------------------------------------------------- 1 | **DAVID:CODE/TEST**-Check that an interface broadcasts a neighbor rid of 0 in an LSU update if there is 2 | no hello from the neighbor on that interface, or if the hello has timed out 3 | 4 | **DAVID:CODE/TEST**-Check that if a hello expires, or a new one is heard (that adds a neighbor to a link), 5 | that it immediately updates the associated pwospf_router (ours), and initiates a LSU flood, and dijkstra update 6 | 7 | **DAVID:CODE/TEST**-Ensure nbr_rid is reset to 0 on a hello timeout (and the rest of the associated 8 | fields are reset, nbr_ip etc) 9 | 10 | **DAVID:CODE**-Ensure pwospf packets NOT in our area get dropped 11 | 12 | -Ensure when a link is downed via the CLI that it's neighbor info is reset to 0, 13 | the pwospf_router is updated, a LSU flood is initiated, and dijkstra's is run 14 | 15 | -Same thing for bringing a link up 16 | 17 | **DAVID:CODE/TEST**-Test that pwospf_router's get deleted when their entry times out (3x LSU INT) 18 | 19 | **DAVID:CODE/TEST**-If pwospf packet's authtype != 0 it is dropped 20 | 21 | **DAVID:CODE**-Ensure incoming hello packet's source ips are checked to see if they match 22 | the given interface's neighbor ip, if it exists. 23 | 24 | **DAVID:CODE/TEST**-ensure helloint timeout is a global value (NOT per interface), and that 25 | if an incoming hello packet's helloint does not match our router's helloint, 26 | that the packet is dropped 27 | 28 | **FILIP:CODE/TEST**-Check that we rebroadcast LSU packets that we receive to all interfaces 29 | except the one we received it on, and that we have decremented and checked the 30 | ttl to see if we need to expire the packet. Make sure we create a new 31 | ethernet, ip, etc header. 32 | 33 | **DAVID:CODE/TEST**-Ensure a helloint timeout on a link causes an LSU flood and dijkstra run 34 | 35 | **DAVID:CODE/TEST**-Have a flag on the dijkstra thread letting it know it needs to run in addition to the signal 36 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/cpuhw: -------------------------------------------------------------------------------- 1 | eth0 192.168.3.1 255.255.255.0 00:00:00:00:01:01 2 | eth1 192.168.2.2 255.255.255.0 00:00:00:00:01:02 3 | eth2 192.168.1.2 255.255.255.0 00:00:00:00:01:03 4 | eth3 192.168.9.2 255.255.255.0 00:00:00:00:01:04 5 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/design_doc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/projects/reference_router/sw/scone/design_doc.pdf -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/lwtcp/lwtcp_sr_integration.h: -------------------------------------------------------------------------------- 1 | 2 | /******************************************************************************* 3 | * 4 | * @NETFPGA_LICENSE_HEADER_START@ 5 | * 6 | * Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor 7 | * license agreements. See the NOTICE file distributed with this work for 8 | * additional information regarding copyright ownership. NetFPGA licenses this 9 | * file to you under the NetFPGA Hardware-Software License, Version 1.0 (the 10 | * "License"); you may not use this file except in compliance with the 11 | * License. You may obtain a copy of the License at: 12 | * 13 | * http://www.netfpga-cic.org 14 | * 15 | * Unless required by applicable law or agreed to in writing, Work distributed 16 | * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | * CONDITIONS OF ANY KIND, either express or implied. See the License for the 18 | * specific language governing permissions and limitations under the License. 19 | * 20 | * @NETFPGA_LICENSE_HEADER_END@ 21 | * 22 | * 23 | ******************************************************************************/ 24 | 25 | 26 | 27 | #ifndef LWTCP_SR_INTEGRATION_H 28 | #define LWTCP_SR_INTEGRATION_H 29 | 30 | #include "lwip/ip_addr.h" 31 | #include "lwip/ip.h" 32 | #include "lwip/netif.h" 33 | #include "lwip/pbuf.h" 34 | #include "lwip/transport_subsys.h" 35 | 36 | uint32_t /*nbo*/ ip_route(struct ip_addr *dest); 37 | err_t sr_lwip_output(struct pbuf *p,struct ip_addr *src, struct ip_addr *dst, uint8_t proto ); 38 | 39 | #endif /* LWTCP_SR_INTEGRATION_H */ 40 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/lwtcp/main.c: -------------------------------------------------------------------------------- 1 | 2 | /******************************************************************************* 3 | * 4 | * @NETFPGA_LICENSE_HEADER_START@ 5 | * 6 | * Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor 7 | * license agreements. See the NOTICE file distributed with this work for 8 | * additional information regarding copyright ownership. NetFPGA licenses this 9 | * file to you under the NetFPGA Hardware-Software License, Version 1.0 (the 10 | * "License"); you may not use this file except in compliance with the 11 | * License. You may obtain a copy of the License at: 12 | * 13 | * http://www.netfpga-cic.org 14 | * 15 | * Unless required by applicable law or agreed to in writing, Work distributed 16 | * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | * CONDITIONS OF ANY KIND, either express or implied. See the License for the 18 | * specific language governing permissions and limitations under the License. 19 | * 20 | * @NETFPGA_LICENSE_HEADER_END@ 21 | * 22 | * 23 | ******************************************************************************/ 24 | 25 | 26 | 27 | #include "lwip/tcp.h" 28 | 29 | struct netif *ip_route(struct ip_addr *dest) 30 | { 31 | } 32 | 33 | err_t sr_ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, 34 | uint8_t ttl, uint8_t proto) 35 | { 36 | } 37 | 38 | err_t sr_ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, 39 | uint8_t ttl, uint8_t proto, 40 | struct netif *netif) 41 | { 42 | } 43 | 44 | static void 45 | main_thread(void *arg) 46 | { 47 | tcp_init(); 48 | 49 | while(1) 50 | { 51 | tcp_input 52 | } 53 | } 54 | 55 | int main(int argc,char **argv) 56 | { 57 | sys_init(); 58 | mem_init(); 59 | memp_init(); 60 | pbuf_init(); 61 | 62 | 63 | sys_thread_new((void *)(main_thread), NULL); 64 | pause(); 65 | 66 | return 0; 67 | } 68 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/or_cli.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) David Erickson, Filip Paun 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | 35 | #ifndef OR_CLI_H_ 36 | #define OR_CLI_H_ 37 | 38 | #include "or_data_types.h" 39 | 40 | int cli_main(void* subsystem); 41 | 42 | cli_command_handler cli_command_lpm(router_state* rs, char* command); 43 | void process_client_request_np(void* arg); 44 | void* process_client_request(void *arg); 45 | 46 | void lock_cli_commands_rd(void* subsys); 47 | void unlock_cli_commands(void* subsys); 48 | 49 | void cli_help(router_state *rs, cli_request *req); 50 | void cli_show_help(router_state *rs, cli_request *req); 51 | void cli_hw_help(router_state *rs, cli_request *req); 52 | 53 | void cli_nat_test(router_state *rs, cli_request *req); 54 | 55 | #endif /* OR_CLI_H_ */ 56 | 57 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/or_dijkstra.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) David Erickson, Filip Paun 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | #ifndef OR_DIJKSTRA_H_ 35 | #define OR_DIJKSTRA_H_ 36 | 37 | #include "or_data_types.h" 38 | 39 | node* compute_rtable(uint32_t our_router_id, node* pwospf_router_list, node* if_list); 40 | pwospf_router* get_router_by_rid(uint32_t rid, node* pwospf_router_list); 41 | void* dijkstra_thread(void* arg); 42 | void dijkstra_trigger(router_state* rs); 43 | 44 | #endif /*OR_DIJKSTRA_H_*/ 45 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/or_icmp.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) David Erickson, Filip Paun 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | 35 | #ifndef OR_ICMP_H_ 36 | #define OR_ICMP_H_ 37 | 38 | #include "or_data_types.h" 39 | #include "sr_base_internal.h" 40 | 41 | void process_icmp_packet(struct sr_instance* sr, const uint8_t * packet, unsigned int len, const char* interface); 42 | 43 | int send_icmp_packet(struct sr_instance* sr, const uint8_t* src_packet, unsigned int len, uint8_t icmp_type, uint8_t icmp_code); 44 | uint16_t compute_icmp_checksum(icmp_hdr* icmp, int payload_len); 45 | icmp_hdr* get_icmp_hdr(const uint8_t* packet, unsigned int len); 46 | 47 | int send_icmp_echo_request_packet(struct sr_instance* sr, struct in_addr dest, unsigned short id); 48 | int process_icmp_echo_reply_packet(struct sr_instance* sr, const uint8_t* packet, unsigned int len); 49 | 50 | #endif /*OR_ICMP_H_*/ 51 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/or_ip.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) David Erickson, Filip Paun 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | 35 | #ifndef OR_IP_H_ 36 | #define OR_IP_H_ 37 | 38 | #include "or_data_types.h" 39 | #include "sr_base_internal.h" 40 | 41 | void process_ip_packet(struct sr_instance* sr, const uint8_t * packet, unsigned int len, const char* interface); 42 | uint32_t send_ip_packet(struct sr_instance* sr, uint8_t proto, uint32_t src, uint32_t dest, uint8_t *payload, int len); 43 | 44 | 45 | int is_packet_valid(const uint8_t * packet, unsigned int len); 46 | ip_hdr* get_ip_hdr(const uint8_t* packet, unsigned int len); 47 | uint16_t compute_ip_checksum(ip_hdr* iphdr); 48 | int verify_checksum(uint8_t *data, unsigned int len); 49 | 50 | void cli_show_ip_help(router_state *rs, cli_request *req); 51 | void cli_ip_help(router_state *rs, cli_request *req); 52 | 53 | #endif /*OR_IP_H_*/ 54 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/or_main.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) David Erickson, Filip Paun 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | #ifndef OR_MAIN_H_ 35 | #define OR_MAIN_H_ 36 | 37 | #include "sr_base_internal.h" 38 | #include "or_data_types.h" 39 | 40 | /* Default setting for ARP */ 41 | #define INITIAL_ARP_TIMEOUT 300 42 | 43 | void init(struct sr_instance* sr); 44 | void init_add_interface(struct sr_instance* sr, struct sr_vns_if* vns_if); 45 | iface_entry* get_interface(struct sr_instance* sr, const char* name); 46 | void init_router_list(struct sr_instance* sr); 47 | void init_rtable(struct sr_instance* sr); 48 | void init_cli(struct sr_instance* sr); 49 | void init_hardware(router_state* rs); 50 | void init_rawsockets(router_state* rs); 51 | void init_libnet(router_state* rs); 52 | void init_pcap(router_state* rs); 53 | void process_packet(struct sr_instance* sr, const uint8_t * packet, unsigned int len, const char* interface); 54 | 55 | int send_ip(struct sr_instance* sr, uint8_t* packet, unsigned int len, struct in_addr* next_hop, const char* out_iface); 56 | int send_packet(struct sr_instance* sr, uint8_t* packet, unsigned int len, const char* iface); 57 | 58 | uint32_t find_srcip(uint32_t dest); 59 | uint32_t integ_ip_output(uint8_t *payload, uint8_t proto, uint32_t src, uint32_t dst, int len); 60 | 61 | void destroy(struct sr_instance* sr); 62 | router_state* get_router_state(struct sr_instance* sr); 63 | 64 | #endif /*OR_MAIN_H_*/ 65 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/or_rtable.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) David Erickson, Filip Paun 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | #ifndef OR_RTABLE_H_ 35 | #define OR_RTABLE_H_ 36 | 37 | #include "or_data_types.h" 38 | #include "sr_base_internal.h" 39 | 40 | int get_next_hop(struct in_addr* next_hop, char* next_hop_iface, int len, router_state* rs, struct in_addr* destination); 41 | int add_route(router_state* rs, struct in_addr* dest, struct in_addr* gateway, struct in_addr* mask, char* interface); 42 | int del_route(router_state* rs, struct in_addr* dest, struct in_addr* mask); 43 | 44 | int deactivate_routes(router_state* rs, char* interface); 45 | int activate_routes(router_state* rs, char* interface); 46 | 47 | void trigger_rtable_modified(router_state* rs); 48 | void write_rtable_to_hw(router_state* rs); 49 | 50 | void lock_rtable_rd(router_state *rs); 51 | void lock_rtable_wr(router_state *rs); 52 | void unlock_rtable(router_state *rs); 53 | 54 | void cli_show_ip_rtable(router_state *rs, cli_request *req); 55 | void cli_show_ip_rtable_help(router_state *rs, cli_request *req); 56 | 57 | void cli_ip_route_add(router_state *rs, cli_request *req); 58 | void cli_ip_route_del(router_state *rs, cli_request *req); 59 | 60 | void cli_ip_route_help(router_state *rs, cli_request *req); 61 | void cli_ip_route_add_help(router_state *rs, cli_request *req); 62 | void cli_ip_route_del_help(router_state *rs, cli_request *req); 63 | 64 | void cli_show_hw_rtable(router_state *rs, cli_request *req); 65 | 66 | #endif /*OR_RTABLE_H_*/ 67 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/or_sping.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) David Erickson, Filip Paun 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | #ifndef OR_SPING_H_ 35 | #define OR_SPING_H_ 36 | 37 | #include "or_data_types.h" 38 | 39 | void cli_sping(router_state *rs, cli_request *req); 40 | int wait_for_reply(router_state *rs, unsigned short id); 41 | void cli_sping_help(router_state *rs, cli_request *req); 42 | 43 | void sping_queue_cleanup_thread_np(void *arg); 44 | void* sping_queue_cleanup_thread(void *arg); 45 | 46 | void lock_mutex_sping_queue(router_state* rs); 47 | void unlock_mutex_sping_queue(router_state* rs); 48 | 49 | #endif /* OR_SPING_H_ */ 50 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/or_vns.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) David Erickson, Filip Paun 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | #ifndef OR_VNS_H_ 35 | #define OR_VNS_H_ 36 | 37 | #include "or_data_types.h" 38 | 39 | void cli_show_vns(router_state *rs, cli_request *req); 40 | void cli_show_vns_help(router_state *rs, cli_request *req); 41 | 42 | void cli_show_vns_user(router_state *rs, cli_request *req); 43 | void cli_show_vns_user_help(router_state *rs, cli_request *req); 44 | 45 | void cli_show_vns_server(router_state *rs, cli_request *req); 46 | void cli_show_vns_server_help(router_state *rs, cli_request *req); 47 | 48 | void cli_show_vns_vhost(router_state *rs, cli_request *req); 49 | void cli_show_vns_vhost_help(router_state *rs, cli_request *req); 50 | 51 | void cli_show_vns_lhost(router_state *rs, cli_request *req); 52 | void cli_show_vns_lhost_help(router_state *rs, cli_request *req); 53 | 54 | void cli_show_vns_topology(router_state *rs, cli_request *req); 55 | void cli_show_vns_topology_help(router_state *rs, cli_request *req); 56 | 57 | #endif /*OR_VNS_H_*/ 58 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/or_www.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) David Erickson, Filip Paun 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | #ifndef OR_WWW_H_ 35 | #define OR_WWW_H_ 36 | 37 | void www_main(void* subsystem); 38 | void www_client_thread_np(void* arg); 39 | void* www_client_thread(void *arg); 40 | 41 | 42 | #endif /*OR_WWW_H_*/ 43 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/projects/reference_router/sw/scone/rtables/rtable -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable.netfpga: -------------------------------------------------------------------------------- 1 | 192.168.2.0 192.168.1.54 255.255.255.0 eth0 2 | 192.168.1.0 192.168.3.12 255.255.255.0 eth1 3 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable.regress1: -------------------------------------------------------------------------------- 1 | 192.168.1.1 192.168.1.1 255.255.255.0 eth1 2 | 0.0.0.0 192.168.0.1 0.0.0.0 eth0 3 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable.vhost1: -------------------------------------------------------------------------------- 1 | 192.168.130.14 192.168.130.9 255.255.255.254 eth1 2 | 192.168.130.10 192.168.130.9 255.255.255.254 eth1 3 | 192.168.130.8 0.0.0.0 255.255.255.254 eth1 4 | 192.168.130.6 0.0.0.0 255.255.255.254 eth2 5 | 192.168.130.12 192.168.130.7 255.255.255.254 eth2 6 | 0.0.0.0 172.24.74.17 0.0.0.0 eth0 7 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable.vhost1.pwospf: -------------------------------------------------------------------------------- 1 | 0.0.0.0 172.24.74.17 0.0.0.0 eth0 -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable.vhost2: -------------------------------------------------------------------------------- 1 | 192.168.130.6 192.168.130.11 255.255.255.254 eth2 2 | 192.168.130.12 192.168.130.11 255.255.255.254 eth2 3 | 192.168.130.10 0.0.0.0 255.255.255.254 eth2 4 | 192.168.130.14 0.0.0.0 255.255.255.254 eth1 5 | 192.168.130.8 0.0.0.0 255.255.255.254 eth0 6 | 0.0.0.0 192.168.130.8 0.0.0.0 eth0 7 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable.vhost2.pwospf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/projects/reference_router/sw/scone/rtables/rtable.vhost2.pwospf -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable.vhost3: -------------------------------------------------------------------------------- 1 | 192.168.130.14 192.168.130.10 255.255.255.254 eth2 2 | 192.168.130.8 192.168.130.10 255.255.255.254 eth2 3 | 192.168.130.10 0.0.0.0 255.255.255.254 eth2 4 | 192.168.130.12 0.0.0.0 255.255.255.254 eth1 5 | 192.168.130.6 0.0.0.0 255.255.255.254 eth0 6 | 0.0.0.0 192.168.130.6 0.0.0.0 eth0 7 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable.vhost3.pwospf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/projects/reference_router/sw/scone/rtables/rtable.vhost3.pwospf -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable2.vhost1.pwospf: -------------------------------------------------------------------------------- 1 | 0.0.0.0 172.24.74.17 0.0.0.0 eth0 -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable2.vhost2.pwospf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/projects/reference_router/sw/scone/rtables/rtable2.vhost2.pwospf -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/rtables/rtable2.vhost3.pwospf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/NetFPGA/NetFPGA-PLUS/70b333fa269cc6db9bbffc231386c10f4914d020/hw/projects/reference_router/sw/scone/rtables/rtable2.vhost3.pwospf -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/sr_base.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) Martin Casado 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | #ifndef SR_BASE_H 35 | #define SR_BASE_H 36 | 37 | void* sr_init_low_level_subystem(int argc, char **argv); 38 | 39 | #endif /* -- SR_BASE_H -- */ 40 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/sr_cpu_extension_nf.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) Martin Casado 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | 34 | #ifndef SR_CPU_EXTENSIONS_H 35 | #define SR_CPU_EXTENSIONS_H 36 | 37 | #include "sr_base_internal.h" 38 | 39 | static const uint16_t CPU_CONTROL_READ = 0x8804; 40 | static const uint16_t CPU_CONTROL_WRITE = 0x8805; 41 | #define CPU_CONTROL_ADDR "0:20:ce:10:03" 42 | 43 | int sr_cpu_init_hardware(struct sr_instance*, const char* hwfile); 44 | 45 | int sr_cpu_input(struct sr_instance* sr); 46 | int sr_cpu_output(struct sr_instance* sr /* borrowed */, 47 | uint8_t* buf /* borrowed */ , 48 | unsigned int len, 49 | const char* iface /* borrowed */); 50 | 51 | #endif /* -- SR_CPU_EXTENSIONS_H -- */ 52 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/sr_lwtcp_glue.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * All rights reserved. 6 | * 7 | * This software was developed by 8 | * Stanford University and the University of Cambridge Computer Laboratory 9 | * under National Science Foundation under Grant No. CNS-0855268, 10 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 11 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 12 | * as part of the DARPA MRC research programme. 13 | * 14 | * @NETFPGA_LICENSE_HEADER_START@ 15 | * 16 | * Licensed under the Apache License, Version 2.0 (the "License"); 17 | * you may not use this file except in compliance with the License. 18 | * You may obtain a copy of the License at 19 | * 20 | * http://www.apache.org/licenses/LICENSE-2.0 21 | * 22 | * Unless required by applicable law or agreed to in writing, software 23 | * distributed under the License is distributed on an "AS IS" BASIS, 24 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | * See the License for the specific language governing permissions and 26 | * limitations under the License. 27 | * 28 | * @NETFPGA_LICENSE_HEADER_END@ 29 | * 30 | * 31 | ******************************************************************************/ 32 | 33 | #ifndef SR_LWTCP_GLUE_H_ 34 | #define SR_LWTCP_GLUE_H_ 35 | 36 | #include "sr_base_internal.h" 37 | 38 | void sr_transport_input(uint8_t* packet /* borrowed */); 39 | 40 | #endif /*SR_LWTCP_GLUE_H_*/ 41 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/sr_vns.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 4 | * Junior University 5 | * Copyright (C) Martin Casado 6 | * All rights reserved. 7 | * 8 | * This software was developed by 9 | * Stanford University and the University of Cambridge Computer Laboratory 10 | * under National Science Foundation under Grant No. CNS-0855268, 11 | * the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and 12 | * by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"), 13 | * as part of the DARPA MRC research programme. 14 | * 15 | * @NETFPGA_LICENSE_HEADER_START@ 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the "License"); 18 | * you may not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * http://www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an "AS IS" BASIS, 25 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | * 29 | * @NETFPGA_LICENSE_HEADER_END@ 30 | * 31 | * 32 | ******************************************************************************/ 33 | /* 34 | * Description: 35 | * 36 | * Header file for interface to VNS. Able to connect, reserve host, 37 | * receive/parse hardware information, receive/send packets from/to VNS. 38 | * 39 | * See method definitions in sr_vns.c for detailed comments. 40 | * 41 | *---------------------------------------------------------------------------*/ 42 | 43 | #ifndef SR_VNS_H 44 | #define SR_VNS_H 45 | 46 | #ifdef _LINUX_ 47 | #include 48 | #endif /* _LINUX_ */ 49 | 50 | #ifdef _DARWIN_ 51 | #include 52 | #endif /* _DARWIN_ */ 53 | 54 | #ifdef _SOLARIS_ 55 | #include 56 | #endif /* _SOLARIS_ */ 57 | 58 | struct sr_instance* sr; /* -- forward declare -- */ 59 | 60 | int sr_vns_read_from_server(struct sr_instance* ); 61 | 62 | int sr_vns_connected_to_server(struct sr_instance* ); 63 | 64 | void sr_vns_init_log(struct sr_instance* sr, char* logfile); 65 | 66 | int sr_vns_connect_to_server(struct sr_instance* ,unsigned short , char* ); 67 | 68 | int sr_vns_send_packet(struct sr_instance* ,uint8_t* , unsigned int , const char*); 69 | 70 | 71 | #endif /* -- SR_VNS_H -- */ 72 | -------------------------------------------------------------------------------- /hw/projects/reference_router/sw/scone/www/content.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 

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