├── .appveyor.yml ├── .circleci └── config.yml ├── .dockerignore ├── .github └── workflows │ └── build_and_release.yml ├── .gitignore ├── .gitmodules ├── CMakeLists.txt ├── Dockerfile ├── LICENSE ├── MANIFEST.in ├── README.md ├── doc ├── dev_minitutorial.md ├── hdlConvertor_overview.png ├── requirements.txt └── windows_installation_and_build.rst ├── grammars ├── .gitignore ├── java │ └── sv2017Lexer.g4 ├── sv2017Lexer.g4 ├── sv2017Parser.g4 ├── verilogPreprocLexer.g4 ├── verilogPreprocParser.g4 ├── vhdlLexer.g4 └── vhdlParser.g4 ├── hdlConvertor ├── CMakeLists.txt ├── __init__.py ├── _hdlConvertor.pyx ├── python_ver_independent_str.pyx ├── toPy.cpp ├── toPy.h ├── toPy_expr.cpp ├── toPy_statements.cpp ├── toPy_type.cpp └── verilogPreproc.pyx ├── include └── hdlConvertor │ ├── baseHdlParser │ └── baseHdlParser.h │ ├── conversion_exception.h │ ├── createObject.h │ ├── encodingConversions.h │ ├── hdlAst │ ├── bigInteger.h │ ├── codePosition.h │ ├── hdlCompInst.h │ ├── hdlContext.h │ ├── hdlDirection.h │ ├── hdlFunctionDef.h │ ├── hdlIdDef.h │ ├── hdlLibrary.h │ ├── hdlModuleDec.h │ ├── hdlModuleDef.h │ ├── hdlNamespace.h │ ├── hdlOp.h │ ├── hdlOpType.h │ ├── hdlStmAssign.h │ ├── hdlStmBlock.h │ ├── hdlStmCase.h │ ├── hdlStmExpr.h │ ├── hdlStmFor.h │ ├── hdlStmIf.h │ ├── hdlStmProcess.h │ ├── hdlStmWhile.h │ ├── hdlStm_others.h │ ├── hdlTypes.h │ ├── hdlValue.h │ ├── iHdlExpr.h │ ├── iHdlExprItem.h │ ├── iHdlObj.h │ ├── iHdlStatement.h │ └── named.h │ ├── hdlConvertor.h │ ├── language.h │ ├── notImplementedLogger.h │ ├── parserContainer.h │ ├── svConvertor │ ├── attributeParser.h │ ├── baseSvParser.h │ ├── commentParser.h │ ├── declrParser.h │ ├── delayParser.h │ ├── eventExprParser.h │ ├── exprParser.h │ ├── exprPrimaryParser.h │ ├── gateParser.h │ ├── generateParser.h │ ├── literalParser.h │ ├── moduleInstanceParser.h │ ├── moduleParser.h │ ├── paramDefParser.h │ ├── portParser.h │ ├── programParser.h │ ├── source_textParser.h │ ├── statementParser.h │ ├── typeParser.h │ └── utils.h │ ├── syntaxErrorLogger.h │ ├── toString.h │ ├── universal_fs.h │ ├── verilogPreproc │ ├── a_macro_def.h │ ├── default_macro_defs.h │ ├── file_line_map.h │ ├── macroDB.h │ ├── macro_def_verilog.h │ ├── out_buffer.h │ ├── str_utils.h │ ├── verilogPreproc.h │ └── verilogPreprocContainer.h │ └── vhdlConvertor │ ├── archParser.h │ ├── baseVhdlParser.h │ ├── blockDeclarationParser.h │ ├── blockParser.h │ ├── commentParser.h │ ├── compInstanceParser.h │ ├── constantParser.h │ ├── designFileParser.h │ ├── directionParser.h │ ├── entityParser.h │ ├── exprParser.h │ ├── generateStatementParser.h │ ├── interfaceParser.h │ ├── literalParser.h │ ├── operatorTypeParser.h │ ├── packageHeaderParser.h │ ├── packageParser.h │ ├── processParser.h │ ├── referenceParser.h │ ├── signalParser.h │ ├── statementParser.h │ ├── subProgramDeclarationParser.h │ ├── subProgramParser.h │ ├── typeDeclarationParser.h │ └── variableParser.h ├── notebooks ├── .gitignore └── 01_parse_and_dump.ipynb ├── pyproject.toml ├── requirements.txt ├── setup.cfg ├── setup.py ├── src ├── CMakeLists.txt ├── CMake_antlr4.txt ├── CMake_coverage.txt ├── baseHdlParser │ └── baseHdlParser.cpp ├── conversion_exception.cpp ├── encodingConversions.cpp ├── hdlAst │ ├── bigInteger.cpp │ ├── codePosition.cpp │ ├── hdlCompInst.cpp │ ├── hdlContext.cpp │ ├── hdlFunctionDef.cpp │ ├── hdlIdDef.cpp │ ├── hdlLibrary.cpp │ ├── hdlModuleDec.cpp │ ├── hdlModuleDef.cpp │ ├── hdlNamespace.cpp │ ├── hdlOp.cpp │ ├── hdlOpType.cpp │ ├── hdlStmAssign.cpp │ ├── hdlStmBlock.cpp │ ├── hdlStmCase.cpp │ ├── hdlStmExpr.cpp │ ├── hdlStmFor.cpp │ ├── hdlStmIf.cpp │ ├── hdlStmProcess.cpp │ ├── hdlStmWhile.cpp │ ├── hdlStm_others.cpp │ ├── hdlTypes.cpp │ ├── hdlValue.cpp │ ├── iHdlExpr.cpp │ ├── iHdlStatement.cpp │ └── named.cpp ├── hdlConvertor.cpp ├── notImplementedLogger.cpp ├── svConvertor │ ├── CMakeLists.txt │ ├── attributeParser.cpp │ ├── baseSvParser.cpp │ ├── commentParser.cpp │ ├── declrParser.cpp │ ├── delayParser.cpp │ ├── eventExprParser.cpp │ ├── exprParser.cpp │ ├── exprPrimaryParser.cpp │ ├── gateParser.cpp │ ├── generateParser.cpp │ ├── literalParser.cpp │ ├── moduleInstanceParser.cpp │ ├── moduleParser.cpp │ ├── paramDefParser.cpp │ ├── portParser.cpp │ ├── programParser.cpp │ ├── source_textParser.cpp │ ├── statementParser.cpp │ ├── typeParser.cpp │ └── utils.cpp ├── syntaxErrorLogger.cpp ├── toString.cpp ├── universal_fs.cpp ├── verilogPreproc │ ├── CMakeLists.txt │ ├── a_macro_def.cpp │ ├── default_macro_defs.cpp │ ├── file_line_map.cpp │ ├── macro_def_verilog.cpp │ ├── out_buffer.cpp │ ├── str_utils.cpp │ ├── verilogPreproc.cpp │ └── verilogPreprocContainer.cpp └── vhdlConvertor │ ├── CMakeLists.txt │ ├── archParser.cpp │ ├── baseVhdlParser.cpp │ ├── blockDeclarationParser.cpp │ ├── blockParser.cpp │ ├── commentParser.cpp │ ├── compInstanceParser.cpp │ ├── constantParser.cpp │ ├── designFileParser.cpp │ ├── directionParser.cpp │ ├── entityParser.cpp │ ├── exprParser.cpp │ ├── generateStatementParser.cpp │ ├── interfaceParser.cpp │ ├── literalParser.cpp │ ├── operatorTypeParser.cpp │ ├── packageHeaderParser.cpp │ ├── packageParser.cpp │ ├── processParser.cpp │ ├── referenceParser.cpp │ ├── signalParser.cpp │ ├── statementParser.cpp │ ├── subProgramDeclarationParser.cpp │ ├── subProgramParser.cpp │ ├── typeDeclarationParser.cpp │ └── variableParser.cpp └── tests ├── __init__.py ├── all.py ├── basic_hdl_sim_model └── expected │ └── simple_subunit.py.txt ├── docker ├── python2hdlconvertor │ └── Dockerfile └── readme.md ├── extern_test_utils.py ├── file_utils.py ├── hdl_parse_tc.py ├── hwt └── expected │ ├── decoder_using_case.py.txt │ └── uart.py.txt ├── notebook_exec.py ├── sv_pp ├── expected │ ├── 2012_p641.txt │ ├── 2012_p642.txt │ ├── 2012_p642_2.txt │ ├── 2012_p643.txt │ ├── 2012_p643_2.txt │ ├── 2012_p643_3.txt │ ├── 2012_p644.txt │ ├── 2012_p644_2.txt │ ├── debug_macro.txt │ ├── def_in_def.txt │ ├── defined_defargs.txt │ ├── include_many_dir │ │ ├── dir0-a │ │ │ ├── dir1-a │ │ │ │ └── spec_incdir.txt │ │ │ └── local_include_higher_priority.txt │ │ ├── from_subdirectory.txt │ │ └── transitive.txt │ ├── include_same_dir │ │ ├── basic_include.txt │ │ └── basic_include2times.txt │ ├── macro_args.txt │ ├── preproc_hash_table.txt │ ├── protect.v │ ├── stringify.txt │ └── stringify_multiline.txt ├── raw │ ├── test_celldefine.txt │ ├── test_comments.txt │ ├── test_default_nettype.txt │ ├── test_define1.txt │ ├── test_define10.txt │ ├── test_define11.txt │ ├── test_define12.txt │ ├── test_define13.txt │ ├── test_define2.txt │ ├── test_define3.txt │ ├── test_define4.txt │ ├── test_define5.txt │ ├── test_define6.txt │ ├── test_define7.txt │ ├── test_define8.txt │ ├── test_define9.txt │ ├── test_ifdef.txt │ ├── test_ifdef1.txt │ ├── test_ifdef2.txt │ ├── test_ifdef3.txt │ ├── test_ifndef1.txt │ ├── test_include.txt │ ├── test_keywords1.txt │ ├── test_keywords2.txt │ ├── test_line_directive.txt │ ├── test_pragma1.txt │ ├── test_pragma2.txt │ ├── test_real1.txt │ ├── test_real2.txt │ ├── test_space_between_comments.txt │ ├── test_timingspec.txt │ ├── test_token1.txt │ ├── test_token2.txt │ ├── test_token3.txt │ ├── test_token4.txt │ ├── test_token5.txt │ ├── test_token6.txt │ ├── test_token7.txt │ ├── test_token8.txt │ ├── test_unconnected_drive.txt │ └── test_undef.txt └── src │ ├── 2012_p641.txt │ ├── 2012_p641_il1.txt │ ├── 2012_p641_il2.txt │ ├── 2012_p641_il3.txt │ ├── 2012_p642.txt │ ├── 2012_p642_2.txt │ ├── 2012_p642_il1.txt │ ├── 2012_p642_il2.txt │ ├── 2012_p642_il3.txt │ ├── 2012_p643.txt │ ├── 2012_p643_2.txt │ ├── 2012_p643_3.txt │ ├── 2012_p644.txt │ ├── 2012_p644_2.txt │ ├── debug_macro.txt │ ├── debug_macro.vh │ ├── def_in_def.txt │ ├── defined_defargs.txt │ ├── empty.txt │ ├── include_many_dir │ ├── dir0-a │ │ ├── dir1-a │ │ │ ├── file2-a.txt │ │ │ ├── spec_incdir.txt │ │ │ └── transitive-1.txt │ │ ├── file.txt │ │ ├── local_include_higher_priority.txt │ │ ├── transitive-0.txt │ │ ├── transitive-2.txt │ │ └── transitive-3.txt │ ├── file.txt │ ├── from_subdirectory.txt │ └── transitive.txt │ ├── include_same_dir │ ├── a.vh │ ├── basic_include.txt │ └── basic_include2times.txt │ ├── indirect_ifdef.err.txt │ ├── macro_args.txt │ ├── preproc_hash_table.txt │ ├── protect.v │ ├── stringify.txt │ ├── stringify_multiline.txt │ └── test_FILE_LINE.sv ├── sv_test ├── others │ ├── crc_functions.sv │ ├── expected │ │ ├── crc_functions.sv │ │ ├── hierarchical_name_of_type.sv │ │ ├── operator_type.sv │ │ └── stm_import.sv │ ├── hierarchical_name_of_type.sv │ ├── mem_base_object.sv │ ├── operator_type.sv │ └── stm_import.sv ├── std2012 │ ├── p102.sv │ ├── p12.sv │ ├── p134.sv │ ├── p138.sv │ ├── p139.sv │ ├── p140.sv │ ├── p141.sv │ ├── p142.sv │ ├── p147.sv │ ├── p148.sv │ ├── p154_1.sv │ ├── p154_2.sv │ ├── p158.sv │ ├── p160_1.sv │ ├── p160_2.sv │ ├── p49.sv │ ├── p57.sv │ ├── p58.sv │ ├── p59.sv │ ├── p753_1.sv │ ├── p753_2.sv │ ├── p76.sv │ ├── p77.sv │ ├── p84.sv │ ├── p87.sv │ ├── p88.sv │ ├── p90.sv │ ├── p91.sv │ └── p94.sv └── std2017 │ ├── p123.sv │ ├── p123_2.sv │ ├── p124.sv │ ├── p125.sv │ ├── p126.sv │ ├── p127.sv │ ├── p130.sv │ ├── p137.sv │ ├── p137_2.sv │ ├── p140.sv │ ├── p141.sv │ ├── p142.sv │ ├── p143.sv │ ├── p168.sv │ ├── p170.sv │ ├── p172.sv │ ├── p174.sv │ ├── p174_2.sv │ ├── p175.sv │ ├── p176.sv │ ├── p177.sv │ ├── p178.sv │ ├── p179.sv │ ├── p180.sv │ ├── p180_2.sv │ ├── p181.sv │ ├── p181_2.sv │ ├── p183.sv │ ├── p184.sv │ ├── p184_2.sv │ ├── p185.sv │ ├── p185_2.sv │ ├── p186.sv │ ├── p188.sv │ ├── p188_2.sv │ ├── p188_3.sv │ ├── p189.sv │ ├── p190.sv │ ├── p190_2.sv │ ├── p191.sv │ ├── p193.sv │ ├── p193_2.sv │ ├── p194.sv │ ├── p196.sv │ ├── p196_2.sv │ ├── p197.sv │ ├── p198.sv │ ├── p199.sv │ ├── p200.sv │ ├── p200_2.sv │ ├── p201.sv │ ├── p202.sv │ ├── p203.sv │ ├── p220.sv │ ├── p221.sv │ ├── p229.sv │ ├── p229_2.sv │ ├── p230.sv │ ├── p234.sv │ ├── p238.sv │ ├── p239.sv │ ├── p240.sv │ ├── p242.sv │ ├── p243.sv │ ├── p248.sv │ ├── p249.sv │ ├── p252.sv │ ├── p253.sv │ ├── p269.sv │ ├── p278.sv │ ├── p284.sv │ ├── p288.sv │ ├── p289.sv │ ├── p292.sv │ ├── p294.sv │ ├── p295.sv │ ├── p296.sv │ ├── p297.sv │ ├── p322.sv │ ├── p327.sv │ ├── p328.sv │ ├── p330.sv │ ├── p331.sv │ ├── p332.sv │ ├── p333.sv │ ├── p334.sv │ ├── p335.sv │ ├── p338.sv │ ├── p339.sv │ ├── p340.sv │ ├── p341.sv │ ├── p342.sv │ ├── p346.sv │ ├── p347.sv │ ├── p348.sv │ ├── p352.sv │ ├── p371.sv │ ├── p372.sv │ ├── p454.sv │ ├── p469.sv │ ├── p475.sv │ ├── p477.sv │ ├── p478.sv │ ├── p482.sv │ ├── p488.sv │ ├── p489.sv │ ├── p490.sv │ ├── p491.sv │ ├── p492.sv │ ├── p493.sv │ ├── p493_2.sv │ ├── p494.sv │ ├── p494_2.sv │ ├── p495.sv │ ├── p496.sv │ ├── p499.sv │ ├── p501.sv │ ├── p501_2.sv │ ├── p502.sv │ ├── p503.sv │ ├── p504.sv │ ├── p504_2.sv │ ├── p506.sv │ ├── p507.sv │ ├── p508.sv │ ├── p510.sv │ ├── p511.sv │ ├── p516.sv │ ├── p517.sv │ ├── p517_2.sv │ ├── p518.sv │ ├── p519.sv │ ├── p521.sv │ ├── p522.sv │ ├── p524.sv │ ├── p525.sv │ ├── p526.sv │ ├── p527.sv │ ├── p530.sv │ ├── p531.sv │ ├── p532.sv │ ├── p535.sv │ ├── p537.sv │ ├── p541.sv │ ├── p550.sv │ ├── p552.sv │ ├── p556.sv │ ├── p557.sv │ ├── p558.sv │ ├── p560.sv │ ├── p565.sv │ ├── p566.sv │ ├── p568.sv │ ├── p573.sv │ ├── p576.sv │ ├── p577.sv │ ├── p578.sv │ ├── p580.sv │ ├── p581.sv │ ├── p584.sv │ ├── p594.sv │ ├── p597.sv │ ├── p599.sv │ ├── p600.sv │ ├── p608.sv │ ├── p612.sv │ ├── p621.sv │ ├── p622.sv │ ├── p623.sv │ ├── p627.sv │ ├── p628.sv │ ├── p629.sv │ ├── p633.sv │ ├── p700.sv │ ├── p701.sv │ ├── p702.sv │ ├── p703.sv │ ├── p704.sv │ ├── p705.sv │ ├── p706.sv │ ├── p707.sv │ ├── p710.sv │ ├── p711.sv │ ├── p713.sv │ ├── p714.sv │ ├── p716.sv │ ├── p718.sv │ ├── p719.sv │ ├── p720.sv │ ├── p721.sv │ ├── p723.sv │ ├── p724.sv │ ├── p726.sv │ ├── p728.sv │ ├── p729.sv │ ├── p730.sv │ ├── p731.sv │ ├── p732.sv │ ├── p733.sv │ ├── p734.sv │ ├── p735.sv │ ├── p736.sv │ ├── p737.sv │ ├── p738.sv │ ├── p745.sv │ ├── p751.sv │ ├── p752.sv │ ├── p753.sv │ ├── p754.sv │ ├── p755.sv │ ├── p756.sv │ ├── p757.sv │ ├── p758.sv │ ├── p759.sv │ ├── p760.sv │ ├── p761.sv │ ├── p762.sv │ ├── p764.sv │ ├── p765.sv │ ├── p766.sv │ ├── p770.sv │ ├── p771.sv │ ├── p772.sv │ ├── p773.sv │ ├── p774.sv │ ├── p776.sv │ ├── p777.sv │ ├── p779.sv │ ├── p780.sv │ ├── p781.sv │ ├── p782.sv │ ├── p783.sv │ ├── p790.sv │ ├── p791.sv │ ├── p793.sv │ ├── p794.sv │ ├── p795.sv │ ├── p801.sv │ ├── p802.sv │ ├── p825.sv │ ├── p827.sv │ ├── p832.sv │ ├── p833.sv │ ├── p834.sv │ ├── p835.sv │ ├── p836.sv │ ├── p837.sv │ ├── p844.sv │ ├── p845.sv │ ├── p847.sv │ ├── p85.sv │ ├── p884.sv │ ├── p886.sv │ ├── p918.sv_unsupported │ ├── p919.sv_unsupported │ ├── p93.sv │ ├── p94.sv │ ├── p940.sv │ ├── p95.sv │ └── p95 │ ├── cmp.sv │ ├── cmp.svr │ ├── driver.sv │ ├── driver.svr │ ├── lib.map │ ├── nets.pkg │ └── top.sv ├── test_basic_hdl_sim_model_from_verilog.py ├── test_ghdl_testsuite.py ├── test_icarus_verilog_testsuite.py ├── test_notebook.py ├── test_sv2017_std_examples_parse.py ├── test_uvvm_testsuite.py ├── test_verilator_testsuite.py ├── test_verilog_conversion.py ├── test_verilog_preproc.py ├── test_verilog_preproc_grammar.py ├── test_verilog_preproc_include.py ├── test_verilog_preproc_macro_db_api.py ├── test_verilog_to_hwt.py ├── test_vhdl_conversion.py ├── test_vhdl_std_examples_parse.py ├── test_vunit_testsuite.py ├── test_yosys_testsuite.py ├── time_logging_test_runner.py ├── verilog ├── aFifo.v ├── adder_implicit.v ├── aes.v ├── arbiter.v ├── arbiter_tb.v ├── cam.v ├── decoder_using_case.v ├── define.v ├── dff_async_reset.v ├── directive_verilogpp.v ├── dlatch_reset.v ├── expected │ ├── aFifo.v │ ├── adder_implicit.v │ ├── aes.v │ ├── arbiter_tb.v │ ├── cam.v │ ├── decoder_using_case.v │ ├── define.v │ ├── dff_async_reset.v │ ├── directive_verilogpp.v │ ├── dlatch_reset.v │ ├── function_non_ansi.v │ ├── generate_for.v │ ├── lfsr_updown_tb.v │ ├── macro.v │ ├── parity_using_function2.v │ ├── pri_encoder_using_assign.v │ ├── pri_encoder_using_if.v │ ├── ram_sp_ar_sw.v │ ├── ram_sp_sr_sw.v │ ├── rom_using_file.v │ ├── test_verilog_primitives.v │ └── uart.v ├── fifo_rx.v ├── function_non_ansi.v ├── generate_for.v ├── include.v ├── lfsr_updown_tb.v ├── macro.v ├── parity_using_function2.v ├── pri_encoder_using_assign.v ├── pri_encoder_using_if.v ├── ram_sp_ar_sw.v ├── ram_sp_sr_sw.v ├── rom_using_file.v ├── simple_subunit.v ├── sram.v ├── test_verilog_primitives.v ├── timescale.v └── uart.v └── vhdl ├── FloPoCoLibRightShifter.vhd ├── arch_signal_declr_identifier_list.vhd ├── arch_with_assig.vhd ├── array.vhd ├── association_open.vhd ├── call.vhd ├── carry_lookahead.vhd ├── component1-Four_Bit_Adder.vhd ├── direct_instantiation.vhd ├── entity_declarative_item.vhd ├── enum.vhd ├── expected ├── FloPoCoLibRightShifter.vhd ├── arch_signal_declr_identifier_list.vhd ├── arch_with_assig.vhd ├── array.vhd ├── association_open.vhd ├── call.vhd ├── carry_lookahead.vhd ├── direct_instantiation.vhd ├── entity_declarative_item.vhd ├── enum.vhd ├── for_in.vhd ├── function_noarg.vhd ├── generate_for.vhd ├── generate_for_and_if.vhd ├── mux.vhd ├── operator_example.vhd ├── package_constants.vhd ├── package_enum.vhd ├── package_record.vhd ├── package_typedefs.vhd ├── ram.vhd ├── record_in_record.vhd ├── stm_exit.vhd ├── stm_nop.vhd ├── subtype.vhd ├── type_attribute_designator.vhd └── with_select.vhd ├── for_in.vhd ├── fourbit_adder.vhd ├── function0-f_ASCII_2_HEX.vhd ├── function_noarg.vhd ├── generate_for.vhd ├── generate_for_and_if.vhd ├── lfsr_pkg.vhd ├── malformed.vhd ├── mux.vhd ├── mux2i.vhd ├── operator_example.vhd ├── package_array_const.vhd ├── package_component.vhd ├── package_constants.vhd ├── package_enum.vhd ├── package_instance.vhd ├── package_record.vhd ├── package_typedefs.vhd ├── procedure0-example_procedure_simple.vhd ├── ram.vhd ├── record_in_record.vhd ├── standard.vhd ├── std2008 ├── arch.vhd ├── configuration.vhd ├── declarations.vhd ├── entity.vhd ├── package.vhd ├── subprograms.vhd ├── types.vhd └── units.vhd ├── stm_exit.vhd ├── stm_nop.vhd ├── subtype.vhd ├── type_attribute_designator.vhd └── with_select.vhd /.dockerignore: -------------------------------------------------------------------------------- 1 | _skbuild/ 2 | build/ 3 | 4 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "ivtest"] 2 | path = tests/ivtest 3 | url = https://github.com/steveicarus/ivtest 4 | branch = master 5 | [submodule "yosys"] 6 | path = tests/yosys 7 | url = https://github.com/YosysHQ/yosys.git 8 | branch = master 9 | [submodule "verilator"] 10 | path = tests/verilator 11 | url = https://github.com/verilator/verilator 12 | branch = master 13 | [submodule "vunit"] 14 | path = tests/vunit 15 | url = https://github.com/VUnit/vunit.git 16 | branch = master 17 | [submodule "ghdl"] 18 | path = tests/ghdl 19 | url = https://github.com/ghdl/ghdl.git 20 | [submodule "UVVM"] 21 | path = tests/UVVM 22 | url = https://github.com/UVVM/UVVM.git 23 | -------------------------------------------------------------------------------- /MANIFEST.in: -------------------------------------------------------------------------------- 1 | include *.txt *.md 2 | include MANIFEST.in 3 | include README.md 4 | include setup.py 5 | include setup.cfg 6 | include pyproject.toml 7 | include LICENSE 8 | 9 | recursive-include include *.h 10 | recursive-include src *.cpp *.h *.txt 11 | recursive-include grammars *.g4 12 | recursive-include hdlConvertor *.cpp *.h *.txt *.pyx *.py 13 | 14 | -------------------------------------------------------------------------------- /doc/hdlConvertor_overview.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertor/3f0e5a9218a4689c703161dc335357366fb4e98f/doc/hdlConvertor_overview.png -------------------------------------------------------------------------------- /doc/requirements.txt: -------------------------------------------------------------------------------- 1 | git+https://github.com/Nic30/hdlConvertorAst.git@master#egg=hdlConvertorAst -------------------------------------------------------------------------------- /grammars/.gitignore: -------------------------------------------------------------------------------- 1 | *.interp 2 | *.java 3 | *.tokens 4 | *.class 5 | -------------------------------------------------------------------------------- /hdlConvertor/__init__.py: -------------------------------------------------------------------------------- 1 | from ._hdlConvertor import HdlConvertorPy as HdlConvertor, ParseException -------------------------------------------------------------------------------- /hdlConvertor/python_ver_independent_str.pyx: -------------------------------------------------------------------------------- 1 | from cpython.version cimport PY_MAJOR_VERSION 2 | 3 | IS_PY3 = PY_MAJOR_VERSION == 3 4 | 5 | if IS_PY3: 6 | string_type = str 7 | 8 | def str_decode(s): 9 | return s.decode("utf-8") 10 | 11 | def str_encode(s): 12 | return s.encode("utf-8") 13 | 14 | else: 15 | string_type = basestring 16 | 17 | def str_decode(s): 18 | return s 19 | 20 | def str_encode(s): 21 | return s 22 | -------------------------------------------------------------------------------- /include/hdlConvertor/baseHdlParser/baseHdlParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #include 6 | 7 | namespace hdlConvertor { 8 | 9 | class BaseHdlParser { 10 | public: 11 | antlr4::TokenStream &tokens; 12 | hdlAst::HdlContext &context; 13 | bool hierarchyOnly; 14 | 15 | BaseHdlParser(antlr4::TokenStream &tokens, hdlAst::HdlContext &ctx, 16 | bool _hierarchyOnly); 17 | }; 18 | 19 | } 20 | -------------------------------------------------------------------------------- /include/hdlConvertor/conversion_exception.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | 6 | namespace hdlConvertor { 7 | 8 | class ParseException: public std::exception { 9 | private: 10 | std::string _msg; 11 | 12 | public: 13 | ParseException(std::string msg) throw (); 14 | virtual const char* what() const throw (); 15 | }; 16 | 17 | } 18 | -------------------------------------------------------------------------------- /include/hdlConvertor/encodingConversions.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | namespace hdlConvertor { 6 | 7 | std::string iso_8859_1_to_utf8(const std::string &str); 8 | std::string _to_utf8(const std::string &str, const std::string &encoding); 9 | antlr4::ANTLRInputStream ANTLRFileStream_with_encoding( 10 | const std::filesystem::path &file_name, const std::string &encoding); 11 | 12 | } 13 | -------------------------------------------------------------------------------- /include/hdlConvertor/hdlAst/hdlContext.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | namespace hdlConvertor { 8 | namespace hdlAst { 9 | 10 | /* 11 | * Container of any HDL objects 12 | * */ 13 | class HdlContext { 14 | public: 15 | std::vector> objs; 16 | 17 | ~HdlContext(); 18 | }; 19 | 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /include/hdlConvertor/hdlAst/hdlDirection.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | enum HdlDirection { 7 | DIR_IN, 8 | DIR_OUT, 9 | DIR_INOUT, 10 | DIR_BUFFER, 11 | DIR_LINKAGE, 12 | DIR_INTERNAL, 13 | DIR_UNKNOWN, 14 | }; 15 | 16 | inline const char* HdlDirection_toString(HdlDirection d) { 17 | switch (d) { 18 | case DIR_IN: 19 | return "IN"; 20 | case DIR_OUT: 21 | return "OUT"; 22 | case DIR_INOUT: 23 | return "INOUT"; 24 | case DIR_BUFFER: 25 | return "BUFFER"; 26 | case DIR_LINKAGE: 27 | return "LINKAGE"; 28 | case DIR_INTERNAL: 29 | return "INTERNAL"; 30 | default: 31 | throw std::runtime_error("Invalid direction value"); 32 | } 33 | } 34 | 35 | } 36 | } 37 | -------------------------------------------------------------------------------- /include/hdlConvertor/hdlAst/hdlLibrary.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | namespace hdlConvertor { 9 | namespace hdlAst { 10 | 11 | /* 12 | * HDL library reference 13 | * */ 14 | class HdlLibrary : public WithNameAndDoc, public iHdlObj { 15 | public: 16 | HdlLibrary(const std::string& name); 17 | ~HdlLibrary(); 18 | }; 19 | 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /include/hdlConvertor/hdlAst/hdlModuleDef.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | 6 | 7 | namespace hdlConvertor { 8 | namespace hdlAst { 9 | 10 | /* 11 | * HDL AST node for module definition (the body of the module in Verilog, Architecture in VHDL) 12 | * */ 13 | class HdlModuleDef: public WithNameAndDoc, public iHdlObj { 14 | public: 15 | std::unique_ptr module_name; 16 | std::unique_ptr dec; 17 | 18 | std::vector> objs; 19 | 20 | ~HdlModuleDef(); 21 | }; 22 | 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /include/hdlConvertor/hdlAst/hdlNamespace.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | namespace hdlConvertor { 9 | namespace hdlAst { 10 | 11 | /* 12 | * HDL AST node for namespace (namespace in System Verilog, package/package body in VHDL) 13 | * */ 14 | class HdlValueIdspace: public WithNameAndDoc, public iHdlObj { 15 | public: 16 | bool defs_only; // true for VHDL package, false for VHDL package body 17 | std::vector> objs; 18 | 19 | HdlValueIdspace(); 20 | virtual ~HdlValueIdspace() override; 21 | }; 22 | 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /include/hdlConvertor/hdlAst/hdlStmExpr.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | namespace hdlConvertor { 8 | namespace hdlAst { 9 | 10 | /* 11 | * HDL AST node for expression statement, wrapper around expression which adds label, code position etc. 12 | * */ 13 | class HdlStmExpr: public iHdlStatement { 14 | public: 15 | std::unique_ptr expr; 16 | HdlStmExpr(std::unique_ptr expr); 17 | }; 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /include/hdlConvertor/hdlAst/iHdlExpr.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | 9 | namespace hdlConvertor { 10 | namespace hdlAst { 11 | 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /include/hdlConvertor/hdlAst/iHdlObj.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | /* 7 | * Interface for object which can appear in HDL AST 8 | * */ 9 | class iHdlObj { 10 | public: 11 | virtual ~iHdlObj() { 12 | } 13 | }; 14 | 15 | 16 | } 17 | } 18 | -------------------------------------------------------------------------------- /include/hdlConvertor/language.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | namespace hdlConvertor { 4 | 5 | enum Language { 6 | VHDL = 0, 7 | VERILOG1995 = 1, 8 | VERILOG2001 = 2, 9 | VERILOG2001_NOCONFIG = 3, 10 | VERILOG2005 = 4, 11 | VERILOG = VERILOG2001, 12 | SV2005 = 5, 13 | SV2009 = 6, 14 | SV2012 = 7, 15 | SV2017 = 8, 16 | SYSTEM_VERILOG = SV2017, 17 | HWT = 9, 18 | // [note] the size of this enum is made larger than 1B in order to avoid warnings 19 | // in cython generated code 20 | INVALID = 1 << 31 21 | }; 22 | 23 | } 24 | -------------------------------------------------------------------------------- /include/hdlConvertor/notImplementedLogger.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #include 6 | 7 | namespace hdlConvertor { 8 | 9 | class NotImplementedLogger { 10 | public: 11 | static bool ENABLE; 12 | 13 | static void print(const char *msg, antlr4::ParserRuleContext *ctx); 14 | static void print(const std::string &msg, antlr4::ParserRuleContext *ctx); 15 | static void print(const std::string &msg, antlr4::tree::TerminalNode *ctx); 16 | 17 | }; 18 | 19 | } 20 | -------------------------------------------------------------------------------- /include/hdlConvertor/svConvertor/attributeParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #include 6 | #include 7 | 8 | namespace hdlConvertor { 9 | namespace sv { 10 | 11 | class VerAttributeParser { 12 | public: 13 | using sv2017Parser = sv2017_antlr::sv2017Parser; 14 | 15 | static void visitAttribute_instance( 16 | sv2017Parser::Attribute_instanceContext *ctx); 17 | static void visitAttribute_instance( 18 | std::vector ctx); 19 | }; 20 | 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /include/hdlConvertor/svConvertor/baseSvParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | namespace hdlConvertor { 9 | namespace sv { 10 | 11 | class BaseSvParser { 12 | public: 13 | SVCommentParser &commentParser; 14 | bool hierarchyOnly; 15 | using sv2017Parser = sv2017_antlr::sv2017Parser; 16 | BaseSvParser(SVCommentParser &commentParser, bool hierarchyOnly); 17 | BaseSvParser(BaseSvParser * other); 18 | }; 19 | 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /include/hdlConvertor/svConvertor/source_textParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #include 6 | 7 | namespace hdlConvertor { 8 | namespace sv { 9 | 10 | class Source_textParser: public BaseHdlParser { 11 | public: 12 | using sv2017Parser = sv2017_antlr::sv2017Parser; 13 | 14 | Source_textParser(antlr4::TokenStream &tokens, hdlAst::HdlContext &ctx, 15 | bool _hierarchyOnly); 16 | void visitSource_text(sv2017Parser::Source_textContext *ctx); 17 | void visitTimeunits_declaration( 18 | sv2017Parser::Timeunits_declarationContext *ctx); 19 | void visitDescription(sv2017Parser::DescriptionContext *ctx); 20 | }; 21 | 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /include/hdlConvertor/universal_fs.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include 3 | /* 4 | * path std namespace to have std::filesystem if required for older compilers 5 | * */ 6 | 7 | #if (defined(__GNUC__) && __GNUC__ < 8) 8 | #include 9 | namespace std { 10 | namespace filesystem = experimental::filesystem; 11 | } 12 | #else 13 | #include 14 | #endif 15 | 16 | // the filename which is used if the code comes from string and not from file 17 | extern const std::string STRING_FILENAME; 18 | -------------------------------------------------------------------------------- /include/hdlConvertor/verilogPreproc/file_line_map.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | 6 | namespace hdlConvertor { 7 | namespace verilog_pp { 8 | 9 | class FileLineMapItem { 10 | public: 11 | FileLineMapItem(size_t line, const std::string &file_override, 12 | size_t line_override); 13 | size_t line; 14 | std::string file_override; 15 | size_t line_override; 16 | }; 17 | 18 | // Container of information about offsets in code positions for error logging and code analysis 19 | using FileLineMap = std::vector; 20 | 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /include/hdlConvertor/verilogPreproc/macroDB.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | #include 8 | #include 9 | 10 | namespace hdlConvertor { 11 | namespace verilog_pp { 12 | 13 | /** 14 | * Container to store all the defined macro. 15 | */ 16 | typedef std::map MacroDB; 17 | 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /include/hdlConvertor/vhdlConvertor/archParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | 9 | namespace hdlConvertor { 10 | namespace vhdl { 11 | 12 | class VhdlArchParser : public BaseVhdlParser { 13 | public: 14 | using BaseVhdlParser::BaseVhdlParser; 15 | using vhdlParser = vhdl_antlr::vhdlParser; 16 | 17 | std::unique_ptr visitArchitecture_body( 18 | vhdlParser::Architecture_bodyContext *ctx); 19 | 20 | }; 21 | 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /include/hdlConvertor/vhdlConvertor/baseVhdlParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #include 6 | 7 | namespace hdlConvertor { 8 | namespace vhdl { 9 | 10 | class BaseVhdlParser { 11 | public: 12 | VhdlCommentParser &commentParser; 13 | bool hierarchyOnly; 14 | 15 | BaseVhdlParser(VhdlCommentParser &commentParser, bool _hierarchyOnly); 16 | BaseVhdlParser(BaseVhdlParser & parent); 17 | }; 18 | 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /include/hdlConvertor/vhdlConvertor/constantParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #include 6 | 7 | #include 8 | 9 | namespace hdlConvertor { 10 | namespace vhdl { 11 | 12 | class VhdlConstantParser { 13 | public: 14 | using vhdlParser = vhdl_antlr::vhdlParser; 15 | 16 | static std::unique_ptr>> visitConstant_declaration( 17 | vhdlParser::Constant_declarationContext *ctx); 18 | 19 | }; 20 | 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /include/hdlConvertor/vhdlConvertor/directionParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #include 6 | #include 7 | 8 | namespace hdlConvertor { 9 | namespace vhdl { 10 | 11 | hdlAst::HdlDirection visitSignalMode( 12 | vhdl_antlr::vhdlParser::Signal_modeContext *ctx); 13 | hdlAst::HdlOpType visitDirection( 14 | vhdl_antlr::vhdlParser::DirectionContext *ctx); 15 | 16 | } 17 | } 18 | -------------------------------------------------------------------------------- /include/hdlConvertor/vhdlConvertor/signalParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include 3 | 4 | #include 5 | 6 | #include 7 | 8 | namespace hdlConvertor { 9 | namespace vhdl { 10 | 11 | class VhdlSignalParser { 12 | public: 13 | using vhdlParser = vhdl_antlr::vhdlParser; 14 | 15 | static std::unique_ptr< 16 | std::vector>> visitSignal_declaration( 17 | vhdlParser::Signal_declarationContext *ctx); 18 | 19 | }; 20 | 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /include/hdlConvertor/vhdlConvertor/variableParser.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #include 6 | 7 | #include 8 | 9 | namespace hdlConvertor { 10 | namespace vhdl { 11 | 12 | class VhdlVariableParser { 13 | public: 14 | using vhdlParser = vhdl_antlr::vhdlParser; 15 | 16 | static std::unique_ptr< 17 | std::vector>> visitVariable_declaration( 18 | vhdlParser::Variable_declarationContext *ctx); 19 | 20 | }; 21 | 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /notebooks/.gitignore: -------------------------------------------------------------------------------- 1 | .ipynb_checkpoints/ 2 | *_all_output.ipynb 3 | -------------------------------------------------------------------------------- /pyproject.toml: -------------------------------------------------------------------------------- 1 | [build-system] 2 | requires = ["setuptools", "wheel", "scikit-build", "Cython", "cmake", "ninja"] 3 | build-backend = "setuptools.build_meta" 4 | -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | scikit-build 2 | Cython -------------------------------------------------------------------------------- /setup.cfg: -------------------------------------------------------------------------------- 1 | [metadata] 2 | description_file = README.md 3 | -------------------------------------------------------------------------------- /src/baseHdlParser/baseHdlParser.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | 5 | using namespace hdlConvertor::hdlAst; 6 | 7 | BaseHdlParser::BaseHdlParser(antlr4::TokenStream &_tokens, HdlContext &ctx, 8 | bool _hierarchyOnly) : 9 | tokens(_tokens), context(ctx), hierarchyOnly(_hierarchyOnly) { 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /src/conversion_exception.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | 5 | ParseException::ParseException(std::string msg) throw () : 6 | _msg(msg) { 7 | } 8 | 9 | const char* ParseException::what() const throw () { 10 | return _msg.c_str(); 11 | } 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/hdlAst/bigInteger.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | BigInteger::BigInteger(int64_t v) : 7 | val(v), bitstring(), bitstring_base(INVALID_BASE) { 8 | } 9 | 10 | BigInteger::BigInteger(const std::string & _bit_string, int base) : 11 | val(0), bitstring(_bit_string), bitstring_base(base) { 12 | } 13 | 14 | bool BigInteger::is_bitstring() const { 15 | return bitstring_base != BigInteger::INVALID_BASE; 16 | } 17 | 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /src/hdlAst/codePosition.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | CodePosition::CodePosition() : 7 | CodePosition(INVALID, INVALID, INVALID, INVALID) { 8 | } 9 | 10 | CodePosition::CodePosition(size_t startLine, size_t stopLine, size_t startColumn, 11 | size_t stopColumn) { 12 | this->start_line = startLine; 13 | this->stop_line = stopLine; 14 | this->start_column = startColumn; 15 | this->stop_column = stopColumn; 16 | } 17 | 18 | bool CodePosition::isKnown() const { 19 | return start_line != INVALID || stop_line != INVALID || start_column != INVALID 20 | || stop_column != INVALID; 21 | } 22 | 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /src/hdlAst/hdlCompInst.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include 4 | 5 | namespace hdlConvertor { 6 | namespace hdlAst { 7 | 8 | HdlCompInst::HdlCompInst(std::unique_ptr _name, 9 | std::unique_ptr _module_name) { 10 | module_name = move(_module_name); 11 | name = move(_name); 12 | } 13 | 14 | HdlCompInst::~HdlCompInst() { 15 | } 16 | 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /src/hdlAst/hdlContext.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | HdlContext::~HdlContext() { 7 | } 8 | 9 | } 10 | } 11 | -------------------------------------------------------------------------------- /src/hdlAst/hdlFunctionDef.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | HdlFunctionDef::HdlFunctionDef(const std::string &name, bool isOperator, 7 | std::unique_ptr returnT, 8 | std::unique_ptr>> params) : 9 | HdlIdDef(name, nullptr, nullptr), returnT(move(returnT)), params(move(params)), is_operator( 10 | isOperator), is_static(false), is_virtual(false), is_task( 11 | false), is_declaration_only(true) { 12 | if (!params) { 13 | params = 14 | std::make_unique>>(); 15 | } 16 | } 17 | 18 | HdlFunctionDef::~HdlFunctionDef() { 19 | } 20 | 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /src/hdlAst/hdlLibrary.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | HdlLibrary::HdlLibrary(const std::string& name) : 7 | WithNameAndDoc(name), iHdlObj() { 8 | } 9 | 10 | HdlLibrary::~HdlLibrary() { 11 | } 12 | 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /src/hdlAst/hdlModuleDec.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | namespace hdlConvertor { 5 | namespace hdlAst { 6 | 7 | HdlModuleDec::HdlModuleDec() : 8 | WithNameAndDoc() { 9 | } 10 | HdlIdDef* HdlModuleDec::getPortByName(const std::string &name) { 11 | for (auto & p : ports) { 12 | if (p->name == name) 13 | return p.get(); 14 | } 15 | return nullptr; 16 | } 17 | 18 | HdlModuleDec::~HdlModuleDec() { 19 | } 20 | 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /src/hdlAst/hdlModuleDef.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | HdlModuleDef::~HdlModuleDef() { 7 | } 8 | 9 | } 10 | } 11 | -------------------------------------------------------------------------------- /src/hdlAst/hdlNamespace.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | HdlValueIdspace::HdlValueIdspace() : 7 | WithNameAndDoc(), defs_only(false) { 8 | } 9 | 10 | HdlValueIdspace::~HdlValueIdspace() { 11 | } 12 | 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /src/hdlAst/hdlStmExpr.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | HdlStmExpr::HdlStmExpr(std::unique_ptr _expr) : 7 | iHdlStatement(), expr(move(_expr)) { 8 | } 9 | 10 | 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /src/hdlAst/hdlStmWhile.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | HdlStmWhile::HdlStmWhile(std::unique_ptr _cond, 7 | std::unique_ptr _body) : 8 | iHdlStatement(), cond(move(_cond)), body(move(_body)) { 9 | } 10 | 11 | HdlStmWhile::~HdlStmWhile() { 12 | } 13 | 14 | HdlStmDoWhile::HdlStmDoWhile(std::unique_ptr _body, 15 | std::unique_ptr _cond) : 16 | iHdlStatement(), body(move(_body)), cond(move(_cond)) { 17 | } 18 | 19 | HdlStmDoWhile::~HdlStmDoWhile() { 20 | } 21 | 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /src/hdlAst/iHdlExpr.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/hdlAst/iHdlStatement.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace hdlAst { 5 | 6 | HdlExprAndiHdlObj::HdlExprAndiHdlObj() { 7 | } 8 | 9 | HdlExprAndiHdlObj::HdlExprAndiHdlObj(std::unique_ptr _expr, 10 | std::unique_ptr _stm) : 11 | expr(move(_expr)), obj(move(_stm)) { 12 | } 13 | 14 | iHdlStatement::iHdlStatement() : 15 | iHdlObj() { 16 | in_preproc = false; 17 | } 18 | 19 | iHdlStatement::~iHdlStatement() { 20 | } 21 | 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /src/hdlAst/named.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | namespace hdlConvertor { 5 | namespace hdlAst { 6 | 7 | Named::Named() { 8 | } 9 | 10 | Named::Named(const std::string & name) : 11 | name(name) { 12 | } 13 | 14 | Named::~Named() { 15 | } 16 | 17 | WithNameAndDoc::WithNameAndDoc() : 18 | Named() { 19 | } 20 | 21 | WithNameAndDoc::WithNameAndDoc(const std::string & name) : 22 | Named(name) { 23 | } 24 | 25 | } 26 | } 27 | -------------------------------------------------------------------------------- /src/svConvertor/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | AddParserToBuild("sv2017" "svConvertor" OFF OFF ON) -------------------------------------------------------------------------------- /src/svConvertor/attributeParser.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include 4 | 5 | namespace hdlConvertor { 6 | namespace sv { 7 | 8 | void VerAttributeParser::visitAttribute_instance( 9 | sv2017Parser::Attribute_instanceContext *ctx) { 10 | // attribute_instance : '(' '*' attr_spec ( ',' attr_spec )* '*' ')' ; 11 | NotImplementedLogger::print("AttributeParser.visitAttribute_instance", ctx); 12 | } 13 | 14 | void VerAttributeParser::visitAttribute_instance( 15 | std::vector ctx) { 16 | for (auto ai : ctx) 17 | visitAttribute_instance(ai); 18 | } 19 | 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /src/svConvertor/baseSvParser.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace sv { 5 | 6 | using namespace hdlConvertor::hdlAst; 7 | 8 | BaseSvParser::BaseSvParser(SVCommentParser &_commentParser, 9 | bool _hierarchyOnly) : 10 | commentParser(_commentParser), hierarchyOnly(_hierarchyOnly) { 11 | } 12 | 13 | BaseSvParser::BaseSvParser(BaseSvParser *other) : 14 | BaseSvParser(other->commentParser, other->hierarchyOnly) { 15 | } 16 | 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /src/svConvertor/commentParser.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace sv { 5 | 6 | SVCommentParser::SVCommentParser(antlr4::TokenStream & _tokens) : 7 | tokens(dynamic_cast(_tokens)) { 8 | } 9 | 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/universal_fs.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | const std::string STRING_FILENAME = ""; 4 | 5 | -------------------------------------------------------------------------------- /src/verilogPreproc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | AddParserToBuild("verilogPreproc" "verilogPreproc" ON OFF ON) 2 | -------------------------------------------------------------------------------- /src/verilogPreproc/a_macro_def.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace verilog_pp { 5 | 6 | aMacroDef::aMacroDef(const std::string &_name) : 7 | is_persistent(false), name(_name), defined_in_file(""), defined_in_line_no( 8 | -1) { 9 | } 10 | 11 | void aMacroDef::throw_doest_not_support_args() { 12 | std::string msg = "Macro " + name 13 | + " does not expect any arguments or braces."; 14 | throw ParseException(msg); 15 | } 16 | 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /src/verilogPreproc/file_line_map.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace verilog_pp { 5 | 6 | FileLineMapItem::FileLineMapItem(size_t _line, 7 | const std::string &_file_override, size_t _line_override) : 8 | line(_line), file_override(_file_override), line_override( 9 | _line_override) { 10 | } 11 | 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /src/vhdlConvertor/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | AddParserToBuild("vhdl" "vhdlConvertor" OFF OFF ON) 2 | -------------------------------------------------------------------------------- /src/vhdlConvertor/baseVhdlParser.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace vhdl { 5 | 6 | BaseVhdlParser::BaseVhdlParser(VhdlCommentParser &_commentParser, 7 | bool _hierarchyOnly) : 8 | commentParser(_commentParser), hierarchyOnly(_hierarchyOnly) { 9 | } 10 | BaseVhdlParser::BaseVhdlParser(BaseVhdlParser &parent) : 11 | commentParser(parent.commentParser), hierarchyOnly(parent.hierarchyOnly) { 12 | } 13 | 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /src/vhdlConvertor/commentParser.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | namespace hdlConvertor { 4 | namespace vhdl { 5 | 6 | VhdlCommentParser::VhdlCommentParser(antlr4::TokenStream& _tokens) : 7 | tokens(dynamic_cast(_tokens)) { 8 | } 9 | 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/vhdlConvertor/signalParser.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | namespace hdlConvertor { 5 | namespace vhdl { 6 | 7 | using namespace hdlConvertor::hdlAst; 8 | 9 | std::unique_ptr>> VhdlSignalParser::visitSignal_declaration( 10 | vhdlParser::Signal_declarationContext *ctx) { 11 | //signal_declaration 12 | // : SIGNAL identifier_list COLON 13 | // subtype_indication ( signal_kind )? ( VARASGN expression )? SEMI 14 | // ; 15 | return VhdlInterfaceParser::extractVariables(ctx->identifier_list(), 16 | ctx->subtype_indication(), ctx->expression()); 17 | } 18 | 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /tests/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .all import main_test_suite 3 | from .time_logging_test_runner import TimeLoggingTestRunner -------------------------------------------------------------------------------- /tests/docker/python2hdlconvertor/Dockerfile: -------------------------------------------------------------------------------- 1 | FROM python:2 2 | 3 | WORKDIR /usr/src/hdlConvetor 4 | COPY . ./ 5 | 6 | RUN apt update && apt install -y cmake ninja-build libantlr4-runtime-dev antlr4 7 | RUN pip install git+https://github.com/Nic30/hdlConvertorAst.git 8 | RUN pip install -e . 9 | 10 | #CMD ["python", "-m", "tests.all"] 11 | -------------------------------------------------------------------------------- /tests/docker/readme.md: -------------------------------------------------------------------------------- 1 | # Docker files for tesing purposes 2 | 3 | Docker build should be executed from root folder (docker build context should be a root folder) 4 | ```sh 5 | docker build -t nic30/python2hdlconvertor -f tests/docker/python2hdlconvertor/Dockerfile . 6 | ``` 7 | 8 | To run use: 9 | ```sh 10 | docker run --name test -it nic30/python2hdlconvertor 11 | docker container attach test 12 | docker container exec -it test /bin/bash 13 | ``` 14 | 15 | 16 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/2012_p641.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | initial $display("start", "msg1" , "msg2", "end"); 4 | initial $display("start", " msg1" , , "end"); 5 | initial $display("start", , "msg2 ", "end"); 6 | initial $display("start", , , "end"); 7 | 8 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/2012_p642.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | $display(5,,2,,3); 4 | $display(1,,"B",,3); 5 | $display(5,,2,,); 6 | 7 | 8 | 9 | $display(1,,,,3); 10 | $display(5,,2,,"C"); 11 | $display(5,,2,,"C"); 12 | 13 | 14 | 15 | $display(1,,0,,"C"); 16 | $display(5,,0,,"C"); 17 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/2012_p642_2.txt: -------------------------------------------------------------------------------- 1 | 2 | logic [1:8] data; 3 | //define a nand with variable delay 4 | 5 | nand #(2) g121 (q21, n10, n11); 6 | nand #(5) g122 (q22, n10, n11); 7 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/2012_p643.txt: -------------------------------------------------------------------------------- 1 | 2 | n = ((p+q) > (r+s)) ? (p+q) : (r+s) ; 3 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/2012_p643_2.txt: -------------------------------------------------------------------------------- 1 | 2 | b + 1 + 42 + a 3 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/2012_p643_3.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | "`HI, world" 5 | "`HI, world" 6 | "Hello, x" 7 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/2012_p644.txt: -------------------------------------------------------------------------------- 1 | 2 | "left side: \"right side\"" 3 | 4 | 5 | clock_master 6 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/2012_p644_2.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/debug_macro.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | $display(">> %s, %d: %s", "sv_pp/src/debug_macro.txt", 3, "msg") 11 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/def_in_def.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 0 10 | 1 11 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/defined_defargs.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf p 2 | 3 | 4 | 5 | 6 | $display("Format a=%x, b=%x",a,b,); 7 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/include_many_dir/dir0-a/dir1-a/spec_incdir.txt: -------------------------------------------------------------------------------- 1 | 2 | "good content" -------------------------------------------------------------------------------- /tests/sv_pp/expected/include_many_dir/dir0-a/local_include_higher_priority.txt: -------------------------------------------------------------------------------- 1 | 2 | "good content" -------------------------------------------------------------------------------- /tests/sv_pp/expected/include_many_dir/from_subdirectory.txt: -------------------------------------------------------------------------------- 1 | 2 | "file2-a.txt" 3 | 4 | "file2-a.txt" 5 | 6 | "file2-a.txt" 7 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/include_many_dir/transitive.txt: -------------------------------------------------------------------------------- 1 | 2 | "transitive-0" 3 | 4 | "transitive-1" 5 | 6 | "transitive-2" 7 | 8 | "transitive-3" -------------------------------------------------------------------------------- /tests/sv_pp/expected/include_same_dir/basic_include.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | "a.vh" 5 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/include_same_dir/basic_include2times.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | "a.vh" 5 | 6 | 7 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/macro_args.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | "abc"(123) 5 | "abc"(123, "a" 6 | , "b", 1++<<< 7 | >> ) 8 | 456 9 | // `m2( -------------------------------------------------------------------------------- /tests/sv_pp/expected/preproc_hash_table.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf 2 | 3 | // Read hash: hash[key] 4 | 5 | // Store hash: hash[key] = v 6 | 7 | 8 | // Hash exists: defined(hash[key]) 9 | 10 | 11 | // For wrapping defines 12 | // Note the backslash newline on the `define line 13 | // and the newline following, required to form the end of a define 14 | 15 | 16 | // If defined() then 1 else 0 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 0 1 2 28 | 10 11 12 29 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/protect.v: -------------------------------------------------------------------------------- 1 | module mux_using_if( 2 | din_0 , // Mux first input 3 | din_1 , // Mux Second input 4 | sel , // Select input 5 | mux_out // Mux output 6 | ); 7 | 8 | 9 | //-----------Input Ports--------------- 10 | input din_0, din_1, sel ; 11 | //-----------Output Ports--------------- 12 | output mux_out; 13 | //------------Internal Variables-------- 14 | reg mux_out; 15 | //-------------Code Starts Here--------- 16 | always @ (sel or din_0 or din_1) 17 | begin : MUX 18 | if (sel == 1'b0) begin 19 | mux_out = din_0; 20 | end else begin 21 | mux_out = din_1 ; 22 | end 23 | end 24 | 25 | 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/stringify.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf 2 | 3 | 4 | "hello" 5 | -------------------------------------------------------------------------------- /tests/sv_pp/expected/stringify_multiline.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf 2 | 3 | 4 | 5 | 6 | $display("line1 \ 7 | line2") -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_celldefine.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | `celldefine 4 | 5 | 6 | `endcelldefine 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_default_nettype.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | `default_nettype wire 4 | 5 | `default_nettype tri 6 | 7 | `default_nettype tri0 8 | 9 | `default_nettype tri1 10 | 11 | `default_nettype wand 12 | 13 | `default_nettype triand 14 | 15 | `default_nettype wor 16 | 17 | `default_nettype trior 18 | 19 | `default_nettype trireg 20 | 21 | `default_nettype none 22 | 23 | `default_nettype uwire 24 | 25 | 26 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define1.txt: -------------------------------------------------------------------------------- 1 | `define toto 2 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define10.txt: -------------------------------------------------------------------------------- 1 | 2 | `define uvm_message_add_tag(NAME, VALUE, ACTION=(UVM_LOG|UVM_RM_RECORD)) \ 3 | __uvm_msg.add_string(NAME, VALUE, ACTION); 4 | 5 | 6 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define11.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | `define uvm_cb_trace_noobj(CB,OPER) /* null */ 4 | 5 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define12.txt: -------------------------------------------------------------------------------- 1 | `define max(a,b)- 2 | 3 | 4 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define13.txt: -------------------------------------------------------------------------------- 1 | `define max(a,b)(a,b) 2 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define2.txt: -------------------------------------------------------------------------------- 1 | `define macro toto 2 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define3.txt: -------------------------------------------------------------------------------- 1 | `define macro(a) a+a 2 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define4.txt: -------------------------------------------------------------------------------- 1 | `define macro(a,b) a**b 2 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define5.txt: -------------------------------------------------------------------------------- 1 | `define macro(a) a\ 2 | +\ 3 | a 4 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define6.txt: -------------------------------------------------------------------------------- 1 | `define macro(a=) a+a 2 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define7.txt: -------------------------------------------------------------------------------- 1 | `define macro(a=rdfhgjnk) a+a 2 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define8.txt: -------------------------------------------------------------------------------- 1 | `define A 2 | 3 | rigolo l'asticot 4 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_define9.txt: -------------------------------------------------------------------------------- 1 | 2 | //lala 3 | `define toto 4 | 5 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_ifdef.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `ifdef macro 5 | 6 | 7 | `endif 8 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_ifdef1.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `ifdef macro 5 | 6 | zozo 7 | 8 | `endif 9 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_ifdef2.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | `ifdef macro 4 | 5 | Zozo1 6 | 7 | `else 8 | 9 | ZoZo2 10 | 11 | `endif 12 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_ifdef3.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | `ifdef macro 4 | 5 | Zozo1 6 | 7 | `elsif DATA 8 | 9 | AZERTYHJ 10 | 11 | `define A 12 | i 13 | `else 14 | 15 | ZoZo2 16 | 17 | `endif 18 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_ifndef1.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | `ifndef macro 8 | 9 | 10 | `endif 11 | 12 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_include.txt: -------------------------------------------------------------------------------- 1 | 2 | `include "file1.txt" 3 | 4 | `include 5 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_keywords1.txt: -------------------------------------------------------------------------------- 1 | 2 | `begin_keywords "1800-2005" 3 | module m2 (...); 4 | reg [63:0] logic; 5 | // ERROR: "logic" is a keyword in 1800-2005 6 | ... 7 | endmodule 8 | `end_keywords 9 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_keywords2.txt: -------------------------------------------------------------------------------- 1 | 2 | `begin_keywords "1800-2005" // use IEEE Std 1800-2005 SystemVerilog keywords 3 | module m2 (...); 4 | reg [63:0] logic; 5 | // ERROR: "logic" is a keyword in 1800-2005 6 | ... 7 | endmodule 8 | `end_keywords 9 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_line_directive.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | `line 145 "thefile.txt" 4 4 | 5 | 6 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_pragma1.txt: -------------------------------------------------------------------------------- 1 | module secret (a, b); 2 | input a; 3 | output b; 4 | `pragma protect encoding=(enctype="raw") 5 | `pragma protect data_method="x-caesar", data_keyname="rot13", begin 6 | `pragma protect 7 | runtime_license=(library="lic.so",feature="runSecret",entry="chk", match=42) 8 | logic b; 9 | 10 | initial begin 11 | b = 0; 12 | end 13 | 14 | always begin 15 | #5 b = a; 16 | end 17 | `pragma protect end 18 | 19 | endmodule // secret 20 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_pragma2.txt: -------------------------------------------------------------------------------- 1 | module secret (a, b); 2 | input a; 3 | output b; 4 | `pragma protect encoding=(enctype="raw") 5 | `pragma protect data_method="x-caesar", data_keyname="rot13", begin 6 | `pragma protect runtime_license=(library="lic.so",feature="runSecret",entry="chk", match=42) 7 | logic b; 8 | 9 | initial begin 10 | b = 0; 11 | end 12 | 13 | always begin 14 | #5 b = a; 15 | end 16 | `pragma protect end 17 | 18 | endmodule // secret 19 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_real1.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | `define uvm_object_utils(T) 4 | `define uvm_field_int(ARG,FLAG=UVM_DEFAULT) 5 | 6 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_real2.txt: -------------------------------------------------------------------------------- 1 | `ifndef UVM_OBJECT_DEFINES_SVH 2 | `define UVM_OBJECT_DEFINES_SVH 3 | 4 | 5 | `ifdef UVM_EMPTY_MACROS 6 | 7 | `define uvm_object_utils(T) 8 | `define uvm_field_int(ARG,FLAG=UVM_DEFAULT) 9 | 10 | `else 11 | // The ~utils~ macros define the infrastructure needed to enable the 12 | // object/component for correct factory operation. See <`uvm_object_utils> and 13 | // <`uvm_component_utils> for details. 14 | 15 | `endif 16 | `endif 17 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_space_between_comments.txt: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | 3 | // CVS Log 4 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_timingspec.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `timescale 1ns / 10ps 5 | 6 | 7 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_token1.txt: -------------------------------------------------------------------------------- 1 | module dut(dut_if dif); 2 | import uvm_pkg::*; 3 | always @(posedge dif.clock) 4 | if (dif.reset != 1) begin 5 | `uvm_info 6 | end 7 | endmodule 8 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_token2.txt: -------------------------------------------------------------------------------- 1 | `uvm_info 2 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_token3.txt: -------------------------------------------------------------------------------- 1 | `D( "msg1" , "msg2" ) 2 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_token4.txt: -------------------------------------------------------------------------------- 1 | 2 | `D( " msg1", ) 3 | 4 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_token5.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | `D(, "msg2 ") 4 | 5 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_token6.txt: -------------------------------------------------------------------------------- 1 | 2 | `D(,) 3 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_token7.txt: -------------------------------------------------------------------------------- 1 | `wordsize data; 2 | logic [1:`wordsize] data; 3 | 4 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_token8.txt: -------------------------------------------------------------------------------- 1 | 2 | `sum ( \ 3 | `sqr(a) \ 4 | , \ 5 | `sqr(b) \ 6 | ) 7 | 8 | 9 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_unconnected_drive.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | `unconnected_drive pull0 6 | 7 | 8 | `nounconnected_drive 9 | -------------------------------------------------------------------------------- /tests/sv_pp/raw/test_undef.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | `undef y6aze 4 | 5 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p641.txt: -------------------------------------------------------------------------------- 1 | `define D(x,y) initial $display("start", x , y, "end"); 2 | 3 | `D( "msg1" , "msg2" ) 4 | `D( " msg1", ) 5 | `D(, "msg2 ") 6 | `D(,) 7 | 8 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p641_il1.txt: -------------------------------------------------------------------------------- 1 | `define D(x,y) initial $display("start", x , y, "end"); 2 | 3 | `D("msg1") 4 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p641_il2.txt: -------------------------------------------------------------------------------- 1 | `define D(x,y) initial $display("start", x , y, "end"); 2 | 3 | `D() 4 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p641_il3.txt: -------------------------------------------------------------------------------- 1 | `define D(x,y) initial $display("start", x , y, "end"); 2 | 3 | `D(,,) 4 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p642.txt: -------------------------------------------------------------------------------- 1 | `define MACRO1(a=5,b="B",c) $display(a,,b,,c); 2 | 3 | `MACRO1 ( , 2, 3 ) 4 | `MACRO1 ( 1 , , 3 ) 5 | `MACRO1 ( , 2, ) 6 | 7 | `define MACRO2(a=5, b, c="C") $display(a,,b,,c); 8 | 9 | `MACRO2 (1, , 3) 10 | `MACRO2 (, 2, ) 11 | `MACRO2 (, 2) 12 | 13 | `define MACRO3(a=5, b=0, c="C") $display(a,,b,,c); 14 | 15 | `MACRO3 ( 1 ) 16 | `MACRO3 ( ) 17 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p642_2.txt: -------------------------------------------------------------------------------- 1 | `define wordsize 8 2 | logic [1:`wordsize] data; 3 | //define a nand with variable delay 4 | `define var_nand(dly) nand #(dly) 5 | `var_nand(2) g121 (q21, n10, n11); 6 | `var_nand(5) g122 (q22, n10, n11); 7 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p642_il1.txt: -------------------------------------------------------------------------------- 1 | `define MACRO1(a=5,b="B",c) $display(a,,b,,c); 2 | 3 | `MACRO1 ( 1 ) 4 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p642_il2.txt: -------------------------------------------------------------------------------- 1 | `define MACRO3(a=5, b=0, c="C") $display(a,,b,,c); 2 | 3 | `MACRO3 4 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p642_il3.txt: -------------------------------------------------------------------------------- 1 | `define first_half "start of string 2 | $display(`first_half end of string"); 3 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p643.txt: -------------------------------------------------------------------------------- 1 | `define max(a,b)((a) > (b)) ? (a) : (b) 2 | n = `max(p+q, r+s) ; 3 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p643_2.txt: -------------------------------------------------------------------------------- 1 | `define TOP(a,b) a + b 2 | `TOP( `TOP(b,1), `TOP(42,a) ) 3 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p643_3.txt: -------------------------------------------------------------------------------- 1 | `define HI Hello 2 | `define LO "`HI, world" 3 | `define H(x) "Hello, x" 4 | "`HI, world" 5 | `LO 6 | `H(world) 7 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p644.txt: -------------------------------------------------------------------------------- 1 | `define msg(x,y) `"x: `\`"y`\`"`" 2 | `msg(left side,right side) 3 | 4 | `define append(f) f``_master 5 | `append(clock) 6 | -------------------------------------------------------------------------------- /tests/sv_pp/src/2012_p644_2.txt: -------------------------------------------------------------------------------- 1 | `define home(filename) `"empty.txt`" 2 | `include `home(myfile) 3 | -------------------------------------------------------------------------------- /tests/sv_pp/src/debug_macro.txt: -------------------------------------------------------------------------------- 1 | `include "../src/debug_macro.vh" 2 | 3 | `debug("msg") 4 | -------------------------------------------------------------------------------- /tests/sv_pp/src/debug_macro.vh: -------------------------------------------------------------------------------- 1 | `ifndef _debug_macro_vh_ 2 | `define _debug_macro_vh_ 3 | 4 | `define debug(msg) \ 5 | $display(">> %s, %d: %s", `__FILE__, `__LINE__, msg) 6 | 7 | `endif -------------------------------------------------------------------------------- /tests/sv_pp/src/def_in_def.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf 2 | `define DODEF(d) d \ 3 | 4 | `define DEF2 `DODEF(`define DEF0 0) 5 | 6 | `DODEF(`define DEF1 1) 7 | `DEF2 8 | 9 | `DEF0 10 | `DEF1 11 | -------------------------------------------------------------------------------- /tests/sv_pp/src/defined_defargs.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf p 2 | `define NONE 3 | `define MSG(fmt,a1=`NONE,a2=`NONE,a3=`NONE) \ 4 | $display(fmt,a1,a2,a3) 5 | `MSG("Format a=%x, b=%x",a,b); 6 | -------------------------------------------------------------------------------- /tests/sv_pp/src/empty.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertor/3f0e5a9218a4689c703161dc335357366fb4e98f/tests/sv_pp/src/empty.txt -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/dir0-a/dir1-a/file2-a.txt: -------------------------------------------------------------------------------- 1 | "file2-a.txt" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/dir0-a/dir1-a/spec_incdir.txt: -------------------------------------------------------------------------------- 1 | `include "file.txt" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/dir0-a/dir1-a/transitive-1.txt: -------------------------------------------------------------------------------- 1 | "transitive-1" 2 | `include "../transitive-2.txt" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/dir0-a/file.txt: -------------------------------------------------------------------------------- 1 | "good content" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/dir0-a/local_include_higher_priority.txt: -------------------------------------------------------------------------------- 1 | `include "file.txt" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/dir0-a/transitive-0.txt: -------------------------------------------------------------------------------- 1 | "transitive-0" 2 | `include "dir1-a/transitive-1.txt" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/dir0-a/transitive-2.txt: -------------------------------------------------------------------------------- 1 | "transitive-2" 2 | `include "transitive-3.txt" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/dir0-a/transitive-3.txt: -------------------------------------------------------------------------------- 1 | "transitive-3" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/file.txt: -------------------------------------------------------------------------------- 1 | "this file should not be included" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/from_subdirectory.txt: -------------------------------------------------------------------------------- 1 | `include "dir0-a/dir1-a/file2-a.txt" 2 | `include "./dir0-a/dir1-a/file2-a.txt" 3 | `include "./dir0-a/../dir0-a/dir1-a/file2-a.txt" 4 | -------------------------------------------------------------------------------- /tests/sv_pp/src/include_many_dir/transitive.txt: -------------------------------------------------------------------------------- 1 | `include "dir0-a/transitive-0.txt" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_same_dir/a.vh: -------------------------------------------------------------------------------- 1 | `ifndef _a_vh_ 2 | `define _a_vh_ 3 | "a.vh" 4 | `endif -------------------------------------------------------------------------------- /tests/sv_pp/src/include_same_dir/basic_include.txt: -------------------------------------------------------------------------------- 1 | `include "a.vh" -------------------------------------------------------------------------------- /tests/sv_pp/src/include_same_dir/basic_include2times.txt: -------------------------------------------------------------------------------- 1 | `include "a.vh" 2 | `include "a.vh" -------------------------------------------------------------------------------- /tests/sv_pp/src/indirect_ifdef.err.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf 2 | `define DEFINED 3 | `define INDIRECT(d) d 4 | `ifdef `INDIRECT(DEFINED) 5 | "passed" 6 | `endif -------------------------------------------------------------------------------- /tests/sv_pp/src/macro_args.txt: -------------------------------------------------------------------------------- 1 | `define m0 "abc" 2 | `define m1(x) x 3 | 4 | `m0(123) 5 | `m0(123, "a" 6 | , "b", 1++<<< 7 | >> ) 8 | `m1(456) 9 | // `m2( -------------------------------------------------------------------------------- /tests/sv_pp/src/protect.v: -------------------------------------------------------------------------------- 1 | module mux_using_if( 2 | din_0 , // Mux first input 3 | din_1 , // Mux Second input 4 | sel , // Select input 5 | mux_out // Mux output 6 | ); 7 | 8 | `protect 9 | //-----------Input Ports--------------- 10 | input din_0, din_1, sel ; 11 | //-----------Output Ports--------------- 12 | output mux_out; 13 | //------------Internal Variables-------- 14 | reg mux_out; 15 | //-------------Code Starts Here--------- 16 | always @ (sel or din_0 or din_1) 17 | begin : MUX 18 | if (sel == 1'b0) begin 19 | mux_out = din_0; 20 | end else begin 21 | mux_out = din_1 ; 22 | end 23 | end 24 | `endprotect 25 | 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /tests/sv_pp/src/stringify.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf 2 | 3 | `define STRINGIFY(d) `"d`" 4 | `STRINGIFY(hello) 5 | -------------------------------------------------------------------------------- /tests/sv_pp/src/stringify_multiline.txt: -------------------------------------------------------------------------------- 1 | // https://www.veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf 2 | `define MULTILINE line1 \ 3 | line2 4 | `define MSG(m) `"m`" 5 | 6 | $display(`MSG(`MULTILINE)) -------------------------------------------------------------------------------- /tests/sv_pp/src/test_FILE_LINE.sv: -------------------------------------------------------------------------------- 1 | module tb(); 2 | 3 | initial 4 | $display("Internal error: null handle at %s, line %d.", 5 | `__FILE__, `__LINE__); 6 | 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests/sv_test/others/expected/hierarchical_name_of_type.sv: -------------------------------------------------------------------------------- 1 | module ibex_alu #( 2 | parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone 3 | ) ( 4 | input ibex_pkg::alu_op_e operator_i, 5 | input logic[31:0] operand_a_i, 6 | input logic[31:0] operand_b_i 7 | ); 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests/sv_test/others/expected/operator_type.sv: -------------------------------------------------------------------------------- 1 | module top; 2 | real a = 4.76; 3 | real b = 0.74; 4 | var type(a + b) c; 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/sv_test/others/expected/stm_import.sv: -------------------------------------------------------------------------------- 1 | module chip; 2 | import chip_pkg::*; 3 | endmodule 4 | -------------------------------------------------------------------------------- /tests/sv_test/others/hierarchical_name_of_type.sv: -------------------------------------------------------------------------------- 1 | module ibex_alu #( 2 | parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone 3 | ) ( 4 | input ibex_pkg::alu_op_e operator_i, 5 | input logic [31:0] operand_a_i, 6 | input logic [31:0] operand_b_i); 7 | 8 | endmodule -------------------------------------------------------------------------------- /tests/sv_test/others/mem_base_object.sv: -------------------------------------------------------------------------------- 1 | `ifndef MEM_BASE_OBJECT_SV 2 | `define MEM_BASE_OBJECT_SV 3 | class mem_base_object; 4 | bit [7:0] addr; 5 | bit [7:0] data; 6 | // Read = 0, Write = 1 7 | bit rd_wr; 8 | endclass 9 | `endif 10 | -------------------------------------------------------------------------------- /tests/sv_test/others/operator_type.sv: -------------------------------------------------------------------------------- 1 | module top(); 2 | real a = 4.76; 3 | real b = 0.74; 4 | var type(a+b) c; 5 | endmodule -------------------------------------------------------------------------------- /tests/sv_test/others/stm_import.sv: -------------------------------------------------------------------------------- 1 | module chip; 2 | import chip_pkg::*; 3 | endmodule 4 | -------------------------------------------------------------------------------- /tests/sv_test/std2012/p102.sv: -------------------------------------------------------------------------------- 1 | virtual class C#(parameter type T = logic, parameter SIZE = 1); 2 | typedef logic [SIZE-1:0] t_vector; 3 | typedef T t_array [SIZE-1:0]; 4 | typedef struct { 5 | t_vector m0 [2*SIZE-1:0]; 6 | t_array m1; 7 | } t_struct; 8 | endclass 9 | 10 | 11 | module top (); 12 | typedef logic [7:0] t_t0; 13 | C#(t_t0,3)::t_vector v0; C#(t_t0,3)::t_array a0; 14 | C#(bit,4)::t_struct s0; 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2012/p12.sv: -------------------------------------------------------------------------------- 1 | 2 | module mux2to1 ( 3 | input wire a, 4 | output logic y 5 | 6 | ); 7 | endmodule 8 | 9 | 10 | /* 11 | module mux2to1 (input wire a, b, sel, 12 | output logic y); 13 | 14 | always_comb begin 15 | if (sel) y = a; 16 | else 17 | y = b; 18 | end 19 | 20 | endmodule: mux2to1 21 | */ 22 | -------------------------------------------------------------------------------- /tests/sv_test/std2012/p138.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | integer command; 3 | function new(); 4 | command = IDLE; 5 | endfunction 6 | endclass -------------------------------------------------------------------------------- /tests/sv_test/std2012/p139.sv: -------------------------------------------------------------------------------- 1 | class C; 2 | int c1 = 1; 3 | int c2 = 1; 4 | int c3 = 1; 5 | 6 | function new(int a); 7 | c2 = 2; 8 | c3 = a; 9 | endfunction 10 | endclass 11 | 12 | class D extends C; 13 | int d1 = 4; 14 | int d2 = c2; 15 | int d3 = 6; 16 | 17 | function new; 18 | super.new(d3); 19 | endfunction 20 | endclass -------------------------------------------------------------------------------- /tests/sv_test/std2012/p140.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertor/3f0e5a9218a4689c703161dc335357366fb4e98f/tests/sv_test/std2012/p140.sv -------------------------------------------------------------------------------- /tests/sv_test/std2012/p141.sv: -------------------------------------------------------------------------------- 1 | class id; 2 | static int current = 0; 3 | static function int next_id(); 4 | next_id = ++current; // OK to access static class property 5 | endfunction 6 | endclass -------------------------------------------------------------------------------- /tests/sv_test/std2012/p142.sv: -------------------------------------------------------------------------------- 1 | class Demo ; 2 | integer x; 3 | function new (integer x); 4 | this.x = x; 5 | endfunction 6 | endclass -------------------------------------------------------------------------------- /tests/sv_test/std2012/p147.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | local integer i; 3 | function integer compare (Packet other); 4 | compare = (this.i == other.i); 5 | endfunction 6 | endclass -------------------------------------------------------------------------------- /tests/sv_test/std2012/p148.sv: -------------------------------------------------------------------------------- 1 | class Jumbo_Packet; 2 | const int max_size = 9 * 1024; // global constant 3 | byte payload []; 4 | function new( int size ); 5 | payload = new[ size > max_size ? max_size : size ]; 6 | endfunction 7 | endclass 8 | 9 | class Big_Packet; 10 | const int size; // instance constant 11 | byte payload []; 12 | function new(); 13 | size = $urandom % 4096; //one assignment in new -> ok 14 | payload = new[ size ]; 15 | endfunction 16 | endclass -------------------------------------------------------------------------------- /tests/sv_test/std2012/p154_1.sv: -------------------------------------------------------------------------------- 1 | typedef real T; 2 | 3 | class C; 4 | typedef int T; 5 | extern function T f(); 6 | extern function real f2(); 7 | endclass 8 | 9 | function C::T C::f(); 10 | // the return must use the scope resolution 11 | // since the type is defined within the class 12 | return 1; 13 | endfunction 14 | 15 | function real C::f2(); 16 | return 1.0; 17 | endfunction -------------------------------------------------------------------------------- /tests/sv_test/std2012/p154_2.sv: -------------------------------------------------------------------------------- 1 | typedef int T; 2 | 3 | class C; 4 | extern function void f(T x); 5 | typedef real T; 6 | endclass 7 | 8 | function void C::f(T x); 9 | endfunction -------------------------------------------------------------------------------- /tests/sv_test/std2012/p160_1.sv: -------------------------------------------------------------------------------- 1 | interface class PutImp#(type PUT_T = logic); 2 | pure virtual function void put(PUT_T a); 3 | endclass 4 | 5 | interface class GetImp#(type GET_T = logic); 6 | pure virtual function GET_T get(); 7 | endclass 8 | 9 | class MyQueue #(type T = logic, int DEPTH = 1); 10 | T PipeQueue[$:DEPTH-1]; 11 | virtual function void deleteQ(); 12 | PipeQueue.delete(); 13 | endfunction 14 | endclass 15 | 16 | class Fifo #(type T = logic, int DEPTH = 1) extends MyQueue#(T, DEPTH) 17 | implements PutImp#(T), GetImp#(T); 18 | virtual function void put(T a); 19 | PipeQueue.push_back(a); 20 | endfunction 21 | virtual function T get(); 22 | get = PipeQueue.pop_front(); 23 | endfunction 24 | endclass -------------------------------------------------------------------------------- /tests/sv_test/std2012/p160_2.sv: -------------------------------------------------------------------------------- 1 | virtual class XFifo#(type T_in = logic, type T_out = logic, int DEPTH = 1) extends MyQueue#(T_out) 2 | implements PutImp#(T_in), GetImp#(T_out); 3 | pure virtual function T_out translate(T_in a); 4 | virtual function void put(T_in a); 5 | PipeQueue.push_back(translate(a)); 6 | endfunction 7 | virtual function T_out get(); 8 | get = PipeQueue.pop_front(); 9 | endfunction 10 | endclass -------------------------------------------------------------------------------- /tests/sv_test/std2012/p49.sv: -------------------------------------------------------------------------------- 1 | struct { 2 | bit [7:0] A; 3 | bit [7:0] B; 4 | byte C; 5 | } abc; -------------------------------------------------------------------------------- /tests/sv_test/std2012/p58.sv: -------------------------------------------------------------------------------- 1 | class Base #(parameter p = 1); 2 | typedef struct { 3 | real r; 4 | bit[p-1:0] data; 5 | } T; 6 | 7 | static function T Tsum (input T driver[]); 8 | Tsum.r = 0.0; 9 | Tsum.data = 0; 10 | foreach (driver[i]) 11 | Tsum.data += driver[i].data; 12 | Tsum.r = $itor(Tsum.data); 13 | endfunction 14 | endclass 15 | 16 | typedef Base#(32) MyBaseT; 17 | 18 | nettype MyBaseT::T narrowTsum with MyBaseT::Tsum; 19 | 20 | typedef Base#(64) MyBaseType; 21 | 22 | nettype MyBaseType::T wideTsum with MyBaseType::Tsum; 23 | 24 | narrowTsum net1; // data is 32 bits wide 25 | 26 | wideTsum net2; // data is 64 bits wide -------------------------------------------------------------------------------- /tests/sv_test/std2012/p59.sv: -------------------------------------------------------------------------------- 1 | package NetsPkg; 2 | nettype real realNet; 3 | endpackage : NetsPkg 4 | 5 | 6 | module top(); 7 | interconnect [0:1] iBus; 8 | lDriver l1(iBus[0]); 9 | rDriver r1(iBus[1]); 10 | rlMod m1(iBus); 11 | endmodule : top 12 | 13 | module lDriver(output wire logic out); 14 | endmodule : lDriver 15 | 16 | module rDriver 17 | import NetsPkg::*; 18 | (output realNet out); 19 | endmodule : rDriver 20 | 21 | module rlMod(input interconnect [0:1] iBus); 22 | lMod l1(iBus[0]); 23 | rMod r1(iBus[1]); 24 | endmodule : rlMod -------------------------------------------------------------------------------- /tests/sv_test/std2012/p753_1.sv: -------------------------------------------------------------------------------- 1 | module gray2bin1 (bin, gray); 2 | parameter SIZE = 8; 3 | // this module is parameterizable 4 | output [SIZE-1:0] bin; 5 | input [SIZE-1:0] gray; 6 | genvar i; 7 | generate 8 | for (i=0; i (expr [* min_cks]); 8 | endproperty 9 | a2: assert property (width); 10 | end 11 | else begin 12 | property assert_width_p; 13 | @(posedge clk) 14 | (reset_n && $rose(expr)) |-> (expr[* min_cks:max_cks]) 15 | ##1 (!expr); 16 | endproperty 17 | a2: assert property (width); 18 | end 19 | endgenerate 20 | endinterface -------------------------------------------------------------------------------- /tests/sv_test/std2012/p88.sv: -------------------------------------------------------------------------------- 1 | module ma #( parameter p1 = 1, parameter type p2 = shortint ) 2 | (input logic [p1:0] i, output logic [p1:0] o); 3 | p2 j = 0; // type of j is set by a parameter, (shortint unless redefined) 4 | always @(i) begin 5 | o = i; 6 | j++; 7 | end 8 | endmodule 9 | 10 | module mb; 11 | logic [3:0] i,o; 12 | ma #(.p1(3), .p2(int)) u1(i,o); //redefines p2 to a type of int 13 | endmodule -------------------------------------------------------------------------------- /tests/sv_test/std2012/p90.sv: -------------------------------------------------------------------------------- 1 | module msl; 2 | int st0; 3 | initial begin 4 | int st1; 5 | static int st2; 6 | automatic int auto1; 7 | end 8 | 9 | task automatic t1(); 10 | int auto2; 11 | static int st3; 12 | automatic int auto3; 13 | endtask 14 | 15 | endmodule -------------------------------------------------------------------------------- /tests/sv_test/std2012/p91.sv: -------------------------------------------------------------------------------- 1 | module top_legal; 2 | int svar1 = 1; // static keyword optional 3 | initial begin 4 | for (int i=0; i<3; i++) begin 5 | automatic int loop3 = 0; // executes every loop 6 | for (int j=0; j<3; j++) begin 7 | loop3++; 8 | $display(loop3); 9 | end 10 | end // prints 1 2 3 1 2 3 1 2 3 11 | 12 | for (int i=0; i<3; i++) begin 13 | static int loop2 = 0; // executes once before time 0 14 | for (int j=0; j<3; j++) begin 15 | loop2++; 16 | $display(loop2); 17 | end 18 | end // prints 1 2 3 4 5 6 7 8 9 19 | end 20 | endmodule : top_legal -------------------------------------------------------------------------------- /tests/sv_test/std2017/p123.sv: -------------------------------------------------------------------------------- 1 | interface quiet_time_checker #(parameter min_quiet = 0, parameter max_quiet = 0) 2 | (input logic clk, reset_n, logic [1:0]en); 3 | generate 4 | if ( max_quiet == 0) begin 5 | property quiet_time; 6 | @(posedge clk) reset_n |-> ($countones(en) == 1); 7 | endproperty 8 | a1: assert property (quiet_time); 9 | end 10 | else begin 11 | property quiet_time; 12 | @(posedge clk) 13 | (reset_n && ($past(en) != 0) && en == 0) |->(en == 0)[*min_quiet:max_quiet] ##1 ($countones(en) == 1); 14 | endproperty 15 | a1: assert property (quiet_time); 16 | end 17 | if ( (min_quiet == 0) && $isunbounded(max_quiet) ) 18 | $warning(warning_msg); 19 | endgenerate 20 | 21 | endinterface 22 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p123_2.sv: -------------------------------------------------------------------------------- 1 | interface width_checker #(parameter min_cks = 1, parameter max_cks = 1) 2 | (input logic clk, reset_n, expr); 3 | generate 4 | if ($isunbounded(max_cks)) begin 5 | property width; 6 | @(posedge clk) 7 | (reset_n && $rose(expr)) |-> (expr [* min_cks]); 8 | endproperty 9 | a2: assert property (width); 10 | end 11 | else begin 12 | property assert_width_p; 13 | @(posedge clk) 14 | (reset_n && $rose(expr)) |-> (expr[* min_cks:max_cks]) 15 | ##1 (!expr); 16 | endproperty 17 | a2: assert property (width); 18 | end 19 | endgenerate 20 | endinterface 21 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p124.sv: -------------------------------------------------------------------------------- 1 | module ma 2 | #( parameter p1 = 1, parameter type p2 = shortint ) 3 | (input logic [p1:0] i, output logic [p1:0] o); 4 | p2 j = 0; // type of j is set by a parameter, (shortint unless redefined) 5 | always @(i) begin 6 | o = i; 7 | j++; 8 | end 9 | endmodule 10 | module mb; 11 | logic [3:0] i,o; 12 | ma #(.p1(3), .p2(int)) u1(i,o); //redefines p2 to a type of int 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p125.sv: -------------------------------------------------------------------------------- 1 | module top; 2 | 3 | specify 4 | specparam tRise_clk_q = 150, tFall_clk_q = 200; 5 | specparam tRise_control = 40, tFall_control = 50; 6 | endspecify 7 | 8 | endmodule; -------------------------------------------------------------------------------- /tests/sv_test/std2017/p126.sv: -------------------------------------------------------------------------------- 1 | module msl; 2 | int st0; 3 | initial begin 4 | int st1; 5 | static int st2; 6 | automatic int auto1; 7 | end 8 | task automatic t1(); 9 | int auto2; 10 | static int st3; 11 | automatic int auto3; 12 | endtask 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p127.sv: -------------------------------------------------------------------------------- 1 | module top_legal; 2 | int svar1 = 1; 3 | // static keyword optional 4 | initial begin 5 | for (int i=0; i<3; i++) begin 6 | automatic int loop3 = 0; 7 | // executes every loop 8 | for (int j=0; j<3; j++) begin 9 | loop3++; 10 | $display(loop3); 11 | end 12 | end // prints 1 2 3 1 2 3 1 2 3 13 | for (int i=0; i<3; i++) begin 14 | static int loop2 = 0; 15 | // executes once at time zero 16 | for (int j=0; j<3; j++) begin 17 | loop2++; 18 | $display(loop2); 19 | end 20 | end // prints 1 2 3 4 5 6 7 8 9 21 | end 22 | endmodule : top_legal 23 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p130.sv: -------------------------------------------------------------------------------- 1 | package p1; 2 | typedef struct {int A;} t_1; 3 | endpackage 4 | typedef struct {int A;} t_2; 5 | module sub(); 6 | import p1::t_1; 7 | parameter type t_3 = int; 8 | parameter type t_4 = int; 9 | typedef struct {int A;} t_5; 10 | t_1 v1; t_2 v2; t_3 v3; t_4 v4; t_5 v5; 11 | endmodule 12 | module top(); 13 | typedef struct {int A;} t_6; 14 | sub #(.t_3(t_6)) s1 (); 15 | sub #(.t_3(t_6)) s2 (); 16 | initial begin 17 | s1.v1 = s2.v1; 18 | s1.v2 = s2.v2; 19 | s1.v3 = s2.v3; 20 | s1.v4 = s2.v4; 21 | //s1.v5 = s2.v5; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p137.sv: -------------------------------------------------------------------------------- 1 | typedef struct { 2 | byte length; 3 | shortint address; 4 | byte payload[]; 5 | byte chksum; 6 | } Packet; 7 | 8 | function Packet genPkt(); 9 | Packet p; 10 | void'( randomize( p.address, p.length, p.payload ) 11 | with { p.length > 1 && p.payload.size == p.length; } ); 12 | p.chksum = p.payload.xor(); 13 | return p; 14 | endfunction 15 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p137_2.sv: -------------------------------------------------------------------------------- 1 | virtual class C#(parameter type T = logic, parameter SIZE = 1); 2 | typedef logic [SIZE-1:0] t_vector; 3 | typedef T t_array [SIZE-1:0]; 4 | typedef struct { 5 | t_vector m0 [2*SIZE-1:0]; 6 | t_array m1; 7 | } t_struct; 8 | endclass 9 | 10 | module top (); 11 | typedef logic [7:0] t_t0; 12 | C#(t_t0,3)::t_vector v0; 13 | C#(t_t0,3)::t_array a0; 14 | C#(bit,4)::t_struct s0; 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p140.sv: -------------------------------------------------------------------------------- 1 | struct packed signed { 2 | int a; 3 | shortint b; 4 | byte c; 5 | bit [7:0] d; 6 | } pack1; // signed, 2-state 7 | struct packed unsigned { 8 | time a; 9 | integer b; 10 | logic [31:0] c; 11 | } pack2; // unsigned, 4-state 12 | 13 | typedef struct packed { // default unsigned 14 | bit [3:0] GFC; 15 | bit [7:0] VPI; 16 | bit [11:0] VCI; 17 | bit CLP; 18 | bit [3:0] PT ; 19 | bit [7:0] HEC; 20 | bit [47:0] [7:0] Payload; 21 | bit [2:0] filler; 22 | } s_atmcell; 23 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p141.sv: -------------------------------------------------------------------------------- 1 | typedef struct { 2 | int addr = 1 + constant; 3 | int crc; 4 | byte data [4] = '{4{1}}; 5 | } packet1; 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p142.sv: -------------------------------------------------------------------------------- 1 | typedef union packed { // default unsigned 2 | s_atmcell acell; 3 | bit [423:0] bit_slice; 4 | bit [52:0][7:0] byte_slice; 5 | } u_atmcell; 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p143.sv: -------------------------------------------------------------------------------- 1 | typedef union tagged { 2 | void Invalid; 3 | int Valid; 4 | } VInt; 5 | 6 | typedef union tagged { 7 | struct { 8 | bit [4:0] reg1, reg2, regd; 9 | } Add; 10 | union tagged { 11 | bit [9:0] JmpU; 12 | struct { 13 | bit [1:0] cc; 14 | bit [9:0] addr; 15 | } JmpC; 16 | } Jmp; 17 | } Instr; 18 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p168.sv: -------------------------------------------------------------------------------- 1 | module top; 2 | 3 | function void fn0; 4 | byte b[] = { 1, 2, 3, 4 }; 5 | int y; 6 | y = b.sum ; // y becomes 10 => 1 + 2 + 3 + 4 7 | y = b.product ; // y becomes 24 => 1 * 2 * 3 * 4 8 | y = b.xor with ( item + 4 ); // y becomes 12 => 5 ^ 6 ^ 7 ^ 8 9 | endfunction 10 | 11 | function void fn1; 12 | logic [7:0] m [2][2] = '{ '{5, 10}, '{15, 20} }; 13 | int y; 14 | y = m.sum with (item.sum with (item)); // y becomes 50 => 5+10+15+20 15 | endfunction 16 | 17 | function void fn2; 18 | logic bit_arr [1024]; 19 | int y; 20 | y = bit_arr.sum with ( int'(item) ); // forces result to be 32-bit 21 | endfunction 22 | 23 | 24 | endmodule -------------------------------------------------------------------------------- /tests/sv_test/std2017/p172.sv: -------------------------------------------------------------------------------- 1 | task task1(integer a, obj_example myexample); 2 | if (myexample == null) myexample = new; 3 | endtask 4 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p174.sv: -------------------------------------------------------------------------------- 1 | class vector #(parameter width = 7, type T = int); 2 | endclass 3 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p174_2.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | integer command; 3 | function new(); 4 | command = IDLE; 5 | endfunction 6 | endclass 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p175.sv: -------------------------------------------------------------------------------- 1 | class C; 2 | int c1 = 1; 3 | int c2 = 1; 4 | int c3 = 1; 5 | function new(int a); 6 | c2 = 2; 7 | c3 = a; 8 | endfunction 9 | endclass 10 | class D extends C; 11 | int d1 = 4; 12 | int d2 = c2; 13 | int d3 = 6; 14 | function new; 15 | super.new(d3); 16 | endfunction 17 | endclass 18 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p176.sv: -------------------------------------------------------------------------------- 1 | class E #(type T = int) extends C; 2 | T x; 3 | function new(T x_init); 4 | super.new(); 5 | x = x_init; 6 | endfunction 7 | endclass 8 | 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p177.sv: -------------------------------------------------------------------------------- 1 | class id; 2 | static int current = 0; 3 | static function int next_id(); 4 | next_id = ++current; // OK to access static class property 5 | endfunction 6 | endclass 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p178.sv: -------------------------------------------------------------------------------- 1 | class Demo ; 2 | integer x; 3 | function new (integer x); 4 | this.x = x; 5 | endfunction 6 | endclass 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p179.sv: -------------------------------------------------------------------------------- 1 | class baseA ; 2 | integer j = 5; 3 | endclass 4 | class B ; 5 | integer i = 1; 6 | baseA a = new; 7 | endclass 8 | class xtndA extends baseA; 9 | rand int x; 10 | constraint cst1 { x < 10; } 11 | endclass 12 | function integer test; 13 | xtndA xtnd1; 14 | baseA base2, base3; 15 | B b1 = new; 16 | B b2 = new b1; 17 | b2.i = 10; 18 | b2.a.j = 50; 19 | test = b1.i; 20 | test = b1.a.j; 21 | xtnd1 = new; 22 | xtnd1.x = 3; 23 | base2 = xtnd1; 24 | base3 = new base2; 25 | endfunction 26 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p180.sv: -------------------------------------------------------------------------------- 1 | class LinkedPacket; 2 | Packet packet_c; 3 | LinkedPacket next; 4 | function LinkedPacket get_next(); 5 | get_next = next; 6 | endfunction 7 | endclass 8 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p180_2.sv: -------------------------------------------------------------------------------- 1 | class LinkedPacket extends Packet; 2 | LinkedPacket next; 3 | function LinkedPacket get_next(); 4 | get_next = next; 5 | endfunction 6 | endclass 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p181.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | integer i = 1; 3 | function integer get(); 4 | get = i; 5 | endfunction 6 | endclass 7 | class LinkedPacket extends Packet; 8 | integer i = 2; 9 | function integer get(); 10 | get = -i; 11 | endfunction 12 | endclass 13 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p181_2.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | integer value; 3 | function integer delay(); 4 | delay = value * value; 5 | endfunction 6 | endclass 7 | // base class 8 | class LinkedPacket extends Packet; 9 | // derived class 10 | integer value; 11 | function integer delay(); 12 | delay = super.delay()+ value * super.value; 13 | endfunction 14 | endclass 15 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p183.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | local integer i; 3 | function integer compare (Packet other); 4 | compare = (this.i == other.i); 5 | endfunction 6 | endclass 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p184.sv: -------------------------------------------------------------------------------- 1 | class Jumbo_Packet; 2 | const int max_size = 9 * 1024; // global constant 3 | byte payload []; 4 | function new( int size ); 5 | payload = new[ size > max_size ? max_size : size ]; 6 | endfunction 7 | endclass 8 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p184_2.sv: -------------------------------------------------------------------------------- 1 | class Big_Packet; 2 | const int size; // instance constant 3 | byte payload []; 4 | function new(); 5 | size = $urandom % 4096; //one assignment in new -> ok 6 | payload = new[ size ]; 7 | endfunction 8 | endclass 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p185_2.sv: -------------------------------------------------------------------------------- 1 | typedef int T; 2 | // T and int are matching data types. 3 | class C; 4 | virtual function C some_method(int a); endfunction 5 | endclass 6 | class D extends C; 7 | virtual function D some_method(T a); endfunction 8 | endclass 9 | class E #(type Y = logic) extends C; 10 | virtual function D some_method(Y a); endfunction 11 | endclass 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p186.sv: -------------------------------------------------------------------------------- 1 | virtual class BasePacket; 2 | pure virtual function integer send(bit[31:0] data); // No implementation 3 | endclass 4 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p188.sv: -------------------------------------------------------------------------------- 1 | class Base; 2 | typedef enum {bin,oct,dec,hex} radix; 3 | static task print( radix r, integer n ); 4 | endtask 5 | endclass 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p188_2.sv: -------------------------------------------------------------------------------- 1 | class StringList; 2 | class Node; // Nested class for a node in a linked list. 3 | string name; 4 | Node link; 5 | endclass 6 | endclass 7 | class StringTree; 8 | class Node; // Nested class for a node in a binary tree. 9 | string name; 10 | Node left, right; 11 | endclass 12 | endclass 13 | // StringList::Node is different from StringTree::Node 14 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p188_3.sv: -------------------------------------------------------------------------------- 1 | class Outer; 2 | int outerProp; 3 | local int outerLocalProp; 4 | static int outerStaticProp; 5 | static local int outerLocalStaticProp; 6 | 7 | class Inner; 8 | function void innerMethod(Outer h); 9 | outerStaticProp = 0; // Legal, same as Outer::outerStaticProp 10 | outerLocalStaticProp = 0; // Legal, nested classes may access local's in outer class 11 | outerProp = 0; // Illegal, unqualified access to non-static outer 12 | h.outerProp = 0; // Legal, qualified access. 13 | h.outerLocalProp = 0; // Legal, qualified access and locals to outer class allowed. 14 | endfunction 15 | endclass 16 | endclass 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p189.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | Packet next; 3 | function Packet get_next();// single line 4 | get_next = next; 5 | endfunction 6 | // out-of-body (extern) declaration 7 | extern protected virtual function int send(int value); 8 | endclass 9 | function int Packet::send(int value); 10 | endfunction 11 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p190.sv: -------------------------------------------------------------------------------- 1 | typedef real T; 2 | class C; 3 | typedef int T; 4 | extern function T f(); 5 | extern function real f2(); 6 | endclass 7 | function C::T C::f(); 8 | return 1; 9 | endfunction 10 | // the return must use the class scope resolution 11 | // operator, since the type is defined within the 12 | // class 13 | function real C::f2(); 14 | return 1.0; 15 | endfunction 16 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p190_2.sv: -------------------------------------------------------------------------------- 1 | typedef int T; 2 | class C; 3 | extern function void f(T x); 4 | typedef real T; 5 | endclass 6 | function void C::f(T x); 7 | endfunction 8 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p191.sv: -------------------------------------------------------------------------------- 1 | class vector #(int size = 1); 2 | bit [size-1:0] a; 3 | endclass 4 | 5 | class stack #(type T = int); 6 | local T items[]; 7 | task push( T a ); endtask 8 | task pop( ref T a ); endtask 9 | endclass 10 | 11 | class vector #(int size = 1); 12 | bit [size-1:0] a; 13 | static int count = 0; 14 | function void disp_count(); 15 | $display( "count: %d of size %d", count, size ); 16 | endfunction 17 | endclass 18 | 19 | 20 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p193.sv: -------------------------------------------------------------------------------- 1 | class C #(int p = 1); 2 | parameter int q = 5; // local parameter 3 | static task t; 4 | int p; 5 | int x = C::p; // C::p disambiguates p 6 | // C::p is not p in the default specialization 7 | endtask 8 | endclass 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p193_2.sv: -------------------------------------------------------------------------------- 1 | class C #(int p = 1, type T = int); 2 | extern static function T f(); 3 | endclass 4 | function C::T C::f(); 5 | return p + C::p; 6 | endfunction 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p196.sv: -------------------------------------------------------------------------------- 1 | 2 | interface class PutImp#(type PUT_T = logic); 3 | pure virtual function void put(PUT_T a); 4 | endclass 5 | 6 | interface class GetImp#(type GET_T = logic); 7 | pure virtual function GET_T get(); 8 | endclass 9 | 10 | class MyQueue #(type T = logic, int DEPTH = 1); 11 | T PipeQueue[$:DEPTH-1]; 12 | virtual function void deleteQ(); 13 | PipeQueue.delete(); 14 | endfunction 15 | endclass 16 | 17 | class Fifo #(type T = logic, int DEPTH = 1) extends MyQueue#(T, DEPTH) implements PutImp#(T), GetImp#(T); 18 | virtual function void put(T a); 19 | PipeQueue.push_back(a); 20 | endfunction 21 | 22 | virtual function T get(); 23 | get = PipeQueue.pop_front(); 24 | endfunction 25 | endclass 26 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p196_2.sv: -------------------------------------------------------------------------------- 1 | virtual class XFifo#(type T_in = logic, type T_out = logic, int DEPTH = 1) 2 | extends MyQueue#(T_out) 3 | implements PutImp#(T_in), GetImp#(T_out); 4 | pure virtual function T_out translate(T_in a); 5 | virtual function void put(T_in a); 6 | PipeQueue.push_back(translate(a)); 7 | endfunction 8 | virtual function T_out get(); 9 | get = PipeQueue.pop_front(); 10 | endfunction 11 | endclass 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p197.sv: -------------------------------------------------------------------------------- 1 | interface class IntfClass; 2 | pure virtual function bit funcBase(); 3 | pure virtual function bit funcExt(); 4 | endclass 5 | 6 | class BaseClass; 7 | virtual function bit funcBase(); 8 | return (1); 9 | endfunction 10 | endclass 11 | 12 | class ExtClass extends BaseClass implements IntfClass; 13 | virtual function bit funcExt(); 14 | return (0); 15 | endfunction 16 | endclass 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p199.sv: -------------------------------------------------------------------------------- 1 | interface class IntfBase1; 2 | pure virtual function bit funcBase(); 3 | endclass 4 | 5 | interface class IntfBase2; 6 | pure virtual function bit funcBase(); 7 | endclass 8 | 9 | virtual class ClassBase; 10 | pure virtual function bit funcBase(); 11 | endclass 12 | 13 | class ClassExt extends ClassBase implements IntfBase1, IntfBase2; 14 | virtual function bit funcBase(); 15 | return (0); 16 | endfunction 17 | endclass 18 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p200.sv: -------------------------------------------------------------------------------- 1 | interface class IntfBaseA; 2 | pure virtual function bit funcBase(); 3 | endclass 4 | 5 | interface class IntfBaseB; 6 | pure virtual function string funcBase(); 7 | endclass 8 | 9 | class ClassA implements IntfBaseA, IntfBaseB; 10 | virtual function bit funcBase(); 11 | return (0); 12 | endfunction 13 | endclass 14 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p200_2.sv: -------------------------------------------------------------------------------- 1 | interface class PutImp#(type T = logic); 2 | pure virtual function void put(T a); 3 | endclass 4 | 5 | interface class GetImp#(type T = logic); 6 | pure virtual function T get(); 7 | endclass 8 | 9 | interface class PutGetIntf#(type TYPE = logic) extends PutImp#(TYPE), GetImp#(TYPE); 10 | typedef TYPE T; 11 | endclass 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p202.sv: -------------------------------------------------------------------------------- 1 | interface class IntfClass; 2 | pure virtual function bit funcA(); 3 | pure virtual function bit funcB(); 4 | endclass 5 | 6 | // Partial implementation of IntfClass 7 | virtual class ClassA implements IntfClass; 8 | virtual function bit funcA(); 9 | return (1); 10 | endfunction 11 | 12 | pure virtual function bit funcB(); 13 | 14 | endclass 15 | 16 | // Complete implementation of IntfClass 17 | class ClassB extends ClassA; 18 | virtual function bit funcB(); 19 | return (1); 20 | endfunction 21 | endclass 22 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p203.sv: -------------------------------------------------------------------------------- 1 | typedef class C2; 2 | class C1; 3 | C2 c; 4 | endclass 5 | class C2; 6 | C1 c; 7 | endclass 8 | 9 | 10 | typedef class C ; 11 | module top ; 12 | C#(1, real) v2 ; 13 | C#(.p(2), .T(real)) v3 ; 14 | endmodule 15 | // positional parameter override 16 | // named parameter override 17 | class C #(parameter p = 2, type T = int); 18 | endclass 19 | 20 | 21 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p220.sv: -------------------------------------------------------------------------------- 1 | sequence abc; 2 | @(posedge clk) a ##1 b ##1 c; 3 | endsequence 4 | program test; 5 | initial begin 6 | @ abc $display( "Saw a-b-c" ); 7 | end 8 | endprogram 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p221.sv: -------------------------------------------------------------------------------- 1 | sequence abc; 2 | @(posedge clk) a ##1 b ##1 c; 3 | endsequence 4 | sequence de; 5 | @(negedge clk) d ##[2:5] e; 6 | endsequence 7 | program check; 8 | initial begin 9 | wait( abc.triggered || de.triggered ); 10 | if( abc.triggered ) 11 | $display( "abc succeeded" ); 12 | if( de.triggered ) 13 | $display( "de succeeded" ); 14 | end 15 | endprogram 16 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p229.sv: -------------------------------------------------------------------------------- 1 | task get_first( output int adr ); 2 | fork 3 | wait_device( 1, adr ); 4 | wait_device( 7, adr ); 5 | wait_device( 13, adr ); 6 | join_any 7 | disable fork; 8 | endtask 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p229_2.sv: -------------------------------------------------------------------------------- 1 | class process; 2 | typedef enum { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED } state; 3 | static function process self(); 4 | endfunction 5 | 6 | function state status(); 7 | endfunction 8 | 9 | function void kill(); 10 | endfunction 11 | 12 | task await(); 13 | endtask 14 | 15 | function void suspend(); 16 | endfunction 17 | 18 | function void resume(); 19 | endfunction 20 | 21 | function void srandom( int seed ); 22 | endfunction 23 | 24 | function string get_randstate(); 25 | endfunction 26 | 27 | function void set_randstate( string state ); 28 | endfunction 29 | 30 | endclass 31 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p230.sv: -------------------------------------------------------------------------------- 1 | task automatic do_n_way( int N ); 2 | process job[] = new [N]; 3 | foreach (job[j]) 4 | fork 5 | automatic int k = j; 6 | begin job[k] = process::self(); end 7 | join_none 8 | foreach (job[j]) 9 | wait( job[j] != null ); 10 | job[1].await(); 11 | // wait for first process to finish 12 | foreach (job[j]) begin 13 | if ( job[j].status != process::FINISHED ) 14 | job[j].kill(); 15 | end 16 | endtask 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p238.sv: -------------------------------------------------------------------------------- 1 | module evaluates (out); 2 | output out; 3 | logic a, b, c; 4 | initial begin 5 | a = 0; 6 | b = 1; 7 | c = 0; 8 | end 9 | always c = #5 ~c; 10 | always @(posedge c) begin 11 | a <= b; // evaluates, schedules, 12 | b <= a; // and executes in two steps 13 | end 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p240.sv: -------------------------------------------------------------------------------- 1 | module multiple2; 2 | logic a; 3 | initial a = 1; 4 | initial a <= #4 0; 5 | initial a <= #4 1; 6 | // schedules 0 at time 4 7 | // schedules 1 at time 4 8 | // At time 4, a = ?? 9 | // The assigned value of the variable is indeterminate 10 | endmodule 11 | 12 | 13 | module multiple3; 14 | logic a; 15 | initial #8 a <= #8 1; 16 | initial #12 a <= #4 0; 17 | endmodule 18 | 19 | module multiple4; 20 | logic r1; 21 | logic [2:0] i; 22 | initial begin 23 | // makes assignments to r1 without cancelling previous assignments 24 | for (i = 0; i <= 5; i++) 25 | r1 <= # (i*10) i[0]; 26 | end 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p242.sv: -------------------------------------------------------------------------------- 1 | module dff (q, d, clear, preset, clock); 2 | output q; 3 | input d, clear, preset, clock; 4 | logic q; 5 | always @(clear or preset) 6 | if (!clear) 7 | assign q = 0; 8 | else if (!preset) 9 | assign q = 1; 10 | else 11 | deassign q; 12 | always @(posedge clock) 13 | q = d; 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p243.sv: -------------------------------------------------------------------------------- 1 | module test; 2 | logic a, b, c, d; 3 | wire e; 4 | and and1 (e, a, b, c); 5 | initial begin 6 | $monitor("%d d=%b,e=%b", $stime, d, e); 7 | assign d = a& b & c; 8 | a = 1; 9 | b = 0; 10 | c = 1; 11 | #10; 12 | force d = (a | b | c); 13 | force e = (a | b | c); 14 | #10; 15 | release d; 16 | release e; 17 | #10 $finish; 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p248.sv: -------------------------------------------------------------------------------- 1 | module mod1; 2 | typedef struct { 3 | int x; 4 | int y; 5 | } st; 6 | st s1; 7 | int k = 1; 8 | initial begin 9 | #1 s1 = '{1, 2+k}; 10 | #1 $display( s1.x, s1.y); 11 | #1 s1 = '{x:2, y:3+k}; 12 | #1 $display( s1.x, s1.y); 13 | #1 $finish; 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p249.sv: -------------------------------------------------------------------------------- 1 | typedef struct { 2 | logic [7:0] a; 3 | bit b; 4 | bit signed [31:0] c; 5 | string s; 6 | } sa; 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p252.sv: -------------------------------------------------------------------------------- 1 | module byte_swap (inout wire [31:0] A, inout wire [31:0] B); 2 | alias {A[7:0],A[15:8],A[23:16],A[31:24]} = B; 3 | endmodule 4 | 5 | 6 | module byte_rip (inout wire [31:0] W, inout wire [7:0] LSB, MSB); 7 | alias W[7:0] = LSB; 8 | alias W[31:24] = MSB; 9 | endmodule 10 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p253.sv: -------------------------------------------------------------------------------- 1 | `define LIB_DFF lib1_dff 2 | 3 | module overlap(inout wire [15:0] bus16, inout wire [11:0] low12, high12); 4 | alias bus16[11:0] = low12; 5 | alias bus16[15:4] = high12; 6 | endmodule 7 | module overlap(inout wire [15:0] bus16, inout wire [11:0] low12, high12); 8 | alias bus16 = {high12, low12[3:0]}; 9 | alias high12[7:0] = low12[11:4]; 10 | endmodule 11 | 12 | module my_dff(rst, clk, d, q, q_bar); // wrapper cell 13 | input rst, clk, d; 14 | output q, q_bar; 15 | alias rst = Reset = reset = RST; 16 | alias clk = Clk = clock = CLK; 17 | alias d = Data = data = D; 18 | alias q = Q; 19 | alias Q_ = q_bar = Q_Bar = qbar; 20 | `LIB_DFF my_dff (.*); // LIB_DFF is any of lib1_dff, lib2_dff or lib3_dff 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p269.sv: -------------------------------------------------------------------------------- 1 | module shift; 2 | logic [3:0] start, result; 3 | initial begin 4 | start = 1; 5 | result = (start << 2); 6 | end 7 | endmodule 8 | 9 | module ashift; 10 | logic signed [3:0] start, result; 11 | initial begin 12 | start = 4'b1000; 13 | result = (start >>> 2); 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p278.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | rand int header; 3 | rand int len; 4 | rand byte payload[]; 5 | int crc; 6 | constraint G { len > 1; payload.size == len ; } 7 | function void post_randomize; crc = payload.sum; endfunction 8 | endclass 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p284.sv: -------------------------------------------------------------------------------- 1 | module bitlength(); 2 | logic [3:0] a, b, c; 3 | logic [4:0] d; 4 | 5 | initial begin 6 | a = 9; 7 | b = 8; 8 | c = 1; 9 | $display("answer = %b", c ? (a&b) : d); 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p288.sv: -------------------------------------------------------------------------------- 1 | typedef union tagged { 2 | struct { 3 | bit [4:0] reg1, reg2, regd; 4 | } Add; 5 | union tagged { 6 | bit [9:0] JmpU; 7 | struct { 8 | bit [1:0] cc; 9 | bit [9:0] addr; 10 | } JmpC; 11 | } Jmp; 12 | } Instr; 13 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p289.sv: -------------------------------------------------------------------------------- 1 | module string_test; 2 | bit [8*14:1] stringvar; 3 | initial begin 4 | stringvar = "Hello world"; 5 | $display("%s is stored as %h", stringvar, stringvar); 6 | stringvar = {stringvar,"!!!"}; 7 | $display("%s is stored as %h", stringvar, stringvar); 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p292.sv: -------------------------------------------------------------------------------- 1 | package pex_gen9_common_expressions; 2 | let valid_arb(request, valid, override) = |(request & valid) || override; 3 | 4 | endpackage 5 | 6 | 7 | module my_checker; 8 | import pex_gen9_common_expressions::*; 9 | logic a, b; 10 | wire [1:0] req; 11 | wire [1:0] vld; 12 | logic ovr; 13 | initial begin 14 | if (valid_arb(.request(req), .valid(vld), .override(ovr))) begin 15 | end 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p296.sv: -------------------------------------------------------------------------------- 1 | module m(input clock); 2 | logic [15:0] a, b; 3 | logic c, d; 4 | typedef bit [15:0] bits; 5 | // let ones_match(bits x, y) = x == y; 6 | // let same(logic x, y) = x === y; 7 | always_comb 8 | a1:assert((bits'(a) == bits'(b))); 9 | property toggles(bit x, y); 10 | (logic'(x) === logic'(y)) |=> ! (logic'(x) === logic'(y)); 11 | endproperty 12 | a2: assert property (@(posedge clock) toggles(c, d)); 13 | endmodule : m 14 | 15 | 16 | module m(input clock); 17 | logic a; 18 | let p1(x) = $past(x); 19 | let p2(x) = $past(x,,,@(posedge clock)); 20 | let s(x) = $sampled(x); 21 | always_comb begin 22 | a1: assert(p1(a)); 23 | a2: assert(p2(a)); 24 | a3: assert(s(a)); 25 | end 26 | a4: assert property(@(posedge clock) p1(a)); 27 | endmodule : m 28 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p297.sv: -------------------------------------------------------------------------------- 1 | module m(input clock); 2 | logic a; 3 | // let p1(x) = $past(x); 4 | // let p2(x) = $past(x,,,@(posedge clock)); 5 | // let s(x) = $sampled(x); 6 | always_comb begin 7 | a1: assert(($past(a))); // Illegal: no clock can be inferred 8 | a2: assert(($past(a,,,@(posedge clock)))); 9 | a3: assert(($sampled (a))); 10 | end 11 | a4: assert property(@(posedge clock)($past(a))); 12 | // @(posedge clock) 13 | // is inferred 14 | endmodule : m 15 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p322.sv: -------------------------------------------------------------------------------- 1 | module traffic_lights; 2 | logic clock, red, amber, green; 3 | parameter on = 1, off = 0, red_tics = 350, 4 | amber_tics = 30, green_tics = 200; 5 | // initialize color 6 | initial red = off; 7 | initial amber = off; 8 | initial green = off; 9 | 10 | always begin 11 | red = on; 12 | light(red, red_tics); 13 | green = on; 14 | light(green, green_tics); 15 | amber = on; 16 | light(amber, amber_tics); 17 | end 18 | 19 | task light (output color, input [31:0] tics); 20 | repeat (tics) @ (posedge clock); 21 | color = off; 22 | endtask: light 23 | 24 | always begin 25 | #100 clock = 0; 26 | #100 clock = 1; 27 | end 28 | endmodule: traffic_lights 29 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p327.sv: -------------------------------------------------------------------------------- 1 | module tryfact; 2 | // define the function 3 | function automatic integer factorial (input [31:0] operand); 4 | if (operand >= 2) 5 | factorial = factorial (operand - 1) * operand; 6 | else 7 | factorial = 1; 8 | endfunction: factorial 9 | 10 | // test the function 11 | integer result; 12 | 13 | initial begin 14 | for (int n = 0; n <= 7; n++) begin 15 | result = factorial(n); 16 | $display("%0d factorial=%0d", n, result); 17 | end 18 | end 19 | endmodule: tryfact 20 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p328.sv: -------------------------------------------------------------------------------- 1 | module ram_model (address, write, chip_select, data); 2 | parameter data_width = 8; 3 | parameter ram_depth = 256; 4 | localparam addr_width = clogb2(ram_depth); 5 | input [addr_width - 1:0] address; 6 | input write, chip_select; 7 | inout [data_width - 1:0] data; 8 | //define the clogb2 function 9 | function integer clogb2 (input [31:0] value); 10 | value = value - 1; 11 | for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 12 | value = value >> 1; 13 | endfunction 14 | logic [data_width - 1:0] data_store[0:ram_depth - 1]; 15 | //the rest of the ram model 16 | endmodule: ram_model 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p330.sv: -------------------------------------------------------------------------------- 1 | function automatic int crc( byte packet [1000:1] ); 2 | for( int j= 1; j <= 1000; j++ ) begin 3 | crc ^= packet[j]; 4 | end 5 | endfunction 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p331.sv: -------------------------------------------------------------------------------- 1 | function automatic int crc( ref byte packet [1000:1] ); 2 | for( int j= 1; j <= 1000; j++ ) begin 3 | crc ^= packet[j]; 4 | end 5 | endfunction 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p332.sv: -------------------------------------------------------------------------------- 1 | task automatic show ( const ref byte data [] ); 2 | for ( int j = 0; j < data.size ; j++ ) 3 | $display( data[j] ); // data can be read but not written 4 | endtask 5 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p333.sv: -------------------------------------------------------------------------------- 1 | module m; 2 | logic a, w; 3 | task t1 (output o = a) ; // default binds to m.a 4 | endtask :t1 5 | task t3 (inout io = w) ; // default binds to m.w 6 | endtask :t3 7 | endmodule :m 8 | module n; 9 | logic a; 10 | initial begin 11 | m.t1(); // 12 | m.t3(); // 13 | end 14 | endmodule :n 15 | 16 | 17 | function int fun( int j = 1, string s = "no" ); 18 | endfunction 19 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p334.sv: -------------------------------------------------------------------------------- 1 | virtual class C#(parameter DECODE_W, parameter ENCODE_W = $clog2(DECODE_W)); 2 | static function logic [ENCODE_W-1:0] ENCODER_f 3 | (input logic [DECODE_W-1:0] DecodeIn); 4 | ENCODER_f = '0; 5 | for (int i=0; i ack; 7 | endproperty 8 | 9 | property p2(req, ack, interrupt); 10 | @($global_clock) accept_on(interrupt) p1(req, ack); 11 | endproperty 12 | 13 | my_checker check( 14 | p2(a, b, c), 15 | @($global_clock) a[*1:$] ##1 b); 16 | endmodule 17 | 18 | checker my_checker(property p, sequence s); 19 | logic checker_clk; 20 | global clocking checker_clocking @(checker_clk); endclocking 21 | assert property (p); 22 | cover property (s); 23 | endchecker 24 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p352.sv: -------------------------------------------------------------------------------- 1 | module m; 2 | bit a = 1'b1; 3 | default clocking cb @(posedge clk); 4 | output a; 5 | endclocking 6 | initial begin 7 | ## 1; 8 | cb.a <= 1'b0; 9 | @(x); // x is triggered by reactive stimulus running in same time step 10 | cb.a <= 1'b1; 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p372.sv: -------------------------------------------------------------------------------- 1 | module m (input a, b); 2 | a1: assert #0 (a == b); 3 | endmodule 4 | 5 | module m (input a, b); 6 | always_comb begin 7 | a1: assert #0 (a == b); 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p482.sv: -------------------------------------------------------------------------------- 1 | module A; 2 | logic a, clk; 3 | clocking cb_with_input @(posedge clk); 4 | input a; 5 | property p1; 6 | a; 7 | endproperty 8 | endclocking 9 | 10 | clocking cb_without_input @(posedge clk); 11 | property p1; 12 | a; 13 | endproperty 14 | endclocking 15 | 16 | property p1; 17 | @(posedge clk) a; 18 | endproperty 19 | 20 | property p2; 21 | @(posedge clk) cb_with_input.a; 22 | endproperty 23 | 24 | a1: assert property (p1); 25 | a2: assert property (cb_with_input.p1); 26 | a3: assert property (p2); 27 | a4: assert property (cb_without_input.p1); 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p488.sv: -------------------------------------------------------------------------------- 1 | checker mutex (logic [31:0] sig, event clock, output bit failure); 2 | assert property (@clock $onehot0(sig)) 3 | failure = 1'b0; else failure = 1'b1; 4 | endchecker : mutex 5 | module m(wire [31:0] bus, logic clk); 6 | logic res, scan; 7 | // ... 8 | mutex check_bus(bus, posedge clk, res); 9 | always @(posedge clk) scan <= res; 10 | endmodule : m 11 | 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p491.sv: -------------------------------------------------------------------------------- 1 | checker check(logic a, b, c, clk, rst); 2 | logic x, y, z, v, t; 3 | assign x = a; 4 | // current value of a 5 | always_ff @(posedge clk or negedge rst) // current values of clk and rst 6 | begin 7 | a1: assert (b); 8 | if (rst) 9 | z <= b; 10 | else z <= !c; 11 | end 12 | always_comb begin 13 | a2: assert (b); 14 | if (a) 15 | v = b; 16 | else v = !b; 17 | end 18 | always_latch begin 19 | a3: assert (b); 20 | if (clk) 21 | t <= b; 22 | end 23 | // ... 24 | endchecker : check 25 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p492.sv: -------------------------------------------------------------------------------- 1 | checker clocking_example (logic sig1, sig2, default_clk, rst, 2 | event e1, e2, e3 ); 3 | bit local_sig; 4 | default clocking @(posedge default_clk); endclocking 5 | always_ff @(e1) begin: p1_block 6 | p1a: assert property (sig1 == sig2); 7 | p1b: assert property (@(e1) (sig1 == sig2)); 8 | end 9 | always_ff @(e2 or e3) begin: p2_block 10 | local_sig <= rst; 11 | p2a: assert property (sig1 == sig2); 12 | p2b: assert property (@(e2) (sig1 == sig2)); 13 | end 14 | always_ff @(rst or e3) begin: p3_block 15 | local_sig <= rst; 16 | p3a: assert property (sig1 == sig2); 17 | p3b: assert property (@(e3) (sig1 == sig2)); 18 | end 19 | endchecker 20 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p493.sv: -------------------------------------------------------------------------------- 1 | checker my_check(logic clk, active); 2 | bit active_d1 = 1'b0; 3 | always_ff @(posedge clk) begin 4 | active_d1 <= active; 5 | end 6 | covergroup cg_active @(posedge clk); 7 | cp_active : coverpoint active 8 | { 9 | bins idle = { 1'b0 }; 10 | bins active = { 1'b1 }; 11 | } 12 | cp_active_d1 : coverpoint active_d1 13 | { 14 | bins idle = { 1'b0 }; 15 | bins active = { 1'b1 }; 16 | } 17 | option.per_instance = 1; 18 | endgroup 19 | cg_active cg_active_1 = new(); 20 | endchecker : my_check 21 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p493_2.sv: -------------------------------------------------------------------------------- 1 | checker op_test (logic clk, vld_1, vld_2, logic [3:0] opcode); 2 | bit [3:0] opcode_d1; 3 | always_ff @(posedge clk) opcode_d1 <= opcode; 4 | covergroup cg_op; 5 | cp_op : coverpoint opcode_d1; 6 | endgroup: cg_op 7 | cg_op cg_op_1 = new(); 8 | sequence op_accept; 9 | @(posedge clk) vld_1 ##1 (vld_2, cg_op_1.sample()); 10 | endsequence 11 | cover property (op_accept); 12 | endchecker 13 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p494.sv: -------------------------------------------------------------------------------- 1 | checker op_test (logic clk, vld_1, vld_2, logic [3:0] opcode); 2 | bit [3:0] opcode_d1; 3 | always_ff @(posedge clk) opcode_d1 <= opcode; 4 | covergroup cg_op with function sample(bit [3:0] opcode_d1); 5 | cp_op : coverpoint opcode_d1; 6 | endgroup: cg_op 7 | 8 | cg_op cg_op_1 = new(); 9 | 10 | sequence op_accept; 11 | @(posedge clk) vld_1 ##1 (vld_2, cg_op_1.sample(opcode_d1)); 12 | endsequence 13 | 14 | cover property (op_accept); 15 | 16 | endchecker 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p494_2.sv: -------------------------------------------------------------------------------- 1 | checker counter_model(logic flag); 2 | bit [2:0] counter = '0; 3 | always_ff @($global_clock) 4 | counter <= counter + 1'b1; 5 | 6 | assert property (@($global_clock) counter == 0 |-> flag); 7 | 8 | endchecker : counter_model 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p495.sv: -------------------------------------------------------------------------------- 1 | checker observer_model(bit valid, reset); 2 | default clocking @($global_clock); endclocking 3 | rand bit flag; 4 | m1: assume property (reset |=> !flag); 5 | m2: assume property (!reset && flag |=> flag); 6 | m3: assume property ($rising_gclk(flag) |-> valid); 7 | endchecker : observer_model 8 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p499.sv: -------------------------------------------------------------------------------- 1 | module my_mod(); 2 | bit mclk, v1, v2; 3 | checker c1(bit fclk, bit a, bit b); 4 | default clocking @ (posedge fclk); endclocking 5 | checker c2(bit bclk, bit x, bit y); 6 | default clocking @ (posedge bclk); endclocking 7 | rand bit m, n; 8 | u1: assume property (f1(x,m)); 9 | u2: assume property (f2(y,n)); 10 | endchecker 11 | rand bit q, r; 12 | c2 B1(fclk, q+r, r); 13 | always_ff @ (posedge fclk) 14 | r <= a || q; // assignment makes r inactive 15 | u3: assume property (f3(a, q)); 16 | u4: assume property (f4(b, r)); 17 | endchecker 18 | 19 | c1 F1(mclk, v1, const'(v2)); 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p501.sv: -------------------------------------------------------------------------------- 1 | checker check(bit clk1); // clk1 assigned in the Active region 2 | rand bit v, w; 3 | assign clk2 = clk1; 4 | m1: assume property (@clk1 !(v && w)); 5 | m2: assume property (@clk2 v || w); 6 | a1: assert property (@clk1 v != w); 7 | // ... 8 | endchecker : check 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p503.sv: -------------------------------------------------------------------------------- 1 | class Bus; 2 | rand bit[15:0] addr; 3 | rand bit[31:0] data; 4 | constraint word_align {addr[1:0] == 2'b0;} 5 | endclass 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p504.sv: -------------------------------------------------------------------------------- 1 | typedef enum {low, mid, high} AddrType; 2 | class MyBus extends Bus; 3 | rand AddrType atype; 4 | constraint addr_range 5 | { 6 | (atype == low ) -> addr inside { [0 : 15] }; 7 | (atype == mid ) -> addr inside { [16 : 127]}; 8 | (atype == high) -> addr inside {[128 : 255]}; 9 | } 10 | endclass 11 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p504_2.sv: -------------------------------------------------------------------------------- 1 | task exercise_bus (MyBus bus); 2 | int res; 3 | // EXAMPLE 1: restrict to low addresses 4 | res = bus.randomize() with {atype == low;}; 5 | // EXAMPLE 2: restrict to address between 10 and 20 6 | res = bus.randomize() with {10 <= addr && addr <= 20;}; 7 | // EXAMPLE 3: restrict data values to powers-of-two 8 | res = bus.randomize() with {(data & (data - 1)) == 0;}; 9 | endtask 10 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p506.sv: -------------------------------------------------------------------------------- 1 | class XYPair; 2 | rand integer x, y; 3 | endclass 4 | 5 | class MyXYPair extends XYPair; 6 | function void pre_randomize(); 7 | super.pre_randomize(); 8 | $display("Before randomize x=%0d, y=%0d", x, y); 9 | endfunction 10 | 11 | function void post_randomize(); 12 | super.post_randomize(); 13 | $display("After randomize x=%0d, y=%0d", x, y); 14 | endfunction 15 | endclass 16 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p507.sv: -------------------------------------------------------------------------------- 1 | class packet; 2 | typedef struct { 3 | randc int addr = 1 + constant; 4 | int crc; 5 | rand byte data [] = {1,2,3,4}; 6 | } header; 7 | rand header h1; 8 | endclass 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p508.sv: -------------------------------------------------------------------------------- 1 | typedef enum bit [1:0] { A=2'b00, B=2'b11 } ab_e; 2 | typedef struct packed { 3 | ab_e ValidAB; 4 | } VStructEnum; 5 | typedef union packed { 6 | ab_e ValidAB; 7 | } VUnion; 8 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p510.sv: -------------------------------------------------------------------------------- 1 | class C; 2 | rand int x; 3 | constraint proto1; 4 | extern constraint proto2; 5 | endclass 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p511.sv: -------------------------------------------------------------------------------- 1 | virtual class D; 2 | pure constraint Test; 3 | endclass 4 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p516.sv: -------------------------------------------------------------------------------- 1 | class C; 2 | rand byte A[] ; 3 | constraint C1 { foreach ( A [ i ] ) A[i] inside {2,4,8,16}; } 4 | constraint C2 { foreach ( A [ j ] ) A[j] > 2 * j; } 5 | endclass 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p517.sv: -------------------------------------------------------------------------------- 1 | class C; 2 | rand int A[] ; 3 | constraint c1 { A.size inside {[1:10]}; } 4 | constraint c2 { foreach ( A[ k ] ) (k < A.size - 1) -> A[k + 1] > A[k]; } 5 | endclass 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p517_2.sv: -------------------------------------------------------------------------------- 1 | class C; 2 | rand bit [7:0] A[] ; 3 | constraint c1 { A.size == 5; } 4 | constraint c2 { A.sum() with (int'(item)) < 1000; } 5 | endclass 6 | 7 | 8 | class A; 9 | // leaf node 10 | rand bit [7:0] v; 11 | endclass 12 | 13 | class B extends A; // heap node 14 | rand A left; 15 | rand A right; 16 | constraint heapcond {left.v <= v; right.v > v;} 17 | endclass 18 | 19 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p518.sv: -------------------------------------------------------------------------------- 1 | class B; 2 | rand bit s; 3 | rand bit [31:0] d; 4 | constraint c { s -> d == 0; } 5 | endclass 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p519.sv: -------------------------------------------------------------------------------- 1 | class B; 2 | rand bit s; 3 | rand bit [31:0] d; 4 | constraint c { s -> d == 0; } 5 | constraint order { solve s before d; } 6 | endclass 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p521.sv: -------------------------------------------------------------------------------- 1 | function int count_ones ( bit [9:0] w ); 2 | for( count_ones = 0; w != 0; w = w >> 1 ) 3 | count_ones += w & 1'b1; 4 | endfunction 5 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p522.sv: -------------------------------------------------------------------------------- 1 | class B; 2 | rand int x, y; 3 | constraint C { x <= F(y); } 4 | constraint D { y inside { 2, 4, 8 } ; } 5 | endclass 6 | 7 | 8 | class SList; 9 | rand int n; 10 | rand Slist next; 11 | constraint sort { n < next.n; } 12 | endclass 13 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p524.sv: -------------------------------------------------------------------------------- 1 | class D; 2 | int x; 3 | endclass 4 | class C; 5 | rand int x, y; 6 | D a, b; 7 | constraint c1 { (x < y || a.x > b.x || a.x == 5 ) -> x+y == 10; } 8 | endclass 9 | 10 | 11 | class D; 12 | int x; 13 | endclass 14 | class C; 15 | rand int x, y; 16 | D a, b; 17 | constraint c1 { (x < y && a.x > b.x && a.x == 5 ) -> x+y == 10; } 18 | endclass 19 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p525.sv: -------------------------------------------------------------------------------- 1 | class D; 2 | int x; 3 | endclass 4 | class C; 5 | rand int x, y; 6 | D a, b; 7 | constraint c1 { (x < y && (a.x > b.x || a.x ==5)) -> x+y == 10; } 8 | endclass 9 | 10 | 11 | class Packet; 12 | rand bit mode; 13 | rand int length; 14 | constraint deflt { 15 | soft length inside {32,1024}; 16 | soft mode -> length == 1024; 17 | // Note: soft mode -> {length == 1024;} is not legal syntax, 18 | // as soft must be followed by an expression 19 | } 20 | endclass 21 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p526.sv: -------------------------------------------------------------------------------- 1 | class B1; 2 | rand int x; 3 | constraint a { soft x > 10 ; soft x < 100 ; } 4 | endclass 5 | /* a1 */ 6 | /* a2 */ 7 | class D1 extends B1; 8 | constraint b { soft x inside {[5:9]} ; } 9 | endclass 10 | /* b1 */ 11 | class B2; 12 | rand int y; 13 | constraint c { soft y > 10 ; } 14 | endclass 15 | 16 | 17 | class D2 extends B2; 18 | constraint d { soft y inside {[5:9]} ; } 19 | constraint e ; 20 | /* d1 */ 21 | rand D1 p1; 22 | rand B1 p2; 23 | rand D1 p3; 24 | constraint f { soft p1.x < p2.x ; } 25 | endclass 26 | /* f1 */ 27 | constraint D2::e { soft y > 100 ; } 28 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p527.sv: -------------------------------------------------------------------------------- 1 | class A; 2 | rand int x; 3 | constraint A1 { soft x == 3; } 4 | constraint A2 { disable soft x; } // discard soft constraints 5 | constraint A3 { soft x inside { 1, 2 }; } 6 | endclass 7 | 8 | module top; 9 | initial begin 10 | A a = new(); 11 | a.randomize(); 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p530.sv: -------------------------------------------------------------------------------- 1 | class SimpleSum; 2 | rand bit [7:0] x, y, z; 3 | constraint c {z == x + y;} 4 | endclass 5 | task InlineConstraintDemo(SimpleSum p); 6 | int success; 7 | success = p.randomize() with {x < y;}; 8 | endtask 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p531.sv: -------------------------------------------------------------------------------- 1 | class C1; 2 | rand integer x; 3 | endclass 4 | class C2; 5 | integer x; 6 | integer y; 7 | task doit(C1 f, integer x, integer z); 8 | int result; 9 | result = f.randomize() with {x < y + z;}; 10 | endtask 11 | endclass 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p532.sv: -------------------------------------------------------------------------------- 1 | class C; 2 | rand integer x; 3 | endclass 4 | function int F(C obj, integer y); 5 | F = obj.randomize() with (x) { x < y; }; 6 | endfunction 7 | 8 | class C; 9 | rand integer x; 10 | endclass 11 | function int F(C obj, integer x); 12 | F = obj.randomize() with { x < local::x; }; 13 | endfunction 14 | 15 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p535.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | rand integer source_value; 3 | constraint filter1 { source_value > 2 * m; } 4 | endclass 5 | 6 | function integer toggle_rand( Packet p ); 7 | if ( p.filter1.constraint_mode() ) 8 | p.filter1.constraint_mode(0); 9 | else 10 | p.filter1.constraint_mode(1); 11 | toggle_rand = p.randomize(); 12 | endfunction 13 | 14 | 15 | class CA; 16 | rand byte x, y; 17 | byte v, w; 18 | constraint c1 { x < v && y > w; }; 19 | endclass 20 | 21 | 22 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p537.sv: -------------------------------------------------------------------------------- 1 | module stim; 2 | bit [15:0] addr; 3 | bit [31:0] data; 4 | function bit gen_stim(); 5 | bit success, rd_wr; 6 | success = randomize( addr, data, rd_wr ); 7 | return rd_wr ; 8 | endfunction 9 | // call std::randomize 10 | //... 11 | endmodule 12 | 13 | 14 | class stimc; 15 | rand bit [15:0] addr; 16 | rand bit [31:0] data; 17 | rand bit rd_wr; 18 | endclass 19 | function bit gen_stim( stimc p ); 20 | bit [15:0] addr; 21 | bit [31:0] data; 22 | bit success; 23 | success = p.randomize(); 24 | addr = p.addr; 25 | data = p.data; 26 | return p.rd_wr; 27 | endfunction 28 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p541.sv: -------------------------------------------------------------------------------- 1 | class C1; 2 | rand integer x; 3 | endclass 4 | 5 | class C2; 6 | rand integer y; 7 | endclass 8 | 9 | module top; 10 | initial begin 11 | C1 c1 = new(); 12 | C2 c2 = new(); 13 | integer z; 14 | void'(c1.randomize()); 15 | // z = $random; 16 | void'(c2.randomize()); 17 | end 18 | endmodule -------------------------------------------------------------------------------- /tests/sv_test/std2017/p550.sv: -------------------------------------------------------------------------------- 1 | module rand_sequence1(); 2 | initial begin 3 | 4 | randsequence( bin_op ) 5 | void bin_op : value operator value // void type is optional 6 | { $display("%s %b %b", operator, value[1], value[2]); } 7 | ; 8 | bit [7:0] value : { return $urandom; } ; 9 | string operator : add := 5 { return "+" ; } 10 | | dec := 2 { return "-" ; } 11 | | mult := 1 { return "*" ; } 12 | ; 13 | endsequence 14 | end 15 | endmodule -------------------------------------------------------------------------------- /tests/sv_test/std2017/p556.sv: -------------------------------------------------------------------------------- 1 | class xyz; 2 | bit [3:0] m_x; 3 | int m_y; 4 | bit m_z; 5 | covergroup cov1 @m_z; 6 | coverpoint m_x; 7 | coverpoint m_y; 8 | endgroup 9 | function new(); cov1 = new; endfunction 10 | endclass 11 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p557.sv: -------------------------------------------------------------------------------- 1 | class MC; 2 | logic [3:0] m_x; 3 | local logic m_z; 4 | bit m_e; 5 | covergroup cv1 @(posedge clk); coverpoint m_x; endgroup 6 | covergroup cv2 @m_e ; coverpoint m_z; endgroup 7 | endclass 8 | 9 | class Helper; 10 | int m_ev; 11 | endclass 12 | class MyClass; 13 | Helper m_obj; 14 | int m_a; 15 | covergroup Cov @(m_obj.m_ev); 16 | coverpoint m_a; 17 | endgroup 18 | function new(); 19 | m_obj = new; 20 | Cov = new; 21 | endfunction 22 | endclass 23 | 24 | 25 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p558.sv: -------------------------------------------------------------------------------- 1 | class C1; 2 | bit [7:0] x; 3 | covergroup cv (int arg) @(posedge clk); 4 | option.at_least = arg; 5 | coverpoint x; 6 | endgroup 7 | function new(int p1); 8 | cv = new(p1); 9 | endfunction 10 | endclass 11 | 12 | module top; 13 | initial begin 14 | C1 obj = new(4); 15 | end 16 | endmodule -------------------------------------------------------------------------------- /tests/sv_test/std2017/p560.sv: -------------------------------------------------------------------------------- 1 | covergroup cg ( ref int x , ref int y, input int c); 2 | coverpoint x; 3 | b: coverpoint y; 4 | cx: coverpoint x; 5 | option.weight = c; // set weight of "cg" to value of formal "c" 6 | bit [7:0] d: coverpoint y[31:24]; // creates coverpoint "d" covering the 7 | // high order 8 bits of the formal "y" 8 | e: coverpoint x { 9 | option.weight = 2; // set the weight of coverpoint "e" 10 | } 11 | 12 | cross x, y { 13 | option.weight = c; 14 | } 15 | endgroup 16 | 17 | 18 | covergroup g4; 19 | coverpoint s0 iff(!reset); 20 | endgroup 21 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p565.sv: -------------------------------------------------------------------------------- 1 | covergroup cg @(posedge clk); 2 | coverpoint v_a 3 | { 4 | bins sa = (4 => 5 => 6), ([7:9],10=>11,12); 5 | bins sb[] = (4=> 5 => 6), ([7:9],10=>11,12); 6 | bins sc = (12 => 3 [-> 1]); 7 | bins allother = default sequence ; 8 | } 9 | endgroup 10 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p566.sv: -------------------------------------------------------------------------------- 1 | covergroup sg @(posedge clk); 2 | coverpoint v 3 | { 4 | bins b2 = (2 [-> 3:5] ); 5 | bins b3 = (3[-> 3:5] ); 6 | bins b5 = (5 [* 3] ); 7 | bins b6 = (1 => 2 [= 3:6] => 5); 8 | } 9 | endgroup 10 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p568.sv: -------------------------------------------------------------------------------- 1 | covergroup cg23; 2 | coverpoint a 3 | { 4 | ignore_bins ignore_vals = {7,8}; 5 | ignore_bins ignore_trans = (1=>3=>5); 6 | } 7 | endgroup 8 | 9 | 10 | covergroup cg3; 11 | coverpoint b 12 | { 13 | illegal_bins bad_vals = {1,2,3}; 14 | illegal_bins bad_trans = (4=>5=>6); 15 | } 16 | endgroup 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p573.sv: -------------------------------------------------------------------------------- 1 | module top; 2 | bit [7:0] v_a, v_b; 3 | covergroup cg @(posedge clk); 4 | a: coverpoint v_a 5 | { 6 | bins a1 = { [0:63] }; 7 | bins a2 = { [64:127] }; 8 | bins a3 = { [128:191] }; 9 | bins a4 = { [192:255] }; 10 | } 11 | b: coverpoint v_b 12 | { 13 | bins b1 = {0}; 14 | bins b2 = { [1:84] }; 15 | bins b3 = { [85:169] }; 16 | bins b4 = { [170:255] }; 17 | } 18 | c : cross a, b 19 | { 20 | bins c1 = ! binsof(a) intersect {[100:200]};// 4 cross products 21 | bins c2 = binsof(a.a2) || binsof(b.b2);// 7 cross products 22 | bins c3 = binsof(a.a1) && binsof(b.b4);// 1 cross product 23 | } 24 | endgroup 25 | endmodule -------------------------------------------------------------------------------- /tests/sv_test/std2017/p576.sv: -------------------------------------------------------------------------------- 1 | class cg_cls; 2 | 3 | covergroup cg (ref logic [0:3] x, ref logic [0:7] y, ref logic [0:2] a); 4 | xy: coverpoint {x,y}; 5 | coverpoint y; 6 | XYA: cross xy, a 7 | { 8 | // the cross types are as if defined here as follows: 9 | // typedef struct {logic [11:0] xy;logic [0:2] a;} CrossValType; 10 | // typedef CrossValType CrossQueueType[$]; 11 | } 12 | endgroup 13 | 14 | covergroup cg; 15 | coverpoint a { bins x[] = {[0:10]}; } 16 | coverpoint b { bins y[] = {[0:20]}; } 17 | aXb : cross a, b 18 | { 19 | bins one = '{ '{1,2}, '{3,4}, '{5,6} }; 20 | } 21 | endgroup 22 | 23 | endclass -------------------------------------------------------------------------------- /tests/sv_test/std2017/p577.sv: -------------------------------------------------------------------------------- 1 | module mod_m; 2 | logic [31:0] a, b; 3 | covergroup cg(int cg_lim); 4 | coverpoint a; 5 | coverpoint b; 6 | aXb : cross a, b 7 | { 8 | function CrossQueueType myFunc1(int f_lim); 9 | for (int i = 0; i < f_lim; ++i) 10 | myFunc1.push_back('{i,i}); 11 | endfunction 12 | bins one = myFunc1(cg_lim); 13 | bins two = myFunc2(cg_lim); 14 | function CrossQueueType myFunc2(logic [31:0] f_lim); 15 | for (logic [31:0] i = 0; i < f_lim; ++i) 16 | myFunc2.push_back('{2*i,2*i}); 17 | endfunction 18 | } 19 | endgroup 20 | cg cg_inst = new(3); 21 | 22 | covergroup yy; 23 | cross a, b 24 | { 25 | ignore_bins ignore = binsof(a) intersect { 5, [1:3] }; 26 | } 27 | endgroup 28 | endmodule 29 | 30 | 31 | 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p578.sv: -------------------------------------------------------------------------------- 1 | covergroup zz(int bad); 2 | cross x, y 3 | { 4 | illegal_bins illegal = binsof(y) intersect {bad}; 5 | } 6 | endgroup 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p580.sv: -------------------------------------------------------------------------------- 1 | covergroup g1 (int w, string instComment) @(posedge clk) ; 2 | // track coverage information for each instance of g1 in addition 3 | // to the cumulative coverage information for covergroup type g1 4 | option.per_instance = 1; 5 | // comment for each instance of this covergroup 6 | option.comment = instComment; 7 | a : coverpoint a_var 8 | { 9 | // Create 128 automatic bins for coverpoint “a” of each instance of g1 10 | option.auto_bin_max = 128; 11 | } 12 | b : coverpoint b_var 13 | { 14 | // This coverpoint contributes w times as much to the coverage of an 15 | // instance of g1 as coverpoints "a" and "c1" 16 | option.weight = w; 17 | } 18 | c1 : cross a_var, b_var ; 19 | endgroup 20 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p584.sv: -------------------------------------------------------------------------------- 1 | module top; 2 | 3 | covergroup p_cg with function sample(bit a, int x); 4 | coverpoint x; 5 | cross x, a; 6 | endgroup : p_cg 7 | 8 | p_cg cg1 = new; 9 | 10 | property p1; 11 | int x; 12 | @(posedge clk)(a, x = b) ##1 (c, cg1.sample(a, x)); 13 | endproperty : p1 14 | 15 | c1: cover property (p1); 16 | 17 | function automatic void F(int j); 18 | bit d; 19 | cg1.sample( d, j ); 20 | endfunction 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p594.sv: -------------------------------------------------------------------------------- 1 | module test; 2 | logic set; 3 | parameter p = 1.55; 4 | initial begin 5 | $monitor($time,,"set=", set); 6 | #p set = 0; 7 | #p set = 1; 8 | end 9 | endmodule 10 | 11 | 12 | module test; 13 | logic set; 14 | parameter p = 1.55; 15 | initial begin 16 | $monitor($realtime,,"set=", set); 17 | #p set = 0; 18 | #p set = 1; 19 | end 20 | endmodule 21 | 22 | 23 | module a_dat; 24 | initial 25 | $printtimescale(b_dat.c1); 26 | endmodule 27 | 28 | module b_dat; 29 | c_dat c1 (); 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p597.sv: -------------------------------------------------------------------------------- 1 | module cntrl; 2 | initial 3 | $timeformat(-9, 5, " ns", 10); 4 | endmodule 5 | 6 | module a1_dat; 7 | logic in1; 8 | integer file; 9 | buf #10000000 (o1,in1); 10 | initial begin 11 | file = $fopen("a1.dat"); 12 | #00000000 $fmonitor(file,"%m: %t in1=%d o1=%h", $realtime,in1,o1); 13 | #10000000 in1 = 0; 14 | #10000000 in1 = 1; 15 | end 16 | endmodule 17 | 18 | module a2_dat; 19 | logic in2; 20 | integer file2; 21 | buf #10000 (o2,in2); 22 | initial begin 23 | file2=$fopen("a2.dat"); 24 | #00000 $fmonitor(file2,"%m: %t in2=%d o2=%h",$realtime,in2,o2); 25 | #10000 in2 = 0; 26 | #10000 in2 = 1; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p599.sv: -------------------------------------------------------------------------------- 1 | module driver (net_r); 2 | output [64:1] net_r; 3 | real r; 4 | wire [64:1] net_r = $realtobits(r); 5 | endmodule 6 | module receiver (net_r); 7 | input [64:1] net_r; 8 | wire [64:1] net_r; 9 | real r; 10 | initial assign r = $bitstoreal(net_r); 11 | endmodule 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p600.sv: -------------------------------------------------------------------------------- 1 | // source code 2 | // $typename would return 3 | typedef bit node; 4 | // "bit" 5 | node [2:0] X; 6 | // "bit [2:0]" 7 | int signed Y; 8 | // "int" 9 | package A; 10 | enum {A,B,C=99} X; 11 | // "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::e$1" 12 | typedef bit [9:1'b1] word; // "A::bit[9:1]" 13 | endpackage : A 14 | import A::*; 15 | module top; 16 | typedef struct {node A,B;} AB_t; 17 | AB_t AB[10]; 18 | // "struct{bit A;bit B;}top.AB_t$[0:9]" 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p608.sv: -------------------------------------------------------------------------------- 1 | module test #(N = 1) (input [N-1:0] in, output [N-1:0] out); 2 | if ((N < 1) || (N > 8)) // conditional generate construct 3 | $error("Parameter N has an invalid value of %0d", N); 4 | assign out = in; 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p621.sv: -------------------------------------------------------------------------------- 1 | module async_array(a1,a2,a3,a4,a5,a6,a7,b1,b2,b3); 2 | input a1, a2, a3, a4, a5, a6, a7 ; 3 | output b1, b2, b3; 4 | logic [1:7] mem[1:3]; // memory declaration for array personality 5 | logic b1, b2, b3; 6 | initial begin 7 | // set up the personality from the file array.dat 8 | $readmemb("array.dat", mem); 9 | // set up an asynchronous logic array with the input 10 | // and output terms expressed as concatenations 11 | $async$and$array(mem,{a1,a2,a3,a4,a5,a6,a7},{b1,b2,b3}); 12 | end 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p623.sv: -------------------------------------------------------------------------------- 1 | module top; 2 | initial $system("mv design.v adder.v"); 3 | endmodule 4 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p627.sv: -------------------------------------------------------------------------------- 1 | module disp; 2 | initial begin 3 | $display("\\\t\\\n\"\123"); 4 | end 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p628.sv: -------------------------------------------------------------------------------- 1 | module disp; 2 | logic [31:0] rval; 3 | pulldown (pd); 4 | initial begin 5 | rval = 101; 6 | $display("rval = %h hex %d decimal",rval,rval); 7 | $display("rval = %o octal\nrval = %b bin",rval,rval); 8 | $display("rval has %c ascii character value",rval); 9 | $display("pd strength value is %v",pd); 10 | $display("current scope is %m"); 11 | $display("%s is ascii value for 101",101); 12 | $display("simulation time is %t", $time); 13 | end 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p629.sv: -------------------------------------------------------------------------------- 1 | module printval; 2 | logic [11:0] r1; 3 | initial begin 4 | r1 = 10; 5 | $display( "Printing with maximum size - :%d: :%h:", r1,r1 ); 6 | $display( "Printing with minimum size - :%0d: :%0h:", r1,r1 ); 7 | end 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p633.sv: -------------------------------------------------------------------------------- 1 | module top; 2 | typedef enum {ON, OFF} switch_e; 3 | typedef struct {switch_e sw; string s;} pair_t; 4 | pair_t va[int] = '{10:'{OFF, "switch10"}, 20:'{ON, "switch20"}}; 5 | initial begin 6 | $display("va[int] = %p;",va); 7 | $display("va[int] = %0p;",va); 8 | $display("va[10].s = %p;", va[10].s); 9 | end 10 | endmodule : top 11 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p700.sv: -------------------------------------------------------------------------------- 1 | module test(a,b,c,d,e,f,g,h); 2 | input [7:0] a; 3 | input [7:0] b; 4 | input signed [7:0] c; 5 | input signed [7:0] d; 6 | output [7:0] e; 7 | output [7:0] f; 8 | output signed [7:0] g; 9 | output signed [7:0] h; // 10 | wire signed [7:0] b; // 11 | wire [7:0] c; 12 | logic signed [7:0] f;// 13 | logic [7:0] g; 14 | endmodule 15 | 16 | 17 | module complex_ports( {c,d}, .e(f) ); 18 | endmodule 19 | 20 | module split_ports (a[7:4], a[3:0]); 21 | endmodule 22 | 23 | module same_port (.a(i), .b(i)); 24 | endmodule 25 | 26 | 27 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p701.sv: -------------------------------------------------------------------------------- 1 | module renamed_concat (.a({b,c}), f, .g(h[1])); 2 | endmodule 3 | 4 | module same_input (a,a); 5 | input a; 6 | endmodule 7 | 8 | module mixed_direction (.p({a, e})); 9 | input a; 10 | // p contains both input and output directions. 11 | output e; 12 | endmodule 13 | 14 | 15 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p702.sv: -------------------------------------------------------------------------------- 1 | module test ( 2 | input [7:0] a, 3 | input signed [7:0] b, c, d, 4 | output [7:0] e, 5 | output var signed [7:0] f, g, 6 | output signed 7 | [7:0] h) ; 8 | endmodule 9 | 10 | 11 | module cpuMod(interface d, interface j); 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p703.sv: -------------------------------------------------------------------------------- 1 | module mymod ( 2 | output .P1(r[3:0]), 3 | output .P2(r[7:4]), 4 | ref 5 | .Y(x), 6 | input 7 | R ); 8 | logic [7:0] r; 9 | int x; 10 | endmodule 11 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p705.sv: -------------------------------------------------------------------------------- 1 | module mh16([5:0] x, wire y); 2 | // inout wire logic [5:0] x 3 | // inout wire logic y 4 | endmodule 5 | module mh17(input var integer x, wire y); // input var integer x 6 | // input wire logic y 7 | endmodule 8 | module mh18(output var x, input y); 9 | // output var logic x 10 | // input wire logic y 11 | endmodule 12 | module mh19(output signed [5:0] x, integer y); 13 | // output wire logic signed [5:0] x 14 | // output var integer y 15 | endmodule 16 | module mh20(ref [5:0] x, y); // ref var logic [5:0] x 17 | // ref var logic [5:0] y 18 | endmodule 19 | module mh21(ref x [5:0], y); // ref var logic x [5:0] 20 | // ref var logic y 21 | endmodule 22 | 23 | module mh22 (input wire integer p_a, .p_b(s_b), p_c); 24 | logic [5:0] s_b; 25 | endmodule 26 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p707.sv: -------------------------------------------------------------------------------- 1 | module generic_decoder 2 | #(num_code_bits = 3, localparam num_out_bits = 1 << num_code_bits) 3 | (input [num_code_bits-1:0] A, output reg [num_out_bits-1:0] Y); 4 | endmodule 5 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p710.sv: -------------------------------------------------------------------------------- 1 | parameter logic [7:0] My_DataIn = 2 | 8'hFF; 3 | module alu ( 4 | output reg [7:0] alu_out, 5 | output reg zero, 6 | input [7:0] ain, bin, 7 | input [2:0] opcode); 8 | // RTL code for the alu module 9 | endmodule 10 | module accum ( 11 | output reg [7:0] dataout, 12 | input [7:0] datain = My_DataIn, 13 | input clk, rst_n = 1'b1); 14 | // RTL code for the accumulator module 15 | endmodule 16 | module xtend ( 17 | output reg [7:0] dout, 18 | input din, 19 | input clk, rst = 1'b0 ); 20 | // RTL code for the sign-extension module 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p713.sv: -------------------------------------------------------------------------------- 1 | module alu_accum3 ( 2 | output [15:0] dataout, 3 | input [7:0] ain, bin, 4 | input [2:0] opcode, 5 | input clk, rst_n); 6 | wire [7:0] alu_out; 7 | alu 8 | alu 9 | (.alu_out, .zero(), .ain, .bin, .opcode); 10 | accum accum (.dataout(dataout[7:0]), .datain(alu_out), .clk, .rst_n()); 11 | xtend xtend (.dout(dataout[15:8]), .din(alu_out[7]), .clk, .rst); 12 | // Error: rst does not exist in the instantiation module 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p716.sv: -------------------------------------------------------------------------------- 1 | module child(output o, input i[5]); 2 | //... 3 | endmodule : child 4 | module parent(output o[8][4], 5 | input i[8][4][5] ); 6 | child c[8][4](o,i); 7 | //... 8 | endmodule : parent 9 | 10 | module MxN_pipeline #(M=3,N=4) 11 | (input [M-1:0] in, output [M-1:0] out, input clk); 12 | typedef logic T [M-1:0][1:N]; 13 | T Ins, Outs; 14 | DFF dff[M-1:0][1:N](Outs, Ins, clk); 15 | for (genvar I = M-1; I >= 0; I--) begin 16 | for (genvar J = 1; J <= N; J++) begin 17 | case (J) 18 | 1: begin 19 | assign out[I] = Outs[I][1]; 20 | assign Ins[I][J] = Outs[I][2]; 21 | end 22 | default: assign Ins[I][J] = Outs[I][J+1]; 23 | N: assign Ins[I][N] = in[I]; 24 | endcase 25 | end 26 | end 27 | endmodule : MxN_pipeline 28 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p718.sv: -------------------------------------------------------------------------------- 1 | module netlist; 2 | interconnect iwire; 3 | dut1 child1(iwire); 4 | dut2 child2(iwire); 5 | endmodule 6 | 7 | module dut1(inout wire w); 8 | assign w = 1; 9 | endmodule 10 | module dut2(inout wand w); 11 | assign w = 0; 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p720.sv: -------------------------------------------------------------------------------- 1 | extern module m (a,b,c,d); 2 | extern module a #(parameter size= 8, parameter type TP = logic [7:0]) 3 | (input [size:0] a, output TP b); 4 | module top (); 5 | wire [8:0] a; 6 | logic [7:0] b; 7 | wire 8 | c, d; 9 | m mm (.*); 10 | a aa (.*); 11 | endmodule 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p721.sv: -------------------------------------------------------------------------------- 1 | extern module m (a,b,c,d); 2 | extern module a #(parameter size = 8, parameter type TP = logic [7:0]) 3 | (input [size:0] a, output TP b); 4 | module m (.*); 5 | input a,b,c; 6 | output d; 7 | endmodule 8 | module a (.*); 9 | endmodule 10 | 11 | 12 | module m (a,b,c,d); 13 | input a,b,c; 14 | output d; 15 | endmodule 16 | module a #(parameter size = 8, parameter type TP = logic [7:0]) 17 | (input [size:0] a, output TP b); 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p723.sv: -------------------------------------------------------------------------------- 1 | module cct (stim1, stim2); 2 | input stim1, stim2; 3 | // instantiate mod 4 | mod amod(stim1), 5 | bmod(stim2); 6 | endmodule 7 | module mod (in); 8 | input in; 9 | always @(posedge in) begin : keep 10 | logic hold; 11 | hold = in; 12 | end 13 | endmodule 14 | module wave; 15 | logic stim1, stim2; 16 | cct a(stim1, stim2); // instantiate cct 17 | initial begin :wave1 18 | #100 19 | fork :innerwave 20 | reg hold; 21 | join 22 | #150 23 | begin 24 | stim1 = 0; 25 | end 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p726.sv: -------------------------------------------------------------------------------- 1 | package p; 2 | struct { int x; } s1; 3 | struct { int x; } s2; 4 | function void f(); 5 | int x; 6 | endfunction 7 | endpackage 8 | module m; 9 | import p::*; 10 | if (1) begin : s1 11 | initial begin 12 | s1.x = 1; 13 | // 14 | s2.x = 1; 15 | // 16 | f.x = 1; 17 | // 18 | f2.x = 1; 19 | // 20 | end 21 | int x; 22 | some_module s2(); 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p728.sv: -------------------------------------------------------------------------------- 1 | module a; 2 | integer i; 3 | b a_b1(); 4 | endmodule 5 | module b; 6 | integer i; 7 | c b_c1(), 8 | b_c2(); 9 | initial 10 | #10 b_c1.i = 2; 11 | endmodule 12 | // downward path references two copies of i: 13 | // a.a_b1.b_c1.i, d.d_b1.b_c1.i 14 | module c; 15 | integer i; 16 | initial begin 17 | i = 1; 18 | // 19 | // 20 | // 21 | // 22 | // 23 | b.i = 1; 24 | end 25 | endmodule 26 | module d; 27 | integer i; 28 | b d_b1(); 29 | initial begin 30 | a.i = 1; 31 | a.a_b1.i = 2; 32 | a.a_b1.b_c1.i = 3; 33 | a.a_b1.b_c2.i = 4; 34 | end 35 | endmodule 36 | 37 | 38 | task t; 39 | int x; 40 | x = f(1); // valid reference to function f in $unit scope 41 | endtask 42 | function int f(int y); 43 | return y+1; 44 | endfunction 45 | 46 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p729.sv: -------------------------------------------------------------------------------- 1 | package p; 2 | function void f(); 3 | $display("p::f"); 4 | endfunction 5 | endpackage 6 | module top; 7 | import p::*; 8 | if (1) begin : b 9 | // generate block 10 | initial f(); 11 | // reference to “f” 12 | function void f(); 13 | $display("top.b.f"); 14 | endfunction 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p730.sv: -------------------------------------------------------------------------------- 1 | task t; 2 | logic s; 3 | begin : b 4 | logic r; 5 | t.b.r = 0;// These three lines access the same variable r 6 | b.r = 0; 7 | r = 0; 8 | t.s = 0;// These two lines access the same variable s 9 | s = 0; 10 | end 11 | endtask 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p731.sv: -------------------------------------------------------------------------------- 1 | module generic_fifo 2 | #(MSB=3, LSB=0) // parameter port list parameters 3 | (input wire [MSB:LSB] in, 4 | input wire clk, read, write, reset, 5 | output logic [MSB:LSB] out, 6 | output logic full, empty ); 7 | parameter DEPTH=4; 8 | // module item parameter 9 | localparam FIFO_MSB = DEPTH*MSB; 10 | localparam FIFO_LSB = LSB; 11 | // These constants are local, and cannot be overridden. 12 | // They can be affected by altering the value parameters above 13 | logic [FIFO_MSB:FIFO_LSB] fifo; 14 | logic [LOG2(DEPTH):0] depth; 15 | always @(posedge clk or posedge reset) begin 16 | casez ({read,write,reset}) 17 | 3'b??? : out <= 0; 18 | endcase 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p732.sv: -------------------------------------------------------------------------------- 1 | module m1 (a,b); 2 | real r1,r2; 3 | parameter [2:0] A = 3'h2; 4 | parameter B = 3'h2; 5 | initial begin 6 | r1 = A; 7 | r2 = B; 8 | $display("r1 is %f r2 is %f",r1,r2); 9 | end 10 | endmodule: m1 11 | module m2; 12 | wire a,b; 13 | defparam f1.A = 3.1415; 14 | defparam f1.B = 3.1415; 15 | m1 f1(a,b); 16 | endmodule: m2 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p733.sv: -------------------------------------------------------------------------------- 1 | module top; 2 | logic clk; 3 | logic [0:4] in1; 4 | logic [0:9] in2; 5 | wire [0:4] o1; 6 | wire [0:9] o2; 7 | vdff m1 (o1, in1, clk); 8 | vdff m2 (o2, in2, clk); 9 | endmodule 10 | module vdff (out, in, clk); 11 | parameter size = 1, delay = 1; 12 | input [0:size-1] in; 13 | input 14 | clk; 15 | output [0:size-1] out; 16 | logic [0:size-1] out; 17 | always @(posedge clk) 18 | # delay out = in; 19 | endmodule 20 | 21 | module annotate; 22 | defparam 23 | top.m1.size = 5, 24 | top.m1.delay = 10, 25 | top.m2.size = 10, 26 | top.m2.delay = 20; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p734.sv: -------------------------------------------------------------------------------- 1 | module tb1; 2 | wire [9:0] out_a, out_d; 3 | wire [4:0] out_b, out_c; 4 | logic [9:0] in_a, in_d; 5 | logic [4:0] in_b, in_c; 6 | logic clk; 7 | vdff #(10,15) mod_a (.out(out_a), .in(in_a),.clk(clk)); 8 | vdff mod_b (.out(out_b), .in(in_b),.clk(clk)); 9 | vdff #( 5,12) mod_c (.out(out_c), .in(in_c),.clk(clk)); 10 | vdff #(10) mod_d (.out(out_d), .in(in_d),.clk(clk)); 11 | 12 | 13 | 14 | 15 | endmodule 16 | module vdff (out, in, clk); 17 | parameter size=5, delay=1; 18 | output [size-1:0] out; 19 | input [size-1:0] in; 20 | input 21 | logic 22 | clk; 23 | [size-1:0] out; 24 | always @(posedge clk) 25 | #delay out = in; 26 | endmodule 27 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p736.sv: -------------------------------------------------------------------------------- 1 | module tb3; 2 | // declarations & code 3 | // legal mixture of instance with positional parameters and 4 | // another instance with named parameters 5 | vdff #(10, 15) 6 | mod_a (.out(out_a), .in(in_a), .clk(clk)); 7 | vdff 8 | mod_b (.out(out_b), .in(in_b), .clk(clk)); 9 | vdff #(.delay(12)) mod_c (.out(out_c), .in(in_c), .clk(clk)); 10 | endmodule 11 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p737.sv: -------------------------------------------------------------------------------- 1 | class C ; 2 | endclass 3 | module M #( type T = C, T p = 4, 4 | type T2, T2 p2 = 4 5 | ) () ; 6 | endmodule 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p738.sv: -------------------------------------------------------------------------------- 1 | module m; 2 | m1 n(); 3 | endmodule 4 | module m1; 5 | parameter p = 2; 6 | defparam m.n.p = 1; 7 | initial $display(m.n.p); 8 | generate 9 | if (p == 1) begin : m 10 | m2 n(); 11 | end 12 | endgenerate 13 | endmodule 14 | module m2; 15 | parameter p = 3; 16 | endmodule 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p745.sv: -------------------------------------------------------------------------------- 1 | module m; 2 | logic r; 3 | wire dw1, dw2; 4 | initial begin 5 | r = 0; 6 | #10 r = 1; 7 | end 8 | assign dw1 = r; 9 | p p_i(dw2, dw1); 10 | always @(dw2) 11 | $display("dw2 is %b", dw2); 12 | endmodule 13 | program p(output pw2, input pw1); 14 | assign pw2 = pw1; 15 | endprogram 16 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p753.sv: -------------------------------------------------------------------------------- 1 | module memMod (interface a, input logic clk); 2 | endmodule 3 | module cpuMod (interface b, input logic clk); 4 | endmodule 5 | module top; 6 | logic clk = 0; 7 | simple_bus sb_intf(); 8 | memMod mem (.*, .a(sb_intf)); // partial implicit port connections 9 | cpuMod cpu (.*, .b(sb_intf)); // partial implicit port connections 10 | endmodule 11 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p755.sv: -------------------------------------------------------------------------------- 1 | module m (i2.master i); 2 | endmodule 3 | module s (i2.slave i); 4 | endmodule 5 | module top; 6 | i2 i(); 7 | m u1(.i(i)); 8 | s u2(.i(i)); 9 | endmodule 10 | 11 | module m (i2 i); 12 | endmodule 13 | module s (i2 i); 14 | endmodule 15 | module top; 16 | i2 i(); 17 | m u1(.i(i.master)); 18 | s u2(.i(i.slave)); 19 | endmodule 20 | 21 | 22 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p758.sv: -------------------------------------------------------------------------------- 1 | interface I; 2 | logic [7:0] r; 3 | const int x=1; 4 | bit R; 5 | modport A (output .P(r[3:0]), input .Q(x), R); 6 | modport B (output .P(r[7:4]), input .Q(2), R); 7 | endinterface 8 | module M ( interface i); 9 | initial i.P = i.Q; 10 | endmodule 11 | module top; 12 | I i1 (); 13 | M u1 (i1.A); 14 | M u2 (i1.B); 15 | initial #1 $display("%b", i1.r); 16 | endmodule 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p760.sv: -------------------------------------------------------------------------------- 1 | interface itf; 2 | logic c,q,d; 3 | modport flop (input c,d, output q); 4 | endinterface 5 | 6 | module dtype (itf.flop ch); 7 | always_ff @(posedge ch.c) ch.q <= ch.d; 8 | specify 9 | ( posedge ch.c => (ch.q+:ch.d)) = (5,6); 10 | $setup( ch.d, posedge ch.c, 1 ); 11 | endspecify 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p772.sv: -------------------------------------------------------------------------------- 1 | module top; 2 | logic clk; 3 | SyncBus b1( clk ); 4 | SyncBus b2( clk ); 5 | initial begin 6 | VI v[2] = '{ b1, b2 }; 7 | repeat( 20 ) 8 | do_it( v[ $urandom_range( 0, 1 ) ] ); 9 | end 10 | endmodule 11 | 12 | 13 | interface A_Bus( input logic clk ); 14 | wire req, gnt; 15 | wire [7:0] addr, data; 16 | clocking sb @(posedge clk); 17 | input gnt; 18 | output req, addr; 19 | inout data; 20 | property p1; req ##[1:3] gnt; endproperty 21 | endclocking 22 | modport DUT ( input clk, req, addr, 23 | output gnt, 24 | inout data ); // Device under test modport 25 | modport STB ( clocking sb ); // synchronous testbench modport 26 | modport TB ( input gnt, 27 | output req, addr, 28 | inout data ); 29 | endinterface 30 | 31 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p774.sv: -------------------------------------------------------------------------------- 1 | interface ebus_i; 2 | integer I; 3 | // reference to I not allowed through modport mp 4 | typedef enum {Y,N} choice; 5 | choice Q; 6 | localparam True = 1; 7 | modport mp(input Q); 8 | endinterface 9 | module Top; 10 | ebus_i ebus (); 11 | sub s1 (ebus.mp); 12 | endmodule 13 | module sub(interface.mp i); 14 | typedef i.choice yes_no; 15 | yes_no P; 16 | assign P = i.Q; 17 | initial 18 | Top.ebus.Q = i.True; 19 | initial 20 | Top.ebus.I = 0; 21 | endmodule 22 | 23 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p776.sv: -------------------------------------------------------------------------------- 1 | package ComplexPkg; 2 | typedef struct { 3 | shortreal i, r; 4 | } Complex; 5 | function Complex add(Complex a, b); 6 | add.r = a.r + b.r; 7 | add.i = a.i + b.i; 8 | endfunction 9 | function Complex mul(Complex a, b); 10 | mul.r = (a.r * b.r) - (a.i * b.i); 11 | mul.i = (a.r * b.i) + (a.i * b.r); 12 | endfunction 13 | endpackage : ComplexPkg 14 | 15 | 16 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p777.sv: -------------------------------------------------------------------------------- 1 | package p; 2 | typedef enum { FALSE, TRUE } bool_t; 3 | endpackage 4 | package q; 5 | typedef enum { ORIGINAL, FALSE } teeth_t; 6 | endpackage 7 | module top1 ; 8 | import p::*; 9 | import q::teeth_t; 10 | teeth_t myteeth; 11 | initial begin 12 | myteeth = q:: FALSE; // OK: 13 | myteeth = FALSE; 14 | // ERROR: Direct reference to FALSE refers to the 15 | end 16 | // FALSE enumeration literal imported from p 17 | endmodule 18 | module top2 ; 19 | import p::*; 20 | import q::teeth_t, q::ORIGINAL, q::FALSE; 21 | teeth_t myteeth; 22 | initial begin 23 | myteeth = FALSE; 24 | end 25 | endmodule 26 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p779.sv: -------------------------------------------------------------------------------- 1 | package p; 2 | int x; 3 | endpackage 4 | module top; 5 | import p::*; 6 | if (1) begin : b 7 | initial x = 1; 8 | int x; 9 | initial x = 1; 10 | end 11 | int x; 12 | endmodule 13 | 14 | package p; 15 | int x; 16 | endpackage 17 | package p2; 18 | int x; 19 | endpackage 20 | module top; 21 | import p::*; 22 | if (1) begin : b 23 | initial x = 1; 24 | import p2::*; 25 | end 26 | endmodule 27 | 28 | package p; 29 | function int f(); 30 | return 1; 31 | endfunction 32 | endpackage 33 | module top; 34 | int x; 35 | if (1) begin : b 36 | initial x = f(); 37 | import p::*; 38 | end 39 | 40 | function int f(); 41 | return 1; 42 | endfunction 43 | endmodule 44 | 45 | 46 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p780.sv: -------------------------------------------------------------------------------- 1 | package p; 2 | function int f(); 3 | return 1; 4 | endfunction 5 | endpackage 6 | package p2; 7 | function int f(); 8 | return 1; 9 | endfunction 10 | endpackage 11 | module top; 12 | import p::*; 13 | int x; 14 | if (1) begin : b 15 | initial x = f(); 16 | end 17 | import p2::*; 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p781.sv: -------------------------------------------------------------------------------- 1 | package A; 2 | typedef struct { 3 | bit [ 7:0] opcode; 4 | bit [23:0] addr; 5 | } instruction_t; 6 | endpackage: A 7 | package B; 8 | typedef enum bit {FALSE, TRUE} boolean_t; 9 | endpackage: B 10 | module M import A::instruction_t, B::*; 11 | #(WIDTH = 32) 12 | (input [WIDTH-1:0] 13 | data, 14 | input instruction_t a, 15 | output [WIDTH-1:0] 16 | result, 17 | output boolean_t 18 | OK 19 | ); 20 | endmodule: M 21 | 22 | 23 | package p; 24 | typedef enum { FALSE, TRUE } BOOL; 25 | const BOOL c = FALSE; 26 | endpackage 27 | 28 | package q; 29 | const int c = 0; 30 | endpackage 31 | 32 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p782.sv: -------------------------------------------------------------------------------- 1 | module m; 2 | import q::*; 3 | wire 4 | a = c; 5 | import p::c; 6 | endmodule 7 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p791.sv: -------------------------------------------------------------------------------- 1 | module addergen1 (co, sum, a, b, ci); 2 | parameter SIZE = 4; 3 | output [SIZE-1:0] sum; 4 | output 5 | co; 6 | input [SIZE-1:0] a, b; 7 | input 8 | ci; 9 | wire 10 | [SIZE :0] c; 11 | genvar 12 | i; 13 | assign c[0] = ci; 14 | for(i=0; i out) = (invertrise, invertfall); 9 | if (b) (a => out) = (invertrise, invertfall); 10 | if (~a)(b => out) = (noninvrise, noninvfall); 11 | if (~b)(a => out) = (noninvrise, noninvfall); 12 | endspecify 13 | endmodule 14 | 15 | 16 | 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p845.sv: -------------------------------------------------------------------------------- 1 | module ALU (o1, i1, i2, opcode); 2 | input [7:0] i1, i2; 3 | input [2:1] opcode; 4 | output [7:0] o1; 5 | //functional description omitted 6 | specify 7 | // add operation 8 | if (opcode == 2'b00) (i1,i2 *> o1) = (25.0, 25.0); 9 | // pass-through i1 operation 10 | if (opcode == 2'b01) (i1 => o1) = (5.6, 8.0); 11 | // pass-through i2 operation 12 | if (opcode == 2'b10) (i2 => o1) = (5.6, 8.0); 13 | // delays on opcode changes 14 | (opcode *> o1) = (6.1, 6.5); 15 | endspecify 16 | endmodule 17 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p847.sv: -------------------------------------------------------------------------------- 1 | module mux8 (in1, in2, s, q) ; 2 | output [7:0] q; 3 | input [7:0] in1, in2; 4 | input s; 5 | // Functional description omitted ... 6 | specify 7 | (in1 => q) = (3, 4) ; 8 | (in2 => q) = (2, 3) ; 9 | (s *> q) = 1; 10 | endspecify 11 | endmodule 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p85.sv: -------------------------------------------------------------------------------- 1 | struct { 2 | bit [7:0] A; 3 | bit [7:0] B; 4 | byte C; 5 | } abc; 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p886.sv: -------------------------------------------------------------------------------- 1 | module DFF (Q, CLK, DAT); 2 | input CLK; 3 | input [7:0] DAT; 4 | output [7:0] Q; 5 | always @(posedge clk) 6 | Q = DAT; 7 | specify 8 | $setup (DAT, posedge CLK, 10); 9 | endspecify 10 | endmodule 11 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p918.sv_unsupported: -------------------------------------------------------------------------------- 1 | module secret (a, b); 2 | input a; 3 | output b; 4 | `pragma protect encoding=(enctype="raw") 5 | `pragma protect data_method="x-caesar", data_keyname="rot13", begin 6 | `pragma protect 7 | runtime_license=(library="lic.so",feature="runSecret",entry="chk", match=42) 8 | logic b; 9 | initial 10 | begin 11 | b = 0; 12 | end 13 | always 14 | begin 15 | #5 b = a; 16 | end 17 | `pragma protect end 18 | endmodule // secret 19 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p919.sv_unsupported: -------------------------------------------------------------------------------- 1 | module secret (a, b); 2 | input a; 3 | output b; 4 | `pragma protect encoding=(enctype="raw") 5 | `pragma protect data_method="x-caesar", data_keyname="rot13", 6 | begin_protected 7 | `pragma protect encoding=(enctype="raw", bytes=190), data_block 8 | `centzn cebgrpg ehagvzr_yvprafr=(yvoenel="yvp.fb",srngher="ehaFrperg", 9 | ragel="pux",zngpu=42) 10 | ert o; 11 | vavgvny 12 | ortva 13 | o = 0; 14 | raq 15 | nyjnlf 16 | ortva 17 | #5 o = n; 18 | raq 19 | `pragma protect end_protected 20 | `pragma reset protect 21 | endmodule // secret 22 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p93.sv: -------------------------------------------------------------------------------- 1 | // user-defined data type T 2 | typedef struct { 3 | real field1; 4 | bit field2; 5 | } T; 6 | // user-defined resolution function Tsum 7 | function automatic T Tsum (input T driver[]); 8 | Tsum.field1 = 0.0; 9 | foreach (driver[i]) 10 | Tsum.field1 += driver[i].field1; 11 | endfunction 12 | nettype T wT; 13 | // an unresolved nettype wT whose data type is T 14 | // a nettype wTsum whose data type is T and 15 | // resolution function is Tsum 16 | nettype T wTsum with Tsum; 17 | // user-defined data type TR 18 | typedef real TR[5]; 19 | // an unresolved nettype wTR whose data type 20 | // is an array of real 21 | nettype TR wTR; 22 | // declare another name nettypeid2 for nettype wTsum 23 | nettype wTsum nettypeid2; 24 | 25 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p94.sv: -------------------------------------------------------------------------------- 1 | class Base #(parameter p = 1); 2 | typedef struct { 3 | real r; 4 | bit[p-1:0] data; 5 | } T; 6 | static function T Tsum (input T driver[]); 7 | Tsum.r = 0.0; 8 | Tsum.data = 0; 9 | foreach (driver[i]) 10 | Tsum.data += driver[i].data; 11 | Tsum.r = $itor(Tsum.data); 12 | endfunction 13 | endclass 14 | typedef Base#(32) MyBaseT; 15 | nettype MyBaseT::T narrowTsum with MyBaseT::Tsum; 16 | typedef Base#(64) MyBaseType; 17 | nettype MyBaseType::T wideTsum with MyBaseType::Tsum; 18 | narrowTsum net1; // data is 32 bits wide 19 | wideTsum net2; // data is 64 bits wide 20 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p940.sv: -------------------------------------------------------------------------------- 1 | export "DPI-C" f_plus = function \f+ ; // "f+" exported as "f_plus" 2 | export "DPI-C" function f; // "f" exported under its own name 3 | import "DPI-C" init_1 = function void \init[1] (); // "init_1" is a linkage name 4 | import "DPI-C" \begin = function void \init[2] (); // "begin" is a linkage name 5 | 6 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p95.sv: -------------------------------------------------------------------------------- 1 | package NetsPkg; 2 | nettype real realNet; 3 | endpackage : NetsPkg 4 | module top(); 5 | interconnect [0:1] iBus; 6 | lDriver l1(iBus[0]); 7 | rDriver r1(iBus[1]); 8 | rlMod m1(iBus); 9 | endmodule : top 10 | module lDriver(output wire logic out); 11 | endmodule : lDriver 12 | module rDriver 13 | import NetsPkg::*; 14 | (output realNet out); 15 | endmodule : rDriver 16 | module rlMod(input interconnect [0:1] iBus); 17 | lMod l1(iBus[0]); 18 | rMod r1(iBus[1]); 19 | endmodule : rlMod 20 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p95/cmp.sv: -------------------------------------------------------------------------------- 1 | module cmp #(parameter real hyst = 0.65) 2 | (input wire logic [0:1] inA, 3 | input logic rst, 4 | output logic out); 5 | initial out = 1'b0; 6 | always @(inA, rst) begin 7 | if (rst) out <= 1'b0; 8 | else if (inA[0] & ~inA[1]) out <= 1'b1; 9 | else out <= 1'b0; 10 | end 11 | endmodule : cmp 12 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p95/cmp.svr: -------------------------------------------------------------------------------- 1 | module cmp 2 | import NetsPkg::*; 3 | #(parameter real hyst = 0.65) 4 | (input realNet [0:1] inA, 5 | input logic rst, 6 | output logic out); 7 | timeunit 1ns / 1ps; 8 | real updatePeriod = 100.0; 9 | initial out = 1'b0; 10 | always #updatePeriod begin 11 | if (rst) out <= 1'b0; 12 | else if (inA[0] > inA[1]) out <= 1'b1; 13 | else if (inA[0] < inA[1] - hyst) out <= 1'b0; 14 | end 15 | endmodule : cmp 16 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p95/driver.sv: -------------------------------------------------------------------------------- 1 | module driver #(parameter int delay = 30, 2 | int iterations = 256) 3 | (output wire logic [0:1] out); 4 | timeunit 1ns / 1ps; 5 | logic [0:1] outvar; 6 | assign out = outvar; 7 | initial begin 8 | outvar = '0; 9 | for (int i = 0; i < iterations; i++) 10 | #delay outvar++; 11 | end 12 | endmodule : driver 13 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p95/driver.svr: -------------------------------------------------------------------------------- 1 | module driver 2 | import NetsPkg::*; 3 | #(parameter int delay = 30, 4 | int iterations = 256) 5 | (output realNet [0:1] out); 6 | timeunit 1ns / 1ps; 7 | real outR[1:0]; 8 | assign out = outR; 9 | initial begin 10 | outR[0] = 0.0; 11 | outR[1] = 3.3; 12 | for (int i = 0; i < iterations; i++) begin 13 | #delay outR[0] += 0.2; 14 | outR[1] -= 0.2; 15 | end 16 | end 17 | endmodule : driver 18 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p95/lib.map: -------------------------------------------------------------------------------- 1 | library realLib *.svr; 2 | library logicLib *.sv; 3 | config cfgReal; 4 | design logicLib.top; 5 | default liblist realLib logicLib; 6 | endconfig 7 | config cfgLogic; 8 | design logicLib.top; 9 | default liblist logicLib realLib; 10 | endconfig 11 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p95/nets.pkg: -------------------------------------------------------------------------------- 1 | package NetsPkg; 2 | nettype real realNet; 3 | endpackage : NetsPkg 4 | -------------------------------------------------------------------------------- /tests/sv_test/std2017/p95/top.sv: -------------------------------------------------------------------------------- 1 | module top(); 2 | interconnect [0:3] [0:1] aBus; 3 | logic [0:3] dBus; 4 | driver driverArray[0:3](aBus); 5 | cmp cmpArray[0:3](aBus,rst,dBus); 6 | endmodule : top 7 | -------------------------------------------------------------------------------- /tests/test_notebook.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # -*- coding: utf-8 -*- 3 | 4 | import os 5 | import unittest 6 | 7 | from tests.notebook_exec import run_notebook 8 | 9 | 10 | ROOT = os.path.join(os.path.dirname(__file__), "..") 11 | 12 | 13 | class NotebookTC(unittest.TestCase): 14 | 15 | def test01_parse_and_dump(self): 16 | f = os.path.join(ROOT, 'notebooks', '01_parse_and_dump.ipynb') 17 | _, errors = run_notebook(f) 18 | self.assertEqual(errors, []) 19 | 20 | 21 | if __name__ == '__main__': 22 | unittest.main() 23 | -------------------------------------------------------------------------------- /tests/verilog/define.v: -------------------------------------------------------------------------------- 1 | // Examples of `define text macros 2 | `define MY_NUMBER 5 3 | `define MY_STRING "Hello world!" 4 | `define ADD2PLUS2 2 + 2 5 | `define ADD5(RESULT, SOURCE) \ 6 | RESULT = SOURCE + 5; \ 7 | $display("Inside ADD5 macro. Scope is %m"); 8 | 9 | module test; 10 | 11 | reg [7:0] a, b; 12 | 13 | initial begin 14 | $display(`MY_NUMBER); 15 | $display(`MY_STRING); 16 | $display(2 + 2); 17 | $display(`ADD2PLUS2); 18 | 19 | a = 1; 20 | `ifdef MY_FEATURE 21 | `ADD5(b, a) 22 | $display("a:%0d, b:%0d", a, b); 23 | `else 24 | $display("No feature"); 25 | `endif 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /tests/verilog/directive_verilogpp.v: -------------------------------------------------------------------------------- 1 | `celldefine 2 | 3 | `endcelldefine 4 | 5 | `default_nettype wire 6 | 7 | `define MYDEFINE "is the best!" 8 | 9 | `undef MYDEFINE 10 | 11 | `include "fifo_rx.v" 12 | 13 | `resetall 14 | 15 | `line 14 "noexistingfile.v" 2 16 | 17 | `timescale 1 ns / 1ps 18 | 19 | `unconnected_drive pull1 20 | 21 | `nounconnected_drive 22 | -------------------------------------------------------------------------------- /tests/verilog/expected/define.v: -------------------------------------------------------------------------------- 1 | // Examples of `define text macros 2 | module test; 3 | reg[7:0] a; 4 | reg[7:0] b; 5 | initial begin 6 | $display(5); 7 | $display("Hello world!"); 8 | $display(2 + 2); 9 | $display(2 + 2); 10 | a = 1; 11 | $display("No feature"); 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/verilog/expected/function_non_ansi.v: -------------------------------------------------------------------------------- 1 | module module0; 2 | function clkout_duty_chk ( 3 | input integer CLKOUT_DIVIDE, 4 | input real CLKOUT_DUTY_CYCLE, 5 | input [160:0] CLKOUT_DUTY_CYCLE_N 6 | ); 7 | integer step_tmp; 8 | real CLK_DUTY_CYCLE_MIN; 9 | real CLK_DUTY_CYCLE_MAX; 10 | real CLK_DUTY_CYCLE_STEP; 11 | real CLK_DUTY_CYCLE_MIN_rnd; 12 | reg clk_duty_tmp_int; 13 | begin 14 | clkout_duty_chk = 1'b1; 15 | end 16 | endfunction 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/verilog/expected/generate_for.v: -------------------------------------------------------------------------------- 1 | module top; 2 | wire[2:0] out; 3 | wire[2:0] out1; 4 | wire[2:0] out2; 5 | genvar i; 6 | generate for (i = 0; i < 3; i = i + 1) 7 | assign out[i] = i; 8 | endgenerate 9 | 10 | generate for (i = 0; i < 3; i = i + 1) 11 | assign out1[i] = i; 12 | endgenerate 13 | 14 | generate for (i = 0; i < 3; i = i + 1) begin: test1 15 | assign out2[i] = i; 16 | end 17 | endgenerate 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests/verilog/expected/macro.v: -------------------------------------------------------------------------------- 1 | module macro ( 2 | input wire clock, 3 | input wire reset 4 | ); 5 | wire[31:0] up_data; 6 | wire[31:0] down_data; 7 | assign down_data = up_data * up_data + (4 + 8) * (4 + 8); 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests/verilog/expected/rom_using_file.v: -------------------------------------------------------------------------------- 1 | // http://www.asic-world.com/code/hdl_models/rom_using_file.v 2 | //----------------------------------------------------- 3 | // Design Name : rom_using_file 4 | // File Name : rom_using_file.v 5 | // Function : ROM using readmemh 6 | // Coder : Deepak Kumar Tala 7 | //----------------------------------------------------- 8 | module rom_using_file ( 9 | input wire[7:0] address, 10 | // Address input 11 | output wire[7:0] data, 12 | // Data output 13 | input wire read_en, 14 | // Read Enable 15 | input wire ce 16 | ); 17 | reg[7:0] mem[0:255]; 18 | assign data = (ce && read_en) ? mem[address] : 8'b0; 19 | initial 20 | $readmemb("memory.list", mem); 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests/verilog/function_non_ansi.v: -------------------------------------------------------------------------------- 1 | 2 | module module0 (); 3 | 4 | function clkout_duty_chk; 5 | input CLKOUT_DIVIDE; 6 | input CLKOUT_DUTY_CYCLE; 7 | input reg [160:0] CLKOUT_DUTY_CYCLE_N; 8 | integer CLKOUT_DIVIDE, step_tmp; 9 | real CLKOUT_DUTY_CYCLE; 10 | real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP; 11 | real CLK_DUTY_CYCLE_MIN_rnd; 12 | reg clk_duty_tmp_int; 13 | begin 14 | clkout_duty_chk = 1'b1; 15 | end 16 | endfunction 17 | 18 | endmodule -------------------------------------------------------------------------------- /tests/verilog/generate_for.v: -------------------------------------------------------------------------------- 1 | module top(); 2 | wire[2:0] out; 3 | wire[2:0] out1; 4 | wire[2:0] out2; 5 | genvar i; 6 | 7 | generate 8 | for(i=0;i<3;i=i+1) 9 | assign out[i]=i; 10 | endgenerate 11 | 12 | generate 13 | for(i=0;i<3;i=i+1) 14 | begin 15 | assign out1[i]=i; 16 | end 17 | endgenerate 18 | 19 | generate 20 | for(i=0;i<3;i=i+1) 21 | begin:test1 22 | assign out2[i]=i; 23 | end 24 | endgenerate 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /tests/verilog/include.v: -------------------------------------------------------------------------------- 1 | `include "arbiter.v" 2 | `include "uart.v" -------------------------------------------------------------------------------- /tests/verilog/macro.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `define sqr( x ) (x * x) // comment0 4 | 5 | `define sum( a /* comment1 */ , b /* comment2 */ ) /* comment3 */ \ 6 | (a + b) 7 | 8 | `define sumsqr( 9 | a // comment4 10 | , 11 | b // comment5 12 | ) \ 13 | `sum ( \ 14 | `sqr(a) \ 15 | , \ 16 | `sqr(b) \ 17 | ) 18 | 19 | 20 | module macro(input clock, reset); 21 | 22 | wire [31:0] up_data; 23 | wire [31:0] down_data; 24 | 25 | assign down_data = `sumsqr( 26 | up_data /* comment6 */ 27 | , 28 | (4 + 8) /* 12 */ 29 | ); 30 | 31 | 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /tests/verilog/simple_subunit.v: -------------------------------------------------------------------------------- 1 | module subunit0(input a, 2 | output b 3 | ); 4 | 5 | assign b = a; 6 | endmodule 7 | 8 | module SimpleSubunit(input a, 9 | output b 10 | ); 11 | 12 | wire sig_subunit0_a; 13 | wire sig_subunit0_b; 14 | subunit0 subunit0_inst (.a(sig_subunit0_a), 15 | .b(sig_subunit0_b) 16 | ); 17 | 18 | 19 | assign b = sig_subunit0_b; 20 | assign sig_subunit0_a = a; 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests/verilog/test_verilog_primitives.v: -------------------------------------------------------------------------------- 1 | // Test Scenario to validate correct translation 2 | // Refer: https://github.com/Nic30/hdlConvertor/issues/173 3 | 4 | module dummy(c, a, b); 5 | output c; 6 | input a, b; 7 | and a1(c, a, b); 8 | endmodule 9 | 10 | module d2(y, a); 11 | output y; 12 | input a; 13 | 14 | not n1 (y, a); 15 | endmodule 16 | 17 | module example (a, b, c, d); 18 | input a, b, c; 19 | output d; 20 | 21 | wire tmp; 22 | wire tmp2; 23 | and a1 (tmp, a, b); 24 | dummy du(tmp2, b, c); 25 | or o1 (d, tmp, tmp2); 26 | endmodule 27 | -------------------------------------------------------------------------------- /tests/verilog/timescale.v: -------------------------------------------------------------------------------- 1 | // https://opencores.org/websvn/filedetails?repname=aes_core&path=%2Faes_core%2Ftrunk%2Frtl%2Fverilog%2Ftimescale.v 2 | `timescale 1ns / 10ps -------------------------------------------------------------------------------- /tests/vhdl/arch_signal_declr_identifier_list.vhd: -------------------------------------------------------------------------------- 1 | architecture arch of module is 2 | signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0'); 3 | begin 4 | end architecture arch; 5 | -------------------------------------------------------------------------------- /tests/vhdl/arch_with_assig.vhd: -------------------------------------------------------------------------------- 1 | architecture arch of module is 2 | begin 3 | data <= i_data and i_mask; 4 | end architecture arch; -------------------------------------------------------------------------------- /tests/vhdl/association_open.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity test_module is 5 | generic ( 6 | a : integer 7 | ); 8 | port ( 9 | clk : std_logic; 10 | b : in std_logic := '0' 11 | ); 12 | end entity; 13 | 14 | entity test_entity_top is 15 | end entity; 16 | 17 | architecture test of test_entity_top is 18 | begin 19 | test_inst : entity work.test_module 20 | generic map ( 21 | a => 4 22 | ) 23 | port map ( 24 | clk => clk, 25 | b => open 26 | ); 27 | end architecture; -------------------------------------------------------------------------------- /tests/vhdl/call.vhd: -------------------------------------------------------------------------------- 1 | architecture arch of module is 2 | begin 3 | data <= i_data(i_data'range) and i_mask; 4 | end architecture arch; -------------------------------------------------------------------------------- /tests/vhdl/direct_instantiation.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity test_module is 5 | generic ( 6 | a : integer 7 | ); 8 | port ( 9 | clk : std_logic 10 | ); 11 | end entity; 12 | 13 | entity test_entity_top is 14 | end entity; 15 | 16 | architecture test of test_entity_top is 17 | begin 18 | test_inst : entity work.test_module 19 | generic map ( 20 | a => 4 21 | ) 22 | port map ( 23 | clk => clk 24 | ); 25 | end architecture; -------------------------------------------------------------------------------- /tests/vhdl/entity_declarative_item.vhd: -------------------------------------------------------------------------------- 1 | entity entity_declarative_item is 2 | port ( Addr: in Word; 3 | Data: out Word; 4 | Sel: in Bit); 5 | type Instruction is array (1 to 5) of Natural; 6 | type Program is array (Natural range <>) of Instruction; 7 | use Work.OpCodes.all, Work.RegisterNames.all; 8 | constant ROM_Code: Program := 9 | ( 10 | (STM, R14, R12, 12, R13), 11 | (LD, R7, 32, 0, R1 ), 12 | (BAL, R14, 0, 0, R7 ) 13 | ); 14 | end entity; 15 | -------------------------------------------------------------------------------- /tests/vhdl/enum.vhd: -------------------------------------------------------------------------------- 1 | architecture EXAMPLE of ENUMERATION is 2 | -- http://vhdl.renerta.com/mobile/source/vhd00026.htm 3 | type e1 is (L, H); 4 | type e2 is ('0', '1'); 5 | type e3 is ('0', '1', L, H); 6 | type e4 is (Init, Read, Decode, Execute, Write); 7 | 8 | signal s : e1; 9 | begin 10 | s <= L; 11 | end; 12 | -------------------------------------------------------------------------------- /tests/vhdl/expected/arch_signal_declr_identifier_list.vhd: -------------------------------------------------------------------------------- 1 | ARCHITECTURE arch OF module IS 2 | SIGNAL Reg1 : signed(7 DOWNTO 0) := (OTHERS => '0'); 3 | SIGNAL Reg2 : signed(7 DOWNTO 0) := (OTHERS => '0'); 4 | SIGNAL Reg3 : signed(7 DOWNTO 0) := (OTHERS => '0'); 5 | BEGIN 6 | END ARCHITECTURE; 7 | -------------------------------------------------------------------------------- /tests/vhdl/expected/arch_with_assig.vhd: -------------------------------------------------------------------------------- 1 | ARCHITECTURE arch OF module IS 2 | BEGIN 3 | data <= i_data AND i_mask; 4 | END ARCHITECTURE; 5 | -------------------------------------------------------------------------------- /tests/vhdl/expected/array.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | USE ieee.numeric_std.ALL; 4 | ENTITY test_entity_top IS 5 | END ENTITY; 6 | 7 | ARCHITECTURE test OF test_entity_top IS 8 | TYPE Real_Matrix IS ARRAY (1 TO 10) OF REAL; 9 | TYPE BYTE IS ARRAY (0 TO 7) OF BIT; 10 | TYPE Log_4_Vector IS ARRAY (POSITIVE RANGE 1 TO 8, POSITIVE RANGE 1 TO 2) OF Log_4; 11 | TYPE X IS (LOW, HIGH); 12 | TYPE DATA_BUS IS ARRAY (0 TO 7, X) OF BIT; 13 | TYPE Real_Matrix IS ARRAY (POSITIVE RANGE <>) OF Real; 14 | VARIABLE Real_Matrix_Object : Real_Matrix(1 TO 8); 15 | TYPE Log_4_Vector IS ARRAY (NATURAL RANGE <>, POSITIVE RANGE <>) OF Log_4; 16 | VARIABLE L4_Object : Log_4_Vector(0 TO 7, 1 TO 2); 17 | BEGIN 18 | END ARCHITECTURE; 19 | -------------------------------------------------------------------------------- /tests/vhdl/expected/association_open.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | ENTITY test_module IS 4 | GENERIC( 5 | a : integer 6 | ); 7 | PORT( 8 | clk : IN std_logic; 9 | b : IN std_logic := '0' 10 | ); 11 | END ENTITY; 12 | 13 | ENTITY test_entity_top IS 14 | END ENTITY; 15 | 16 | ARCHITECTURE test OF test_entity_top IS 17 | BEGIN 18 | test_inst: ENTITY work.test_module GENERIC MAP( 19 | a => 4 20 | ) PORT MAP( 21 | clk => clk, 22 | b => OPEN 23 | ); 24 | END ARCHITECTURE; 25 | -------------------------------------------------------------------------------- /tests/vhdl/expected/call.vhd: -------------------------------------------------------------------------------- 1 | ARCHITECTURE arch OF module IS 2 | BEGIN 3 | data <= i_data(i_data'range) AND i_mask; 4 | END ARCHITECTURE; 5 | -------------------------------------------------------------------------------- /tests/vhdl/expected/direct_instantiation.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | ENTITY test_module IS 4 | GENERIC( 5 | a : integer 6 | ); 7 | PORT( 8 | clk : IN std_logic 9 | ); 10 | END ENTITY; 11 | 12 | ENTITY test_entity_top IS 13 | END ENTITY; 14 | 15 | ARCHITECTURE test OF test_entity_top IS 16 | BEGIN 17 | test_inst: ENTITY work.test_module GENERIC MAP( 18 | a => 4 19 | ) PORT MAP( 20 | clk => clk 21 | ); 22 | END ARCHITECTURE; 23 | -------------------------------------------------------------------------------- /tests/vhdl/expected/entity_declarative_item.vhd: -------------------------------------------------------------------------------- 1 | ENTITY entity_declarative_item IS 2 | PORT( 3 | Addr : IN Word; 4 | Data : OUT Word; 5 | Sel : IN Bit 6 | ); 7 | TYPE Instruction IS ARRAY (1 TO 5) OF Natural; 8 | TYPE Program IS ARRAY (Natural RANGE <>) OF Instruction; 9 | USE Work.OpCodes.ALL; 10 | USE Work.RegisterNames.ALL; 11 | CONSTANT ROM_Code : Program := (( 12 | STM, 13 | R14, 14 | R12, 15 | 12, 16 | R13), ( 17 | LD, 18 | R7, 19 | 32, 20 | 0, 21 | R1), ( 22 | BAL, 23 | R14, 24 | 0, 25 | 0, 26 | R7)); 27 | END ENTITY; 28 | 29 | -------------------------------------------------------------------------------- /tests/vhdl/expected/enum.vhd: -------------------------------------------------------------------------------- 1 | ARCHITECTURE EXAMPLE OF ENUMERATION IS 2 | TYPE e1 IS (L, H); 3 | TYPE e2 IS ('0', '1'); 4 | TYPE e3 IS ('0', '1', L, H); 5 | TYPE e4 IS (Init, Read, Decode, Execute, Write); 6 | SIGNAL s : e1; 7 | BEGIN 8 | s <= L; 9 | END ARCHITECTURE; 10 | -------------------------------------------------------------------------------- /tests/vhdl/expected/for_in.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | USE ieee.numeric_std.ALL; 4 | ARCHITECTURE behave OF Example_For_Loop IS 5 | SIGNAL r_Shift_With_For : std_logic_vector(3 DOWNTO 0) := X"1"; 6 | SIGNAL r_Shift_Regular : std_logic_vector(3 DOWNTO 0) := X"1"; 7 | BEGIN 8 | p_Shift_With_For: PROCESS(i_Clock) 9 | BEGIN 10 | IF rising_edge(i_Clock) THEN 11 | FOR ii IN 0 TO 2 LOOP 12 | r_Shift_With_For(ii + 1) <= r_Shift_With_For(ii); 13 | END LOOP; 14 | END IF; 15 | END PROCESS; 16 | END ARCHITECTURE; 17 | -------------------------------------------------------------------------------- /tests/vhdl/expected/function_noarg.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | ENTITY test_entity_top IS 4 | END ENTITY; 5 | 6 | ARCHITECTURE test OF test_entity_top IS 7 | FUNCTION test_func RETURN integer 8 | IS 9 | BEGIN 10 | RETURN 42; 11 | END FUNCTION; 12 | CONSTANT test_const : integer := test_func; 13 | BEGIN 14 | END ARCHITECTURE; 15 | -------------------------------------------------------------------------------- /tests/vhdl/expected/generate_for.vhd: -------------------------------------------------------------------------------- 1 | ARCHITECTURE GEN OF REG_BANK IS 2 | COMPONENT REG IS 3 | PORT( 4 | D : IN std_ulogic; 5 | CLK : IN std_ulogic; 6 | RESET : IN std_ulogic; 7 | Q : OUT std_ulogic 8 | ); 9 | END COMPONENT; 10 | BEGIN 11 | GEN_REG: FOR I IN 0 TO 3 GENERATE 12 | REGX: REG PORT MAP( 13 | DIN(I), 14 | CLK, 15 | RESET, 16 | DOUT(I) 17 | ); 18 | END GENERATE; 19 | END ARCHITECTURE; 20 | -------------------------------------------------------------------------------- /tests/vhdl/expected/package_enum.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY IEEE; 2 | PACKAGE CONFIG IS 3 | TYPE AddersType IS (RCA, CLA, CSA, CSA_CLA); 4 | END PACKAGE; 5 | 6 | -------------------------------------------------------------------------------- /tests/vhdl/expected/ram.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | -- https://surf-vhdl.com/vhdl-syntax-web-course-surf-vhdl/vhdl-generics/ 4 | ENTITY RAM IS 5 | GENERIC( 6 | data_width : integer := 64; 7 | addr_width : integer := 12; 8 | Taa : time := 50; 9 | Toe : time := 40 10 | ); 11 | PORT( 12 | oeb : IN std_logic; 13 | wrb : IN std_logic; 14 | csb : IN std_logic; 15 | data : INOUT std_logic_vector(data_width - 1 DOWNTO 0); 16 | addr : IN std_logic_vector(addr_width - 1 DOWNTO 0) 17 | ); 18 | END ENTITY; 19 | 20 | -------------------------------------------------------------------------------- /tests/vhdl/expected/record_in_record.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | ARCHITECTURE behave OF example_record IS 4 | TYPE register_0_t IS RECORD 5 | pll_lock : std_logic; 6 | cnt_limit : std_logic_vector(9 DOWNTO 0); 7 | latency : std_logic_vector(20 DOWNTO 0); 8 | END RECORD; 9 | TYPE register_record_t IS RECORD 10 | register_0 : register_0_t; 11 | register_1 : register_1_t; 12 | END RECORD; 13 | SIGNAL r_WR_DATA : register_record_t; 14 | BEGIN 15 | regs.register_0.pll_lock <= '1'; 16 | END ARCHITECTURE; 17 | -------------------------------------------------------------------------------- /tests/vhdl/expected/stm_exit.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | ENTITY test_entity_top IS 4 | END ENTITY; 5 | 6 | ARCHITECTURE test OF test_entity_top IS 7 | BEGIN 8 | PROCESS 9 | BEGIN 10 | OuterLoop: LOOP 11 | FOR i IN 3 TO 5 LOOP 12 | IF i = 5 THEN 13 | EXIT OuterLoop; 14 | END IF; 15 | END LOOP; 16 | END LOOP; 17 | END PROCESS; 18 | END ARCHITECTURE; 19 | -------------------------------------------------------------------------------- /tests/vhdl/expected/stm_nop.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | ARCHITECTURE rtl OF mux4_case IS 4 | BEGIN 5 | p_mux: PROCESS(a, b, c, d, s) 6 | BEGIN 7 | CASE s IS 8 | WHEN "00" => 9 | m <= a; 10 | WHEN "01" => 11 | m <= b; 12 | WHEN "10" => 13 | m <= c; 14 | WHEN OTHERS => 15 | NULL; 16 | END CASE; 17 | END PROCESS; 18 | END ARCHITECTURE; 19 | -------------------------------------------------------------------------------- /tests/vhdl/expected/subtype.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | USE ieee.numeric_std.ALL; 4 | ENTITY test_entity_top IS 5 | END ENTITY; 6 | 7 | ARCHITECTURE test OF test_entity_top IS 8 | SUBTYPE DIGITS IS INTEGER RANGE 0 TO 9; 9 | FUNCTION RESOLVE_VALUE (SIGNAL anonymous : BIT_VECTOR) RETURN BIT; 10 | SUBTYPE BIT_NEW IS RESOLVE_VALUE BIT; 11 | BEGIN 12 | END ARCHITECTURE; 13 | -------------------------------------------------------------------------------- /tests/vhdl/expected/type_attribute_designator.vhd: -------------------------------------------------------------------------------- 1 | ARCHITECTURE Behavioral OF file_read IS 2 | BEGIN 3 | PROCESS(ALL) 4 | BEGIN 5 | write(buf_out, string'("This is an example offormatted IO")); 6 | writeline(outfile, buf_out); 7 | write(buf_out, string'("Enter the parameter")); 8 | writeline(outfile, buf_out); 9 | readline(infile, buf_in); 10 | read(buf_in, count); 11 | write(buf_out, string'("The parameter is=")); 12 | write(buf_out, count); 13 | writeline(outfile, buf_out); 14 | file_close(outfile); 15 | WAIT; 16 | END PROCESS; 17 | END ARCHITECTURE; 18 | -------------------------------------------------------------------------------- /tests/vhdl/expected/with_select.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.ALL; 3 | -- https://www.nandland.com/vhdl/examples/example-select.html 4 | ENTITY ex_select IS 5 | END ENTITY; 6 | 7 | ARCHITECTURE behave OF ex_select IS 8 | SIGNAL r_Index : integer := 2; 9 | SIGNAL w_One_Hot : std_logic_vector(3 DOWNTO 0); 10 | BEGIN 11 | CASE r_Index IS 12 | WHEN 0 => 13 | w_One_Hot <= "0000"; 14 | WHEN 1 => 15 | w_One_Hot <= "0001"; 16 | WHEN 2 => 17 | w_One_Hot <= "0010"; 18 | WHEN 3 => 19 | w_One_Hot <= "0100"; 20 | WHEN 4 => 21 | w_One_Hot <= "1000"; 22 | WHEN OTHERS => 23 | w_One_Hot <= "0000"; 24 | END CASE; 25 | END ARCHITECTURE; 26 | -------------------------------------------------------------------------------- /tests/vhdl/for_in.vhd: -------------------------------------------------------------------------------- 1 | -- https://www.nandland.com/vhdl/examples/example-for-loop.html 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | architecture behave of Example_For_Loop is 7 | 8 | signal r_Shift_With_For : std_logic_vector(3 downto 0) := X"1"; 9 | signal r_Shift_Regular : std_logic_vector(3 downto 0) := X"1"; 10 | 11 | begin 12 | 13 | -- Creates a Left Shift using a For Loop 14 | p_Shift_With_For : process (i_Clock) 15 | begin 16 | if rising_edge(i_Clock) then 17 | for ii in 0 to 2 loop 18 | r_Shift_With_For(ii+1) <= r_Shift_With_For(ii); 19 | end loop; -- ii 20 | end if; 21 | end process; 22 | 23 | end behave; 24 | -------------------------------------------------------------------------------- /tests/vhdl/function_noarg.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity test_entity_top is 5 | end entity; 6 | 7 | architecture test of test_entity_top is 8 | function test_func 9 | return integer is 10 | begin 11 | return 42; 12 | end function; 13 | constant test_const : integer := test_func; 14 | begin 15 | end architecture; -------------------------------------------------------------------------------- /tests/vhdl/generate_for.vhd: -------------------------------------------------------------------------------- 1 | architecture GEN of REG_BANK is 2 | component REG 3 | port(D,CLK,RESET : in std_ulogic; 4 | Q : out std_ulogic); 5 | end component; 6 | begin 7 | GEN_REG: 8 | for I in 0 to 3 generate 9 | REGX : REG port map 10 | (DIN(I), CLK, RESET, DOUT(I)); 11 | end generate GEN_REG; 12 | end GEN; 13 | -------------------------------------------------------------------------------- /tests/vhdl/malformed.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity malformed is 5 | port ( 6 | i0); 7 | end sadfas%; 8 | 9 | architecture Behavioral of multiplexer4_1 is 10 | begin 11 | 12 | process(i0,i1,i2,i3,sel, *) 13 | begin 14 | case sel is 15 | when "00" => bitout <= i0; 16 | when "01" => bitout <= i1; 17 | << <<; 18 | when others => bitout <= i3; 19 | end case; 20 | end process; 21 | 22 | end Behavioral; 23 | 24 | -------------------------------------------------------------------------------- /tests/vhdl/mux.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity multiplexer4_1 is 5 | port ( 6 | i0 : in std_logic; 7 | i1 : in std_logic; 8 | i2 : in std_logic; 9 | i3 : in std_logic; 10 | sel : in std_logic_vector(1 downto 0); 11 | bitout : out std_logic 12 | ); 13 | end multiplexer4_1; 14 | 15 | architecture Behavioral of multiplexer4_1 is 16 | begin 17 | 18 | process(i0,i1,i2,i3,sel) 19 | begin 20 | case sel is 21 | when "00" => bitout <= i0; 22 | when "01" => bitout <= i1; 23 | when "10" => bitout <= i2; 24 | when others => bitout <= i3; 25 | end case; 26 | end process; 27 | 28 | end Behavioral; 29 | 30 | -------------------------------------------------------------------------------- /tests/vhdl/mux2i.vhd: -------------------------------------------------------------------------------- 1 | -- https://www.doulos.com/knowhow/vhdl_designers_guide/components_and_port_maps/ 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.all; 4 | 5 | entity MUX2I is 6 | port (SEL, A, B: in STD_LOGIC; 7 | F : out STD_LOGIC); 8 | end; 9 | 10 | architecture STRUCTURE of MUX2I is 11 | 12 | component INV 13 | port (A: in STD_LOGIC; 14 | F: out STD_LOGIC); 15 | end component; 16 | 17 | component AOI 18 | port (A, B, C, D: in STD_LOGIC; 19 | F : out STD_LOGIC); 20 | end component; 21 | 22 | signal SELB: STD_LOGIC; 23 | 24 | begin 25 | G1: INV port map (SEL, SELB); 26 | G2: AOI port map (SEL, A, SELB, B, F); 27 | end; -------------------------------------------------------------------------------- /tests/vhdl/package_array_const.vhd: -------------------------------------------------------------------------------- 1 | package array_const_pkg is 2 | constant CONST_ARRAY : externally_defined_array_t 3 | := ( 4 | X"00000001", 5 | X"00000002", 6 | X"00000003", 7 | X"00000004" 8 | ); 9 | end package; 10 | -------------------------------------------------------------------------------- /tests/vhdl/package_component.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_arith.all; 4 | use ieee.std_logic_unsigned.all; 5 | 6 | package components_pkg is 7 | 8 | component demo is 9 | generic ( 10 | GENERIC1: boolean := false; 11 | GENERIC2: integer := 100 12 | ); 13 | port ( 14 | a, b : in std_ulogic := '1'; 15 | c, d : out std_ulogic_vector(7 downto 0); 16 | e, f : inout unsigned(7 downto 0) 17 | ); 18 | end component; 19 | end components_pkg; 20 | -------------------------------------------------------------------------------- /tests/vhdl/package_enum.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | package CONFIG is 4 | TYPE AddersType is (RCA, CLA, CSA, CSA_CLA); 5 | end package ; -------------------------------------------------------------------------------- /tests/vhdl/package_instance.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | package fixed_pkg is new IEEE.fixed_generic_pkg 4 | generic map ( 5 | fixed_round_style => IEEE.fixed_float_types.fixed_round, 6 | fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate, 7 | fixed_guard_bits => 3, 8 | no_warning => false 9 | ); -------------------------------------------------------------------------------- /tests/vhdl/ram.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | -- https://surf-vhdl.com/vhdl-syntax-web-course-surf-vhdl/vhdl-generics/ 4 | entity RAM is 5 | generic( 6 | data_width : integer := 64; 7 | addr_width : integer := 12; 8 | Taa : time := 50; 9 | Toe : time := 40); 10 | port( 11 | oeb, wrb, csb : in std_logic; 12 | data : inout std_logic_vector(data_width-1 downto 0); 13 | addr : in std_logic_vector(addr_width-1 downto 0)); 14 | end RAM; 15 | -------------------------------------------------------------------------------- /tests/vhdl/record_in_record.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | architecture behave of example_record is 5 | type register_0_t is record 6 | pll_lock : std_logic; 7 | cnt_limit : std_logic_vector(9 downto 0); 8 | latency : std_logic_vector(20 downto 0); 9 | end record; 10 | 11 | type register_record_t is record 12 | register_0 : register_0_t; 13 | register_1 : register_1_t; 14 | end record; 15 | 16 | signal r_WR_DATA : register_record_t; 17 | begin 18 | regs.register_0.pll_lock <= '1'; 19 | end architecture; 20 | 21 | -------------------------------------------------------------------------------- /tests/vhdl/std2008/units.vhd: -------------------------------------------------------------------------------- 1 | 2 | architecture test of test_ent is 3 | variable x: distance; 4 | variable y: duration; 5 | variable z: integer; 6 | begin 7 | process 8 | begin 9 | x := 5 Å + 13 ft - 27 inch; 10 | y := 3 ns + 5 min; 11 | z := ns / ps; 12 | x := z * mi; 13 | y := y/10; 14 | z := 39.34 inch / m; 15 | end process; 16 | end architecture; 17 | -------------------------------------------------------------------------------- /tests/vhdl/stm_exit.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity test_entity_top is 5 | end entity; 6 | 7 | architecture test of test_entity_top is 8 | begin 9 | process 10 | begin 11 | OuterLoop : loop 12 | for i in 3 to 5 loop 13 | if i = 5 then 14 | exit OuterLoop; 15 | end if; 16 | end loop; 17 | end loop; 18 | end process; 19 | end architecture; -------------------------------------------------------------------------------- /tests/vhdl/stm_nop.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all; 3 | 4 | architecture rtl of mux4_case is 5 | begin 6 | p_mux : process(a,b,c,d,s) 7 | begin 8 | case s is 9 | when "00" => m <= a; 10 | when "01" => m <= b; 11 | when "10" => m <= c; 12 | when others => null; 13 | end case; 14 | end process p_mux; 15 | end rtl; 16 | -------------------------------------------------------------------------------- /tests/vhdl/subtype.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity test_entity_top is 6 | end entity; 7 | 8 | architecture test of test_entity_top is 9 | -- http://vhdl.renerta.com/mobile/source/vhd00071.htm 10 | subtype DIGITS is INTEGER range 0 to 9; 11 | 12 | function RESOLVE_VALUE (anonymous: BIT_VECTOR) return BIT; 13 | subtype BIT_NEW is RESOLVE_VALUE BIT; 14 | begin 15 | end architecture; 16 | 17 | -------------------------------------------------------------------------------- /tests/vhdl/type_attribute_designator.vhd: -------------------------------------------------------------------------------- 1 | 2 | architecture Behavioral of file_read is 3 | begin 4 | 5 | process (all) 6 | begin 7 | 8 | L1: write(buf_out, string'("This is an example offormatted IO")); 9 | L2: writeline(outfile, buf_out); 10 | L3: write(buf_out, string'("Enter the parameter")); 11 | L4: writeline(outfile, buf_out); 12 | L5: readline(infile, buf_in); 13 | L6: read(buf_in, count); 14 | L7: write(buf_out, string'("The parameter is=")); 15 | L8: write(buf_out, count); 16 | L9: writeline(outfile, buf_out); 17 | L10: file_close(outfile); 18 | wait; 19 | end process; 20 | end architecturebeh; -------------------------------------------------------------------------------- /tests/vhdl/with_select.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | -- https://www.nandland.com/vhdl/examples/example-select.html 5 | entity ex_select is 6 | end ex_select; 7 | 8 | architecture behave of ex_select is 9 | 10 | signal r_Index : integer := 2; 11 | signal w_One_Hot : std_logic_vector(3 downto 0); 12 | 13 | begin 14 | 15 | with r_Index select 16 | w_One_Hot <= "0000" when 0, 17 | "0001" when 1, 18 | "0010" when 2, 19 | "0100" when 3, 20 | "1000" when 4, 21 | "0000" when others; 22 | 23 | end behave; --------------------------------------------------------------------------------