├── .circleci └── config.yml ├── .coveragerc ├── .gitignore ├── .readthedocs.yml ├── LICENSE ├── MANIFEST.in ├── README.md ├── doc ├── conf.py ├── index.rst └── requirements.doc.txt ├── hdlConvertorAst ├── __init__.py ├── hdlAst │ ├── __init__.py │ ├── _bases.py │ ├── _defs.py │ ├── _expr.py │ ├── _statements.py │ ├── _structural.py │ ├── _typeDefs.py │ └── utils.py ├── language.py ├── parse_hdlConvertor_json.py ├── py_ver_compatibility.py ├── to │ ├── __init__.py │ ├── basic_hdl_sim_model │ │ ├── __init__.py │ │ ├── _main.py │ │ ├── expr.py │ │ ├── keywords.py │ │ ├── stm.py │ │ └── utils.py │ ├── common.py │ ├── hdlUtils.py │ ├── hdl_ast_modifier.py │ ├── hdl_ast_visitor.py │ ├── hwt │ │ ├── __init__.py │ │ ├── _main.py │ │ ├── expr.py │ │ ├── keywords.py │ │ ├── stm.py │ │ └── utils.py │ ├── json.py │ ├── json_debug.py │ ├── systemc │ │ ├── __init__.py │ │ ├── _main.py │ │ ├── expr.py │ │ ├── keywords.py │ │ └── stm.py │ ├── verilog │ │ ├── __init__.py │ │ ├── constants.py │ │ ├── expr.py │ │ ├── keywords.py │ │ ├── stm.py │ │ ├── utils.py │ │ └── verilog2005.py │ └── vhdl │ │ ├── __init__.py │ │ ├── expr.py │ │ ├── keywords.py │ │ ├── stm.py │ │ └── vhdl2008.py └── translate │ ├── __init__.py │ ├── common │ ├── __init__.py │ ├── add_call_operator_for_call_without_parenthesis.py │ ├── discover_declarations.py │ ├── name_scope.py │ └── resolve_names.py │ ├── verilog_builtins.py │ ├── verilog_to_basic_hdl_sim_model │ ├── __init__.py │ ├── add_unique_labels_to_all_processes.py │ ├── apply_io_scope_to_signal_names.py │ ├── assignment_to_update_assignment.py │ ├── detect_compiletime_statements.py │ ├── discover_stm_outputs.py │ ├── elifs_to_if_then_else.py │ ├── main.py │ ├── utils.py │ ├── verilog_operands_to_basic_hdl_sim_model.py │ ├── verilog_resolve_types.py │ ├── verilog_types_to_basic_hdl_sim_model.py │ └── wrap_module_statements_to_processes.py │ ├── verilog_to_hwt │ ├── __init__.py │ ├── main.py │ ├── signal_assignments_to_call_op.py │ └── verilog_types_to_hwt.py │ ├── verilog_to_vhdl │ ├── __init__.py │ └── inject_process_sens_to_statements.py │ └── vhdl_to_verilog.py ├── pyproject.toml ├── setup.cfg └── tests ├── __init__.py ├── all.py ├── data ├── GroupOfBlockrams.Verilog.json ├── GroupOfBlockrams.Vhdl2008.json ├── GroupOfBlockrams.hwt.json ├── GroupOfBlockrams.sim_model.json ├── GroupOfBlockrams.systemc.json ├── README.md ├── Showcase0.Verilog.json ├── Showcase0.Vhdl2008.json ├── Showcase0.hwt.json ├── Showcase0.sim_model.json ├── Showcase0.systemc.json └── ref │ ├── GroupOfBlockrams.cpp │ ├── GroupOfBlockrams.hwt.py.txt │ ├── GroupOfBlockrams.sim_model.py.txt │ ├── GroupOfBlockrams.v │ ├── GroupOfBlockrams.vhd │ ├── Showcase0.cpp │ ├── Showcase0.hwt.py.txt │ ├── Showcase0.sim_model.py.txt │ ├── Showcase0.v │ └── Showcase0.vhd ├── fromJsonToHdl_test.py └── generate_test_data.py /.circleci/config.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/.circleci/config.yml -------------------------------------------------------------------------------- /.coveragerc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/.coveragerc -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/.gitignore -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/.readthedocs.yml -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/LICENSE -------------------------------------------------------------------------------- /MANIFEST.in: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/MANIFEST.in -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/README.md -------------------------------------------------------------------------------- /doc/conf.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/doc/conf.py -------------------------------------------------------------------------------- /doc/index.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/doc/index.rst -------------------------------------------------------------------------------- /doc/requirements.doc.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/doc/requirements.doc.txt -------------------------------------------------------------------------------- /hdlConvertorAst/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /hdlConvertorAst/hdlAst/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/hdlAst/__init__.py -------------------------------------------------------------------------------- /hdlConvertorAst/hdlAst/_bases.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/hdlAst/_bases.py -------------------------------------------------------------------------------- /hdlConvertorAst/hdlAst/_defs.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/hdlAst/_defs.py -------------------------------------------------------------------------------- /hdlConvertorAst/hdlAst/_expr.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/hdlAst/_expr.py -------------------------------------------------------------------------------- /hdlConvertorAst/hdlAst/_statements.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/hdlAst/_statements.py -------------------------------------------------------------------------------- /hdlConvertorAst/hdlAst/_structural.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/hdlAst/_structural.py -------------------------------------------------------------------------------- /hdlConvertorAst/hdlAst/_typeDefs.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/hdlAst/_typeDefs.py -------------------------------------------------------------------------------- /hdlConvertorAst/hdlAst/utils.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/hdlAst/utils.py -------------------------------------------------------------------------------- /hdlConvertorAst/language.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/language.py -------------------------------------------------------------------------------- /hdlConvertorAst/parse_hdlConvertor_json.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/parse_hdlConvertor_json.py -------------------------------------------------------------------------------- /hdlConvertorAst/py_ver_compatibility.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/py_ver_compatibility.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/__init__.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/basic_hdl_sim_model/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/basic_hdl_sim_model/__init__.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/basic_hdl_sim_model/_main.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/basic_hdl_sim_model/_main.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/basic_hdl_sim_model/expr.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/basic_hdl_sim_model/expr.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/basic_hdl_sim_model/keywords.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/basic_hdl_sim_model/keywords.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/basic_hdl_sim_model/stm.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/basic_hdl_sim_model/stm.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/basic_hdl_sim_model/utils.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/basic_hdl_sim_model/utils.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/common.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/common.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/hdlUtils.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/hdlUtils.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/hdl_ast_modifier.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/hdl_ast_modifier.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/hdl_ast_visitor.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/hdl_ast_visitor.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/hwt/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/hwt/__init__.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/hwt/_main.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/hwt/_main.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/hwt/expr.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/hwt/expr.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/hwt/keywords.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/hwt/keywords.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/hwt/stm.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/hwt/stm.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/hwt/utils.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/hwt/utils.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/json.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/json.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/json_debug.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/json_debug.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/systemc/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /hdlConvertorAst/to/systemc/_main.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/systemc/_main.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/systemc/expr.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/systemc/expr.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/systemc/keywords.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/systemc/keywords.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/systemc/stm.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/systemc/stm.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/verilog/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/verilog/__init__.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/verilog/constants.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/verilog/constants.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/verilog/expr.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/verilog/expr.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/verilog/keywords.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/verilog/keywords.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/verilog/stm.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/verilog/stm.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/verilog/utils.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/verilog/utils.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/verilog/verilog2005.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/verilog/verilog2005.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/vhdl/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/vhdl/__init__.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/vhdl/expr.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/vhdl/expr.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/vhdl/keywords.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/vhdl/keywords.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/vhdl/stm.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/vhdl/stm.py -------------------------------------------------------------------------------- /hdlConvertorAst/to/vhdl/vhdl2008.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/to/vhdl/vhdl2008.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/__init__.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/common/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /hdlConvertorAst/translate/common/add_call_operator_for_call_without_parenthesis.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/common/add_call_operator_for_call_without_parenthesis.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/common/discover_declarations.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/common/discover_declarations.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/common/name_scope.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/common/name_scope.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/common/resolve_names.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/common/resolve_names.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_builtins.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_builtins.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/__init__.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/add_unique_labels_to_all_processes.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/add_unique_labels_to_all_processes.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/apply_io_scope_to_signal_names.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/apply_io_scope_to_signal_names.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/assignment_to_update_assignment.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/assignment_to_update_assignment.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/detect_compiletime_statements.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/detect_compiletime_statements.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/discover_stm_outputs.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/discover_stm_outputs.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/elifs_to_if_then_else.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/elifs_to_if_then_else.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/main.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/main.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/utils.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/utils.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/verilog_operands_to_basic_hdl_sim_model.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/verilog_operands_to_basic_hdl_sim_model.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/verilog_resolve_types.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/verilog_resolve_types.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/verilog_types_to_basic_hdl_sim_model.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/verilog_types_to_basic_hdl_sim_model.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/wrap_module_statements_to_processes.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_basic_hdl_sim_model/wrap_module_statements_to_processes.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_hwt/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_hwt/__init__.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_hwt/main.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_hwt/main.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_hwt/signal_assignments_to_call_op.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_hwt/signal_assignments_to_call_op.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_hwt/verilog_types_to_hwt.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_hwt/verilog_types_to_hwt.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_vhdl/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /hdlConvertorAst/translate/verilog_to_vhdl/inject_process_sens_to_statements.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/verilog_to_vhdl/inject_process_sens_to_statements.py -------------------------------------------------------------------------------- /hdlConvertorAst/translate/vhdl_to_verilog.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/hdlConvertorAst/translate/vhdl_to_verilog.py -------------------------------------------------------------------------------- /pyproject.toml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/pyproject.toml -------------------------------------------------------------------------------- /setup.cfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/setup.cfg -------------------------------------------------------------------------------- /tests/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /tests/all.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/all.py -------------------------------------------------------------------------------- /tests/data/GroupOfBlockrams.Verilog.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/GroupOfBlockrams.Verilog.json -------------------------------------------------------------------------------- /tests/data/GroupOfBlockrams.Vhdl2008.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/GroupOfBlockrams.Vhdl2008.json -------------------------------------------------------------------------------- /tests/data/GroupOfBlockrams.hwt.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/GroupOfBlockrams.hwt.json -------------------------------------------------------------------------------- /tests/data/GroupOfBlockrams.sim_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/GroupOfBlockrams.sim_model.json -------------------------------------------------------------------------------- /tests/data/GroupOfBlockrams.systemc.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/GroupOfBlockrams.systemc.json -------------------------------------------------------------------------------- /tests/data/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/README.md -------------------------------------------------------------------------------- /tests/data/Showcase0.Verilog.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/Showcase0.Verilog.json -------------------------------------------------------------------------------- /tests/data/Showcase0.Vhdl2008.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/Showcase0.Vhdl2008.json -------------------------------------------------------------------------------- /tests/data/Showcase0.hwt.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/Showcase0.hwt.json -------------------------------------------------------------------------------- /tests/data/Showcase0.sim_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/Showcase0.sim_model.json -------------------------------------------------------------------------------- /tests/data/Showcase0.systemc.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/Showcase0.systemc.json -------------------------------------------------------------------------------- /tests/data/ref/GroupOfBlockrams.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/GroupOfBlockrams.cpp -------------------------------------------------------------------------------- /tests/data/ref/GroupOfBlockrams.hwt.py.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/GroupOfBlockrams.hwt.py.txt -------------------------------------------------------------------------------- /tests/data/ref/GroupOfBlockrams.sim_model.py.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/GroupOfBlockrams.sim_model.py.txt -------------------------------------------------------------------------------- /tests/data/ref/GroupOfBlockrams.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/GroupOfBlockrams.v -------------------------------------------------------------------------------- /tests/data/ref/GroupOfBlockrams.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/GroupOfBlockrams.vhd -------------------------------------------------------------------------------- /tests/data/ref/Showcase0.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/Showcase0.cpp -------------------------------------------------------------------------------- /tests/data/ref/Showcase0.hwt.py.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/Showcase0.hwt.py.txt -------------------------------------------------------------------------------- /tests/data/ref/Showcase0.sim_model.py.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/Showcase0.sim_model.py.txt -------------------------------------------------------------------------------- /tests/data/ref/Showcase0.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/Showcase0.v -------------------------------------------------------------------------------- /tests/data/ref/Showcase0.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/data/ref/Showcase0.vhd -------------------------------------------------------------------------------- /tests/fromJsonToHdl_test.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/fromJsonToHdl_test.py -------------------------------------------------------------------------------- /tests/generate_test_data.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nic30/hdlConvertorAst/HEAD/tests/generate_test_data.py --------------------------------------------------------------------------------