├── .circleci
    └── config.yml
├── .coveragerc
├── .gitignore
├── .readthedocs.yml
├── LICENSE
├── MANIFEST.in
├── README.md
├── doc
    ├── .gitignore
    ├── build.py
    ├── conf.py
    ├── index.rst
    └── requirements.doc.txt
├── pyDigitalWaveTools
    ├── __init__.py
    ├── json
    │   ├── __init__.py
    │   ├── value_format.py
    │   └── writer.py
    └── vcd
    │   ├── __init__.py
    │   ├── common.py
    │   ├── parser.py
    │   ├── value_format.py
    │   └── writer.py
├── setup.cfg
├── setup.py
└── tests
    ├── AxiRegTC_test_write.vcd
    ├── __init__.py
    ├── all.py
    ├── example0.json
    ├── example0.vcd
    ├── jsonWriter_test.py
    ├── multiscope.vcd
    ├── vcdParser_test.py
    ├── vcdWriter_test.py
    ├── verilog2005-sample0.vcd
    └── verilog2005-sample1.vcd


/.circleci/config.yml:
--------------------------------------------------------------------------------
 1 | version: 2.1
 2 | 
 3 | orbs:
 4 |   python: circleci/python@0.2.1
 5 |   py: nic30/python-all-in-1@0.3.0
 6 | 
 7 | jobs:
 8 |   install-test-deploy:
 9 |     executor: python/default
10 |     resource_class: small
11 |     steps:
12 |       - checkout
13 |       # - python/load-cache
14 |       - py/install-setup-py
15 |       # - python/save-cache
16 |       - py/test-and-coverage
17 |       - py/deploy-pypi-on-tag
18 | 
19 | workflows:
20 |   main:
21 |     jobs:
22 |       - install-test-deploy:
23 |           context:
24 |             - pypi
25 |           filters:
26 |             tags:
27 |               only: /.*/


--------------------------------------------------------------------------------
/.coveragerc:
--------------------------------------------------------------------------------
 1 | [run]
 2 | branch = True
 3 | 
 4 | source =
 5 |     pyDigitalWaveTools
 6 | 
 7 | [report]
 8 | exclude_lines =
 9 |     pragma: no cover
10 |     def __repr__
11 |     raise AssertionError
12 |     raise NotImplementedError
13 |     if __name__ == .__main__.:
14 | 


--------------------------------------------------------------------------------
/.gitignore:
--------------------------------------------------------------------------------
  1 | # Byte-compiled / optimized / DLL files
  2 | __pycache__/
  3 | *.py[cod]
  4 | *$py.class
  5 | 
  6 | # C extensions
  7 | *.so
  8 | 
  9 | # Distribution / packaging
 10 | .Python
 11 | env/
 12 | build/
 13 | develop-eggs/
 14 | dist/
 15 | downloads/
 16 | eggs/
 17 | .eggs/
 18 | lib/
 19 | lib64/
 20 | parts/
 21 | sdist/
 22 | var/
 23 | wheels/
 24 | *.egg-info/
 25 | .installed.cfg
 26 | *.egg
 27 | 
 28 | # PyInstaller
 29 | #  Usually these files are written by a python script from a template
 30 | #  before PyInstaller builds the exe, so as to inject date/other infos into it.
 31 | *.manifest
 32 | *.spec
 33 | 
 34 | # Installer logs
 35 | pip-log.txt
 36 | pip-delete-this-directory.txt
 37 | 
 38 | # Unit test / coverage reports
 39 | htmlcov/
 40 | .tox/
 41 | .coverage
 42 | .coverage.*
 43 | .cache
 44 | nosetests.xml
 45 | coverage.xml
 46 | *.cover
 47 | .hypothesis/
 48 | 
 49 | # Translations
 50 | *.mo
 51 | *.pot
 52 | 
 53 | # Django stuff:
 54 | *.log
 55 | local_settings.py
 56 | 
 57 | # Flask stuff:
 58 | instance/
 59 | .webassets-cache
 60 | 
 61 | # Scrapy stuff:
 62 | .scrapy
 63 | 
 64 | # Sphinx documentation
 65 | doc/_build/
 66 | 
 67 | # PyBuilder
 68 | target/
 69 | 
 70 | # Jupyter Notebook
 71 | .ipynb_checkpoints
 72 | 
 73 | # pyenv
 74 | .python-version
 75 | 
 76 | # celery beat schedule file
 77 | celerybeat-schedule
 78 | 
 79 | # SageMath parsed files
 80 | *.sage.py
 81 | 
 82 | # dotenv
 83 | .env
 84 | 
 85 | # virtualenv
 86 | .venv
 87 | venv/
 88 | ENV/
 89 | 
 90 | # Spyder project settings
 91 | .spyderproject
 92 | .spyproject
 93 | 
 94 | # Rope project settings
 95 | .ropeproject
 96 | 
 97 | # mkdocs documentation
 98 | /site
 99 | 
100 | # mypy
101 | .mypy_cache/
102 | 
103 | # eclipse project
104 | .project
105 | .pydevproject
106 | .settings/
107 | 
108 | 


--------------------------------------------------------------------------------
/.readthedocs.yml:
--------------------------------------------------------------------------------
 1 | version: 2
 2 | build:
 3 |   os: ubuntu-lts-latest
 4 |   tools:
 5 |     python: "3.12"
 6 |   apt_packages:
 7 |     - graphviz
 8 | python:
 9 |   install:
10 |     - requirements: doc/requirements.doc.txt
11 | 
12 | 


--------------------------------------------------------------------------------
/LICENSE:
--------------------------------------------------------------------------------
 1 | MIT License
 2 | 
 3 | Copyright (c) 2018 Nic30
 4 | 
 5 | Permission is hereby granted, free of charge, to any person obtaining a copy
 6 | of this software and associated documentation files (the "Software"), to deal
 7 | in the Software without restriction, including without limitation the rights
 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 9 | copies of the Software, and to permit persons to whom the Software is
10 | furnished to do so, subject to the following conditions:
11 | 
12 | The above copyright notice and this permission notice shall be included in all
13 | copies or substantial portions of the Software.
14 | 
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 | SOFTWARE.
22 | 


--------------------------------------------------------------------------------
/MANIFEST.in:
--------------------------------------------------------------------------------
1 | recursive-include pyDigitalWaveTools *.vcd
2 | include README.md
3 | include MANIFEST.in


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
 1 | # pyDigitalWaveTools
 2 | [![CircleCI](https://circleci.com/gh/Nic30/pyDigitalWaveTools.svg?style=svg)](https://circleci.com/gh/Nic30/pyDigitalWaveTools)
 3 | [![Coverage Status](https://coveralls.io/repos/github/Nic30/pyDigitalWaveTools/badge.svg?branch=master)](https://coveralls.io/github/Nic30/pyDigitalWaveTools?branch=master)
 4 | [![PyPI version](https://badge.fury.io/py/pyDigitalWaveTools.svg)](http://badge.fury.io/py/pyDigitalWaveTools)
 5 | [![Documentation Status](https://readthedocs.org/projects/pydigitalwavetools/badge/?version=latest)](http://pydigitalwavetools.readthedocs.io/en/latest/?badge=latest)
 6 | [![Python version](https://img.shields.io/pypi/pyversions/pyDigitalWaveTools.svg)](https://img.shields.io/pypi/pyversions/pyDigitalWaveTools.svg)
 7 | 
 8 | python library for operations with VCD and other digital wave files
 9 | 
10 | ## Feature list
11 | * parse VCD (std 2009) files to intermediate format
12 | * write VCD files, user specified formatters for user types, predefined formatters for vectors, bits and enum values
13 | * dump intermediate format as simple json
14 | 
15 | ## Hello pyDigitalWaveTools
16 | 
17 | Here is a simple example how to use the VCD parser:
18 | 
19 | ```python
20 | #!/usr/bin/env python3
21 | import json
22 | import sys
23 | from pyDigitalWaveTools.vcd.parser import VcdParser
24 | 
25 | if len(sys.argv) > 1:
26 |     fname = sys.argv[1]
27 | else:
28 |     print('Give me a vcd file to parse')
29 |     sys.exit(-1)
30 | 
31 | with open(fname) as vcd_file:
32 |     vcd = VcdParser()
33 |     vcd.parse(vcd_file)
34 |     data = vcd.scope.toJson()
35 |     print(json.dumps(data, indent=4, sort_keys=True))
36 | ```
37 | 
38 | 
39 | ## Output json format
40 | ```
41 | scope
42 | { "name": "<scope name>"
43 |   "children" : {"<children name>" : child}
44 | }
45 | 
46 | child can be scope or signal record
47 | 
48 | signal record
49 | { "name": "<signal name>"
50 |   "type": {"sigType": "<vcd signal type>",
51 |            "width": <bit width of signal (integer)>},
52 |   "data": [<data records>],
53 | }
54 | 
55 | data record format
56 | [<time (number)>, <value (string, format dependent on datatype)>]
57 | ```
58 | 
59 | 
60 | ## Related open source
61 | 
62 | * [verilog-vcd-parser](https://github.com/ben-marshall/verilog-vcd-parser) - Python, A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
63 | * [pyvcd](https://github.com/SanDisk-Open-Source/pyvcd) - Python, vcd writer, GTKWave config writer
64 | * [vcdvcd](https://github.com/cirosantilli/vcdvcd) - Python, vcd parser, dump pretty printer
65 | 


--------------------------------------------------------------------------------
/doc/.gitignore:
--------------------------------------------------------------------------------
1 | html
2 | _build/
3 | *.rst
4 | make.bat
5 | Makefile
6 | !index.rst
7 | 


--------------------------------------------------------------------------------
/doc/build.py:
--------------------------------------------------------------------------------
 1 | #!/usr/bin/env python3
 2 | # -*- coding: utf-8 -*-
 3 | 
 4 | """
 5 | An equivalent of `sphinx-build -b html . build`
 6 | Used for simple debugger execution for doc build.
 7 | """
 8 | 
 9 | from sphinx.cmd.build import build_main
10 | build_main(["-b", "html", ".", "_build"])
11 | 


--------------------------------------------------------------------------------
/doc/conf.py:
--------------------------------------------------------------------------------
 1 | # This file only contains a selection of the most common options. For a full
 2 | # list see the documentation:
 3 | # https://www.sphinx-doc.org/en/master/usage/configuration.html
 4 | from datetime import datetime
 5 | import glob
 6 | import os
 7 | from sphinx.ext.apidoc import main as apidoc_main
 8 | import sys
 9 | import sphinx_bootstrap_theme
10 | # -- Path setup --------------------------------------------------------------
11 | 
12 | # If extensions (or modules to document with autodoc) are in another directory,
13 | # add these directories to sys.path here. If the directory is relative to the
14 | # documentation root, use os.path.abspath to make it absolute, like shown here.
15 | #
16 | # sys.path.insert(0, os.path.abspath('.'))
17 | sys.path.insert(0, os.path.abspath('../'))
18 | 
19 | # -- Project information -----------------------------------------------------
20 | 
21 | project = 'pyDigitalWaveTools'
22 | copyright = '2017-%d, Michal Orsak' % datetime.now().year
23 | author = 'Michal Orsak'
24 | 
25 | 
26 | # -- General configuration ---------------------------------------------------
27 | 
28 | # Add any Sphinx extension module names here, as strings. They can be
29 | # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
30 | # ones.
31 | extensions = [
32 |     'sphinx.ext.autodoc',
33 | ]
34 | 
35 | # Add any paths that contain templates here, relative to this directory.
36 | templates_path = ['_templates']
37 | 
38 | # List of patterns, relative to source directory, that match files and
39 | # directories to ignore when looking for source files.
40 | # This pattern also affects html_static_path and html_extra_path.
41 | exclude_patterns = []
42 | 
43 | 
44 | # -- Options for HTML output -------------------------------------------------
45 | 
46 | # The theme to use for HTML and HTML Help pages.  See the documentation for
47 | # a list of builtin themes.
48 | #
49 | html_theme = 'bootstrap'
50 | html_theme_path = sphinx_bootstrap_theme.get_html_theme_path()
51 | 
52 | 
53 | # Add any paths that contain custom static files (such as style sheets) here,
54 | # relative to this directory. They are copied after the builtin static files,
55 | # so a file named "default.css" will overwrite the builtin "default.css".
56 | html_static_path = ['_static']
57 | 
58 | # update generated *.rst pages
59 | for file in glob.glob("*.rst"):
60 |     if file != "index.rst":
61 |         print("removing: ", file)
62 |         os.remove(file)
63 | 
64 | 
65 | apidoc_main(["--module-first", "--full", "--maxdepth", "-1",
66 |              "--output-dir", "../doc", "../pyDigitalWaveTools"])


--------------------------------------------------------------------------------
/doc/index.rst:
--------------------------------------------------------------------------------
 1 | Welcome to pyDigitalWaveTools's documentation!
 2 | ==========================================
 3 | 
 4 | Readme File
 5 | ===========
 6 | 
 7 | This is a python library for operations with VCD and other digital wave files.
 8 | 
 9 | .. toctree::
10 |    :maxdepth: 3
11 |    :caption: Contents:
12 | 
13 |    pyDigitalWaveTools
14 | 
15 | 
16 | 
17 | Indices and tables
18 | ==================
19 | 
20 | * :ref:`genindex`
21 | * :ref:`modindex`
22 | * :ref:`search`
23 | 


--------------------------------------------------------------------------------
/doc/requirements.doc.txt:
--------------------------------------------------------------------------------
1 | sphinx_bootstrap_theme


--------------------------------------------------------------------------------
/pyDigitalWaveTools/__init__.py:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/Nic30/pyDigitalWaveTools/971bf71ac3e4d625854e359b44fed0506be6e139/pyDigitalWaveTools/__init__.py


--------------------------------------------------------------------------------
/pyDigitalWaveTools/json/__init__.py:
--------------------------------------------------------------------------------
1 | """
2 | A module for loading and producing of wave data in json format
3 | (json equivalent to vcd module)
4 | """
5 | 


--------------------------------------------------------------------------------
/pyDigitalWaveTools/json/value_format.py:
--------------------------------------------------------------------------------
 1 | from copy import copy
 2 | from typing import List, Tuple
 3 | 
 4 | from pyDigitalWaveTools.vcd.value_format import bitToStr, bitVectorToStr, \
 5 |     LogValueFormatter
 6 | from pyDigitalWaveTools.vcd.writer import VcdVarWritingInfo
 7 | 
 8 | 
 9 | class JsonArrayFormatter(LogValueFormatter):
10 |     def __init__(self, dimmensions, elm_formatter):
11 |         self.dimmensions = dimmensions
12 |         self.elm_formatter = elm_formatter
13 | 
14 |     def bind_var_info(self, varInfo: VcdVarWritingInfo):
15 |         vi = copy(varInfo)
16 |         vi.width = vi.width[-1]
17 |         self.elm_formatter.bind_var_info(vi)
18 | 
19 |     def format(self, newVal: "Value", updater, t: int, out: List[Tuple]):
20 |         # updater can assign value of whole array, that is why it does not
21 |         # need to have indexes
22 |         indexes = getattr(updater, "indexes", None)
23 |         if indexes:
24 |             indexes = [int(i) for i in updater.indexes]
25 |             for i in indexes:
26 |                 newVal = newVal[i]
27 |             self.elm_formatter.format(newVal, updater, t, out) 
28 |             v = out.pop()
29 |             v = (t, (indexes, v[1]))
30 |             out.append(v)
31 |         else:
32 |             for i, v in enumerate(newVal):
33 |                 self.elm_formatter.format(v, updater, t, out) 
34 |                 v = out.pop()
35 |                 v = (t, ([i,], v[1]))
36 |                 out.append(v)
37 |                 
38 | 
39 | class JsonEnumFormatter(LogValueFormatter):
40 | 
41 |     def format(self, newVal: "Value", updater, t: int, out: List[Tuple]):
42 |         if newVal.vld_mask:
43 |             v = newVal.val
44 |         else:
45 |             v = ""
46 |         out.append((t, v))
47 |         
48 | 
49 | class JsonBitsFormatter(LogValueFormatter):
50 |     
51 |     def bind_var_info(self, varInfo: VcdVarWritingInfo):
52 |         self.width = varInfo.width
53 |         if self.width == 1:
54 |             self.format = self._format_bit
55 |         else:
56 |             self.format = self._format_bits
57 | 
58 |     def _format_bit(self, newVal: "Value", updater, t: int, out: List[Tuple]):
59 |         out.append((t, bitToStr(newVal.val, newVal.vld_mask)))
60 | 
61 |     def _format_bits(self, newVal: "Value", updater, t: int, out: List[Tuple]):
62 |         out.append((t, bitVectorToStr(newVal.val, self.width, newVal.vld_mask, 'b', None)))
63 | 
64 |     def format(self, newVal: "Value", updater, t: int, out: List[Tuple]):
65 |         raise Exception("Should have been replaced in bind_var_info")
66 | 


--------------------------------------------------------------------------------
/pyDigitalWaveTools/json/writer.py:
--------------------------------------------------------------------------------
  1 | #!/usr/bin/env python3
  2 | # -*- coding: utf-8 -*-
  3 | 
  4 | from pyDigitalWaveTools.vcd.common import VcdVarScope, VCD_SIG_TYPE
  5 | from pyDigitalWaveTools.vcd.parser import VcdVarParsingInfo
  6 | from pyDigitalWaveTools.vcd.value_format import LogValueFormatter
  7 | from pyDigitalWaveTools.vcd.writer import VarAlreadyRegistered, VcdVarWritingScope, VcdWriter
  8 | 
  9 | 
 10 | class VarIdScopeJson(dict):
 11 | 
 12 |     def registerVariable(self, sig: object, name: str, parent: VcdVarScope,
 13 |                          width: int, sigType: VCD_SIG_TYPE,
 14 |                          valueFormatter: LogValueFormatter):
 15 |         if sig is not None and sig in self:
 16 |             raise VarAlreadyRegistered(f"{sig} is already registered")
 17 |         vInf = VcdVarParsingInfo(
 18 |             None, name, width, sigType, parent)
 19 |         valueFormatter.bind_var_info(vInf)
 20 |         vInf.valueFormatter = valueFormatter.format
 21 |         self[sig] = vInf
 22 | 
 23 |         return vInf
 24 | 
 25 | 
 26 | class VarWritingScopeJson(VcdVarWritingScope):
 27 |     """
 28 |     Logical container of signals
 29 |     """
 30 | 
 31 |     def addVar(self, sig: object, name: str, sigType: VCD_SIG_TYPE, width: int,
 32 |                valueFormatter: LogValueFormatter):
 33 |         """
 34 |         Add variable to scope
 35 | 
 36 |         :ivar ~.sig: user specified object to keep track of VcdVarInfo in change()
 37 |         :ivar ~.sigType: vcd type name
 38 |         :ivar ~.valueFormatter: value which converts new value in change() to vcd string
 39 |         """
 40 |         vInf = self._writer._idScope.registerVariable(sig, name, self, width,
 41 |                                                       sigType, valueFormatter)
 42 |         self.children[vInf.name] = vInf
 43 | 
 44 |     def __enter__(self) -> "VcdVarWritingScope":
 45 |         return self
 46 | 
 47 |     def __exit__(self, exc_type, exc_val, exc_tb):
 48 |         pass
 49 | 
 50 | 
 51 | class JsonWriter(VcdWriter):
 52 | 
 53 |     def __init__(self, output: dict):
 54 |         self._output = output
 55 |         self._idScope = VarIdScopeJson()
 56 |         self.lastTime = -1
 57 |         self._top_var_scope = None
 58 | 
 59 |     def date(self, text):
 60 |         pass
 61 | 
 62 |     def version(self, text):
 63 |         pass
 64 | 
 65 |     def timescale(self, picoSeconds):
 66 |         pass
 67 | 
 68 |     def varScope(self, name) -> VcdVarWritingScope:
 69 |         """
 70 |         Create sub variable scope with defined name
 71 |         """
 72 |         vs = VarWritingScopeJson(name, self, parent=self)
 73 |         if self._top_var_scope is not None:
 74 |             raise AssertionError("Only one top scope currently supported")
 75 |         self._top_var_scope = vs
 76 |         return vs
 77 | 
 78 |     def enddefinitions(self):
 79 |         self._output.update(self._top_var_scope.toJson())
 80 | 
 81 |     def setTime(self, t):
 82 |         lt = self.lastTime
 83 |         if lt == t:
 84 |             return
 85 |         elif lt < t:
 86 |             self.lastTime = t
 87 |         else:
 88 |             raise ValueError(f"VcdWriter invalid time update {lt:d} -> {t:d}")
 89 | 
 90 |     def logChange(self, time, sig, newVal, valueUpdater):
 91 |         self.setTime(time)
 92 |         varInfo = self._idScope[sig]
 93 |         varInfo.valueFormatter(newVal, valueUpdater, self.lastTime, varInfo.data)
 94 | 
 95 | 
 96 | 
 97 | if __name__ == "__main__":
 98 |     from pyDigitalWaveTools.json.value_format import JsonBitsFormatter
 99 |     from tests.vcdWriter_test import example_dump_values0
100 | 
101 |     res = {}
102 |     vcd = JsonWriter(res)
103 |     example_dump_values0(vcd, JsonBitsFormatter)
104 | 
105 |     print(res)
106 | 


--------------------------------------------------------------------------------
/pyDigitalWaveTools/vcd/__init__.py:
--------------------------------------------------------------------------------
1 | """
2 | A module for parsing and writing of Value Change Dump (VCD) files
3 | """
4 | 


--------------------------------------------------------------------------------
/pyDigitalWaveTools/vcd/common.py:
--------------------------------------------------------------------------------
 1 | #!/usr/bin/env python3
 2 | # -*- coding: utf-8 -*-
 3 | from typing import Union
 4 | 
 5 | 
 6 | class VCD_SIG_TYPE():
 7 |     WIRE = "wire"
 8 |     REAL = "real"
 9 |     # not part of vcd
10 |     ENUM = "enum"
11 |     ARRAY = "array"
12 | 
13 | 
14 | class VcdVarInfo():
15 |     """
16 |     Common part of VcdParsingVarInfo and VcdVarWritingInfo
17 |     Container of informations about variable in VCD
18 | 
19 |     :ivar ~.vcdId: id in VCD file or the first VcdVarInfo which uses the same id (in this case this var is just reference to it)
20 |     :ivar ~.name: name in VCD file
21 |     :ivar ~.width: width in VCD file (int)
22 |     :ivar ~.sigType: VCD var type name (from VCD_SIG_TYPE)
23 |     :ivar ~.parent: parent VcdSignalScope object
24 |     """
25 | 
26 |     def __init__(self, vcdId: Union[str, 'VcdVarInfo'], name: str, width, sigType, parent):
27 |         self.vcdId = vcdId
28 |         self.name = name
29 |         self.width = width
30 |         self.sigType = sigType
31 |         self.parent = parent
32 | 
33 |     def __repr__(self):
34 |         return "<%s %s vcdId:%r>" % (
35 |             self.__class__.__name__,
36 |             VcdVarScope._getDebugName(self),
37 |             self.vcdId)
38 | 
39 | 
40 | class VcdVarScope():
41 |     """
42 |     VCD module - container for variables
43 | 
44 |     :ivar ~.name: name of this scope
45 |     :ivar ~.parent: parent scope of this scope or None
46 |     :ivar ~.children: dict {name: <VcdVarScope or VcdVarInfo instance>}
47 |     """
48 | 
49 |     def __init__(self, name, parent=None):
50 |         self.name = name
51 |         self.parent = parent
52 |         self.children = {}
53 | 
54 |     def _getDebugName(self):
55 |         buff = []
56 |         o = self
57 |         while True:
58 |             try:
59 |                 n = o.name
60 |             except AttributeError:
61 |                 buff.append(repr(o))
62 |                 break
63 | 
64 |             buff.append(n)
65 |             o = o.parent
66 |             if o is None:
67 |                 break
68 |         return ".".join(reversed(buff))
69 | 
70 |     def toJson(self):
71 |         return {
72 |             "name": self.name,
73 |             "type": {"name": "struct"},
74 |             "children": [ch.toJson() for ch in self.children.values()]
75 |         }
76 | 
77 |     def __repr__(self):
78 |         return "<%s %s>" % (self.__class__.__name__, self._getDebugName())
79 | 


--------------------------------------------------------------------------------
/pyDigitalWaveTools/vcd/parser.py:
--------------------------------------------------------------------------------
  1 | #!/usr/bin/env python3
  2 | # -*- coding: utf-8 -*-
  3 | 
  4 | '''
  5 | :note: inspired by https://github.com/GordonMcGregor/vcd_parser/blob/master/vcd/parser.py
  6 | 
  7 | A basic self contained VCD parser object
  8 | 
  9 | Walks through the definitions constructing the appropriate signal references.
 10 | Caches XMR paths if and when the signal value changes in the dump for future reference.
 11 | Needs some hooks for callbacks on signal changes and methods to allow sampling of a signal with an appropriate clock reference
 12 | 
 13 | Refer to IEEE SystemVerilog standard 1800-2009 for VCD details Section 21.7 Value Change Dump (VCD) files
 14 | '''
 15 | 
 16 | from collections import defaultdict
 17 | from io import StringIO
 18 | from itertools import dropwhile
 19 | from typing import Union, Dict, Tuple, List
 20 | 
 21 | from pyDigitalWaveTools.vcd.common import VcdVarScope, VcdVarInfo
 22 | 
 23 | 
 24 | class VcdSyntaxError(Exception):
 25 |     pass
 26 | 
 27 | 
 28 | class VcdDuplicatedVariableError(Exception):
 29 |     """
 30 |     This is when multiple definition to one variable happens.
 31 |     E.g.
 32 |     $scope module testbench $end
 33 |     $var reg 3 ! x [2:0] $end
 34 |     $upscope $end
 35 |     $scope module testbench $end
 36 |     $var wire 8 " x [7:0] $end
 37 |     $upscope $end
 38 |     """
 39 |     pass
 40 | 
 41 | 
 42 | class VcdVarParsingInfo(VcdVarInfo):
 43 |     """
 44 |     Container of informations about variable in VCD for parsing of VCD file
 45 |     """
 46 | 
 47 |     def __init__(self, vcdId: Union[str, VcdVarInfo], name: str, width, sigType, parent):
 48 |         super(VcdVarParsingInfo, self).__init__(
 49 |             vcdId, name, width, sigType, parent)
 50 |         self.data: List[Tuple[int, str]] = []
 51 | 
 52 |     def toJson(self):
 53 |         return {"name": self.name,
 54 |                 "type": {"width": self.width,
 55 |                          "name": self.sigType},
 56 |                 "data": self.data}
 57 | 
 58 | 
 59 | class VcdParser(object):
 60 |     '''
 61 |     A parser object for VCD files.
 62 |     Reads definitions and walks through the value changes
 63 |     https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=954909&tag=1
 64 | 
 65 |     :ivar ~.keyword_dispatch: dictionary {keyword: parse function}
 66 |     :ivar ~.scope: actual VcdSignalInfo
 67 |     :ivar ~.now: actual time (int)
 68 |     :ivar ~.idcode2var: dictionary mapping vcd id to VcdVarParsingInfo
 69 |     :ivar ~.idcode2series: dictionary {idcode: series} where series are list of tuples (time, value),
 70 |         the list commes from VcdVarParsingInfo object
 71 |     :ivar ~.signals: dict {topName: VcdSignalInfo instance}
 72 |     '''
 73 |     VECTOR_VALUE_CHANGE_PREFIX = {
 74 |         "b", "B", "r", "R"
 75 |     }
 76 |     SCOPE_TYPES = {
 77 |         "begin", "fork", "function", "module", "task"
 78 |     }
 79 | 
 80 |     def __init__(self):
 81 |         keyword_functions = {
 82 |             # declaration_keyword ::=
 83 |             "$comment": self.drop_while_end,
 84 |             "$date": self.save_declaration,
 85 |             "$enddefinitions": self.vcd_enddefinitions,
 86 |             "$scope": self.vcd_scope,
 87 |             "$timescale": self.save_declaration,
 88 |             "$upscope": self.vcd_upscope,
 89 |             "$var": self.vcd_var,
 90 |             "$version": self.save_declaration,
 91 |             # simulation_keyword ::=
 92 |             "$dumpall": self.vcd_dumpall,
 93 |             "$dumpoff": self.vcd_dumpoff,
 94 |             "$dumpon": self.vcd_dumpon,
 95 |             "$dumpvars": self.vcd_dumpvars,
 96 |             "$end": self.vcd_end,
 97 |         }
 98 | 
 99 |         self.keyword_dispatch = defaultdict(
100 |             lambda: self.parse_error, keyword_functions)
101 | 
102 |         # A root scope is used to deal with situations like
103 |         # ------
104 |         # $scope module testbench $end
105 |         # $var reg 3 ! x [2:0] $end
106 |         # $upscope $end
107 |         # $scope module testbench $end
108 |         # $var wire 8 " y [7:0] $end
109 |         # $upscope $end
110 |         # $enddefinitions $end
111 |         # ------
112 |         self.scope = VcdVarScope("root", None)
113 |         self.setNow(0)
114 |         self.idcode2var: Dict[str, VcdVarParsingInfo] = {}
115 |         self.idcode2series: Dict[str, List[Tuple[int, str]]] = {}
116 |         self.end_of_definitions = False
117 | 
118 |     def on_error(self, lineNo, vcdId):
119 |         print ("Wrong vcdId @ line", lineNo, ":", vcdId) 
120 |         
121 |     def value_change(self, vcdId, value, lineNo):
122 |         '''append change from VCD file signal data series'''
123 |         try: 
124 |             self.idcode2series[vcdId].append((self.now, value))
125 |         except:
126 |             self.on_error(lineNo, vcdId)
127 | 
128 |     def parse_str(self, vcd_string: str):
129 |         """
130 |         Same as :func:`~.parse` just for string
131 |         """
132 |         buff = StringIO(vcd_string)
133 |         return self.parse(buff)
134 |  
135 |     def setNow(self, value):
136 |         self.now = int(value)  # TODO: can be float
137 | 
138 |     def parse(self, file_handle):
139 |         '''
140 |         Tokenize and parse the VCD file
141 | 
142 |         :ivar ~.file_handle: opened file with vcd string
143 |         '''
144 |         # open the VCD file and create a token generator
145 |         lineIterator = iter(enumerate(file_handle))
146 |         tokeniser = ((lineNo, word)
147 |                      for lineNo, line in lineIterator
148 |                      for word in line.split() if word)
149 |         # def tokeniser_wrap():
150 |         #    for t in _tokeniser:
151 |         #        print(t)
152 |         #        yield t
153 |         # tokeniser = tokeniser_wrap()
154 | 
155 |         while True:
156 |             token = next(tokeniser)
157 |             # parse VCD until the end of definitions
158 |             self.keyword_dispatch[token[1]](tokeniser, token[1])
159 |             if self.end_of_definitions:
160 |                 break
161 | 
162 |         while True:
163 |             try:
164 |                 lineNo, token = next(tokeniser)
165 |             except StopIteration:
166 |                 break
167 | 
168 |             # parse changes
169 |             c = token[0]
170 |             if c == '$':
171 |                 fn = self.keyword_dispatch[token.strip()]
172 |                 fn(tokeniser, token)
173 |             elif c == '#':
174 |                 self.setNow (token[1:])
175 |             else:
176 |                 self.vcd_value_change(lineNo, token, tokeniser)
177 | 
178 |     def vcd_value_change(self, lineNo, token, tokenizer):
179 |         token = token.strip()
180 |         if not token:
181 |             return
182 | 
183 |         if token[0] in self.VECTOR_VALUE_CHANGE_PREFIX:
184 |             # vectors and strings
185 |             value = token
186 |             _, vcdId = next(tokenizer)
187 |         elif token[0] == "s":
188 |             # string value
189 |             value = token[1:]
190 |             _, vcdId = next(tokenizer)
191 |         elif token[0] == '#':  # In many VCD files there is no $end terminator
192 |             self.setNow(token[1:])
193 |             return
194 |         else:
195 |             # 1 bit value
196 |             value = token[0]
197 |             vcdId = token[1:]
198 | 
199 |         self.value_change(vcdId, value, lineNo)
200 | 
201 |     def parse_error(self, tokeniser, keyword):
202 |         raise VcdSyntaxError("Don't understand keyword: ", keyword)
203 | 
204 |     def drop_while_end(self, tokeniser, keyword):
205 |         next(dropwhile(lambda x: x[1] != "$end", tokeniser))
206 | 
207 |     def read_while_end(self, tokeniser):
208 |         for _, word in tokeniser:
209 |             if word == "$end":
210 |                 return
211 |             else:
212 |                 yield word
213 | 
214 |     def save_declaration(self, tokeniser, keyword):
215 |         self.__setattr__(keyword.lstrip('$'),
216 |                          " ".join(self.read_while_end(tokeniser)))
217 | 
218 |     def vcd_enddefinitions(self, tokeniser, keyword):
219 |         self.end_of_definitions = True
220 |         self.drop_while_end(tokeniser, keyword)
221 | 
222 |     def vcd_scope(self, tokeniser, keyword):
223 |         scopeType = next(tokeniser)
224 |         scopeTypeName = scopeType[1]
225 |         assert scopeTypeName in self.SCOPE_TYPES, scopeType
226 |         scopeName = next(tokeniser)
227 |         assert next(tokeniser)[1] == "$end"
228 |         s = self.scope
229 |         name = scopeName[1]
230 |         self.scope = VcdVarScope(name, s)
231 |         if isinstance(s, VcdVarScope):
232 |             if name in s.children:
233 |                 self.scope = s.children[name]
234 |                 assert isinstance(self.scope, VcdVarScope), self.scope
235 |             else:
236 |                 s.children[name] = self.scope
237 | 
238 |     def vcd_upscope(self, tokeniser, keyword):
239 |         self.scope = self.scope.parent
240 |         assert next(tokeniser)[1] == "$end"
241 | 
242 |     def vcd_var(self, tokeniser, keyword):
243 |         data = tuple(self.read_while_end(tokeniser))
244 |         # ignore range on identifier ( TODO  Fix this )
245 |         (var_type, size, vcdId, reference) = data[:4]
246 |         parent = self.scope
247 |         size = int(size)
248 |         parent_var = self.idcode2var.get(vcdId, None)
249 |         info = VcdVarParsingInfo(vcdId if parent_var is None else parent_var,
250 |                                  reference, size, var_type, parent)
251 |         assert reference not in parent.children
252 |         parent.children[reference] = info
253 |         if parent_var is None:
254 |             self.idcode2var[vcdId] = info
255 |             self.idcode2series[vcdId] = info.data
256 | 
257 |     def _vcd_value_change_list(self, tokeniser):
258 |         while True:
259 |             try:
260 |                 lineNo, token = next(tokeniser)
261 |             except StopIteration:
262 |                 break
263 |             if token and token[0] == "$":
264 |                 if token.startswith("$end"):
265 |                     return
266 |                 else:
267 |                     raise VcdSyntaxError(
268 |                         f"Line {lineNo:d}: Expected $end: {token:s}")
269 |             else:
270 |                 self.vcd_value_change(lineNo, token, tokeniser)
271 | 
272 |     def vcd_dumpall(self, tokeniser, keyword):
273 |         """
274 |         specifies current values of all variables dumped
275 | 
276 |         vcd_simulation_dumpall ::= $dumpall { value_changes } $end
277 | 
278 |         .. code-block:: verilog
279 | 
280 |             $dumpall   1*@  x*#   0*$   bx   (k $end
281 |         """
282 |         self._vcd_value_change_list(tokeniser)
283 | 
284 |     def vcd_dumpoff(self, tokeniser, keyword):
285 |         """
286 |         all variables dumped with X values
287 | 
288 |         vcd_simulation_dumpoff ::= $dumpoff { value_changes } $end
289 | 
290 |         .. code-block:: verilog
291 | 
292 |             $dumpoff  x*@  x*#   x*$   bx   (k $end
293 |         """
294 |         self._vcd_value_change_list(tokeniser)
295 | 
296 |     def vcd_dumpon(self, tokeniser, keyword):
297 |         """
298 |         resumption of dumping and lists current values of all variables dumped.
299 | 
300 |         vcd_simulation_dumpon ::= $dumpon { value_changes } $end
301 | 
302 |         .. code-block:: verilog
303 | 
304 |             $dumpon   x*@  0*#   x*$   b1   (k $end
305 |         """
306 |         self._vcd_value_change_list(tokeniser)
307 | 
308 |     def vcd_dumpvars(self, tokeniser, keyword):
309 |         """
310 |         lists initial values of all variables dumped
311 | 
312 |         vcd_simulation_dumpvars ::= $dumpvars { value_changes } $end
313 | 
314 |         .. code-block:: verilog
315 | 
316 |             $dumpvars   x*@   z*$   b0   (k $end
317 |         """
318 |         self._vcd_value_change_list(tokeniser)
319 | 
320 |     def vcd_end(self, tokeniser, keyword):
321 |         if not self.end_of_definitions:
322 |             raise VcdSyntaxError("missing end of declaration section")
323 | 
324 | 
325 | if __name__ == '__main__':
326 |     import json
327 |     import sys
328 |     argc = len(sys.argv)
329 |     if argc == 1:
330 |         fIn = "../tests/AxiRegTC_test_write.vcd"
331 |     elif argc == 2:
332 |         fIn = sys.argv[1]
333 |     elif argc == 3:
334 |         fIn = sys.argv[1]
335 |         fOut = sys.argv[2]
336 |     else:
337 |         raise ValueError(sys.argv)
338 | 
339 |     with open(fIn) as vcd_file:
340 |         vcd = VcdParser()
341 |         vcd.parse(vcd_file)
342 |         data = vcd.scope.toJson()
343 | 
344 |         if argc == 3:
345 |             with open(fOut, 'w') as jsonFile:
346 |                 jsonFile.write(data)
347 |         else:
348 |             print(json.dumps(data))
349 | 


--------------------------------------------------------------------------------
/pyDigitalWaveTools/vcd/value_format.py:
--------------------------------------------------------------------------------
 1 | from io import StringIO
 2 | from typing import Optional
 3 | 
 4 | 
 5 | def bitVectorToStr(val: int, width: int, vld_mask: int, prefix: Optional[str], suffix: Optional[str]):
 6 |     buff = []
 7 |     if prefix is not None:
 8 |         buff.append(prefix)
 9 | 
10 |     for i in range(width - 1, -1, -1):
11 |         mask = (1 << i)
12 |         b = val & mask
13 | 
14 |         if vld_mask & mask:
15 |             s = "1" if b else "0"
16 |         else:
17 |             s = "X"
18 |         buff.append(s)
19 | 
20 |     if suffix is not None:
21 |         buff.append(suffix)
22 | 
23 |     return ''.join(buff)
24 | 
25 | 
26 | def bitToStr(val: int, vld_mask: int):
27 |     if vld_mask:
28 |         return "1" if val else "0"
29 |     else:
30 |         return "X"
31 | 
32 | 
33 | class LogValueFormatter():
34 | 
35 |     def bind_var_info(self, varInfo: "VcdVarWritingInfo"):
36 |         pass
37 | 
38 |     def format(self, newVal: "Value", updater, t: int, out: StringIO):
39 |         pass
40 | 
41 | 
42 | class VcdEnumFormatter(LogValueFormatter):
43 | 
44 |     def bind_var_info(self, varInfo: "VcdVarWritingInfo"):
45 |         self.vcdId = varInfo.vcdId
46 | 
47 |     def format(self, newVal: "Value", updater, t: int, out: StringIO):
48 |         if newVal.vld_mask:
49 |             val = newVal.val
50 |         else:
51 |             val = "UNDEF"
52 | 
53 |         out.write(f"s{val:s} {self.vcdId:s}\n")
54 | 
55 | 
56 | class VcdBitsFormatter(LogValueFormatter):
57 | 
58 |     def bind_var_info(self, varInfo: "VcdVarWritingInfo"):
59 |         self.width = varInfo.width
60 |         self.vcdId = varInfo.vcdId
61 |         if self.width == 1:
62 |             self.format = self._format_bit
63 |             self.suffix = f"{self.vcdId:s}\n"
64 |         else:
65 |             self.format = self._format_bits
66 |             self.suffix = f" {self.vcdId:s}\n"
67 | 
68 |     def _format_bit(self, newVal: "Value", updater, t: int, out: StringIO):
69 |         v = bitToStr(newVal.val, newVal.vld_mask)
70 |         out.write(v + self.suffix)
71 | 
72 |     def _format_bits(self, newVal: "Value", updater, t: int, out: StringIO):
73 |         out.write(bitVectorToStr(newVal.val, self.width, newVal.vld_mask, "b", self.suffix))
74 | 
75 |     def format(self, newVal: "Value", updater):
76 |         raise AssertionError("Should have been replaced in bind_var_info")
77 | 
78 | 


--------------------------------------------------------------------------------
/pyDigitalWaveTools/vcd/writer.py:
--------------------------------------------------------------------------------
  1 | #!/usr/bin/env python3
  2 | # -*- coding: utf-8 -*-
  3 | 
  4 | import sys
  5 | 
  6 | from pyDigitalWaveTools.vcd.common import VcdVarScope, VCD_SIG_TYPE, VcdVarInfo
  7 | from pyDigitalWaveTools.vcd.value_format import LogValueFormatter
  8 | 
  9 | 
 10 | class VarAlreadyRegistered(Exception):
 11 |     pass
 12 | 
 13 | 
 14 | class VcdVarWritingInfo(VcdVarInfo):
 15 |     """
 16 |     Container of informations about variable in VCD for VCD file generating
 17 |     """
 18 | 
 19 |     def __init__(self, vcdId, name, width, sigType, parent,
 20 |                  valueFormatter: LogValueFormatter):
 21 |         super(VcdVarWritingInfo, self).__init__(
 22 |             vcdId, name, width, sigType, parent)
 23 |         valueFormatter.bind_var_info(self)
 24 |         self.valueFormatter = valueFormatter.format
 25 | 
 26 | 
 27 | class VcdVarIdScope(dict):
 28 | 
 29 |     def __init__(self):
 30 |         super(VcdVarIdScope, self).__init__()
 31 |         self._nextId = 0
 32 |         self._idChars = [chr(i) for i in range(ord("!"), ord("~") + 1)]
 33 |         self._idCharsCnt = len(self._idChars)
 34 | 
 35 |     def _idToStr(self, x):
 36 |         """
 37 |         Convert VCD id in int to string
 38 |         """
 39 |         if x < 0:
 40 |             sign = -1
 41 |         elif x == 0:
 42 |             return self._idChars[0]
 43 |         else:
 44 |             sign = 1
 45 |         x *= sign
 46 |         digits = []
 47 |         while x:
 48 |             digits.append(self._idChars[x % self._idCharsCnt])
 49 |             x //= self._idCharsCnt
 50 |         if sign < 0:
 51 |             digits.append('-')
 52 |         digits.reverse()
 53 | 
 54 |         return ''.join(digits)
 55 | 
 56 |     def registerVariable(self, sig: object, name: str, parent: VcdVarScope,
 57 |                          width: int, sigType: VCD_SIG_TYPE,
 58 |                          valueFormatter: LogValueFormatter):
 59 |         varId = self._idToStr(self._nextId)
 60 |         if sig is not None and sig in self:
 61 |             raise VarAlreadyRegistered(f"{sig} is already registered")
 62 |         vInf = VcdVarWritingInfo(
 63 |             varId, name, width, sigType, parent, valueFormatter)
 64 |         self[sig] = vInf
 65 |         self._nextId += 1
 66 |         return vInf
 67 | 
 68 | 
 69 | class VcdVarWritingScope(VcdVarScope):
 70 |     """
 71 |     Vcd module - container for variables
 72 | 
 73 |     :ivar ~.oFile: output file to write vcd to
 74 |     :ivar ~.name: name of scope
 75 |     :ivar ~.vars: subscopes or signals
 76 |     """
 77 | 
 78 |     def __init__(self, name, writer, parent=None):
 79 |         super(VcdVarWritingScope, self).__init__(name, parent=parent)
 80 |         self._writer = writer
 81 | 
 82 |     def addVar(self, sig: object, name: str, sigType: VCD_SIG_TYPE, width: int,
 83 |                valueFormatter: LogValueFormatter):
 84 |         """
 85 |         Add variable to scope
 86 | 
 87 |         :ivar ~.sig: user specified object to keep track of VcdVarInfo in change()
 88 |         :ivar ~.sigType: vcd type name
 89 |         :ivar ~.valueFormatter: value which converts new value in change() to vcd string
 90 |         """
 91 |         assert name, sig
 92 |         vInf = self._writer._idScope.registerVariable(sig, name, self, width,
 93 |                                                       sigType, valueFormatter)
 94 |         self.children[vInf.name] = vInf
 95 |         self._writer._oFile.write(f"$var {sigType:s} {vInf.width:d} {vInf.vcdId:s} {vInf.name:s} $end\n")
 96 | 
 97 |     def varScope(self, name):
 98 |         """
 99 |         Create sub variable scope with defined name
100 |         """
101 |         ch = self.__class__(name, self._writer, parent=self)
102 |         assert name not in self.children, (name, "Names of scopes and variables must be unique")
103 |         self.children[name] = ch
104 |         return ch
105 | 
106 |     def __enter__(self) -> "VcdVarWritingScope":
107 |         self._writeHeader()
108 |         return self
109 | 
110 |     def __exit__(self, exc_type, exc_val, exc_tb):
111 |         if exc_type is None:
112 |             self._writeFooter()
113 | 
114 |     def _writeHeader(self):
115 |         self._writer._oFile.write(f"$scope module {self.name:s} $end\n")
116 | 
117 |     def _writeFooter(self):
118 |         self._writer._oFile.write("$upscope $end\n")
119 | 
120 | 
121 | class VcdWriter():
122 | 
123 |     def __init__(self, oFile=sys.stdout):
124 |         self._oFile = oFile
125 |         self._idScope = VcdVarIdScope()
126 |         self.scopes = []
127 |         self.lastTime = -1
128 | 
129 |     def date(self, text):
130 |         d = str(text)
131 |         self._oFile.write(f"$date\n   {d:s}\n$end\n")
132 | 
133 |     def version(self, text):
134 |         self._oFile.write(f"$version   \n{text:s}\n$end\n")
135 | 
136 |     def timescale(self, picoSeconds):
137 |         self._oFile.write(f"$timescale {picoSeconds:d}ps $end\n")
138 | 
139 |     def varScope(self, name) -> VcdVarWritingScope:
140 |         """
141 |         Create sub variable scope with defined name
142 |         """
143 |         s = VcdVarWritingScope(name, self, parent=self)
144 |         self.scopes.append(s)
145 |         return s
146 | 
147 |     def enddefinitions(self):
148 |         self._oFile.write("$enddefinitions $end\n")
149 | 
150 |     def setTime(self, t):
151 |         lt = self.lastTime
152 |         if lt == t:
153 |             return
154 |         elif lt < t:
155 |             self.lastTime = t
156 |             self._oFile.write(f"#{t:d}\n")
157 |         else:
158 |             raise Exception(f"VcdWriter invalid time update {lt:d} -> {t:d}")
159 | 
160 |     def logChange(self, time, sig, newVal, valueUpdater):
161 |         self.setTime(time)
162 |         varInfo = self._idScope[sig]
163 |         varInfo.valueFormatter(newVal, valueUpdater, time, self._oFile)
164 | 
165 | 
166 | if __name__ == "__main__":
167 |     from datetime import datetime
168 |     from pyDigitalWaveTools.vcd.value_format import VcdBitsFormatter
169 |     from tests.vcdWriter_test import example_dump_values0
170 | 
171 |     vcd = VcdWriter()
172 |     vcd.date(datetime.now())
173 |     vcd.timescale(1)
174 |     example_dump_values0(vcd, VcdBitsFormatter)
175 | 
176 | 


--------------------------------------------------------------------------------
/setup.cfg:
--------------------------------------------------------------------------------
1 | [metadata]
2 | description-file = README.md
3 | 


--------------------------------------------------------------------------------
/setup.py:
--------------------------------------------------------------------------------
 1 | #!/usr/bin/env python3
 2 | # -*- coding: UTF-8 -*-
 3 | 
 4 | from os import path
 5 | from setuptools import setup, find_packages
 6 | 
 7 | this_directory = path.abspath(path.dirname(__file__))
 8 | with open(path.join(this_directory, 'README.md'), encoding='utf-8') as f:
 9 |     long_description = f.read()
10 | 
11 | setup(name='pyDigitalWaveTools',
12 |       version='1.2',
13 |       description='Library for operations with VCD and other digital wave files',
14 |       long_description=long_description,
15 |       long_description_content_type="text/markdown",
16 |       classifiers=[
17 |         "Development Status :: 4 - Beta",
18 |         "Intended Audience :: Developers",
19 |         "License :: OSI Approved :: MIT License",
20 |         "Operating System :: OS Independent",
21 |         "Programming Language :: Python :: 3",
22 |         "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
23 |         "Topic :: System :: Hardware",
24 |         "Topic :: System :: Emulators",
25 |         "Topic :: Utilities",
26 |       ],
27 |       url='https://github.com/Nic30/pyDigitalWaveTools',
28 |       author='Michal Orsak',
29 |       author_email='Nic30original@gmail.com',
30 |       license='MIT',
31 |       packages=find_packages(exclude=["tests", ]),
32 |       zip_safe=True
33 | )
34 | 


--------------------------------------------------------------------------------
/tests/AxiRegTC_test_write.vcd:
--------------------------------------------------------------------------------
   1 | $date
   2 |    2018-03-21 20:20:48.479224
   3 | $end
   4 | $timescale 1ps $end
   5 | $scope module EpWithReg $end
   6 | $var wire 3 ! bus_aw_prot $end
   7 | $var wire 1 " sig_ep_bus_r_valid $end
   8 | $var wire 1 # sig_reg_out_m_ar_valid $end
   9 | $var wire 1 $ bus_aw_ready $end
  10 | $var wire 32 % sig_ep_bus_w_data $end
  11 | $var wire 32 & sig_reg_out_m_aw_addr $end
  12 | $var wire 1 ' bus_aw_valid $end
  13 | $var wire 1 ( sig_ep_bus_w_ready $end
  14 | $var wire 3 ) sig_reg_out_m_aw_prot $end
  15 | $var wire 1 * bus_b_ready $end
  16 | $var wire 4 + sig_ep_bus_w_strb $end
  17 | $var wire 1 , sig_reg_out_m_aw_ready $end
  18 | $var wire 2 - bus_b_resp $end
  19 | $var wire 1 . sig_ep_bus_w_valid $end
  20 | $var wire 1 / sig_reg_out_m_aw_valid $end
  21 | $var wire 1 0 bus_b_valid $end
  22 | $var wire 1 1 sig_ep_clk $end
  23 | $var wire 1 2 sig_reg_out_m_b_ready $end
  24 | $var wire 32 3 bus_r_data $end
  25 | $var wire 32 4 sig_ep_decoded_field0_din $end
  26 | $var wire 2 5 sig_reg_out_m_b_resp $end
  27 | $var wire 1 6 bus_r_ready $end
  28 | $var wire 32 7 sig_ep_decoded_field0_dout_data $end
  29 | $var wire 1 8 sig_reg_out_m_b_valid $end
  30 | $var wire 2 9 bus_r_resp $end
  31 | $var wire 1 : sig_ep_decoded_field0_dout_vld $end
  32 | $var wire 32 ; sig_reg_out_m_r_data $end
  33 | $var wire 1 < bus_r_valid $end
  34 | $var wire 32 = sig_ep_decoded_field1_din $end
  35 | $var wire 1 > sig_reg_out_m_r_ready $end
  36 | $var wire 32 ? bus_w_data $end
  37 | $var wire 32 @ sig_ep_decoded_field1_dout_data $end
  38 | $var wire 2 A sig_reg_out_m_r_resp $end
  39 | $var wire 1 B bus_w_ready $end
  40 | $var wire 1 C sig_ep_decoded_field1_dout_vld $end
  41 | $var wire 1 D sig_reg_out_m_r_valid $end
  42 | $var wire 4 E bus_w_strb $end
  43 | $var wire 1 F sig_ep_rst_n $end
  44 | $var wire 32 G sig_reg_out_m_w_data $end
  45 | $var wire 1 H bus_w_valid $end
  46 | $var wire 1 I sig_reg_clk $end
  47 | $var wire 1 J sig_reg_out_m_w_ready $end
  48 | $var wire 1 K clk $end
  49 | $var wire 32 L sig_reg_in_s_ar_addr $end
  50 | $var wire 4 M sig_reg_out_m_w_strb $end
  51 | $var wire 32 N decoded_field0_din $end
  52 | $var wire 3 O sig_reg_in_s_ar_prot $end
  53 | $var wire 1 P sig_reg_out_m_w_valid $end
  54 | $var wire 32 Q decoded_field0_dout_data $end
  55 | $var wire 1 R sig_reg_in_s_ar_ready $end
  56 | $var wire 1 S sig_reg_rst_n $end
  57 | $var wire 1 T sig_reg_in_s_ar_valid $end
  58 | $var wire 1 U decoded_field0_dout_vld $end
  59 | $var wire 32 V decoded_field1_din $end
  60 | $var wire 32 W sig_reg_in_s_aw_addr $end
  61 | $var wire 32 X decoded_field1_dout_data $end
  62 | $var wire 3 Y sig_reg_in_s_aw_prot $end
  63 | $var wire 1 Z decoded_field1_dout_vld $end
  64 | $var wire 1 [ sig_reg_in_s_aw_ready $end
  65 | $var wire 1 \ rst_n $end
  66 | $var wire 1 ] sig_reg_in_s_aw_valid $end
  67 | $var wire 32 ^ sig_ep_bus_ar_addr $end
  68 | $var wire 1 _ sig_reg_in_s_b_ready $end
  69 | $var wire 3 ` sig_ep_bus_ar_prot $end
  70 | $var wire 2 a sig_reg_in_s_b_resp $end
  71 | $var wire 1 b sig_ep_bus_ar_ready $end
  72 | $var wire 1 c sig_reg_in_s_b_valid $end
  73 | $var wire 1 d sig_ep_bus_ar_valid $end
  74 | $var wire 32 e sig_reg_in_s_r_data $end
  75 | $var wire 32 f sig_ep_bus_aw_addr $end
  76 | $var wire 1 g sig_reg_in_s_r_ready $end
  77 | $var wire 3 h sig_ep_bus_aw_prot $end
  78 | $var wire 2 i sig_reg_in_s_r_resp $end
  79 | $var wire 1 j sig_ep_bus_aw_ready $end
  80 | $var wire 1 k sig_reg_in_s_r_valid $end
  81 | $var wire 1 l sig_ep_bus_aw_valid $end
  82 | $var wire 32 m sig_reg_in_s_w_data $end
  83 | $var wire 1 n sig_ep_bus_b_ready $end
  84 | $var wire 1 o sig_reg_in_s_w_ready $end
  85 | $var wire 2 p sig_ep_bus_b_resp $end
  86 | $var wire 4 q sig_reg_in_s_w_strb $end
  87 | $var wire 1 r sig_ep_bus_b_valid $end
  88 | $var wire 1 s sig_reg_in_s_w_valid $end
  89 | $var wire 32 t sig_ep_bus_r_data $end
  90 | $var wire 32 u sig_reg_out_m_ar_addr $end
  91 | $var wire 1 v sig_ep_bus_r_ready $end
  92 | $var wire 3 w sig_reg_out_m_ar_prot $end
  93 | $var wire 1 x sig_reg_out_m_ar_ready $end
  94 | $var wire 2 y sig_ep_bus_r_resp $end
  95 | $var wire 32 z bus_ar_addr $end
  96 | $var wire 3 { bus_ar_prot $end
  97 | $var wire 1 | bus_ar_ready $end
  98 | $var wire 1 } bus_ar_valid $end
  99 | $var wire 32 ~ bus_aw_addr $end
 100 | $scope module ep $end
 101 | $var wire 1 "! isBramAddr $end
 102 | $var real 1 "" rSt $end
 103 | $var real 1 "# rSt_next $end
 104 | $var real 1 "$ wSt $end
 105 | $var real 1 "% wSt_next $end
 106 | $var wire 1 "& w_hs $end
 107 | $var wire 32 "' arAddr $end
 108 | $var wire 32 "( arAddr_next $end
 109 | $var wire 32 ") awAddr $end
 110 | $var wire 32 "* awAddr_next $end
 111 | $upscope $end
 112 | $scope module reg $end
 113 | $var wire 1 "+ sig_gen_ar_reg_0_clk $end
 114 | $var wire 32 ", sig_gen_ar_reg_0_dataIn_addr $end
 115 | $var wire 3 "- sig_gen_ar_reg_0_dataIn_prot $end
 116 | $var wire 1 ". sig_gen_ar_reg_0_dataIn_ready $end
 117 | $var wire 1 "/ sig_gen_ar_reg_0_dataIn_valid $end
 118 | $var wire 32 "0 sig_gen_ar_reg_0_dataOut_addr $end
 119 | $var wire 3 "1 sig_gen_ar_reg_0_dataOut_prot $end
 120 | $var wire 1 "2 sig_gen_ar_reg_0_dataOut_ready $end
 121 | $var wire 1 "3 sig_gen_ar_reg_0_dataOut_valid $end
 122 | $var wire 1 "4 sig_gen_ar_reg_0_rst_n $end
 123 | $var wire 1 "5 sig_gen_aw_reg_0_clk $end
 124 | $var wire 32 "6 sig_gen_aw_reg_0_dataIn_addr $end
 125 | $var wire 3 "7 sig_gen_aw_reg_0_dataIn_prot $end
 126 | $var wire 1 "8 sig_gen_aw_reg_0_dataIn_ready $end
 127 | $var wire 1 "9 sig_gen_aw_reg_0_dataIn_valid $end
 128 | $var wire 32 ": sig_gen_aw_reg_0_dataOut_addr $end
 129 | $var wire 3 "; sig_gen_aw_reg_0_dataOut_prot $end
 130 | $var wire 1 "< sig_gen_aw_reg_0_dataOut_ready $end
 131 | $var wire 1 "= sig_gen_aw_reg_0_dataOut_valid $end
 132 | $var wire 1 "> sig_gen_aw_reg_0_rst_n $end
 133 | $var wire 1 "? sig_gen_b_reg_0_clk $end
 134 | $var wire 1 "@ sig_gen_b_reg_0_dataIn_ready $end
 135 | $var wire 2 "A sig_gen_b_reg_0_dataIn_resp $end
 136 | $var wire 1 "B sig_gen_b_reg_0_dataIn_valid $end
 137 | $var wire 1 "C sig_gen_b_reg_0_dataOut_ready $end
 138 | $var wire 2 "D sig_gen_b_reg_0_dataOut_resp $end
 139 | $var wire 1 "E sig_gen_b_reg_0_dataOut_valid $end
 140 | $var wire 1 "F sig_gen_b_reg_0_rst_n $end
 141 | $var wire 1 "G sig_gen_r_reg_0_clk $end
 142 | $var wire 32 "H sig_gen_r_reg_0_dataIn_data $end
 143 | $var wire 1 "I sig_gen_r_reg_0_dataIn_ready $end
 144 | $var wire 2 "J sig_gen_r_reg_0_dataIn_resp $end
 145 | $var wire 1 "K sig_gen_r_reg_0_dataIn_valid $end
 146 | $var wire 32 "L sig_gen_r_reg_0_dataOut_data $end
 147 | $var wire 1 "M sig_gen_r_reg_0_dataOut_ready $end
 148 | $var wire 2 "N sig_gen_r_reg_0_dataOut_resp $end
 149 | $var wire 1 "O sig_gen_r_reg_0_dataOut_valid $end
 150 | $var wire 1 "P sig_gen_r_reg_0_rst_n $end
 151 | $var wire 1 "Q sig_gen_w_reg_0_clk $end
 152 | $var wire 32 "R sig_gen_w_reg_0_dataIn_data $end
 153 | $var wire 1 "S sig_gen_w_reg_0_dataIn_ready $end
 154 | $var wire 4 "T sig_gen_w_reg_0_dataIn_strb $end
 155 | $var wire 1 "U sig_gen_w_reg_0_dataIn_valid $end
 156 | $var wire 32 "V sig_gen_w_reg_0_dataOut_data $end
 157 | $var wire 1 "W sig_gen_w_reg_0_dataOut_ready $end
 158 | $var wire 4 "X sig_gen_w_reg_0_dataOut_strb $end
 159 | $var wire 1 "Y sig_gen_w_reg_0_dataOut_valid $end
 160 | $var wire 1 "Z sig_gen_w_reg_0_rst_n $end
 161 | $scope module gen_ar_reg_0 $end
 162 | $var wire 1 "[ latency1_reg_we $end
 163 | $var wire 1 "\ latency1_isOccupied_next $end
 164 | $var wire 3 "] latency1_reg_prot_next $end
 165 | $var wire 1 "^ latency1_isOccupied $end
 166 | $var wire 3 "_ latency1_reg_prot $end
 167 | $var wire 32 "` latency1_reg_addr_next $end
 168 | $var wire 32 "a latency1_reg_addr $end
 169 | $upscope $end
 170 | $scope module gen_aw_reg_0 $end
 171 | $var wire 32 "b latency1_reg_addr $end
 172 | $var wire 1 "c latency1_reg_we $end
 173 | $var wire 1 "d latency1_isOccupied_next $end
 174 | $var wire 3 "e latency1_reg_prot_next $end
 175 | $var wire 1 "f latency1_isOccupied $end
 176 | $var wire 3 "g latency1_reg_prot $end
 177 | $var wire 32 "h latency1_reg_addr_next $end
 178 | $upscope $end
 179 | $scope module gen_b_reg_0 $end
 180 | $var wire 1 "i latency1_reg_we $end
 181 | $var wire 1 "j latency1_isOccupied $end
 182 | $var wire 1 "k latency1_isOccupied_next $end
 183 | $var wire 2 "l latency1_reg_resp $end
 184 | $var wire 2 "m latency1_reg_resp_next $end
 185 | $upscope $end
 186 | $scope module gen_r_reg_0 $end
 187 | $var wire 1 "n latency1_reg_we $end
 188 | $var wire 2 "o latency1_reg_resp_next $end
 189 | $var wire 1 "p latency1_isOccupied_next $end
 190 | $var wire 2 "q latency1_reg_resp $end
 191 | $var wire 1 "r latency1_isOccupied $end
 192 | $var wire 32 "s latency1_reg_data $end
 193 | $var wire 32 "t latency1_reg_data_next $end
 194 | $upscope $end
 195 | $scope module gen_w_reg_0 $end
 196 | $var wire 32 "u latency1_reg_data_next $end
 197 | $var wire 4 "v latency1_reg_strb_next $end
 198 | $var wire 32 "w latency1_reg_data $end
 199 | $var wire 1 "x latency1_isOccupied_next $end
 200 | $var wire 1 "y latency1_reg_we $end
 201 | $var wire 1 "z latency1_isOccupied $end
 202 | $var wire 4 "{ latency1_reg_strb $end
 203 | $upscope $end
 204 | $upscope $end
 205 | $upscope $end
 206 | $enddefinitions $end
 207 | #0
 208 | srdIdle ""
 209 | srdIdle "#
 210 | swrIdle "$
 211 | swrIdle "%
 212 | 0"^
 213 | 0"f
 214 | 0"j
 215 | 0"r
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 231 | 1"I
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 233 | 1"S
 234 | 0"Y
 235 | 01
 236 | 0F
 237 | 0I
 238 | 0S
 239 | 0D
 240 | 1,
 241 | 08
 242 | 0J
 243 | 0:
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 246 | 1R
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 265 | 0"F
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 270 | 0U
 271 | 0Z
 272 | 1x
 273 | 1|
 274 | 0d
 275 | 1$
 276 | 0l
 277 | 1n
 278 | 00
 279 | 1v
 280 | 0<
 281 | 1B
 282 | 0.
 283 | 0"p
 284 | 0"n
 285 | 0"k
 286 | 0"i
 287 | 1"2
 288 | #2500
 289 | 0'
 290 | 06
 291 | 0*
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 295 | 0"9
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 299 | 0"c
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 301 | 1K
 302 | b00000000000000000000000001100100 ?
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 304 | 0H
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 306 | 11
 307 | 1I
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 310 | 0s
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 312 | 1"G
 313 | 1"5
 314 | 1"+
 315 | 1"Q
 316 | 1"?
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 318 | b1111 "T
 319 | 0"U
 320 | 0"/
 321 | 0"y
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 323 | 0"\
 324 | 0"[
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 326 | 1\
 327 | 1S
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 329 | 1"4
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 333 | 1"F
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 342 | 0"?
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 345 | b00000000000000000000000000000000 ~
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 350 | 11
 351 | 1I
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 356 | 1g
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 363 | b000 "7
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 386 | 0"y
 387 | b1111 "X
 388 | b00000000000000000000000001100100 "V
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 391 | b00000000000000000000000000000000 &
 392 | 0o
 393 | 1P
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 395 | b00000000000000000000000001100100 G
 396 | 1l
 397 | b000 h
 398 | b00000000000000000000000000000000 f
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 402 | b00000000000000000000000001100100 %
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 404 | b00000000000000000000000000000000 "*
 405 | b00000000000000000000000001100100 7
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 408 | b00000000000000000000000001100100 X
 409 | #20000
 410 | 0K
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 412 | 0I
 413 | 0"G
 414 | 0"5
 415 | 0"+
 416 | 0"Q
 417 | 0"?
 418 | #22500
 419 | 0H
 420 | 0'
 421 | 0s
 422 | 0]
 423 | 0"U
 424 | 0"9
 425 | 0"d
 426 | 0"c
 427 | #25000
 428 | 1K
 429 | b00000000000000000000000000000100 ~
 430 | 1'
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 432 | 1I
 433 | b00000000000000000000000000000100 W
 434 | 1]
 435 | 1"G
 436 | 1"5
 437 | 1"+
 438 | 1"Q
 439 | 1"?
 440 | b00000000000000000000000000000100 "6
 441 | 1"9
 442 | 1"d
 443 | 1"c
 444 | b00000000000000000000000000000100 "h
 445 | swrData "$
 446 | b00000000000000000000000000000000 ")
 447 | b00000000000000000000000000000100 "b
 448 | 0j
 449 | swrResp "%
 450 | 1(
 451 | 1"&
 452 | b00 p
 453 | b00000000000000000000000000000100 ":
 454 | 0,
 455 | 1J
 456 | 1:
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 458 | b00 5
 459 | b00000000000000000000000000000100 &
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 475 | #30000
 476 | 0K
 477 | 01
 478 | 0I
 479 | 0"G
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 483 | 0"?
 484 | #32500
 485 | 06
 486 | 0'
 487 | 0g
 488 | 0]
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 490 | 0"9
 491 | #35000
 492 | 1K
 493 | 1*
 494 | 11
 495 | 1I
 496 | 1_
 497 | 1"G
 498 | 1"5
 499 | 1"+
 500 | 1"Q
 501 | 1"?
 502 | 1"C
 503 | swrResp "$
 504 | 0"z
 505 | swrIdle "%
 506 | 1r
 507 | 0(
 508 | 0"&
 509 | 0"Y
 510 | 18
 511 | 0J
 512 | 0:
 513 | 1b
 514 | 0P
 515 | 1"B
 516 | 0"W
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 527 | 0I
 528 | 0"G
 529 | 0"5
 530 | 0"+
 531 | 0"Q
 532 | 0"?
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 534 | 0*
 535 | 0_
 536 | 0"C
 537 | #45000
 538 | 1K
 539 | 11
 540 | 1I
 541 | 1"G
 542 | 1"5
 543 | 1"+
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 545 | 1"?
 546 | swrIdle "$
 547 | b00 "l
 548 | 1"j
 549 | 1j
 550 | swrData "%
 551 | 0r
 552 | b00000000000000000000000000000100 "*
 553 | b00 "D
 554 | 0"@
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 576 | 0"5
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 580 | #55000
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 582 | b00000000000000000000000000000000 ~
 583 | 1'
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 585 | 1H
 586 | 1*
 587 | 11
 588 | 1I
 589 | b00000000000000000000000000000000 W
 590 | 1]
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 599 | b00000000000000000000000000000000 "6
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1906 | 0"Q
1907 | 0"?
1908 | #435000
1909 | 1K
1910 | 16
1911 | 11
1912 | 1I
1913 | 1g
1914 | 1"G
1915 | 1"5
1916 | 1"+
1917 | 1"Q
1918 | 1"?
1919 | 1"M
1920 | #440000
1921 | 0K
1922 | 01
1923 | 0I
1924 | 0"G
1925 | 0"5
1926 | 0"+
1927 | 0"Q
1928 | 0"?
1929 | #442500
1930 | 06
1931 | 0g
1932 | 0"M
1933 | #445000
1934 | 1K
1935 | 1*
1936 | 11
1937 | 1I
1938 | 1_
1939 | 1"G
1940 | 1"5
1941 | 1"+
1942 | 1"Q
1943 | 1"?
1944 | 1"C
1945 | #450000
1946 | 0K
1947 | 01
1948 | 0I
1949 | 0"G
1950 | 0"5
1951 | 0"+
1952 | 0"Q
1953 | 0"?
1954 | #455000
1955 | 1K
1956 | 16
1957 | 11
1958 | 1I
1959 | 1g
1960 | 1"G
1961 | 1"5
1962 | 1"+
1963 | 1"Q
1964 | 1"?
1965 | 1"M
1966 | #460000
1967 | 0K
1968 | 01
1969 | 0I
1970 | 0"G
1971 | 0"5
1972 | 0"+
1973 | 0"Q
1974 | 0"?
1975 | #462500
1976 | 0*
1977 | 06
1978 | 0_
1979 | 0g
1980 | 0"C
1981 | 0"M
1982 | #465000
1983 | 1K
1984 | 11
1985 | 1I
1986 | 1"G
1987 | 1"5
1988 | 1"+
1989 | 1"Q
1990 | 1"?
1991 | #470000
1992 | 0K
1993 | 01
1994 | 0I
1995 | 0"G
1996 | 0"5
1997 | 0"+
1998 | 0"Q
1999 | 0"?
2000 | #475000
2001 | 1K
2002 | 1*
2003 | 11
2004 | 1I
2005 | 1_
2006 | 1"G
2007 | 1"5
2008 | 1"+
2009 | 1"Q
2010 | 1"?
2011 | 1"C
2012 | #480000
2013 | 0K
2014 | 01
2015 | 0I
2016 | 0"G
2017 | 0"5
2018 | 0"+
2019 | 0"Q
2020 | 0"?
2021 | #482500
2022 | 0*
2023 | 0_
2024 | 0"C
2025 | #485000
2026 | 1K
2027 | 16
2028 | 1*
2029 | 11
2030 | 1I
2031 | 1g
2032 | 1_
2033 | 1"G
2034 | 1"5
2035 | 1"+
2036 | 1"Q
2037 | 1"?
2038 | 1"M
2039 | 1"C
2040 | #490000
2041 | 0K
2042 | 01
2043 | 0I
2044 | 0"G
2045 | 0"5
2046 | 0"+
2047 | 0"Q
2048 | 0"?
2049 | #492500
2050 | 06
2051 | 0*
2052 | 0g
2053 | 0_
2054 | 0"M
2055 | 0"C
2056 | #495000
2057 | 1K
2058 | 1*
2059 | 11
2060 | 1I
2061 | 1_
2062 | 1"G
2063 | 1"5
2064 | 1"+
2065 | 1"Q
2066 | 1"?
2067 | 1"C
2068 | 


--------------------------------------------------------------------------------
/tests/__init__.py:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/Nic30/pyDigitalWaveTools/971bf71ac3e4d625854e359b44fed0506be6e139/tests/__init__.py


--------------------------------------------------------------------------------
/tests/all.py:
--------------------------------------------------------------------------------
 1 | #!/usr/bin/env python3
 2 | # -*- coding: utf-8 -*-
 3 | 
 4 | import sys
 5 | from unittest import TestLoader, TextTestRunner, TestSuite
 6 | from tests.jsonWriter_test import JsonWriterTC
 7 | from tests.vcdParser_test import VcdParserTC
 8 | from tests.vcdWriter_test import VcdWriterTC
 9 | 
10 | 
11 | 
12 | def testSuiteFromTCs(*tcs):
13 |     loader = TestLoader()
14 |     loadedTcs = [loader.loadTestsFromTestCase(tc) for tc in tcs]
15 |     suite = TestSuite(loadedTcs)
16 |     return suite
17 | 
18 | 
19 | suite = testSuiteFromTCs(
20 |     JsonWriterTC,
21 |     VcdParserTC,
22 |     VcdWriterTC,
23 | )
24 | 
25 | 
26 | if __name__ == '__main__':
27 |     runner = TextTestRunner(verbosity=2)
28 | 
29 |     try:
30 |         from concurrencytest import ConcurrentTestSuite, fork_for_tests
31 |         useParallelTest = True
32 |     except ImportError:
33 |         # concurrencytest is not installed, use regular test runner
34 |         useParallelTest = False
35 | 
36 |     if useParallelTest:
37 |         # Run same tests across 4 processes
38 |         concurrent_suite = ConcurrentTestSuite(suite, fork_for_tests())
39 |         runner.run(concurrent_suite)
40 |     else:
41 |         sys.exit(not runner.run(suite).wasSuccessful())
42 | 


--------------------------------------------------------------------------------
/tests/example0.json:
--------------------------------------------------------------------------------
 1 | {
 2 |   "children": [
 3 |     {
 4 |       "data": [
 5 |         [
 6 |           0,
 7 |           "X"
 8 |         ],
 9 |         [
10 |           1,
11 |           "0"
12 |         ]
13 |       ],
14 |       "name": "sig0",
15 |       "type": {
16 |         "name": "wire",
17 |         "width": 1
18 |       }
19 |     },
20 |     {
21 |       "data": [
22 |         [
23 |           0,
24 |           "X"
25 |         ],
26 |         [
27 |           2,
28 |           "1"
29 |         ]
30 |       ],
31 |       "name": "sig1",
32 |       "type": {
33 |         "name": "wire",
34 |         "width": 1
35 |       }
36 |     },
37 |     {
38 |       "data": [
39 |         [
40 |           0,
41 |           "bXXXXXXXXXXXXXXXX"
42 |         ],
43 |         [
44 |           3,
45 |           "b0000000000001010"
46 |         ],
47 |         [
48 |           4,
49 |           "b0000000000010100"
50 |         ]
51 |       ],
52 |       "name": "vect0",
53 |       "type": {
54 |         "name": "wire",
55 |         "width": 16
56 |       }
57 |     }
58 |   ],
59 |   "name": "unit0",
60 |   "type": {
61 |     "name": "struct"
62 |   }
63 | }


--------------------------------------------------------------------------------
/tests/example0.vcd:
--------------------------------------------------------------------------------
 1 | $date
 2 |    2018-04-12 18:04:03.652880
 3 | $end
 4 | $timescale 1ps $end
 5 | $scope module unit0 $end
 6 | $var wire 1 ! sig0 $end
 7 | $var wire 1 " sig1 $end
 8 | $var wire 16 # vect0 $end
 9 | $upscope $end
10 | $enddefinitions $end
11 | #0
12 | X!
13 | X"
14 | bXXXXXXXXXXXXXXXX #
15 | #1
16 | 0!
17 | #2
18 | 1"
19 | #3
20 | b0000000000001010 #
21 | #4
22 | b0000000000010100 #
23 | 


--------------------------------------------------------------------------------
/tests/jsonWriter_test.py:
--------------------------------------------------------------------------------
 1 | #!/usr/bin/env python3
 2 | # -*- coding: utf-8 -*-
 3 | 
 4 | import json
 5 | import os
 6 | import unittest
 7 | 
 8 | from pyDigitalWaveTools.json.value_format import JsonBitsFormatter
 9 | from pyDigitalWaveTools.json.writer import JsonWriter
10 | from tests.vcdWriter_test import example_dump_values0
11 | 
12 | 
13 | BASE = os.path.dirname(os.path.realpath(__file__))
14 | 
15 | 
16 | def value_tuples_to_lists(scope: dict):
17 |     """
18 |     We need to convert all tuples to list because the tuple is serialized as list in json
19 |     and after de-serialization the tuple objects will become lists
20 |     """
21 |     data = scope.get("data", None)
22 |     if data is not None:
23 |         data = [list(d) for d in data]
24 |         scope["data"] = data
25 | 
26 |     children = scope.get("children", None)
27 |     if children is not None:
28 |         for c in children:
29 |             value_tuples_to_lists(c)
30 |     return scope
31 | 
32 | 
33 | class JsonWriterTC(unittest.TestCase):
34 | 
35 |     def test_example0(self):
36 | 
37 |         res = {}
38 |         w = JsonWriter(res)
39 |         example_dump_values0(w, JsonBitsFormatter)
40 | 
41 |         # with open(os.path.join(BASE, "example0.json"), "w") as f:
42 |         #    json.dump(res, f, indent=2, sort_keys=True)
43 | 
44 |         res = value_tuples_to_lists(res)
45 |         with open(os.path.join(BASE, "example0.json")) as f:
46 |             ref = json.load(f)
47 |             self.assertDictEqual(ref, res)
48 | 
49 | 
50 | if __name__ == "__main__":
51 |     testLoader = unittest.TestLoader()
52 |     # suite = unittest.TestSuite([JsonWriterTC("test_example0")])
53 |     suite = testLoader.loadTestsFromTestCase(JsonWriterTC)
54 |     runner = unittest.TextTestRunner(verbosity=3)
55 |     runner.run(suite)
56 | 


--------------------------------------------------------------------------------
/tests/multiscope.vcd:
--------------------------------------------------------------------------------
 1 | $date
 2 |     Tue Mar 16 16:28:35 2021
 3 | $end
 4 | $version
 5 |     Icarus Verilog
 6 | $end
 7 | $timescale
 8 |     1s
 9 | $end
10 | $scope module testbench $end
11 | $var reg 1 ! sel $end
12 | $upscope $end
13 | $scope module testbench $end
14 | $var reg 1 " a $end
15 | $upscope $end
16 | $scope module testbench $end
17 | $var reg 1 # b $end
18 | $upscope $end
19 | $scope module testbench $end
20 | $var wire 1 $ out $end
21 | $upscope $end
22 | $enddefinitions $end
23 | #0
24 | $dumpvars
25 | x$
26 | x#
27 | x"
28 | x!
29 | $end
30 | #1
31 | 0$
32 | 0#
33 | 0"
34 | 0!
35 | #2
36 | 1$
37 | 1"
38 | #3
39 | 1#
40 | #4
41 | 0$
42 | 0"
43 | #5
44 | 0#
45 | 1!
46 | #6
47 | 1"
48 | #7
49 | 1$
50 | 1#
51 | #8
52 | 0"
53 | 


--------------------------------------------------------------------------------
/tests/vcdParser_test.py:
--------------------------------------------------------------------------------
 1 | #!/usr/bin/env python3
 2 | # -*- coding: utf-8 -*-
 3 | 
 4 | import unittest
 5 | import os
 6 | from pyDigitalWaveTools.vcd.parser import VcdParser
 7 | 
 8 | BASE = os.path.dirname(os.path.realpath(__file__))
 9 | 
10 | 
11 | class VcdParserTC(unittest.TestCase):
12 | 
13 |     def test_example0(self):
14 |         reference = {
15 |             "name": "root",
16 |             "type": {"name": "struct"},
17 |             "children": [
18 |                 {
19 |                     "name": "unit0",
20 |                     "type": {"name": "struct"},
21 |                     "children": [
22 |                         {
23 |                             "name": "sig0",
24 |                             "type": {"name": "wire", "width": 1},
25 |                             "data": [(0, "X"), (1, "0")],
26 |                         },
27 |                         {
28 |                             "name": "sig1",
29 |                             "type": {"name": "wire", "width": 1},
30 |                             "data": [(0, "X"), (2, "1")],
31 |                         },
32 |                         {
33 |                             "name": "vect0",
34 |                             "type": {"name": "wire", "width": 16},
35 |                             "data": [(0, "bXXXXXXXXXXXXXXXX"), (3, "b0000000000001010"), (4, "b0000000000010100")],
36 |                         },
37 |                     ]
38 |                 }
39 |             ]
40 |         }
41 |         vcd = self.parse_file("example0.vcd")
42 |         data = vcd.scope.toJson()
43 |         self.assertDictEqual(reference, data)
44 | 
45 |     def parse_file(self, rel_name) -> VcdParser:
46 |         fIn = os.path.join(BASE, rel_name)
47 |         with open(fIn) as vcd_file:
48 |             vcd = VcdParser()
49 |             vcd.parse(vcd_file)
50 |             return vcd
51 | 
52 |     def test_AxiRegTC_test_write(self):
53 |         self.parse_file("AxiRegTC_test_write.vcd")
54 | 
55 |     def test_verilog2005_sample0(self):
56 |         vcd = self.parse_file("verilog2005-sample0.vcd")
57 |         data = vcd.scope
58 |         self.assertEqual(len(data.children["top"].children), 2)
59 | 
60 |     def test_verilog2005_sample1(self):
61 |         vcd = self.parse_file("verilog2005-sample0.vcd")
62 |         vcd.scope.toJson()
63 | 
64 |     def test_multiscope(self):
65 |         vcd = self.parse_file("multiscope.vcd")
66 |         vcd.scope.toJson()
67 | 
68 | 
69 | if __name__ == "__main__":
70 |     testLoader = unittest.TestLoader()
71 |     # suite = unittest.TestSuite([VcdParserTC("test_verilog2005_sample0")])
72 |     suite = testLoader.loadTestsFromTestCase(VcdParserTC)
73 |     runner = unittest.TextTestRunner(verbosity=3)
74 |     runner.run(suite)
75 | 


--------------------------------------------------------------------------------
/tests/vcdWriter_test.py:
--------------------------------------------------------------------------------
  1 | #!/usr/bin/env python3
  2 | # -*- coding: utf-8 -*-
  3 | 
  4 | from datetime import datetime
  5 | from io import StringIO
  6 | import os
  7 | from typing import Union, Dict, Tuple, List
  8 | import unittest
  9 | 
 10 | from pyDigitalWaveTools.vcd.common import VCD_SIG_TYPE, VcdVarScope
 11 | from pyDigitalWaveTools.vcd.parser import VcdParser, VcdVarParsingInfo
 12 | from pyDigitalWaveTools.vcd.value_format import VcdBitsFormatter, \
 13 |     LogValueFormatter
 14 | from pyDigitalWaveTools.vcd.writer import VcdWriter, VcdVarWritingScope
 15 | 
 16 | 
 17 | BASE = os.path.dirname(os.path.realpath(__file__))
 18 | 
 19 | 
 20 | class MaskedValue():
 21 | 
 22 |     def __init__(self, val, vld_mask):
 23 |         self.val = val
 24 |         self.vld_mask = vld_mask
 25 | 
 26 | 
 27 | def example_dump_values0(vcd, bitsFromatter=VcdBitsFormatter):
 28 |     sig0 = "sig0"
 29 |     vect0 = "vect0"
 30 |     sig1 = "sig1"
 31 | 
 32 |     with vcd.varScope("unit0") as m:
 33 |         m.addVar(sig0, sig0, VCD_SIG_TYPE.WIRE, 1, bitsFromatter())
 34 |         m.addVar(sig1, sig1, VCD_SIG_TYPE.WIRE, 1, bitsFromatter())
 35 |         m.addVar(vect0, vect0, VCD_SIG_TYPE.WIRE, 16, bitsFromatter())
 36 |     vcd.enddefinitions()
 37 | 
 38 |     for s in [sig0, sig1, vect0]:
 39 |         vcd.logChange(0, s, MaskedValue(0, 0), None)
 40 | 
 41 |     vcd.logChange(1, sig0, MaskedValue(0, 1), None)
 42 |     vcd.logChange(2, sig1, MaskedValue(1, 1), None)
 43 | 
 44 |     vcd.logChange(3, vect0, MaskedValue(10, (1 << 16) - 1), None)
 45 |     vcd.logChange(4, vect0, MaskedValue(20, (1 << 16) - 1), None)
 46 | 
 47 | 
 48 | class AsIsFormatter(LogValueFormatter):
 49 |     """
 50 |     Return value as is withou any formating or conversion
 51 |     """
 52 | 
 53 |     def bind_var_info(self, varInfo: "VcdVarWritingInfo"):
 54 |         self.vcdId = varInfo.vcdId
 55 | 
 56 |         if varInfo.sigType == VCD_SIG_TYPE.WIRE and varInfo.width == 1:
 57 |             self.format = self.format_bit
 58 |         elif varInfo.sigType == VCD_SIG_TYPE.WIRE:
 59 |             self.format = self.format_bits
 60 |         elif varInfo.sigType == VCD_SIG_TYPE.ENUM or varInfo.sigType == VCD_SIG_TYPE.REAL:
 61 |             self.format = self.format_enum
 62 |         else:
 63 |             raise NotImplementedError(varInfo.sigType)
 64 | 
 65 |     def format_bit(self, newVal: str, updater, t, of):
 66 |         of.write(newVal)
 67 |         of.write(self.vcdId)
 68 |         of.write("\n")
 69 | 
 70 |     def format_bits(self, newVal: str, updater, t, of):
 71 |         of.write(newVal)
 72 |         of.write(" ")
 73 |         of.write(self.vcdId)
 74 |         of.write("\n")
 75 | 
 76 |     def format_enum(self, newVal: str, updater, t, of):
 77 |         of.write("s")
 78 |         of.write(newVal)
 79 |         of.write(" ")
 80 |         of.write(self.vcdId)
 81 |         of.write("\n")
 82 | 
 83 |     def format(self, newVal: str, updater, t, of):
 84 |         raise NotImplementedError()
 85 | 
 86 | 
 87 | def copy_signals_from_parser_recursion(parser_scope: Union[VcdVarScope, VcdVarParsingInfo], writer_scope: VcdVarWritingScope):
 88 |     if isinstance(parser_scope, VcdVarScope):
 89 |         with writer_scope.varScope(parser_scope.name) as m:
 90 |             for _, child in sorted(parser_scope.children.items(), key=lambda x: x[0]):
 91 |                 copy_signals_from_parser_recursion(child, m)
 92 |     else:
 93 |         writer_scope.addVar(parser_scope, parser_scope.name, parser_scope.sigType, parser_scope.width, AsIsFormatter())
 94 | 
 95 | 
 96 | def copy_signals_from_parser(vcd_in: VcdParser, vcd_out: VcdWriter):
 97 |     root = list(vcd_in.scope.children.values())[0]
 98 |     copy_signals_from_parser_recursion(root, vcd_out)
 99 |     vcd_out.enddefinitions()
100 | 
101 | 
102 | def aggregate_signal_updates_by_time(parser_scope: VcdVarScope, res: Dict[int, List[Tuple[VcdVarParsingInfo, str]]]):
103 |     if isinstance(parser_scope, VcdVarScope):
104 |         for _, child in sorted(parser_scope.children.items(), key=lambda x: x[0]):
105 |             aggregate_signal_updates_by_time(child, res)
106 |     else:
107 |         for (t, val) in parser_scope.data:
108 |             try:
109 |                 time_quantum = res[t]
110 |             except KeyError:
111 |                 time_quantum = res[t] = []
112 |             time_quantum.append((parser_scope, val))
113 | 
114 | 
115 | class VcdWriterTC(unittest.TestCase):
116 | 
117 |     def test_example0(self):
118 | 
119 |         out = StringIO()
120 |         vcd = VcdWriter(out)
121 |         d = datetime.strptime("2018-04-12 18:04:03.652880",
122 |                               "%Y-%m-%d %H:%M:%S.%f")
123 |         vcd.date(d)
124 |         vcd.timescale(1)
125 |         example_dump_values0(vcd)
126 | 
127 |         with open(os.path.join(BASE, "example0.vcd")) as f:
128 |             ref = f.read()
129 |             out = out.getvalue()
130 |             self.assertEqual(ref, out)
131 | 
132 |     def test_rewrite_AxiRegTC_test_write(self):
133 |         fIn = os.path.join(BASE, "AxiRegTC_test_write.vcd")
134 |         with open(fIn) as vcd_file:
135 |             vcd_in = VcdParser()
136 |             vcd_in.parse(vcd_file)
137 | 
138 |         out = StringIO()
139 |         vcd_out = VcdWriter(out)
140 |         d = datetime.strptime("2018-03-21 20:20:48.479224",
141 |                               "%Y-%m-%d %H:%M:%S.%f")
142 |         vcd_out.date(d)
143 |         vcd_out.timescale(1)
144 | 
145 |         copy_signals_from_parser(vcd_in, vcd_out)
146 | 
147 |         # for value writing we need to have it time order because
148 |         # we can not move back in time in VCD
149 |         all_updates = {}
150 |         aggregate_signal_updates_by_time(vcd_in.scope, all_updates)
151 |         for t, updates in sorted(all_updates.items()):
152 |             for sig, val in updates:
153 |                 vcd_out.logChange(t, sig, val, None)
154 | 
155 |         new_vcd_str = out.getvalue()
156 | 
157 |         # parse it again to check if format is correct
158 |         vcd_in = VcdParser()
159 |         vcd_in.parse_str(new_vcd_str)
160 | 
161 | 
162 | if __name__ == "__main__":
163 |     testLoader = unittest.TestLoader()
164 |     # suite = unittest.TestSuite([VcdWriterTC("test_example0")])
165 |     suite = testLoader.loadTestsFromTestCase(VcdWriterTC)
166 |     runner = unittest.TextTestRunner(verbosity=3)
167 |     runner.run(suite)
168 | 


--------------------------------------------------------------------------------
/tests/verilog2005-sample0.vcd:
--------------------------------------------------------------------------------
 1 | $date June 26, 1989 10:05:41
 2 | $end
 3 | $version VERILOG-SIMULATOR 1.0a
 4 | $end
 5 | $timescale 1 ns
 6 | $end
 7 | $scope module top $end
 8 | $scope module m1  $end
 9 | $var trireg 1 *@ net1 $end
10 | $var trireg 1 *# net2 $end
11 | $var trireg 1 *$ net3 $end
12 | $upscope $end
13 | $scope task t1 $end
14 | $var reg 32 (k accumulator[31:0] $end
15 | $var integer 32 {2 index  $end
16 | $upscope $end
17 | $upscope $end
18 | $enddefinitions $end
19 | #500
20 | $dumpvars
21 | x*@
22 | x*#
23 | x*$
24 | bx (k
25 | bx {2
26 | $end
27 | #505
28 | 0*@
29 | 1*#
30 | 1*$
31 | b10zx1110x11100 (k
32 | b1111000101z01x {2
33 | #510
34 | 0*$
35 | #520
36 | 1*$
37 | #530
38 | 0*$
39 | bz (k
40 | #535
41 | $dumpall   0*@   1*#   0*$
42 | bz (k
43 | b1111000101z01x {2
44 | $end
45 | #540
46 | 1*$
47 | #1000
48 | $dumpoff
49 | x*@
50 | x*#
51 | x*$
52 | bx (k
53 | bx {2
54 | $end
55 | #2000
56 | $dumpon
57 | z*@
58 | 1*#
59 | 0*$
60 | b0 (k
61 | bx {2
62 | $end
63 | #2010
64 | 1*$


--------------------------------------------------------------------------------
/tests/verilog2005-sample1.vcd:
--------------------------------------------------------------------------------
 1 | $date June 26, 1989 10:05:41 
 2 | $end
 3 | $version VERILOG-SIMULATOR 1.0a 
 4 | $end
 5 | $timescale 1 ns 
 6 | $end
 7 | $scope module top 
 8 | $end
 9 | $scope module m1  
10 | $end
11 | $var trireg 1 *@ net1 
12 | $end
13 | $var trireg 1 *# net2 
14 | $end
15 | $var trireg 1 *
16 | $ net3 
17 | $end
18 | $upscope 
19 | $end
20 | $scope task t1 
21 | $end
22 | $var reg 32 (k accumulator[31:0] 
23 | $end
24 | $var integer 32 {2 index  
25 | $end
26 | $upscope 
27 | $end
28 | $upscope 
29 | $end
30 | $enddefinitions 
31 | $end
32 | $comment  
33 | $dumpvars was executed at time '#500'.   All initial values are dumped at this time.
34 | $end
35 | 
36 | #500
37 | $dumpvars
38 | x*@
39 | x*#
40 | x*$
41 | bx (k
42 | bx {2
43 | $end
44 | #505 
45 | 0*@
46 | 1*#
47 | 1*$ 
48 | b10zx1110x11100 (k 
49 | b1111000101z01x {2
50 | #510 
51 | 0*$
52 | #520 
53 | 1*$
54 | #530 
55 | 0*$ 
56 | bz (k
57 | #535 
58 | $dumpall   0*@   1*#   0*$
59 | 
60 | bz (k
61 | b1111000101z01x {2
62 | $end
63 | #540 
64 | 1*$
65 | #1000
66 | $dumpoff
67 | x*@ 
68 | x*# 
69 | x*$ 
70 | bx (k 
71 | bx {2 
72 | $end
73 | #2000
74 | $dumpon
75 | z*@ 
76 | 1*# 
77 | 0*$ 
78 | b0 (k 
79 | bx {2 
80 | $end
81 | #2010
82 | 1*$
83 |  
84 |  


--------------------------------------------------------------------------------