├── .gitignore ├── README.md ├── Verilog没有葵花宝典 ├── Doc │ ├── VLSI_Ch9_CMOS逻辑电路的高级技术_2017.pdf │ ├── coding_guidelines.pdf │ ├── hdlcv.pdf │ ├── 低功耗设计方法.pptx │ └── 相同面积的与非门和或非门谁快、.pdf ├── Verilog没有葵花宝典打卡day1.md ├── Verilog没有葵花宝典打卡day10.md ├── Verilog没有葵花宝典打卡day11.md ├── Verilog没有葵花宝典打卡day2.md ├── Verilog没有葵花宝典打卡day3.md ├── Verilog没有葵花宝典打卡day4.md ├── Verilog没有葵花宝典打卡day5.md ├── Verilog没有葵花宝典打卡day6.md ├── Verilog没有葵花宝典打卡day7.md ├── Verilog没有葵花宝典打卡day8.md └── Verilog没有葵花宝典打卡day9.md ├── ip_lib ├── Readme构建自己的IP库，搭建起你的数字积木.md ├── rtl │ ├── .complex_mult.v.swp │ ├── ALU_Design_Function │ │ ├── ALU_Design_8.v │ │ ├── ALU_Design_Define.v │ │ ├── ALU_Design_Function.v │ │ ├── ALU_Top.v │ │ ├── key.v │ │ └── key_scan_design.v │ ├── ALU_Design_Task │ │ ├── ALU_Design_8.v │ │ ├── ALU_Design_Define.v │ │ ├── ALU_Design_Task.v │ │ ├── ALU_Top.v │ │ ├── key.v │ │ └── key_scan_design.v │ ├── Carry_Look_Ahead_Adder │ │ ├── full_Adder4.v │ │ ├── full_adder16.v │ │ ├── full_adder32.v │ │ └── full_adder64.v │ ├── Combination Logic │ │ ├── BCD_5121_8421.v │ │ ├── BCD_8421_BCD_2421.v │ │ ├── BCD_8421_BCD_3.v │ │ ├── BCD_D.v │ │ ├── adder_one.v │ │ ├── binbcd.v │ │ ├── choose_four_one │ │ │ ├── M.v │ │ │ └── four_one.v │ │ ├── eight_three.v │ │ ├── five_one.v │ │ ├── five_voter.v │ │ ├── four_adder.v │ │ ├── four_compare.v │ │ ├── four_one.v │ │ ├── four_voter.v │ │ ├── mult.v │ │ ├── shifter.v │ │ ├── three_eight.v │ │ └── voter3.v │ ├── Cordic_Test │ │ ├── Cordic_Arctan.v │ │ ├── Cordic_Cos_Sin.v │ │ └── Cordic_Top.v │ ├── DDS │ │ ├── cos.txt │ │ ├── dds_top.v │ │ ├── sin.txt │ │ ├── single_port_rom.v │ │ ├── square.txt │ │ └── triangular.txt │ ├── I2C Control EEPROM │ │ ├── Ctrl_I2C_Op.v │ │ ├── I2C_Ctrl_EEPROM.v │ │ ├── Seven_Seg_Display.v │ │ └── Top.v │ ├── Memory │ │ ├── dp_sram.v │ │ ├── sram.v │ │ └── ture_dp_sram.v │ ├── Monocycle_CPU_Design │ │ ├── ALU_Design.v │ │ ├── Control_Unit.v │ │ ├── Data_Mem.v │ │ ├── Inst_Decode.v │ │ ├── Inst_Exe.v │ │ ├── Inst_Mem.v │ │ ├── Monocycle_CPU_Design.v │ │ ├── Program_Count.v │ │ ├── Regfile.v │ │ ├── Shift.v │ │ ├── full_Adder4.v │ │ ├── full_adder16.v │ │ ├── full_adder32.v │ │ └── include.v │ ├── Mult_function │ │ ├── beep.v │ │ ├── clock_set.v │ │ ├── cnt_clk.v │ │ ├── cnt_second.v │ │ ├── cpu.v │ │ ├── key_scan.v │ │ ├── seven_seg_display.v │ │ ├── tb.v │ │ └── top.v │ ├── Sequential Logic │ │ ├── D.v │ │ ├── Mfour_count.v │ │ ├── count74LS161.v │ │ ├── count_74LS163.v │ │ ├── counter_8421_BCD.v │ │ ├── register_move.v │ │ ├── seven_display.v │ │ └── three_count.v │ ├── Simple_Calculator │ │ ├── Bin_BCD.v │ │ ├── Matrix_Key_Scan.v │ │ ├── Seven_Seg_Display.v │ │ ├── Simple_Caculator.v │ │ ├── Top.v │ │ └── test.v │ ├── complex_mult.v │ ├── lcd_qc12864b.v │ ├── signed_cmp.v │ └── signed_mult.v ├── sim │ ├── .tb_dds_top.v.swp │ ├── tb_complex_mult.v │ ├── tb_dds_top.v │ └── tb_ram.v ├── vc │ ├── .dds.f.swp │ ├── complex_mult.f │ ├── dds.f │ └── ram.f └── work │ ├── csrc │ ├── 5NrIB_d.o │ ├── 5NrI_d.o │ ├── Makefile │ ├── Makefile.hsopt │ ├── SIM_l.o │ ├── _csrc0.so │ ├── _csrc1.so │ ├── _vcs_const_SIM_0.incr.dat │ ├── _vcs_etype_SIM_0.incr.dat │ ├── _vcsobj_1_1.a │ ├── _vcsobj_1_1.a.info │ ├── _vcsobj_archive_info_0.lst │ ├── _vcsobj_archive_info_1.lst │ ├── excl_vcsobj_1_0.a │ ├── excl_vcsobj_1_0.a.info │ ├── filelist │ ├── filelist.dpi │ ├── filelist.hsopt │ ├── filelist.hsopt.objs │ ├── filelist.pli │ ├── incr.sdb │ ├── product_timestamp │ ├── rmapats.c │ ├── rmapats.h │ ├── rmapats.m │ ├── rmapats.o │ ├── rmapats_mop.o │ ├── rmar.c │ ├── rmar.o │ └── vcspieces.incr │ ├── novas.conf │ ├── novas.rc │ ├── simv │ ├── simv.daidir │ ├── .vcs.timestamp.tmp │ ├── _csrc0.so │ ├── _csrc1.so │ ├── binmap.sdb │ ├── build_db │ ├── covg_defs │ ├── debug_dump │ │ ├── .version │ │ ├── HsimSigOptDb.sdb │ │ ├── dumpcheck.db │ │ ├── dve_debug.db.gz │ │ ├── fsearch │ │ │ ├── .create_fsearch_db │ │ │ ├── check_fsearch_db │ │ │ └── idents_NkuRnU.xml.gz │ │ ├── src_files_verilog │ │ ├── topmodules │ │ └── vir.sdb │ ├── elabmoddb.sdb │ ├── external_functions │ ├── nsparam.dat │ ├── pcxpxmr.dat │ ├── pre_vcsobj_1_1.so │ ├── prof.sdb │ ├── rmapats.dat │ ├── saifNetInfo.db │ ├── tt.sdb │ ├── uniqifyDidMap.dat │ ├── uniqifyModulesMap.dat │ ├── vcs_rebuild │ ├── vcselab_master_hsim_elabout.db │ ├── vcselab_misc_hsdef.db │ ├── vcselab_misc_hsim_checkloop_I2Oedge.db │ ├── vcselab_misc_hsim_elab.db │ ├── vcselab_misc_hsim_fegate.db │ ├── vcselab_misc_hsim_lvl.db │ ├── vcselab_misc_hsim_name.db │ ├── vcselab_misc_hsim_uds.db │ ├── vcselab_misc_midd.db │ ├── vcselab_misc_mnmn.db │ ├── vcselab_misc_partition.db │ ├── vcselab_misc_tCEYNb │ ├── vcselab_misc_vcselabref.db │ └── vcselab_misc_vpdnodenums │ ├── ucli.key │ ├── verdiLog │ ├── .13952IC.conf │ ├── .20760IC.conf │ ├── .4443IC.conf │ ├── ToNetlist.log │ ├── compiler.log │ ├── exe.log │ ├── fsdb.log │ ├── novas.log │ ├── novas.rc │ ├── pes.bat │ ├── turbo.log │ ├── verdi.cmd │ └── verdi.cmd.bak │ └── vfastLog │ ├── pes.bat │ └── turbo.log └── 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