├── Makefile ├── README.md ├── prj └── xilinx │ ├── template.cache │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf │ ├── template.hw │ └── template.lpr │ ├── template.ip_user_files │ └── README.txt │ ├── template.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── testbench.tcl │ │ ├── testbench_behav.wdb │ │ ├── testbench_vlog.prj │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_30588.backup.jou │ │ ├── webtalk_30588.backup.log │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── testbench_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ └── xil_defaultlib │ │ │ ├── @line_@shift_@r@a@m.sdb │ │ │ ├── @matrix_@generate_3@x3.sdb │ │ │ ├── @r@a@mshift_taps.sdb │ │ │ ├── @sqrt.sdb │ │ │ ├── @video_@image_@simulate_@c@m@o@s.sdb │ │ │ ├── glbl.sdb │ │ │ ├── testbench.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xvlog.log │ │ └── xvlog.pb │ └── template.xpr └── user ├── TOP.v ├── sim ├── Video_Image_Simulate_CMOS.v ├── Video_Image_Simulate_tb.v └── testbench.v └── src ├── Malloc └── Shift_RAM │ ├── Line_Shift_RAM.v │ └── RAMshift_taps.v ├── Math ├── Sort3.v └── Sqrt.v └── Video_Image_Processor ├── Advance_Apply ├── Image_XYCrop.v └── Parallel_Line_Detector.v └── Basic_Apply ├── Dat ├── RAW8_RGB888.v └── RGB888_YCbCr444.v ├── Detector ├── Dilation_Detector.v ├── Erosion_Detector.v └── Sobel_Edge_Detector.v ├── Filter ├── Gray_Median_Filter.v └── Median_Filter_3X3.v ├── Matrix ├── Matrix_Generate_3X3.v └── Matrix_Generate_3X3_Buf.v └── Video_Image_Processor.v /Makefile: -------------------------------------------------------------------------------- 1 | ////////////////////////////Prj Info//////////////////////////// 2 | #/*****************/which project you want to build,you can choose[ xilinx alter modelsim ] 3 | xilinx 4 | ///////////////////////////LIB Config/////////////////////////// 5 | #/*****************/if include Soc,you can choose none[ cortexM0 cortexM3 cortexA9 ] 6 | Soc 7 | none 8 | #/*****************/if include DSP,you can choose 0/1 9 | DSP 10 | 0 11 | #/*****************/if include Driver,you can choose 0/1 12 | Driver 13 | 0 14 | ///////////////////////////Run Config/////////////////////////// 15 | #/*****************/Whether to display logs during compilation yes/no 16 | Showlog 17 | no 18 | #/*****************/download typle TEST BOOT 19 | Download 20 | TEST 21 | #/*****************/flash typle 22 | Flash 23 | TEST 24 | #/*****************/The info of device Note: auto generate do not touch 25 | Device 26 | xc7z020clg400-2 27 | xc7z020clg400-2 28 | xc7z020clg400-2 29 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 9 | 10 | # Image_sim 11 | 12 | 基于FPGA的图像处理模块（出自于crazybingo）（将里面的Intel的shift_RAM以及altsqrt的IP核换为Verilog来实现，方便实现跨平台移植） 13 | 14 | 含有图像的仿真模块 15 | 16 | 文件结构基于vscode下FPGA_Develop_Support插件 17 | -------------------------------------------------------------------------------- /prj/xilinx/template.cache/wt/gui_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:32:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:31:00:00 5 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:33:00:00 6 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3132:00:00 7 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:36:00:00 8 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:3234:00:00 9 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:39:00:00 10 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:34:00:00 11 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:34:00:00 12 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:35:00:00 13 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:3337:00:00 14 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e73636f70657370616e656c5f73696d756c6174655f73636f70655f7461626c65:3738:00:00 15 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:3132:00:00 16 | eof:2119516093 17 | -------------------------------------------------------------------------------- /prj/xilinx/template.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:38:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:34:00:00 5 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:3233:00:00 6 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b70726f6a6563746d616e61676572:31:00:00 7 | eof:1597584850 8 | -------------------------------------------------------------------------------- /prj/xilinx/template.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c54434c4d6f6465:5 4 | eof: 5 | -------------------------------------------------------------------------------- /prj/xilinx/template.cache/wt/webtalk_pa.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
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48 | 49 | 50 | -------------------------------------------------------------------------------- /prj/xilinx/template.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:2427094519 5 | -------------------------------------------------------------------------------- /prj/xilinx/template.hw/template.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /prj/xilinx/template.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2018.3 (64-bit) 4 | REM 5 | REM Filename : compile.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for compiling the simulation design source files 8 | REM 9 | REM Generated by Vivado on Thu Apr 02 14:30:09 +0800 2020 10 | REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 11 | REM 12 | REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: compile.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xvlog --incr --relax -prj testbench_vlog.prj" 18 | call xvlog --incr --relax -prj testbench_vlog.prj -log xvlog.log 19 | call type xvlog.log > compile.log 20 | if "%errorlevel%"=="1" goto END 21 | if "%errorlevel%"=="0" goto SUCCESS 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/compile.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Malloc/Shift_RAM/Line_Shift_RAM.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module Line_Shift_RAM 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Video_Image_Processor/Basic_Apply/Matrix/Matrix_Generate_3X3.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module Matrix_Generate_3X3 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Malloc/Shift_RAM/RAMshift_taps.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module RAMshift_taps 7 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/sim/Video_Image_Simulate_CMOS.v" into library xil_defaultlib 8 | INFO: [VRFC 10-311] analyzing module Video_Image_Simulate_CMOS 9 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/sim/testbench.v" into library xil_defaultlib 10 | INFO: [VRFC 10-311] analyzing module testbench 11 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2018.3 (64-bit) 4 | REM 5 | REM Filename : elaborate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for elaborating the compiled design 8 | REM 9 | REM Generated by Vivado on Thu Apr 02 14:30:11 +0800 2020 10 | REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 11 | REM 12 | REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: elaborate.bat 15 | REM 16 | REM **************************************************************************** 17 | call xelab -wto c9f625389fa24240af78ff8848025c90 --incr --debug typical --relax --mt 6 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log 18 | if "%errorlevel%"=="0" goto SUCCESS 19 | if "%errorlevel%"=="1" goto END 20 | :END 21 | exit 1 22 | :SUCCESS 23 | exit 0 24 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2018.3 2 | Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. 3 | Running: D:/APP/vivado_18_3/Vivado/2018.3/bin/unwrapped/win64.o/xelab.exe -wto c9f625389fa24240af78ff8848025c90 --incr --debug typical --relax --mt 6 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log 4 | Using 6 slave threads. 5 | Starting static elaboration 6 | Completed static elaboration 7 | Starting simulation data flow analysis 8 | WARNING: [XSIM 43-4099] "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Malloc/Shift_RAM/Line_Shift_RAM.v" Line 1. Module Line_Shift_RAM(RAM_Length=16) doesn't have a timescale but at least one module in design has a timescale. 9 | Completed simulation data flow analysis 10 | Time Resolution for simulation is 1ps 11 | Compiling module xil_defaultlib.Video_Image_Simulate_CMOS(IMG_HD... 12 | Compiling module xil_defaultlib.RAMshift_taps(TOTAL_RAM_Length=1... 13 | Compiling module xil_defaultlib.Line_Shift_RAM(RAM_Length=16) 14 | Compiling module xil_defaultlib.Matrix_Generate_3X3(IMG_HDISP=16... 15 | Compiling module xil_defaultlib.testbench 16 | Compiling module xil_defaultlib.glbl 17 | Built simulation snapshot testbench_behav 18 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | 11 | //-------- STARTUP Globals -------------- 12 | wire GSR; 13 | wire GTS; 14 | wire GWE; 15 | wire PRLD; 16 | tri1 p_up_tmp; 17 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 18 | 19 | wire PROGB_GLBL; 20 | wire CCLKO_GLBL; 21 | wire FCSBO_GLBL; 22 | wire [3:0] DO_GLBL; 23 | wire [3:0] DI_GLBL; 24 | 25 | reg GSR_int; 26 | reg GTS_int; 27 | reg PRLD_int; 28 | 29 | //-------- JTAG Globals -------------- 30 | wire JTAG_TDO_GLBL; 31 | wire JTAG_TCK_GLBL; 32 | wire JTAG_TDI_GLBL; 33 | wire JTAG_TMS_GLBL; 34 | wire JTAG_TRST_GLBL; 35 | 36 | reg JTAG_CAPTURE_GLBL; 37 | reg JTAG_RESET_GLBL; 38 | reg JTAG_SHIFT_GLBL; 39 | reg JTAG_UPDATE_GLBL; 40 | reg JTAG_RUNTEST_GLBL; 41 | 42 | reg JTAG_SEL1_GLBL = 0; 43 | reg JTAG_SEL2_GLBL = 0 ; 44 | reg JTAG_SEL3_GLBL = 0; 45 | reg JTAG_SEL4_GLBL = 0; 46 | 47 | reg JTAG_USER_TDO1_GLBL = 1'bz; 48 | reg JTAG_USER_TDO2_GLBL = 1'bz; 49 | reg JTAG_USER_TDO3_GLBL = 1'bz; 50 | reg JTAG_USER_TDO4_GLBL = 1'bz; 51 | 52 | assign (strong1, weak0) GSR = GSR_int; 53 | assign (strong1, weak0) GTS = GTS_int; 54 | assign (weak1, weak0) PRLD = PRLD_int; 55 | 56 | initial begin 57 | GSR_int = 1'b1; 58 | PRLD_int = 1'b1; 59 | #(ROC_WIDTH) 60 | GSR_int = 1'b0; 61 | PRLD_int = 1'b0; 62 | end 63 | 64 | initial begin 65 | GTS_int = 1'b1; 66 | #(TOC_WIDTH) 67 | GTS_int = 1'b0; 68 | end 69 | 70 | endmodule 71 | `endif 72 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2018.3 (64-bit) 4 | REM 5 | REM Filename : simulate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for simulating the design by launching the simulator 8 | REM 9 | REM Generated by Vivado on Thu Apr 02 13:48:05 +0800 2020 10 | REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 11 | REM 12 | REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: simulate.bat 15 | REM 16 | REM **************************************************************************** 17 | call xsim testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch testbench.tcl -log simulate.log 18 | if "%errorlevel%"=="0" goto SUCCESS 19 | if "%errorlevel%"=="1" goto END 20 | :END 21 | exit 1 22 | :SUCCESS 23 | exit 0 24 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2018.3 2 | Time resolution is 1 ps 3 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/testbench.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/testbench_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/testbench_behav.wdb -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/testbench_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../../../user/src/Malloc/Shift_RAM/Line_Shift_RAM.v" \ 4 | "../../../../../../user/src/Video_Image_Processor/Basic_Apply/Matrix/Matrix_Generate_3X3.v" \ 5 | "../../../../../../user/src/Malloc/Shift_RAM/RAMshift_taps.v" \ 6 | "../../../../../../user/sim/Video_Image_Simulate_CMOS.v" \ 7 | "../../../../../../user/sim/testbench.v" \ 8 | 9 | # compile glbl module 10 | verilog xil_defaultlib "glbl.v" 11 | 12 | # Do not sort compile order 13 | nosort 14 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.3 (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Wed Apr 1 16:21:19 2020 6 | # Process ID: 16424 7 | # Current directory: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/webtalk.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.3 (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Wed Apr 1 16:21:19 2020 6 | # Process ID: 16424 7 | # Current directory: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace 13 | webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 83.313 ; gain = 1.070 14 | INFO: [Common 17-206] Exiting Webtalk at Wed Apr 1 16:21:24 2020... 15 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/webtalk_30588.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.3 (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Wed Apr 1 16:20:46 2020 6 | # Process ID: 30588 7 | # Current directory: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/webtalk_30588.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.3 (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Wed Apr 1 16:20:46 2020 6 | # Process ID: 30588 7 | # Current directory: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/project/My_FPGA/TCL_project/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace 13 | webtalk_transmit: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 83.496 ; gain = 1.219 14 | INFO: [Common 17-206] Exiting Webtalk at Wed Apr 1 16:20:51 2020... 15 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "c9f625389fa24240af78ff8848025c90" --incr --debug "typical" --relax --mt "6" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "testbench_behav" "xil_defaultlib.testbench" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/obj/xsim_0.win64.obj -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/obj/xsim_1.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /**********************************************************************/ 12 | 13 | 14 | #include "iki.h" 15 | #include 16 | #include 17 | #ifdef __GNUC__ 18 | #include 19 | #else 20 | #include 21 | #define alloca _alloca 22 | #endif 23 | /**********************************************************************/ 24 | /* ____ ____ */ 25 | /* / /\/ / */ 26 | /* /___/ \ / */ 27 | /* \ \ \/ */ 28 | /* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ 29 | /* / / All Right Reserved. */ 30 | /* /---/ /\ */ 31 | /* \ \ / \ */ 32 | /* \___\/\___\ */ 33 | /**********************************************************************/ 34 | 35 | 36 | #include "iki.h" 37 | #include 38 | #include 39 | #ifdef __GNUC__ 40 | #include 41 | #else 42 | #include 43 | #define alloca _alloca 44 | #endif 45 | typedef void (*funcp)(char *, char *); 46 | extern int main(int, char**); 47 | extern void execute_2(char*, char *); 48 | extern void execute_27(char*, char *); 49 | extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); 50 | extern void execute_48(char*, char *); 51 | extern void execute_49(char*, char *); 52 | extern void execute_50(char*, char *); 53 | extern void execute_51(char*, char *); 54 | extern void execute_52(char*, char *); 55 | extern void execute_53(char*, char *); 56 | extern void execute_54(char*, char *); 57 | extern void execute_55(char*, char *); 58 | extern void execute_56(char*, char *); 59 | extern void execute_57(char*, char *); 60 | extern void execute_58(char*, char *); 61 | extern void execute_5(char*, char *); 62 | extern void execute_6(char*, char *); 63 | extern void execute_7(char*, char *); 64 | extern void execute_8(char*, char *); 65 | extern void execute_9(char*, char *); 66 | extern void execute_10(char*, char *); 67 | extern void execute_32(char*, char *); 68 | extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); 69 | extern void execute_36(char*, char *); 70 | extern void execute_12(char*, char *); 71 | extern void execute_24(char*, char *); 72 | extern void execute_25(char*, char *); 73 | extern void execute_41(char*, char *); 74 | extern void execute_42(char*, char *); 75 | extern void execute_44(char*, char *); 76 | extern void execute_45(char*, char *); 77 | extern void execute_39(char*, char *); 78 | extern void execute_40(char*, char *); 79 | extern void execute_15(char*, char *); 80 | extern void execute_16(char*, char *); 81 | extern void execute_17(char*, char *); 82 | extern void execute_18(char*, char *); 83 | extern void execute_37(char*, char *); 84 | extern void execute_29(char*, char *); 85 | extern void execute_30(char*, char *); 86 | extern void execute_31(char*, char *); 87 | extern void execute_59(char*, char *); 88 | extern void execute_60(char*, char *); 89 | extern void execute_61(char*, char *); 90 | extern void execute_62(char*, char *); 91 | extern void execute_63(char*, char *); 92 | extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); 93 | extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); 94 | funcp funcTab[47] = {(funcp)execute_2, (funcp)execute_27, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_32, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_36, (funcp)execute_12, (funcp)execute_24, (funcp)execute_25, (funcp)execute_41, (funcp)execute_42, (funcp)execute_44, (funcp)execute_45, (funcp)execute_39, (funcp)execute_40, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_37, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_0}; 95 | const int NumRelocateId= 47; 96 | 97 | void relocate(char *dp) 98 | { 99 | iki_relocate(dp, "xsim.dir/testbench_behav/xsim.reloc", (void **)funcTab, 47); 100 | 101 | /*Populate the transaction function pointer field in the whole net structure */ 102 | } 103 | 104 | void sensitize(char *dp) 105 | { 106 | iki_sensitize(dp, "xsim.dir/testbench_behav/xsim.reloc"); 107 | } 108 | 109 | void simulate(char *dp) 110 | { 111 | iki_schedule_processes_at_time_zero(dp, "xsim.dir/testbench_behav/xsim.reloc"); 112 | // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net 113 | iki_execute_processes(); 114 | 115 | // Schedule resolution functions for the multiply driven Verilog nets that have strength 116 | // Schedule transaction functions for the singly driven Verilog nets that have strength 117 | 118 | } 119 | #include "iki_bridge.h" 120 | void relocate(char *); 121 | 122 | void sensitize(char *); 123 | 124 | void simulate(char *); 125 | 126 | extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); 127 | extern void implicit_HDL_SCinstatiate(); 128 | 129 | extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; 130 | extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; 131 | 132 | int main(int argc, char **argv) 133 | { 134 | iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; 135 | iki_set_sv_type_file_path_name("xsim.dir/testbench_behav/xsim.svtype"); 136 | iki_set_crvs_dump_file_path_name("xsim.dir/testbench_behav/xsim.crvsdump"); 137 | void* design_handle = iki_create_design("xsim.dir/testbench_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); 138 | iki_set_rc_trial_count(100); 139 | (void) design_handle; 140 | return iki_simulate_design(); 141 | } 142 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/obj/xsim_1.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/obj/xsim_1.win64.obj -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/.xsim_webtallk.info: -------------------------------------------------------------------------------- 1 | 1585729244 2 | 1585729277 3 | 19 4 | 1 5 | c9f625389fa24240af78ff8848025c90 6 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.html: -------------------------------------------------------------------------------- 1 | Device Usage Statistics Report 2 |

XSIM Usage Report


3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
software_version_and_target_device
betaFALSEbuild_version2405991
date_generatedWed Apr 1 16:21:17 2020os_platformWIN64
product_versionXSIM v2018.3 (64-bit)project_idc9f625389fa24240af78ff8848025c90
project_iteration2random_idb707f647-c58c-433b-a1dd-56c6716d2eef
registration_idb707f647-c58c-433b-a1dd-56c6716d2eefroute_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 |
user_environment
cpu_nameIntel(R) Core(TM) i7-7700HQ CPU @ 2.80GHzcpu_speed2808 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

30 | 31 | 32 |
vivado_usage

33 | 34 | 35 | 41 | 51 |
xsim
36 | 37 | 38 | 39 |
command_line_options
command=xsim
40 |
42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 |
usage
iteration=1runtime=1 ussimulation_memory=5952_KBsimulation_time=0.05_sec
trace_waveform=true
50 |

52 | 53 | 54 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.wdm: -------------------------------------------------------------------------------- 1 | version = "1.0"; 2 | clients = 3 | ( 4 | { client_name = "project"; 5 | rules = ( 6 | { 7 | context="software_version_and_target_device"; 8 | xml_map="software_version_and_target_device"; 9 | html_map="software_version_and_target_device"; 10 | html_format="UserEnvStyle"; 11 | }, 12 | { 13 | context="user_environment"; 14 | xml_map="user_environment"; 15 | html_map="user_environment"; 16 | html_format="UserEnvStyle"; 17 | } 18 | ); 19 | }, 20 | 21 | { client_name = "xsim"; 22 | rules = ( 23 | { 24 | context="xsim\\command_line_options"; 25 | xml_map="xsim\\command_line_options"; 26 | html_map="xsim\\command_line_options"; 27 | html_format="UnisimStatsStyle"; 28 | }, 29 | { 30 | context="xsim\\usage"; 31 | xml_map="xsim\\usage"; 32 | html_map="xsim\\usage"; 33 | html_format="UnisimStatsStyle"; 34 | } 35 | ); 36 | } 37 | ); 38 | 39 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 |
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36 | 37 | 38 | 39 | 40 | 41 |
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43 |
44 | 45 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl: -------------------------------------------------------------------------------- 1 | webtalk_init -webtalk_dir D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/ 2 | webtalk_register_client -client project 3 | webtalk_add_data -client project -key date_generated -value "Thu Apr 2 14:32:18 2020" -context "software_version_and_target_device" 4 | webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" 5 | webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" 6 | webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" 7 | webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" 8 | webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" 9 | webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" 10 | webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" 11 | webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" 12 | webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" 13 | webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" 14 | webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" 15 | webtalk_add_data -client project -key random_id -value "b707f647-c58c-433b-a1dd-56c6716d2eef" -context "software_version_and_target_device" 16 | webtalk_add_data -client project -key project_id -value "c9f625389fa24240af78ff8848025c90" -context "software_version_and_target_device" 17 | webtalk_add_data -client project -key project_iteration -value "18" -context "software_version_and_target_device" 18 | webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" 19 | webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" 20 | webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-7700HQ CPU @ 2.80GHz" -context "user_environment" 21 | webtalk_add_data -client project -key cpu_speed -value "2808 MHz" -context "user_environment" 22 | webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" 23 | webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment" 24 | webtalk_register_client -client xsim 25 | webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" 26 | webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" 27 | webtalk_add_data -client xsim -key runtime -value "31 us" -context "xsim\\usage" 28 | webtalk_add_data -client xsim -key iteration -value "1" -context "xsim\\usage" 29 | webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" 30 | webtalk_add_data -client xsim -key Simulation_Memory -value "6104_KB" -context "xsim\\usage" 31 | webtalk_transmit -clientid 324807266 -regid "" -xml D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" 32 | webtalk_terminate 33 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.dbg -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.mem: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.mem -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.reloc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.reloc -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.rlx: -------------------------------------------------------------------------------- 1 | 2 | { 3 | crc : 865015806690466103 , 4 | ccp_crc : 0 , 5 | cmdline : " -wto c9f625389fa24240af78ff8848025c90 --incr --debug typical --relax --mt 6 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl" , 6 | buildDate : "Dec 7 2018" , 7 | buildTime : "00:33:28" , 8 | linkCmd : "D:\\APP\\vivado_18_3\\Vivado\\2018.3\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/testbench_behav/xsimk.exe\" \"xsim.dir/testbench_behav/obj/xsim_0.win64.obj\" \"xsim.dir/testbench_behav/obj/xsim_1.win64.obj\" -L\"D:\\APP\\vivado_18_3\\Vivado\\2018.3\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.rtti: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.rtti -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsim.svtype: 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/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VHDL_PROCEDURE_SCOPE_FILTER=false 11 | VERILOG_MODULE_SCOPE_FILTER=true 12 | VERILOG_PACKAGE_SCOPE_FILTER=false 13 | VERILOG_BLOCK_SCOPE_FILTER=false 14 | VERILOG_TASK_SCOPE_FILTER=false 15 | VERILOG_PROCESS_SCOPE_FILTER=false 16 | INPUT_OBJECT_FILTER=true 17 | OUTPUT_OBJECT_FILTER=true 18 | INOUT_OBJECT_FILTER=true 19 | INTERNAL_OBJECT_FILTER=true 20 | CONSTANT_OBJECT_FILTER=true 21 | VARIABLE_OBJECT_FILTER=true 22 | SCOPE_NAME_COLUMN_WIDTH=253 23 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=90 24 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=117 25 | OBJECT_NAME_COLUMN_WIDTH=230 26 | OBJECT_VALUE_COLUMN_WIDTH=177 27 | OBJECT_DATA_TYPE_COLUMN_WIDTH=75 28 | PROCESS_NAME_COLUMN_WIDTH=75 29 | PROCESS_TYPE_COLUMN_WIDTH=75 30 | FRAME_INDEX_COLUMN_WIDTH=75 31 | FRAME_NAME_COLUMN_WIDTH=75 32 | FRAME_FILE_NAME_COLUMN_WIDTH=75 33 | FRAME_LINE_NUM_COLUMN_WIDTH=230 34 | LOCAL_NAME_COLUMN_WIDTH=177 35 | LOCAL_VALUE_COLUMN_WIDTH=75 36 | INPUT_LOCAL_FILTER=1 37 | OUTPUT_LOCAL_FILTER=1 38 | INOUT_LOCAL_FILTER=1 39 | INTERNAL_LOCAL_FILTER=1 40 | CONSTANT_LOCAL_FILTER=1 41 | VARIABLE_LOCAL_FILTER=1 42 | [Object Radixes] 43 | RADIX_0=unsigned /testbench/Matrix_Generate_3X3_8Bit_u/u_Line_Shift_RAM/RAMshfit_taps_u1/Delay_Length; 44 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsimcrash.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsimcrash.log -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsimk.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsimk.exe -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/testbench_behav/xsimk.exe -simmode gui -wdb testbench_behav.wdb -simrunnum 0 -socket 7709 2 | Design successfully loaded 3 | Design Loading Memory Usage: 5344 KB (Peak: 5344 KB) 4 | Design Loading CPU Usage: 46 ms 5 | Simulation completed 6 | Simulation Memory Usage: 6104 KB (Peak: 6104 KB) 7 | Simulation CPU Usage: 61 ms 8 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@line_@shift_@r@a@m.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@line_@shift_@r@a@m.sdb -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@matrix_@generate_3@x3.sdb: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@sqrt.sdb -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@video_@image_@simulate_@c@m@o@s.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@video_@image_@simulate_@c@m@o@s.sdb -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/testbench.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/testbench.sdb -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx: -------------------------------------------------------------------------------- 1 | 0.6 2 | 2018.3 3 | Dec 7 2018 4 | 00:33:28 5 | D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/prj/Xilinx/template.sim/sim_1/behav/xsim/glbl.v,1544155481,verilog,,,,glbl,,,,,,,, 6 | D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/sim/Video_Image_Simulate_CMOS.v,1585648740,verilog,,D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/sim/testbench.v,,Video_Image_Simulate_CMOS,,,,,,,, 7 | D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/sim/testbench.v,1585806394,verilog,,,,testbench,,,,,,,, 8 | D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Malloc/Shift_RAM/Line_Shift_RAM.v,1585807197,verilog,,D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Video_Image_Processor/Basic_Apply/Matrix/Matrix_Generate_3X3.v,,Line_Shift_RAM,,,,,,,, 9 | D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Malloc/Shift_RAM/RAMshift_taps.v,1585808948,verilog,,D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/sim/Video_Image_Simulate_CMOS.v,,RAMshift_taps,,,,,,,, 10 | D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Video_Image_Processor/Basic_Apply/Matrix/Matrix_Generate_3X3.v,1585720564,verilog,,D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Malloc/Shift_RAM/RAMshift_taps.v,,Matrix_Generate_3X3,,,,,,,, 11 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xsim.ini: -------------------------------------------------------------------------------- 1 | xil_defaultlib=xsim.dir/xil_defaultlib 2 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xvlog.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Malloc/Shift_RAM/Line_Shift_RAM.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module Line_Shift_RAM 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Video_Image_Processor/Basic_Apply/Matrix/Matrix_Generate_3X3.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module Matrix_Generate_3X3 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/src/Malloc/Shift_RAM/RAMshift_taps.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module RAMshift_taps 7 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/sim/Video_Image_Simulate_CMOS.v" into library xil_defaultlib 8 | INFO: [VRFC 10-311] analyzing module Video_Image_Simulate_CMOS 9 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/project/FPGA/My_FPGA/TCL_project/Sim/Image_sim/user/sim/testbench.v" into library xil_defaultlib 10 | INFO: [VRFC 10-311] analyzing module testbench 11 | -------------------------------------------------------------------------------- /prj/xilinx/template.sim/sim_1/behav/xsim/xvlog.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Nitcloud/Image_sim/a8ddda1663e93292acd9cb758c9832e432fffc79/prj/xilinx/template.sim/sim_1/behav/xsim/xvlog.pb -------------------------------------------------------------------------------- /prj/xilinx/template.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 178 | 179 | 180 | 181 | 182 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 216 | 217 | 218 | 219 | 220 | 222 | 223 | 224 | 225 | 226 | 229 | 230 | 232 | 233 | 235 | 236 | 238 | 239 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | default_dashboard 296 | 297 | 298 | 299 | 300 | 301 | 302 | -------------------------------------------------------------------------------- /user/TOP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module TOP #( 3 | parameter RAW2RG888_YUV444 = "ON", 4 | parameter GRAY_MEDIUM = "ON", 5 | parameter GRAY_SOBEL = "ON", 6 | parameter GRAY_EROSION = "ON", 7 | parameter GRAY_DILATION = "ON", 8 | parameter IMG_HDISP = 11'd640, //640*480 9 | parameter IMG_VDISP = 11'd480 10 | ) ( 11 | //global clock 12 | input clk, //cmos video pixel clock 13 | input rst_n, //global reset 14 | 15 | //Image data prepred to be processd 16 | input per_frame_vsync, //Prepared Image data vsync valid signal 17 | input per_frame_href, //Prepared Image data href vaild signal 18 | input [7:0] per_img_RAW, //Prepared Image data of YCbCr 4:2:2 {CbY} {CrY} 19 | 20 | //Image data has been processd 21 | output post_frame_vsync, //Processed Image data vsync valid signal 22 | output post_frame_href, //Processed Image data href vaild signal 23 | output [7:0] post_img_Gray, //Processed Image Gray output 24 | 25 | //user interface 26 | input [7:0] Sobel_Threshold //Sobel Threshold for image edge detect 27 | ); 28 | 29 | Video_Image_Processor #( 30 | .RAW2RG888_YUV444 ( "ON" ), 31 | .GRAY_MEDIUM ( "ON" ), 32 | .GRAY_SOBEL ( "ON" ), 33 | .GRAY_EROSION ( "ON" ), 34 | .GRAY_DILATION ( "ON" ), 35 | .IMG_HDISP ( IMG_HDISP ), 36 | .IMG_VDISP ( IMG_VDISP ) 37 | ) u_Video_Image_Processor ( 38 | .clk ( clk ), 39 | .rst_n ( rst_n ), 40 | .per_frame_vsync ( per_frame_vsync ), 41 | .per_frame_href ( per_frame_href ), 42 | .per_img_RAW ( per_img_RAW ), 43 | .Sobel_Threshold ( Sobel_Threshold ), 44 | 45 | .post_frame_vsync ( post_frame_vsync ), 46 | .post_frame_href ( post_frame_href ), 47 | .post_img_Gray ( post_img_Gray ) 48 | ); 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /user/sim/Video_Image_Simulate_CMOS.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Video_Image_Simulate_CMOS 3 | #( 4 | parameter CMOS_VSYNC_VALID = 1'b1, //H : Data Valid; L : Frame Sync(Set it by register) 5 | parameter [10:0] IMG_HDISP = 11'd640, //640*480 6 | parameter [10:0] IMG_VDISP = 11'd480 7 | ) 8 | ( 9 | //global reset 10 | input rst_n, 11 | 12 | //CMOS Camera interface and data output simulation 13 | input cmos_xclk, //cmos driver clock 14 | output cmos_pclk, //24MHz when rgb output, 12MHz when raw output 15 | output cmos_vsync, //L: vaild, H: invalid 16 | output reg cmos_href, //H: vaild, L: invalid 17 | output reg [7:0] cmos_data //8 bits cmos data input 18 | ); 19 | wire clk = cmos_xclk; 20 | // wire rst_n = 1'b1; 21 | 22 | //------------------------------------------ 23 | //generate cmos timing 24 | /* 25 | localparam H_SYNC = 11'd80; 26 | localparam H_BACK = 11'd45; 27 | localparam H_DISP = IMG_HDISP; //11'd640 28 | localparam H_FRONT = 11'd19; 29 | localparam H_TOTAL = H_SYNC + H_BACK + H_DISP + H_FRONT; //10'd784 30 | 31 | localparam V_SYNC = 11'd3; 32 | localparam V_BACK = 11'd17; 33 | localparam V_DISP = IMG_VDISP; //11'd480 34 | localparam V_FRONT = 11'd10; 35 | localparam V_TOTAL = V_SYNC + V_BACK + V_DISP + V_FRONT; //10'd510 36 | */ 37 | //Just for simulation 38 | localparam H_SYNC = 11'd5; 39 | localparam H_BACK = 11'd5; 40 | localparam H_DISP = IMG_HDISP; 41 | localparam H_FRONT = 11'd5; 42 | localparam H_TOTAL = H_SYNC + H_BACK + H_DISP + H_FRONT; //10'd784 43 | 44 | localparam V_SYNC = 11'd1; 45 | localparam V_BACK = 11'd0; 46 | localparam V_DISP = IMG_VDISP; 47 | localparam V_FRONT = 11'd1; 48 | localparam V_TOTAL = V_SYNC + V_BACK + V_DISP + V_FRONT; //10'd510 49 | 50 | 51 | //---------------------------------- 52 | ////25MHz when rgb output, 12.5MHz when raw output 53 | reg pixel_cnt; 54 | always@(posedge clk or negedge rst_n) begin 55 | if(!rst_n) 56 | pixel_cnt <= 0; 57 | else 58 | pixel_cnt <= pixel_cnt + 1'b1; 59 | end 60 | wire pixel_flag = 1'b1; 61 | assign cmos_pclk = ~clk; 62 | 63 | 64 | 65 | //--------------------------------------------- 66 | //Horizontal counter 67 | reg [10:0] hcnt; 68 | always@(posedge clk or negedge rst_n) begin 69 | if(!rst_n) 70 | hcnt <= 11'd0; 71 | else if(pixel_flag) 72 | hcnt <= (hcnt < H_TOTAL - 1'b1) ? hcnt + 1'b1 : 11'd0; 73 | else 74 | hcnt <= hcnt; 75 | end 76 | 77 | //--------------------------------------------- 78 | //Vertical counter 79 | reg [10:0] vcnt; 80 | always@(posedge clk or negedge rst_n) begin 81 | if(!rst_n) 82 | vcnt <= 11'd0; 83 | else if(pixel_flag) begin 84 | if(hcnt == H_TOTAL - 1'b1) 85 | vcnt <= (vcnt < V_TOTAL - 1'b1) ? vcnt + 1'b1 : 11'd0; 86 | else 87 | vcnt <= vcnt; 88 | end 89 | else 90 | vcnt <= vcnt; 91 | end 92 | 93 | //--------------------------------------------- 94 | //Image data vsync valid signal 95 | reg cmos_vsync_r; 96 | always@(posedge clk or negedge rst_n) begin 97 | if(!rst_n) 98 | cmos_vsync_r <= 1'b0; //H: Vaild, L: inVaild 99 | else if(pixel_flag) begin 100 | if(vcnt <= V_SYNC - 1'b1) 101 | cmos_vsync_r <= 1'b0; //H: Vaild, L: inVaild 102 | else 103 | cmos_vsync_r <= 1'b1; //H: Vaild, L: inVaild 104 | end 105 | else 106 | cmos_vsync_r <= cmos_vsync_r; 107 | end 108 | assign cmos_vsync = (CMOS_VSYNC_VALID == 1'b0) ? ~cmos_vsync_r : cmos_vsync_r; 109 | 110 | 111 | //--------------------------------------------- 112 | //Image data href vaild signal 113 | wire frame_valid_ahead = ((vcnt >= V_SYNC + V_BACK && vcnt < V_SYNC + V_BACK + V_DISP && 114 | hcnt >= H_SYNC + H_BACK && hcnt < H_SYNC + H_BACK + H_DISP)) 115 | ? 1'b1 : 1'b0; 116 | always@(posedge clk or negedge rst_n) begin 117 | if(!rst_n) 118 | cmos_href <= 0; 119 | else if(pixel_flag) begin 120 | if(frame_valid_ahead) 121 | cmos_href <= 1; 122 | else 123 | cmos_href <= 0; 124 | end 125 | else 126 | cmos_href <= cmos_href; 127 | end 128 | 129 | //--------------------------------------------- 130 | //CMOS Camera data output 131 | always@(posedge clk or negedge rst_n) begin 132 | if(!rst_n) 133 | cmos_data <= 16'd0; 134 | else if(pixel_flag) begin 135 | if(frame_valid_ahead) 136 | cmos_data <= hcnt[7:0] - (8'd10 - 8'd1); 137 | else 138 | cmos_data <= 0; 139 | end 140 | else 141 | cmos_data <= cmos_data; 142 | end 143 | 144 | 145 | 146 | endmodule 147 | 148 | -------------------------------------------------------------------------------- /user/sim/Video_Image_Simulate_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module testbench; 3 | 4 | //------------------------------------------ 5 | //Generate 24MHz driver clock 6 | reg clk; 7 | localparam PERIOD2 = 41; //24MHz 8 | initial begin 9 | clk = 0; 10 | forever #(PERIOD2/2) 11 | clk = ~clk; 12 | end 13 | 14 | //------------------------------------------ 15 | //Generate global reset 16 | reg rst_n; 17 | task task_reset; begin 18 | rst_n = 0; 19 | repeat(2) @(negedge clk); 20 | rst_n = 1; 21 | end 22 | endtask 23 | wire sys_rst_n = rst_n; 24 | 25 | localparam IMG_HDISP = 16; 26 | localparam IMG_VDISP = 5; 27 | //----------------------------------------- 28 | //CMOS Camera interface and data output simulation 29 | wire cmos_xclk = clk; //24MHz drive clock 30 | wire cmos_pclk; //24MHz CMOS Pixel clock input 31 | wire cmos_vsync; //L: vaild, H: invalid 32 | wire cmos_href; //H: vaild, L: invalid 33 | wire [7:0] cmos_data; //8 bits cmos data input 34 | Video_Image_Simulate_CMOS #( 35 | .CMOS_VSYNC_VALID (1'b1), //VSYNC = 1 36 | .IMG_HDISP (IMG_HDISP), //640*480 37 | .IMG_VDISP (IMG_VDISP) 38 | ) u_Video_Image_Simulate_CMOS ( 39 | //global reset 40 | .rst_n (sys_rst_n), 41 | //CMOS Camera interface and data output simulation 42 | .cmos_xclk (cmos_xclk), //25MHz cmos clock 43 | .cmos_pclk (cmos_pclk), //25MHz when rgb output 44 | .cmos_vsync (cmos_vsync), //L: vaild, H: invalid 45 | .cmos_href (cmos_href), //H: vaild, L: invalid 46 | .cmos_data (cmos_data) //8 bits cmos data input 47 | ); 48 | 49 | wire matrix_frame_vsync; //Prepared Image data vsync valid signal 50 | wire matrix_frame_href; //Prepared Image data href vaild signal 51 | wire [7:0] matrix_p11, matrix_p12, matrix_p13; //3X3 Matrix output 52 | wire [7:0] matrix_p21, matrix_p22, matrix_p23; 53 | wire [7:0] matrix_p31, matrix_p32, matrix_p33; 54 | Matrix_Generate_3X3 #( 55 | .DATA_WIDTH (8), 56 | .IMG_HDISP (IMG_HDISP), //640*480 57 | .IMG_VDISP (IMG_VDISP) 58 | ) Matrix_Generate_3X3_8Bit_u ( 59 | //global clock 60 | .clk (cmos_pclk), //cmos video pixel clock 61 | .rst_n (sys_rst_n), //global reset 62 | 63 | //Image data prepred to be processd 64 | .per_frame_vsync (cmos_vsync), //Prepared Image data vsync valid signal 65 | .per_frame_href (cmos_href), //Prepared Image data href vaild signal 66 | .per_img_Data (cmos_data), //Prepared Image brightness input 67 | 68 | //Image data has been processd 69 | .matrix_frame_vsync (matrix_frame_vsync), //Processed Image data vsync valid signal 70 | .matrix_frame_href (matrix_frame_href), //Processed Image data href vaild signal 71 | .matrix_p11(matrix_p11), .matrix_p12(matrix_p12), .matrix_p13(matrix_p13), //3X3 Matrix output 72 | .matrix_p21(matrix_p21), .matrix_p22(matrix_p22), .matrix_p23(matrix_p23), 73 | .matrix_p31(matrix_p31), .matrix_p32(matrix_p32), .matrix_p33(matrix_p33) 74 | ); 75 | 76 | //--------------------------------------------- 77 | //testbench of the RTL 78 | task task_sysinit; begin 79 | 80 | end 81 | endtask 82 | 83 | //---------------------------------------------- 84 | initial begin 85 | task_sysinit; 86 | task_reset; 87 | 88 | end 89 | 90 | endmodule 91 | 92 | -------------------------------------------------------------------------------- /user/sim/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module testbench; 3 | 4 | //------------------------------------------ 5 | //Generate 24MHz driver clock 6 | reg clk; 7 | localparam PERIOD2 = 41; //24MHz 8 | initial begin 9 | clk = 0; 10 | forever #(PERIOD2/2) 11 | clk = ~clk; 12 | end 13 | 14 | //------------------------------------------ 15 | //Generate global reset 16 | reg rst_n; 17 | task task_reset; begin 18 | rst_n = 0; 19 | repeat(2) @(negedge clk); 20 | rst_n = 1; 21 | end 22 | endtask 23 | wire sys_rst_n = rst_n; 24 | 25 | localparam IMG_HDISP = 16; 26 | localparam IMG_VDISP = 5; 27 | //----------------------------------------- 28 | //CMOS Camera interface and data output simulation 29 | wire cmos_xclk = clk; //24MHz drive clock 30 | wire cmos_pclk; //24MHz CMOS Pixel clock input 31 | wire cmos_vsync; //L: vaild, H: invalid 32 | wire cmos_href; //H: vaild, L: invalid 33 | wire [7:0] cmos_data; //8 bits cmos data input 34 | Video_Image_Simulate_CMOS #( 35 | .CMOS_VSYNC_VALID (1'b1), //VSYNC = 1 36 | .IMG_HDISP (IMG_HDISP), //640*480 37 | .IMG_VDISP (IMG_VDISP) 38 | ) u_Video_Image_Simulate_CMOS ( 39 | //global reset 40 | .rst_n (sys_rst_n), 41 | //CMOS Camera interface and data output simulation 42 | .cmos_xclk (cmos_xclk), //25MHz cmos clock 43 | .cmos_pclk (cmos_pclk), //25MHz when rgb output 44 | .cmos_vsync (cmos_vsync), //L: vaild, H: invalid 45 | .cmos_href (cmos_href), //H: vaild, L: invalid 46 | .cmos_data (cmos_data) //8 bits cmos data input 47 | ); 48 | 49 | wire matrix_frame_vsync; //Prepared Image data vsync valid signal 50 | wire matrix_frame_href; //Prepared Image data href vaild signal 51 | wire [7:0] matrix_p11, matrix_p12, matrix_p13; //3X3 Matrix output 52 | wire [7:0] matrix_p21, matrix_p22, matrix_p23; 53 | wire [7:0] matrix_p31, matrix_p32, matrix_p33; 54 | Matrix_Generate_3X3 #( 55 | .DATA_WIDTH (8), 56 | .IMG_HDISP (IMG_HDISP), //640*480 57 | .IMG_VDISP (IMG_VDISP) 58 | ) Matrix_Generate_3X3_8Bit_u ( 59 | //global clock 60 | .clk (cmos_pclk), //cmos video pixel clock 61 | .rst_n (sys_rst_n), //global reset 62 | 63 | //Image data prepred to be processd 64 | .per_frame_vsync (cmos_vsync), //Prepared Image data vsync valid signal 65 | .per_frame_href (cmos_href), //Prepared Image data href vaild signal 66 | .per_img_Data (cmos_data), //Prepared Image brightness input 67 | 68 | //Image data has been processd 69 | .matrix_frame_vsync (matrix_frame_vsync), //Processed Image data vsync valid signal 70 | .matrix_frame_href (matrix_frame_href), //Processed Image data href vaild signal 71 | .matrix_p11(matrix_p11), .matrix_p12(matrix_p12), .matrix_p13(matrix_p13), //3X3 Matrix output 72 | .matrix_p21(matrix_p21), .matrix_p22(matrix_p22), .matrix_p23(matrix_p23), 73 | .matrix_p31(matrix_p31), .matrix_p32(matrix_p32), .matrix_p33(matrix_p33) 74 | ); 75 | 76 | //--------------------------------------------- 77 | //testbench of the RTL 78 | task task_sysinit; begin 79 | 80 | end 81 | endtask 82 | 83 | //---------------------------------------------- 84 | initial begin 85 | task_sysinit; 86 | task_reset; 87 | 88 | end 89 | 90 | endmodule 91 | 92 | -------------------------------------------------------------------------------- /user/src/Malloc/Shift_RAM/Line_Shift_RAM.v: -------------------------------------------------------------------------------- 1 | module Line_Shift_RAM #( 2 | parameter RAM_Length = 640, //640*480 3 | parameter DATA_WIDTH = 8 4 | ) ( 5 | input clken, 6 | input clock, 7 | input [DATA_WIDTH-1:0] shiftin, 8 | output [DATA_WIDTH-1:0] taps0x, 9 | output [DATA_WIDTH-1:0] taps1x 10 | ); 11 | 12 | RAMshift_taps #( 13 | .TOTAL_RAM_Length (RAM_Length), 14 | .DATA_WIDTH (DATA_WIDTH) 15 | ) RAMshfit_taps_u1 ( 16 | .clken(clken), 17 | .clock(clock), 18 | .Delay_Length(RAM_Length), 19 | .shiftin(shiftin), 20 | .shiftout(taps0x) 21 | ); 22 | 23 | RAMshift_taps #( 24 | .TOTAL_RAM_Length (RAM_Length), 25 | .DATA_WIDTH (DATA_WIDTH) 26 | ) RAMshfit_taps_u2 ( 27 | .clken(clken), 28 | .clock(clock), 29 | .Delay_Length(RAM_Length), 30 | .shiftin(taps0x), 31 | .shiftout(taps1x) 32 | ); 33 | endmodule -------------------------------------------------------------------------------- /user/src/Malloc/Shift_RAM/RAMshift_taps.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ns 2 | 3 | module RAMshift_taps #( 4 | parameter TOTAL_RAM_Length = 640, 5 | parameter DATA_WIDTH = 8 6 | ) ( 7 | input clken, 8 | input clock, 9 | input [31:0] Delay_Length, 10 | input [DATA_WIDTH - 1 : 0] shiftin, 11 | output [DATA_WIDTH - 1 : 0] shiftout 12 | ); 13 | 14 | reg [31:0] RAM_CNT = 0; 15 | reg [DATA_WIDTH - 1 : 0] ram_buf = 0; 16 | reg [DATA_WIDTH - 1 : 0] shift_ram [TOTAL_RAM_Length - 1 : 0]; 17 | 18 | integer m; 19 | initial begin 20 | for (m = 0; m<=TOTAL_RAM_Length; m=m+1) begin 21 | shift_ram[m] = 0; 22 | end 23 | end 24 | 25 | always @(posedge clock) begin 26 | if (RAM_CNT == (Delay_Length - 1)) 27 | RAM_CNT <= 0; 28 | else if (clken) 29 | RAM_CNT <= RAM_CNT + 1; 30 | else 31 | RAM_CNT <= RAM_CNT; 32 | end 33 | 34 | always @(posedge clock) begin 35 | if (clken) begin 36 | shift_ram[RAM_CNT] <= shiftin; 37 | end 38 | else begin 39 | shift_ram[RAM_CNT] <= shift_ram[RAM_CNT]; 40 | end 41 | end 42 | 43 | assign shiftout = shift_ram[RAM_CNT]; 44 | 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /user/src/Math/Sort3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Sort3 ( 3 | input clk, 4 | input rst_n, 5 | 6 | input [7:0] data1, data2, data3, 7 | output reg [7:0] max_data, mid_data, min_data 8 | ); 9 | 10 | //----------------------------------- 11 | //Sort of 3 datas 12 | always@(posedge clk or negedge rst_n) begin 13 | if(!rst_n) begin 14 | max_data <= 0; 15 | mid_data <= 0; 16 | min_data <= 0; 17 | end 18 | else begin 19 | //get the max value 20 | if(data1 >= data2 && data1 >= data3) 21 | max_data <= data1; 22 | else if(data2 >= data1 && data2 >= data3) 23 | max_data <= data2; 24 | else//(data3 >= data1 && data3 >= data2) 25 | max_data <= data3; 26 | 27 | //get the mid value 28 | if((data1 >= data2 && data1 <= data3) || (data1 >= data3 && data1 <= data2)) 29 | mid_data <= data1; 30 | else if((data2 >= data1 && data2 <= data3) || (data2 >= data3 && data2 <= data1)) 31 | mid_data <= data2; 32 | else//((data3 >= data1 && data3 <= data2) || (data3 >= data2 && data3 <= data1)) 33 | mid_data <= data3; 34 | 35 | //ge the min value 36 | if(data1 <= data2 && data1 <= data3) 37 | min_data <= data1; 38 | else if(data2 <= data1 && data2 <= data3) 39 | min_data <= data2; 40 | else//(data3 <= data1 && data3 <= data2) 41 | min_data <= data3; 42 | end 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /user/src/Math/Sqrt.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps / 1 ps 2 | 3 | module Sqrt # ( 4 | // GLOBAL PARAMETER DECLARATION 5 | parameter q_port_width = 16, // The width of the q port 6 | parameter r_port_width = 16, // The width of the remainder port 7 | parameter width = 16 // The width of the radical 8 | ) ( 9 | // INPUT PORT DECLARATION 10 | input [width - 1 : 0] radical, 11 | // OUTPUT PORT DECLARATION 12 | output [q_port_width - 1 : 0] q, 13 | output [r_port_width - 1 : 0] remainder 14 | ); 15 | 16 | // INTERNAL REGISTERS DECLARATION 17 | reg [r_port_width : 0] r_temp = 0; 18 | reg [q_port_width - 1 : 0] q_temp = 0; 19 | reg [q_port_width - 1 : 0] q_value_temp = 0; 20 | reg [r_port_width : 0] q_value_comp = 0; 21 | 22 | // LOCAL INTEGER DECLARATION 23 | integer value1; 24 | integer value2; 25 | integer index; 26 | integer q_index; 27 | integer i; 28 | integer pipe_ptr; 29 | 30 | // INITIAL CONSTRUCT BLOCK 31 | initial begin : INITIALIZE 32 | // Check for illegal mode 33 | if(width < 1) begin 34 | $display("width (%d) must be greater than 0.(ERROR)", width); 35 | $finish; 36 | end 37 | end 38 | 39 | // ALWAYS CONSTRUCT BLOCK 40 | always @(radical) begin : SQUARE_ROOT 41 | value1 = 0; 42 | value2 = 0; 43 | q_index = (width - 1) >> 1; 44 | q_temp = {q_port_width{1'b0}}; 45 | r_temp = {(r_port_width + 1){1'b0}}; 46 | q_value_temp = {q_port_width{1'b0}}; 47 | q_value_comp = {(r_port_width + 1){1'b0}}; 48 | if((width[0]) == 1) begin 49 | index = width + 1; 50 | value1 = 0; 51 | value2 = (radical[index - 2] === 1'b1) ? 1'b1 : 1'b0; 52 | end 53 | else if (width > 1) begin 54 | index = width; 55 | value1 = (radical[index - 1] === 1'b1) ? 1'b1 : 1'b0; 56 | value2 = (radical[index - 2] === 1'b1) ? 1'b1 : 1'b0; 57 | end 58 | for(index = index - 2; index >= 0; index = index - 2) begin 59 | r_temp = (r_temp<<2) + (2 * value1) + value2; 60 | q_value_comp = ((q_value_temp<<2) + 1); 61 | if (r_temp >= q_value_comp) begin 62 | r_temp = r_temp - q_value_comp; 63 | q_value_temp = (q_value_temp<<1) + 1; 64 | q_temp[q_index] = 1'b1; 65 | end 66 | else begin 67 | q_value_temp = q_value_temp<<1; 68 | q_temp[q_index] = 1'b0; 69 | end 70 | if(index >= 2) begin 71 | value1 = (radical[index - 1] === 1'b1)? 1: 0; 72 | value2 = (radical[index - 2] === 1'b1)? 1: 0; 73 | end 74 | q_index = q_index - 1; 75 | end 76 | end 77 | 78 | // CONTINOUS ASSIGNMENT 79 | assign q = q_temp; 80 | assign remainder = r_temp[(r_port_width - 1) : 0]; 81 | 82 | endmodule //altsqrt -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Advance_Apply/Image_XYCrop.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Image_XYCrop( 3 | input clk, 4 | input rst_n, 5 | 6 | //CMOS 7 | input image_in_vsync, 8 | input image_in_href, 9 | input image_in_data, 10 | 11 | output image_out_vsync, 12 | output image_out_href_left, 13 | output image_out_data_left, 14 | output image_out_href_right, 15 | output image_out_data_right 16 | ); 17 | 18 | //----------------------------------- 19 | reg image_in_href_r = 0; 20 | reg image_in_vsync_r = 0; 21 | reg image_in_data_r = 0; 22 | always@(posedge clk or negedge rst_n) begin 23 | if(!rst_n) begin 24 | image_in_vsync_r <= 0; 25 | image_in_href_r <= 0; 26 | image_in_data_r <= 0; 27 | end 28 | else begin 29 | image_in_vsync_r <= image_in_vsync; 30 | image_in_href_r <= image_in_href; 31 | image_in_data_r <= image_in_data; 32 | end 33 | end 34 | //----------------------------------- 35 | //Image Ysize Crop 36 | reg [11:0] image_ypos = 0; 37 | wire image_in_href_negedge = (image_in_href_r & ~image_in_href) ? 1'b1 : 1'b0; 38 | always@(posedge clk or negedge rst_n) begin 39 | if(!rst_n) 40 | image_ypos <= 0; 41 | else if(image_in_vsync == 1'b1) begin 42 | if(image_in_href_negedge == 1'b1) //行同步信号的下降沿，一行信号赋值完成后，image_ypos累加1 43 | image_ypos <= image_ypos + 1'b1; 44 | else 45 | image_ypos <= image_ypos; 46 | end 47 | else 48 | image_ypos <= 0; 49 | end 50 | assign image_out_vsync = image_in_vsync_r; // image_out_vsync是打一拍后的 image_in_vsync的信号，延时了一个时钟周期 51 | 52 | //----------------------------------- 53 | //Image Hsize Crop 54 | reg [11:0] image_xpos = 0; 55 | always@(posedge clk or negedge rst_n) begin 56 | if(!rst_n) 57 | image_xpos <= 0; 58 | else if(image_in_href == 1'b1) 59 | image_xpos <= image_xpos + 1'b1; 60 | else 61 | image_xpos <= 0; 62 | end 63 | 64 | assign image_out_href_right = ((image_in_href_r == 1'b1) && (image_xpos > 10'd640) && (image_xpos < 12'd1280)) ? 1'b1 : 1'b0; 65 | assign image_out_data_right = (image_out_vsync & image_out_href_right) ? image_in_data_r : 1'd0; 66 | assign image_out_href_left = ((image_in_href_r == 1'b1) && (image_xpos <= 10'd640)) ? 1'b1 : 1'b0; 67 | assign image_out_data_left = (image_out_vsync & image_out_href_left) ? image_in_data_r : 1'd0; 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Advance_Apply/Parallel_Line_Detector.v: -------------------------------------------------------------------------------- 1 | module Parallel_Line_Detector #( 2 | parameter IMG_VDISP = 1240, 3 | parameter X_THRESHOLD = 100, 4 | parameter Y_THRESHOLD = 100, 5 | parameter X_Center_Value = 540, 6 | parameter Y_Center_Value = 540 7 | ) ( 8 | input clk, 9 | input rst_n, 10 | // 11 | input per_img_Bit, 12 | input per_frame_href, 13 | input per_frame_vsync, 14 | // 15 | output X_up_down, 16 | output Y_up_down, 17 | output [15:0] X_distance, 18 | output [15:0] Y_distance 19 | ); 20 | 21 | 22 | //检测行同步信号边沿，一行数据的开始和结束 23 | wire href_pos,href_neg,vsync_neg; 24 | reg [1:0] per_frame_href_r,per_frame_vsync_r; 25 | always @ (posedge clk or negedge rst_n) begin 26 | if(!rst_n) begin 27 | per_frame_href_r <= 2'b0; 28 | per_frame_vsync_r <= 2'b0; 29 | end 30 | else begin 31 | per_frame_href_r <= {per_frame_href_r[0],per_frame_href}; 32 | per_frame_vsync_r <= {per_frame_vsync_r[0],per_frame_vsync}; 33 | end 34 | end 35 | assign href_pos =(~per_frame_href_r[1] & per_frame_href_r[0]) ? 1'b1 : 1'b0; //一行信号的开始 36 | assign href_neg =(~per_frame_href_r[0] & per_frame_href_r[1]) ? 1'b1 : 1'b0; //一行信号的结束 37 | assign vsync_neg =(~per_frame_vsync_r[0] & per_frame_vsync_r[1]) ? 1'b1 : 1'b0; //一帧信号的结束 38 | 39 | /**************************************直线检测部分**************************************/ 40 | wire IMG_BIT_INPUT = ~per_img_Bit; //输入的边缘数据 41 | 42 | reg [15:0] x_coordinate_cnt; //列计数器，横坐标 X 43 | reg [15:0] y_coordinate_cnt; //行计数器，纵坐标 Y 44 | 45 | reg [15:0] X_edge_center; //纵向纤芯坐标 46 | reg [15:0] Y_edge_center; //横向纤芯坐标 47 | 48 | //竖线线检测的相关变量 49 | reg [15:0] X_edge_acc = 0; //列边沿坐标的累加 50 | reg [15:0] X_edge_cnt = 0; //列边沿的计数器 51 | reg [15:0] per_row_acc [IMG_VDISP:1]; //每列的累加值 52 | reg [IMG_VDISP:1] per_row_flag; //每列的累加值 53 | 54 | //横线检测的相关变量 55 | reg [15:0] Y_edge_acc = 0; //行边沿坐标的累加 56 | reg [15:0] Y_edge_cnt = 0; //行边沿的计数器 57 | reg [15:0] per_href_acc = 0; //每行的累加值 58 | 59 | //直线检测处理语句块 60 | integer i; 61 | always @ (posedge clk or negedge rst_n) begin 62 | if(!rst_n) begin 63 | Y_edge_acc <= 16'd0; 64 | Y_edge_cnt <= 16'd0; 65 | X_edge_acc <= 16'd0; 66 | X_edge_cnt <= 16'd0; 67 | per_href_acc <= 16'd0; 68 | x_coordinate_cnt <= 16'd0; 69 | y_coordinate_cnt <= 16'd0; 70 | for (i = 1; i<=IMG_VDISP; i=i+1) begin 71 | per_row_acc[i] <= 16'd0; 72 | per_row_flag[i] <= 1'd0; 73 | end 74 | end 75 | else if (per_frame_href) begin 76 | if (href_pos) y_coordinate_cnt <= y_coordinate_cnt + 1'd1; 77 | else y_coordinate_cnt <= y_coordinate_cnt; 78 | if ((per_row_acc[x_coordinate_cnt] >= X_THRESHOLD) && (~per_row_flag[x_coordinate_cnt])) begin 79 | X_edge_cnt <= X_edge_cnt + 1'd1; 80 | per_row_flag[x_coordinate_cnt] <= 1'b1; 81 | X_edge_acc <= X_edge_acc + x_coordinate_cnt; 82 | end 83 | per_href_acc <= per_href_acc + IMG_BIT_INPUT; 84 | x_coordinate_cnt <= x_coordinate_cnt + 1'd1; 85 | per_row_acc[x_coordinate_cnt] <= per_row_acc[x_coordinate_cnt] + IMG_BIT_INPUT; 86 | end 87 | else if(href_neg) begin //一行数据结束 88 | if(per_href_acc >= Y_THRESHOLD) begin 89 | Y_edge_cnt <= Y_edge_cnt + 1'd1; 90 | Y_edge_acc <= Y_edge_acc + y_coordinate_cnt; 91 | end 92 | per_href_acc <= 16'd0; 93 | x_coordinate_cnt <= 16'd0; 94 | end 95 | else if (vsync_neg) begin 96 | X_edge_center = X_edge_acc / X_edge_cnt; 97 | Y_edge_center = Y_edge_acc / Y_edge_cnt; 98 | X_edge_acc <= 16'd0; X_edge_cnt <= 16'd0; 99 | Y_edge_acc <= 16'd0; Y_edge_cnt <= 16'd0; 100 | for (i = 1; i<=IMG_VDISP; i=i+1) begin 101 | per_row_acc[i] <= 16'd0; 102 | per_row_flag[i] <= 1'd0; 103 | end 104 | y_coordinate_cnt <= 16'd0; 105 | end 106 | end 107 | 108 | assign X_distance = $signed(X_edge_center) - $signed(X_Center_Value); 109 | assign Y_distance = $signed(Y_edge_center) - $signed(Y_Center_Value); 110 | assign X_up_down = X_distance[16]; 111 | assign Y_up_down = Y_distance[16]; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Dat/RAW8_RGB888.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module RAW8_RGB888 #( 3 | parameter [10:0] IMG_HDISP = 11'd640, //640*480 4 | parameter [10:0] IMG_VDISP = 11'd480 5 | ) ( 6 | //global clock 7 | input clk, //cmos video pixel clock 8 | input rst_n, //global reset 9 | 10 | //CMOS YCbCr444 data output 11 | input per_frame_vsync, //Prepared Image data vsync valid signal 12 | input per_frame_href, //Prepared Image data href vaild signal 13 | 14 | input [7:0] per_img_RAW, //Prepared Image data 8 Bit RAW Data 15 | 16 | 17 | //CMOS RGB888 data output 18 | output post_frame_vsync, //Processed Image data vsync valid signal 19 | output post_frame_href, //Processed Image data href vaild signal 20 | output [7:0] post_img_red, //Prepared Image green data to be processed 21 | output [7:0] post_img_green, //Prepared Image green data to be processed 22 | output [7:0] post_img_blue //Prepared Image blue data to be processed 23 | ); 24 | 25 | //---------------------------------------------------- 26 | //Generate 8Bit 3X3 Matrix for Video Image Processor. 27 | //Image data has been processd 28 | wire matrix_frame_vsync; //Prepared Image data vsync valid signal 29 | wire matrix_frame_href; //Prepared Image data href vaild signal 30 | wire [7:0] matrix_p11, matrix_p12, matrix_p13; //3X3 Matrix output 31 | wire [7:0] matrix_p21, matrix_p22, matrix_p23; 32 | wire [7:0] matrix_p31, matrix_p32, matrix_p33; 33 | Matrix_Generate_3X3_Buf # ( 34 | .DATA_WIDTH ( 8 ), 35 | .IMG_HDISP (IMG_HDISP), //640*480 36 | .IMG_VDISP (IMG_VDISP) 37 | ) Matrix_Generate_3X3_Buf_u ( 38 | //global clock 39 | .clk (clk), //cmos video pixel clock 40 | .rst_n (rst_n), //global reset 41 | 42 | //Image data prepred to be processd 43 | .per_frame_vsync (per_frame_vsync), //Prepared Image data vsync valid signal 44 | .per_frame_href (per_frame_href), //Prepared Image data href vaild signal 45 | .per_img_Data (per_img_RAW), //Prepared Image brightness input 46 | 47 | //Image data has been processd 48 | .matrix_frame_vsync (matrix_frame_vsync), //Processed Image data vsync valid signal 49 | .matrix_frame_href (matrix_frame_href), //Processed Image data href vaild signal 50 | .matrix_p11(matrix_p11), .matrix_p12(matrix_p12), .matrix_p13(matrix_p13), //3X3 Matrix output 51 | .matrix_p21(matrix_p21), .matrix_p22(matrix_p22), .matrix_p23(matrix_p23), 52 | .matrix_p31(matrix_p31), .matrix_p32(matrix_p32), .matrix_p33(matrix_p33) 53 | ); 54 | 55 | //------------------------------------------------------------- 56 | //sync the frame vsync and href signal and generate frame begin & end signal 57 | reg matrix_frame_href_r; 58 | always@(posedge clk or negedge rst_n) begin 59 | if(!rst_n) 60 | matrix_frame_href_r <= 0; 61 | else 62 | matrix_frame_href_r <= matrix_frame_href; 63 | end 64 | wire matrix_frame_href_end = (matrix_frame_href_r & ~matrix_frame_href) ? 1'b1 : 1'b0; //Line over signal 65 | 66 | //---------------------------------------- 67 | //Count the frame lines 68 | reg [10:0] line_cnt; 69 | always@(posedge clk or negedge rst_n) begin 70 | if(!rst_n) 71 | line_cnt <= 0; 72 | else if(matrix_frame_vsync == 1'b1) begin 73 | if(matrix_frame_href_end) 74 | line_cnt <= (line_cnt < IMG_VDISP - 1'b1) ? line_cnt + 1'b1 : 10'd0; 75 | else 76 | line_cnt <= line_cnt; 77 | end 78 | else 79 | line_cnt <= 0; 80 | end 81 | 82 | //---------------------------------------- 83 | //Count the pixels 84 | reg [10:0] point_cnt; 85 | always@(posedge clk or negedge rst_n) begin 86 | if(!rst_n) 87 | point_cnt <= 0; 88 | else if(matrix_frame_href == 1'b1) //Line valid 89 | point_cnt <= (line_cnt < IMG_HDISP - 1'b1) ? point_cnt + 1'b1 : 10'd0; 90 | else 91 | point_cnt <= 0; 92 | end 93 | 94 | //-------------------------------------- 95 | //Convet RAW 2 RGB888 Format 96 | // 97 | localparam OddLINE_OddPOINT = 2'b10; //odd lines + odd point 98 | localparam OddLINE_Even_POINT = 2'b11; //odd lines + even point 99 | localparam EvenLINE_OddPOINT = 2'b00; //even lines + odd point 100 | localparam EvenLINE_EvenPOINT = 2'b01; //even lines + even point 101 | reg [9:0] post_img_red_r; 102 | reg [9:0] post_img_green_r; 103 | reg [9:0] post_img_blue_r; 104 | always@(posedge clk or negedge rst_n) begin 105 | if(!rst_n) begin 106 | post_img_red_r <= 0; 107 | post_img_green_r<= 0; 108 | post_img_blue_r <= 0; 109 | end 110 | else begin 111 | case({line_cnt[0], point_cnt[0]}) 112 | //-------------------------BGBG...BGBG--------------------// 113 | OddLINE_OddPOINT:begin //odd lines + odd point 114 | //Center Blue 115 | post_img_red_r <= (matrix_p11 + matrix_p13 + matrix_p31 + matrix_p33)>>2; 116 | post_img_green_r<= (matrix_p12 + matrix_p21 + matrix_p23 + matrix_p32)>>2; 117 | post_img_blue_r <= matrix_p22; 118 | end 119 | OddLINE_Even_POINT:begin //odd lines + even point 120 | //Center Green 121 | post_img_red_r <= (matrix_p12 + matrix_p32)>>1; 122 | post_img_green_r<= matrix_p22; 123 | post_img_blue_r <= (matrix_p21 + matrix_p23)>>1; 124 | end 125 | //-------------------------GRGR...GRGR--------------------// 126 | EvenLINE_OddPOINT:begin //even lines + odd point 127 | //Center Green 128 | post_img_red_r <= (matrix_p21 + matrix_p23)>>1; 129 | post_img_green_r<= matrix_p22; 130 | post_img_blue_r <= (matrix_p12 + matrix_p32)>>1; 131 | end 132 | EvenLINE_EvenPOINT:begin //even lines + even point 133 | //Center Red 134 | post_img_red_r <= matrix_p22; 135 | post_img_green_r<= (matrix_p12 + matrix_p21 + matrix_p23 + matrix_p32)>>2; 136 | post_img_blue_r <= (matrix_p11 + matrix_p13 + matrix_p31 + matrix_p33)>>2; 137 | end 138 | endcase 139 | end 140 | end 141 | assign post_img_red = post_img_red_r[7:0]; 142 | assign post_img_green = post_img_green_r[7:0]; 143 | assign post_img_blue = post_img_blue_r[7:0]; 144 | 145 | //------------------------------------------ 146 | //lag n clocks signal sync 147 | reg [1:0] post_frame_vsync_r; 148 | reg [1:0] post_frame_href_r; 149 | always@(posedge clk or negedge rst_n) begin 150 | if(!rst_n) begin 151 | post_frame_vsync_r <= 0; 152 | post_frame_href_r <= 0; 153 | end 154 | else begin 155 | post_frame_vsync_r <= {post_frame_vsync_r[0], matrix_frame_vsync}; 156 | post_frame_href_r <= {post_frame_href_r[0], matrix_frame_href}; 157 | end 158 | end 159 | assign post_frame_vsync = post_frame_vsync_r[0]; 160 | assign post_frame_href = post_frame_href_r[0]; 161 | 162 | endmodule 163 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Dat/RGB888_YCbCr444.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module RGB888_YCbCr444 ( 3 | //global clock 4 | input clk, //cmos video pixel clock 5 | input rst_n, //global reset 6 | 7 | //Image data prepred to be processd 8 | input per_frame_vsync, //Prepared Image data vsync valid signal 9 | input per_frame_href, //Prepared Image data href vaild signal 10 | input [7:0] per_img_red, //Prepared Image red data to be processed 11 | input [7:0] per_img_green, //Prepared Image green data to be processed 12 | input [7:0] per_img_blue, //Prepared Image blue data to be processed 13 | 14 | //Image data has been processd 15 | output post_frame_vsync, //Processed Image data vsync valid signal 16 | output post_frame_href, //Processed Image data href vaild signal 17 | output [7:0] post_img_Y, //Processed Image brightness output 18 | output [7:0] post_img_Cb, //Processed Image blue shading output 19 | output [7:0] post_img_Cr //Processed Image red shading output 20 | ); 21 | 22 | //-------------------------------------------- 23 | /********************************************* 24 | //Refer to page 5 25 | Y = (77 *R + 150*G + 29 *B)>>8 26 | Cb = (-43*R - 85 *G + 128*B)>>8 + 128 27 | Cr = (128*R - 107*G - 21 *B)>>8 + 128 28 | ---> 29 | Y = (77 *R + 150*G + 29 *B)>>8 30 | Cb = (-43*R - 85 *G + 128*B + 32768)>>8 31 | Cr = (128*R - 107*G - 21 *B + 32768)>>8 32 | **********************************************/ 33 | //Step 1 34 | reg [15:0] img_red_r0, img_red_r1, img_red_r2; 35 | reg [15:0] img_green_r0, img_green_r1, img_green_r2; 36 | reg [15:0] img_blue_r0, img_blue_r1, img_blue_r2; 37 | always@(posedge clk or negedge rst_n) begin 38 | if(!rst_n) begin 39 | img_red_r0 <= 0; 40 | img_red_r1 <= 0; 41 | img_red_r2 <= 0; 42 | img_green_r0 <= 0; 43 | img_green_r1 <= 0; 44 | img_green_r2 <= 0; 45 | img_blue_r0 <= 0; 46 | img_blue_r1 <= 0; 47 | img_blue_r2 <= 0; 48 | end 49 | else begin 50 | img_red_r0 <= per_img_red * 8'd77; 51 | img_red_r1 <= per_img_red * 8'd43; 52 | img_red_r2 <= per_img_red * 8'd128; 53 | img_green_r0 <= per_img_green * 8'd150; 54 | img_green_r1 <= per_img_green * 8'd85; 55 | img_green_r2 <= per_img_green * 8'd107; 56 | img_blue_r0 <= per_img_blue * 8'd29; 57 | img_blue_r1 <= per_img_blue * 8'd128; 58 | img_blue_r2 <= per_img_blue * 8'd21; 59 | end 60 | end 61 | 62 | //-------------------------------------------------- 63 | //Step 2 64 | reg [15:0] img_Y_r0; 65 | reg [15:0] img_Cb_r0; 66 | reg [15:0] img_Cr_r0; 67 | always@(posedge clk or negedge rst_n) begin 68 | if(!rst_n) begin 69 | img_Y_r0 <= 0; 70 | img_Cb_r0 <= 0; 71 | img_Cr_r0 <= 0; 72 | end 73 | else begin 74 | img_Y_r0 <= img_red_r0 + img_green_r0 + img_blue_r0; 75 | img_Cb_r0 <= img_blue_r1 - img_red_r1 - img_green_r1 + 16'd32768; 76 | img_Cr_r0 <= img_red_r2 + img_green_r2 + img_blue_r2 + 16'd32768; 77 | end 78 | end 79 | 80 | //-------------------------------------------------- 81 | //Step 3 82 | reg [7:0] img_Y_r1; 83 | reg [7:0] img_Cb_r1; 84 | reg [7:0] img_Cr_r1; 85 | always@(posedge clk or negedge rst_n) begin 86 | if(!rst_n) begin 87 | img_Y_r1 <= 0; 88 | img_Cb_r1 <= 0; 89 | img_Cr_r1 <= 0; 90 | end 91 | else begin 92 | img_Y_r1 <= img_Y_r0[15:8]; 93 | img_Cb_r1 <= img_Cb_r0[15:8]; 94 | img_Cr_r1 <= img_Cr_r0[15:8]; 95 | end 96 | end 97 | 98 | //------------------------------------------ 99 | //lag 3 clocks signal sync 100 | reg [2:0] per_frame_vsync_r; 101 | reg [2:0] per_frame_href_r; 102 | always@(posedge clk or negedge rst_n) begin 103 | if(!rst_n) begin 104 | per_frame_vsync_r <= 0; 105 | per_frame_href_r <= 0; 106 | end 107 | else begin 108 | per_frame_vsync_r <= {per_frame_vsync_r[1:0], per_frame_vsync}; 109 | per_frame_href_r <= {per_frame_href_r[1:0], per_frame_href}; 110 | end 111 | end 112 | assign post_frame_vsync = per_frame_vsync_r[2]; 113 | assign post_frame_href = per_frame_href_r[2]; 114 | assign post_img_Y = post_frame_href ? img_Y_r1 : 8'd0; 115 | assign post_img_Cb = post_frame_href ? img_Cb_r1: 8'd0; 116 | assign post_img_Cr = post_frame_href ? img_Cr_r1: 8'd0; 117 | 118 | endmodule 119 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Detector/Dilation_Detector.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Bit_Dilation_Detector #( 3 | parameter [10:0] IMG_HDISP = 11'd640, //640*480 4 | parameter [10:0] IMG_VDISP = 11'd480 5 | ) ( 6 | //global clock 7 | input clk, //cmos video pixel clock 8 | input rst_n, //global reset 9 | //Image data prepred to be processd 10 | input per_frame_vsync, //Prepared Image data vsync valid signal 11 | input per_frame_href, //Prepared Image data href vaild signal 12 | input per_img_Bit, //Prepared Image Bit flag outout(1: Value, 0:inValid) 13 | //Image data has been processd 14 | output post_frame_vsync, //Processed Image data vsync valid signal 15 | output post_frame_href, //Processed Image data href vaild signal 16 | output post_img_Bit //Processed Image Bit flag outout(1: Value, 0:inValid) 17 | ); 18 | 19 | //---------------------------------------------------- 20 | //Generate 1Bit 3X3 Matrix for Video Image Processor. 21 | //Image data has been processd 22 | wire matrix_frame_vsync; //Prepared Image data vsync valid signal 23 | wire matrix_frame_href; //Prepared Image data href vaild signal 24 | wire matrix_p11, matrix_p12, matrix_p13; //3X3 Matrix output 25 | wire matrix_p21, matrix_p22, matrix_p23; 26 | wire matrix_p31, matrix_p32, matrix_p33; 27 | Matrix_Generate_3X3 #( 28 | .DATA_WIDTH ( 1 ), 29 | .IMG_HDISP (IMG_HDISP), //640*480 30 | .IMG_VDISP (IMG_VDISP) 31 | ) Matrix_Generate_3X3_u ( 32 | //global clock 33 | .clk (clk), //cmos video pixel clock 34 | .rst_n (rst_n), //global reset 35 | //Image data prepred to be processd 36 | .per_frame_vsync (per_frame_vsync), //Prepared Image data vsync valid signal 37 | .per_frame_href (per_frame_href), //Prepared Image data href vaild signal 38 | .per_img_Data (per_img_Bit), //Prepared Image brightness input 39 | //Image data has been processd 40 | .matrix_frame_vsync (matrix_frame_vsync), //Processed Image data vsync valid signal 41 | .matrix_frame_href (matrix_frame_href), //Processed Image data href vaild signal 42 | .matrix_p11(matrix_p11), .matrix_p12(matrix_p12), .matrix_p13(matrix_p13), //3X3 Matrix output 43 | .matrix_p21(matrix_p21), .matrix_p22(matrix_p22), .matrix_p23(matrix_p23), 44 | .matrix_p31(matrix_p31), .matrix_p32(matrix_p32), .matrix_p33(matrix_p33) 45 | ); 46 | 47 | //Add you arithmetic here 48 | //---------------------------------------------------------------------------- 49 | //---------------------------------------------------------------------------- 50 | //---------------------------------------------------------------------------- 51 | //------------------------------------------- 52 | //------------------------------------------- 53 | //Dilation Parameter 54 | // Original Dilation Pixel 55 | // [ 0 0 0 ] [ 1 1 1 ] [ P1 P2 P3 ] 56 | // [ 0 1 0 ] [ 1 1 1 ] [ P4 P5 P6 ] 57 | // [ 0 0 0 ] [ 1 1 1 ] [ P7 P8 P9 ] 58 | //P = P1 | P2 | P3 | P4 | P5 | P6 | P7 | 8 | 9; 59 | //--------------------------------------- 60 | //Dilation with or operation,1 : White, 0 : Black 61 | //Step1 62 | reg post_img_Bit1, post_img_Bit2, post_img_Bit3; 63 | always@(posedge clk or negedge rst_n) begin 64 | if(!rst_n) begin 65 | post_img_Bit1 <= 1'b0; 66 | post_img_Bit2 <= 1'b0; 67 | post_img_Bit3 <= 1'b0; 68 | end 69 | else begin 70 | post_img_Bit1 <= matrix_p11 | matrix_p12 | matrix_p13; 71 | post_img_Bit2 <= matrix_p21 | matrix_p22 | matrix_p23; 72 | post_img_Bit3 <= matrix_p21 | matrix_p32 | matrix_p33; 73 | end 74 | end 75 | 76 | //Step 2 77 | reg post_img_Bit4; 78 | always@(posedge clk or negedge rst_n) begin 79 | if(!rst_n) 80 | post_img_Bit4 <= 1'b0; 81 | else 82 | post_img_Bit4 <= post_img_Bit1 | post_img_Bit2 | post_img_Bit3; 83 | end 84 | 85 | //------------------------------------------ 86 | //lag 2 clocks signal sync 87 | reg [1:0] per_frame_vsync_r; 88 | reg [1:0] per_frame_href_r; 89 | always@(posedge clk or negedge rst_n) begin 90 | if(!rst_n) begin 91 | per_frame_vsync_r <= 0; 92 | per_frame_href_r <= 0; 93 | end 94 | else begin 95 | per_frame_vsync_r <= {per_frame_vsync_r[0], matrix_frame_vsync}; 96 | per_frame_href_r <= {per_frame_href_r[0], matrix_frame_href}; 97 | end 98 | end 99 | assign post_frame_vsync = per_frame_vsync_r[1]; 100 | assign post_frame_href = per_frame_href_r[1]; 101 | assign post_img_Bit = post_frame_href ? post_img_Bit4 : 1'b0; 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Detector/Erosion_Detector.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Bit_Erosion_Detector #( 3 | parameter [10:0] IMG_HDISP = 11'd640, //640*480 4 | parameter [10:0] IMG_VDISP = 11'd480 5 | ) ( 6 | //global clock 7 | input clk, //cmos video pixel clock 8 | input rst_n, //global reset 9 | 10 | //Image data prepred to be processd 11 | input per_frame_vsync, //Prepared Image data vsync valid signal 12 | input per_frame_href, //Prepared Image data href vaild signal 13 | input per_img_Bit, //Prepared Image Bit flag outout(1: Value, 0:inValid) 14 | 15 | //Image data has been processd 16 | output post_frame_vsync, //Processed Image data vsync valid signal 17 | output post_frame_href, //Processed Image data href vaild signal 18 | output post_img_Bit //Processed Image Bit flag outout(1: Value, 0:inValid) 19 | ); 20 | 21 | //---------------------------------------------------- 22 | //Generate 1Bit 3X3 Matrix for Video Image Processor. 23 | //Image data has been processd 24 | wire matrix_frame_vsync; //Prepared Image data vsync valid signal 25 | wire matrix_frame_href; //Prepared Image data href vaild signal 26 | wire matrix_p11, matrix_p12, matrix_p13; //3X3 Matrix output 27 | wire matrix_p21, matrix_p22, matrix_p23; 28 | wire matrix_p31, matrix_p32, matrix_p33; 29 | Matrix_Generate_3X3 #( 30 | .DATA_WIDTH ( 1 ), 31 | .IMG_HDISP (IMG_HDISP), //640*480 32 | .IMG_VDISP (IMG_VDISP) 33 | ) Matrix_Generate_3X3_u ( 34 | //global clock 35 | .clk (clk), //cmos video pixel clock 36 | .rst_n (rst_n), //global reset 37 | //Image data prepred to be processd 38 | .per_frame_vsync (per_frame_vsync), //Prepared Image data vsync valid signal 39 | .per_frame_href (per_frame_href), //Prepared Image data href vaild signal 40 | .per_img_Data (per_img_Bit), //Prepared Image brightness input 41 | //Image data has been processd 42 | .matrix_frame_vsync (matrix_frame_vsync), //Processed Image data vsync valid signal 43 | .matrix_frame_href (matrix_frame_href), //Processed Image data href vaild signal 44 | .matrix_p11(matrix_p11), .matrix_p12(matrix_p12), .matrix_p13(matrix_p13), //3X3 Matrix output 45 | .matrix_p21(matrix_p21), .matrix_p22(matrix_p22), .matrix_p23(matrix_p23), 46 | .matrix_p31(matrix_p31), .matrix_p32(matrix_p32), .matrix_p33(matrix_p33) 47 | ); 48 | 49 | //Add you arithmetic here 50 | //---------------------------------------------------------------------------- 51 | //---------------------------------------------------------------------------- 52 | //---------------------------------------------------------------------------- 53 | //------------------------------------------- 54 | //------------------------------------------- 55 | //Eronsion Parameter 56 | // Original Dilation Pixel 57 | // [ 0 0 0 ] [ 1 1 1 ] [ P1 P2 P3 ] 58 | // [ 0 1 0 ] [ 1 1 1 ] [ P4 P5 P6 ] 59 | // [ 0 0 0 ] [ 1 1 1 ] [ P7 P8 P9 ] 60 | //P = P1 & P2 & P3 & P4 & P5 & P6 & P7 & 8 & 9; 61 | //--------------------------------------- 62 | //Eonsion with or operation 63 | //Step1 64 | reg post_img_Bit1, post_img_Bit2, post_img_Bit3; 65 | always@(posedge clk or negedge rst_n) begin 66 | if(!rst_n) begin 67 | post_img_Bit1 <= 1'b0; 68 | post_img_Bit2 <= 1'b0; 69 | post_img_Bit3 <= 1'b0; 70 | end 71 | else begin 72 | post_img_Bit1 <= matrix_p11 & matrix_p12 & matrix_p13; 73 | post_img_Bit2 <= matrix_p21 & matrix_p22 & matrix_p23; 74 | post_img_Bit3 <= matrix_p21 & matrix_p32 & matrix_p33; 75 | end 76 | end 77 | 78 | //Step 2 79 | reg post_img_Bit4; 80 | always@(posedge clk or negedge rst_n) begin 81 | if(!rst_n) 82 | post_img_Bit4 <= 1'b0; 83 | else 84 | post_img_Bit4 <= post_img_Bit1 & post_img_Bit2 & post_img_Bit3; 85 | end 86 | 87 | //------------------------------------------ 88 | //lag 2 clocks signal sync 89 | reg [1:0] per_frame_vsync_r; 90 | reg [1:0] per_frame_href_r; 91 | always@(posedge clk or negedge rst_n) begin 92 | if(!rst_n) begin 93 | per_frame_vsync_r <= 0; 94 | per_frame_href_r <= 0; 95 | end 96 | else begin 97 | per_frame_vsync_r <= {per_frame_vsync_r[0], matrix_frame_vsync}; 98 | per_frame_href_r <= {per_frame_href_r[0], matrix_frame_href}; 99 | end 100 | end 101 | assign post_frame_vsync = per_frame_vsync_r[1]; 102 | assign post_frame_href = per_frame_href_r[1]; 103 | assign post_img_Bit = post_frame_href ? post_img_Bit4 : 1'b0; 104 | 105 | endmodule 106 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Detector/Sobel_Edge_Detector.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Sobel_Edge_Detector #( 3 | parameter [10:0] IMG_HDISP = 11'd640, //640*480 4 | parameter [10:0] IMG_VDISP = 11'd480 5 | ) ( 6 | //global clock 7 | input clk, //cmos video pixel clock 8 | input rst_n, //global reset 9 | //Image data prepred to be processd 10 | input per_frame_vsync, //Prepared Image data vsync valid signal 11 | input per_frame_href, //Prepared Image data href vaild signal 12 | input [7:0] per_img_Gray, //Prepared Image brightness input 13 | //Image data has been processd 14 | output post_frame_vsync, //Processed Image data vsync valid signal 15 | output post_frame_href, //Processed Image data href vaild signal 16 | output post_img_Bit, //Processed Image Bit flag outout(1: Value, 0:inValid) 17 | //user interface 18 | input [7:0] Sobel_Threshold //Sobel Threshold for image edge detect 19 | ); 20 | 21 | //---------------------------------------------------- 22 | //Generate 8Bit 3X3 Matrix for Video Image Processor. 23 | //Image data has been processd 24 | wire matrix_frame_vsync; //Prepared Image data vsync valid signal 25 | wire matrix_frame_href; //Prepared Image data href vaild signal 26 | wire [7:0] matrix_p11, matrix_p12, matrix_p13; //3X3 Matrix output 27 | wire [7:0] matrix_p21, matrix_p22, matrix_p23; 28 | wire [7:0] matrix_p31, matrix_p32, matrix_p33; 29 | Matrix_Generate_3X3_Buf # ( 30 | .DATA_WIDTH ( 8 ), 31 | .IMG_HDISP (IMG_HDISP), //640*480 32 | .IMG_VDISP (IMG_VDISP) 33 | ) Matrix_Generate_3X3_Buf_u ( 34 | //global clock 35 | .clk (clk), //cmos video pixel clock 36 | .rst_n (rst_n), //global reset 37 | //Image data prepred to be processd 38 | .per_frame_vsync (per_frame_vsync), //Prepared Image data vsync valid signal 39 | .per_frame_href (per_frame_href), //Prepared Image data href vaild signal 40 | .per_img_Data (per_img_Gray), //Prepared Image brightness input 41 | //Image data has been processd 42 | .matrix_frame_vsync (matrix_frame_vsync), //Processed Image data vsync valid signal 43 | .matrix_frame_href (matrix_frame_href), //Processed Image data href vaild signal 44 | .matrix_p11(matrix_p11), .matrix_p12(matrix_p12), .matrix_p13(matrix_p13), //3X3 Matrix output 45 | .matrix_p21(matrix_p21), .matrix_p22(matrix_p22), .matrix_p23(matrix_p23), 46 | .matrix_p31(matrix_p31), .matrix_p32(matrix_p32), .matrix_p33(matrix_p33) 47 | ); 48 | 49 | //Add you arithmetic here 50 | //---------------------------------------------------------------------------- 51 | //---------------------------------------------------------------------------- 52 | //---------------------------------------------------------------------------- 53 | //------------------------------------------- 54 | //Sobel Parameter 55 | // Gx Gy Pixel 56 | // [ -1 0 +1 ] [ +1 +2 +1 ] [ P11 P12 P13 ] 57 | // [ -2 0 +2 ] [ 0 0 0 ] [ P21 P22 P23 ] 58 | // [ -1 0 +1 ] [ -1 -2 -1 ] [ P31 P32 P33 ] 59 | 60 | // localparam P11 = 8'd15, P12 = 8'd94, P13 = 8'd136; 61 | // localparam P21 = 8'd31, P22 = 8'd127, P23 = 8'd231; 62 | // localparam P31 = 8'd44, P32 = 8'd181, P33 = 8'd249; 63 | //Caculate horizontal Grade with |abs| 64 | //Step 1-2 65 | reg [9:0] Gx_temp1; //postive result 66 | reg [9:0] Gx_temp2; //negetive result 67 | reg [9:0] Gx_data; //Horizontal grade data 68 | always@(posedge clk or negedge rst_n) begin 69 | if(!rst_n) begin 70 | Gx_temp1 <= 0; 71 | Gx_temp2 <= 0; 72 | Gx_data <= 0; 73 | end 74 | else begin 75 | Gx_temp1 <= matrix_p13 + (matrix_p23 << 1) + matrix_p33; //postive result 76 | Gx_temp2 <= matrix_p11 + (matrix_p21 << 1) + matrix_p31; //negetive result 77 | Gx_data <= (Gx_temp1 >= Gx_temp2) ? Gx_temp1 - Gx_temp2 : Gx_temp2 - Gx_temp1; 78 | end 79 | end 80 | 81 | //--------------------------------------- 82 | //Caculate vertical Grade with |abs| 83 | //Step 1-2 84 | reg [9:0] Gy_temp1; //postive result 85 | reg [9:0] Gy_temp2; //negetive result 86 | reg [9:0] Gy_data; //Vertical grade data 87 | always@(posedge clk or negedge rst_n) begin 88 | if(!rst_n) begin 89 | Gy_temp1 <= 0; 90 | Gy_temp2 <= 0; 91 | Gy_data <= 0; 92 | end 93 | else begin 94 | Gy_temp1 <= matrix_p11 + (matrix_p12 << 1) + matrix_p13; //postive result 95 | Gy_temp2 <= matrix_p31 + (matrix_p32 << 1) + matrix_p33; //negetive result 96 | Gy_data <= (Gy_temp1 >= Gy_temp2) ? Gy_temp1 - Gy_temp2 : Gy_temp2 - Gy_temp1; 97 | end 98 | end 99 | 100 | //--------------------------------------- 101 | //Caculate the square of distance = (Gx^2 + Gy^2) 102 | //Step 3 103 | reg [20:0] Gxy_square; 104 | always@(posedge clk or negedge rst_n) begin 105 | if(!rst_n) 106 | Gxy_square <= 0; 107 | else 108 | Gxy_square <= Gx_data * Gx_data + Gy_data * Gy_data; 109 | end 110 | 111 | //--------------------------------------- 112 | //Caculate the distance of P5 = (Gx^2 + Gy^2)^0.5 113 | //Step 4 114 | Sqrt #( 115 | .q_port_width (11), 116 | .r_port_width (12), 117 | .width (21) 118 | ) SQRT_u ( 119 | .radical (Gxy_square), 120 | .q (Dim), 121 | .remainder () 122 | ); 123 | 124 | //--------------------------------------- 125 | //Compare and get the Sobel_data 126 | //Step 5 127 | reg post_img_Bit_r; 128 | always@(posedge clk or negedge rst_n) begin 129 | if(!rst_n) 130 | post_img_Bit_r <= 1'b0; //Default None 131 | else if(Dim >= Sobel_Threshold) 132 | post_img_Bit_r <= 1'b1; //Edge Flag 133 | else 134 | post_img_Bit_r <= 1'b0; //Not Edge 135 | end 136 | 137 | //------------------------------------------ 138 | //lag 5 clocks signal sync 139 | reg [4:0] per_frame_vsync_r; 140 | reg [4:0] per_frame_href_r; 141 | always@(posedge clk or negedge rst_n) begin 142 | if(!rst_n) begin 143 | per_frame_vsync_r <= 0; 144 | per_frame_href_r <= 0; 145 | end 146 | else begin 147 | per_frame_vsync_r <= {per_frame_vsync_r[3:0], matrix_frame_vsync}; 148 | per_frame_href_r <= {per_frame_href_r[3:0], matrix_frame_href}; 149 | end 150 | end 151 | assign post_frame_vsync = per_frame_vsync_r[4]; 152 | assign post_frame_href = per_frame_href_r[4]; 153 | assign post_img_Bit = post_frame_href ? post_img_Bit_r : 1'b0; 154 | 155 | endmodule 156 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Filter/Gray_Median_Filter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Gray_Median_Filter #( 3 | parameter [10:0] IMG_HDISP = 11'd640, //640*480 4 | parameter [10:0] IMG_VDISP = 11'd480 5 | ) ( 6 | //global clock 7 | input clk, //100MHz 8 | input rst_n, //global reset 9 | //Image data prepred to be processd 10 | input per_frame_vsync, //Prepared Image data vsync valid signal 11 | input per_frame_href, //Prepared Image data href vaild signal 12 | input [7:0] per_img_Gray, //Prepared Image brightness input 13 | //Image data has been processd 14 | output post_frame_vsync, //Processed Image data vsync valid signal 15 | output post_frame_href, //Processed Image data href vaild signal 16 | output [7:0] post_img_Gray //Processed Image brightness input 17 | ); 18 | 19 | //---------------------------------------------------- 20 | //Generate 8Bit 3X3 Matrix for Video Image Processor. 21 | //Image data has been processd 22 | wire matrix_frame_vsync; //Prepared Image data vsync valid signal 23 | wire matrix_frame_href; //Prepared Image data href vaild signal 24 | wire matrix_frame_clken; //Prepared Image data output/capture enable clock 25 | wire [7:0] matrix_p11, matrix_p12, matrix_p13; //3X3 Matrix output 26 | wire [7:0] matrix_p21, matrix_p22, matrix_p23; 27 | wire [7:0] matrix_p31, matrix_p32, matrix_p33; 28 | Matrix_Generate_3X3_Buf # ( 29 | .DATA_WIDTH ( 8 ), 30 | .IMG_HDISP (IMG_HDISP), //640*480 31 | .IMG_VDISP (IMG_VDISP) 32 | ) Matrix_Generate_3X3_Buf_u ( 33 | //global clock 34 | .clk (clk), //cmos video pixel clock 35 | .rst_n (rst_n), //global reset 36 | //Image data prepred to be processd 37 | .per_frame_vsync (per_frame_vsync), //Prepared Image data vsync valid signal 38 | .per_frame_href (per_frame_href), //Prepared Image data href vaild signal 39 | .per_img_Data (per_img_Gray), //Prepared Image brightness input 40 | //Image data has been processd 41 | .matrix_frame_vsync (matrix_frame_vsync), //Processed Image data vsync valid signal 42 | .matrix_frame_href (matrix_frame_href), //Processed Image data href vaild signal 43 | .matrix_p11(matrix_p11), .matrix_p12(matrix_p12), .matrix_p13(matrix_p13), //3X3 Matrix output 44 | .matrix_p21(matrix_p21), .matrix_p22(matrix_p22), .matrix_p23(matrix_p23), 45 | .matrix_p31(matrix_p31), .matrix_p32(matrix_p32), .matrix_p33(matrix_p33) 46 | ); 47 | 48 | 49 | //Add you arithmetic here 50 | //---------------------------------------------------------------------------- 51 | //---------------------------------------------------------------------------- 52 | //---------------------------------------------------------------------------- 53 | //Median Filter of 3X3 datas, need 3 clock 54 | wire [7:0] mid_value; 55 | Median_Filter_3X3 u_Median_Filter_3X3( 56 | .clk (clk), 57 | .rst_n (rst_n), 58 | //ROW1 59 | .data11 (matrix_p11), 60 | .data12 (matrix_p12), 61 | .data13 (matrix_p13), 62 | //ROW2 63 | .data21 (matrix_p21), 64 | .data22 (matrix_p22), 65 | .data23 (matrix_p23), 66 | //ROW3 67 | .data31 (matrix_p31), 68 | .data32 (matrix_p32), 69 | .data33 (matrix_p33), 70 | 71 | .target_data (mid_value) 72 | ); 73 | 74 | //------------------------------------------ 75 | //lag 3 clocks signal sync 76 | reg [2:0] per_frame_vsync_r; 77 | reg [2:0] per_frame_href_r; 78 | always@(posedge clk or negedge rst_n) begin 79 | if(!rst_n) begin 80 | per_frame_vsync_r <= 0; 81 | per_frame_href_r <= 0; 82 | end 83 | else begin 84 | per_frame_vsync_r <= {per_frame_vsync_r[1:0], matrix_frame_vsync}; 85 | per_frame_href_r <= {per_frame_href_r[1:0], matrix_frame_href}; 86 | end 87 | end 88 | assign post_frame_vsync = per_frame_vsync_r[2]; 89 | assign post_frame_href = per_frame_href_r[2]; 90 | assign post_img_Gray = post_frame_href ? mid_value : 8'd0; 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Filter/Median_Filter_3X3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Median_Filter_3X3 ( 3 | input clk, 4 | input rst_n, 5 | 6 | input [7:0] data11, data12, data13, 7 | input [7:0] data21, data22, data23, 8 | input [7:0] data31, data32, data33, 9 | 10 | output [7:0] target_data 11 | ); 12 | 13 | //-------------------------------------------------------------------------------------- 14 | //FPGA Median Filter Sort order 15 | // Pixel Sort1 Sort2 Sort3 16 | // [ P1 P2 P3 ] [ Max1 Mid1 Min1 ] 17 | // [ P4 P5 P6 ] [ Max2 Mid2 Min2 ] [Max_min, Mid_mid, Min_max] mid_valid 18 | // [ P7 P8 P9 ] [ Max3 Mid3 Min3 ] 19 | 20 | //Step1 21 | wire [7:0] max_data1, mid_data1, min_data1; 22 | Sort3 u_Sort3_1 ( 23 | .clk (clk), 24 | .rst_n (rst_n), 25 | 26 | .data1 (data11), 27 | .data2 (data12), 28 | .data3 (data13), 29 | 30 | .max_data (max_data1), 31 | .mid_data (mid_data1), 32 | .min_data (min_data1) 33 | ); 34 | 35 | wire [7:0] max_data2, mid_data2, min_data2; 36 | Sort3 u_Sort3_2 ( 37 | .clk (clk), 38 | .rst_n (rst_n), 39 | 40 | .data1 (data21), 41 | .data2 (data22), 42 | .data3 (data23), 43 | 44 | .max_data (max_data2), 45 | .mid_data (mid_data2), 46 | .min_data (min_data2) 47 | ); 48 | 49 | wire [7:0] max_data3, mid_data3, min_data3; 50 | Sort3 u_Sort3_3 ( 51 | .clk (clk), 52 | .rst_n (rst_n), 53 | 54 | .data1 (data31), 55 | .data2 (data32), 56 | .data3 (data33), 57 | 58 | .max_data (max_data3), 59 | .mid_data (mid_data3), 60 | .min_data (min_data3) 61 | ); 62 | 63 | //Step2 64 | wire [7:0] max_min_data, mid_mid_data, min_max_data; 65 | Sort3 u_Sort3_4 ( 66 | .clk (clk), 67 | .rst_n (rst_n), 68 | 69 | .data1 (max_data1), 70 | .data2 (max_data2), 71 | .data3 (max_data3), 72 | 73 | .max_data (), 74 | .mid_data (), 75 | .min_data (max_min_data) 76 | ); 77 | 78 | Sort3 u_Sort3_5 ( 79 | .clk (clk), 80 | .rst_n (rst_n), 81 | 82 | .data1 (mid_data1), 83 | .data2 (mid_data2), 84 | .data3 (mid_data3), 85 | 86 | .max_data (), 87 | .mid_data (mid_mid_data), 88 | .min_data () 89 | ); 90 | 91 | Sort3 u_Sort3_6 ( 92 | .clk (clk), 93 | .rst_n (rst_n), 94 | 95 | .data1 (min_data1), 96 | .data2 (min_data2), 97 | .data3 (min_data3), 98 | 99 | .max_data (min_max_data), 100 | .mid_data (), 101 | .min_data () 102 | ); 103 | 104 | //step3 105 | Sort3 u_Sort3_7 ( 106 | .clk (clk), 107 | .rst_n (rst_n), 108 | 109 | .data1 (max_min_data), 110 | .data2 (mid_mid_data), 111 | .data3 (min_max_data), 112 | 113 | .max_data (), 114 | .mid_data (target_data), 115 | .min_data () 116 | ); 117 | 118 | endmodule 119 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Matrix/Matrix_Generate_3X3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Matrix_Generate_3X3 #( 3 | parameter DATA_WIDTH = 8, 4 | parameter IMG_HDISP = 640, //640*480 5 | parameter IMG_VDISP = 480 6 | ) ( 7 | //global clock 8 | input clk, //cmos video pixel clock 9 | input rst_n, //global reset 10 | 11 | //Image data prepred to be processd 12 | input per_frame_vsync, //Prepared Image data vsync valid signal 13 | input per_frame_href, //Prepared Image data href vaild signal 14 | input [DATA_WIDTH-1:0] per_img_Data, //Prepared Image brightness input 15 | 16 | //Image data has been processd 17 | output matrix_frame_vsync, //Prepared Image data vsync valid signal 18 | output matrix_frame_href, //Prepared Image data href vaild signal 19 | 20 | output reg [DATA_WIDTH-1:0] matrix_p11, matrix_p12, matrix_p13, //3X3 Matrix output 21 | output reg [DATA_WIDTH-1:0] matrix_p21, matrix_p22, matrix_p23, 22 | output reg [DATA_WIDTH-1:0] matrix_p31, matrix_p32, matrix_p33 23 | ); 24 | 25 | 26 | //Generate 3*3 matrix 27 | //-------------------------------------------------------------------------- 28 | //-------------------------------------------------------------------------- 29 | //-------------------------------------------------------------------------- 30 | //sync row3_data with per_frame_clken & row1_data & raw2_data 31 | wire [DATA_WIDTH-1:0] row1_data; //frame data of the 1th row 32 | wire [DATA_WIDTH-1:0] row2_data; //frame data of the 2th row 33 | reg [DATA_WIDTH-1:0] row3_data; //frame data of the 3th row 34 | always@(posedge clk or negedge rst_n) begin 35 | if(!rst_n) 36 | row3_data <= 0; 37 | else begin 38 | if(per_frame_href) 39 | row3_data <= per_img_Data; 40 | else 41 | row3_data <= row3_data; 42 | end 43 | end 44 | 45 | //--------------------------------------- 46 | //module of shift ram for raw data 47 | wire shift_clk_en = per_frame_href; 48 | Line_Shift_RAM #( 49 | .RAM_Length ( IMG_HDISP ), 50 | .DATA_WIDTH ( DATA_WIDTH ) 51 | ) u_Line_Shift_RAM ( 52 | .clock ( clk ), 53 | .clken ( shift_clk_en ), 54 | .shiftin ( row3_data ), 55 | 56 | .taps0x ( row2_data ), 57 | .taps1x ( row1_data ) 58 | ); 59 | //------------------------------------------ 60 | //lag 2 clocks signal sync 61 | reg [1:0] per_frame_vsync_r; 62 | reg [1:0] per_frame_href_r; 63 | always@(posedge clk or negedge rst_n) begin 64 | if(!rst_n) begin 65 | per_frame_vsync_r <= 0; 66 | per_frame_href_r <= 0; 67 | end 68 | else begin 69 | per_frame_vsync_r <= {per_frame_vsync_r[0], per_frame_vsync}; 70 | per_frame_href_r <= {per_frame_href_r[0], per_frame_href}; 71 | end 72 | end 73 | //Give up the 1th and 2th row edge data caculate for simple process 74 | //Give up the 1th and 2th point of 1 line for simple process 75 | wire read_frame_href = per_frame_href_r[0]; //RAM read href sync signal 76 | assign matrix_frame_vsync = per_frame_vsync_r[1]; 77 | assign matrix_frame_href = per_frame_href_r[1]; 78 | 79 | //---------------------------------------------------------------------------- 80 | //---------------------------------------------------------------------------- 81 | /****************************************************************************** 82 | ---------- Convert Matrix ---------- 83 | [ P31 -> P32 -> P33 -> ] ---> [ P11 P12 P13 ] 84 | [ P21 -> P22 -> P23 -> ] ---> [ P21 P22 P23 ] 85 | [ P11 -> P12 -> P11 -> ] ---> [ P31 P32 P33 ] 86 | ******************************************************************************/ 87 | //--------------------------------------------------------------------------- 88 | //--------------------------------------------------- 89 | /*********************************************** 90 | (1) Read data from Shift_RAM 91 | (2) Caculate the Sobel 92 | (3) Steady data after Sobel generate 93 | ************************************************/ 94 | //wire [2:0] matrix_row1 = {matrix_p11, matrix_p12, matrix_p13}; //Just for test 95 | //wire [2:0] matrix_row2 = {matrix_p21, matrix_p22, matrix_p23}; 96 | //wire [2:0] matrix_row3 = {matrix_p31, matrix_p32, matrix_p33}; 97 | always@(posedge clk or negedge rst_n) begin 98 | if(!rst_n) begin 99 | {matrix_p11, matrix_p12, matrix_p13} <= 0; 100 | {matrix_p21, matrix_p22, matrix_p23} <= 0; 101 | {matrix_p31, matrix_p32, matrix_p33} <= 0; 102 | end 103 | else if(read_frame_href) begin 104 | {matrix_p11, matrix_p12, matrix_p13} <= {matrix_p12, matrix_p13, row1_data}; //1th shift input 105 | {matrix_p21, matrix_p22, matrix_p23} <= {matrix_p22, matrix_p23, row2_data}; //2th shift input 106 | {matrix_p31, matrix_p32, matrix_p33} <= {matrix_p32, matrix_p33, row3_data}; //3th shift input 107 | end 108 | else begin 109 | {matrix_p11, matrix_p12, matrix_p13} <= 0; 110 | {matrix_p21, matrix_p22, matrix_p23} <= 0; 111 | {matrix_p31, matrix_p32, matrix_p33} <= 0; 112 | end 113 | end 114 | 115 | endmodule 116 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Matrix/Matrix_Generate_3X3_Buf.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Matrix_Generate_3X3_Buf #( 3 | parameter DATA_WIDTH = 8, 4 | parameter IMG_HDISP = 640, //640*480 5 | parameter IMG_VDISP = 480 6 | ) ( 7 | //global clock 8 | input clk, //cmos video pixel clock 9 | input rst_n, //global reset 10 | 11 | //Image data prepred to be processd 12 | input per_frame_vsync, //Prepared Image data vsync valid signal 13 | input per_frame_href, //Prepared Image data href vaild signal 14 | input [DATA_WIDTH-1:0] per_img_Data, //Prepared Image brightness input 15 | 16 | //Image data has been processd 17 | output matrix_frame_vsync, //Prepared Image data vsync valid signal 18 | output matrix_frame_href, //Prepared Image data href vaild signal 19 | 20 | output reg [DATA_WIDTH-1:0] matrix_p11, matrix_p12, matrix_p13, //3X3 Matrix output 21 | output reg [DATA_WIDTH-1:0] matrix_p21, matrix_p22, matrix_p23, 22 | output reg [DATA_WIDTH-1:0] matrix_p31, matrix_p32, matrix_p33 23 | ); 24 | 25 | 26 | //Generate 3*3 matrix 27 | //-------------------------------------------------------------------------- 28 | //-------------------------------------------------------------------------- 29 | //-------------------------------------------------------------------------- 30 | //sync row3_data with per_frame_clken & row1_data & raw2_data 31 | wire [DATA_WIDTH-1:0] row1_data; //frame data of the 1th row 32 | wire [DATA_WIDTH-1:0] row2_data; //frame data of the 2th row 33 | reg [DATA_WIDTH-1:0] row3_data; //frame data of the 3th row 34 | always@(posedge clk or negedge rst_n) begin 35 | if(!rst_n) 36 | row3_data <= 0; 37 | else begin 38 | if(per_frame_href) 39 | row3_data <= per_img_Data; 40 | else 41 | row3_data <= row3_data; 42 | end 43 | end 44 | 45 | //--------------------------------------- 46 | //module of shift ram for raw data 47 | wire shift_clk_en = per_frame_href; 48 | Line_Shift_RAM #( 49 | .RAM_Length ( IMG_HDISP ), 50 | .DATA_WIDTH ( DATA_WIDTH ) 51 | ) u_Line_Shift_RAM ( 52 | .clock ( clk ), 53 | .clken ( shift_clk_en ), 54 | .shiftin ( row3_data ), 55 | 56 | .taps0x ( row2_data ), 57 | .taps1x ( row1_data ) 58 | ); 59 | //------------------------------------------ 60 | //lag 2 clocks signal sync 61 | reg [2:0] per_frame_vsync_r; 62 | reg [2:0] per_frame_href_r; 63 | always@(posedge clk or negedge rst_n) begin 64 | if(!rst_n) begin 65 | per_frame_vsync_r <= 0; 66 | per_frame_href_r <= 0; 67 | end 68 | else begin 69 | per_frame_vsync_r <= {per_frame_vsync_r[1:0], per_frame_vsync}; 70 | per_frame_href_r <= {per_frame_href_r[1:0], per_frame_href}; 71 | end 72 | end 73 | //Give up the 1th and 2th row edge data caculate for simple process 74 | //Give up the 1th and 2th point of 1 line for simple process 75 | wire read_frame_href = per_frame_href_r[0]|per_frame_href_r[1]; //RAM read href sync signal 76 | assign matrix_frame_vsync = per_frame_vsync_r[2]; 77 | assign matrix_frame_href = per_frame_href_r[2]; 78 | 79 | //---------------------------------------------------------------------------- 80 | //---------------------------------------------------------------------------- 81 | /****************************************************************************** 82 | ---------- Convert Matrix ---------- 83 | [ P31 -> P32 -> P33 -> ] ---> [ P11 P12 P13 ] 84 | [ P21 -> P22 -> P23 -> ] ---> [ P21 P22 P23 ] 85 | [ P11 -> P12 -> P11 -> ] ---> [ P31 P32 P33 ] 86 | ******************************************************************************/ 87 | //--------------------------------------------------------------------------- 88 | //--------------------------------------------------- 89 | /*********************************************** 90 | (1) Read data from Shift_RAM 91 | (2) Caculate the Sobel 92 | (3) Steady data after Sobel generate 93 | ************************************************/ 94 | //wire [23:0] matrix_row1 = {matrix_p11, matrix_p12, matrix_p13}; //Just for test 95 | //wire [23:0] matrix_row2 = {matrix_p21, matrix_p22, matrix_p23}; 96 | //wire [23:0] matrix_row3 = {matrix_p31, matrix_p32, matrix_p33}; 97 | reg [31:0] pixel_cnt; 98 | reg [DATA_WIDTH-1:0] row1_data0; 99 | reg [DATA_WIDTH-1:0] row2_data0; 100 | reg [DATA_WIDTH-1:0] row3_data0; 101 | reg [DATA_WIDTH-1:0] row1_data1; 102 | reg [DATA_WIDTH-1:0] row2_data1; 103 | reg [DATA_WIDTH-1:0] row3_data1; 104 | always@(posedge clk or negedge rst_n) begin 105 | if(!rst_n) begin 106 | pixel_cnt <= 0; 107 | row1_data0 <= 0; row1_data1 <= 0; 108 | row2_data0 <= 0; row2_data1 <= 0; 109 | row3_data0 <= 0; row3_data1 <= 0; 110 | {matrix_p11, matrix_p12, matrix_p13} <= 0; 111 | {matrix_p21, matrix_p22, matrix_p23} <= 0; 112 | {matrix_p31, matrix_p32, matrix_p33} <= 0; 113 | end 114 | else if(read_frame_href) begin 115 | pixel_cnt <= (pixel_cnt < IMG_HDISP) ? pixel_cnt + 1'b1 : 32'd0; //Point Counter 116 | {row1_data1, row1_data0} <= {row1_data0, row1_data}; 117 | {row2_data1, row2_data0} <= {row2_data0, row2_data}; 118 | {row3_data1, row3_data0} <= {row3_data0, row3_data}; 119 | if(pixel_cnt == 0) begin 120 | {matrix_p11, matrix_p12, matrix_p13} <= 0; 121 | {matrix_p21, matrix_p22, matrix_p23} <= 0; 122 | {matrix_p31, matrix_p32, matrix_p33} <= 0; 123 | end 124 | else if(pixel_cnt == 1) begin 125 | {matrix_p11, matrix_p12, matrix_p13} <= {row1_data, row1_data0, row1_data}; 126 | {matrix_p21, matrix_p22, matrix_p23} <= {row2_data, row2_data0, row2_data}; 127 | {matrix_p31, matrix_p32, matrix_p33} <= {row3_data, row3_data0, row3_data}; 128 | end 129 | else if(pixel_cnt == IMG_HDISP) begin 130 | {matrix_p11, matrix_p12, matrix_p13} <= {row1_data1, row1_data, row1_data1}; 131 | {matrix_p21, matrix_p22, matrix_p23} <= {row2_data1, row2_data, row2_data1}; 132 | {matrix_p31, matrix_p32, matrix_p33} <= {row3_data1, row3_data, row3_data1}; 133 | end 134 | else begin 135 | {matrix_p11, matrix_p12, matrix_p13} <= {row1_data1, row1_data0, row1_data}; 136 | {matrix_p21, matrix_p22, matrix_p23} <= {row2_data1, row2_data0, row2_data}; 137 | {matrix_p31, matrix_p32, matrix_p33} <= {row3_data1, row3_data0, row3_data}; 138 | end 139 | end 140 | else begin 141 | pixel_cnt <= 0; 142 | {matrix_p11, matrix_p12, matrix_p13} <= 0; 143 | {matrix_p21, matrix_p22, matrix_p23} <= 0; 144 | {matrix_p31, matrix_p32, matrix_p33} <= 0; 145 | end 146 | end 147 | 148 | endmodule 149 | -------------------------------------------------------------------------------- /user/src/Video_Image_Processor/Basic_Apply/Video_Image_Processor.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module Video_Image_Processor #( 3 | parameter RAW2RG888_YUV444 = "ON", 4 | parameter GRAY_MEDIUM = "ON", 5 | parameter GRAY_SOBEL = "ON", 6 | parameter GRAY_EROSION = "ON", 7 | parameter GRAY_DILATION = "ON", 8 | parameter IMG_HDISP = 11'd640, //640*480 9 | parameter IMG_VDISP = 11'd480 10 | ) ( 11 | //global clock 12 | input clk, //cmos video pixel clock 13 | input rst_n, //global reset 14 | //Image data prepred to be processd 15 | input per_frame_vsync, //Prepared Image data vsync valid signal 16 | input per_frame_href, //Prepared Image data href vaild signal 17 | input [7:0] per_img_RAW, //Prepared Image data of YCbCr 4:2:2 {CbY} {CrY} 18 | //Image data has been processd 19 | output post_frame_vsync, //Processed Image data vsync valid signal 20 | output post_frame_href, //Processed Image data href vaild signal 21 | output [7:0] post_img_Gray, //Processed Image Gray output 22 | //user interface 23 | input [7:0] Sobel_Threshold //Sobel Threshold for image edge detect 24 | ); 25 | 26 | //------------------------------------- 27 | //Convert the RAW format to RGB888 format. 28 | wire post1_frame_vsync; //Processed Image data vsync valid signal 29 | wire post1_frame_href; //Processed Image data href vaild signal 30 | wire [7:0] post1_img_red; //Processed Image Red output 31 | wire [7:0] post1_img_green; //Processed Image Green output 32 | wire [7:0] post1_img_blue; //Processed Image Blueoutput 33 | wire post2_frame_vsync; //Processed Image data vsync valid signal 34 | wire post2_frame_href; //Processed Image data href vaild signal 35 | wire [7:0] post2_img_Gray; //Processed Image Gray output 36 | 37 | generate if(RAW2RG888_YUV444 == "ON") begin : RAW2RG888_YUV444_ON 38 | RAW8_RGB888 # ( 39 | .IMG_HDISP (IMG_HDISP), //640*480 40 | .IMG_VDISP (IMG_VDISP) 41 | ) RAW8_RGB888_u ( 42 | //global clock 43 | .clk (clk), //cmos video pixel clock 44 | .rst_n (rst_n), //system reset 45 | 46 | //Image data prepred to be processd 47 | .per_frame_vsync (per_frame_vsync), //Prepared Image data vsync valid signal 48 | .per_frame_href (per_frame_href), //Prepared Image data href vaild signal 49 | .per_img_RAW (per_img_RAW), //Prepared Image data 8 Bit RAW Data 50 | 51 | //Image data has been processd 52 | .post_frame_vsync (post1_frame_vsync), //Processed Image data vsync valid signal 53 | .post_frame_href (post1_frame_href), //Processed Image data href vaild signal 54 | .post_img_red (post1_img_red), //Prepared Image green data to be processed 55 | .post_img_green (post1_img_green), //Prepared Image green data to be processed 56 | .post_img_blue (post1_img_blue) //Prepared Image blue data to be processed 57 | ); 58 | //------------------------------------- 59 | //Convert the RGB888 format to YCbCr444 format. 60 | RGB888_YCbCr444 RGB888_YCbCr444_u( 61 | //global clock 62 | .clk (clk), //cmos video pixel clock 63 | .rst_n (rst_n), //system reset 64 | 65 | //Image data prepred to be processd 66 | .per_frame_vsync (post1_frame_vsync), //Prepared Image data vsync valid signal 67 | .per_frame_href (post1_frame_href), //Prepared Image data href vaild signal 68 | .per_img_red (post1_img_red), //Prepared Image red data input 69 | .per_img_green (post1_img_green), //Prepared Image green data input 70 | .per_img_blue (post1_img_blue), //Prepared Image blue data input 71 | 72 | //Image data has been processd 73 | .post_frame_vsync (post2_frame_vsync), //Processed Image frame data valid signal 74 | .post_frame_href (post2_frame_href), //Processed Image hsync data valid signal 75 | .post_img_Y (post2_img_Gray), //Processed Image brightness output 76 | .post_img_Cb (), //Processed Image blue shading output 77 | .post_img_Cr () //Processed Image red shading output 78 | ); 79 | end 80 | else if(RAW2RG888_YUV444 == "OFF") begin : RAW2RG888_YUV444_OFF 81 | assign post2_frame_vsync = per_frame_vsync; 82 | assign post2_frame_href = per_frame_href; 83 | assign post2_img_Gray = per_img_RAW; 84 | end 85 | endgenerate 86 | 87 | //-------------------------------------- 88 | //Gray Image median filter for better picture quality. 89 | wire post3_frame_vsync; //Processed Image data vsync valid signal 90 | wire post3_frame_href; //Processed Image data href vaild signal 91 | wire [7:0] post3_img_Gray; //Processed Image Gray output 92 | generate if(GRAY_MEDIUM == "ON") begin : GRAY_MEDIUM_ON 93 | Gray_Median_Filter # ( 94 | .IMG_HDISP (IMG_HDISP), //640*480 95 | .IMG_VDISP (IMG_VDISP) 96 | ) Gray_Median_Filter_u ( 97 | //global clock 98 | .clk (clk), //cmos video pixel clock 99 | .rst_n (rst_n), //global reset 100 | 101 | //Image data prepred to be processd 102 | .per_frame_vsync (post2_frame_vsync), //Prepared Image data vsync valid signal 103 | .per_frame_href (post2_frame_href), //Prepared Image data href vaild signal 104 | .per_img_Gray (post2_img_Gray), //Prepared Image brightness input 105 | 106 | //Image data has been processd 107 | .post_frame_vsync (post3_frame_vsync), //Processed Image data vsync valid signal 108 | .post_frame_href (post3_frame_href), //Processed Image data href vaild signal 109 | .post_img_Gray (post3_img_Gray) //Processed Image brightness output 110 | ); 111 | end 112 | else if(GRAY_MEDIUM == "OFF") begin : GRAY_MEDIUM_OFF 113 | assign post3_frame_vsync = post2_frame_vsync; 114 | assign post3_frame_href = post2_frame_href; 115 | assign post3_img_Gray = post2_img_Gray; 116 | end 117 | endgenerate 118 | 119 | //-------------------------------------- 120 | //Image edge detector with Sobel. 121 | wire post4_frame_vsync; //Processed Image data vsync valid signal 122 | wire post4_frame_href; //Processed Image data href vaild signal 123 | wire post4_img_Bit; //Processed Image Bit flag outout(1: Value, 0:inValid) 124 | wire [7:0] post4_img_Gray; 125 | generate if(GRAY_SOBEL == "ON") begin : GRAY_SOBEL_ON 126 | Sobel_Edge_Detector # ( 127 | .IMG_HDISP (IMG_HDISP), //640*480 128 | .IMG_VDISP (IMG_VDISP) 129 | ) Sobel_Edge_Detector_u ( 130 | //global clock 131 | .clk (clk), //cmos video pixel clock 132 | .rst_n (rst_n), //global reset 133 | 134 | //Image data prepred to be processd 135 | .per_frame_vsync (post3_frame_vsync), //Prepared Image data vsync valid signal 136 | .per_frame_href (post3_frame_href), //Prepared Image data href vaild signal 137 | .per_img_Gray (post3_img_Gray), //Prepared Image brightness input 138 | 139 | //Image data has been processd 140 | .post_frame_vsync (post4_frame_vsync), //Processed Image data vsync valid signal 141 | .post_frame_href (post4_frame_href), //Processed Image data href vaild signal 142 | .post_img_Bit (post4_img_Bit), //Processed Image Bit flag outout(1: Value, 0:inValid) 143 | 144 | //User interface 145 | .Sobel_Threshold (Sobel_Threshold) //Sobel Threshold for image edge detect 146 | ); 147 | assign post4_img_Gray = {8{~post4_img_Bit}}; 148 | end 149 | else if(GRAY_SOBEL == "OFF") begin : GRAY_SOBEL_OFF 150 | assign post4_frame_vsync = post3_frame_vsync; 151 | assign post4_frame_href = post3_frame_href; 152 | assign post4_img_Gray = post3_img_Gray; 153 | end 154 | endgenerate 155 | 156 | //-------------------------------------- 157 | //Bit Image Process with Erosion before Dilation Detector. 158 | wire post5_frame_vsync; //Processed Image data vsync valid signal 159 | wire post5_frame_href; //Processed Image data href vaild signal 160 | wire post5_img_Bit; //Processed Image Bit flag outout(1: Value, 0:inValid) 161 | wire [7:0] post5_img_Gray; 162 | generate if(GRAY_EROSION == "ON") begin : GRAY_EROSION_ON 163 | Bit_Erosion_Detector # ( 164 | .IMG_HDISP (IMG_HDISP), //640*480 165 | .IMG_VDISP (IMG_VDISP) 166 | ) Bit_Erosion_Detector_u ( 167 | //global clock 168 | .clk (clk), //cmos video pixel clock 169 | .rst_n (rst_n), //global reset 170 | 171 | //Image data prepred to be processd 172 | .per_frame_vsync (post4_frame_vsync), //Prepared Image data vsync valid signal 173 | .per_frame_href (post4_frame_href), //Prepared Image data href vaild signal 174 | .per_img_Bit (post4_img_Gray[0]), //Processed Image Bit flag outout(1: Value, 0:inValid) 175 | 176 | //Image data has been processd 177 | .post_frame_vsync (post5_frame_vsync), //Processed Image data vsync valid signal 178 | .post_frame_href (post5_frame_href), //Processed Image data href vaild signal 179 | .post_img_Bit (post5_img_Bit) //Processed Image Bit flag outout(1: Value, 0:inValid) 180 | ); 181 | assign post5_img_Gray = {8{post5_img_Bit}}; 182 | end 183 | else if(GRAY_EROSION == "OFF") begin : GRAY_EROSION_OFF 184 | assign post5_frame_vsync = post4_frame_vsync; 185 | assign post5_frame_href = post4_frame_href; 186 | assign post5_img_Gray = post4_img_Gray; 187 | end 188 | endgenerate 189 | 190 | //-------------------------------------- 191 | //Bit Image Process with Dilation after Erosion Detector. 192 | wire post6_frame_vsync; //Processed Image data vsync valid signal 193 | wire post6_frame_href; //Processed Image data href vaild signal 194 | wire post6_img_Bit; //Processed Image Bit flag outout(1: Value, 0:inValid) 195 | wire [7:0] post6_img_Gray; 196 | generate if(GRAY_DILATION == "ON") begin : GRAY_DILATION_ON 197 | Bit_Dilation_Detector # ( 198 | .IMG_HDISP (IMG_HDISP), //640*480 199 | .IMG_VDISP (IMG_VDISP) 200 | ) Bit_Dilation_Detector_u ( 201 | //global clock 202 | .clk (clk), //cmos video pixel clock 203 | .rst_n (rst_n), //global reset 204 | 205 | //Image data prepred to be processd 206 | .per_frame_vsync (post5_frame_vsync), //Prepared Image data vsync valid signal 207 | .per_frame_href (post5_frame_href), //Prepared Image data href vaild signal 208 | .per_img_Bit (post5_img_Gray[0]), //Processed Image Bit flag outout(1: Value, 0:inValid) 209 | 210 | //Image data has been processd 211 | .post_frame_vsync (post6_frame_vsync), //Processed Image data vsync valid signal 212 | .post_frame_href (post6_frame_href), //Processed Image data href vaild signal 213 | .post_img_Bit (post6_img_Bit) //Processed Image Bit flag outout(1: Value, 0:inValid) 214 | ); 215 | assign post6_img_Gray = {8{post6_img_Bit}}; 216 | end 217 | else if(GRAY_DILATION == "OFF") begin : GRAY_DILATION_OFF 218 | assign post6_frame_vsync = post5_frame_vsync; 219 | assign post6_frame_href = post5_frame_href; 220 | assign post6_img_Gray = post5_img_Gray; 221 | end 222 | endgenerate 223 | 224 | assign post_frame_vsync = post6_frame_vsync; //Processed Image data vsync valid signal 225 | assign post_frame_href = post6_frame_href; //Processed Image data href vaild signal 226 | assign post_img_Gray = post6_img_Gray; //Processed Image Gray output 227 | 228 | endmodule 229 | --------------------------------------------------------------------------------