├── .gitignore ├── .gitlab-ci.yml ├── Dockerfile ├── LICENSE ├── Makefile ├── README.md ├── cmos.default ├── cmos.layout ├── devicetree-v2.cb ├── devicetree.cb ├── flash.sh ├── gpio.c ├── nitropad-ns50-defconfig ├── nitropad-ns50.mk ├── nitropad-nv41-defconfig ├── nitropad-nv41.mk ├── nitropc-defconfig ├── nitropc-v2-Kconfig ├── nitropc-v2-defconfig ├── nitropc-v2-mainboard.c ├── nitropc-v2.mk ├── nitropc.mk ├── nitrowall-defconfig ├── nitrowall-pro-defconfig ├── nitrowall-pro.mk └── nitrowall.mk /.gitignore: -------------------------------------------------------------------------------- 1 | blobs 2 | coreboot 3 | docker-image 4 | -------------------------------------------------------------------------------- /.gitlab-ci.yml: -------------------------------------------------------------------------------- 1 | 2 | include: 3 | - project: 'nitrokey/gitlab-ci' 4 | file: 5 | - 'common-jobs/common_jobs.yml' 6 | 7 | stages: 8 | - pull-github 9 | - build 10 | - deploy 11 | 12 | variables: 13 | #Repo for shared scripts (pull.sh release.sh, nightly_upload.sh): 14 | GIT_STRATEGY: clone #This seems to have no effect also set in webinterface 15 | GIT_DEPTH: 0 #This seems to have no effect also set in webinterface 16 | GIT_SUBMODULE_STRATEGY: recursive #This seems to have no effect also set in webinterfac 17 | REPO_USER: nitrokey 18 | REPO_NAME: coreboot-builder 19 | MAIN_BRANCH: main 20 | COMMON_PULL: "true" 21 | COMMON_UPLOAD_NIGHTLY: "false" 22 | COMMON_GITHUB_RELEASE: "false" 23 | COMMON_UPLOAD_FILES: "false" 24 | DEVICE_FOLDER: "nitropc" 25 | UPLOAD_FOLDER: "tianocore" 26 | 27 | build-nitropc: 28 | rules: 29 | - if: '$CI_PIPELINE_SOURCE == "push"' 30 | tags: 31 | - docker 32 | image: $CI_REGISTRY/nitrokey/coreboot-builder:latest 33 | stage: build 34 | script: 35 | - make nitropc SKIP_DOCKER=true 36 | - mkdir -p artifacts 37 | - cp firmware-nitropc.rom artifacts/ 38 | artifacts: 39 | paths: 40 | - artifacts 41 | 42 | build-nitropc-v2: 43 | rules: 44 | - if: '$CI_PIPELINE_SOURCE == "push"' 45 | tags: 46 | - docker 47 | image: $CI_REGISTRY/nitrokey/coreboot-builder:latest 48 | stage: build 49 | script: 50 | - make nitropc-v2 SKIP_DOCKER=true 51 | - mkdir -p artifacts 52 | - cp firmware-nitropc-v2.rom artifacts/ 53 | artifacts: 54 | paths: 55 | - artifacts 56 | 57 | build-nitrowall-pro: 58 | rules: 59 | - if: '$CI_PIPELINE_SOURCE == "push"' 60 | tags: 61 | - docker 62 | image: $CI_REGISTRY/nitrokey/coreboot-builder:latest 63 | stage: build 64 | script: 65 | - make nitrowall-pro SKIP_DOCKER=true 66 | - mkdir -p artifacts 67 | - cp firmware-nitrowall-pro.rom artifacts/ 68 | artifacts: 69 | paths: 70 | - artifacts 71 | 72 | build-nitropad-nv41: 73 | rules: 74 | - if: '$CI_PIPELINE_SOURCE == "push"' 75 | tags: 76 | - docker 77 | image: $CI_REGISTRY/nitrokey/coreboot-builder:latest 78 | stage: build 79 | script: 80 | - make nitropad-nv41 SKIP_DOCKER=true 81 | - mkdir -p artifacts 82 | - cp firmware-nitropad-nv41.rom artifacts/ 83 | artifacts: 84 | paths: 85 | - artifacts 86 | 87 | build-nitropad-ns50: 88 | rules: 89 | - if: '$CI_PIPELINE_SOURCE == "push"' 90 | tags: 91 | - docker 92 | image: $CI_REGISTRY/nitrokey/coreboot-builder:latest 93 | stage: build 94 | script: 95 | - make nitropad-ns50 SKIP_DOCKER=true 96 | - mkdir -p artifacts 97 | - cp firmware-nitropad-ns50.rom artifacts/ 98 | artifacts: 99 | paths: 100 | - artifacts 101 | 102 | build-nitrowall: 103 | rules: 104 | - if: '$CI_PIPELINE_SOURCE == "push"' 105 | tags: 106 | - docker 107 | image: $CI_REGISTRY/nitrokey/coreboot-builder:latest 108 | stage: build 109 | script: 110 | - make nitrowall SKIP_DOCKER=true 111 | - mkdir -p artifacts 112 | - cp firmware-nitrowall.rom artifacts/ 113 | artifacts: 114 | paths: 115 | - artifacts 116 | -------------------------------------------------------------------------------- /Dockerfile: -------------------------------------------------------------------------------- 1 | FROM debian:11 2 | RUN apt-get update && apt-get install -y \ 3 | git build-essential gnat flex bison libncurses5-dev wget zlib1g-dev python3 nasm uuid-dev python pkg-config imagemagick openssl libssl-dev curl python3-apt python3-distutils iasl nasm python3-pip 4 | 5 | RUN pip3 install -q uefi_firmware 6 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Use with the GNU Affero General Public License. 553 | 554 | Notwithstanding any other provision of this License, you have 555 | permission to link or combine any covered work with a work licensed 556 | under version 3 of the GNU Affero General Public License into a single 557 | combined work, and to convey the resulting work. The terms of this 558 | License will continue to apply to the part which is the covered work, 559 | but the special requirements of the GNU Affero General Public License, 560 | section 13, concerning interaction through a network will apply to the 561 | combination as such. 562 | 563 | 14. Revised Versions of this License. 564 | 565 | The Free Software Foundation may publish revised and/or new versions of 566 | the GNU General Public License from time to time. Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | 2 | ##### docker env 3 | 4 | CPU_COUNT = $(shell nproc) 5 | BASEDIR = $(shell pwd) 6 | 7 | CONTNAME = coreboot-builder 8 | SRCDIR = $(BASEDIR) 9 | 10 | COREBOOT_REMOTE ?= https://review.coreboot.org/coreboot 11 | 12 | DOCKERDIR = $(BASEDIR) 13 | DOCKERUIDGID = --user $(shell id -u):$(shell id -g) 14 | #DOCKERUIDGID= 15 | 16 | COREBOOT_ORIGIN = https://review.coreboot.org/coreboot 17 | COREBOOT_DASHARO = https://github.com/Dasharo/coreboot.git 18 | 19 | BLOBS_COMMIT = cba08e83d8bbd7d3470769afd7dbc8e61d6cd8b5 20 | 21 | ## 22 | ## switch mechanism for with or without docker 23 | ## 24 | DOCKER_RUN := docker run $(DOCKERUIDGID) --name $(CONTNAME) \ 25 | --mount type=bind,source=$(SRCDIR),target=/build \ 26 | $(CONTNAME)-img make -C /build 27 | 28 | ifeq ($(SKIP_DOCKER),true) 29 | DOCKER_RUN := make 30 | endif 31 | 32 | 33 | all: 34 | @echo "no default target" 35 | @echo "choose any of: " 36 | @echo " nitropc, nitrowall, nitrowall-pro, nitropad-nv41, nitropad-ns50, nitropc-v2" 37 | 38 | nitropc: 39 | $(MAKE) TARGET=nitropc firmware-nitropc.rom 40 | nitropc-v2: 41 | $(MAKE) TARGET=nitropc-v2 firmware-nitropc-v2.rom 42 | nitrowall: 43 | $(MAKE) TARGET=nitrowall firmware-nitrowall.rom 44 | nitrowall-pro: 45 | $(MAKE) TARGET=nitrowall-pro firmware-nitrowall-pro.rom 46 | nitropad-nv41: 47 | $(MAKE) TARGET=nitropad-nv41 firmware-nitropad-nv41.rom 48 | nitropad-ns50: 49 | $(MAKE) TARGET=nitropad-ns50 firmware-nitropad-ns50.rom 50 | 51 | coreboot/configs/defconfig: coreboot-update $(TARGET)-defconfig 52 | cp $(TARGET)-defconfig coreboot/configs/defconfig 53 | 54 | -include $(TARGET).mk 55 | 56 | firmware-$(TARGET).rom: raw_firmware.rom 57 | cp raw_firmware.rom firmware-$(TARGET).rom 58 | # -> BUILD DONE 59 | 60 | docker-image: Dockerfile 61 | docker build -t $(CONTNAME)-img . 62 | touch $@ 63 | 64 | docker-enter: 65 | -docker rm coreboot-builder 66 | docker run -it $(DOCKERUIDGUID) --name $(CONTNAME) \ 67 | --mount type=bind,source=$(SRCDIR),target=/build \ 68 | $(CONTNAME)-img bash 69 | 70 | docker-run: 71 | -docker rm coreboot-builder 72 | docker run -it $(DOCKERUIDGUID) --name $(CONTNAME) \ 73 | --mount type=bind,source=$(SRCDIR),target=/build \ 74 | $(CONTNAME)-img $(CMD) 75 | 76 | 77 | upload-docker-image: 78 | docker image tag $(CONTNAME)-img registry.git.nitrokey.com/nitrokey/coreboot-builder:latest 79 | docker login registry.git.nitrokey.com 80 | docker push registry.git.nitrokey.com/nitrokey/coreboot-builder:latest 81 | 82 | blobs: 83 | git clone https://github.com/Nitrokey/firmware-blobs.git blobs 84 | .PHONY: blobs-update 85 | blobs-update: blobs 86 | cd blobs && git fetch 87 | cd blobs && git checkout $(BLOBS_COMMIT) 88 | 89 | raw_firmware.rom: coreboot/configs/defconfig blobs-update 90 | 91 | make -C coreboot defconfig 92 | 93 | -docker rm coreboot-builder 94 | # for debug outputs: 95 | #$(DOCKER_RUN) TARGET=$(TARGET) V=1 coreboot/build/coreboot.rom 96 | $(DOCKER_RUN) TARGET=$(TARGET) coreboot/build/coreboot.rom 97 | 98 | cp coreboot/build/coreboot.rom raw_firmware.rom 99 | 100 | coreboot/util/crossgcc/xgcc: coreboot-update 101 | make -C coreboot crossgcc-i386 CPUS=$(CPU_COUNT) 102 | 103 | coreboot/bootsplash.bmp: blobs/common/bootsplash.bmp coreboot-update blobs-update 104 | cp $< $@ 105 | coreboot/bootsplash.jpg: blobs/common/bootsplash.jpg coreboot-update blobs-update 106 | cp $< $@ 107 | 108 | coreboot: 109 | git clone $(COREBOOT_ORIGIN) coreboot 110 | cd coreboot && \ 111 | git remote add dasharo $(COREBOOT_DASHARO) && \ 112 | git fetch dasharo && \ 113 | git fetch dasharo --tags -f && \ 114 | git fetch origin --tags -f && \ 115 | git fetch origin 116 | 117 | 118 | .PHONY: coreboot-update 119 | coreboot-update: coreboot 120 | cd coreboot && \ 121 | git reset --hard && \ 122 | git checkout $(COREBOOT_REF) 123 | 124 | distclean: 125 | make -C coreboot distclean 126 | 127 | clean-all: clean 128 | rm -rf coreboot docker-image 129 | rm -rf blobs 130 | 131 | clean: 132 | rm -f firmware.rom raw_firmware.rom firmware-*.rom 133 | rm -f run-build defconfig 134 | rm -rf coreboot blobs 135 | 136 | 137 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # coreboot-builder 2 | Builder Repository for Nitrokey Coreboot Devices 3 | 4 | Run: 5 | ``` 6 | make docker-image 7 | make 8 | ``` 9 | to see which devices can be built. 10 | -------------------------------------------------------------------------------- /cmos.default: -------------------------------------------------------------------------------- 1 | power_on_after_fail=Enable 2 | -------------------------------------------------------------------------------- /cmos.layout: -------------------------------------------------------------------------------- 1 | ## SPDX-License-Identifier: GPL-2.0-only 2 | 3 | entries 4 | 5 | # start-bit length config config-ID name 6 | 0 112 r 0 reserved_memory 7 | 400 80 r 0 ramtop 8 | 1352 8 e 1 power_on_after_fail 9 | 10 | enumerations 11 | #ID value text 12 | 1 0 Enable 13 | 1 1 Disable 14 | 15 | checksums 16 | 17 | # The EC firmware does initialize power_on_after_fail if it is invalid, but it 18 | # does not have a checksum. Put a checksum at the end of bank 1. 19 | checksum 1352 1359 1520 20 | -------------------------------------------------------------------------------- /devicetree-v2.cb: -------------------------------------------------------------------------------- 1 | chip soc/intel/cannonlake 2 | 3 | # CPU (soc/intel/cannonlake/cpu.c) 4 | # Power limit 5 | register "power_limits_config" = "{ 6 | .tdp_pl1_override = 15, 7 | .tdp_pl2_override = 25, 8 | }" 9 | 10 | # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) 11 | register "SaGv" = "SaGv_FixedHigh" 12 | 13 | # FSP Silicon (soc/intel/cannonlake/fsp_params.c) 14 | 15 | # Thermal 16 | register "tcc_offset" = "12" 17 | 18 | # Serial IRQ Mode 19 | register "serirq_mode" = "SERIRQ_CONTINUOUS" 20 | 21 | # Actual device tree 22 | device domain 0 on 23 | device pci 14.0 on # USB xHCI 24 | chip drivers/usb/acpi 25 | device usb 0.0 on 26 | chip drivers/usb/acpi 27 | register "desc" = ""USB2 Type-A Rear Upper"" 28 | register "type" = "UPC_TYPE_A" 29 | register "group" = "ACPI_PLD_GROUP(1, 0)" 30 | device usb 2.0 on end 31 | end 32 | chip drivers/usb/acpi 33 | register "desc" = ""USB2 Type-A Rear Lower"" 34 | register "type" = "UPC_TYPE_A" 35 | register "group" = "ACPI_PLD_GROUP(1, 1)" 36 | device usb 2.1 on end 37 | end 38 | chip drivers/usb/acpi 39 | register "desc" = ""USB2 Type-A Front Left Upper"" 40 | register "type" = "UPC_TYPE_A" 41 | register "group" = "ACPI_PLD_GROUP(0, 0)" 42 | device usb 2.2 on end 43 | end 44 | chip drivers/usb/acpi 45 | register "desc" = ""USB2 Audio"" 46 | register "type" = "UPC_TYPE_INTERNAL" 47 | device usb 2.3 on end 48 | end 49 | chip drivers/usb/acpi 50 | device usb 2.4 on end 51 | end 52 | chip drivers/usb/acpi 53 | register "desc" = ""USB2 Type-C Port Rear"" 54 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" 55 | register "group" = "ACPI_PLD_GROUP(1, 2)" 56 | device usb 2.5 on end 57 | end 58 | chip drivers/usb/acpi 59 | register "desc" = ""USB2 Bluetooth"" 60 | register "type" = "UPC_TYPE_INTERNAL" 61 | device usb 2.6 on end 62 | end 63 | chip drivers/usb/acpi 64 | register "desc" = ""USB2 Type-A Front Right Upper"" 65 | register "type" = "UPC_TYPE_A" 66 | register "group" = "ACPI_PLD_GROUP(0, 3)" 67 | device usb 2.7 on end 68 | end 69 | chip drivers/usb/acpi 70 | register "desc" = ""USB2 Type-A Front Right Lower"" 71 | register "type" = "UPC_TYPE_A" 72 | register "group" = "ACPI_PLD_GROUP(0, 2)" 73 | device usb 2.8 on end 74 | end 75 | chip drivers/usb/acpi 76 | register "desc" = ""USB2 Type-A Front Left Lower"" 77 | register "type" = "UPC_TYPE_A" 78 | register "group" = "ACPI_PLD_GROUP(0, 1)" 79 | device usb 2.9 on end 80 | end 81 | chip drivers/usb/acpi 82 | register "desc" = ""USB3 Type-A Front Left Upper"" 83 | register "type" = "UPC_TYPE_USB3_A" 84 | register "group" = "ACPI_PLD_GROUP(0, 0)" 85 | device usb 3.0 on end 86 | end 87 | chip drivers/usb/acpi 88 | register "desc" = ""USB3 Type-A Front Left Lower"" 89 | register "type" = "UPC_TYPE_USB3_A" 90 | register "group" = "ACPI_PLD_GROUP(0, 1)" 91 | device usb 3.1 on end 92 | end 93 | chip drivers/usb/acpi 94 | register "desc" = ""USB3 Type-C Rear"" 95 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" 96 | register "group" = "ACPI_PLD_GROUP(1, 2)" 97 | device usb 3.2 on end 98 | end 99 | chip drivers/usb/acpi 100 | device usb 3.3 on end 101 | end 102 | chip drivers/usb/acpi 103 | register "desc" = ""USB3 Type-A Rear Lower"" 104 | register "type" = "UPC_TYPE_USB3_A" 105 | register "group" = "ACPI_PLD_GROUP(1, 1)" 106 | device usb 3.4 on end 107 | end 108 | chip drivers/usb/acpi 109 | register "desc" = ""USB3 Type-A Rear Upper"" 110 | register "type" = "UPC_TYPE_USB3_A" 111 | register "group" = "ACPI_PLD_GROUP(1, 0)" 112 | device usb 3.5 on end 113 | end 114 | end 115 | end 116 | register "usb2_ports" = "{ 117 | #define USB2_PORT_LIBREM_MINI(ocnum) { \ 118 | .enable = 1, \ 119 | .ocpin = ocnum, \ 120 | .tx_bias = USB2_BIAS_45MV, \ 121 | .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ 122 | .pre_emp_bias = USB2_BIAS_28P15MV, \ 123 | .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ 124 | } 125 | 126 | #define USB2_PORT_LIBREM_MINI2(ocnum) { \ 127 | .enable = 1, \ 128 | .ocpin = ocnum, \ 129 | .tx_bias = USB2_BIAS_56P3MV, \ 130 | .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ 131 | .pre_emp_bias = USB2_BIAS_28P15MV, \ 132 | .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ 133 | } 134 | 135 | [0] = USB2_PORT_LIBREM_MINI(OC2), /* Type-A rear upper */ 136 | [1] = USB2_PORT_LIBREM_MINI2(OC_SKIP), /* Type-A rear lower */ 137 | [2] = USB2_PORT_LIBREM_MINI(OC2), /* Type-A front left upper */ 138 | [3] = USB2_PORT_MID(OC2), /* Onboard audio */ 139 | [4] = USB2_PORT_MID(OC3), /* Unused? */ 140 | [5] = USB2_PORT_TYPE_C(OC3), /* Type-C rear */ 141 | [6] = USB2_PORT_MID(OC3), /* M.2-2230/Bluetooth */ 142 | [7] = USB2_PORT_MID(OC3), /* Type-A front right upper */ 143 | [8] = USB2_PORT_MID(OC_SKIP), /* Type-A front right lower */ 144 | [9] = USB2_PORT_LIBREM_MINI(OC_SKIP), /* Type-A front left lower */ 145 | }" 146 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A front left upper 147 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower 148 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-C rear 149 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Unused? 150 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A rear lower 151 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A rear upper 152 | end 153 | device pci 17.0 on # SATA 154 | register "SataPortsEnable[0]" = "1" # 2.5" 155 | register "SataPortsEnable[2]" = "1" # m.2 156 | register "satapwroptimize" = "1" 157 | end 158 | device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN) 159 | register "PcieRpSlotImplemented[7]" = "1" 160 | register "PcieRpEnable[7]" = "1" 161 | register "PcieRpLtrEnable[7]" = "1" 162 | # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC 163 | register "PcieClkSrcUsage[2]" = "0x80" 164 | smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" 165 | end 166 | device pci 1d.1 on # PCI Express Port 10 167 | device pci 00.0 on end # x1 (LAN) 168 | register "PcieRpEnable[9]" = "1" 169 | register "PcieClkSrcUsage[3]" = "9" 170 | register "PcieClkSrcClkReq[3]" = "3" 171 | end 172 | device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) 173 | register "PcieRpSlotImplemented[12]" = "1" 174 | register "PcieRpEnable[12]" = "1" 175 | register "PcieRpLtrEnable[12]" = "1" 176 | register "PcieClkSrcUsage[1]" = "12" 177 | register "PcieClkSrcClkReq[1]" = "1" 178 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" 179 | end 180 | device pci 1f.0 on # LPC Bridge 181 | 182 | register "gen1_dec" = "0x00040069" 183 | register "gen2_dec" = "0x00fc0e01" 184 | register "gen3_dec" = "0x00fc0f01" 185 | 186 | chip superio/ite/it8528e 187 | device pnp 2e.1 on # UART1 188 | io 0x60 = 0x3F8 189 | irq 0x70 = 0x04 190 | end 191 | device pnp 2e.2 on end # UART2 192 | device pnp 2e.4 on end # System Wake-Up Control (SWUC) 193 | device pnp 2e.5 on end # KBC/Mouse 194 | device pnp 2e.6 on end # KBC/Keyboard 195 | device pnp 2e.a on end # Consumer IR 196 | device pnp 2e.f on end # Shared Memory/Flash Interface (SMFI) 197 | device pnp 2e.10 on # RTC-like Timer 198 | io 0x62 = 0x360 # BRAM1 I/O base address 199 | end 200 | device pnp 2e.11 on end # Power Management I/F Channel 1 (PMC1) 201 | device pnp 2e.12 on end # Power Management I/F Channel 2 (PMC2) 202 | device pnp 2e.13 on end # Serial Peripheral Interface (SSPI) 203 | device pnp 2e.14 on end # Platform Environment Control Interface (PECI) 204 | device pnp 2e.17 on end # Power Management I/F Channel 3 (PMC3) 205 | device pnp 2e.18 on end # Power Management I/F Channel 4 (PMC4) 206 | device pnp 2e.19 on end # Power Management I/F Channel 5 (PMC5) 207 | end 208 | end 209 | end 210 | end 211 | -------------------------------------------------------------------------------- /devicetree.cb: -------------------------------------------------------------------------------- 1 | chip soc/intel/cannonlake 2 | 3 | # CPU (soc/intel/cannonlake/cpu.c) 4 | # Power limit 5 | register "power_limits_config" = "{ 6 | .tdp_pl1_override = 15, 7 | .tdp_pl2_override = 25, 8 | }" 9 | 10 | # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) 11 | register "SaGv" = "SaGv_FixedHigh" 12 | 13 | # FSP Silicon (soc/intel/cannonlake/fsp_params.c) 14 | 15 | # Thermal 16 | register "tcc_offset" = "12" 17 | 18 | # Serial IRQ Mode 19 | register "serirq_mode" = "SERIRQ_CONTINUOUS" 20 | 21 | # Actual device tree 22 | device domain 0 on 23 | device pci 14.0 on # USB xHCI 24 | chip drivers/usb/acpi 25 | device usb 0.0 on 26 | chip drivers/usb/acpi 27 | register "desc" = ""USB2 Type-A Front Left Upper"" 28 | register "type" = "UPC_TYPE_A" 29 | register "group" = "ACPI_PLD_GROUP(0, 0)" 30 | device usb 2.0 on end 31 | end 32 | chip drivers/usb/acpi 33 | register "desc" = ""USB2 Type-A Front Left Lower"" 34 | register "type" = "UPC_TYPE_A" 35 | register "group" = "ACPI_PLD_GROUP(0, 1)" 36 | device usb 2.1 on end 37 | end 38 | chip drivers/usb/acpi 39 | register "desc" = ""USB2 Type-A Rear Upper"" 40 | register "type" = "UPC_TYPE_A" 41 | register "group" = "ACPI_PLD_GROUP(1, 0)" 42 | device usb 2.2 on end 43 | end 44 | chip drivers/usb/acpi 45 | register "desc" = ""USB2 Type-A Front Right Lower"" 46 | register "type" = "UPC_TYPE_A" 47 | register "group" = "ACPI_PLD_GROUP(0, 2)" 48 | device usb 2.3 on end 49 | end 50 | chip drivers/usb/acpi 51 | register "desc" = ""USB2 Type-A Front Right Upper"" 52 | register "type" = "UPC_TYPE_A" 53 | register "group" = "ACPI_PLD_GROUP(0, 3)" 54 | device usb 2.4 on end 55 | end 56 | chip drivers/usb/acpi 57 | register "desc" = ""USB2 Type-C Port Rear"" 58 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" 59 | register "group" = "ACPI_PLD_GROUP(1, 2)" 60 | device usb 2.5 on end 61 | end 62 | chip drivers/usb/acpi 63 | device usb 2.6 off end 64 | end 65 | chip drivers/usb/acpi 66 | device usb 2.7 off end 67 | end 68 | chip drivers/usb/acpi 69 | device usb 2.8 off end 70 | end 71 | chip drivers/usb/acpi 72 | register "desc" = ""USB2 Type-A Rear Lower"" 73 | register "type" = "UPC_TYPE_A" 74 | register "group" = "ACPI_PLD_GROUP(1, 1)" 75 | device usb 2.9 on end 76 | end 77 | chip drivers/usb/acpi 78 | register "desc" = ""USB3 Type-A Front Left Upper"" 79 | register "type" = "UPC_TYPE_USB3_A" 80 | register "group" = "ACPI_PLD_GROUP(0, 0)" 81 | device usb 3.0 on end 82 | end 83 | chip drivers/usb/acpi 84 | register "desc" = ""USB3 Type-A Front Left Lower"" 85 | register "type" = "UPC_TYPE_USB3_A" 86 | register "group" = "ACPI_PLD_GROUP(0, 1)" 87 | device usb 3.1 on end 88 | end 89 | chip drivers/usb/acpi 90 | device usb 3.2 off end 91 | end 92 | chip drivers/usb/acpi 93 | register "desc" = ""USB3 Type-C Rear"" 94 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" 95 | register "group" = "ACPI_PLD_GROUP(1, 2)" 96 | device usb 3.3 on end 97 | end 98 | chip drivers/usb/acpi 99 | register "desc" = ""USB3 Type-A Rear Lower"" 100 | register "type" = "UPC_TYPE_USB3_A" 101 | register "group" = "ACPI_PLD_GROUP(1, 1)" 102 | device usb 3.4 on end 103 | end 104 | chip drivers/usb/acpi 105 | register "desc" = ""USB3 Type-A Rear Upper"" 106 | register "type" = "UPC_TYPE_USB3_A" 107 | register "group" = "ACPI_PLD_GROUP(1, 0)" 108 | device usb 3.5 on end 109 | end 110 | end 111 | end 112 | register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A front left upper 113 | register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A front left lower 114 | register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper 115 | register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A front right lower 116 | register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A front right upper 117 | register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear 118 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth 119 | register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower 120 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left upper 121 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left lower 122 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear 123 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower 124 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper 125 | end 126 | device pci 17.0 on # SATA 127 | register "SataPortsEnable[0]" = "1" # 2.5" 128 | register "SataPortsEnable[2]" = "1" # m.2 129 | register "satapwroptimize" = "1" 130 | end 131 | device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN) 132 | register "PcieRpSlotImplemented[7]" = "1" 133 | register "PcieRpEnable[7]" = "1" 134 | register "PcieRpLtrEnable[7]" = "1" 135 | # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC 136 | register "PcieClkSrcUsage[2]" = "0x80" 137 | smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" 138 | end 139 | device pci 1d.1 on # PCI Express Port 10 140 | device pci 00.0 on end # x1 (LAN) 141 | register "PcieRpEnable[9]" = "1" 142 | register "PcieClkSrcUsage[3]" = "9" 143 | register "PcieClkSrcClkReq[3]" = "3" 144 | end 145 | device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) 146 | register "PcieRpSlotImplemented[12]" = "1" 147 | register "PcieRpEnable[12]" = "1" 148 | register "PcieRpLtrEnable[12]" = "1" 149 | register "PcieClkSrcUsage[1]" = "12" 150 | register "PcieClkSrcClkReq[1]" = "1" 151 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" 152 | end 153 | device pci 1f.0 on # LPC Bridge 154 | chip superio/ite/it8528e 155 | device pnp 2e.1 on # UART1 156 | io 0x60 = 0x3F8 157 | irq 0x70 = 0x04 158 | end 159 | device pnp 2e.2 off end # UART2 160 | device pnp 2e.4 off end # System Wake-Up Control (SWUC) 161 | device pnp 2e.5 off end # KBC/Mouse 162 | device pnp 2e.6 off end # KBC/Keyboard 163 | device pnp 2e.a off end # Consumer IR 164 | device pnp 2e.f off end # Shared Memory/Flash Interface (SMFI) 165 | device pnp 2e.10 on # RTC-like Timer 166 | io 0x62 = 0x360 # BRAM1 I/O base address 167 | end 168 | device pnp 2e.11 off end # Power Management I/F Channel 1 (PMC1) 169 | device pnp 2e.12 off end # Power Management I/F Channel 2 (PMC2) 170 | device pnp 2e.13 off end # Serial Peripheral Interface (SSPI) 171 | device pnp 2e.14 off end # Platform Environment Control Interface (PECI) 172 | device pnp 2e.17 off end # Power Management I/F Channel 3 (PMC3) 173 | device pnp 2e.18 off end # Power Management I/F Channel 4 (PMC4) 174 | device pnp 2e.19 off end # Power Management I/F Channel 5 (PMC5) 175 | end 176 | end 177 | end 178 | end 179 | -------------------------------------------------------------------------------- /flash.sh: -------------------------------------------------------------------------------- 1 | sudo flashrom -p ch341a_spi -c W25Q128.V -w $1 2 | -------------------------------------------------------------------------------- /gpio.c: -------------------------------------------------------------------------------- 1 | 2 | #include "../../variant.h" 3 | 4 | /* Pad configuration was generated automatically using intelp2m utility */ 5 | static const struct pad_config gpio_table[] = { 6 | 7 | /* ------- GPIO Community 0 ------- */ 8 | 9 | /* ------- GPIO Group GPP_A ------- */ 10 | _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* RCIN# */ 11 | _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* LAD0 */ 12 | _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* LAD1 */ 13 | _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* LAD2 */ 14 | _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* LAD3 */ 15 | _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* LFRAME# */ 16 | _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SERIRQ */ 17 | _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 18 | _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CLKRUN# */ 19 | _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), /* CLKOUT_LPC0 */ 20 | _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), /* CLKOUT_LPC1 */ 21 | _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 22 | _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 23 | _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 24 | _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUS_STAT# */ 25 | _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 26 | _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(UP_20K)), /* GPIO */ 27 | _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* SD_VDD1_PWR_EN# */ 28 | _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ 29 | _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ 30 | _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ 31 | _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ 32 | _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ 33 | _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ 34 | 35 | /* ------- GPIO Group GPP_B ------- */ 36 | _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CORE_VID0 */ 37 | _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CORE_VID1 */ 38 | _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) | 1, 0), /* VRALERT# */ 39 | _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 40 | _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 41 | _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 42 | _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 43 | _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 44 | _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 45 | _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 46 | _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 47 | _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 48 | _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S0# */ 49 | _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PLTRST# */ 50 | _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 51 | _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(UP_20K)), /* GPIO */ 52 | _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GSPI0_CLK */ 53 | _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GSPI0_MISO */ 54 | _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GSPI0_MOSI */ 55 | _PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), /* GSPI1_CS0# */ 56 | _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), /* GSPI1_CLK */ 57 | _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), /* GSPI1_MISO */ 58 | _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), /* GSPI1_MOSI */ 59 | _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 60 | 61 | /* ------- GPIO Group GPP_G ------- */ 62 | _PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* SD_CMD */ 63 | _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* SD_DATA0 */ 64 | _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* SD_DATA1 */ 65 | _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* SD_DATA2 */ 66 | _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* SD_DATA3 */ 67 | _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* SD3_CD# */ 68 | _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SD3_CLK */ 69 | _PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), /* SD3_WP */ 70 | 71 | /* ------- GPIO Group SPI ------- */ 72 | 73 | /* ------- GPIO Community 1 ------- */ 74 | 75 | /* ------- GPIO Group GPP_D ------- */ 76 | _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 77 | _PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 78 | _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 79 | _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 80 | _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 81 | _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ISH_I2C0_SDA */ 82 | _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ISH_I2C0_SCL */ 83 | _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 84 | _PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 85 | _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 86 | _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 87 | _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(UP_20K)), /* GPIO */ 88 | _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* GPIO */ 89 | _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 90 | _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 91 | _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 92 | _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GPIO */ 93 | _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_CLK1 */ 94 | _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_DATA1 */ 95 | _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_CLK0 */ 96 | _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_DATA0 */ 97 | _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 98 | _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 99 | _PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 100 | 101 | /* ------- GPIO Group GPP_F ------- */ 102 | _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_BUF(TX_RX_DISABLE) | 1, 0), /* GPIO */ 103 | _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GPIO */ 104 | _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(UP_20K)), /* GPIO */ 105 | _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ 106 | _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* CNV_BRI_DT */ 107 | _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_BRI_RSP */ 108 | _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* CNV_RGI_DT */ 109 | _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_RGI_RSP */ 110 | _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 111 | _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 112 | _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 113 | _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 114 | _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 115 | _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 116 | _PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 117 | _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 118 | _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 119 | _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 120 | _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 121 | _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 122 | _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 123 | _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 124 | _PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 125 | _PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), /* A4WP_PRESENT */ 126 | 127 | /* ------- GPIO Group GPP_H ------- */ 128 | _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ 129 | _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* CNV_RF_RESET# */ 130 | _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* MODEM_CLKREQ */ 131 | _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ 132 | _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 133 | _PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 134 | _PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C3_SDA */ 135 | _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C3_SCL */ 136 | _PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C4_SDA */ 137 | _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C4_SCL */ 138 | _PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) | 1, 0), /* I2C5_SDA */ 139 | _PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) | 1, 0), /* I2C5_SCL */ 140 | _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 141 | _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 142 | _PAD_CFG_STRUCT(GPP_H14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 143 | _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 144 | _PAD_CFG_STRUCT(GPP_H16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 145 | _PAD_CFG_STRUCT(GPP_H17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GPIO */ 146 | _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CPU_C10_GATE# */ 147 | _PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 148 | _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 149 | _PAD_CFG_STRUCT(GPP_H21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GPIO */ 150 | _PAD_CFG_STRUCT(GPP_H22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 151 | _PAD_CFG_STRUCT(GPP_H23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GPIO */ 152 | 153 | /* ------- GPIO Group VGPIO ------- */ 154 | 155 | /* ------- GPIO Community 2 ------- */ 156 | 157 | /* ------- GPIO Group GPD ------- */ 158 | _PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* BATLOW# */ 159 | _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* ACPRESENT */ 160 | _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* LAN_WAKE# */ 161 | _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* PRWBTN# */ 162 | _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_S3# */ 163 | _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_S4# */ 164 | _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ 165 | _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GPIO */ 166 | _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ 167 | _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_WLAN# */ 168 | _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_S5# */ 169 | _PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* LANPHYPC */ 170 | 171 | /* ------- GPIO Community 3 ------- */ 172 | 173 | /* ------- GPIO Group AZA ------- */ 174 | 175 | /* ------- GPIO Group CPU ------- */ 176 | 177 | /* ------- GPIO Community 4 ------- */ 178 | 179 | /* ------- GPIO Group GPP_C ------- */ 180 | _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBCLK */ 181 | _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBDATA */ 182 | _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 183 | _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0CLK */ 184 | _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0DATA */ 185 | _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 186 | _PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 187 | _PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 188 | _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 189 | _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 190 | _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GPIO */ 191 | _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), /* GPIO */ 192 | _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) | 1, 0), /* UART1_RXD */ 193 | _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* UART1_TXD */ 194 | _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* UART1_RTS# */ 195 | _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) | 1, 0), /* UART1_CTS# */ 196 | _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), /* I2C0_SDA */ 197 | _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), /* I2C0_SCL */ 198 | _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C1_SDA */ 199 | _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C1_SCL */ 200 | _PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 201 | _PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 202 | _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 203 | _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), /* GPIO */ 204 | 205 | /* ------- GPIO Group GPP_E ------- */ 206 | _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 207 | _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 208 | _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* SATAXPCIE2 */ 209 | _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ 210 | _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 211 | _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 212 | _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ 213 | _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ 214 | _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATALED# */ 215 | _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* RESERVED */ 216 | _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* RESERVED */ 217 | _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC2# */ 218 | _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC3# */ 219 | _PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD0 */ 220 | _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPC_HPD1 */ 221 | _PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ 222 | _PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* GPIO */ 223 | _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* EDP_HPD */ 224 | _PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DPPB_CTRLCLK */ 225 | _PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* DPPB_CTRLDATA */ 226 | _PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DPPC_CTRLCLK */ 227 | _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* DPPC_CTRLDATA */ 228 | _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) | 1, 0), /* DPPD_CTRLCLK */ 229 | _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) | 1, 0), /* DPPD_CTRLDATA */ 230 | 231 | /* ------- GPIO Group JTAG ------- */ 232 | 233 | /* ------- GPIO Group HVMOS ------- */ 234 | }; 235 | 236 | 237 | const struct pad_config *variant_gpio_table(size_t *num) 238 | { 239 | *num = ARRAY_SIZE(gpio_table); 240 | return gpio_table; 241 | } 242 | 243 | -------------------------------------------------------------------------------- /nitropad-ns50-defconfig: -------------------------------------------------------------------------------- 1 | CONFIG_LOCALVERSION="v1.7.2" 2 | CONFIG_USE_OPTION_TABLE=y 3 | CONFIG_VENDOR_NOVACUSTOM=y 4 | CONFIG_MAINBOARD_VERSION="v2.1" 5 | 6 | #CONFIG_MAINBOARD_VENDOR="Nitrokey" 7 | CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="NitroPad-NS50/NS70" 8 | CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Nitrokey" 9 | 10 | CONFIG_IFD_BIN_PATH="flashdescriptor.bin" 11 | CONFIG_ME_BIN_PATH="me.bin" 12 | CONFIG_HAVE_IFD_BIN=y 13 | CONFIG_HAVE_ME_BIN=y 14 | 15 | # CONFIG_CONSOLE_SERIAL is not set 16 | # CONFIG_POST_IO is not set 17 | #CONFIG_VBOOT=y 18 | CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 19 | CONFIG_PCIEXP_HOTPLUG_BUSES=42 20 | CONFIG_PCIEXP_HOTPLUG_MEM=0xc200000 21 | CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x1c000000 22 | #CONFIG_BOARD_NOVACUSTOM_NS5X_ADLP=y 23 | CONFIG_UART_PCI_ADDR=0x0 24 | CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y 25 | CONFIG_PCIEXP_HOTPLUG_IO=0x2000 26 | CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 27 | CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 28 | CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 29 | CONFIG_SMMSTORE_SIZE=0x40000 30 | # CONFIG_TPM_PPI is not set 31 | CONFIG_CBFS_MCACHE_RW_PERCENTAGE=10 32 | CONFIG_VBOOT_KEYBLOCK_VERSION=1 33 | CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS=0x0 34 | CONFIG_TPM_MEASURED_BOOT=y 35 | 36 | 37 | CONFIG_DRIVERS_EFI_VARIABLE_STORE=y 38 | CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y 39 | CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y 40 | CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y 41 | CONFIG_BOOTMEDIA_SMM_BWP=y 42 | # CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set 43 | # CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set 44 | 45 | CONFIG_PAYLOAD_EDK2=y 46 | 47 | CONFIG_EDK2_BOOTSPLASH_FILE="bootsplash.bmp" 48 | CONFIG_EDK2_BOOT_TIMEOUT=2 49 | 50 | CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" 51 | CONFIG_EDK2_TAG_OR_REV="b7274c98697e972e772236caf830c0780ec498bd" 52 | CONFIG_EDK2_USE_EDK2_PLATFORMS=y 53 | CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" 54 | CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" 55 | CONFIG_EDK2_FOLLOW_BGRT_SPEC=y 56 | CONFIG_EDK2_SKIP_PS2_DETECT=y 57 | CONFIG_EDK2_ENABLE_IPXE=y 58 | CONFIG_EDK2_SECURE_BOOT=y 59 | # CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set 60 | CONFIG_EDK2_SETUP_PASSWORD=y 61 | CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y 62 | CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y 63 | CONFIG_EDK2_SHOW_CAMERA_OPTION=y 64 | CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y 65 | CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y 66 | CONFIG_EDK2_DASHARO_USB_CONFIG=y 67 | CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y 68 | CONFIG_EDK2_DASHARO_POWER_CONFIG=y 69 | CONFIG_EDK2_SLEEP_TYPE_OPTION=y 70 | CONFIG_EDK2_FAN_CURVE_OPTION=y 71 | CONFIG_EDK2_BATTERY_CONFIG_OPTION=y 72 | CONFIG_EDK2_BOOT_MENU_KEY=0x0011 73 | CONFIG_EDK2_SETUP_MENU_KEY=0x000C 74 | CONFIG_EDK2_ENABLE_BATTERY_CHECK=y 75 | CONFIG_EDK2_PRINT_SOL_STRINGS=y 76 | CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdS3SupportExperimental=TRUE" 77 | CONFIG_EDK2_CBMEM_LOGGING=y 78 | CONFIG_EDK2_SYSTEM76_EC_LOGGING=y 79 | CONFIG_EDK2_SERIAL_SUPPORT=y 80 | CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y 81 | CONFIG_PXE_ADD_SCRIPT=y 82 | CONFIG_PXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" 83 | CONFIG_PXE_CUSTOM_BUILD_ID="0123456789" 84 | 85 | 86 | -------------------------------------------------------------------------------- /nitropad-ns50.mk: -------------------------------------------------------------------------------- 1 | 2 | COREBOOT_REF = novacustom_ns5x_adl_v1.7.2 3 | 4 | coreboot/build/coreboot.rom: coreboot/configs/defconfig coreboot/util/crossgcc/xgcc blobs-update 5 | 6 | cp blobs/nitropad-ns50/*.bin coreboot/ 7 | cp blobs/common/bootsplash-1080.bmp coreboot/bootsplash.bmp 8 | cd coreboot && git checkout $(COREBOOT_REF) 9 | 10 | make -C coreboot CPUS=$(CPU_COUNT) 11 | 12 | -------------------------------------------------------------------------------- /nitropad-nv41-defconfig: -------------------------------------------------------------------------------- 1 | CONFIG_LOCALVERSION="v1.7.2" 2 | #CONFIG_CCACHE=y 3 | CONFIG_USE_OPTION_TABLE=y 4 | CONFIG_VENDOR_NOVACUSTOM=y 5 | CONFIG_MAINBOARD_VERSION="v2.1" 6 | 7 | CONFIG_MAINBOARD_VENDOR="Nitrokey" 8 | CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="NitroPad-NV41" 9 | CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Nitrokey" 10 | 11 | CONFIG_IFD_BIN_PATH="flashdescriptor.bin" 12 | CONFIG_ME_BIN_PATH="me.bin" 13 | CONFIG_HAVE_IFD_BIN=y 14 | CONFIG_HAVE_ME_BIN=y 15 | 16 | CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 17 | CONFIG_PCIEXP_HOTPLUG_BUSES=42 18 | CONFIG_PCIEXP_HOTPLUG_MEM=0xc200000 19 | CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x1c000000 20 | CONFIG_BOARD_NOVACUSTOM_NV4X_ADLP=y 21 | CONFIG_UART_PCI_ADDR=0x0 22 | CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y 23 | CONFIG_PCIEXP_HOTPLUG_IO=0x2000 24 | CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 25 | CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 26 | CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 27 | CONFIG_SMMSTORE_SIZE=0x40000 28 | CONFIG_CBFS_MCACHE_RW_PERCENTAGE=10 29 | CONFIG_VBOOT_KEYBLOCK_VERSION=1 30 | CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS=0x0 31 | CONFIG_TPM_MEASURED_BOOT=y 32 | 33 | CONFIG_DRIVERS_EFI_VARIABLE_STORE=y 34 | CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y 35 | CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y 36 | CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y 37 | CONFIG_BOOTMEDIA_SMM_BWP=y 38 | # CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set 39 | # CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set 40 | 41 | CONFIG_EDK2_BOOT_TIMEOUT=2 42 | CONFIG_EDK2_BOOTSPLASH_FILE="bootsplash.bmp" 43 | 44 | CONFIG_PAYLOAD_EDK2=y 45 | CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" 46 | CONFIG_EDK2_TAG_OR_REV="b7274c98697e972e772236caf830c0780ec498bd" 47 | CONFIG_EDK2_USE_EDK2_PLATFORMS=y 48 | CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" 49 | CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" 50 | CONFIG_EDK2_FOLLOW_BGRT_SPEC=y 51 | CONFIG_EDK2_SKIP_PS2_DETECT=y 52 | CONFIG_EDK2_ENABLE_IPXE=y 53 | CONFIG_EDK2_SECURE_BOOT=y 54 | # CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set 55 | CONFIG_EDK2_SETUP_PASSWORD=y 56 | CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y 57 | CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y 58 | CONFIG_EDK2_SHOW_CAMERA_OPTION=y 59 | CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y 60 | CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y 61 | CONFIG_EDK2_DASHARO_USB_CONFIG=y 62 | CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y 63 | CONFIG_EDK2_DASHARO_POWER_CONFIG=y 64 | CONFIG_EDK2_SLEEP_TYPE_OPTION=y 65 | CONFIG_EDK2_FAN_CURVE_OPTION=y 66 | CONFIG_EDK2_BATTERY_CONFIG_OPTION=y 67 | CONFIG_EDK2_BOOT_MENU_KEY=0x0011 68 | CONFIG_EDK2_SETUP_MENU_KEY=0x000C 69 | CONFIG_EDK2_ENABLE_BATTERY_CHECK=y 70 | CONFIG_EDK2_PRINT_SOL_STRINGS=y 71 | CONFIG_EDK2_CBMEM_LOGGING=y 72 | CONFIG_EDK2_SYSTEM76_EC_LOGGING=y 73 | CONFIG_EDK2_SERIAL_SUPPORT=y 74 | CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y 75 | CONFIG_PXE_ADD_SCRIPT=y 76 | CONFIG_PXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" 77 | CONFIG_PXE_CUSTOM_BUILD_ID="0123456789" 78 | 79 | 80 | -------------------------------------------------------------------------------- /nitropad-nv41.mk: -------------------------------------------------------------------------------- 1 | 2 | COREBOOT_REF = novacustom_nv4x_adl_v1.7.2 3 | 4 | coreboot/build/coreboot.rom: coreboot/configs/defconfig coreboot/util/crossgcc/xgcc blobs-update 5 | 6 | cp blobs/nitropad-nv41/*.bin coreboot/ 7 | cp blobs/common/bootsplash-1080.bmp coreboot/bootsplash.bmp 8 | cd coreboot && git checkout $(COREBOOT_REF) 9 | 10 | make -C coreboot CPUS=$(CPU_COUNT) 11 | 12 | -------------------------------------------------------------------------------- /nitropc-defconfig: -------------------------------------------------------------------------------- 1 | CONFIG_VENDOR_PURISM=y 2 | CONFIG_MAINBOARD_VENDOR="Nitrokey" 3 | CONFIG_INTEL_GMA_VBT_FILE="vbt.bin" 4 | CONFIG_IFD_BIN_PATH="flashdescriptor.bin" 5 | CONFIG_ME_BIN_PATH="me.bin" 6 | CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="NitroPC" 7 | CONFIG_HAVE_IFD_BIN=y 8 | CONFIG_BOARD_PURISM_LIBREM_MINI_V2=y 9 | CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y 10 | CONFIG_CPU_UCODE_BINARIES="cpu_microcode_blob.bin" 11 | CONFIG_HAVE_ME_BIN=y 12 | 13 | CONFIG_PAYLOAD_EDK2=y 14 | 15 | CONFIG_RUN_FSP_GOP=y 16 | CONFIG_SMMSTORE=y 17 | 18 | CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y 19 | CONFIG_EDK2_CBMEM_LOGGING=y 20 | CONFIG_EDK2_FOLLOW_BGRT_SPEC=y 21 | 22 | 23 | CONFIG_EDK2_BOOTSPLASH_FILE="bootsplash.jpg" 24 | 25 | #CONFIG_BOOTSPLASH_IMAGE=y 26 | #CONFIG_BOOTSPLASH_FILE="bootsplash.jpg" 27 | #CONFIG_BOOTSPLASH_CONVERT=y 28 | #CONFIG_BOOTSPLASH_CONVERT_QUALITY="90" 29 | #CONFIG_BOOTSPLASH_CONVERT_RESIZE=y 30 | #CONFIG_BOOTSPLASH_CONVERT_RESOLUTION="1920x1080" 31 | 32 | 33 | #CONFIG_TIANOCORE_BOOTSPLASH_IMAGE=y 34 | -------------------------------------------------------------------------------- /nitropc-v2-Kconfig: -------------------------------------------------------------------------------- 1 | config BOARD_PURISM_BASEBOARD_LIBREM_CNL 2 | def_bool n 3 | select BOARD_ROMSIZE_KB_16384 4 | select DRIVERS_GENERIC_CBFS_SERIAL 5 | select DRIVERS_USB_ACPI 6 | select HAVE_ACPI_RESUME 7 | select HAVE_ACPI_TABLES 8 | select INTEL_GMA_HAVE_VBT 9 | select MAINBOARD_HAS_LIBGFXINIT 10 | select NO_UART_ON_SUPERIO 11 | select SOC_INTEL_COMMON_BLOCK_HDA_VERB 12 | select SPD_CACHE_IN_FMAP 13 | select SPD_READ_BY_WORD 14 | select USE_LEGACY_8254_TIMER 15 | 16 | config BOARD_PURISM_LIBREM_MINI 17 | select BOARD_PURISM_BASEBOARD_LIBREM_CNL 18 | select HAVE_CMOS_DEFAULT 19 | select HAVE_OPTION_TABLE 20 | select SOC_INTEL_WHISKEYLAKE 21 | select SUPERIO_ITE_IT8528E 22 | 23 | config BOARD_PURISM_LIBREM_MINI_V2 24 | select BOARD_PURISM_BASEBOARD_LIBREM_CNL 25 | select HAVE_CMOS_DEFAULT 26 | select HAVE_OPTION_TABLE 27 | select SOC_INTEL_COMETLAKE_1 28 | select SUPERIO_ITE_IT8528E 29 | select EC_ACPI 30 | 31 | config BOARD_PURISM_LIBREM_14 32 | select BOARD_PURISM_BASEBOARD_LIBREM_CNL 33 | select DRIVERS_I2C_HID 34 | select EC_LIBREM_EC 35 | select MEMORY_MAPPED_TPM 36 | select MAINBOARD_HAS_TPM1 37 | select SOC_INTEL_COMETLAKE_1_2 38 | select SYSTEM_TYPE_LAPTOP 39 | 40 | if BOARD_PURISM_BASEBOARD_LIBREM_CNL 41 | 42 | config MAINBOARD_DIR 43 | default "purism/librem_cnl" 44 | 45 | config MAINBOARD_FAMILY 46 | string 47 | default "Librem Mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 48 | default "Librem 14" if BOARD_PURISM_LIBREM_14 49 | 50 | config MAINBOARD_PART_NUMBER 51 | default "Librem Mini" if BOARD_PURISM_LIBREM_MINI 52 | default "Librem Mini v2" if BOARD_PURISM_LIBREM_MINI_V2 53 | default "Librem 14" if BOARD_PURISM_LIBREM_14 54 | 55 | config VARIANT_DIR 56 | default "librem_mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 57 | default "librem_14" if BOARD_PURISM_LIBREM_14 58 | 59 | config OVERRIDE_DEVICETREE 60 | default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" 61 | 62 | config CBFS_SIZE 63 | default 0x800000 if BOARD_PURISM_LIBREM_MINI 64 | default 0xA00000 if BOARD_PURISM_LIBREM_MINI_V2 65 | default 0x900000 if BOARD_PURISM_LIBREM_14 66 | 67 | config DIMM_MAX 68 | default 2 69 | 70 | config DIMM_SPD_SIZE 71 | default 512 72 | 73 | config VGA_BIOS_ID 74 | string 75 | default "8086,3ea0" if BOARD_PURISM_LIBREM_MINI 76 | default "8086,9b41" if BOARD_PURISM_LIBREM_MINI_V2 || BOARD_PURISM_LIBREM_14 77 | 78 | config PXE_ROM_ID 79 | string 80 | default "10ec,8168" 81 | 82 | # This platform has limited means to display POST codes 83 | config NO_POST 84 | default y 85 | 86 | endif 87 | 88 | if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 89 | 90 | config PC_CMOS_BASE_PORT_BANK1 91 | default 0x360 92 | 93 | config CMOS_LAYOUT_FILE 94 | default "src/mainboard/\$(MAINBOARDDIR)/variants/librem_mini/cmos.layout" 95 | 96 | config CMOS_DEFAULT_FILE 97 | default "src/mainboard/\$(MAINBOARDDIR)/variants/librem_mini/cmos.default" 98 | 99 | endif 100 | 101 | config ENABLE_EC_UART1 102 | bool "Enable EC UART1" 103 | depends on BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 104 | default n 105 | select DRIVERS_UART_8250IO 106 | help 107 | Enable UART1 on the EC. 108 | 109 | This UART can be used for boot logging by coreboot, SeaBIOS, or 110 | Linux. It also works as a general-purpose UART. 111 | 112 | Soldering is required to access these signals. Locate the pads for 113 | U81 on the bottom of the board near the front edge; the IC is not 114 | populated. TX is pin 14, RX is pin 19. The signals are 3.3V (do NOT 115 | connect directly to an RS-232 serial port). 116 | -------------------------------------------------------------------------------- /nitropc-v2-defconfig: -------------------------------------------------------------------------------- 1 | CONFIG_VENDOR_PURISM=y 2 | CONFIG_MAINBOARD_VENDOR="Nitrokey" 3 | CONFIG_INTEL_GMA_VBT_FILE="vbt.bin" 4 | CONFIG_IFD_BIN_PATH="flashdescriptor.bin" 5 | CONFIG_ME_BIN_PATH="me.bin" 6 | CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="NitroPC" 7 | CONFIG_HAVE_IFD_BIN=y 8 | CONFIG_BOARD_PURISM_LIBREM_MINI_V2=y 9 | CONFIG_HAVE_ME_BIN=y 10 | 11 | # Set to 1MB to fit EDK2 and coreboot logs alltogether 12 | CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 13 | 14 | CONFIG_PAYLOAD_EDK2=y 15 | 16 | CONFIG_RUN_FSP_GOP=y 17 | CONFIG_SMMSTORE=y 18 | 19 | CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y 20 | CONFIG_EDK2_CBMEM_LOGGING=y 21 | CONFIG_EDK2_FOLLOW_BGRT_SPEC=y 22 | 23 | CONFIG_EDK2_BOOTSPLASH_FILE="bootsplash.jpg" 24 | 25 | #CONFIG_BOOTSPLASH_IMAGE=y 26 | #CONFIG_BOOTSPLASH_CONVERT=y 27 | #CONFIG_BOOTSPLASH_CONVERT_QUALITY=90 28 | #CONFIG_BOOTSPLASH_CONVERT_RESIZE=y 29 | #CONFIG_BOOTSPLASH_CONVERT_RESOLUTION="1920x1080" 30 | 31 | #CONFIG_SUPERIO_ITE_ENV_CTRL=y 32 | #CONFIG_ITE_ENV_CTRL_NO_ONOFF=y 33 | 34 | CONFIG_USE_OPTION_TABLE=y 35 | CONFIG_STATIC_OPTION_TABLE=y 36 | 37 | -------------------------------------------------------------------------------- /nitropc-v2-mainboard.c: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | 3 | #include 4 | #include 5 | 6 | static void mainboard_final(void *chip_info) 7 | { 8 | /* Start fan control */ 9 | ec_set_ports(0x6c, 0x68); 10 | send_ec_command(0x06); 11 | send_ec_data(0x00); 12 | } 13 | 14 | struct chip_operations mainboard_ops = { 15 | .final = mainboard_final, 16 | }; 17 | -------------------------------------------------------------------------------- /nitropc-v2.mk: -------------------------------------------------------------------------------- 1 | 2 | COREBOOT_REF = 4.22 3 | 4 | coreboot/build/coreboot.rom: coreboot/bootsplash.jpg coreboot/configs/defconfig coreboot/util/crossgcc/xgcc blobs-update 5 | rm coreboot/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb 6 | cp devicetree-v2.cb coreboot/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb 7 | cp gpio.c coreboot/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c 8 | cp nitropc-v2-mainboard.c coreboot/src/mainboard/purism/librem_cnl/mainboard.c 9 | cp nitropc-v2-Kconfig coreboot/src/mainboard/purism/librem_cnl/Kconfig 10 | cp cmos.default coreboot/src/mainboard/purism/librem_cnl/variants/librem_mini/ 11 | cp cmos.layout coreboot/src/mainboard/purism/librem_cnl/variants/librem_mini/ 12 | cp blobs/nitropc/* coreboot/ 13 | cp -r blobs/common coreboot/common-blobs 14 | 15 | # Run defconfig again after overriding mainbaord's Kconfig file 16 | make -C coreboot defconfig 17 | make -C coreboot CPUS=$(CPU_COUNT) 18 | 19 | -------------------------------------------------------------------------------- /nitropc.mk: -------------------------------------------------------------------------------- 1 | 2 | COREBOOT_REF = 4.22 3 | 4 | coreboot/build/coreboot.rom: coreboot/bootsplash.jpg coreboot/configs/defconfig coreboot/util/crossgcc/xgcc blobs-update 5 | rm coreboot/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb 6 | cp devicetree.cb coreboot/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb 7 | cp blobs/nitropc/* coreboot/ 8 | 9 | make -C coreboot CPUS=$(CPU_COUNT) 10 | 11 | -------------------------------------------------------------------------------- /nitrowall-defconfig: -------------------------------------------------------------------------------- 1 | CONFIG_VENDOR_PROTECTLI=y 2 | CONFIG_MAINBOARD_VENDOR="Nitrokey" 3 | CONFIG_VGA_BIOS=y 4 | CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="NitroWall-NW4J3" 5 | CONFIG_BOARD_PROTECTLI_FW4B=y 6 | CONFIG_VGA_ROM_RUN=y 7 | CONFIG_ON_DEVICE_ROM_LOAD=y 8 | CONFIG_SMMSTORE=y 9 | 10 | CONFIG_USE_ME_CLEANER=y 11 | 12 | CONFIG_HAVE_IFD_BIN=y 13 | CONFIG_IFD_BIN_PATH="fd.bin" 14 | 15 | CONFIG_HAVE_ME_BIN=y 16 | CONFIG_ME_BIN_PATH="me.bin" 17 | -------------------------------------------------------------------------------- /nitrowall-pro-defconfig: -------------------------------------------------------------------------------- 1 | CONFIG_LOCALVERSION="4.12" 2 | CONFIG_BOOTSPLASH_IMAGE=y 3 | CONFIG_BOOTSPLASH_FILE="bootsplash.jpg" 4 | CONFIG_VENDOR_PROTECTLI=y 5 | CONFIG_VGA_BIOS=y 6 | CONFIG_VGA_BIOS_FILE="vgabios.bin" 7 | CONFIG_VGA_BIOS_SECOND=y 8 | CONFIG_VGA_BIOS_SECOND_FILE="vgabios2.bin" 9 | CONFIG_HAVE_IFD_BIN=y 10 | CONFIG_BOARD_PROTECTLI_FW6=y 11 | CONFIG_HAVE_ME_BIN=y 12 | CONFIG_MAINBOARD_VENDOR="Nitrokey" 13 | CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="NitroWall-NW678" 14 | CONFIG_USE_ME_CLEANER=y 15 | CONFIG_IFD_BIN_PATH="fd.bin" 16 | CONFIG_ME_BIN_PATH="me.bin" 17 | 18 | 19 | CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y 20 | CONFIG_SEABIOS_DEBUG_LEVEL=0 21 | -------------------------------------------------------------------------------- /nitrowall-pro.mk: -------------------------------------------------------------------------------- 1 | 2 | COREBOOT_REF = 0895a061d5fd356c0a951954d4714265bbbc04b8 3 | #dasharo 4 | #9f221f6566e7bd3d1170903a4211a0ecc39c564c 5 | # ref: tags/protectli_vault_kbl_v1.0.14 6 | 7 | coreboot/build/coreboot.rom: coreboot/bootsplash.jpg coreboot/configs/defconfig coreboot/util/crossgcc/xgcc blobs-update 8 | 9 | cp blobs/nitrowall-pro/*.bin coreboot/ 10 | cd coreboot && \ 11 | git checkout 71899c9fc9697435a1309db40cfd05f0180065eb -- payloads/external/SeaBIOS/Makefile 12 | # ref: tags/4.17 13 | 14 | make -C coreboot CPUS=$(CPU_COUNT) 15 | 16 | -------------------------------------------------------------------------------- /nitrowall.mk: -------------------------------------------------------------------------------- 1 | 2 | COREBOOT_REF = 4.22 3 | # 6c05f0de191afb35781896da00473dc24e048e48 4 | # 0895a061d5fd356c0a951954d4714265bbbc04b8 5 | # 7f69d690d22efb4d0c9e79acd94bf138a3a81b47 6 | # ref: tags/4.16 7 | 8 | coreboot/build/coreboot.rom: coreboot/bootsplash.bmp coreboot/configs/defconfig coreboot/util/crossgcc/xgcc blobs-update 9 | cp blobs/nitrowall/vgabios.bin coreboot/ 10 | cp blobs/nitrowall/vgabios.bin coreboot/vgabios_c0.bin 11 | cp blobs/nitrowall/fd.bin coreboot/ 12 | cp blobs/nitrowall/me.bin coreboot/ 13 | 14 | make -C coreboot CPUS=$(CPU_COUNT) 15 | 16 | --------------------------------------------------------------------------------