├── .gitignore ├── LICENSE.adoc ├── README.adoc ├── drv_gpio ├── drv_gpio_def_check.h ├── drv_gpio.h ├── sdk_config.h └── drv_gpio.c ├── drv_gpio_example.c └── pca10040 └── arm5_no_packs └── drv_gpio_example.uvprojx /.gitignore: -------------------------------------------------------------------------------- 1 | *.axf 2 | *.swp 3 | *.htm 4 | *.Inp 5 | *.map 6 | *.tra 7 | *.dep 8 | *._2i 9 | *.l2p 10 | *.__i 11 | *.fed 12 | *.crf 13 | *.d 14 | *.o 15 | *.lst 16 | *.lnp 17 | *.bak 18 | 19 | *.ini 20 | *.iex 21 | *.sct 22 | *.uvgui.* 23 | *.uvguix.* 24 | *.tmp 25 | **/arm/JLinkLog.txt 26 | **/_viminfo 27 | **/_vimtags 28 | _build/ 29 | RTE/ -------------------------------------------------------------------------------- /LICENSE.adoc: -------------------------------------------------------------------------------- 1 | Copyright (c) Nordic Semiconductor ASA 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without modification, 5 | are permitted provided that the following conditions are met: 6 | 7 | 1. Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | 10 | 2. Redistributions in binary form must reproduce the above copyright notice, this 11 | list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | 14 | 3. Neither the name of Nordic Semiconductor ASA nor the names of other 15 | contributors to this software may be used to endorse or promote products 16 | derived from this software without specific prior written permission. 17 | 18 | 4. This software must only be used in a processor manufactured by Nordic 19 | Semiconductor ASA, or in a processor manufactured by a third party that 20 | is used in combination with a processor manufactured by Nordic Semiconductor. 21 | 22 | 23 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 27 | ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 | ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -------------------------------------------------------------------------------- /README.adoc: -------------------------------------------------------------------------------- 1 | nrf52-drv-gpio-example 2 | ====================== 3 | 4 | Description 5 | ----------- 6 | This is a gpio driver example supporting the following features: 7 | 8 | - Configuring a pin or group of pins as input pin(s). 9 | - Configuring a pin or group of pins as output pin(s). 10 | - Getting the logical level an input pin or group of input pins. 11 | - Setting the logical level an output pin or group of output pins. 12 | - Sensing pin(s) using interrupts and the low-power PORT-event. 13 | - Sensing pin(s) using interrupts and the high-accuracy IN-event. 14 | - Toggling of pin(s) without involving the CPU. 15 | - Disconnecting a pin or group of pins. 16 | 17 | Follow these steps to run the example: 18 | 19 | . Extract the 12.3.0 version of the SDK. 20 | . Enter the nRF5_SDK_12.3.0_d7731ad\examples\peripheral directory. 21 | . Clone the repo: git clone https://github.com/NordicPlayground/nrf52-drv-gpio-example.git 22 | . Enter the nRF5_SDK_12.3.0_d7731ad\examples\peripheral\nrf52-drv-gpio-example\pca10040\arm5_no_packs directory 23 | . Open the drv_gpio_example.uvprojx Keil project file. 24 | . Build the project. 25 | . Select and configure the debugger. 26 | . Press the LOAD button. 27 | . All four LEDs should now blink 4 times. 28 | . Press one button at a time to observe the behavior of the example. 29 | . Press all four buttons simultaneously to proceed to the next example. 30 | . Repeat from step 9 until the board does not respond to button presses anymore, which means the program has run to the end. 31 | 32 | NOTE: Power-cycle the board to run all examples again. 33 | 34 | Requirements 35 | ------------ 36 | - nRF5 SDK version 12.3.0 37 | - nRF52DK 38 | 39 | The project may need modifications to work with later versions or other boards. 40 | 41 | To compile it, clone the repository in the /nRF5_SDK_12.3.0/examples/peripheral directory. 42 | 43 | About this project 44 | ------------------ 45 | This application is one of several applications that has been built by the support team at Nordic Semiconductor, as a demo of some particular feature or use case. It has not necessarily been thoroughly tested, so there might be unknown issues. It is hence provided as-is, without any warranty. 46 | 47 | However, in the hope that it still may be useful also for others than the ones we initially wrote it for, we've chosen to distribute it here on GitHub. 48 | 49 | The application is built to be used with the official nRF5 SDK that can be downloaded from developer.nordicsemi.com 50 | -------------------------------------------------------------------------------- /drv_gpio/drv_gpio_def_check.h: -------------------------------------------------------------------------------- 1 | /* Copyright (c) Nordic Semiconductor ASA 2 | * All rights reserved. 3 | * 4 | * Redistribution and use in source and binary forms, with or without modification, 5 | * are permitted provided that the following conditions are met: 6 | * 7 | * 1. Redistributions of source code must retain the above copyright notice, this 8 | * list of conditions and the following disclaimer. 9 | * 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, this 11 | * list of conditions and the following disclaimer in the documentation and/or 12 | * other materials provided with the distribution. 13 | * 14 | * 3. Neither the name of Nordic Semiconductor ASA nor the names of other 15 | * contributors to this software may be used to endorse or promote products 16 | * derived from this software without specific prior written permission. 17 | * 18 | * 4. This software must only be used in a processor manufactured by Nordic 19 | * Semiconductor ASA, or in a processor manufactured by a third party that 20 | * is used in combination with a processor manufactured by Nordic Semiconductor. 21 | * 22 | * 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 27 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 | */ 34 | 35 | 36 | #ifdef DRV_GPIO_H__ 37 | 38 | 39 | #if DRV_GPIO_SENSE_NONE != GPIOTE_CONFIG_POLARITY_None 40 | #error "ERROR: DRV_GPIO_SENSE_NONE != GPIOTE_CONFIG_POLARITY_None." 41 | #endif 42 | #if DRV_GPIO_SENSE_LOTOHI != GPIOTE_CONFIG_POLARITY_LoToHi 43 | #error "ERROR: DRV_GPIO_SENSE_LOTOHI != GPIOTE_CONFIG_POLARITY_LoToHi." 44 | #endif 45 | #if DRV_GPIO_SENSE_HITOLO != GPIOTE_CONFIG_POLARITY_HiToLo 46 | #error "ERROR: DRV_GPIO_SENSE_HITOLO != GPIOTE_CONFIG_POLARITY_HiToLo." 47 | #endif 48 | #if DRV_GPIO_SENSE_ANY != GPIOTE_CONFIG_POLARITY_Toggle 49 | #error "ERROR: DRV_GPIO_SENSE_ANY != GPIOTE_CONFIG_POLARITY_Toggle." 50 | #endif 51 | 52 | 53 | #if DRV_GPIO_PULL_NONE != GPIO_PIN_CNF_PULL_Disabled 54 | #error "ERROR: DRV_GPIO_PULL_NONE != GPIO_PIN_CNF_PULL_Disabled." 55 | #endif 56 | #if DRV_GPIO_PULL_UP != GPIO_PIN_CNF_PULL_Pullup 57 | #error "ERROR: DRV_GPIO_PULL_UP != GPIO_PIN_CNF_PULL_Pullup." 58 | #endif 59 | #if DRV_GPIO_PULL_DOWN != GPIO_PIN_CNF_PULL_Pulldown 60 | #error "ERROR: DRV_GPIO_PULL_DOWN != GPIO_PIN_CNF_PULL_Pulldown." 61 | #endif 62 | 63 | 64 | #if DRV_GPIO_LEVEL_LOW != GPIOTE_CONFIG_OUTINIT_Low 65 | #error "ERROR: DRV_GPIO_LEVEL_LOW != GPIOTE_CONFIG_OUTINIT_Low." 66 | #endif 67 | #if DRV_GPIO_LEVEL_HIGH != GPIOTE_CONFIG_OUTINIT_High 68 | #error "ERROR: DRV_GPIO_LEVEL_HIGH != GPIOTE_CONFIG_OUTINIT_High." 69 | #endif 70 | 71 | 72 | #if DRV_GPIO_DRIVE_S0S1 != GPIO_PIN_CNF_DRIVE_S0S1 73 | #error "ERROR: DRV_GPIO_DRIVE_S0S1 != GPIO_PIN_CNF_DRIVE_S0S1." 74 | #endif 75 | #if DRV_GPIO_DRIVE_H0S1 != GPIO_PIN_CNF_DRIVE_H0S1 76 | #error "ERROR: DRV_GPIO_DRIVE_H0S1 != GPIO_PIN_CNF_DRIVE_H0S1." 77 | #endif 78 | #if DRV_GPIO_DRIVE_S0H1 != GPIO_PIN_CNF_DRIVE_S0H1 79 | #error "ERROR: DRV_GPIO_DRIVE_S0H1 != GPIO_PIN_CNF_DRIVE_S0H1." 80 | #endif 81 | #if DRV_GPIO_DRIVE_H0H1 != GPIO_PIN_CNF_DRIVE_H0H1 82 | #error "ERROR: DRV_GPIO_DRIVE_H0H1 != GPIO_PIN_CNF_DRIVE_H0H1." 83 | #endif 84 | #if DRV_GPIO_DRIVE_D0S1 != GPIO_PIN_CNF_DRIVE_D0S1 85 | #error "ERROR: DRV_GPIO_DRIVE_D0S1 != GPIO_PIN_CNF_DRIVE_D0S1." 86 | #endif 87 | #if DRV_GPIO_DRIVE_D0H1 != GPIO_PIN_CNF_DRIVE_D0H1 88 | #error "ERROR: DRV_GPIO_DRIVE_D0H1 != GPIO_PIN_CNF_DRIVE_D0H1." 89 | #endif 90 | #if DRV_GPIO_DRIVE_S0D1 != GPIO_PIN_CNF_DRIVE_S0D1 91 | #error "ERROR: DRV_GPIO_DRIVE_S0D1 != GPIO_PIN_CNF_DRIVE_S0D1." 92 | #endif 93 | #if DRV_GPIO_DRIVE_H0D1 != GPIO_PIN_CNF_DRIVE_H0D1 94 | #error "ERROR: DRV_GPIO_DRIVE_H0D1 != GPIO_PIN_CNF_DRIVE_H0D1." 95 | #endif 96 | 97 | #else 98 | 99 | #error "ERROR: No DRV_GPIO definitions to check because drv_gpio.h was not included prior to this check." 100 | 101 | #endif // DRV_GPIO_H__ 102 | -------------------------------------------------------------------------------- /drv_gpio_example.c: -------------------------------------------------------------------------------- 1 | /* Copyright (c) Nordic Semiconductor ASA 2 | * All rights reserved. 3 | * 4 | * Redistribution and use in source and binary forms, with or without modification, 5 | * are permitted provided that the following conditions are met: 6 | * 7 | * 1. Redistributions of source code must retain the above copyright notice, this 8 | * list of conditions and the following disclaimer. 9 | * 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, this 11 | * list of conditions and the following disclaimer in the documentation and/or 12 | * other materials provided with the distribution. 13 | * 14 | * 3. Neither the name of Nordic Semiconductor ASA nor the names of other 15 | * contributors to this software may be used to endorse or promote products 16 | * derived from this software without specific prior written permission. 17 | * 18 | * 4. This software must only be used in a processor manufactured by Nordic 19 | * Semiconductor ASA, or in a processor manufactured by a third party that 20 | * is used in combination with a processor manufactured by Nordic Semiconductor. 21 | * 22 | * 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 27 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 | */ 34 | 35 | 36 | #include "pca10040.h" 37 | #include "nrf_error.h" 38 | #include "drv_gpio.h" 39 | #include "nrf_delay.h" 40 | 41 | #include 42 | 43 | #ifndef NRF52 44 | #error "ERROR: This example is only for NRF52." 45 | #endif 46 | 47 | 48 | #define M_NO_PIN_MSK (0) 49 | #define M_BUTTON_PINS_MSK ((1UL << BUTTON_1) | (1UL << BUTTON_2) | (1UL << BUTTON_3) | (1UL << BUTTON_4)) 50 | #define M_LED_PINS_MSK ((1UL << LED_1) | (1UL << LED_2) | (1UL << LED_3) | (1UL << LED_4)) 51 | 52 | 53 | /* 54 | This function blinks all 4 leds 4 times. 55 | */ 56 | static void m_example_start_indicate(void) 57 | { 58 | drv_gpio_outpin_cfg_t out_cfg = DRV_GPIO_OUTPIN_CFG_DEFAULT; 59 | 60 | drv_gpio_outpins_cfg(M_LED_PINS_MSK, out_cfg, DRV_GPIO_NO_PARAM_PTR); 61 | 62 | for (uint_fast8_t n = 0; n < 4; ++n) 63 | { 64 | nrf_delay_ms(250); 65 | drv_gpio_outport_modify(M_LED_PINS_MSK, M_NO_PIN_MSK); 66 | nrf_delay_ms(250); 67 | drv_gpio_outport_modify(M_NO_PIN_MSK, M_LED_PINS_MSK); 68 | } 69 | 70 | drv_gpio_pins_disconnect(M_LED_PINS_MSK); 71 | } 72 | 73 | 74 | /* 75 | m_drv_gpio_pin_cfg_example shows: 76 | - Configuration of individual pins. 77 | - Getting the level of single pins. 78 | - Setting the level of single pins. 79 | - Disconnecting single pins. 80 | */ 81 | static void m_drv_gpio_pin_cfg_example(void) 82 | { 83 | static const uint8_t MAPPING_SIZE = 4; 84 | static const uint8_t BUTTONS_PIN_MAP[MAPPING_SIZE] = {BUTTON_1, BUTTON_2, BUTTON_3, BUTTON_4}; 85 | static const uint8_t LEDS_PIN_MAP[MAPPING_SIZE] = {LED_1, LED_2, LED_3, LED_4}; 86 | 87 | /* Indicate the start of the example. */ 88 | m_example_start_indicate(); 89 | 90 | drv_gpio_outpin_cfg_t out_cfg = DRV_GPIO_OUTPIN_CFG_DEFAULT; 91 | drv_gpio_inpin_cfg_t in_cfg = DRV_GPIO_INPIN_CFG_DEFAULT; 92 | 93 | /* Tweak the default to use the internal pullup resistors of the nRF52 since 94 | there are no external pullup resistors on the nRF52 development board. */ 95 | in_cfg.pull = DRV_GPIO_PULL_UP; 96 | 97 | drv_gpio_outpin_cfg(LED_1, out_cfg, DRV_GPIO_NO_PARAM_PTR); 98 | drv_gpio_outpin_cfg(LED_2, out_cfg, DRV_GPIO_NO_PARAM_PTR); 99 | drv_gpio_outpin_cfg(LED_3, out_cfg, DRV_GPIO_NO_PARAM_PTR); 100 | drv_gpio_outpin_cfg(LED_4, out_cfg, DRV_GPIO_NO_PARAM_PTR); 101 | 102 | drv_gpio_inpin_cfg(BUTTON_1, in_cfg, DRV_GPIO_NO_PARAM_PTR); 103 | drv_gpio_inpin_cfg(BUTTON_2, in_cfg, DRV_GPIO_NO_PARAM_PTR); 104 | drv_gpio_inpin_cfg(BUTTON_3, in_cfg, DRV_GPIO_NO_PARAM_PTR); 105 | drv_gpio_inpin_cfg(BUTTON_4, in_cfg, DRV_GPIO_NO_PARAM_PTR); 106 | 107 | do 108 | { 109 | uint8_t level; 110 | 111 | for (uint_fast8_t i = 0; i < MAPPING_SIZE; ++i) 112 | { 113 | if (drv_gpio_inpin_get(BUTTONS_PIN_MAP[i], &level) == NRF_SUCCESS) 114 | { 115 | if (level == DRV_GPIO_LEVEL_LOW) 116 | { 117 | drv_gpio_outpin_level_set(LEDS_PIN_MAP[i], DRV_GPIO_LEVEL_HIGH); 118 | } 119 | else 120 | { 121 | drv_gpio_outpin_level_set(LEDS_PIN_MAP[i], DRV_GPIO_LEVEL_LOW); 122 | } 123 | } 124 | } 125 | } 126 | while ((drv_gpio_inport_get() & M_BUTTON_PINS_MSK) != 0); 127 | while ((drv_gpio_inport_get() & M_BUTTON_PINS_MSK) != M_BUTTON_PINS_MSK); 128 | 129 | for (uint_fast8_t i = 0; i < MAPPING_SIZE; ++i) 130 | { 131 | drv_gpio_pin_disconnect(BUTTONS_PIN_MAP[i]); 132 | drv_gpio_pin_disconnect(LEDS_PIN_MAP[i]); 133 | } 134 | } 135 | 136 | 137 | /* 138 | m_drv_gpio_pins_cfg_example shows: 139 | - Configuration of groups of pins. 140 | - Getting the level of a group of pins. 141 | - Setting the level of a group of pins. 142 | - Disconnecting a group of pins. 143 | */ 144 | static void m_drv_gpio_pins_cfg_example(void) 145 | { 146 | uint32_t inport; 147 | 148 | drv_gpio_outpin_cfg_t out_cfg = DRV_GPIO_OUTPIN_CFG_DEFAULT; 149 | drv_gpio_inpin_cfg_t in_cfg = DRV_GPIO_INPIN_CFG_DEFAULT; 150 | 151 | /* Indicate the start of the example. */ 152 | m_example_start_indicate(); 153 | 154 | /* Tweak the default to use the internal pullup resistors of the nRF52 since 155 | there are no external pullup resistors on the nRF52 development board. */ 156 | in_cfg.pull = DRV_GPIO_PULL_UP; 157 | 158 | drv_gpio_outpins_cfg(M_LED_PINS_MSK, out_cfg, DRV_GPIO_NO_PARAM_PTR); 159 | drv_gpio_inpins_cfg(M_BUTTON_PINS_MSK, in_cfg, DRV_GPIO_NO_PARAM_PTR); 160 | 161 | do 162 | { 163 | inport = drv_gpio_inport_get(); 164 | 165 | drv_gpio_outport_set((inport >> BUTTON_1) << LED_1); 166 | } 167 | while ((inport & M_BUTTON_PINS_MSK) != 0); 168 | while ((drv_gpio_inport_get() & M_BUTTON_PINS_MSK) != M_BUTTON_PINS_MSK); 169 | 170 | drv_gpio_pins_disconnect(M_BUTTON_PINS_MSK | M_LED_PINS_MSK); 171 | } 172 | 173 | 174 | /* 175 | m_drv_gpio_toggle_example shows: 176 | - Configuration of groups of pins. 177 | - Getting the level of a group of pins. 178 | - Sensing a group of pins using interrupts and the low-power PORT-event. 179 | - Setting the level of single pins. 180 | - Disconnecting a group of pins. 181 | */ 182 | static void m_drv_gpio_toggle_example_sig_handler(uint8_t pin, uint8_t sensed_state) 183 | { 184 | uint8_t level = (sensed_state == DRV_GPIO_SENSE_HITOLO) ? DRV_GPIO_LEVEL_HIGH : DRV_GPIO_LEVEL_LOW; 185 | 186 | switch (pin) 187 | { 188 | case BUTTON_1: 189 | drv_gpio_outpin_level_set(LED_1, level); 190 | break; 191 | case BUTTON_2: 192 | drv_gpio_outpin_level_set(LED_2, level); 193 | break; 194 | case BUTTON_3: 195 | drv_gpio_outpin_level_set(LED_3, level); 196 | break; 197 | case BUTTON_4: 198 | drv_gpio_outpin_level_set(LED_4, level); 199 | break; 200 | } 201 | } 202 | 203 | 204 | static void m_drv_gpio_toggle_example(void) 205 | { 206 | drv_gpio_outpin_cfg_t out_cfg = DRV_GPIO_OUTPIN_CFG_DEFAULT; 207 | drv_gpio_inpin_cfg_t in_cfg = 208 | { 209 | .sense = DRV_GPIO_SENSE_ANY, 210 | .pull = DRV_GPIO_PULL_UP, 211 | .gpiote = DRV_GPIO_GPIOTE_DISABLE, 212 | .handler = DRV_GPIO_HANDLER_ENABLE, 213 | }; 214 | 215 | /* Indicate the start of the example. */ 216 | m_example_start_indicate(); 217 | 218 | drv_gpio_outpins_cfg(M_LED_PINS_MSK, out_cfg, DRV_GPIO_NO_PARAM_PTR); 219 | drv_gpio_inpins_cfg(M_BUTTON_PINS_MSK, in_cfg, DRV_GPIO_NO_PARAM_PTR); 220 | 221 | drv_gpio_sig_handler_set(m_drv_gpio_toggle_example_sig_handler); 222 | 223 | while ((drv_gpio_inport_get() & M_BUTTON_PINS_MSK) != 0); 224 | while ((drv_gpio_inport_get() & M_BUTTON_PINS_MSK) != M_BUTTON_PINS_MSK); 225 | 226 | drv_gpio_pins_disconnect(M_BUTTON_PINS_MSK | M_LED_PINS_MSK); 227 | 228 | drv_gpio_sig_handler_set(DRV_GPIO_NO_SIG_HANDLER); 229 | } 230 | 231 | 232 | /* 233 | m_drv_gpio_toggle_hw_example shows: 234 | - Configuration of groups of pins. 235 | - Getting the level of a group of pins. 236 | - Toggling of sensing of inputs and toggling of outputs without firmware interraction. 237 | - Disconnecting a group of pins. 238 | */ 239 | static void m_drv_gpio_toggle_hw_example(void) 240 | { 241 | uint32_t * tasks[4]; 242 | uint32_t * events[4]; 243 | drv_gpio_outpin_cfg_t out_cfg = 244 | { 245 | .level = DRV_GPIO_LEVEL_LOW, 246 | .drive = DRV_GPIO_DRIVE_S0S1, 247 | .gpiote = DRV_GPIO_GPIOTE_ENABLE, 248 | .task = DRV_GPIO_TASK_TOGGLE, 249 | }; 250 | drv_gpio_inpin_cfg_t in_cfg = 251 | { 252 | .sense = DRV_GPIO_SENSE_ANY, 253 | .pull = DRV_GPIO_PULL_UP, 254 | .gpiote = DRV_GPIO_GPIOTE_ENABLE, 255 | .handler = DRV_GPIO_HANDLER_DISABLE, 256 | }; 257 | 258 | /* Indicate the start of the example. */ 259 | m_example_start_indicate(); 260 | 261 | drv_gpio_outpins_cfg(M_LED_PINS_MSK, out_cfg, &(tasks[0])); 262 | drv_gpio_inpins_cfg(M_BUTTON_PINS_MSK, in_cfg, &(events[0])); 263 | 264 | for (uint_fast8_t i = 0; i < 4; ++i) 265 | { 266 | NRF_PPI->CH[i].EEP = (uint32_t)events[i]; 267 | NRF_PPI->CH[i].TEP = (uint32_t)tasks[i]; 268 | 269 | NRF_PPI->CHENSET = 1UL << i; 270 | } 271 | 272 | while ((drv_gpio_inport_get() & M_BUTTON_PINS_MSK) != 0); 273 | while ((drv_gpio_inport_get() & M_BUTTON_PINS_MSK) != M_BUTTON_PINS_MSK); 274 | 275 | for (uint_fast8_t i = 0; i < 4; ++i) 276 | { 277 | NRF_PPI->CHENCLR = 1UL << i; 278 | } 279 | 280 | drv_gpio_pins_disconnect(M_BUTTON_PINS_MSK | M_LED_PINS_MSK); 281 | } 282 | 283 | 284 | /* 285 | m_drv_gpio_select_example shows: 286 | - Configuration of groups of pins. 287 | - Sensing a group of pins using interrupts and GPIOTE IN-event. 288 | - Interrupt on falling edge for a group of pins. 289 | - Toggling output pins on interrupt. 290 | - Disconnecting a group of pins. 291 | */ 292 | static void m_drv_gpio_select_example_sig_handler(uint8_t pin, uint8_t sensed_state) 293 | { 294 | switch (pin) 295 | { 296 | case BUTTON_1: 297 | drv_gpio_outport_toggle(1UL << LED_1); 298 | break; 299 | case BUTTON_2: 300 | drv_gpio_outport_toggle(1UL << LED_2); 301 | break; 302 | case BUTTON_3: 303 | drv_gpio_outport_toggle(1UL << LED_3); 304 | break; 305 | case BUTTON_4: 306 | drv_gpio_outport_toggle(1UL << LED_4); 307 | break; 308 | } 309 | } 310 | 311 | 312 | static void m_drv_gpio_select_example(void) 313 | { 314 | drv_gpio_outpin_cfg_t out_cfg = DRV_GPIO_OUTPIN_CFG_DEFAULT; 315 | drv_gpio_inpin_cfg_t in_cfg = 316 | { 317 | .sense = DRV_GPIO_SENSE_HITOLO, 318 | .pull = DRV_GPIO_PULL_UP, 319 | .gpiote = DRV_GPIO_GPIOTE_ENABLE, 320 | .handler = DRV_GPIO_HANDLER_ENABLE, 321 | }; 322 | 323 | /* Indicate the start of the example. */ 324 | m_example_start_indicate(); 325 | 326 | drv_gpio_outpins_cfg(M_LED_PINS_MSK, out_cfg, DRV_GPIO_NO_PARAM_PTR); 327 | drv_gpio_inpins_cfg(M_BUTTON_PINS_MSK, in_cfg, DRV_GPIO_NO_PARAM_PTR); 328 | 329 | drv_gpio_sig_handler_set(m_drv_gpio_select_example_sig_handler); 330 | 331 | while ((drv_gpio_inport_get() & M_BUTTON_PINS_MSK) != 0); 332 | while ((drv_gpio_inport_get() & M_BUTTON_PINS_MSK) != M_BUTTON_PINS_MSK); 333 | 334 | drv_gpio_pins_disconnect(M_BUTTON_PINS_MSK | M_LED_PINS_MSK); 335 | 336 | drv_gpio_sig_handler_set(DRV_GPIO_NO_SIG_HANDLER); 337 | } 338 | 339 | 340 | int main(void) 341 | { 342 | m_drv_gpio_pin_cfg_example(); 343 | 344 | m_drv_gpio_pins_cfg_example(); 345 | 346 | m_drv_gpio_toggle_example(); 347 | 348 | m_drv_gpio_toggle_hw_example(); 349 | 350 | m_drv_gpio_select_example(); 351 | 352 | for (;;) 353 | { 354 | } 355 | } 356 | -------------------------------------------------------------------------------- /drv_gpio/drv_gpio.h: -------------------------------------------------------------------------------- 1 | /* Copyright (c) Nordic Semiconductor ASA 2 | * All rights reserved. 3 | * 4 | * Redistribution and use in source and binary forms, with or without modification, 5 | * are permitted provided that the following conditions are met: 6 | * 7 | * 1. Redistributions of source code must retain the above copyright notice, this 8 | * list of conditions and the following disclaimer. 9 | * 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, this 11 | * list of conditions and the following disclaimer in the documentation and/or 12 | * other materials provided with the distribution. 13 | * 14 | * 3. Neither the name of Nordic Semiconductor ASA nor the names of other 15 | * contributors to this software may be used to endorse or promote products 16 | * derived from this software without specific prior written permission. 17 | * 18 | * 4. This software must only be used in a processor manufactured by Nordic 19 | * Semiconductor ASA, or in a processor manufactured by a third party that 20 | * is used in combination with a processor manufactured by Nordic Semiconductor. 21 | * 22 | * 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 27 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 | */ 34 | 35 | 36 | #ifndef DRV_GPIO_H__ 37 | #define DRV_GPIO_H__ 38 | 39 | #include "nrf.h" 40 | 41 | #include 42 | 43 | 44 | /**@brief Definition for undefined signal handler. */ 45 | #define DRV_GPIO_NO_SIG_HANDLER NULL 46 | 47 | 48 | /**@brief Definition of a pointer that does not point to parameters. */ 49 | #define DRV_GPIO_NO_PARAM_PTR NULL 50 | 51 | 52 | /**@brief The total number of GPIO pins. */ 53 | #define DRV_GPIO_NR_OF_PINS (32) 54 | 55 | 56 | /**@brief The total number of GPIOTE instances. */ 57 | #define DRV_GPIO_NR_OF_GPIOTE_INSTANCES (8) 58 | 59 | 60 | /**@brief Default input pin configuration is simple input without 61 | using the GPIOTE peripheral, sensing nor internal pull resistors. */ 62 | #define DRV_GPIO_INPIN_CFG_DEFAULT \ 63 | { \ 64 | .sense = DRV_GPIO_SENSE_NONE, \ 65 | .pull = DRV_GPIO_PULL_NONE, \ 66 | .gpiote = DRV_GPIO_GPIOTE_DISABLE, \ 67 | .handler = DRV_GPIO_HANDLER_DISABLE, \ 68 | } 69 | 70 | 71 | /**@brief Default output pin configuration is initially logical 72 | low signal level with standard output drive without using the GPIOTE peripheral. */ 73 | #define DRV_GPIO_OUTPIN_CFG_DEFAULT \ 74 | { \ 75 | .level = DRV_GPIO_LEVEL_LOW, \ 76 | .drive = DRV_GPIO_DRIVE_S0S1, \ 77 | .gpiote = DRV_GPIO_GPIOTE_DISABLE, \ 78 | } 79 | 80 | 81 | #define DRV_GPIO_SENSE_Width (2) /**< The width of the sense field. */ 82 | #define DRV_GPIO_SENSE_NONE (0) /**< No sense. */ 83 | #define DRV_GPIO_SENSE_LOTOHI (1) /**< Low to high sensing. */ 84 | #define DRV_GPIO_SENSE_HITOLO (2) /**< High to low sensing. */ 85 | #define DRV_GPIO_SENSE_ANY (3) /**< Either low to high or high to low sensing. */ 86 | 87 | 88 | #define DRV_GPIO_PULL_Width (2) /**< The width of the pull field. */ 89 | #define DRV_GPIO_PULL_NONE (0) /**< No pull. */ 90 | #define DRV_GPIO_PULL_UP (3) /**< Pull-up. */ 91 | #define DRV_GPIO_PULL_DOWN (1) /**< Pull-down */ 92 | 93 | 94 | #define DRV_GPIO_GPIOTE_Width (1) /**< The width of the gpiote field. */ 95 | #define DRV_GPIO_GPIOTE_DISABLE (0) /**< GPIOTE handling disabled. */ 96 | #define DRV_GPIO_GPIOTE_ENABLE (1) /**< GPIOTE handling enabled. */ 97 | 98 | 99 | #define DRV_GPIO_HANDLER_Width (1) /**< The width of the handler field. */ 100 | #define DRV_GPIO_HANDLER_DISABLE (0) /**< Handler disabled. */ 101 | #define DRV_GPIO_HANDLER_ENABLE (1) /**< Handler enabled. */ 102 | 103 | 104 | #define DRV_GPIO_LEVEL_Width (1) /**< The width of the level field. */ 105 | #define DRV_GPIO_LEVEL_LOW (0) /**< Logical low level. */ 106 | #define DRV_GPIO_LEVEL_HIGH (1) /**< Logical high level. */ 107 | 108 | 109 | #define DRV_GPIO_DRIVE_Width (3) /**< The width of the drive field. */ 110 | #define DRV_GPIO_DRIVE_S0S1 (0) /**< Standard '0', standard '1' */ 111 | #define DRV_GPIO_DRIVE_H0S1 (1) /**< High drive '0', standard '1' */ 112 | #define DRV_GPIO_DRIVE_S0H1 (2) /**< Standard '0', high drive '1' */ 113 | #define DRV_GPIO_DRIVE_H0H1 (3) /**< High drive '0', high drive '1' */ 114 | #define DRV_GPIO_DRIVE_D0S1 (4) /**< Disconnect '0' standard '1' (normally used for wired-or connections) */ 115 | #define DRV_GPIO_DRIVE_D0H1 (5) /**< Disconnect '0', high drive '1' (normally used for wired-or connections) */ 116 | #define DRV_GPIO_DRIVE_S0D1 (6) /**< Standard '0'. disconnect '1' (normally used for wired-and connections) */ 117 | #define DRV_GPIO_DRIVE_H0D1 (7) /**< High drive '0', disconnect '1' (normally used for wired-and connections) */ 118 | 119 | 120 | #define DRV_GPIO_TASK_Width (2) /**< The width of the task field. */ 121 | #define DRV_GPIO_TASK_CLEAR (0) /**< Task of clear-task type. */ 122 | #define DRV_GPIO_TASK_SET (1) /**< Task of set-task type. */ 123 | #define DRV_GPIO_TASK_TOGGLE (3) /**< Task of toggle-task type. */ 124 | 125 | 126 | /**@brief Input pin configuration. */ 127 | typedef struct 128 | { 129 | uint8_t sense : DRV_GPIO_SENSE_Width; /**< The sense type of the pin. */ 130 | uint8_t pull : DRV_GPIO_PULL_Width; /**< The pull resistor configuration of the pin. */ 131 | uint8_t gpiote : DRV_GPIO_GPIOTE_Width; /**< GPIOTE handling enable bit for the pin. */ 132 | uint8_t handler : DRV_GPIO_HANDLER_Width; /**< Interrupt handler enable bit for the pin. */ 133 | uint8_t rfu0 : sizeof(uint8_t) * 8 - 134 | ( 135 | DRV_GPIO_SENSE_Width + 136 | DRV_GPIO_PULL_Width + 137 | DRV_GPIO_GPIOTE_Width + 138 | DRV_GPIO_HANDLER_Width 139 | ); 140 | } drv_gpio_inpin_cfg_t; 141 | 142 | 143 | /**@brief Output pin configuration. */ 144 | typedef struct 145 | { 146 | uint8_t level : DRV_GPIO_LEVEL_Width; /**< The default level of the pin when initiated. */ 147 | uint8_t drive : DRV_GPIO_DRIVE_Width; /**< The drive configuration of the pin. */ 148 | uint8_t task : DRV_GPIO_TASK_Width; /**< The task type assosiated with the pin. */ 149 | uint8_t gpiote : DRV_GPIO_GPIOTE_Width; /**< GPIOTE handling enable bit for the pin. */ 150 | uint8_t rfu0 : sizeof(uint8_t) * 8 - 151 | ( 152 | DRV_GPIO_LEVEL_Width + 153 | DRV_GPIO_DRIVE_Width + 154 | DRV_GPIO_TASK_Width + 155 | DRV_GPIO_GPIOTE_Width 156 | ); 157 | } drv_gpio_outpin_cfg_t; 158 | 159 | 160 | /**@brief GPIO signal handler. 161 | * 162 | * @note The sensed edge is only unknown in case GPIOTE is sensing both edges. 163 | * 164 | * @param pin The pin which trigged signal. 165 | * @param sense_edge The edge that triggered the signal, or :DRV_GPIO_SENSE_ANY if unknown. */ 166 | typedef void (*drv_gpio_sig_handler_t)(uint8_t pin, uint8_t sensed_edge); 167 | 168 | 169 | /**@brief Sets the signal handler function. 170 | * 171 | * @param sig_handler The specified signal handler. */ 172 | void drv_gpio_sig_handler_set(drv_gpio_sig_handler_t sig_handler); 173 | 174 | 175 | /**@brief Configures the input pin according to the specified pin configuration. 176 | * 177 | * @param pin The specified pin to configure. 178 | * @param cfg The specified pin configuration. 179 | * @param p_event[out] Points to storage (or NULL) for the address of the hardware event associated with the pin, or NULL if none. 180 | * 181 | * @retval NRF_ERROR_INVALID_PARAM If the specified pin does not exist. 182 | * @retval NRF_ERROR_NOT_FOUND If no available GPIO instance was found. 183 | * @retval NRF_SUCCESS If successful. */ 184 | uint32_t drv_gpio_inpin_cfg(uint8_t pin, drv_gpio_inpin_cfg_t cfg, uint32_t ** p_event); 185 | 186 | 187 | /**@brief Configures the input pin according to the specified pin configuration. 188 | * 189 | * @param pin_msk The mask specifying the pins to configure. 190 | * @param cfg The specified pin configuration. 191 | * @param p_event_arr[out] Points to storage (or NULL) for the addresses of the hardware event associated with the pins, or NULL if none. 192 | * 193 | * @retval NRF_ERROR_INVALID_PARAM If the specified pin does not exist. 194 | * @retval NRF_ERROR_NOT_FOUND If no available GPIO instance was found. 195 | * @retval NRF_SUCCESS If successful. */ 196 | uint32_t drv_gpio_inpins_cfg(uint32_t pin_msk, drv_gpio_inpin_cfg_t cfg, uint32_t ** p_event_arr); 197 | 198 | 199 | /**@brief Configures the output pin according to the specified pin configuration. 200 | * 201 | * @param pin The specified pin to configure. 202 | * @param cfg The specified pin configuration. 203 | * @param p_task[out] Points to storage (or NULL) for the address of the hardware task associated with the pin, or NULL if none. 204 | * 205 | * @retval NRF_ERROR_INVALID_PARAM If the specified pin does not exist. 206 | * @retval NRF_ERROR_NOT_FOUND If no available GPIO instance was found. 207 | * @retval NRF_SUCCESS If successful. */ 208 | uint32_t drv_gpio_outpin_cfg(uint8_t pin, drv_gpio_outpin_cfg_t cfg, uint32_t ** p_task); 209 | 210 | 211 | /**@brief Configures the output pin according to the specified pin configuration. 212 | * 213 | * @param pin_msk The mask specifying the pins to configure. 214 | * @param cfg The specified pin configuration. 215 | * @param p_task_arr[out] Points to storage (or NULL) for the addresses of the hardware task associated with the pins, or NULL if none. 216 | * 217 | * @retval NRF_ERROR_INVALID_PARAM If the specified pin does not exist. 218 | * @retval NRF_ERROR_NOT_FOUND If no available GPIO instance was found. 219 | * @retval NRF_SUCCESS If successful. */ 220 | uint32_t drv_gpio_outpins_cfg(uint32_t pin_msk, drv_gpio_outpin_cfg_t cfg, uint32_t ** p_task_arr); 221 | 222 | 223 | /**@brief Disconnects the specified pin. 224 | * 225 | * @param pin The specified pin to disconnect. 226 | * 227 | * @retval NRF_ERROR_INVALID_PARAM If the specified pin does not exist. 228 | * @retval NRF_SUCCESS If successful. */ 229 | uint32_t drv_gpio_pin_disconnect(uint8_t pin); 230 | 231 | 232 | /**@brief Disconnects the specified pins. 233 | * 234 | * @param pin_msk The mask specifying the pins to disconnect. 235 | * @param cfg The specified pin configuration. 236 | * @param p_task_arr[out] Points to storage (or NULL) for the addresses of the hardware task associated with the pins, or NULL if none. 237 | * 238 | * @retval NRF_ERROR_INVALID_PARAM If no pin specified. 239 | * @retval NRF_SUCCESS If successful. */ 240 | uint32_t drv_gpio_pins_disconnect(uint32_t pin_msk); 241 | 242 | 243 | /**@brief Gets the logical level of the specified pin. 244 | * 245 | * @param pin The specified pin to configure. 246 | * @param p_level Pointer to storage where the pin level is to be stored. 247 | * 248 | * @retval NRF_ERROR_INVALID_PARAM If the specified pin does not exist or if the pointer is invalid. 249 | * @retval NRF_SUCCESS If successful. */ 250 | uint32_t drv_gpio_inpin_get(uint8_t pin, uint8_t *p_level); 251 | 252 | 253 | /**@brief Gets the logical level of all pins. 254 | * 255 | * @return The logical levels of all pins. */ 256 | uint32_t drv_gpio_inport_get(void); 257 | 258 | 259 | /**@brief Sets the specified logical level of the specified pin. 260 | * 261 | * @param pin The specified pin to configure. 262 | * @param level The specified level. 263 | * 264 | * @retval NRF_ERROR_INVALID_PARAM If the specified pin or level does not exist. 265 | * @retval NRF_SUCCESS If successful. */ 266 | uint32_t drv_gpio_outpin_level_set(uint8_t pin, uint8_t level); 267 | 268 | 269 | /**@brief Modifies the specified logical levels of the output port. 270 | * 271 | * @param high_msk The pins to be set to logical high value. 272 | * @param low_msk The pins to be cleared to logical low value. 273 | * 274 | * @retval NRF_ERROR_INVALID_PARAM If the specified masks overlap. 275 | * @retval NRF_SUCCESS If successful. */ 276 | uint32_t drv_gpio_outport_modify(uint32_t high_msk, uint32_t low_msk); 277 | 278 | 279 | /**@brief Toggles the logical levels of the specified output port pins. 280 | * 281 | * @param toggle_msk The pins to be alter their logical values. 282 | * 283 | * @return The logical levels of all pins. */ 284 | void drv_gpio_outport_toggle(uint32_t toggle_msk); 285 | 286 | 287 | /**@brief Sets the specified logical level of the the output port. 288 | * 289 | * @param outport The specified value of the outport. */ 290 | void drv_gpio_outport_set(uint32_t outport); 291 | 292 | 293 | #endif // DRV_GPIO_H__ 294 | -------------------------------------------------------------------------------- /drv_gpio/sdk_config.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | #ifndef SDK_CONFIG_H 4 | #define SDK_CONFIG_H 5 | // <<< Use Configuration Wizard in Context Menu >>>\n 6 | #ifdef USE_APP_CONFIG 7 | #include "app_config.h" 8 | #endif 9 | // nRF_Drivers 10 | 11 | //========================================================== 12 | // GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver 13 | //========================================================== 14 | #ifndef GPIOTE_ENABLED 15 | #define GPIOTE_ENABLED 0 16 | #endif 17 | #if GPIOTE_ENABLED 18 | // GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins 19 | #ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 20 | #define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 21 | #endif 22 | 23 | // GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority 24 | 25 | 26 | // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice 27 | // <0=> 0 (highest) 28 | // <1=> 1 29 | // <2=> 2 30 | // <3=> 3 31 | 32 | #ifndef GPIOTE_CONFIG_IRQ_PRIORITY 33 | #define GPIOTE_CONFIG_IRQ_PRIORITY 3 34 | #endif 35 | 36 | // GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. 37 | //========================================================== 38 | #ifndef GPIOTE_CONFIG_LOG_ENABLED 39 | #define GPIOTE_CONFIG_LOG_ENABLED 0 40 | #endif 41 | #if GPIOTE_CONFIG_LOG_ENABLED 42 | // GPIOTE_CONFIG_LOG_LEVEL - Default Severity level 43 | 44 | // <0=> Off 45 | // <1=> Error 46 | // <2=> Warning 47 | // <3=> Info 48 | // <4=> Debug 49 | 50 | #ifndef GPIOTE_CONFIG_LOG_LEVEL 51 | #define GPIOTE_CONFIG_LOG_LEVEL 3 52 | #endif 53 | 54 | // GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. 55 | 56 | // <0=> Default 57 | // <1=> Black 58 | // <2=> Red 59 | // <3=> Green 60 | // <4=> Yellow 61 | // <5=> Blue 62 | // <6=> Magenta 63 | // <7=> Cyan 64 | // <8=> White 65 | 66 | #ifndef GPIOTE_CONFIG_INFO_COLOR 67 | #define GPIOTE_CONFIG_INFO_COLOR 0 68 | #endif 69 | 70 | // GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. 71 | 72 | // <0=> Default 73 | // <1=> Black 74 | // <2=> Red 75 | // <3=> Green 76 | // <4=> Yellow 77 | // <5=> Blue 78 | // <6=> Magenta 79 | // <7=> Cyan 80 | // <8=> White 81 | 82 | #ifndef GPIOTE_CONFIG_DEBUG_COLOR 83 | #define GPIOTE_CONFIG_DEBUG_COLOR 0 84 | #endif 85 | 86 | #endif //GPIOTE_CONFIG_LOG_ENABLED 87 | // 88 | 89 | #endif //GPIOTE_ENABLED 90 | // 91 | 92 | // PERIPHERAL_RESOURCE_SHARING_ENABLED - nrf_drv_common - Peripheral drivers common module 93 | //========================================================== 94 | #ifndef PERIPHERAL_RESOURCE_SHARING_ENABLED 95 | #define PERIPHERAL_RESOURCE_SHARING_ENABLED 0 96 | #endif 97 | #if PERIPHERAL_RESOURCE_SHARING_ENABLED 98 | // COMMON_CONFIG_LOG_ENABLED - Enables logging in the module. 99 | //========================================================== 100 | #ifndef COMMON_CONFIG_LOG_ENABLED 101 | #define COMMON_CONFIG_LOG_ENABLED 0 102 | #endif 103 | #if COMMON_CONFIG_LOG_ENABLED 104 | // COMMON_CONFIG_LOG_LEVEL - Default Severity level 105 | 106 | // <0=> Off 107 | // <1=> Error 108 | // <2=> Warning 109 | // <3=> Info 110 | // <4=> Debug 111 | 112 | #ifndef COMMON_CONFIG_LOG_LEVEL 113 | #define COMMON_CONFIG_LOG_LEVEL 3 114 | #endif 115 | 116 | // COMMON_CONFIG_INFO_COLOR - ANSI escape code prefix. 117 | 118 | // <0=> Default 119 | // <1=> Black 120 | // <2=> Red 121 | // <3=> Green 122 | // <4=> Yellow 123 | // <5=> Blue 124 | // <6=> Magenta 125 | // <7=> Cyan 126 | // <8=> White 127 | 128 | #ifndef COMMON_CONFIG_INFO_COLOR 129 | #define COMMON_CONFIG_INFO_COLOR 0 130 | #endif 131 | 132 | // COMMON_CONFIG_DEBUG_COLOR - ANSI escape code prefix. 133 | 134 | // <0=> Default 135 | // <1=> Black 136 | // <2=> Red 137 | // <3=> Green 138 | // <4=> Yellow 139 | // <5=> Blue 140 | // <6=> Magenta 141 | // <7=> Cyan 142 | // <8=> White 143 | 144 | #ifndef COMMON_CONFIG_DEBUG_COLOR 145 | #define COMMON_CONFIG_DEBUG_COLOR 0 146 | #endif 147 | 148 | #endif //COMMON_CONFIG_LOG_ENABLED 149 | // 150 | 151 | #endif //PERIPHERAL_RESOURCE_SHARING_ENABLED 152 | // 153 | 154 | // PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver 155 | //========================================================== 156 | #ifndef PPI_ENABLED 157 | #define PPI_ENABLED 0 158 | #endif 159 | #if PPI_ENABLED 160 | // PPI_CONFIG_LOG_ENABLED - Enables logging in the module. 161 | //========================================================== 162 | #ifndef PPI_CONFIG_LOG_ENABLED 163 | #define PPI_CONFIG_LOG_ENABLED 0 164 | #endif 165 | #if PPI_CONFIG_LOG_ENABLED 166 | // PPI_CONFIG_LOG_LEVEL - Default Severity level 167 | 168 | // <0=> Off 169 | // <1=> Error 170 | // <2=> Warning 171 | // <3=> Info 172 | // <4=> Debug 173 | 174 | #ifndef PPI_CONFIG_LOG_LEVEL 175 | #define PPI_CONFIG_LOG_LEVEL 3 176 | #endif 177 | 178 | // PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. 179 | 180 | // <0=> Default 181 | // <1=> Black 182 | // <2=> Red 183 | // <3=> Green 184 | // <4=> Yellow 185 | // <5=> Blue 186 | // <6=> Magenta 187 | // <7=> Cyan 188 | // <8=> White 189 | 190 | #ifndef PPI_CONFIG_INFO_COLOR 191 | #define PPI_CONFIG_INFO_COLOR 0 192 | #endif 193 | 194 | // PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. 195 | 196 | // <0=> Default 197 | // <1=> Black 198 | // <2=> Red 199 | // <3=> Green 200 | // <4=> Yellow 201 | // <5=> Blue 202 | // <6=> Magenta 203 | // <7=> Cyan 204 | // <8=> White 205 | 206 | #ifndef PPI_CONFIG_DEBUG_COLOR 207 | #define PPI_CONFIG_DEBUG_COLOR 0 208 | #endif 209 | 210 | #endif //PPI_CONFIG_LOG_ENABLED 211 | // 212 | 213 | #endif //PPI_ENABLED 214 | // 215 | 216 | // TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver 217 | //========================================================== 218 | #ifndef TIMER_ENABLED 219 | #define TIMER_ENABLED 0 220 | #endif 221 | #if TIMER_ENABLED 222 | // TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode 223 | 224 | // <0=> 16 MHz 225 | // <1=> 8 MHz 226 | // <2=> 4 MHz 227 | // <3=> 2 MHz 228 | // <4=> 1 MHz 229 | // <5=> 500 kHz 230 | // <6=> 250 kHz 231 | // <7=> 125 kHz 232 | // <8=> 62.5 kHz 233 | // <9=> 31.25 kHz 234 | 235 | #ifndef TIMER_DEFAULT_CONFIG_FREQUENCY 236 | #define TIMER_DEFAULT_CONFIG_FREQUENCY 4 237 | #endif 238 | 239 | // TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation 240 | 241 | // <0=> Timer 242 | // <1=> Counter 243 | 244 | #ifndef TIMER_DEFAULT_CONFIG_MODE 245 | #define TIMER_DEFAULT_CONFIG_MODE 0 246 | #endif 247 | 248 | // TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width 249 | 250 | // <0=> 16 bit 251 | // <1=> 8 bit 252 | // <2=> 24 bit 253 | // <3=> 32 bit 254 | 255 | #ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH 256 | #define TIMER_DEFAULT_CONFIG_BIT_WIDTH 3 257 | #endif 258 | 259 | // TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority 260 | 261 | 262 | // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice 263 | // <0=> 0 (highest) 264 | // <1=> 1 265 | // <2=> 2 266 | // <3=> 3 267 | 268 | #ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 269 | #define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 3 270 | #endif 271 | 272 | // TIMER0_ENABLED - Enable TIMER0 instance 273 | 274 | 275 | #ifndef TIMER0_ENABLED 276 | #define TIMER0_ENABLED 1 277 | #endif 278 | 279 | // TIMER1_ENABLED - Enable TIMER1 instance 280 | 281 | 282 | #ifndef TIMER1_ENABLED 283 | #define TIMER1_ENABLED 0 284 | #endif 285 | 286 | // TIMER2_ENABLED - Enable TIMER2 instance 287 | 288 | 289 | #ifndef TIMER2_ENABLED 290 | #define TIMER2_ENABLED 0 291 | #endif 292 | 293 | // TIMER3_ENABLED - Enable TIMER3 instance 294 | 295 | 296 | #ifndef TIMER3_ENABLED 297 | #define TIMER3_ENABLED 0 298 | #endif 299 | 300 | // TIMER4_ENABLED - Enable TIMER4 instance 301 | 302 | 303 | #ifndef TIMER4_ENABLED 304 | #define TIMER4_ENABLED 0 305 | #endif 306 | 307 | // TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. 308 | //========================================================== 309 | #ifndef TIMER_CONFIG_LOG_ENABLED 310 | #define TIMER_CONFIG_LOG_ENABLED 0 311 | #endif 312 | #if TIMER_CONFIG_LOG_ENABLED 313 | // TIMER_CONFIG_LOG_LEVEL - Default Severity level 314 | 315 | // <0=> Off 316 | // <1=> Error 317 | // <2=> Warning 318 | // <3=> Info 319 | // <4=> Debug 320 | 321 | #ifndef TIMER_CONFIG_LOG_LEVEL 322 | #define TIMER_CONFIG_LOG_LEVEL 3 323 | #endif 324 | 325 | // TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. 326 | 327 | // <0=> Default 328 | // <1=> Black 329 | // <2=> Red 330 | // <3=> Green 331 | // <4=> Yellow 332 | // <5=> Blue 333 | // <6=> Magenta 334 | // <7=> Cyan 335 | // <8=> White 336 | 337 | #ifndef TIMER_CONFIG_INFO_COLOR 338 | #define TIMER_CONFIG_INFO_COLOR 0 339 | #endif 340 | 341 | // TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. 342 | 343 | // <0=> Default 344 | // <1=> Black 345 | // <2=> Red 346 | // <3=> Green 347 | // <4=> Yellow 348 | // <5=> Blue 349 | // <6=> Magenta 350 | // <7=> Cyan 351 | // <8=> White 352 | 353 | #ifndef TIMER_CONFIG_DEBUG_COLOR 354 | #define TIMER_CONFIG_DEBUG_COLOR 0 355 | #endif 356 | 357 | #endif //TIMER_CONFIG_LOG_ENABLED 358 | // 359 | 360 | #endif //TIMER_ENABLED 361 | // 362 | 363 | // UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver 364 | //========================================================== 365 | #ifndef UART_ENABLED 366 | #define UART_ENABLED 0 367 | #endif 368 | #if UART_ENABLED 369 | // UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control 370 | 371 | // <0=> Disabled 372 | // <1=> Enabled 373 | 374 | #ifndef UART_DEFAULT_CONFIG_HWFC 375 | #define UART_DEFAULT_CONFIG_HWFC 0 376 | #endif 377 | 378 | // UART_DEFAULT_CONFIG_PARITY - Parity 379 | 380 | // <0=> Excluded 381 | // <14=> Included 382 | 383 | #ifndef UART_DEFAULT_CONFIG_PARITY 384 | #define UART_DEFAULT_CONFIG_PARITY 0 385 | #endif 386 | 387 | // UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate 388 | 389 | // <323584=> 1200 baud 390 | // <643072=> 2400 baud 391 | // <1290240=> 4800 baud 392 | // <2576384=> 9600 baud 393 | // <3862528=> 14400 baud 394 | // <5152768=> 19200 baud 395 | // <7716864=> 28800 baud 396 | // <10289152=> 38400 baud 397 | // <15400960=> 57600 baud 398 | // <20615168=> 76800 baud 399 | // <30924800=> 115200 baud 400 | // <61865984=> 230400 baud 401 | // <67108864=> 250000 baud 402 | // <121634816=> 460800 baud 403 | // <251658240=> 921600 baud 404 | // <268435456=> 57600 baud 405 | 406 | #ifndef UART_DEFAULT_CONFIG_BAUDRATE 407 | #define UART_DEFAULT_CONFIG_BAUDRATE 30924800 408 | #endif 409 | 410 | // UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority 411 | 412 | 413 | // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice 414 | // <0=> 0 (highest) 415 | // <1=> 1 416 | // <2=> 2 417 | // <3=> 3 418 | 419 | #ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY 420 | #define UART_DEFAULT_CONFIG_IRQ_PRIORITY 3 421 | #endif 422 | 423 | // UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA 424 | 425 | 426 | #ifndef UART_EASY_DMA_SUPPORT 427 | #define UART_EASY_DMA_SUPPORT 1 428 | #endif 429 | 430 | // UART_LEGACY_SUPPORT - Driver supporting Legacy mode 431 | 432 | 433 | #ifndef UART_LEGACY_SUPPORT 434 | #define UART_LEGACY_SUPPORT 1 435 | #endif 436 | 437 | // UART0_ENABLED - Enable UART0 instance 438 | //========================================================== 439 | #ifndef UART0_ENABLED 440 | #define UART0_ENABLED 1 441 | #endif 442 | #if UART0_ENABLED 443 | // UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA 444 | 445 | 446 | #ifndef UART0_CONFIG_USE_EASY_DMA 447 | #define UART0_CONFIG_USE_EASY_DMA 1 448 | #endif 449 | 450 | #endif //UART0_ENABLED 451 | // 452 | 453 | // UART_CONFIG_LOG_ENABLED - Enables logging in the module. 454 | //========================================================== 455 | #ifndef UART_CONFIG_LOG_ENABLED 456 | #define UART_CONFIG_LOG_ENABLED 0 457 | #endif 458 | #if UART_CONFIG_LOG_ENABLED 459 | // UART_CONFIG_LOG_LEVEL - Default Severity level 460 | 461 | // <0=> Off 462 | // <1=> Error 463 | // <2=> Warning 464 | // <3=> Info 465 | // <4=> Debug 466 | 467 | #ifndef UART_CONFIG_LOG_LEVEL 468 | #define UART_CONFIG_LOG_LEVEL 3 469 | #endif 470 | 471 | // UART_CONFIG_INFO_COLOR - ANSI escape code prefix. 472 | 473 | // <0=> Default 474 | // <1=> Black 475 | // <2=> Red 476 | // <3=> Green 477 | // <4=> Yellow 478 | // <5=> Blue 479 | // <6=> Magenta 480 | // <7=> Cyan 481 | // <8=> White 482 | 483 | #ifndef UART_CONFIG_INFO_COLOR 484 | #define UART_CONFIG_INFO_COLOR 0 485 | #endif 486 | 487 | // UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. 488 | 489 | // <0=> Default 490 | // <1=> Black 491 | // <2=> Red 492 | // <3=> Green 493 | // <4=> Yellow 494 | // <5=> Blue 495 | // <6=> Magenta 496 | // <7=> Cyan 497 | // <8=> White 498 | 499 | #ifndef UART_CONFIG_DEBUG_COLOR 500 | #define UART_CONFIG_DEBUG_COLOR 0 501 | #endif 502 | 503 | #endif //UART_CONFIG_LOG_ENABLED 504 | // 505 | 506 | #endif //UART_ENABLED 507 | // 508 | 509 | // 510 | //========================================================== 511 | 512 | // nRF_Log 513 | 514 | //========================================================== 515 | // NRF_LOG_ENABLED - nrf_log - Logging 516 | //========================================================== 517 | #ifndef NRF_LOG_ENABLED 518 | #define NRF_LOG_ENABLED 0 519 | #endif 520 | #if NRF_LOG_ENABLED 521 | // NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string 522 | //========================================================== 523 | #ifndef NRF_LOG_USES_COLORS 524 | #define NRF_LOG_USES_COLORS 0 525 | #endif 526 | #if NRF_LOG_USES_COLORS 527 | // NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. 528 | 529 | // <0=> Default 530 | // <1=> Black 531 | // <2=> Red 532 | // <3=> Green 533 | // <4=> Yellow 534 | // <5=> Blue 535 | // <6=> Magenta 536 | // <7=> Cyan 537 | // <8=> White 538 | 539 | #ifndef NRF_LOG_COLOR_DEFAULT 540 | #define NRF_LOG_COLOR_DEFAULT 0 541 | #endif 542 | 543 | // NRF_LOG_ERROR_COLOR - ANSI escape code prefix. 544 | 545 | // <0=> Default 546 | // <1=> Black 547 | // <2=> Red 548 | // <3=> Green 549 | // <4=> Yellow 550 | // <5=> Blue 551 | // <6=> Magenta 552 | // <7=> Cyan 553 | // <8=> White 554 | 555 | #ifndef NRF_LOG_ERROR_COLOR 556 | #define NRF_LOG_ERROR_COLOR 0 557 | #endif 558 | 559 | // NRF_LOG_WARNING_COLOR - ANSI escape code prefix. 560 | 561 | // <0=> Default 562 | // <1=> Black 563 | // <2=> Red 564 | // <3=> Green 565 | // <4=> Yellow 566 | // <5=> Blue 567 | // <6=> Magenta 568 | // <7=> Cyan 569 | // <8=> White 570 | 571 | #ifndef NRF_LOG_WARNING_COLOR 572 | #define NRF_LOG_WARNING_COLOR 0 573 | #endif 574 | 575 | #endif //NRF_LOG_USES_COLORS 576 | // 577 | 578 | // NRF_LOG_DEFAULT_LEVEL - Default Severity level 579 | 580 | // <0=> Off 581 | // <1=> Error 582 | // <2=> Warning 583 | // <3=> Info 584 | // <4=> Debug 585 | 586 | #ifndef NRF_LOG_DEFAULT_LEVEL 587 | #define NRF_LOG_DEFAULT_LEVEL 3 588 | #endif 589 | 590 | // NRF_LOG_DEFERRED - Enable deffered logger. 591 | 592 | // Log data is buffered and can be processed in idle. 593 | //========================================================== 594 | #ifndef NRF_LOG_DEFERRED 595 | #define NRF_LOG_DEFERRED 1 596 | #endif 597 | #if NRF_LOG_DEFERRED 598 | // NRF_LOG_DEFERRED_BUFSIZE - Size of the buffer for logs in words. 599 | // Must be power of 2 600 | 601 | #ifndef NRF_LOG_DEFERRED_BUFSIZE 602 | #define NRF_LOG_DEFERRED_BUFSIZE 256 603 | #endif 604 | 605 | #endif //NRF_LOG_DEFERRED 606 | // 607 | 608 | // NRF_LOG_USES_TIMESTAMP - Enable timestamping 609 | 610 | 611 | // Function for getting the timestamp is provided by the user 612 | 613 | #ifndef NRF_LOG_USES_TIMESTAMP 614 | #define NRF_LOG_USES_TIMESTAMP 0 615 | #endif 616 | 617 | #endif //NRF_LOG_ENABLED 618 | // 619 | 620 | // nrf_log_backend - Logging sink 621 | 622 | //========================================================== 623 | // NRF_LOG_BACKEND_MAX_STRING_LENGTH - Buffer for storing single output string 624 | // Logger backend RAM usage is determined by this value. 625 | 626 | #ifndef NRF_LOG_BACKEND_MAX_STRING_LENGTH 627 | #define NRF_LOG_BACKEND_MAX_STRING_LENGTH 256 628 | #endif 629 | 630 | // NRF_LOG_TIMESTAMP_DIGITS - Number of digits for timestamp 631 | // If higher resolution timestamp source is used it might be needed to increase that 632 | 633 | #ifndef NRF_LOG_TIMESTAMP_DIGITS 634 | #define NRF_LOG_TIMESTAMP_DIGITS 8 635 | #endif 636 | 637 | // NRF_LOG_BACKEND_SERIAL_USES_UART - If enabled data is printed over UART 638 | //========================================================== 639 | #ifndef NRF_LOG_BACKEND_SERIAL_USES_UART 640 | #define NRF_LOG_BACKEND_SERIAL_USES_UART 1 641 | #endif 642 | #if NRF_LOG_BACKEND_SERIAL_USES_UART 643 | // NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE - Default Baudrate 644 | 645 | // <323584=> 1200 baud 646 | // <643072=> 2400 baud 647 | // <1290240=> 4800 baud 648 | // <2576384=> 9600 baud 649 | // <3862528=> 14400 baud 650 | // <5152768=> 19200 baud 651 | // <7716864=> 28800 baud 652 | // <10289152=> 38400 baud 653 | // <15400960=> 57600 baud 654 | // <20615168=> 76800 baud 655 | // <30924800=> 115200 baud 656 | // <61865984=> 230400 baud 657 | // <67108864=> 250000 baud 658 | // <121634816=> 460800 baud 659 | // <251658240=> 921600 baud 660 | // <268435456=> 57600 baud 661 | 662 | #ifndef NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 663 | #define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 30924800 664 | #endif 665 | 666 | // NRF_LOG_BACKEND_SERIAL_UART_TX_PIN - UART TX pin 667 | #ifndef NRF_LOG_BACKEND_SERIAL_UART_TX_PIN 668 | #define NRF_LOG_BACKEND_SERIAL_UART_TX_PIN 9 669 | #endif 670 | 671 | // NRF_LOG_BACKEND_SERIAL_UART_RX_PIN - UART RX pin 672 | #ifndef NRF_LOG_BACKEND_SERIAL_UART_RX_PIN 673 | #define NRF_LOG_BACKEND_SERIAL_UART_RX_PIN 11 674 | #endif 675 | 676 | // NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN - UART RTS pin 677 | #ifndef NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN 678 | #define NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN 8 679 | #endif 680 | 681 | // NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN - UART CTS pin 682 | #ifndef NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN 683 | #define NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN 10 684 | #endif 685 | 686 | // NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL - Hardware Flow Control 687 | 688 | // <0=> Disabled 689 | // <1=> Enabled 690 | 691 | #ifndef NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL 692 | #define NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL 0 693 | #endif 694 | 695 | // NRF_LOG_BACKEND_UART_INSTANCE - UART instance used 696 | 697 | // <0=> 0 698 | 699 | #ifndef NRF_LOG_BACKEND_UART_INSTANCE 700 | #define NRF_LOG_BACKEND_UART_INSTANCE 0 701 | #endif 702 | 703 | #endif //NRF_LOG_BACKEND_SERIAL_USES_UART 704 | // 705 | 706 | // NRF_LOG_BACKEND_SERIAL_USES_RTT - If enabled data is printed using RTT 707 | //========================================================== 708 | #ifndef NRF_LOG_BACKEND_SERIAL_USES_RTT 709 | #define NRF_LOG_BACKEND_SERIAL_USES_RTT 0 710 | #endif 711 | #if NRF_LOG_BACKEND_SERIAL_USES_RTT 712 | // NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE - RTT output buffer size. 713 | // Should be equal or bigger than \ref NRF_LOG_BACKEND_MAX_STRING_LENGTH. 714 | // This value is used in Segger RTT configuration to set the buffer size 715 | // if it is bigger than default RTT buffer size. 716 | 717 | #ifndef NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE 718 | #define NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE 512 719 | #endif 720 | 721 | #endif //NRF_LOG_BACKEND_SERIAL_USES_RTT 722 | // 723 | 724 | // 725 | //========================================================== 726 | 727 | // 728 | //========================================================== 729 | 730 | // nRF_Segger_RTT 731 | 732 | //========================================================== 733 | // segger_rtt - SEGGER RTT 734 | 735 | //========================================================== 736 | // SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - Size of upstream buffer. 737 | #ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 738 | #define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 64 739 | #endif 740 | 741 | // SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS - Size of upstream buffer. 742 | #ifndef SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 743 | #define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 2 744 | #endif 745 | 746 | // SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN - Size of upstream buffer. 747 | #ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 748 | #define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 16 749 | #endif 750 | 751 | // SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS - Size of upstream buffer. 752 | #ifndef SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 753 | #define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 2 754 | #endif 755 | 756 | // 757 | //========================================================== 758 | 759 | // 760 | //========================================================== 761 | 762 | // <<< end of configuration section >>> 763 | #endif //SDK_CONFIG_H 764 | 765 | -------------------------------------------------------------------------------- /pca10040/arm5_no_packs/drv_gpio_example.uvprojx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2.1 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | 10 | drv_gpio_example 11 | 0x4 12 | ARM-ADS 13 | 14 | 15 | nRF52832_xxAA 16 | Nordic Semiconductor 17 | NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1 18 | http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ 19 | IROM(0x00000000,0x80000) IRAM(0x20000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE 20 | 21 | 22 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)) 23 | 0 24 | $$Device:nRF52832_xxAA$Device\Include\nrf.h 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | $$Device:nRF52832_xxAA$SVD\nrf52.svd 35 | 0 36 | 0 37 | 38 | 39 | 40 | 41 | 42 | 43 | 0 44 | 0 45 | 0 46 | 0 47 | 1 48 | 49 | .\build\ 50 | drv_gpio_example 51 | 1 52 | 0 53 | 1 54 | 0 55 | 1 56 | .\build\ 57 | 1 58 | 0 59 | 0 60 | 61 | 0 62 | 0 63 | 64 | 65 | 0 66 | 0 67 | 0 68 | 0 69 | 70 | 71 | 0 72 | 0 73 | msbuild ..\..\..\Framework\builds\ScatterFileParametrization.xml 74 | 75 | 0 76 | 0 77 | 0 78 | 0 79 | 80 | 81 | 0 82 | 0 83 | 84 | 85 | 0 86 | 0 87 | 88 | 0 89 | 90 | 91 | 92 | 0 93 | 0 94 | 0 95 | 0 96 | 0 97 | 1 98 | 0 99 | 0 100 | 0 101 | 0 102 | 3 103 | 104 | 105 | 1 106 | 107 | 108 | SARMCM3.DLL 109 | -MPU 110 | DCM.DLL 111 | -pCM4 112 | SARMCM3.DLL 113 | -MPU 114 | TCM.DLL 115 | -pCM4 116 | 117 | 118 | 119 | 1 120 | 0 121 | 0 122 | 0 123 | 16 124 | 125 | 126 | 0 127 | 0 128 | 0 129 | 1 130 | 1 131 | 1 132 | 1 133 | 1 134 | 0 135 | 1 136 | 137 | 138 | 1 139 | 1 140 | 1 141 | 1 142 | 1 143 | 1 144 | 0 145 | 1 146 | 0 147 | 1 148 | 149 | 0 150 | 6 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | Segger\JL2CM3.dll 165 | 166 | 167 | 168 | 169 | 1 170 | 0 171 | 0 172 | 1 173 | 1 174 | 4096 175 | 176 | 1 177 | BIN\UL2CM3.DLL 178 | "" () 179 | 180 | 181 | 182 | 183 | 0 184 | 185 | 186 | 187 | 0 188 | 1 189 | 1 190 | 1 191 | 1 192 | 1 193 | 1 194 | 1 195 | 0 196 | 1 197 | 1 198 | 0 199 | 1 200 | 1 201 | 0 202 | 0 203 | 1 204 | 1 205 | 1 206 | 1 207 | 1 208 | 1 209 | 1 210 | 1 211 | 1 212 | 0 213 | 0 214 | "Cortex-M4" 215 | 216 | 0 217 | 0 218 | 0 219 | 1 220 | 1 221 | 0 222 | 0 223 | 2 224 | 0 225 | 0 226 | 8 227 | 1 228 | 0 229 | 0 230 | 3 231 | 3 232 | 0 233 | 0 234 | 0 235 | 0 236 | 0 237 | 0 238 | 0 239 | 0 240 | 0 241 | 0 242 | 1 243 | 0 244 | 0 245 | 0 246 | 0 247 | 1 248 | 0 249 | 250 | 251 | 0 252 | 0x0 253 | 0x0 254 | 255 | 256 | 0 257 | 0x0 258 | 0x0 259 | 260 | 261 | 0 262 | 0x0 263 | 0x0 264 | 265 | 266 | 0 267 | 0x0 268 | 0x0 269 | 270 | 271 | 0 272 | 0x0 273 | 0x0 274 | 275 | 276 | 0 277 | 0x0 278 | 0x0 279 | 280 | 281 | 0 282 | 0x20000000 283 | 0x10000 284 | 285 | 286 | 1 287 | 0x0 288 | 0x80000 289 | 290 | 291 | 0 292 | 0x0 293 | 0x0 294 | 295 | 296 | 1 297 | 0x0 298 | 0x0 299 | 300 | 301 | 1 302 | 0x0 303 | 0x0 304 | 305 | 306 | 1 307 | 0x0 308 | 0x0 309 | 310 | 311 | 1 312 | 0x0 313 | 0x80000 314 | 315 | 316 | 1 317 | 0x0 318 | 0x0 319 | 320 | 321 | 0 322 | 0x0 323 | 0x0 324 | 325 | 326 | 0 327 | 0x0 328 | 0x0 329 | 330 | 331 | 0 332 | 0x0 333 | 0x0 334 | 335 | 336 | 0 337 | 0x20000000 338 | 0x10000 339 | 340 | 341 | 0 342 | 0x0 343 | 0x0 344 | 345 | 346 | 347 | 348 | 349 | 1 350 | 1 351 | 0 352 | 0 353 | 0 354 | 0 355 | 0 356 | 0 357 | 0 358 | 0 359 | 0 360 | 0 361 | 0 362 | 0 363 | 0 364 | 365 | --c99 366 | NRF52832 367 | 368 | ..\..\drv_gpio;..\..\..\..\..\components\boards;..\..\..\..\..\components\drivers_nrf\nrf_soc_nosd;..\..\..\..\..\components\drivers_nrf\hal;..\..\..\..\..\components\drivers_nrf\delay;..\..\..\..\..\components\libraries\util;..\..\..\..\..\config 369 | 370 | 371 | 372 | 1 373 | 0 374 | 0 375 | 0 376 | 0 377 | 0 378 | 0 379 | 0 380 | 0 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 1 390 | 0 391 | 0 392 | 0 393 | 1 394 | 0 395 | 0x00000000 396 | 0x00000000 397 | 398 | .\scatter.sct 399 | 400 | 401 | 402 | 403 | 404 | 405 | 406 | 407 | 408 | 409 | Example 410 | 411 | 412 | drv_gpio_example.c 413 | 1 414 | ..\..\drv_gpio_example.c 415 | 416 | 417 | 418 | 419 | Driver 420 | 421 | 422 | drv_gpio.c 423 | 1 424 | ..\..\drv_gpio\drv_gpio.c 425 | 426 | 427 | 428 | 429 | ::CMSIS 430 | 431 | 432 | ::Device 433 | 434 | 435 | 436 | 437 | 438 | 439 | 440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | 450 | 451 | 452 | 453 | 454 | 455 | 456 | RTE\Device\nRF51422_xxAB\arm_startup_nrf51.s 457 | 458 | 459 | 460 | 461 | 462 | RTE\Device\nRF51422_xxAB\system_nrf51.c 463 | 464 | 465 | 466 | 467 | 468 | RTE\Device\nRF52832_xxAA\arm_startup_nrf52.s 469 | 470 | 471 | 472 | 473 | 474 | 475 | 476 | RTE\Device\nRF52832_xxAA\system_nrf52.c 477 | 478 | 479 | 480 | 481 | 482 | 483 | 484 | 485 | 486 | 487 | -------------------------------------------------------------------------------- /drv_gpio/drv_gpio.c: -------------------------------------------------------------------------------- 1 | /* Copyright (c) Nordic Semiconductor ASA 2 | * All rights reserved. 3 | * 4 | * Redistribution and use in source and binary forms, with or without modification, 5 | * are permitted provided that the following conditions are met: 6 | * 7 | * 1. Redistributions of source code must retain the above copyright notice, this 8 | * list of conditions and the following disclaimer. 9 | * 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, this 11 | * list of conditions and the following disclaimer in the documentation and/or 12 | * other materials provided with the distribution. 13 | * 14 | * 3. Neither the name of Nordic Semiconductor ASA nor the names of other 15 | * contributors to this software may be used to endorse or promote products 16 | * derived from this software without specific prior written permission. 17 | * 18 | * 4. This software must only be used in a processor manufactured by Nordic 19 | * Semiconductor ASA, or in a processor manufactured by a third party that 20 | * is used in combination with a processor manufactured by Nordic Semiconductor. 21 | * 22 | * 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 27 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 | */ 34 | 35 | 36 | #include "drv_gpio.h" 37 | #include "drv_gpio_def_check.h" 38 | #include "nrf_error.h" 39 | 40 | #include 41 | #include 42 | 43 | 44 | #define M_NO_PIN_MSK (0) 45 | 46 | 47 | typedef struct 48 | { 49 | uint8_t current_sense : DRV_GPIO_SENSE_Width; 50 | uint8_t handler_enable : DRV_GPIO_HANDLER_Width; 51 | uint8_t rfu0 : sizeof(uint8_t) * 8 - 52 | ( 53 | DRV_GPIO_LEVEL_Width + 54 | DRV_GPIO_SENSE_Width + 55 | DRV_GPIO_HANDLER_Width 56 | ); 57 | } pin_state_t; 58 | 59 | 60 | static struct 61 | { 62 | struct 63 | { 64 | uint32_t pin_msk; 65 | uint8_t cnt; 66 | } gpiote; 67 | pin_state_t gpio_states[DRV_GPIO_NR_OF_PINS]; 68 | drv_gpio_sig_handler_t sig_handler; 69 | } m_drv_gpio = {.gpiote.cnt = 0, .gpiote.pin_msk = 0, .sig_handler = DRV_GPIO_NO_SIG_HANDLER}; 70 | 71 | 72 | /**@brief Acquires a GPIOTE instance for the specified pin. 73 | * 74 | * @param pin_no The pin number of the pin to acquire an instance for. 75 | * 76 | * @retval true If there was a vacant GPIOTE instance to acquire. 77 | * @retval false If there was no vacant GPIOTE instance available. */ 78 | static __INLINE bool gpiote_pin_acquire(uint8_t pin_no) 79 | { 80 | if (((m_drv_gpio.gpiote.pin_msk & (1UL << pin_no)) == 0) 81 | && (m_drv_gpio.gpiote.cnt < DRV_GPIO_NR_OF_GPIOTE_INSTANCES)) 82 | { 83 | for (uint8_t i = 0; i < DRV_GPIO_NR_OF_GPIOTE_INSTANCES; i++) 84 | { 85 | if (((NRF_GPIOTE->CONFIG[i] & GPIOTE_CONFIG_MODE_Msk) >> GPIOTE_CONFIG_MODE_Pos) == GPIOTE_CONFIG_MODE_Disabled) 86 | { 87 | NRF_GPIOTE->CONFIG[i] = (NRF_GPIOTE->CONFIG[i] & ~GPIOTE_CONFIG_PSEL_Msk) | (pin_no << GPIOTE_CONFIG_PSEL_Pos); 88 | 89 | m_drv_gpio.gpiote.pin_msk |= (1UL << pin_no); 90 | ++m_drv_gpio.gpiote.cnt; 91 | 92 | return true; 93 | } 94 | } 95 | } 96 | 97 | return false; 98 | } 99 | 100 | 101 | /**@brief Releases the GPIOTE instance associated with the specified pin. 102 | * 103 | * @param pin_no The pin number of the pin to release the instance for. 104 | * 105 | * @retval true If there was a GPIOTE instance associated with the specified pin. 106 | * @retval false If there was no GPIOTE instance associated with the specified pin. */ 107 | static __INLINE bool gpiote_pin_release(uint8_t pin_no) 108 | { 109 | if (((m_drv_gpio.gpiote.pin_msk & (1UL << pin_no)) != 0) 110 | && (m_drv_gpio.gpiote.cnt > 0)) 111 | { 112 | for (uint8_t i = 0; i < DRV_GPIO_NR_OF_GPIOTE_INSTANCES; i++) 113 | { 114 | if (((NRF_GPIOTE->CONFIG[i] & GPIOTE_CONFIG_MODE_Msk) >> GPIOTE_CONFIG_MODE_Pos) != GPIOTE_CONFIG_MODE_Disabled) 115 | { 116 | NRF_GPIOTE->INTENCLR = GPIOTE_INTENCLR_IN0_Clear << (GPIOTE_INTENCLR_IN0_Pos + i); 117 | 118 | NRF_GPIOTE->CONFIG[i] = (NRF_GPIOTE->CONFIG[i] & ~GPIOTE_CONFIG_MODE_Msk) | (GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos); 119 | 120 | m_drv_gpio.gpiote.pin_msk &= ~(1UL << pin_no); 121 | --m_drv_gpio.gpiote.cnt; 122 | 123 | return true; 124 | } 125 | } 126 | } 127 | 128 | return false; 129 | } 130 | 131 | 132 | /**@brief Gets the index of the GPIOTE instance associated with the specified pin. 133 | * 134 | * @param pin_no The pin number of the pin to get the instance index for. 135 | * 136 | * @return The index of the GPIOTE instance associated with the specified pin, or 137 | * DRV_GPIO_NR_OF_GPIOTE_INSTANCES if there was no GPIOTE instance associated with the specified pin. */ 138 | static __INLINE uint8_t gpiote_instance_idx_get(uint8_t pin_no) 139 | { 140 | uint8_t i; 141 | 142 | for (i = 0; i < DRV_GPIO_NR_OF_GPIOTE_INSTANCES; i++) 143 | { 144 | if ((((NRF_GPIOTE->CONFIG[i] & GPIOTE_CONFIG_PSEL_Msk) >> GPIOTE_CONFIG_PSEL_Pos) == pin_no) 145 | && ((m_drv_gpio.gpiote.pin_msk & (1UL << pin_no)) != 0)) 146 | { 147 | return i; 148 | } 149 | } 150 | 151 | return i; 152 | } 153 | 154 | 155 | /**@brief Enables the interrupt(s) specified by the mask. 156 | * 157 | * @param inten_msk The mask specifying what interrupts to be enabled. */ 158 | static __INLINE void gpiote_intenset(uint32_t inten_msk) 159 | { 160 | if (NRF_GPIOTE->INTENSET == 0) 161 | { 162 | NVIC_EnableIRQ(GPIOTE_IRQn); 163 | } 164 | 165 | NRF_GPIOTE->INTENSET = inten_msk; 166 | } 167 | 168 | 169 | /**@brief Modifies the specified logical levels of the specified GPIOTE pins. 170 | * 171 | * @param high_msk The pins to be set to logical high value. 172 | * @param low_msk The pins to be cleared to logical low value. */ 173 | static void gpiote_outport_modify(uint32_t high_msk, uint32_t low_msk) 174 | { 175 | uint32_t high_msk_gpiote = high_msk & m_drv_gpio.gpiote.pin_msk; 176 | uint32_t low_msk_gpiote = low_msk & m_drv_gpio.gpiote.pin_msk; 177 | uint32_t tmp_u32 = high_msk_gpiote | low_msk_gpiote; 178 | 179 | if ((high_msk_gpiote & low_msk_gpiote) == 0) 180 | { 181 | uint8_t i = 0; 182 | 183 | while (tmp_u32 > 0) 184 | { 185 | if ((tmp_u32 & 1) != 0) 186 | { 187 | uint8_t idx = gpiote_instance_idx_get(i); 188 | 189 | if ((high_msk_gpiote & (1UL << i)) != 0) 190 | { 191 | NRF_GPIOTE->TASKS_SET[idx] = 1; 192 | } 193 | if ((low_msk_gpiote & (1UL << i)) != 0) 194 | { 195 | NRF_GPIOTE->TASKS_CLR[idx] = 1; 196 | } 197 | } 198 | 199 | tmp_u32 >>= 1; 200 | ++i; 201 | } 202 | } 203 | } 204 | 205 | 206 | void drv_gpio_sig_handler_set(drv_gpio_sig_handler_t sig_handler) 207 | { 208 | m_drv_gpio.sig_handler = sig_handler; 209 | } 210 | 211 | 212 | uint32_t drv_gpio_inpin_cfg(uint8_t pin, drv_gpio_inpin_cfg_t cfg, uint32_t ** p_event) 213 | { 214 | if (pin >= DRV_GPIO_NR_OF_PINS) 215 | { 216 | return NRF_ERROR_INVALID_PARAM; 217 | } 218 | 219 | if (cfg.gpiote == DRV_GPIO_GPIOTE_ENABLE) 220 | { 221 | if (gpiote_pin_acquire(pin)) 222 | { 223 | uint8_t const idx = gpiote_instance_idx_get(pin); 224 | 225 | m_drv_gpio.gpio_states[pin].handler_enable = cfg.handler; 226 | 227 | NRF_GPIO->PIN_CNF[pin] = 228 | ( 229 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | 230 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | 231 | (cfg.pull << GPIO_PIN_CNF_PULL_Pos) 232 | ); 233 | 234 | NRF_GPIOTE->CONFIG[idx] = 235 | ( 236 | (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) | 237 | (pin << GPIOTE_CONFIG_PSEL_Pos) | 238 | (cfg.sense << GPIOTE_CONFIG_POLARITY_Pos) 239 | ); 240 | 241 | /* Return the address of the HW event if the storage pointer has been configured. */ 242 | if (p_event != DRV_GPIO_NO_PARAM_PTR) 243 | { 244 | *p_event = (uint32_t *)&(NRF_GPIOTE->EVENTS_IN[idx]); 245 | } 246 | 247 | if (cfg.handler == DRV_GPIO_HANDLER_ENABLE) 248 | { 249 | gpiote_intenset(GPIOTE_INTENSET_IN0_Set << (GPIOTE_INTENSET_IN0_Pos + idx)); 250 | } 251 | } 252 | else 253 | { 254 | return NRF_ERROR_NOT_FOUND; 255 | } 256 | } 257 | else 258 | { 259 | (void)gpiote_pin_release(pin); 260 | 261 | m_drv_gpio.gpio_states[pin].current_sense = cfg.sense; 262 | m_drv_gpio.gpio_states[pin].handler_enable = cfg.handler; 263 | 264 | NRF_GPIO->PIN_CNF[pin] = 265 | ( 266 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | 267 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | 268 | (cfg.pull << GPIO_PIN_CNF_PULL_Pos) 269 | ); 270 | 271 | if (cfg.sense != DRV_GPIO_SENSE_NONE) 272 | { 273 | uint8_t level; 274 | 275 | /* Read the initial logical level of the pin, or decide depending on the pull-resistor direction. */ 276 | if (cfg.pull == DRV_GPIO_PULL_NONE) 277 | { 278 | drv_gpio_inpin_get(pin, &level); 279 | } 280 | else 281 | { 282 | level = (cfg.pull == DRV_GPIO_PULL_UP) ? DRV_GPIO_LEVEL_HIGH : DRV_GPIO_LEVEL_LOW; 283 | } 284 | 285 | /* Enable the latch and clear the status. */ 286 | NRF_GPIO->DETECTMODE = GPIO_DETECTMODE_DETECTMODE_LDETECT << GPIO_DETECTMODE_DETECTMODE_Pos; 287 | NRF_GPIO->LATCH = (1UL << pin); 288 | 289 | /* Configure the sense feature. */ 290 | if (level == DRV_GPIO_LEVEL_LOW) 291 | { 292 | NRF_GPIO->PIN_CNF[pin] |= GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos; 293 | } 294 | else 295 | { 296 | NRF_GPIO->PIN_CNF[pin] |= GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos; 297 | } 298 | 299 | /* Enable the interrupt if requested. */ 300 | if (cfg.handler == DRV_GPIO_HANDLER_ENABLE) 301 | { 302 | gpiote_intenset(GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); 303 | } 304 | } 305 | } 306 | 307 | return NRF_SUCCESS; 308 | } 309 | 310 | 311 | uint32_t drv_gpio_inpins_cfg(uint32_t pin_msk, drv_gpio_inpin_cfg_t cfg, uint32_t ** p_event_arr) 312 | { 313 | uint32_t tmp_u32 = pin_msk; 314 | uint8_t i = 0; 315 | uint8_t n = 0; 316 | 317 | while (tmp_u32 > 0) 318 | { 319 | /* Configure each pin specified by the pin mask. */ 320 | if ((tmp_u32 & 1) != 0) 321 | { 322 | uint32_t ret_val = (p_event_arr == DRV_GPIO_NO_PARAM_PTR) ? drv_gpio_inpin_cfg(i, cfg, DRV_GPIO_NO_PARAM_PTR) : drv_gpio_inpin_cfg(i, cfg, &(p_event_arr[n])); 323 | 324 | /* Abort with error code if configuration fails. */ 325 | if (ret_val != NRF_SUCCESS) 326 | { 327 | return ret_val; 328 | } 329 | ++n; 330 | } 331 | 332 | tmp_u32 >>= 1; 333 | ++i; 334 | } 335 | 336 | return NRF_SUCCESS; 337 | } 338 | 339 | 340 | uint32_t drv_gpio_outpin_cfg(uint8_t pin, drv_gpio_outpin_cfg_t cfg, uint32_t ** p_task) 341 | { 342 | if (pin >= DRV_GPIO_NR_OF_PINS) 343 | { 344 | return NRF_ERROR_INVALID_PARAM; 345 | } 346 | 347 | if (cfg.gpiote == DRV_GPIO_GPIOTE_ENABLE) 348 | { 349 | if (gpiote_pin_acquire(pin)) 350 | { 351 | uint8_t const idx = gpiote_instance_idx_get(pin); 352 | uint32_t config = 353 | ( 354 | (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) | 355 | (pin << GPIOTE_CONFIG_PSEL_Pos) | 356 | (cfg.level << GPIOTE_CONFIG_OUTINIT_Pos) 357 | ); 358 | 359 | /* Return the address of the HW task if the storage pointer has been configured. */ 360 | if (p_task != DRV_GPIO_NO_PARAM_PTR) 361 | { 362 | uint32_t *p_task_addr = NULL; 363 | 364 | switch (cfg.task) 365 | { 366 | case DRV_GPIO_TASK_CLEAR: 367 | p_task_addr = (uint32_t *)&(NRF_GPIOTE->TASKS_CLR[idx]); 368 | break; 369 | case DRV_GPIO_TASK_SET: 370 | p_task_addr = (uint32_t *)&(NRF_GPIOTE->TASKS_SET[idx]); 371 | break; 372 | case DRV_GPIO_TASK_TOGGLE: 373 | config |= GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos; 374 | p_task_addr = (uint32_t *)&(NRF_GPIOTE->TASKS_OUT[idx]); 375 | break; 376 | } 377 | 378 | *p_task = p_task_addr; 379 | } 380 | 381 | NRF_GPIOTE->CONFIG[idx] = config; 382 | } 383 | else 384 | { 385 | return NRF_ERROR_NOT_FOUND; 386 | } 387 | } 388 | else 389 | { 390 | (void)gpiote_pin_release(pin); 391 | 392 | NRF_GPIO->PIN_CNF[pin] = 393 | ( 394 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | 395 | (cfg.drive << GPIO_PIN_CNF_DRIVE_Pos) 396 | ); 397 | } 398 | 399 | return NRF_SUCCESS; 400 | } 401 | 402 | 403 | uint32_t drv_gpio_outpins_cfg(uint32_t pin_msk, drv_gpio_outpin_cfg_t cfg, uint32_t ** p_task_arr) 404 | { 405 | uint32_t tmp_u32 = pin_msk; 406 | uint8_t i = 0; 407 | uint8_t n = 0; 408 | 409 | while (tmp_u32 > 0) 410 | { 411 | /* Configure each pin specified by the pin mask. */ 412 | if ((tmp_u32 & 1) != 0) 413 | { 414 | uint32_t ret_val = (p_task_arr == DRV_GPIO_NO_PARAM_PTR) ? drv_gpio_outpin_cfg(i, cfg, DRV_GPIO_NO_PARAM_PTR) : drv_gpio_outpin_cfg(i, cfg, &(p_task_arr[n])); 415 | 416 | /* Abort with error code if configuration fails. */ 417 | if (ret_val != NRF_SUCCESS) 418 | { 419 | return ret_val; 420 | } 421 | ++n; 422 | } 423 | 424 | tmp_u32 >>= 1; 425 | ++i; 426 | } 427 | 428 | return NRF_SUCCESS; 429 | } 430 | 431 | 432 | uint32_t drv_gpio_pin_disconnect(uint8_t pin) 433 | { 434 | if (pin >= DRV_GPIO_NR_OF_PINS) 435 | { 436 | return NRF_ERROR_INVALID_PARAM; 437 | } 438 | 439 | (void)gpiote_pin_release(pin); 440 | 441 | NRF_GPIO->PIN_CNF[pin] = 442 | ( 443 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | 444 | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) 445 | ); 446 | 447 | return NRF_SUCCESS; 448 | } 449 | 450 | 451 | uint32_t drv_gpio_pins_disconnect(uint32_t pin_msk) 452 | { 453 | uint32_t tmp_u32 = pin_msk; 454 | uint8_t i = 0; 455 | 456 | if (pin_msk == 0) 457 | { 458 | return NRF_ERROR_INVALID_PARAM; 459 | } 460 | 461 | while (tmp_u32 > 0) 462 | { 463 | /* Disconnect each pin specified by the pin mask. */ 464 | if ((tmp_u32 & 1) != 0) 465 | { 466 | (void)drv_gpio_pin_disconnect(i); 467 | } 468 | 469 | tmp_u32 >>= 1; 470 | ++i; 471 | } 472 | 473 | return NRF_SUCCESS; 474 | } 475 | 476 | 477 | uint32_t drv_gpio_inpin_get(uint8_t pin, uint8_t *p_level) 478 | { 479 | if ((pin >= DRV_GPIO_NR_OF_PINS) 480 | && (p_level == DRV_GPIO_NO_PARAM_PTR)) 481 | { 482 | return NRF_ERROR_INVALID_PARAM; 483 | } 484 | 485 | *p_level = ((NRF_GPIO->IN & (1UL << pin)) != 0) ? 1 : 0; 486 | 487 | return NRF_SUCCESS; 488 | } 489 | 490 | 491 | uint32_t drv_gpio_inport_get(void) 492 | { 493 | return NRF_GPIO->IN; 494 | } 495 | 496 | 497 | uint32_t drv_gpio_outpin_level_set(uint8_t pin, uint8_t level) 498 | { 499 | uint32_t const pin_msk = (1UL << pin); 500 | 501 | if ((pin >= DRV_GPIO_NR_OF_PINS) 502 | || (level > DRV_GPIO_LEVEL_HIGH)) 503 | { 504 | return NRF_ERROR_INVALID_PARAM; 505 | } 506 | 507 | if ((pin_msk & m_drv_gpio.gpiote.pin_msk) != 0) 508 | { 509 | if (level == DRV_GPIO_LEVEL_LOW) 510 | { 511 | gpiote_outport_modify(M_NO_PIN_MSK, pin_msk); 512 | } 513 | else 514 | { 515 | gpiote_outport_modify(pin_msk, M_NO_PIN_MSK); 516 | } 517 | } 518 | else 519 | { 520 | if (level == DRV_GPIO_LEVEL_LOW) 521 | { 522 | NRF_GPIO->OUTCLR = pin_msk; 523 | } 524 | else 525 | { 526 | NRF_GPIO->OUTSET = pin_msk; 527 | } 528 | } 529 | 530 | return NRF_SUCCESS; 531 | } 532 | 533 | 534 | uint32_t drv_gpio_outport_modify(uint32_t high_msk, uint32_t low_msk) 535 | { 536 | if ((high_msk & low_msk) != 0) 537 | { 538 | return NRF_ERROR_INVALID_PARAM; 539 | } 540 | 541 | gpiote_outport_modify(high_msk, low_msk); 542 | 543 | NRF_GPIO->OUTSET = high_msk & ~m_drv_gpio.gpiote.pin_msk; 544 | NRF_GPIO->OUTCLR = low_msk & ~m_drv_gpio.gpiote.pin_msk; 545 | 546 | return NRF_SUCCESS; 547 | } 548 | 549 | 550 | void drv_gpio_outport_toggle(uint32_t toggle_msk) 551 | { 552 | if (toggle_msk != 0) 553 | { 554 | uint32_t set_bits = (toggle_msk ^ NRF_GPIO->IN) & toggle_msk; 555 | uint32_t clr_bits = ~set_bits & toggle_msk; 556 | uint32_t set_bits_gpio = set_bits & ~m_drv_gpio.gpiote.pin_msk; 557 | uint32_t clr_bits_gpio = clr_bits & ~m_drv_gpio.gpiote.pin_msk; 558 | uint32_t set_bits_gpiote = set_bits & m_drv_gpio.gpiote.pin_msk; 559 | uint32_t clr_bits_gpiote = clr_bits & m_drv_gpio.gpiote.pin_msk; 560 | 561 | /* Modify the logical level of the GPIOTE pins if there are any. */ 562 | if ((set_bits_gpiote | clr_bits_gpiote) != 0) 563 | { 564 | gpiote_outport_modify(set_bits_gpiote, clr_bits_gpiote); 565 | } 566 | 567 | /* Modify the logical level of the GPIO pins if there are any. */ 568 | if ((set_bits_gpio | clr_bits_gpio) != 0) 569 | { 570 | NRF_GPIO->OUTSET = set_bits_gpio; 571 | NRF_GPIO->OUTCLR = clr_bits_gpio; 572 | } 573 | } 574 | } 575 | 576 | 577 | void drv_gpio_outport_set(uint32_t outport) 578 | { 579 | if (m_drv_gpio.gpiote.pin_msk == 0) 580 | { 581 | NRF_GPIO->OUT = outport; 582 | } 583 | else 584 | { 585 | drv_gpio_outport_modify(outport, ~outport); 586 | } 587 | } 588 | 589 | 590 | static void m_pin_event_report(uint8_t pin, uint8_t sense_edge) 591 | { 592 | /* Report event is the handler is available and enabled for the specified pin. */ 593 | if ((m_drv_gpio.gpio_states[pin].handler_enable == DRV_GPIO_HANDLER_ENABLE) 594 | && (m_drv_gpio.sig_handler != DRV_GPIO_NO_SIG_HANDLER)) 595 | { 596 | m_drv_gpio.sig_handler(pin, sense_edge); 597 | } 598 | } 599 | 600 | 601 | void GPIOTE_IRQHandler(void) 602 | { 603 | for (uint_fast8_t i = 0; i < DRV_GPIO_NR_OF_GPIOTE_INSTANCES; ++i) 604 | { 605 | /* Handle the event if it is set and the interrupt is enabled. */ 606 | if ((NRF_GPIOTE->EVENTS_IN[i] != 0) 607 | && ((NRF_GPIOTE->INTENSET & (GPIOTE_INTENSET_IN0_Set << (GPIOTE_INTENSET_IN0_Pos + i))) != 0)) 608 | { 609 | uint8_t const pin = (NRF_GPIOTE->CONFIG[i] & GPIOTE_CONFIG_PSEL_Msk) >> GPIOTE_CONFIG_PSEL_Pos; 610 | uint8_t const sensed_edge = (NRF_GPIOTE->CONFIG[i] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos; 611 | 612 | NRF_GPIOTE->EVENTS_IN[i] = 0; 613 | (void)NRF_GPIOTE->EVENTS_IN[i]; 614 | 615 | m_pin_event_report(pin, sensed_edge); 616 | } 617 | } 618 | 619 | while (NRF_GPIOTE->EVENTS_PORT != 0) 620 | { 621 | for (uint_fast8_t i = 0; i < DRV_GPIO_NR_OF_PINS; ++i) 622 | { 623 | /* Handle the event if sense is enabled and the latch is set. */ 624 | if ((m_drv_gpio.gpio_states[i].current_sense != DRV_GPIO_SENSE_NONE) 625 | && ((NRF_GPIO->LATCH & (1UL << i)) != 0)) 626 | { 627 | uint8_t const sense_level_at_entry = (((NRF_GPIO->PIN_CNF[i] & GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos) == GPIO_PIN_CNF_SENSE_High) ? DRV_GPIO_LEVEL_HIGH : DRV_GPIO_LEVEL_LOW; 628 | uint8_t const current_pin_sense = m_drv_gpio.gpio_states[i].current_sense; 629 | uint32_t pin_cnf; 630 | 631 | /* Set the new sense level (rapid changes on the input are filtered out). */ 632 | do 633 | { 634 | pin_cnf = NRF_GPIO->PIN_CNF[i]; 635 | NRF_GPIO->PIN_CNF[i] = (pin_cnf & ~GPIO_PIN_CNF_SENSE_Msk) 636 | | (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); 637 | if ( ((pin_cnf & GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos) == GPIO_PIN_CNF_SENSE_Low ) 638 | { 639 | pin_cnf = (pin_cnf & ~GPIO_PIN_CNF_SENSE_Msk) 640 | | (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos); 641 | } 642 | else 643 | { 644 | pin_cnf = (pin_cnf & ~GPIO_PIN_CNF_SENSE_Msk) 645 | | (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos); 646 | } 647 | NRF_GPIO->LATCH = 1UL << i; 648 | while ( (NRF_GPIO->LATCH & (1UL << i)) != 0 ); 649 | NRF_GPIO->PIN_CNF[i] = pin_cnf; 650 | } 651 | while ((NRF_GPIO->LATCH & (1UL << i)) != 0); 652 | 653 | NRF_GPIOTE->EVENTS_PORT = 0; 654 | (void)NRF_GPIOTE->EVENTS_PORT; 655 | 656 | /* Report an event if the detected edge is equal to the configured edge. */ 657 | if (((current_pin_sense == DRV_GPIO_SENSE_LOTOHI) || 658 | (current_pin_sense == DRV_GPIO_SENSE_ANY)) 659 | && (sense_level_at_entry == DRV_GPIO_LEVEL_HIGH)) 660 | { 661 | m_pin_event_report(i, DRV_GPIO_SENSE_LOTOHI); 662 | } 663 | else if (((current_pin_sense == DRV_GPIO_SENSE_HITOLO) || 664 | (current_pin_sense == DRV_GPIO_SENSE_ANY)) 665 | && (sense_level_at_entry == DRV_GPIO_LEVEL_LOW)) 666 | { 667 | m_pin_event_report(i, DRV_GPIO_SENSE_HITOLO); 668 | } 669 | } 670 | } 671 | } 672 | } 673 | --------------------------------------------------------------------------------