├── .gitignore ├── README.md └── tests ├── README.md ├── example_test_script.py ├── test_ctrlap_protection_enabled ├── README.md ├── hex │ └── test_ctrlap_protection_enabled.hex └── src │ ├── JLinkSettings.ini │ ├── RTE │ ├── Device │ │ └── nRF52832_xxAA │ │ │ ├── arm_startup_nrf52.s │ │ │ └── system_nrf52.c │ └── RTE_Components.h │ ├── main.c │ └── test_uicr_write.uvprojx └── test_uicr_write ├── README.md ├── hex └── test_uicr_write.hex └── src ├── JLinkSettings.ini ├── RTE ├── Device │ └── nRF52832_xxAA │ │ ├── arm_startup_nrf52.s │ │ └── system_nrf52.c └── RTE_Components.h ├── main.c └── test_uicr_write.uvprojx /.gitignore: -------------------------------------------------------------------------------- 1 | # Keil uVision specific ignores. 2 | Listings/ 3 | Objects/ 4 | JLinkLog.txt 5 | *.uvguix.* 6 | *.uvoptx 7 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # nrf52-production-programming 2 | A guide to programming nRF52 series devices in production, along with test cases to verify implementation. The white paper on production programming has been moved to Nordic's Infocenter [here](https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.whitepapers/dita/whitepapers/nwp_027/intro.html?cp=11_0). 3 | 4 | ## Test cases 5 | * Provided tests in this repository will help verify that your programming algorithms cover important edge cases (not complete test coverage by any means). They are intended to help you catch the most common mistakes when programming nRF5 devices in production. They will be added over time. 6 | 7 | ## Feel free to open issues and ask questions here, or at [Nordic's devzone](https://devzone.nordicsemi.com/questions/). 8 | -------------------------------------------------------------------------------- /tests/README.md: -------------------------------------------------------------------------------- 1 | # Testing your programming tool 2 | Each folder in this directory contains a specific unit test. The tests provided so far are common and important edge cases that tool manufacturers need to consider when working with nRF52 series devices. Each test folder contains a description of the test and how to run it, along with the hex file (required to run the test) and source code (to understand what's going on). 3 | 4 | # example_test_script.py 5 | This demonstrates how to test your tool. It uses [pynrfjprog](https://pypi.python.org/pypi/pynrfjprog/8.4.0) to test [nrfjprog.exe](https://www.nordicsemi.com/eng/nordic/Products/nRF51822/nRF5x-Command-Line-Tools-Win32/33444) (a programming tool provided by Nordic). 6 | 7 | To run: 8 | > pip install pynrfjprog 9 | > make sure nrfjprog.exe is installed and in your system path 10 | > python example_test_script.py 11 | -------------------------------------------------------------------------------- /tests/example_test_script.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016, Nordic Semiconductor 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of Nordic Semiconductor ASA nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | """ 30 | Example demonstrating programming tool (in this case nrfjprog.exe) verification running tests provided in nrf52-production-programming/tests/. 31 | 32 | """ 33 | 34 | import subprocess 35 | import sys 36 | import unittest 37 | 38 | from pynrfjprog import API 39 | 40 | 41 | class TestProgrammingTool(unittest.TestCase): 42 | """ 43 | This class will run each unit test for the specific programming tool. 44 | 45 | """ 46 | 47 | @classmethod 48 | def setUpClass(cls): 49 | cls.api = setup_api() 50 | 51 | @classmethod 52 | def tearDownClass(cls): 53 | cleanup_api(cls.api) 54 | 55 | def setUp(self): 56 | self.api.recover() 57 | 58 | def tearDown(self): 59 | pass 60 | 61 | def test_uicr_write(self): 62 | run_exe(['-f', 'NRF52', '--program', 'test_uicr_write/hex/test_uicr_write.hex']) 63 | self.api.sys_reset() 64 | 65 | assert(self.api.read_u32(0x10001080) == 0xDEADBEEF) 66 | 67 | def test_ctrlap_protection_enabled(self): 68 | run_exe(['-f', 'NRF52', '--program', 'test_ctrlap_protection_enabled/hex/test_ctrlap_protection_enabled.hex']) 69 | self.api.sys_reset() 70 | 71 | self.api.recover() 72 | assert(self.api.read_u32(0x0) == 0xFFFFFFFF) 73 | 74 | 75 | def run_exe(cmd): 76 | """ 77 | Run nrfjprog with the given commands. 78 | 79 | :param list cmd: Commands to run nrfjprog with. 80 | """ 81 | command = [] 82 | command.append('nrfjprog') 83 | command.extend(cmd) 84 | return subprocess.call(command, stdout=subprocess.PIPE, stderr=subprocess.PIPE) 85 | 86 | def setup_api(): 87 | """ 88 | Initialize api and connect to the target device. 89 | 90 | :return Object api: Instance of API that is initialized and connected to the target device, ready to be used. 91 | """ 92 | api = API.API('NRF52') # TODO: Should not be hard coded. 93 | api.open() 94 | api.connect_to_emu_without_snr() # TODO: Should have the option for snr. 95 | return api 96 | 97 | def cleanup_api(api): 98 | api.disconnect_from_emu() 99 | api.close() 100 | api = None 101 | 102 | 103 | if __name__ == '__main__': 104 | """ 105 | Run the tests with specified options. 106 | 107 | """ 108 | unittest.main(verbosity = 2) # TODO: Run tests in a way where specific Test Cases can be run or the entire suite. 109 | -------------------------------------------------------------------------------- /tests/test_ctrlap_protection_enabled/README.md: -------------------------------------------------------------------------------- 1 | # Running this test 2 | 1. Flash hex/test_ctrlap_protection.hex to device using your programming tool. 3 | 2. Reset the device. Now [Access Port Protection](https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.0/dif.html?cp=1_3_0_14_1#concept_udr_mns_1s) is enabled on the device and the Debug Access Port (DAP) is completly locked to the outside world. 4 | 3. Try to connect (or do any operation through the DAP of the device) and note that the chip is locked. 5 | 4. Unlock the chip using your programming tool. 6 | 5. Verify operations can now be done through the DAP of the device. 7 | 8 | # Troubleshooting 9 | * Access port protection is not enabled until the correct word in the UICR is written AND the chip is reset. 10 | * Many mistakes happen when devices are being programmed in production. If an incorrect firmware image is flashed to a device, and it locks the device, the programming tool must be able to unlock the device to flash the correct firmware image. Other cases may be protection was enabled too early, etc... 11 | -------------------------------------------------------------------------------- /tests/test_ctrlap_protection_enabled/hex/test_ctrlap_protection_enabled.hex: -------------------------------------------------------------------------------- 1 | :020000040000FA 2 | :1000000068400020A1040000A9040000AB04000027 3 | :10001000AD040000AF040000B104000000000000C7 4 | :10002000000000000000000000000000B304000019 5 | :10003000B504000000000000B7040000B90400008F 6 | :10004000BB040000BB040000BB040000BB040000B4 7 | :10005000BB040000BB040000BB040000BB040000A4 8 | :10006000BB040000BB040000BB040000BB04000094 9 | :10007000BB040000BB040000BB040000BB04000084 10 | :10008000BB040000BB040000BB040000BB04000074 11 | :10009000BB040000BB040000BB040000BB04000064 12 | :1000A000BB040000BB040000BB040000BB04000054 13 | :1000B000BB040000BB0400000000000000000000C2 14 | :1000C000BB040000BB040000BB040000BB04000034 15 | :1000D000BB040000BB040000BB04000000000000E3 16 | :1000E0000000000000000000000000000000000010 17 | :1000F0000000000000000000000000000000000000 18 | :1001000000000000000000000000000000000000EF 19 | :1001100000000000000000000000000000000000DF 20 | :1001200000000000000000000000000000000000CF 21 | :1001300000000000000000000000000000000000BF 22 | :1001400000000000000000000000000000000000AF 23 | :10015000000000000000000000000000000000009F 24 | :10016000000000000000000000000000000000008F 25 | :10017000000000000000000000000000000000007F 26 | :10018000000000000000000000000000000000006F 27 | :10019000000000000000000000000000000000005F 28 | :1001A000000000000000000000000000000000004F 29 | :1001B000000000000000000000000000000000003F 30 | :1001C000000000000000000000000000000000002F 31 | :1001D000000000000000000000000000000000001F 32 | :1001E000000000000000000000000000000000000F 33 | :1001F00000000000000000000000000000000000FF 34 | :1002000000000000000000000000000000000000EE 35 | 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:10035000000000000000000000000000000000009D 56 | :10036000000000000000000000000000000000008D 57 | :10037000000000000000000000000000000000007D 58 | :10038000000000000000000000000000000000006D 59 | :10039000000000000000000000000000000000005D 60 | :1003A000000000000000000000000000000000004D 61 | :1003B000000000000000000000000000000000003D 62 | :1003C000000000000000000000000000000000002D 63 | :1003D000000000000000000000000000000000001D 64 | :1003E000000000000000000000000000000000000D 65 | :1003F00000000000000000000000000000000000FD 66 | :1004000000F002F800F03CF80AA090E8000C8244EA 67 | :100410008344AAF10107DA4501D100F031F8AFF2C7 68 | :10042000090EBAE80F0013F0010F18BFFB1A43F0D2 69 | :10043000010318476C0400008C040000103A24BF2C 70 | :1004400078C878C1FAD8520724BF30C830C144BF39 71 | :1004500004680C607047000000230024002500267B 72 | :10046000103A28BF78C1FBD8520728BF30C148BF17 73 | :100470000B6070471FB500F00DFA1FBD10B510BD21 74 | :1004800000F031F81146FFF7F5FF00F001FA00F037 75 | :100490004FF803B4FFF7F2FF03BC00F057F8000079 76 | :1004A0000948804709480047FEE7FEE7FEE7FEE708 77 | :1004B000FEE7FEE7FEE7FEE7FEE7FEE70448054944 78 | :1004C000054A064B704700006D050000010400005E 79 | :1004D000680000206840002068200020682000207C 80 | :1004E000704770477047754600F02CF8AE4605001F 81 | :1004F0006946534620F00700854618B020B5FFF73F 82 | :10050000DDFFBDE820404FF000064FF000074FF040 83 | :1005100000084FF0000B21F00701AC46ACE8C00921 84 | :10052000ACE8C009ACE8C009ACE8C0098D4670472A 85 | :1005300010B50446AFF300802046BDE81040FFF739 86 | :10054000A8BF00000048704704000020014918209F 87 | :10055000ABBEFEE7260002007047000001480249DA 88 | :10056000086070470090D0030000002010B500F034 89 | :10057000C3F810B157485849486700F0D5F828B17A 90 | :1005800056480068C0F342305549086000F0F6F85C 91 | :1005900028B15448006820F080705249086000F08B 92 | :1005A00005F948B10020504908604FF08041C1F87A 93 | :1005B00010014B49091F086000F022F918B103200F 94 | :1005C00047496431086000F033F968B105204749B4 95 | :1005D000086001204549783108600020434908310E 96 | :1005E00008603F20091F086000F03AF9002855D044 97 | :1005F0003F4800683F4908603D48001D0068091DEC 98 | :1006000008603B4808300068091D086038480C3015 99 | :100610000068091D0860364810300068091D086030 100 | :10062000334814300068091D0860314818300068EC 101 | :100630003049203108602E481C300068091D0860D0 102 | :100640002B4820300068091D0860294824300068C4 103 | :10065000091D0860264828300068091D08602448E4 104 | :100660002C300068091D086021483030006821499D 105 | :10067000403108601E4834300068091D08601C487D 106 | :1006800038300068091D086019483C300068091DB1 107 | :100690000860174840300068091D08601148743828 108 | :1006A000006840F470000F497439086000BF00BF53 109 | :1006B00000BFBFF34F8F00BF00BF00BF00BF00BF30 110 | :1006C00000BFBFF36F8F00BF00BF00BFFFF746FF43 111 | :1006D00010BD00000DF0ADBA00C00740440200108C 112 | :1006E0003C050040FCED00E00C01004010560040CD 113 | :1006F0000404001020C500400A48007806280ED1E6 114 | :100700000848001D007800F00F0040B90548083087 115 | :10071000007800F0F000302801D10120704700205F 116 | :10072000FCE70000E00F00F013480078062820D115 117 | :100730001148001D007800F00F00D0B90E480830B5 118 | :10074000007800F0F000302801D1012070470A48FD 119 | :100750000830007800F0F000402801D10120F5E7D2 120 | :1007600005480830007800F0F000502801D1012041 121 | :10077000ECE70020EAE70000E00F00F00A4800780C 122 | :1007800006280ED10848001D007800F00F0040B97F 123 | :1007900005480830007800F0F000302801D1012031 124 | :1007A00070470020FCE70000E00F00F013480078DD 125 | :1007B000062820D11148001D007800F00F00D0B9A4 126 | :1007C0000E480830007800F0F000302801D10120F8 127 | :1007D00070470A480830007800F0F000402801D146 128 | :1007E0000120F5E705480830007800F0F0005028B7 129 | :1007F00001D10120ECE70020EAE70000E00F00F063 130 | :100800000A48007806280ED10848001D007800F03C 131 | :100810000F0040B905480830007800F0F00030289B 132 | :1008200001D1012070470020FCE70000E00F00F03C 133 | :100830000A48007806280ED10848001D007800F00C 134 | :100840000F0040B905480830007800F0F00030286B 135 | :1008500001D1012070470020FCE70000E00F00F00C 136 | :100860000A48007806280ED10848001D007800F0DC 137 | :100870000F0040B905480830007800F0F00050281B 138 | :1008800001D1012070470020FCE70000E00F00F0DC 139 | :1008900000BFFEE74FF04070E1EE100A7047000025 140 | :1008A000C008000000000020040000003C0400001C 141 | :1008B000C408000004000020644000005804000048 142 | :0408C0000090D003D1 143 | :020000041000EA 144 | :0412080000FFFFFFE5 145 | :0400000500000401F2 146 | :00000001FF 147 | -------------------------------------------------------------------------------- /tests/test_ctrlap_protection_enabled/src/JLinkSettings.ini: -------------------------------------------------------------------------------- 1 | [BREAKPOINTS] 2 | ForceImpTypeAny = 0 3 | ShowInfoWin = 1 4 | EnableFlashBP = 2 5 | BPDuringExecution = 0 6 | [CFI] 7 | CFISize = 0x00 8 | CFIAddr = 0x00 9 | [CPU] 10 | MonModeVTableAddr = 0xFFFFFFFF 11 | MonModeDebug = 0 12 | MaxNumAPs = 0 13 | LowPowerHandlingMode = 0 14 | OverrideMemMap = 0 15 | AllowSimulation = 1 16 | ScriptFile="" 17 | [FLASH] 18 | CacheExcludeSize = 0x00 19 | CacheExcludeAddr = 0x00 20 | MinNumBytesFlashDL = 0 21 | SkipProgOnCRCMatch = 1 22 | VerifyDownload = 1 23 | AllowCaching = 1 24 | EnableFlashDL = 2 25 | Override = 0 26 | Device="ARM7" 27 | [GENERAL] 28 | WorkRAMSize = 0x00 29 | WorkRAMAddr = 0x00 30 | RAMUsageLimit = 0x00 31 | [SWO] 32 | SWOLogFile="" 33 | [MEM] 34 | RdOverrideOrMask = 0x00 35 | RdOverrideAndMask = 0xFFFFFFFF 36 | RdOverrideAddr = 0xFFFFFFFF 37 | WrOverrideOrMask = 0x00 38 | WrOverrideAndMask = 0xFFFFFFFF 39 | WrOverrideAddr = 0xFFFFFFFF 40 | -------------------------------------------------------------------------------- /tests/test_ctrlap_protection_enabled/src/RTE/Device/nRF52832_xxAA/arm_startup_nrf52.s: -------------------------------------------------------------------------------- 1 | ;/* Copyright (c) 2012 ARM LIMITED 2 | ; 3 | ; All rights reserved. 4 | ; Redistribution and use in source and binary forms, with or without 5 | ; modification, are permitted provided that the following conditions are met: 6 | ; - Redistributions of source code must retain the above copyright 7 | ; notice, this list of conditions and the following disclaimer. 8 | ; - Redistributions in binary form must reproduce the above copyright 9 | ; notice, this list of conditions and the following disclaimer in the 10 | ; documentation and/or other materials provided with the distribution. 11 | ; - Neither the name of ARM nor the names of its contributors may be used 12 | ; to endorse or promote products derived from this software without 13 | ; specific prior written permission. 14 | ; * 15 | ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 19 | ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ; POSSIBILITY OF SUCH DAMAGE. 26 | ; ---------------------------------------------------------------------------*/ 27 | 28 | IF :DEF: __STACK_SIZE 29 | Stack_Size EQU __STACK_SIZE 30 | ELSE 31 | Stack_Size EQU 8192 32 | ENDIF 33 | 34 | AREA STACK, NOINIT, READWRITE, ALIGN=3 35 | Stack_Mem SPACE Stack_Size 36 | __initial_sp 37 | 38 | IF :DEF: __HEAP_SIZE 39 | Heap_Size EQU __HEAP_SIZE 40 | ELSE 41 | Heap_Size EQU 8192 42 | ENDIF 43 | 44 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 45 | __heap_base 46 | Heap_Mem SPACE Heap_Size 47 | __heap_limit 48 | 49 | PRESERVE8 50 | THUMB 51 | 52 | ; Vector Table Mapped to Address 0 at Reset 53 | 54 | AREA RESET, DATA, READONLY 55 | EXPORT __Vectors 56 | EXPORT __Vectors_End 57 | EXPORT __Vectors_Size 58 | 59 | __Vectors DCD __initial_sp ; Top of Stack 60 | DCD Reset_Handler 61 | DCD NMI_Handler 62 | DCD HardFault_Handler 63 | DCD MemoryManagement_Handler 64 | DCD BusFault_Handler 65 | DCD UsageFault_Handler 66 | DCD 0 ; Reserved 67 | DCD 0 ; Reserved 68 | DCD 0 ; Reserved 69 | DCD 0 ; Reserved 70 | DCD SVC_Handler 71 | DCD DebugMonitor_Handler 72 | DCD 0 ; Reserved 73 | DCD PendSV_Handler 74 | DCD SysTick_Handler 75 | 76 | ; External Interrupts 77 | DCD POWER_CLOCK_IRQHandler 78 | DCD RADIO_IRQHandler 79 | DCD UARTE0_UART0_IRQHandler 80 | DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 81 | DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 82 | DCD NFCT_IRQHandler 83 | DCD GPIOTE_IRQHandler 84 | DCD SAADC_IRQHandler 85 | DCD TIMER0_IRQHandler 86 | DCD TIMER1_IRQHandler 87 | DCD TIMER2_IRQHandler 88 | DCD RTC0_IRQHandler 89 | DCD TEMP_IRQHandler 90 | DCD RNG_IRQHandler 91 | DCD ECB_IRQHandler 92 | DCD CCM_AAR_IRQHandler 93 | DCD WDT_IRQHandler 94 | DCD RTC1_IRQHandler 95 | DCD QDEC_IRQHandler 96 | DCD COMP_LPCOMP_IRQHandler 97 | DCD SWI0_EGU0_IRQHandler 98 | DCD SWI1_EGU1_IRQHandler 99 | DCD SWI2_EGU2_IRQHandler 100 | DCD SWI3_EGU3_IRQHandler 101 | DCD SWI4_EGU4_IRQHandler 102 | DCD SWI5_EGU5_IRQHandler 103 | DCD TIMER3_IRQHandler 104 | DCD TIMER4_IRQHandler 105 | DCD PWM0_IRQHandler 106 | DCD PDM_IRQHandler 107 | DCD 0 ; Reserved 108 | DCD 0 ; Reserved 109 | DCD MWU_IRQHandler 110 | DCD PWM1_IRQHandler 111 | DCD PWM2_IRQHandler 112 | DCD SPIM2_SPIS2_SPI2_IRQHandler 113 | DCD RTC2_IRQHandler 114 | DCD I2S_IRQHandler 115 | DCD FPU_IRQHandler 116 | DCD 0 ; Reserved 117 | DCD 0 ; Reserved 118 | DCD 0 ; Reserved 119 | DCD 0 ; Reserved 120 | DCD 0 ; Reserved 121 | DCD 0 ; Reserved 122 | DCD 0 ; Reserved 123 | DCD 0 ; Reserved 124 | DCD 0 ; Reserved 125 | DCD 0 ; Reserved 126 | DCD 0 ; Reserved 127 | DCD 0 ; Reserved 128 | DCD 0 ; Reserved 129 | DCD 0 ; Reserved 130 | DCD 0 ; Reserved 131 | DCD 0 ; Reserved 132 | DCD 0 ; Reserved 133 | DCD 0 ; Reserved 134 | DCD 0 ; Reserved 135 | DCD 0 ; Reserved 136 | DCD 0 ; Reserved 137 | DCD 0 ; Reserved 138 | DCD 0 ; Reserved 139 | DCD 0 ; Reserved 140 | DCD 0 ; Reserved 141 | DCD 0 ; Reserved 142 | DCD 0 ; Reserved 143 | DCD 0 ; Reserved 144 | DCD 0 ; Reserved 145 | DCD 0 ; Reserved 146 | DCD 0 ; Reserved 147 | DCD 0 ; Reserved 148 | DCD 0 ; Reserved 149 | DCD 0 ; Reserved 150 | DCD 0 ; Reserved 151 | DCD 0 ; Reserved 152 | DCD 0 ; Reserved 153 | DCD 0 ; Reserved 154 | DCD 0 ; Reserved 155 | DCD 0 ; Reserved 156 | DCD 0 ; Reserved 157 | DCD 0 ; Reserved 158 | DCD 0 ; Reserved 159 | DCD 0 ; Reserved 160 | DCD 0 ; Reserved 161 | DCD 0 ; Reserved 162 | DCD 0 ; Reserved 163 | DCD 0 ; Reserved 164 | DCD 0 ; Reserved 165 | DCD 0 ; Reserved 166 | DCD 0 ; Reserved 167 | DCD 0 ; Reserved 168 | DCD 0 ; Reserved 169 | DCD 0 ; Reserved 170 | DCD 0 ; Reserved 171 | DCD 0 ; Reserved 172 | DCD 0 ; Reserved 173 | DCD 0 ; Reserved 174 | DCD 0 ; Reserved 175 | DCD 0 ; Reserved 176 | DCD 0 ; Reserved 177 | DCD 0 ; Reserved 178 | DCD 0 ; Reserved 179 | DCD 0 ; Reserved 180 | DCD 0 ; Reserved 181 | DCD 0 ; Reserved 182 | DCD 0 ; Reserved 183 | DCD 0 ; Reserved 184 | DCD 0 ; Reserved 185 | DCD 0 ; Reserved 186 | DCD 0 ; Reserved 187 | DCD 0 ; Reserved 188 | DCD 0 ; Reserved 189 | DCD 0 ; Reserved 190 | DCD 0 ; Reserved 191 | DCD 0 ; Reserved 192 | DCD 0 ; Reserved 193 | DCD 0 ; Reserved 194 | DCD 0 ; Reserved 195 | DCD 0 ; Reserved 196 | DCD 0 ; Reserved 197 | DCD 0 ; Reserved 198 | DCD 0 ; Reserved 199 | DCD 0 ; Reserved 200 | DCD 0 ; Reserved 201 | DCD 0 ; Reserved 202 | DCD 0 ; Reserved 203 | DCD 0 ; Reserved 204 | DCD 0 ; Reserved 205 | DCD 0 ; Reserved 206 | DCD 0 ; Reserved 207 | DCD 0 ; Reserved 208 | DCD 0 ; Reserved 209 | DCD 0 ; Reserved 210 | DCD 0 ; Reserved 211 | DCD 0 ; Reserved 212 | DCD 0 ; Reserved 213 | DCD 0 ; Reserved 214 | DCD 0 ; Reserved 215 | DCD 0 ; Reserved 216 | DCD 0 ; Reserved 217 | DCD 0 ; Reserved 218 | DCD 0 ; Reserved 219 | DCD 0 ; Reserved 220 | DCD 0 ; Reserved 221 | DCD 0 ; Reserved 222 | DCD 0 ; Reserved 223 | DCD 0 ; Reserved 224 | DCD 0 ; Reserved 225 | DCD 0 ; Reserved 226 | DCD 0 ; Reserved 227 | DCD 0 ; Reserved 228 | DCD 0 ; Reserved 229 | DCD 0 ; Reserved 230 | DCD 0 ; Reserved 231 | DCD 0 ; Reserved 232 | DCD 0 ; Reserved 233 | DCD 0 ; Reserved 234 | DCD 0 ; Reserved 235 | DCD 0 ; Reserved 236 | DCD 0 ; Reserved 237 | DCD 0 ; Reserved 238 | DCD 0 ; Reserved 239 | DCD 0 ; Reserved 240 | DCD 0 ; Reserved 241 | DCD 0 ; Reserved 242 | DCD 0 ; Reserved 243 | DCD 0 ; Reserved 244 | DCD 0 ; Reserved 245 | DCD 0 ; Reserved 246 | DCD 0 ; Reserved 247 | DCD 0 ; Reserved 248 | DCD 0 ; Reserved 249 | DCD 0 ; Reserved 250 | DCD 0 ; Reserved 251 | DCD 0 ; Reserved 252 | DCD 0 ; Reserved 253 | DCD 0 ; Reserved 254 | DCD 0 ; Reserved 255 | DCD 0 ; Reserved 256 | DCD 0 ; Reserved 257 | DCD 0 ; Reserved 258 | DCD 0 ; Reserved 259 | DCD 0 ; Reserved 260 | DCD 0 ; Reserved 261 | DCD 0 ; Reserved 262 | DCD 0 ; Reserved 263 | DCD 0 ; Reserved 264 | DCD 0 ; Reserved 265 | DCD 0 ; Reserved 266 | DCD 0 ; Reserved 267 | DCD 0 ; Reserved 268 | DCD 0 ; Reserved 269 | DCD 0 ; Reserved 270 | DCD 0 ; Reserved 271 | DCD 0 ; Reserved 272 | DCD 0 ; Reserved 273 | DCD 0 ; Reserved 274 | DCD 0 ; Reserved 275 | DCD 0 ; Reserved 276 | DCD 0 ; Reserved 277 | DCD 0 ; Reserved 278 | DCD 0 ; Reserved 279 | DCD 0 ; Reserved 280 | DCD 0 ; Reserved 281 | DCD 0 ; Reserved 282 | DCD 0 ; Reserved 283 | DCD 0 ; Reserved 284 | DCD 0 ; Reserved 285 | DCD 0 ; Reserved 286 | DCD 0 ; Reserved 287 | DCD 0 ; Reserved 288 | DCD 0 ; Reserved 289 | DCD 0 ; Reserved 290 | DCD 0 ; Reserved 291 | DCD 0 ; Reserved 292 | DCD 0 ; Reserved 293 | DCD 0 ; Reserved 294 | DCD 0 ; Reserved 295 | DCD 0 ; Reserved 296 | DCD 0 ; Reserved 297 | DCD 0 ; Reserved 298 | DCD 0 ; Reserved 299 | DCD 0 ; Reserved 300 | DCD 0 ; Reserved 301 | DCD 0 ; Reserved 302 | DCD 0 ; Reserved 303 | DCD 0 ; Reserved 304 | DCD 0 ; Reserved 305 | DCD 0 ; Reserved 306 | DCD 0 ; Reserved 307 | DCD 0 ; Reserved 308 | DCD 0 ; Reserved 309 | DCD 0 ; Reserved 310 | DCD 0 ; Reserved 311 | DCD 0 ; Reserved 312 | DCD 0 ; Reserved 313 | DCD 0 ; Reserved 314 | DCD 0 ; Reserved 315 | DCD 0 ; Reserved 316 | DCD 0 ; Reserved 317 | 318 | __Vectors_End 319 | 320 | __Vectors_Size EQU __Vectors_End - __Vectors 321 | 322 | AREA |.text|, CODE, READONLY 323 | 324 | ; Reset Handler 325 | 326 | 327 | Reset_Handler PROC 328 | EXPORT Reset_Handler [WEAK] 329 | IMPORT SystemInit 330 | IMPORT __main 331 | 332 | 333 | LDR R0, =SystemInit 334 | BLX R0 335 | LDR R0, =__main 336 | BX R0 337 | ENDP 338 | 339 | ; Dummy Exception Handlers (infinite loops which can be modified) 340 | 341 | NMI_Handler PROC 342 | EXPORT NMI_Handler [WEAK] 343 | B . 344 | ENDP 345 | HardFault_Handler\ 346 | PROC 347 | EXPORT HardFault_Handler [WEAK] 348 | B . 349 | ENDP 350 | MemoryManagement_Handler\ 351 | PROC 352 | EXPORT MemoryManagement_Handler [WEAK] 353 | B . 354 | ENDP 355 | BusFault_Handler\ 356 | PROC 357 | EXPORT BusFault_Handler [WEAK] 358 | B . 359 | ENDP 360 | UsageFault_Handler\ 361 | PROC 362 | EXPORT UsageFault_Handler [WEAK] 363 | B . 364 | ENDP 365 | SVC_Handler PROC 366 | EXPORT SVC_Handler [WEAK] 367 | B . 368 | ENDP 369 | DebugMonitor_Handler\ 370 | PROC 371 | EXPORT DebugMonitor_Handler [WEAK] 372 | B . 373 | ENDP 374 | PendSV_Handler PROC 375 | EXPORT PendSV_Handler [WEAK] 376 | B . 377 | ENDP 378 | SysTick_Handler PROC 379 | EXPORT SysTick_Handler [WEAK] 380 | B . 381 | ENDP 382 | 383 | Default_Handler PROC 384 | 385 | EXPORT POWER_CLOCK_IRQHandler [WEAK] 386 | EXPORT RADIO_IRQHandler [WEAK] 387 | EXPORT UARTE0_UART0_IRQHandler [WEAK] 388 | EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK] 389 | EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK] 390 | EXPORT NFCT_IRQHandler [WEAK] 391 | EXPORT GPIOTE_IRQHandler [WEAK] 392 | EXPORT SAADC_IRQHandler [WEAK] 393 | EXPORT TIMER0_IRQHandler [WEAK] 394 | EXPORT TIMER1_IRQHandler [WEAK] 395 | EXPORT TIMER2_IRQHandler [WEAK] 396 | EXPORT RTC0_IRQHandler [WEAK] 397 | EXPORT TEMP_IRQHandler [WEAK] 398 | EXPORT RNG_IRQHandler [WEAK] 399 | EXPORT ECB_IRQHandler [WEAK] 400 | EXPORT CCM_AAR_IRQHandler [WEAK] 401 | EXPORT WDT_IRQHandler [WEAK] 402 | EXPORT RTC1_IRQHandler [WEAK] 403 | EXPORT QDEC_IRQHandler [WEAK] 404 | EXPORT COMP_LPCOMP_IRQHandler [WEAK] 405 | EXPORT SWI0_EGU0_IRQHandler [WEAK] 406 | EXPORT SWI1_EGU1_IRQHandler [WEAK] 407 | EXPORT SWI2_EGU2_IRQHandler [WEAK] 408 | EXPORT SWI3_EGU3_IRQHandler [WEAK] 409 | EXPORT SWI4_EGU4_IRQHandler [WEAK] 410 | EXPORT SWI5_EGU5_IRQHandler [WEAK] 411 | EXPORT TIMER3_IRQHandler [WEAK] 412 | EXPORT TIMER4_IRQHandler [WEAK] 413 | EXPORT PWM0_IRQHandler [WEAK] 414 | EXPORT PDM_IRQHandler [WEAK] 415 | EXPORT MWU_IRQHandler [WEAK] 416 | EXPORT PWM1_IRQHandler [WEAK] 417 | EXPORT PWM2_IRQHandler [WEAK] 418 | EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK] 419 | EXPORT RTC2_IRQHandler [WEAK] 420 | EXPORT I2S_IRQHandler [WEAK] 421 | EXPORT FPU_IRQHandler [WEAK] 422 | POWER_CLOCK_IRQHandler 423 | RADIO_IRQHandler 424 | UARTE0_UART0_IRQHandler 425 | SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 426 | SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 427 | NFCT_IRQHandler 428 | GPIOTE_IRQHandler 429 | SAADC_IRQHandler 430 | TIMER0_IRQHandler 431 | TIMER1_IRQHandler 432 | TIMER2_IRQHandler 433 | RTC0_IRQHandler 434 | TEMP_IRQHandler 435 | RNG_IRQHandler 436 | ECB_IRQHandler 437 | CCM_AAR_IRQHandler 438 | WDT_IRQHandler 439 | RTC1_IRQHandler 440 | QDEC_IRQHandler 441 | COMP_LPCOMP_IRQHandler 442 | SWI0_EGU0_IRQHandler 443 | SWI1_EGU1_IRQHandler 444 | SWI2_EGU2_IRQHandler 445 | SWI3_EGU3_IRQHandler 446 | SWI4_EGU4_IRQHandler 447 | SWI5_EGU5_IRQHandler 448 | TIMER3_IRQHandler 449 | TIMER4_IRQHandler 450 | PWM0_IRQHandler 451 | PDM_IRQHandler 452 | MWU_IRQHandler 453 | PWM1_IRQHandler 454 | PWM2_IRQHandler 455 | SPIM2_SPIS2_SPI2_IRQHandler 456 | RTC2_IRQHandler 457 | I2S_IRQHandler 458 | FPU_IRQHandler 459 | B . 460 | ENDP 461 | ALIGN 462 | 463 | ; User Initial Stack & Heap 464 | 465 | IF :DEF:__MICROLIB 466 | 467 | EXPORT __initial_sp 468 | EXPORT __heap_base 469 | EXPORT __heap_limit 470 | 471 | ELSE 472 | 473 | IMPORT __use_two_region_memory 474 | EXPORT __user_initial_stackheap 475 | 476 | __user_initial_stackheap PROC 477 | 478 | LDR R0, = Heap_Mem 479 | LDR R1, = (Stack_Mem + Stack_Size) 480 | LDR R2, = (Heap_Mem + Heap_Size) 481 | LDR R3, = Stack_Mem 482 | BX LR 483 | ENDP 484 | 485 | ALIGN 486 | 487 | ENDIF 488 | 489 | END 490 | -------------------------------------------------------------------------------- /tests/test_ctrlap_protection_enabled/src/RTE/Device/nRF52832_xxAA/system_nrf52.c: -------------------------------------------------------------------------------- 1 | /* Copyright (c) 2015, Nordic Semiconductor ASA 2 | * All rights reserved. 3 | * 4 | * Redistribution and use in source and binary forms, with or without 5 | * modification, are permitted provided that the following conditions are met: 6 | * 7 | * * Redistributions of source code must retain the above copyright notice, this 8 | * list of conditions and the following disclaimer. 9 | * 10 | * * Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * * Neither the name of Nordic Semiconductor ASA nor the names of its 15 | * contributors may be used to endorse or promote products derived from 16 | * this software without specific prior written permission. 17 | * 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | * 29 | */ 30 | 31 | #include 32 | #include 33 | #include "nrf.h" 34 | #include "system_nrf52.h" 35 | 36 | /*lint ++flb "Enter library region" */ 37 | 38 | #define __SYSTEM_CLOCK_64M (64000000UL) 39 | 40 | static bool errata_16(void); 41 | static bool errata_31(void); 42 | static bool errata_32(void); 43 | static bool errata_36(void); 44 | static bool errata_37(void); 45 | static bool errata_57(void); 46 | static bool errata_66(void); 47 | 48 | 49 | #if defined ( __CC_ARM ) 50 | uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; 51 | #elif defined ( __ICCARM__ ) 52 | __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; 53 | #elif defined ( __GNUC__ ) 54 | uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; 55 | #endif 56 | 57 | void SystemCoreClockUpdate(void) 58 | { 59 | SystemCoreClock = __SYSTEM_CLOCK_64M; 60 | } 61 | 62 | void SystemInit(void) 63 | { 64 | /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document 65 | for your device located at https://infocenter.nordicsemi.com/ */ 66 | if (errata_16()){ 67 | *(volatile uint32_t *)0x4007C074 = 3131961357ul; 68 | } 69 | 70 | /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document 71 | for your device located at https://infocenter.nordicsemi.com/ */ 72 | if (errata_31()){ 73 | *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; 74 | } 75 | 76 | /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document 77 | for your device located at https://infocenter.nordicsemi.com/ */ 78 | if (errata_32()){ 79 | CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; 80 | } 81 | 82 | /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document 83 | for your device located at https://infocenter.nordicsemi.com/ */ 84 | if (errata_36()){ 85 | NRF_CLOCK->EVENTS_DONE = 0; 86 | NRF_CLOCK->EVENTS_CTTO = 0; 87 | NRF_CLOCK->CTIV = 0; 88 | } 89 | 90 | /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document 91 | for your device located at https://infocenter.nordicsemi.com/ */ 92 | if (errata_37()){ 93 | *(volatile uint32_t *)0x400005A0 = 0x3; 94 | } 95 | 96 | /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document 97 | for your device located at https://infocenter.nordicsemi.com/ */ 98 | if (errata_57()){ 99 | *(volatile uint32_t *)0x40005610 = 0x00000005; 100 | *(volatile uint32_t *)0x40005688 = 0x00000001; 101 | *(volatile uint32_t *)0x40005618 = 0x00000000; 102 | *(volatile uint32_t *)0x40005614 = 0x0000003F; 103 | } 104 | 105 | /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document 106 | for your device located at https://infocenter.nordicsemi.com/ */ 107 | if (errata_66()){ 108 | NRF_TEMP->A0 = NRF_FICR->TEMP.A0; 109 | NRF_TEMP->A1 = NRF_FICR->TEMP.A1; 110 | NRF_TEMP->A2 = NRF_FICR->TEMP.A2; 111 | NRF_TEMP->A3 = NRF_FICR->TEMP.A3; 112 | NRF_TEMP->A4 = NRF_FICR->TEMP.A4; 113 | NRF_TEMP->A5 = NRF_FICR->TEMP.A5; 114 | NRF_TEMP->B0 = NRF_FICR->TEMP.B0; 115 | NRF_TEMP->B1 = NRF_FICR->TEMP.B1; 116 | NRF_TEMP->B2 = NRF_FICR->TEMP.B2; 117 | NRF_TEMP->B3 = NRF_FICR->TEMP.B3; 118 | NRF_TEMP->B4 = NRF_FICR->TEMP.B4; 119 | NRF_TEMP->B5 = NRF_FICR->TEMP.B5; 120 | NRF_TEMP->T0 = NRF_FICR->TEMP.T0; 121 | NRF_TEMP->T1 = NRF_FICR->TEMP.T1; 122 | NRF_TEMP->T2 = NRF_FICR->TEMP.T2; 123 | NRF_TEMP->T3 = NRF_FICR->TEMP.T3; 124 | NRF_TEMP->T4 = NRF_FICR->TEMP.T4; 125 | } 126 | 127 | /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the 128 | * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit 129 | * operations are not used in your code. */ 130 | #if (__FPU_USED == 1) 131 | SCB->CPACR |= (3UL << 20) | (3UL << 22); 132 | __DSB(); 133 | __ISB(); 134 | #endif 135 | 136 | /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, 137 | two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as 138 | normal GPIOs. */ 139 | #if defined (CONFIG_NFCT_PINS_AS_GPIOS) 140 | if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ 141 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; 142 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 143 | NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; 144 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 145 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; 146 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 147 | NVIC_SystemReset(); 148 | } 149 | #endif 150 | 151 | /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not 152 | defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be 153 | reserved for PinReset and not available as normal GPIO. */ 154 | #if defined (CONFIG_GPIO_AS_PINRESET) 155 | if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || 156 | ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ 157 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; 158 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 159 | NRF_UICR->PSELRESET[0] = 21; 160 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 161 | NRF_UICR->PSELRESET[1] = 21; 162 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 163 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; 164 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 165 | NVIC_SystemReset(); 166 | } 167 | #endif 168 | 169 | /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product 170 | Specification to see which one). */ 171 | #if defined (ENABLE_SWO) 172 | CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 173 | NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; 174 | NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 175 | #endif 176 | 177 | /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product 178 | Specification to see which ones). */ 179 | #if defined (ENABLE_TRACE) 180 | CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 181 | NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; 182 | NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 183 | NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 184 | NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 185 | NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 186 | NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 187 | #endif 188 | 189 | SystemCoreClockUpdate(); 190 | } 191 | 192 | 193 | static bool errata_16(void) 194 | { 195 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 196 | { 197 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 198 | { 199 | return true; 200 | } 201 | } 202 | 203 | return false; 204 | } 205 | 206 | static bool errata_31(void) 207 | { 208 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 209 | { 210 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 211 | { 212 | return true; 213 | } 214 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) 215 | { 216 | return true; 217 | } 218 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) 219 | { 220 | return true; 221 | } 222 | } 223 | 224 | return false; 225 | } 226 | 227 | static bool errata_32(void) 228 | { 229 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 230 | { 231 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 232 | { 233 | return true; 234 | } 235 | } 236 | 237 | return false; 238 | } 239 | 240 | static bool errata_36(void) 241 | { 242 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 243 | { 244 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 245 | { 246 | return true; 247 | } 248 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) 249 | { 250 | return true; 251 | } 252 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) 253 | { 254 | return true; 255 | } 256 | } 257 | 258 | return false; 259 | } 260 | 261 | static bool errata_37(void) 262 | { 263 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 264 | { 265 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 266 | { 267 | return true; 268 | } 269 | } 270 | 271 | return false; 272 | } 273 | 274 | static bool errata_57(void) 275 | { 276 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 277 | { 278 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 279 | { 280 | return true; 281 | } 282 | } 283 | 284 | return false; 285 | } 286 | 287 | static bool errata_66(void) 288 | { 289 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 290 | { 291 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) 292 | { 293 | return true; 294 | } 295 | } 296 | 297 | return false; 298 | } 299 | 300 | 301 | /*lint --flb "Leave library region" */ 302 | -------------------------------------------------------------------------------- /tests/test_ctrlap_protection_enabled/src/RTE/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'test_uicr_write' 7 | * Target: 'nRF52832' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | #endif /* RTE_COMPONENTS_H */ 15 | -------------------------------------------------------------------------------- /tests/test_ctrlap_protection_enabled/src/main.c: -------------------------------------------------------------------------------- 1 | /* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved. 2 | * 3 | * The information contained herein is property of Nordic Semiconductor ASA. 4 | * Terms and conditions of usage are described in detail in NORDIC 5 | * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. 6 | * 7 | * Licensees are granted free, non-transferable use of the information. NO 8 | * WARRANTY of ANY KIND is provided. This heading must NOT be removed from 9 | * the file. 10 | * 11 | */ 12 | /** @test tests/test_ctrlap_protection_enabled/src/main.c 13 | * 14 | * @brief Locks the device (after this hex file is loaded and the device is reset). 15 | * 16 | * This file contains the source code for the test_ctrlap_protection_enabled hex file provided in ../hex/ 17 | * See the corresponding README for expected behavior. 18 | */ 19 | 20 | #include 21 | 22 | #include "nrf.h" 23 | 24 | // Enable Access Port protection on the device (effective after a reset). 25 | const uint32_t UICR_APPROTECT __attribute__((at(0x10001208))) __attribute__((used)) = 0xFFFFFF00; 26 | 27 | /**@brief Function for application main entry. 28 | */ 29 | int main(void) 30 | { 31 | // Enter main loop. 32 | for (;;) 33 | { 34 | // Loop. 35 | } 36 | } 37 | -------------------------------------------------------------------------------- /tests/test_ctrlap_protection_enabled/src/test_uicr_write.uvprojx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2.1 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | 10 | nRF52832 11 | 0x4 12 | ARM-ADS 13 | 5060061::V5.06 update 1 (build 61)::ARMCC 14 | 15 | 16 | nRF52832_xxAA 17 | Nordic Semiconductor 18 | NordicSemiconductor.nRF_DeviceFamilyPack.8.5.0 19 | http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ 20 | IROM(0x00000000,0x80000) IRAM(0x20000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE 21 | 22 | 23 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)) 24 | 0 25 | $$Device:nRF52832_xxAA$Device\Include\nrf.h 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | $$Device:nRF52832_xxAA$SVD\nrf52.svd 36 | 0 37 | 0 38 | 39 | 40 | 41 | 42 | 43 | 44 | 0 45 | 0 46 | 0 47 | 0 48 | 1 49 | 50 | .\Objects\ 51 | test_ctrlap_protection_enabled 52 | 1 53 | 0 54 | 1 55 | 1 56 | 1 57 | .\Listings\ 58 | 1 59 | 0 60 | 0 61 | 62 | 0 63 | 0 64 | 65 | 66 | 0 67 | 0 68 | 0 69 | 0 70 | 71 | 72 | 0 73 | 0 74 | 75 | 76 | 0 77 | 0 78 | 0 79 | 0 80 | 81 | 82 | 0 83 | 0 84 | 85 | 86 | 0 87 | 0 88 | 0 89 | 0 90 | 91 | 0 92 | 93 | 94 | 95 | 0 96 | 0 97 | 0 98 | 0 99 | 0 100 | 1 101 | 0 102 | 0 103 | 0 104 | 0 105 | 3 106 | 107 | 108 | 1 109 | 110 | 111 | SARMCM3.DLL 112 | -MPU 113 | DCM.DLL 114 | -pCM4 115 | SARMCM3.DLL 116 | -MPU 117 | TCM.DLL 118 | -pCM4 119 | 120 | 121 | 122 | 1 123 | 0 124 | 0 125 | 0 126 | 16 127 | 128 | 129 | 0 130 | 1 131 | 1 132 | 1 133 | 1 134 | 1 135 | 1 136 | 1 137 | 0 138 | 1 139 | 140 | 141 | 1 142 | 1 143 | 1 144 | 1 145 | 1 146 | 1 147 | 0 148 | 1 149 | 1 150 | 1 151 | 152 | 0 153 | 6 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | Segger\JL2CM3.dll 168 | 169 | 170 | 171 | 172 | 1 173 | 0 174 | 0 175 | 1 176 | 0 177 | -1 178 | 179 | 1 180 | BIN\UL2CM3.DLL 181 | 182 | 183 | 184 | 185 | 186 | 0 187 | 188 | 189 | 190 | 0 191 | 1 192 | 1 193 | 1 194 | 1 195 | 1 196 | 1 197 | 1 198 | 0 199 | 1 200 | 1 201 | 0 202 | 1 203 | 1 204 | 0 205 | 0 206 | 1 207 | 1 208 | 1 209 | 1 210 | 1 211 | 1 212 | 1 213 | 1 214 | 1 215 | 0 216 | 0 217 | "Cortex-M4" 218 | 219 | 0 220 | 0 221 | 0 222 | 1 223 | 1 224 | 0 225 | 0 226 | 2 227 | 0 228 | 0 229 | 8 230 | 0 231 | 0 232 | 0 233 | 0 234 | 3 235 | 3 236 | 0 237 | 0 238 | 0 239 | 0 240 | 0 241 | 0 242 | 0 243 | 0 244 | 0 245 | 0 246 | 1 247 | 0 248 | 0 249 | 0 250 | 0 251 | 1 252 | 0 253 | 254 | 255 | 0 256 | 0x0 257 | 0x0 258 | 259 | 260 | 0 261 | 0x0 262 | 0x0 263 | 264 | 265 | 0 266 | 0x0 267 | 0x0 268 | 269 | 270 | 0 271 | 0x0 272 | 0x0 273 | 274 | 275 | 0 276 | 0x0 277 | 0x0 278 | 279 | 280 | 0 281 | 0x0 282 | 0x0 283 | 284 | 285 | 0 286 | 0x20000000 287 | 0x10000 288 | 289 | 290 | 1 291 | 0x0 292 | 0x80000 293 | 294 | 295 | 0 296 | 0x0 297 | 0x0 298 | 299 | 300 | 1 301 | 0x0 302 | 0x0 303 | 304 | 305 | 1 306 | 0x0 307 | 0x0 308 | 309 | 310 | 1 311 | 0x0 312 | 0x0 313 | 314 | 315 | 1 316 | 0x0 317 | 0x80000 318 | 319 | 320 | 1 321 | 0x0 322 | 0x0 323 | 324 | 325 | 0 326 | 0x0 327 | 0x0 328 | 329 | 330 | 0 331 | 0x0 332 | 0x0 333 | 334 | 335 | 0 336 | 0x0 337 | 0x0 338 | 339 | 340 | 0 341 | 0x20000000 342 | 0x10000 343 | 344 | 345 | 0 346 | 0x0 347 | 0x0 348 | 349 | 350 | 351 | 352 | 353 | 1 354 | 1 355 | 0 356 | 0 357 | 1 358 | 0 359 | 0 360 | 0 361 | 0 362 | 0 363 | 2 364 | 0 365 | 0 366 | 0 367 | 0 368 | 0 369 | 0 370 | 0 371 | 0 372 | 373 | 374 | NRF52 375 | 376 | 377 | 378 | 379 | 380 | 1 381 | 0 382 | 0 383 | 0 384 | 0 385 | 0 386 | 0 387 | 0 388 | 0 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | 397 | 1 398 | 0 399 | 0 400 | 0 401 | 1 402 | 0 403 | 0x00000000 404 | 0x20000000 405 | 406 | 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | test 418 | 419 | 420 | main.c 421 | 1 422 | .\main.c 423 | 424 | 425 | 426 | 427 | ::CMSIS 428 | 429 | 430 | ::Device 431 | 432 | 433 | 434 | 435 | 436 | 437 | 438 | 439 | 440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | 450 | 451 | 452 | 453 | 454 | RTE\Device\nRF52832_xxAA\arm_startup_nrf52.s 455 | 456 | 457 | 458 | 459 | 460 | 461 | 462 | RTE\Device\nRF52832_xxAA\system_nrf52.c 463 | 464 | 465 | 466 | 467 | 468 | 469 | 470 | 471 | 472 | 473 | -------------------------------------------------------------------------------- /tests/test_uicr_write/README.md: -------------------------------------------------------------------------------- 1 | # Running this test 2 | 1. Flash hex/test_uicr_write.hex to device using your programming tool. 3 | 2. Read address 0x10001080. Verify the read value is 0xDEADBEEF. 4 | 5 | # Troubleshooting 6 | If a different value was read than expected the programming tool did not write the [UICR](https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.0/nvmc.html?cp=1_3_0_9_2#concept_etv_shz_vr) region of memory properly. 7 | -------------------------------------------------------------------------------- /tests/test_uicr_write/hex/test_uicr_write.hex: -------------------------------------------------------------------------------- 1 | :020000040000FA 2 | :1000000068400020A1040000A9040000AB04000027 3 | :10001000AD040000AF040000B104000000000000C7 4 | :10002000000000000000000000000000B304000019 5 | :10003000B504000000000000B7040000B90400008F 6 | :10004000BB040000BB040000BB040000BB040000B4 7 | :10005000BB040000BB040000BB040000BB040000A4 8 | :10006000BB040000BB040000BB040000BB04000094 9 | :10007000BB040000BB040000BB040000BB04000084 10 | :10008000BB040000BB040000BB040000BB04000074 11 | :10009000BB040000BB040000BB040000BB04000064 12 | :1000A000BB040000BB040000BB040000BB04000054 13 | :1000B000BB040000BB0400000000000000000000C2 14 | :1000C000BB040000BB040000BB040000BB04000034 15 | :1000D000BB040000BB040000BB04000000000000E3 16 | :1000E0000000000000000000000000000000000010 17 | :1000F0000000000000000000000000000000000000 18 | :1001000000000000000000000000000000000000EF 19 | :1001100000000000000000000000000000000000DF 20 | :1001200000000000000000000000000000000000CF 21 | :1001300000000000000000000000000000000000BF 22 | :1001400000000000000000000000000000000000AF 23 | :10015000000000000000000000000000000000009F 24 | :10016000000000000000000000000000000000008F 25 | :10017000000000000000000000000000000000007F 26 | :10018000000000000000000000000000000000006F 27 | :10019000000000000000000000000000000000005F 28 | :1001A000000000000000000000000000000000004F 29 | :1001B000000000000000000000000000000000003F 30 | :1001C000000000000000000000000000000000002F 31 | :1001D000000000000000000000000000000000001F 32 | :1001E000000000000000000000000000000000000F 33 | :1001F00000000000000000000000000000000000FF 34 | :1002000000000000000000000000000000000000EE 35 | :1002100000000000000000000000000000000000DE 36 | :1002200000000000000000000000000000000000CE 37 | :1002300000000000000000000000000000000000BE 38 | :1002400000000000000000000000000000000000AE 39 | :10025000000000000000000000000000000000009E 40 | :10026000000000000000000000000000000000008E 41 | :10027000000000000000000000000000000000007E 42 | :10028000000000000000000000000000000000006E 43 | :10029000000000000000000000000000000000005E 44 | :1002A000000000000000000000000000000000004E 45 | :1002B000000000000000000000000000000000003E 46 | :1002C000000000000000000000000000000000002E 47 | :1002D000000000000000000000000000000000001E 48 | :1002E000000000000000000000000000000000000E 49 | :1002F00000000000000000000000000000000000FE 50 | :1003000000000000000000000000000000000000ED 51 | :1003100000000000000000000000000000000000DD 52 | :1003200000000000000000000000000000000000CD 53 | :1003300000000000000000000000000000000000BD 54 | :1003400000000000000000000000000000000000AD 55 | :10035000000000000000000000000000000000009D 56 | :10036000000000000000000000000000000000008D 57 | :10037000000000000000000000000000000000007D 58 | :10038000000000000000000000000000000000006D 59 | :10039000000000000000000000000000000000005D 60 | :1003A000000000000000000000000000000000004D 61 | :1003B000000000000000000000000000000000003D 62 | :1003C000000000000000000000000000000000002D 63 | :1003D000000000000000000000000000000000001D 64 | :1003E000000000000000000000000000000000000D 65 | :1003F00000000000000000000000000000000000FD 66 | :1004000000F002F800F03CF80AA090E8000C8244EA 67 | :100410008344AAF10107DA4501D100F031F8AFF2C7 68 | :10042000090EBAE80F0013F0010F18BFFB1A43F0D2 69 | :10043000010318476C0400008C040000103A24BF2C 70 | :1004400078C878C1FAD8520724BF30C830C144BF39 71 | :1004500004680C607047000000230024002500267B 72 | :10046000103A28BF78C1FBD8520728BF30C148BF17 73 | :100470000B6070471FB500F00DFA1FBD10B510BD21 74 | :1004800000F031F81146FFF7F5FF00F001FA00F037 75 | :100490004FF803B4FFF7F2FF03BC00F057F8000079 76 | :1004A0000948804709480047FEE7FEE7FEE7FEE708 77 | :1004B000FEE7FEE7FEE7FEE7FEE7FEE70448054944 78 | :1004C000054A064B704700006D050000010400005E 79 | :1004D000680000206840002068200020682000207C 80 | :1004E000704770477047754600F02CF8AE4605001F 81 | :1004F0006946534620F00700854618B020B5FFF73F 82 | :10050000DDFFBDE820404FF000064FF000074FF040 83 | :1005100000084FF0000B21F00701AC46ACE8C00921 84 | :10052000ACE8C009ACE8C009ACE8C0098D4670472A 85 | :1005300010B50446AFF300802046BDE81040FFF739 86 | :10054000A8BF00000048704704000020014918209F 87 | :10055000ABBEFEE7260002007047000001480249DA 88 | :10056000086070470090D0030000002010B500F034 89 | :10057000C3F810B157485849486700F0D5F828B17A 90 | :1005800056480068C0F342305549086000F0F6F85C 91 | :1005900028B15448006820F080705249086000F08B 92 | :1005A00005F948B10020504908604FF08041C1F87A 93 | :1005B00010014B49091F086000F022F918B103200F 94 | :1005C00047496431086000F033F968B105204749B4 95 | :1005D000086001204549783108600020434908310E 96 | :1005E00008603F20091F086000F03AF9002855D044 97 | :1005F0003F4800683F4908603D48001D0068091DEC 98 | :1006000008603B4808300068091D086038480C3015 99 | :100610000068091D0860364810300068091D086030 100 | :10062000334814300068091D0860314818300068EC 101 | :100630003049203108602E481C300068091D0860D0 102 | :100640002B4820300068091D0860294824300068C4 103 | :10065000091D0860264828300068091D08602448E4 104 | :100660002C300068091D086021483030006821499D 105 | :10067000403108601E4834300068091D08601C487D 106 | :1006800038300068091D086019483C300068091DB1 107 | :100690000860174840300068091D08601148743828 108 | :1006A000006840F470000F497439086000BF00BF53 109 | :1006B00000BFBFF34F8F00BF00BF00BF00BF00BF30 110 | :1006C00000BFBFF36F8F00BF00BF00BFFFF746FF43 111 | :1006D00010BD00000DF0ADBA00C00740440200108C 112 | :1006E0003C050040FCED00E00C01004010560040CD 113 | :1006F0000404001020C500400A48007806280ED1E6 114 | :100700000848001D007800F00F0040B90548083087 115 | :10071000007800F0F000302801D10120704700205F 116 | :10072000FCE70000E00F00F013480078062820D115 117 | :100730001148001D007800F00F00D0B90E480830B5 118 | :10074000007800F0F000302801D1012070470A48FD 119 | :100750000830007800F0F000402801D10120F5E7D2 120 | :1007600005480830007800F0F000502801D1012041 121 | :10077000ECE70020EAE70000E00F00F00A4800780C 122 | :1007800006280ED10848001D007800F00F0040B97F 123 | :1007900005480830007800F0F000302801D1012031 124 | :1007A00070470020FCE70000E00F00F013480078DD 125 | :1007B000062820D11148001D007800F00F00D0B9A4 126 | :1007C0000E480830007800F0F000302801D10120F8 127 | :1007D00070470A480830007800F0F000402801D146 128 | :1007E0000120F5E705480830007800F0F0005028B7 129 | :1007F00001D10120ECE70020EAE70000E00F00F063 130 | :100800000A48007806280ED10848001D007800F03C 131 | :100810000F0040B905480830007800F0F00030289B 132 | :1008200001D1012070470020FCE70000E00F00F03C 133 | :100830000A48007806280ED10848001D007800F00C 134 | :100840000F0040B905480830007800F0F00030286B 135 | :1008500001D1012070470020FCE70000E00F00F00C 136 | :100860000A48007806280ED10848001D007800F0DC 137 | :100870000F0040B905480830007800F0F00050281B 138 | :1008800001D1012070470020FCE70000E00F00F0DC 139 | :1008900000BFFEE74FF04070E1EE100A7047000025 140 | :1008A000C008000000000020040000003C0400001C 141 | :1008B000C408000004000020644000005804000048 142 | :0408C0000090D003D1 143 | :020000041000EA 144 | :04108000EFBEADDE34 145 | :0400000500000401F2 146 | :00000001FF 147 | -------------------------------------------------------------------------------- /tests/test_uicr_write/src/JLinkSettings.ini: -------------------------------------------------------------------------------- 1 | [BREAKPOINTS] 2 | ForceImpTypeAny = 0 3 | ShowInfoWin = 1 4 | EnableFlashBP = 2 5 | BPDuringExecution = 0 6 | [CFI] 7 | CFISize = 0x00 8 | CFIAddr = 0x00 9 | [CPU] 10 | MonModeVTableAddr = 0xFFFFFFFF 11 | MonModeDebug = 0 12 | MaxNumAPs = 0 13 | LowPowerHandlingMode = 0 14 | OverrideMemMap = 0 15 | AllowSimulation = 1 16 | ScriptFile="" 17 | [FLASH] 18 | CacheExcludeSize = 0x00 19 | CacheExcludeAddr = 0x00 20 | MinNumBytesFlashDL = 0 21 | SkipProgOnCRCMatch = 1 22 | VerifyDownload = 1 23 | AllowCaching = 1 24 | EnableFlashDL = 2 25 | Override = 0 26 | Device="ARM7" 27 | [GENERAL] 28 | WorkRAMSize = 0x00 29 | WorkRAMAddr = 0x00 30 | RAMUsageLimit = 0x00 31 | [SWO] 32 | SWOLogFile="" 33 | [MEM] 34 | RdOverrideOrMask = 0x00 35 | RdOverrideAndMask = 0xFFFFFFFF 36 | RdOverrideAddr = 0xFFFFFFFF 37 | WrOverrideOrMask = 0x00 38 | WrOverrideAndMask = 0xFFFFFFFF 39 | WrOverrideAddr = 0xFFFFFFFF 40 | -------------------------------------------------------------------------------- /tests/test_uicr_write/src/RTE/Device/nRF52832_xxAA/arm_startup_nrf52.s: -------------------------------------------------------------------------------- 1 | ;/* Copyright (c) 2012 ARM LIMITED 2 | ; 3 | ; All rights reserved. 4 | ; Redistribution and use in source and binary forms, with or without 5 | ; modification, are permitted provided that the following conditions are met: 6 | ; - Redistributions of source code must retain the above copyright 7 | ; notice, this list of conditions and the following disclaimer. 8 | ; - Redistributions in binary form must reproduce the above copyright 9 | ; notice, this list of conditions and the following disclaimer in the 10 | ; documentation and/or other materials provided with the distribution. 11 | ; - Neither the name of ARM nor the names of its contributors may be used 12 | ; to endorse or promote products derived from this software without 13 | ; specific prior written permission. 14 | ; * 15 | ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 19 | ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ; POSSIBILITY OF SUCH DAMAGE. 26 | ; ---------------------------------------------------------------------------*/ 27 | 28 | IF :DEF: __STACK_SIZE 29 | Stack_Size EQU __STACK_SIZE 30 | ELSE 31 | Stack_Size EQU 8192 32 | ENDIF 33 | 34 | AREA STACK, NOINIT, READWRITE, ALIGN=3 35 | Stack_Mem SPACE Stack_Size 36 | __initial_sp 37 | 38 | IF :DEF: __HEAP_SIZE 39 | Heap_Size EQU __HEAP_SIZE 40 | ELSE 41 | Heap_Size EQU 8192 42 | ENDIF 43 | 44 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 45 | __heap_base 46 | Heap_Mem SPACE Heap_Size 47 | __heap_limit 48 | 49 | PRESERVE8 50 | THUMB 51 | 52 | ; Vector Table Mapped to Address 0 at Reset 53 | 54 | AREA RESET, DATA, READONLY 55 | EXPORT __Vectors 56 | EXPORT __Vectors_End 57 | EXPORT __Vectors_Size 58 | 59 | __Vectors DCD __initial_sp ; Top of Stack 60 | DCD Reset_Handler 61 | DCD NMI_Handler 62 | DCD HardFault_Handler 63 | DCD MemoryManagement_Handler 64 | DCD BusFault_Handler 65 | DCD UsageFault_Handler 66 | DCD 0 ; Reserved 67 | DCD 0 ; Reserved 68 | DCD 0 ; Reserved 69 | DCD 0 ; Reserved 70 | DCD SVC_Handler 71 | DCD DebugMonitor_Handler 72 | DCD 0 ; Reserved 73 | DCD PendSV_Handler 74 | DCD SysTick_Handler 75 | 76 | ; External Interrupts 77 | DCD POWER_CLOCK_IRQHandler 78 | DCD RADIO_IRQHandler 79 | DCD UARTE0_UART0_IRQHandler 80 | DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 81 | DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 82 | DCD NFCT_IRQHandler 83 | DCD GPIOTE_IRQHandler 84 | DCD SAADC_IRQHandler 85 | DCD TIMER0_IRQHandler 86 | DCD TIMER1_IRQHandler 87 | DCD TIMER2_IRQHandler 88 | DCD RTC0_IRQHandler 89 | DCD TEMP_IRQHandler 90 | DCD RNG_IRQHandler 91 | DCD ECB_IRQHandler 92 | DCD CCM_AAR_IRQHandler 93 | DCD WDT_IRQHandler 94 | DCD RTC1_IRQHandler 95 | DCD QDEC_IRQHandler 96 | DCD COMP_LPCOMP_IRQHandler 97 | DCD SWI0_EGU0_IRQHandler 98 | DCD SWI1_EGU1_IRQHandler 99 | DCD SWI2_EGU2_IRQHandler 100 | DCD SWI3_EGU3_IRQHandler 101 | DCD SWI4_EGU4_IRQHandler 102 | DCD SWI5_EGU5_IRQHandler 103 | DCD TIMER3_IRQHandler 104 | DCD TIMER4_IRQHandler 105 | DCD PWM0_IRQHandler 106 | DCD PDM_IRQHandler 107 | DCD 0 ; Reserved 108 | DCD 0 ; Reserved 109 | DCD MWU_IRQHandler 110 | DCD PWM1_IRQHandler 111 | DCD PWM2_IRQHandler 112 | DCD SPIM2_SPIS2_SPI2_IRQHandler 113 | DCD RTC2_IRQHandler 114 | DCD I2S_IRQHandler 115 | DCD FPU_IRQHandler 116 | DCD 0 ; Reserved 117 | DCD 0 ; Reserved 118 | DCD 0 ; Reserved 119 | DCD 0 ; Reserved 120 | DCD 0 ; Reserved 121 | DCD 0 ; Reserved 122 | DCD 0 ; Reserved 123 | DCD 0 ; Reserved 124 | DCD 0 ; Reserved 125 | DCD 0 ; Reserved 126 | DCD 0 ; Reserved 127 | DCD 0 ; Reserved 128 | DCD 0 ; Reserved 129 | DCD 0 ; Reserved 130 | DCD 0 ; Reserved 131 | DCD 0 ; Reserved 132 | DCD 0 ; Reserved 133 | DCD 0 ; Reserved 134 | DCD 0 ; Reserved 135 | DCD 0 ; Reserved 136 | DCD 0 ; Reserved 137 | DCD 0 ; Reserved 138 | DCD 0 ; Reserved 139 | DCD 0 ; Reserved 140 | DCD 0 ; Reserved 141 | DCD 0 ; Reserved 142 | DCD 0 ; Reserved 143 | DCD 0 ; Reserved 144 | DCD 0 ; Reserved 145 | DCD 0 ; Reserved 146 | DCD 0 ; Reserved 147 | DCD 0 ; Reserved 148 | DCD 0 ; Reserved 149 | DCD 0 ; Reserved 150 | DCD 0 ; Reserved 151 | DCD 0 ; Reserved 152 | DCD 0 ; Reserved 153 | DCD 0 ; Reserved 154 | DCD 0 ; Reserved 155 | DCD 0 ; Reserved 156 | DCD 0 ; Reserved 157 | DCD 0 ; Reserved 158 | DCD 0 ; Reserved 159 | DCD 0 ; Reserved 160 | DCD 0 ; Reserved 161 | DCD 0 ; Reserved 162 | DCD 0 ; Reserved 163 | DCD 0 ; Reserved 164 | DCD 0 ; Reserved 165 | DCD 0 ; Reserved 166 | DCD 0 ; Reserved 167 | DCD 0 ; Reserved 168 | DCD 0 ; Reserved 169 | DCD 0 ; Reserved 170 | DCD 0 ; Reserved 171 | DCD 0 ; Reserved 172 | DCD 0 ; Reserved 173 | DCD 0 ; Reserved 174 | DCD 0 ; Reserved 175 | DCD 0 ; Reserved 176 | DCD 0 ; Reserved 177 | DCD 0 ; Reserved 178 | DCD 0 ; Reserved 179 | DCD 0 ; Reserved 180 | DCD 0 ; Reserved 181 | DCD 0 ; Reserved 182 | DCD 0 ; Reserved 183 | DCD 0 ; Reserved 184 | DCD 0 ; Reserved 185 | DCD 0 ; Reserved 186 | DCD 0 ; Reserved 187 | DCD 0 ; Reserved 188 | DCD 0 ; Reserved 189 | DCD 0 ; Reserved 190 | DCD 0 ; Reserved 191 | DCD 0 ; Reserved 192 | DCD 0 ; Reserved 193 | DCD 0 ; Reserved 194 | DCD 0 ; Reserved 195 | DCD 0 ; Reserved 196 | DCD 0 ; Reserved 197 | DCD 0 ; Reserved 198 | DCD 0 ; Reserved 199 | DCD 0 ; Reserved 200 | DCD 0 ; Reserved 201 | DCD 0 ; Reserved 202 | DCD 0 ; Reserved 203 | DCD 0 ; Reserved 204 | DCD 0 ; Reserved 205 | DCD 0 ; Reserved 206 | DCD 0 ; Reserved 207 | DCD 0 ; Reserved 208 | DCD 0 ; Reserved 209 | DCD 0 ; Reserved 210 | DCD 0 ; Reserved 211 | DCD 0 ; Reserved 212 | DCD 0 ; Reserved 213 | DCD 0 ; Reserved 214 | DCD 0 ; Reserved 215 | DCD 0 ; Reserved 216 | DCD 0 ; Reserved 217 | DCD 0 ; Reserved 218 | DCD 0 ; Reserved 219 | DCD 0 ; Reserved 220 | DCD 0 ; Reserved 221 | DCD 0 ; Reserved 222 | DCD 0 ; Reserved 223 | DCD 0 ; Reserved 224 | DCD 0 ; Reserved 225 | DCD 0 ; Reserved 226 | DCD 0 ; Reserved 227 | DCD 0 ; Reserved 228 | DCD 0 ; Reserved 229 | DCD 0 ; Reserved 230 | DCD 0 ; Reserved 231 | DCD 0 ; Reserved 232 | DCD 0 ; Reserved 233 | DCD 0 ; Reserved 234 | DCD 0 ; Reserved 235 | DCD 0 ; Reserved 236 | DCD 0 ; Reserved 237 | DCD 0 ; Reserved 238 | DCD 0 ; Reserved 239 | DCD 0 ; Reserved 240 | DCD 0 ; Reserved 241 | DCD 0 ; Reserved 242 | DCD 0 ; Reserved 243 | DCD 0 ; Reserved 244 | DCD 0 ; Reserved 245 | DCD 0 ; Reserved 246 | DCD 0 ; Reserved 247 | DCD 0 ; Reserved 248 | DCD 0 ; Reserved 249 | DCD 0 ; Reserved 250 | DCD 0 ; Reserved 251 | DCD 0 ; Reserved 252 | DCD 0 ; Reserved 253 | DCD 0 ; Reserved 254 | DCD 0 ; Reserved 255 | DCD 0 ; Reserved 256 | DCD 0 ; Reserved 257 | DCD 0 ; Reserved 258 | DCD 0 ; Reserved 259 | DCD 0 ; Reserved 260 | DCD 0 ; Reserved 261 | DCD 0 ; Reserved 262 | DCD 0 ; Reserved 263 | DCD 0 ; Reserved 264 | DCD 0 ; Reserved 265 | DCD 0 ; Reserved 266 | DCD 0 ; Reserved 267 | DCD 0 ; Reserved 268 | DCD 0 ; Reserved 269 | DCD 0 ; Reserved 270 | DCD 0 ; Reserved 271 | DCD 0 ; Reserved 272 | DCD 0 ; Reserved 273 | DCD 0 ; Reserved 274 | DCD 0 ; Reserved 275 | DCD 0 ; Reserved 276 | DCD 0 ; Reserved 277 | DCD 0 ; Reserved 278 | DCD 0 ; Reserved 279 | DCD 0 ; Reserved 280 | DCD 0 ; Reserved 281 | DCD 0 ; Reserved 282 | DCD 0 ; Reserved 283 | DCD 0 ; Reserved 284 | DCD 0 ; Reserved 285 | DCD 0 ; Reserved 286 | DCD 0 ; Reserved 287 | DCD 0 ; Reserved 288 | DCD 0 ; Reserved 289 | DCD 0 ; Reserved 290 | DCD 0 ; Reserved 291 | DCD 0 ; Reserved 292 | DCD 0 ; Reserved 293 | DCD 0 ; Reserved 294 | DCD 0 ; Reserved 295 | DCD 0 ; Reserved 296 | DCD 0 ; Reserved 297 | DCD 0 ; Reserved 298 | DCD 0 ; Reserved 299 | DCD 0 ; Reserved 300 | DCD 0 ; Reserved 301 | DCD 0 ; Reserved 302 | DCD 0 ; Reserved 303 | DCD 0 ; Reserved 304 | DCD 0 ; Reserved 305 | DCD 0 ; Reserved 306 | DCD 0 ; Reserved 307 | DCD 0 ; Reserved 308 | DCD 0 ; Reserved 309 | DCD 0 ; Reserved 310 | DCD 0 ; Reserved 311 | DCD 0 ; Reserved 312 | DCD 0 ; Reserved 313 | DCD 0 ; Reserved 314 | DCD 0 ; Reserved 315 | DCD 0 ; Reserved 316 | DCD 0 ; Reserved 317 | 318 | __Vectors_End 319 | 320 | __Vectors_Size EQU __Vectors_End - __Vectors 321 | 322 | AREA |.text|, CODE, READONLY 323 | 324 | ; Reset Handler 325 | 326 | 327 | Reset_Handler PROC 328 | EXPORT Reset_Handler [WEAK] 329 | IMPORT SystemInit 330 | IMPORT __main 331 | 332 | 333 | LDR R0, =SystemInit 334 | BLX R0 335 | LDR R0, =__main 336 | BX R0 337 | ENDP 338 | 339 | ; Dummy Exception Handlers (infinite loops which can be modified) 340 | 341 | NMI_Handler PROC 342 | EXPORT NMI_Handler [WEAK] 343 | B . 344 | ENDP 345 | HardFault_Handler\ 346 | PROC 347 | EXPORT HardFault_Handler [WEAK] 348 | B . 349 | ENDP 350 | MemoryManagement_Handler\ 351 | PROC 352 | EXPORT MemoryManagement_Handler [WEAK] 353 | B . 354 | ENDP 355 | BusFault_Handler\ 356 | PROC 357 | EXPORT BusFault_Handler [WEAK] 358 | B . 359 | ENDP 360 | UsageFault_Handler\ 361 | PROC 362 | EXPORT UsageFault_Handler [WEAK] 363 | B . 364 | ENDP 365 | SVC_Handler PROC 366 | EXPORT SVC_Handler [WEAK] 367 | B . 368 | ENDP 369 | DebugMonitor_Handler\ 370 | PROC 371 | EXPORT DebugMonitor_Handler [WEAK] 372 | B . 373 | ENDP 374 | PendSV_Handler PROC 375 | EXPORT PendSV_Handler [WEAK] 376 | B . 377 | ENDP 378 | SysTick_Handler PROC 379 | EXPORT SysTick_Handler [WEAK] 380 | B . 381 | ENDP 382 | 383 | Default_Handler PROC 384 | 385 | EXPORT POWER_CLOCK_IRQHandler [WEAK] 386 | EXPORT RADIO_IRQHandler [WEAK] 387 | EXPORT UARTE0_UART0_IRQHandler [WEAK] 388 | EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK] 389 | EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK] 390 | EXPORT NFCT_IRQHandler [WEAK] 391 | EXPORT GPIOTE_IRQHandler [WEAK] 392 | EXPORT SAADC_IRQHandler [WEAK] 393 | EXPORT TIMER0_IRQHandler [WEAK] 394 | EXPORT TIMER1_IRQHandler [WEAK] 395 | EXPORT TIMER2_IRQHandler [WEAK] 396 | EXPORT RTC0_IRQHandler [WEAK] 397 | EXPORT TEMP_IRQHandler [WEAK] 398 | EXPORT RNG_IRQHandler [WEAK] 399 | EXPORT ECB_IRQHandler [WEAK] 400 | EXPORT CCM_AAR_IRQHandler [WEAK] 401 | EXPORT WDT_IRQHandler [WEAK] 402 | EXPORT RTC1_IRQHandler [WEAK] 403 | EXPORT QDEC_IRQHandler [WEAK] 404 | EXPORT COMP_LPCOMP_IRQHandler [WEAK] 405 | EXPORT SWI0_EGU0_IRQHandler [WEAK] 406 | EXPORT SWI1_EGU1_IRQHandler [WEAK] 407 | EXPORT SWI2_EGU2_IRQHandler [WEAK] 408 | EXPORT SWI3_EGU3_IRQHandler [WEAK] 409 | EXPORT SWI4_EGU4_IRQHandler [WEAK] 410 | EXPORT SWI5_EGU5_IRQHandler [WEAK] 411 | EXPORT TIMER3_IRQHandler [WEAK] 412 | EXPORT TIMER4_IRQHandler [WEAK] 413 | EXPORT PWM0_IRQHandler [WEAK] 414 | EXPORT PDM_IRQHandler [WEAK] 415 | EXPORT MWU_IRQHandler [WEAK] 416 | EXPORT PWM1_IRQHandler [WEAK] 417 | EXPORT PWM2_IRQHandler [WEAK] 418 | EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK] 419 | EXPORT RTC2_IRQHandler [WEAK] 420 | EXPORT I2S_IRQHandler [WEAK] 421 | EXPORT FPU_IRQHandler [WEAK] 422 | POWER_CLOCK_IRQHandler 423 | RADIO_IRQHandler 424 | UARTE0_UART0_IRQHandler 425 | SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 426 | SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 427 | NFCT_IRQHandler 428 | GPIOTE_IRQHandler 429 | SAADC_IRQHandler 430 | TIMER0_IRQHandler 431 | TIMER1_IRQHandler 432 | TIMER2_IRQHandler 433 | RTC0_IRQHandler 434 | TEMP_IRQHandler 435 | RNG_IRQHandler 436 | ECB_IRQHandler 437 | CCM_AAR_IRQHandler 438 | WDT_IRQHandler 439 | RTC1_IRQHandler 440 | QDEC_IRQHandler 441 | COMP_LPCOMP_IRQHandler 442 | SWI0_EGU0_IRQHandler 443 | SWI1_EGU1_IRQHandler 444 | SWI2_EGU2_IRQHandler 445 | SWI3_EGU3_IRQHandler 446 | SWI4_EGU4_IRQHandler 447 | SWI5_EGU5_IRQHandler 448 | TIMER3_IRQHandler 449 | TIMER4_IRQHandler 450 | PWM0_IRQHandler 451 | PDM_IRQHandler 452 | MWU_IRQHandler 453 | PWM1_IRQHandler 454 | PWM2_IRQHandler 455 | SPIM2_SPIS2_SPI2_IRQHandler 456 | RTC2_IRQHandler 457 | I2S_IRQHandler 458 | FPU_IRQHandler 459 | B . 460 | ENDP 461 | ALIGN 462 | 463 | ; User Initial Stack & Heap 464 | 465 | IF :DEF:__MICROLIB 466 | 467 | EXPORT __initial_sp 468 | EXPORT __heap_base 469 | EXPORT __heap_limit 470 | 471 | ELSE 472 | 473 | IMPORT __use_two_region_memory 474 | EXPORT __user_initial_stackheap 475 | 476 | __user_initial_stackheap PROC 477 | 478 | LDR R0, = Heap_Mem 479 | LDR R1, = (Stack_Mem + Stack_Size) 480 | LDR R2, = (Heap_Mem + Heap_Size) 481 | LDR R3, = Stack_Mem 482 | BX LR 483 | ENDP 484 | 485 | ALIGN 486 | 487 | ENDIF 488 | 489 | END 490 | -------------------------------------------------------------------------------- /tests/test_uicr_write/src/RTE/Device/nRF52832_xxAA/system_nrf52.c: -------------------------------------------------------------------------------- 1 | /* Copyright (c) 2015, Nordic Semiconductor ASA 2 | * All rights reserved. 3 | * 4 | * Redistribution and use in source and binary forms, with or without 5 | * modification, are permitted provided that the following conditions are met: 6 | * 7 | * * Redistributions of source code must retain the above copyright notice, this 8 | * list of conditions and the following disclaimer. 9 | * 10 | * * Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * * Neither the name of Nordic Semiconductor ASA nor the names of its 15 | * contributors may be used to endorse or promote products derived from 16 | * this software without specific prior written permission. 17 | * 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | * 29 | */ 30 | 31 | #include 32 | #include 33 | #include "nrf.h" 34 | #include "system_nrf52.h" 35 | 36 | /*lint ++flb "Enter library region" */ 37 | 38 | #define __SYSTEM_CLOCK_64M (64000000UL) 39 | 40 | static bool errata_16(void); 41 | static bool errata_31(void); 42 | static bool errata_32(void); 43 | static bool errata_36(void); 44 | static bool errata_37(void); 45 | static bool errata_57(void); 46 | static bool errata_66(void); 47 | 48 | 49 | #if defined ( __CC_ARM ) 50 | uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; 51 | #elif defined ( __ICCARM__ ) 52 | __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; 53 | #elif defined ( __GNUC__ ) 54 | uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; 55 | #endif 56 | 57 | void SystemCoreClockUpdate(void) 58 | { 59 | SystemCoreClock = __SYSTEM_CLOCK_64M; 60 | } 61 | 62 | void SystemInit(void) 63 | { 64 | /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document 65 | for your device located at https://infocenter.nordicsemi.com/ */ 66 | if (errata_16()){ 67 | *(volatile uint32_t *)0x4007C074 = 3131961357ul; 68 | } 69 | 70 | /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document 71 | for your device located at https://infocenter.nordicsemi.com/ */ 72 | if (errata_31()){ 73 | *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; 74 | } 75 | 76 | /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document 77 | for your device located at https://infocenter.nordicsemi.com/ */ 78 | if (errata_32()){ 79 | CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; 80 | } 81 | 82 | /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document 83 | for your device located at https://infocenter.nordicsemi.com/ */ 84 | if (errata_36()){ 85 | NRF_CLOCK->EVENTS_DONE = 0; 86 | NRF_CLOCK->EVENTS_CTTO = 0; 87 | NRF_CLOCK->CTIV = 0; 88 | } 89 | 90 | /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document 91 | for your device located at https://infocenter.nordicsemi.com/ */ 92 | if (errata_37()){ 93 | *(volatile uint32_t *)0x400005A0 = 0x3; 94 | } 95 | 96 | /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document 97 | for your device located at https://infocenter.nordicsemi.com/ */ 98 | if (errata_57()){ 99 | *(volatile uint32_t *)0x40005610 = 0x00000005; 100 | *(volatile uint32_t *)0x40005688 = 0x00000001; 101 | *(volatile uint32_t *)0x40005618 = 0x00000000; 102 | *(volatile uint32_t *)0x40005614 = 0x0000003F; 103 | } 104 | 105 | /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document 106 | for your device located at https://infocenter.nordicsemi.com/ */ 107 | if (errata_66()){ 108 | NRF_TEMP->A0 = NRF_FICR->TEMP.A0; 109 | NRF_TEMP->A1 = NRF_FICR->TEMP.A1; 110 | NRF_TEMP->A2 = NRF_FICR->TEMP.A2; 111 | NRF_TEMP->A3 = NRF_FICR->TEMP.A3; 112 | NRF_TEMP->A4 = NRF_FICR->TEMP.A4; 113 | NRF_TEMP->A5 = NRF_FICR->TEMP.A5; 114 | NRF_TEMP->B0 = NRF_FICR->TEMP.B0; 115 | NRF_TEMP->B1 = NRF_FICR->TEMP.B1; 116 | NRF_TEMP->B2 = NRF_FICR->TEMP.B2; 117 | NRF_TEMP->B3 = NRF_FICR->TEMP.B3; 118 | NRF_TEMP->B4 = NRF_FICR->TEMP.B4; 119 | NRF_TEMP->B5 = NRF_FICR->TEMP.B5; 120 | NRF_TEMP->T0 = NRF_FICR->TEMP.T0; 121 | NRF_TEMP->T1 = NRF_FICR->TEMP.T1; 122 | NRF_TEMP->T2 = NRF_FICR->TEMP.T2; 123 | NRF_TEMP->T3 = NRF_FICR->TEMP.T3; 124 | NRF_TEMP->T4 = NRF_FICR->TEMP.T4; 125 | } 126 | 127 | /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the 128 | * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit 129 | * operations are not used in your code. */ 130 | #if (__FPU_USED == 1) 131 | SCB->CPACR |= (3UL << 20) | (3UL << 22); 132 | __DSB(); 133 | __ISB(); 134 | #endif 135 | 136 | /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, 137 | two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as 138 | normal GPIOs. */ 139 | #if defined (CONFIG_NFCT_PINS_AS_GPIOS) 140 | if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ 141 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; 142 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 143 | NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; 144 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 145 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; 146 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 147 | NVIC_SystemReset(); 148 | } 149 | #endif 150 | 151 | /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not 152 | defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be 153 | reserved for PinReset and not available as normal GPIO. */ 154 | #if defined (CONFIG_GPIO_AS_PINRESET) 155 | if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || 156 | ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ 157 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; 158 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 159 | NRF_UICR->PSELRESET[0] = 21; 160 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 161 | NRF_UICR->PSELRESET[1] = 21; 162 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 163 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; 164 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} 165 | NVIC_SystemReset(); 166 | } 167 | #endif 168 | 169 | /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product 170 | Specification to see which one). */ 171 | #if defined (ENABLE_SWO) 172 | CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 173 | NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; 174 | NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 175 | #endif 176 | 177 | /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product 178 | Specification to see which ones). */ 179 | #if defined (ENABLE_TRACE) 180 | CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 181 | NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; 182 | NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 183 | NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 184 | NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 185 | NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 186 | NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); 187 | #endif 188 | 189 | SystemCoreClockUpdate(); 190 | } 191 | 192 | 193 | static bool errata_16(void) 194 | { 195 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 196 | { 197 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 198 | { 199 | return true; 200 | } 201 | } 202 | 203 | return false; 204 | } 205 | 206 | static bool errata_31(void) 207 | { 208 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 209 | { 210 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 211 | { 212 | return true; 213 | } 214 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) 215 | { 216 | return true; 217 | } 218 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) 219 | { 220 | return true; 221 | } 222 | } 223 | 224 | return false; 225 | } 226 | 227 | static bool errata_32(void) 228 | { 229 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 230 | { 231 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 232 | { 233 | return true; 234 | } 235 | } 236 | 237 | return false; 238 | } 239 | 240 | static bool errata_36(void) 241 | { 242 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 243 | { 244 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 245 | { 246 | return true; 247 | } 248 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) 249 | { 250 | return true; 251 | } 252 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) 253 | { 254 | return true; 255 | } 256 | } 257 | 258 | return false; 259 | } 260 | 261 | static bool errata_37(void) 262 | { 263 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 264 | { 265 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 266 | { 267 | return true; 268 | } 269 | } 270 | 271 | return false; 272 | } 273 | 274 | static bool errata_57(void) 275 | { 276 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 277 | { 278 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) 279 | { 280 | return true; 281 | } 282 | } 283 | 284 | return false; 285 | } 286 | 287 | static bool errata_66(void) 288 | { 289 | if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) 290 | { 291 | if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) 292 | { 293 | return true; 294 | } 295 | } 296 | 297 | return false; 298 | } 299 | 300 | 301 | /*lint --flb "Leave library region" */ 302 | -------------------------------------------------------------------------------- /tests/test_uicr_write/src/RTE/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'test_uicr_write' 7 | * Target: 'Test_nRF52' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | #endif /* RTE_COMPONENTS_H */ 15 | -------------------------------------------------------------------------------- /tests/test_uicr_write/src/main.c: -------------------------------------------------------------------------------- 1 | /* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved. 2 | * 3 | * The information contained herein is property of Nordic Semiconductor ASA. 4 | * Terms and conditions of usage are described in detail in NORDIC 5 | * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. 6 | * 7 | * Licensees are granted free, non-transferable use of the information. NO 8 | * WARRANTY of ANY KIND is provided. This heading must NOT be removed from 9 | * the file. 10 | * 11 | */ 12 | /** @test tests/test_uicr_write/src/main.c 13 | * 14 | * @brief Tests that programming tool can properly write to the UICR area of FLASH. 15 | * 16 | * This file contains the source code for the test_uicr_write hex file provided in ../hex/ 17 | * See the corresponding README for expected behavior. 18 | */ 19 | 20 | #include 21 | 22 | #include "nrf.h" 23 | 24 | // This address/data will be placed in the generated .hex file and should be written when the application is flashed. 25 | const uint32_t UICR_CUSTOMER_0 __attribute__((at(0x10001080))) __attribute__((used)) = 0xDEADBEEF; 26 | 27 | /**@brief Function for application main entry. 28 | */ 29 | int main(void) 30 | { 31 | // Enter main loop. 32 | for (;;) 33 | { 34 | // Loop. 35 | } 36 | } 37 | -------------------------------------------------------------------------------- /tests/test_uicr_write/src/test_uicr_write.uvprojx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2.1 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | 10 | Test_nRF52 11 | 0x4 12 | ARM-ADS 13 | 5060061::V5.06 update 1 (build 61)::ARMCC 14 | 15 | 16 | nRF52832_xxAA 17 | Nordic Semiconductor 18 | NordicSemiconductor.nRF_DeviceFamilyPack.8.5.0 19 | http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ 20 | IROM(0x00000000,0x80000) IRAM(0x20000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE 21 | 22 | 23 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)) 24 | 0 25 | $$Device:nRF52832_xxAA$Device\Include\nrf.h 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | $$Device:nRF52832_xxAA$SVD\nrf52.svd 36 | 0 37 | 0 38 | 39 | 40 | 41 | 42 | 43 | 44 | 0 45 | 0 46 | 0 47 | 0 48 | 1 49 | 50 | .\Objects\ 51 | test_uicr_write 52 | 1 53 | 0 54 | 1 55 | 1 56 | 1 57 | .\Listings\ 58 | 1 59 | 0 60 | 0 61 | 62 | 0 63 | 0 64 | 65 | 66 | 0 67 | 0 68 | 0 69 | 0 70 | 71 | 72 | 0 73 | 0 74 | 75 | 76 | 0 77 | 0 78 | 0 79 | 0 80 | 81 | 82 | 0 83 | 0 84 | 85 | 86 | 0 87 | 0 88 | 0 89 | 0 90 | 91 | 0 92 | 93 | 94 | 95 | 0 96 | 0 97 | 0 98 | 0 99 | 0 100 | 1 101 | 0 102 | 0 103 | 0 104 | 0 105 | 3 106 | 107 | 108 | 1 109 | 110 | 111 | SARMCM3.DLL 112 | -MPU 113 | DCM.DLL 114 | -pCM4 115 | SARMCM3.DLL 116 | -MPU 117 | TCM.DLL 118 | -pCM4 119 | 120 | 121 | 122 | 1 123 | 0 124 | 0 125 | 0 126 | 16 127 | 128 | 129 | 0 130 | 1 131 | 1 132 | 1 133 | 1 134 | 1 135 | 1 136 | 1 137 | 0 138 | 1 139 | 140 | 141 | 1 142 | 1 143 | 1 144 | 1 145 | 1 146 | 1 147 | 0 148 | 1 149 | 1 150 | 1 151 | 152 | 0 153 | 6 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | Segger\JL2CM3.dll 168 | 169 | 170 | 171 | 172 | 1 173 | 0 174 | 0 175 | 1 176 | 0 177 | -1 178 | 179 | 1 180 | BIN\UL2CM3.DLL 181 | 182 | 183 | 184 | 185 | 186 | 0 187 | 188 | 189 | 190 | 0 191 | 1 192 | 1 193 | 1 194 | 1 195 | 1 196 | 1 197 | 1 198 | 0 199 | 1 200 | 1 201 | 0 202 | 1 203 | 1 204 | 0 205 | 0 206 | 1 207 | 1 208 | 1 209 | 1 210 | 1 211 | 1 212 | 1 213 | 1 214 | 1 215 | 0 216 | 0 217 | "Cortex-M4" 218 | 219 | 0 220 | 0 221 | 0 222 | 1 223 | 1 224 | 0 225 | 0 226 | 2 227 | 0 228 | 0 229 | 8 230 | 0 231 | 0 232 | 0 233 | 0 234 | 3 235 | 3 236 | 0 237 | 0 238 | 0 239 | 0 240 | 0 241 | 0 242 | 0 243 | 0 244 | 0 245 | 0 246 | 1 247 | 0 248 | 0 249 | 0 250 | 0 251 | 1 252 | 0 253 | 254 | 255 | 0 256 | 0x0 257 | 0x0 258 | 259 | 260 | 0 261 | 0x0 262 | 0x0 263 | 264 | 265 | 0 266 | 0x0 267 | 0x0 268 | 269 | 270 | 0 271 | 0x0 272 | 0x0 273 | 274 | 275 | 0 276 | 0x0 277 | 0x0 278 | 279 | 280 | 0 281 | 0x0 282 | 0x0 283 | 284 | 285 | 0 286 | 0x20000000 287 | 0x10000 288 | 289 | 290 | 1 291 | 0x0 292 | 0x80000 293 | 294 | 295 | 0 296 | 0x0 297 | 0x0 298 | 299 | 300 | 1 301 | 0x0 302 | 0x0 303 | 304 | 305 | 1 306 | 0x0 307 | 0x0 308 | 309 | 310 | 1 311 | 0x0 312 | 0x0 313 | 314 | 315 | 1 316 | 0x0 317 | 0x80000 318 | 319 | 320 | 1 321 | 0x0 322 | 0x0 323 | 324 | 325 | 0 326 | 0x0 327 | 0x0 328 | 329 | 330 | 0 331 | 0x0 332 | 0x0 333 | 334 | 335 | 0 336 | 0x0 337 | 0x0 338 | 339 | 340 | 0 341 | 0x20000000 342 | 0x10000 343 | 344 | 345 | 0 346 | 0x0 347 | 0x0 348 | 349 | 350 | 351 | 352 | 353 | 1 354 | 1 355 | 0 356 | 0 357 | 1 358 | 0 359 | 0 360 | 0 361 | 0 362 | 0 363 | 2 364 | 0 365 | 0 366 | 0 367 | 0 368 | 0 369 | 0 370 | 0 371 | 0 372 | 373 | 374 | NRF52 375 | 376 | 377 | 378 | 379 | 380 | 1 381 | 0 382 | 0 383 | 0 384 | 0 385 | 0 386 | 0 387 | 0 388 | 0 389 | 390 | 391 | NRF52 392 | 393 | 394 | 395 | 396 | 397 | 1 398 | 0 399 | 0 400 | 0 401 | 1 402 | 0 403 | 0x00000000 404 | 0x20000000 405 | 406 | 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | Application 418 | 419 | 420 | main.c 421 | 1 422 | .\main.c 423 | 424 | 425 | 426 | 427 | ::CMSIS 428 | 429 | 430 | ::Device 431 | 432 | 433 | 434 | 435 | 436 | 437 | 438 | 439 | 440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | 450 | 451 | 452 | 453 | 454 | RTE\Device\nRF52832_xxAA\arm_startup_nrf52.s 455 | 456 | 457 | 458 | 459 | 460 | 461 | 462 | RTE\Device\nRF52832_xxAA\system_nrf52.c 463 | 464 | 465 | 466 | 467 | 468 | 469 | 470 | 471 | 472 | 473 | --------------------------------------------------------------------------------