├── README.md
├── .gitignore
├── sources
    ├── MBIST_TAP_interface.v
    ├── MBIST_diagnostics.v
    ├── MBIST_BRAM_TOP.v
    ├── MBIST_comparator_WF.v
    ├── MBIST_CONTROLLER.v
    ├── MBIST_BRAM_SHELL.v
    └── MBIST_algorithm_generator.v
└── LICENSE


/README.md:
--------------------------------------------------------------------------------
1 | # MBIST-verilog
2 | A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated 
3 | 


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/.gitignore:
--------------------------------------------------------------------------------
 1 | # Prerequisites
 2 | *.d
 3 | 
 4 | # Object files
 5 | *.o
 6 | *.ko
 7 | *.obj
 8 | *.elf
 9 | 
10 | # Linker output
11 | *.ilk
12 | *.map
13 | *.exp
14 | 
15 | # Precompiled Headers
16 | *.gch
17 | *.pch
18 | 
19 | # Libraries
20 | *.lib
21 | *.a
22 | *.la
23 | *.lo
24 | 
25 | # Shared objects (inc. Windows DLLs)
26 | *.dll
27 | *.so
28 | *.so.*
29 | *.dylib
30 | 
31 | # Executables
32 | *.exe
33 | *.out
34 | *.app
35 | *.i*86
36 | *.x86_64
37 | *.hex
38 | 
39 | # Debug files
40 | *.dSYM/
41 | *.su
42 | *.idb
43 | *.pdb
44 | 
45 | # Kernel Module Compile Results
46 | *.mod*
47 | *.cmd
48 | .tmp_versions/
49 | modules.order
50 | Module.symvers
51 | Mkfile.old
52 | dkms.conf
53 | 


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/sources/MBIST_TAP_interface.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | /*
 3 | //////////////////////////////////////////////////////////////////////////////////
 4 | //   Copyright 2013 - 2019 Yang Song
 5 | //   E-mail: googotohell@gmail.com
 6 | //
 7 | //   Licensed under the Apache License, Version 2.0 (the "License");
 8 | //   you may not use this file except in compliance with the License.
 9 | //   You may obtain a copy of the License at
10 | //
11 | //       http://www.apache.org/licenses/LICENSE-2.0
12 | //
13 | //   Unless required by applicable law or agreed to in writing, software
14 | //   distributed under the License is distributed on an "AS IS" BASIS,
15 | //   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 | //   See the License for the specific language governing permissions and
17 | //   limitations under the License.
18 | */
19 | //////////////////////////////////////////////////////////////////////////////////
20 | // Company: <-blank->
21 | // Engineer: Yang Song
22 | // 
23 | // Create Date:		10:21:31 01/03/2014 
24 | // Design Name:		FW-MBIST
25 | // Module Name:		MBIST_TAP_interface
26 | // Project Name: 	<-blank->
27 | // Target Devices:	[VirtexII-FG256]
28 | // Tool versions:  ISE 10.1(x64) QuestaSim 10.x(x64)
29 | // Description: 
30 | // The module designs to meet generic DFT and jtag test. It works on scan mode
31 | // and could bypass on other ways.
32 | // 
33 | // Dependencies: MBIST_CONTROLLER.v, MBIST_comparator_WF.v
34 | //
35 | // Revision: 
36 | // Revision 0.01 - File Created
37 | // Additional Comments: 
38 | //
39 | //////////////////////////////////////////////////////////////////////////////////
40 | /*
41 | module MBIST_TAP_interface (
42 | 	algsel_scan_in, algsel_scan_en, algsel_scan_out, algsel_clock
43 | 	);
44 | 
45 | 	input algsel_scan_in;
46 | 	input algsel_scan_en;
47 | 	input algsel_clock;
48 | 	output algsel_scan_out;
49 | 	
50 | endmodule
51 | */
52 | 


--------------------------------------------------------------------------------
/sources/MBIST_diagnostics.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | /*
 3 | //////////////////////////////////////////////////////////////////////////////////
 4 | //   Copyright 2013 - 2019 Yang Song
 5 | //   E-mail: googotohell@gmail.com
 6 | //
 7 | //   Licensed under the Apache License, Version 2.0 (the "License");
 8 | //   you may not use this file except in compliance with the License.
 9 | //   You may obtain a copy of the License at
10 | //
11 | //       http://www.apache.org/licenses/LICENSE-2.0
12 | //
13 | //   Unless required by applicable law or agreed to in writing, software
14 | //   distributed under the License is distributed on an "AS IS" BASIS,
15 | //   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 | //   See the License for the specific language governing permissions and
17 | //   limitations under the License.
18 | */
19 | //////////////////////////////////////////////////////////////////////////////////
20 | // Company: <-blank->
21 | // Engineer: Yang Song
22 | // 
23 | // Create Date:		10:21:31 01/03/2014 
24 | // Design Name:		FW-MBIST
25 | // Module Name:		MBIST_diagnostics
26 | // Project Name: 	<-blank->
27 | // Target Devices:	[VirtexII-FG256]
28 | // Tool versions:  ISE 10.1(x64) QuestaSim 10.x(x64)
29 | // Description: 
30 | // (MBIST_diagnostics block should exactly locate fail bits position and output
31 | // other details about errors. It needs to custom depend on UUT.)
32 | // 
33 | // Dependencies: None
34 | //
35 | // Revision:
36 | // Additional Comments: 
37 | //
38 | //////////////////////////////////////////////////////////////////////////////////
39 | /*
40 | module MBIST_diagnostics (
41 | 	diag_scan_in, diag_clk, rst_h, hold_l, debugz, diag_scan_out, diag_monitor
42 | 	);
43 | 	
44 | 	input diag_scan_in;
45 | 	input diag_clk;
46 | 	input rst_h;
47 | 	input hold_l;
48 | 	input debugz;
49 | 	output diag_scan_out;
50 | 	output diag_monitor;
51 | 	
52 | 	
53 | endmodule
54 | */
55 | 


--------------------------------------------------------------------------------
/sources/MBIST_BRAM_TOP.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | /*
 3 | //////////////////////////////////////////////////////////////////////////////////
 4 | //   Copyright 2013 - 2019 Yang Song
 5 | //   E-mail: googotohell@gmail.com
 6 | //
 7 | //   Licensed under the Apache License, Version 2.0 (the "License");
 8 | //   you may not use this file except in compliance with the License.
 9 | //   You may obtain a copy of the License at
10 | //
11 | //       http://www.apache.org/licenses/LICENSE-2.0
12 | //
13 | //   Unless required by applicable law or agreed to in writing, software
14 | //   distributed under the License is distributed on an "AS IS" BASIS,
15 | //   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 | //   See the License for the specific language governing permissions and
17 | //   limitations under the License.
18 | */
19 | //////////////////////////////////////////////////////////////////////////////////
20 | // Company: <-blank->
21 | // Engineer: Yang Song
22 | // 
23 | // Create Date:    15:54:30 01/14/2014 
24 | // Design Name:    FW-MBIST
25 | // Module Name:    MBIST_BRAM_TOP 
26 | // Project Name:   <-blank->
27 | // Target Devices: [VirtexII-FG256]
28 | // Tool versions:  ISE 10.1(x64) QuestaSim 10.x(x64)
29 | // Description: 
30 | // The top-level of FW-MBIST
31 | //
32 | // Dependencies: None
33 | //
34 | // Revision:
35 | // Revision 1.00 - Behavioral Simulation Pass and APR Complete 
36 | // Revision 0.01 - File Created
37 | // Additional Comments: 
38 | //
39 | //////////////////////////////////////////////////////////////////////////////////
40 | 
41 | module MBIST_BRAM_TOP (RESET_L, TEST_H, TCLK, ALG_SEL, FAIL, DONE);
42 | 
43 | 	parameter SHN = 4;
44 | 	parameter ASNET = 3;												// Preset algorithm selection bus width, LSB is 0.
45 | 	parameter UUTN = 10;												// Preset UUT number, LSB is 1.
46 | 	parameter ADA = 8;												// Preset address width for port A, LSB is 0.
47 | 	parameter ADB = 8;												// Preset address width for port B, LSB is 0.
48 | 	parameter DAA = 35;												// Preset data width for port A, LSB is 0.
49 | 	parameter DAB = 35;												// Preset data width for port B, LSB is 0.
50 | 	
51 | 	input RESET_L;														// Global asynchronous reset signal, active low.
52 | 	input TEST_H;														// Test start-up enable signal, active high.
53 | 	input TCLK;															// BIST Clock
54 | 	input [ASNET:0] ALG_SEL;										// Algorithm selection bus, bit wise mapping, active high.
55 | 	output FAIL;														// Test fail identifier, active high.
56 | 	output DONE;														// Test done identifier, active high.
57 | 
58 | 	wire [SHN:1] top_fail;
59 | 	wire [SHN:1] top_done;
60 | 	
61 | 	assign FAIL = |top_fail;
62 | 	assign DONE = &top_done;
63 | 	
64 | 	genvar k;
65 | 	generate
66 | 		
67 | 		for (k=1;k<=SHN;k=k+1) begin: SHELL
68 | 			MBIST_BRAM_SHELL #(
69 | 				.ASNET(ASNET),
70 | 				.UUTN(UUTN),
71 | 				.ADA(ADA),
72 | 				.ADB(ADB),
73 | 				.DAA(DAA),
74 | 				.DAB(DAB))
75 | 			MBLOCK (
76 | 				.RESET_L(RESET_L),
77 | 				.TEST_H(TEST_H),
78 | 				.TCLK(TCLK),
79 | 				.ALG_SEL(ALG_SEL),
80 | 				.FAIL(top_fail[k]),
81 | 				.DONE(top_done[k])
82 | 			);
83 | 		end	
84 | 		
85 | 	endgenerate	
86 | 	
87 | endmodule
88 | 


--------------------------------------------------------------------------------
/sources/MBIST_comparator_WF.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | /*
  3 | //////////////////////////////////////////////////////////////////////////////////
  4 | //   Copyright 2013 - 2019 Yang Song
  5 | //   E-mail: googotohell@gmail.com
  6 | //
  7 | //   Licensed under the Apache License, Version 2.0 (the "License");
  8 | //   you may not use this file except in compliance with the License.
  9 | //   You may obtain a copy of the License at
 10 | //
 11 | //       http://www.apache.org/licenses/LICENSE-2.0
 12 | //
 13 | //   Unless required by applicable law or agreed to in writing, software
 14 | //   distributed under the License is distributed on an "AS IS" BASIS,
 15 | //   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 16 | //   See the License for the specific language governing permissions and
 17 | //   limitations under the License.
 18 | */
 19 | //////////////////////////////////////////////////////////////////////////////////
 20 | // Company: <-blank->
 21 | // Engineer: Yang Song
 22 | // 
 23 | // Create Date:    13:25:10 01/04/2014 
 24 | // Design Name:    FW-MBIST
 25 | // Module Name:    MBIST_comparator_write_first 
 26 | // Project Name:   <-blank->
 27 | // Target Devices: [VirtexII-FG256]
 28 | // Tool versions:  ISE 10.1(x64) QuestaSim 10.x(x64)
 29 | // Description: 
 30 | // Data checker block use writing first for FPGA BRAM testing.
 31 | // Each negedge of active checking clock(not BIST Clock) will trigger data checking.
 32 | //
 33 | // Dependencies: MBIST_CONTROLLER.v, MBIST_algorithm_generator.v
 34 | //
 35 | // Revision:
 36 | // Revision 1.00 - Behavioral Simulation Pass 
 37 | // Revision 0.01 - File Created
 38 | // Additional Comments: 
 39 | //
 40 | //////////////////////////////////////////////////////////////////////////////////
 41 | 
 42 | module MBIST_comparator_write_first (
 43 |     reset, comp_en, comp_clk, check, capture, comp_alg_end, data_in, data_out, fail, done
 44 |     );
 45 | 	
 46 | 	parameter DW = 1;										// Define data width
 47 | 	
 48 |     input reset;											// Asynchronous reset, active high
 49 |     input comp_en;											// Block enable, active high
 50 | 	input comp_clk;										// BIST Clock
 51 | 	input check;											// Check Clock
 52 |     input capture;											// Capture input data enable, active high
 53 | 	input comp_alg_end;									// End point enable
 54 |     input [DW:0] data_in;								// Input Data in
 55 |     input [DW:0] data_out;								// Output Data in
 56 | 	output fail;											// Fail ID
 57 | 	output done;											// Done ID
 58 | 	
 59 | 	reg fail_diag;
 60 | 	reg [DW:0] comp_data;
 61 | 	reg done;
 62 | 	reg fail;
 63 | 	
 64 | 	// Comparator asynchronous reset
 65 | 	always @(reset) begin
 66 | 		if (reset) begin
 67 | 			assign comp_data = 0;
 68 | 			assign done = 0;
 69 | 			assign fail = 0;
 70 | 			assign fail_diag = 0;
 71 | 		end	
 72 | 		else begin
 73 | 			deassign comp_data;
 74 | 			deassign done;
 75 | 			deassign fail;
 76 | 			deassign fail_diag;
 77 | 		end
 78 | 	end
 79 | 	
 80 | 	// Fail signal arise 
 81 | 	always @(posedge fail_diag) begin
 82 | 		if (comp_en) begin
 83 | 			fail <= 1;
 84 | 			end
 85 | 		else begin
 86 | 			fail <= fail;
 87 | 		end
 88 | 	end
 89 | 	
 90 | 	// Done signal arise
 91 | 	always @(posedge comp_alg_end) begin
 92 | 		if (comp_en) begin
 93 | 			done <= 1;
 94 | 			end
 95 | 		else begin
 96 | 			done <= done;
 97 | 		end
 98 | 	end
 99 | 	
100 | 	// Capture input data
101 | 	always @(posedge comp_clk) begin
102 | 		if (comp_en) begin
103 | 			if (capture) begin
104 | 				comp_data <= data_in;
105 | 			end			
106 | 		end		
107 | 	end
108 | 	
109 | 	// Check output data
110 | 	always @(negedge check) begin
111 | 		if(comp_en) begin
112 | 			if (comp_data == data_out) begin
113 | 				fail_diag <= 0;
114 | 				end
115 | 			else begin
116 | 				fail_diag <= 1;
117 | 			end
118 | 		end
119 | 	end				
120 | 	
121 | endmodule
122 | 


--------------------------------------------------------------------------------
/sources/MBIST_CONTROLLER.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | /*
  3 | //////////////////////////////////////////////////////////////////////////////////
  4 | //   Copyright 2013 - 2019 Yang Song
  5 | //   E-mail: googotohell@gmail.com
  6 | //
  7 | //   Licensed under the Apache License, Version 2.0 (the "License");
  8 | //   you may not use this file except in compliance with the License.
  9 | //   You may obtain a copy of the License at
 10 | //
 11 | //       http://www.apache.org/licenses/LICENSE-2.0
 12 | //
 13 | //   Unless required by applicable law or agreed to in writing, software
 14 | //   distributed under the License is distributed on an "AS IS" BASIS,
 15 | //   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 16 | //   See the License for the specific language governing permissions and
 17 | //   limitations under the License.
 18 | */
 19 | //////////////////////////////////////////////////////////////////////////////////
 20 | // Company: <-blank->
 21 | // Engineer: Yang Song
 22 | // 
 23 | // Create Date:    13:53:47 12/30/2013 
 24 | // Design Name:    FW-MBIST
 25 | // Module Name:    MBIST_CONTROLLER 
 26 | // Project Name:   <-blank->
 27 | // Target Devices: [VirtexII-FG256]
 28 | // Tool versions:  ISE 10.1(x64) QuestaSim 10.x(x64)
 29 | // Description: 
 30 | // A controller implements memory BIST. Control process base on a 4 bits width FSM.
 31 | // This module also includes some sub-functional modules. For instance 
 32 | // Algorithm Generator Block, MBIST Diagnostics Block, TAP interface Block and more.
 33 | // Feel free to modify the FSM or to extend varietal sub-modules to meet the demand
 34 | // of project.
 35 | //
 36 | // Dependencies: None
 37 | //
 38 | // Revision:
 39 | // Revision 2.00 - Add March 2 algorithm 2/14/2014
 40 | // Revision 1.00 - Behavioral Simulation Pass for three UUTs. Only use Checkerboard.
 41 | // Revision 0.01 - File Created
 42 | // Additional Comments: 
 43 | //
 44 | //////////////////////////////////////////////////////////////////////////////////
 45 | 
 46 | module MBIST_controller (
 47 |    test_h, rst_l, bist_clk, fail_h, alg_end, tst_done, tst_capture, tst_check_ce, tst_ADDRA, tst_ADDRB, tst_DIA, tst_DIB, 
 48 | 	tst_WEA, tst_WEB, tst_ENA, tst_ENB, tst_RRSA, tst_RRSB, tst_algsel, inter_fail, inter_done
 49 |    );
 50 | 	
 51 | 	parameter ALGNUM = 3;												// Preset algorithm selection bus size, LSB is 0.
 52 | 	parameter ADDRA_W = 8;												// Preset address width for port A, LSB is 0.
 53 | 	parameter ADDRB_W = 8;												// Preset address width for port B, LSB is 0.
 54 | 	parameter DA_W = 35;													// Preset data width for port A, LSB is 0.
 55 | 	parameter DB_W = 35;													// Preset data width for port B, LSB is 0.
 56 | 	parameter ENUM = 3;													// Preset UUT enable control bus, LSB is 1.
 57 | 	
 58 | 	input test_h;															// Test start-up enable signal, active high.
 59 | 	input rst_l;															// Controller asynchronous reset signal, active low.
 60 | 	input bist_clk;														// BIST Clock
 61 | 	input [ALGNUM:0] tst_algsel;										// Algorithm selection bus, bit wise mapping, active high.
 62 | 	input [ENUM:1] inter_fail;											// Fail ID bus, input from all of UUT's comparators.
 63 | 	input [ENUM:1] inter_done;											// Done ID bus, input from all of UUT's comparators.
 64 | 	output fail_h;															// Fail signal output
 65 | 	output alg_end;														// Algorithm end signal output
 66 | 	output tst_done;														// Done signal output
 67 | 	output tst_WEA;														// Write enable control for port A
 68 | 	output tst_WEB;														// Write enable control for port B
 69 | 	output tst_ENA;														// Chip-sel enable control for port A
 70 | 	output tst_ENB;														// Chip-sel enable control for port B
 71 | 	output tst_RRSA;														// Reset control for port A
 72 | 	output tst_RRSB;														// Reset control for port B
 73 | 	output tst_capture;													// Input data capture enable to comparator, active high.
 74 | 	output tst_check_ce;													// Output data check enable to comparator, active high.
 75 | 	output [ADDRA_W:0] tst_ADDRA;										// Address output to port A
 76 | 	output [ADDRB_W:0] tst_ADDRB;										// Address output to port B
 77 | 	output [DA_W:0] tst_DIA;											// Data output to port A
 78 | 	output [DB_W:0] tst_DIB;											// Data output to port B	
 79 | 	
 80 | 	wor fail_h;
 81 | 	wand tst_done;
 82 | 	reg state_go;
 83 | 	reg [ENUM:1] tst_ENA;
 84 | 	reg [ENUM:1] tst_ENB;
 85 | 	reg alg_rst_h;
 86 | 	reg tst_RRSA;
 87 | 	reg tst_RRSB;
 88 | 	reg [3:0] t_state;
 89 | 	reg [2:0] rst_cnt;
 90 | 	reg i_next;
 91 | 	reg i_over;
 92 | 	reg i_lock;
 93 | 	reg i_first;
 94 | 	reg alg_start;
 95 | 	reg [ENUM:1] en_shift;
 96 | 	
 97 | 	genvar k;
 98 | 	generate
 99 | 	for (k=0;k<ENUM;k=k+1) begin: FAIL_DONE 
100 | 	assign fail_h = inter_fail[k+1];
101 | 	assign tst_done = inter_done[k+1];
102 | 	end
103 | 	endgenerate
104 | 	
105 | 	// Install testing algorithm core
106 | 	MBIST_algorithm_generator #(.as_ALGNUM(ALGNUM), .as_ADDRA_W(ADDRA_W), .as_ADDRB_W(ADDRB_W), .as_DA_W(DA_W), .as_DB_W(DB_W))
107 | 		BRAM_ALG (
108 | 			.as_algsel(tst_algsel),
109 | 			.as_rst(alg_rst_h),
110 | 			.as_en(alg_start),
111 | 			.as_clk(bist_clk),
112 | 			.as_done(alg_end),
113 | 			.as_ADDRA(tst_ADDRA),
114 | 			.as_ADDRB(tst_ADDRB),
115 | 			.as_DIA(tst_DIA),
116 | 			.as_DIB(tst_DIB),
117 | 			.as_WEA(tst_WEA),
118 | 			.as_WEB(tst_WEB),
119 | 			.as_cap(tst_capture),
120 | 			.as_check_ce(tst_check_ce)
121 | 			);	
122 | 	
123 | 	// Controller asynchronous reset
124 | 	always @(rst_l) begin
125 | 		if (~rst_l) begin
126 | 		assign rst_cnt = 0;
127 | 		assign t_state = 0;
128 | 		assign state_go = 0;
129 | 		assign alg_start = 0;
130 | 		assign alg_rst_h = 1;
131 | 		assign tst_RRSA = 1;
132 | 		assign tst_RRSB = 1;		
133 | 		assign tst_ENA = 0;
134 | 		assign tst_ENB = 0;		
135 | 		assign i_next = 0;
136 | 		assign i_over = 0;
137 | 		assign i_lock = 0;
138 | 		assign i_first = 0;
139 | 		assign en_shift = 1;
140 | 		end
141 | 		else begin		
142 | 		deassign rst_cnt;
143 | 		deassign t_state;
144 | 		deassign alg_start;
145 | 		deassign state_go;		
146 | 		deassign alg_rst_h;
147 | 		deassign tst_RRSA;
148 | 		deassign tst_RRSB;
149 | 		deassign tst_ENA;
150 | 		deassign tst_ENB;	
151 | 		deassign i_next;
152 | 		deassign i_over;
153 | 		deassign i_lock;
154 | 		deassign i_first;
155 | 		deassign en_shift;
156 | 		end
157 | 	end
158 | 	
159 | 	// MBIST_C(MBIST Controller) FSM control producer
160 | 	always @(negedge bist_clk) begin			
161 | 		if (test_h) begin
162 | 			if (tst_ENA[ENUM]) begin
163 | 				i_lock <= 1;
164 | 				end
165 | 			else begin
166 | 				i_lock <= i_lock;
167 | 				end
168 | 			if (rst_cnt[2]||i_next) begin
169 | 				t_state <= 4'b0001;
170 | 				rst_cnt <= 0;
171 | 				end		
172 | 			else if (i_next == 0&&tst_done == 1) begin
173 | 						t_state <= 4'b1111;
174 | 						end
175 | 				  else if (state_go) begin
176 | 							 t_state <= t_state + 1;
177 | 							 end
178 | 						 else if (i_first) begin
179 | 								rst_cnt <= rst_cnt + 1'b1;
180 | 								end
181 | 		end
182 | 	end
183 | 	
184 | 	// MBIST_C FSM Procedure, 4 bits width state machine 
185 | 	always @(posedge bist_clk) begin
186 | 		if (test_h) begin
187 | 			case (t_state)
188 | 				4'b0000: begin: s_RESET							// MBIST_C reset state
189 | 							tst_RRSA <= 1;
190 | 							tst_RRSB <= 1;
191 | 							alg_rst_h <= 1;
192 | 							tst_ENA <= 0;
193 | 							tst_ENB <= 0;
194 | 							en_shift = 1;
195 | 							i_over <= 0;
196 | 							i_first <= 1;							
197 | 							end
198 | 							
199 | 				4'b0001: begin: s_START							// MBIST_C start-up state
200 | 							tst_RRSA <= 0;
201 | 							tst_RRSB <= 0;
202 | 							alg_rst_h <= 0;																				
203 | 							state_go <= 1;
204 | 							i_next <= 0;
205 | 							end
206 | 							
207 | 				4'b0010: begin: s_ALGBEGIN						// MBIST_C algorithm start-up state
208 | 							i_first <= 0;
209 | 							tst_ENA <= en_shift;	
210 | 							alg_start <= 1;							
211 | 							end
212 | 							
213 | 				4'b0011: begin: s_WAIT							// MBIST_C algorithm running state
214 | 							if (alg_end) begin
215 | 							state_go <= 1;
216 | 							alg_rst_h <= 1;
217 | 							alg_start <= 0;
218 | 							tst_ENA <= 0;
219 | 							end
220 | 							else begin
221 | 							state_go <= 0;
222 | 							end
223 | 							end
224 | 							
225 | 				4'b0100: begin: s_ALGEND						// MBIST_C algorithm run over state														
226 | 							en_shift = en_shift<<1;
227 | 							end
228 | 							
229 | 				4'b0101: begin: s_NEXT							// MBIST_C access the next UUT state
230 | 							if (i_lock) begin								
231 | 								i_next <= 0;
232 | 								end
233 | 							else begin								
234 | 								i_next <= 1;
235 | 								end							
236 | 							state_go <= 0;
237 | 							end
238 | 							
239 | 				4'b1000: begin: s_FAIL							// MBIST_C reserve state for diagnostic test
240 | 				
241 | 							end
242 | 							
243 | 				4'b1111: begin: s_OVER							// MBIST_C test over state
244 | 							tst_RRSA <= 0;
245 | 							tst_RRSB <= 0;
246 | 							alg_rst_h <= 0;							
247 | 							tst_ENA <= 0;
248 | 							tst_ENB <= 0;							
249 | 							i_over <= 1;
250 | 							end
251 | 							
252 | 				default: begin: s_BACK							// MBIST_C reserve state for recover from error state 
253 | 				
254 | 							end							
255 | 			endcase
256 | 		end		
257 | 	end
258 | endmodule
259 | 


--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
/sources/MBIST_BRAM_SHELL.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | /*
  3 | //////////////////////////////////////////////////////////////////////////////////
  4 | //   Copyright 2013 - 2019 Yang Song
  5 | //   E-mail: googotohell@gmail.com
  6 | //
  7 | //   Licensed under the Apache License, Version 2.0 (the "License");
  8 | //   you may not use this file except in compliance with the License.
  9 | //   You may obtain a copy of the License at
 10 | //
 11 | //       http://www.apache.org/licenses/LICENSE-2.0
 12 | //
 13 | //   Unless required by applicable law or agreed to in writing, software
 14 | //   distributed under the License is distributed on an "AS IS" BASIS,
 15 | //   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 16 | //   See the License for the specific language governing permissions and
 17 | //   limitations under the License.
 18 | */
 19 | //////////////////////////////////////////////////////////////////////////////////
 20 | // Company: <-blank->
 21 | // Engineer: Yang Song
 22 | // 
 23 | // Create Date:		10:21:31 01/03/2014 
 24 | // Design Name:		FW-MBIST
 25 | // Module Name:		MBIST_BRAM_SHELL
 26 | // Project Name: 	<-blank->
 27 | // Target Devices:	[VirtexII-FG256]
 28 | // Tool versions:  ISE 10.1(x64) QuestaSim 10.x(x64)
 29 | // Description: 
 30 | // A shell for FW-MBIST, it assembles BIST conroller and comparators. Also could
 31 | // include UUTs( e.g. BRAMs on FPGA) or not, it's up to demand. Use writing first
 32 | // for write mode of BRAM. Auto-run memory testing algorithms on sort.
 33 | // 
 34 | // Dependencies: MBIST_CONTROLLER.v, MBIST_comparator_WF.v
 35 | //
 36 | // Revision:
 37 | // Revision 1.00 - Behavioral Simulation Pass for three UUTs. Only use Checkerboard. 
 38 | // Revision 0.01 - File Created
 39 | // Additional Comments: 
 40 | //
 41 | //////////////////////////////////////////////////////////////////////////////////
 42 | 
 43 | module MBIST_BRAM_SHELL (RESET_L, TEST_H, TCLK, ALG_SEL, FAIL, DONE);
 44 | 	
 45 | 	parameter ASNET = 3;												// Preset algorithm selection bus width, LSB is 0.
 46 | 	parameter UUTN = 10;												// Preset UUT number, LSB is 1.
 47 | 	parameter ADA = 8;												// Preset address width for port A, LSB is 0.
 48 | 	parameter ADB = 8;												// Preset address width for port B, LSB is 0.
 49 | 	parameter DAA = 35;												// Preset data width for port A, LSB is 0.
 50 | 	parameter DAB = 35;												// Preset data width for port B, LSB is 0.
 51 | 	
 52 | 	input RESET_L;														// Global asynchronous reset signal, active low.
 53 | 	input TEST_H;														// Test start-up enable signal, active high.
 54 | 	input TCLK;															// BIST Clock
 55 | 	input [ASNET:0] ALG_SEL;										// Algorithm selection bus, bit wise mapping, active high.
 56 | 	output FAIL;														// Test fail identifier, active high.
 57 | 	output DONE;														// Test done identifier, active high.
 58 | 		
 59 | 	wire [UUTN:1] c_fail;
 60 | 	wire [UUTN:1] c_done;
 61 | 	wire [ADA:0] c_addra;
 62 | 	wire [DAA:0] c_dia;
 63 | 	wire [DAA:0] c_doa [UUTN:1];
 64 | 	wire c_wea;
 65 | 	wire [UUTN:1] c_ena;
 66 | 	wire c_rrsa;
 67 | 	wire c_alg_end;
 68 | 	wire c_capture;
 69 | 	wire c_check;
 70 | 	wire c_check_ce;
 71 | 	
 72 | 	// Install BIST controller
 73 | 	MBIST_controller #(
 74 | 		.ALGNUM(ASNET),
 75 | 		.ADDRA_W(ADA),
 76 | 		.ADDRB_W(ADB),
 77 | 		.DA_W(DAA),
 78 | 		.DB_W(DAB),
 79 | 		.ENUM(UUTN))
 80 | 	CONTROLLER (
 81 | 		.test_h(TEST_H),
 82 | 		.rst_l(RESET_L),
 83 | 		.bist_clk(TCLK),
 84 | 		.tst_algsel(ALG_SEL),
 85 | 		.inter_fail(c_fail),
 86 | 		.inter_done(c_done),
 87 | 		.fail_h(FAIL),
 88 | 		.alg_end(c_alg_end),
 89 | 		.tst_done(DONE),
 90 | 		.tst_capture(c_capture),
 91 | 		.tst_check_ce(c_check_ce),
 92 | 		.tst_WEA(c_wea),
 93 | 		.tst_WEB(),
 94 | 		.tst_ENA(c_ena),
 95 | 		.tst_ENB(),
 96 | 		.tst_RRSA(c_rrsa),
 97 | 		.tst_RRSB(),
 98 | 		.tst_ADDRA(c_addra),
 99 | 		.tst_ADDRB(),
100 | 		.tst_DIA(c_dia),
101 | 		.tst_DIB()
102 | 	);
103 | 	
104 | 	// Install a clockgating for comparator's check-clk. It also coould be replaced by DCM or more complicate function.
105 | 	// BUFGCE: Global Clock Buffer with Clock Enable (active high)
106 |     //         Virtex-II/II-Pro/4/5, Spartan-3/3E/3A
107 |     // Xilinx HDL Language Template, version 10.1.2
108 | 
109 |    BUFGCE BUFGCE_inst (
110 |       .O(c_check),   // Clock buffer output
111 |       .CE(c_check_ce), // Clock enable input
112 |       .I(TCLK)    // Clock buffer input
113 |    );
114 | 
115 |    // End of BUFGCE_inst instantiation	
116 | 	
117 | 	// Generate UUT blocks and corresponding comparators.
118 | 	genvar i;
119 | 	generate
120 | 	
121 | 	for (i=1;i<=UUTN;i=i+1) begin: BRAM_COMP
122 | 	
123 |    // RAMB16_S36: Virtex-II/II-Pro, Spartan-3/3E 512 x 32 + 4 Parity bits Single-Port RAM
124 |    // Xilinx HDL Language Template, version 10.1.2
125 | 
126 |    RAMB16_S36 #(
127 |       .INIT(36'h000000000),  // Initial values of RAM registers
128 |       .SRVAL(36'h000000000), // Output values upon SSR assertion
129 |       .WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
130 | 
131 |       // The following INIT_xx declarations specify the initial contents of the RAM
132 |       // Address 0 to 127
133 |       .INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
134 |       .INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
135 |       .INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
136 |       .INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
137 |       .INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
138 |       .INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
139 |       .INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
140 |       .INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
141 |       .INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
142 |       .INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
143 |       .INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
144 |       .INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
145 |       .INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
146 |       .INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
147 |       .INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
148 |       .INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
149 |       // Address 128 to 255
150 |       .INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
151 |       .INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
152 |       .INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
153 |       .INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
154 |       .INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
155 |       .INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
156 |       .INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
157 |       .INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
158 |       .INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
159 |       .INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
160 |       .INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
161 |       .INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
162 |       .INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
163 |       .INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
164 |       .INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
165 |       .INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
166 |       // Address 256 to 383
167 |       .INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
168 |       .INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
169 |       .INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
170 |       .INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
171 |       .INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
172 |       .INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
173 |       .INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
174 |       .INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
175 |       .INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
176 |       .INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
177 |       .INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
178 |       .INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
179 |       .INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
180 |       .INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
181 |       .INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
182 |       .INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
183 |       // Address 384 to 511
184 |       .INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
185 |       .INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
186 |       .INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
187 |       .INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
188 |       .INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
189 |       .INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
190 |       .INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
191 |       .INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
192 |       .INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
193 |       .INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
194 |       .INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
195 |       .INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
196 |       .INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
197 |       .INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
198 |       .INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
199 |       .INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
200 | 
201 |       // The next set of INITP_xx are for the parity bits
202 |       // Address 0 to 127
203 |       .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
204 |       .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
205 |       // Address 128 to 255
206 |       .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
207 |       .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
208 |       // Address 256 to 383
209 |       .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
210 |       .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
211 |       // Address 384 to 511
212 |       .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
213 |       .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
214 |    ) RAMB16_S36_inst (
215 |       .DO(c_doa[i][31:0]),      // 32-bit Data Output
216 |       .DOP(c_doa[i][35:32]),    // 4-bit parity Output
217 |       .ADDR(c_addra),  // 9-bit Address Input
218 |       .CLK(TCLK),    // Clock
219 |       .DI(c_dia[31:0]),      // 32-bit Data Input
220 |       .DIP(c_dia[35:32]),    // 4-bit parity Input
221 |       .EN(c_ena[i]),      // RAM Enable Input
222 |       .SSR(c_rrsa),    // Synchronous Set/Reset Input
223 |       .WE(c_wea)       // Write Enable Input
224 |    );
225 | 
226 |    // End of RAMB16_S36_inst instantiation
227 | 	
228 | 	MBIST_comparator_write_first #(.DW(DAA))
229 | 		COMPARATOR (
230 | 			.reset(c_rrsa),
231 | 			.comp_en(c_ena[i]),
232 | 			.comp_clk(TCLK), 
233 | 			.check(c_check), 
234 | 			.capture(c_capture), 
235 | 			.comp_alg_end(c_alg_end), 
236 | 			.data_in(c_dia), 
237 | 			.data_out(c_doa[i]), 
238 | 			.fail(c_fail[i]), 
239 | 			.done(c_done[i])
240 | 	);
241 | 	
242 | 	end
243 | 	endgenerate
244 | 
245 | endmodule
246 | 


--------------------------------------------------------------------------------
/sources/MBIST_algorithm_generator.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | /*
  3 | //////////////////////////////////////////////////////////////////////////////////
  4 | //   Copyright 2013 - 2019 Yang Song
  5 | //   E-mail: googotohell@gmail.com
  6 | //
  7 | //   Licensed under the Apache License, Version 2.0 (the "License");
  8 | //   you may not use this file except in compliance with the License.
  9 | //   You may obtain a copy of the License at
 10 | //
 11 | //       http://www.apache.org/licenses/LICENSE-2.0
 12 | //
 13 | //   Unless required by applicable law or agreed to in writing, software
 14 | //   distributed under the License is distributed on an "AS IS" BASIS,
 15 | //   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 16 | //   See the License for the specific language governing permissions and
 17 | //   limitations under the License.
 18 | */
 19 | //////////////////////////////////////////////////////////////////////////////////
 20 | // Company: <-blank->
 21 | // Engineer: Yang Song
 22 | // 
 23 | // Create Date:    13:53:47 12/30/2013 
 24 | // Design Name:    FW-MBIST
 25 | // Module Name:    MBIST_algorithm_generator 
 26 | // Project Name:   <-blank->
 27 | // Target Devices: [VirtexII-FG256]
 28 | // Tool versions:  ISE 10.1(x64) QuestaSim 10.x(x64)
 29 | // Description: 
 30 | // MBIST algorithms generation core is implemented by a 8 bits width FSM. It's
 31 | // simple to contain more algorithms and states by enlarge FSM width.
 32 | // Checkerboard and March 2 have existed. Please pay attension to keep the
 33 | // state machine clousre.
 34 | //
 35 | // Dependencies: None
 36 | //
 37 | // Revision:
 38 | // Revision 2.00 - Add March 2 algorithm 2/14/2014
 39 | // Revision 1.00 - Behavioral Simulation Pass for three UUTs. Only use Checkerboard.
 40 | // Revision 0.01 - File Created
 41 | // Additional Comments: 
 42 | //
 43 | //////////////////////////////////////////////////////////////////////////////////
 44 | 
 45 | module MBIST_algorithm_generator (
 46 | 	as_algsel, as_rst, as_en, as_clk, as_done, as_cap, as_check_ce, as_ADDRA, as_ADDRB, as_DIA, as_DIB, as_WEA, as_WEB
 47 | 	);
 48 | 	
 49 | 	parameter as_ALGNUM = 1;												// Preset algorithm selection bus width, LSB is 0.
 50 | 	parameter as_ADDRA_W = 1;												// Preset address width for port A, LSB is 0.
 51 | 	parameter as_ADDRB_W = 1;												// Preset address width for port B, LSB is 0.
 52 | 	parameter as_DA_W = 1;													// Preset data width for port A, LSB is 0.
 53 | 	parameter as_DB_W = 1;													// Preset data width for port B, LSB is 0.
 54 | 	
 55 | 	input [as_ALGNUM:0] as_algsel;										// Algorithm selection bus, bit wise mapping, active high.
 56 | 	input as_rst;																// AG asynchronous reset signal, active high.
 57 | 	input as_en;																// AG enable signal, active high.
 58 | 	input as_clk;																// BIST Clock
 59 | 	output as_cap;																// Input data capture enable to comparator, active high.	
 60 | 	output as_done;															// Done signal output
 61 | 	output as_ADDRA;															// Address output to port A
 62 | 	output as_ADDRB;															// Address output to port B
 63 | 	output as_DIA;																// Data output to port A
 64 | 	output as_DIB;																// Data output to port B
 65 | 	output as_WEA;																// Write enable control for port A
 66 | 	output as_WEB;																// Write enable control for port B
 67 | 	output as_check_ce;														// Output data check enable for comparator, active high.
 68 | 	
 69 | 	reg as_WEA;
 70 | 	reg as_WEB;
 71 | 	reg [as_ADDRA_W:0] as_ADDRA;
 72 | 	reg [as_ADDRB_W:0] as_ADDRB;
 73 | 	reg [as_DA_W:0] as_DIA;
 74 | 	reg [as_DB_W:0] as_DIB;
 75 | 	reg [as_ALGNUM:0] algsel;
 76 | 	reg as_state_go;
 77 | 	reg [7:0] as_state;
 78 | 	reg [1:0] alg_cnt;
 79 | 	reg alg_done;
 80 | 	reg as_done;
 81 | 	reg as_cap;
 82 | 	reg as_check_ce;
 83 | 	reg alg_cap;
 84 | 	reg alg_begin;
 85 | 	reg [1:0] alg_march2_cnt;
 86 | 	
 87 | 	// AG asynchronous reset
 88 | 	always @(as_rst) begin
 89 | 		if (as_rst) begin
 90 | 		assign as_ADDRA = 0;
 91 | 		assign as_ADDRB = 0;
 92 | 		assign as_DIA = 0;
 93 | 		assign as_DIB = 0;
 94 | 		assign as_WEA = 0;
 95 | 		assign as_WEB = 0;
 96 | 		assign algsel = 0;
 97 | 		assign as_state_go = 0;
 98 | 		assign as_state = 0;
 99 | 		assign alg_cnt = 0;
100 | 		assign alg_done = 0;
101 | 		assign as_done = 0;
102 | 		assign as_cap = 0;
103 | 		assign as_check_ce = 0;
104 | 		assign alg_cap = 0;
105 | 		assign alg_begin = 0;
106 | 		assign alg_march2_cnt = 0;
107 | 		end
108 | 		else begin
109 | 		deassign as_ADDRA;
110 | 		deassign as_ADDRB;
111 | 		deassign as_DIA;
112 | 		deassign as_DIB;
113 | 		deassign as_WEA;
114 | 		deassign as_WEB;
115 | 		deassign algsel;
116 | 		deassign as_state_go;
117 | 		deassign as_state;
118 | 		deassign alg_cnt;
119 | 		deassign alg_done;
120 | 		deassign as_done;
121 | 		deassign as_cap;
122 | 		deassign as_check_ce;
123 | 		deassign alg_cap;
124 | 		deassign alg_begin;
125 | 		deassign alg_march2_cnt;
126 | 		end
127 | 	end
128 | 	
129 | 	// AG FSM control producer
130 | 	always @(posedge as_clk) begin
131 | 	if (as_en) begin	
132 | 		if (alg_cap) begin
133 | 			algsel <= as_algsel;
134 | 			alg_begin <= 1;
135 | 			end
136 | 		else begin
137 | 			if (alg_done) begin
138 | 				case (alg_cnt)
139 | 					2'b00: as_state <= 8'b0000_0000;				// Test algorithm 1 done
140 | 					2'b01: as_state <= 8'b0000_0101;				// Test algorithm 2 done
141 | 					2'b10: as_state <= 8'b0000_1100;				// Test algorithm 3 done
142 | 					2'b11: as_state <= 8'b0000_1111;				// Test algorithm 4 done
143 | 				endcase
144 | 				algsel <= algsel<<1;
145 | 			end		
146 | 			else if (as_state_go) begin
147 | 					  as_state <= as_state + 1;
148 | 				  end
149 | 		end		
150 | 	end	
151 | 	end
152 | 	
153 | 	// AG FSM Procedure, 8 bits width state machine
154 | 	always @(negedge as_clk) begin
155 | 		if (as_en) begin
156 | 		if (alg_begin) begin
157 | 			alg_cap <= 0;
158 | 			if (algsel[as_ALGNUM]) begin
159 | 				case (as_state)
160 | 					8'b0000_0000: begin: initial_checker_board								// Initial Checkerboard Algorithm
161 | 									  alg_done <= 0;
162 | 									  as_WEA <= 1;
163 | 									  as_ADDRA <= 0;
164 | 									  as_DIA <= 36'hAAAAAAAAA;
165 | 									  as_state_go <= 1;
166 | 									  as_check_ce <= 1;
167 | 									  as_cap <= 1;
168 | 									  end
169 | 					8'b0000_0001: begin: up_write_checker_board								// Checkerboard Step 1
170 | 									  if (~as_ADDRA) begin									  
171 | 									  as_state_go <= 0;									  
172 | 									  end
173 | 									  else begin
174 | 									  as_state_go <= 1;
175 | 									  as_WEA <= 0;
176 | 									  end									  
177 | 									  as_DIA <= ~as_DIA;
178 | 									  as_ADDRA <= as_ADDRA + 1'b1;
179 | 									  end
180 | 					8'b0000_0010: begin: up_read_checker_board								// Checkerboard Step 2
181 | 									  if (~as_ADDRA) begin
182 | 									  as_state_go <= 0;
183 | 									  as_DIA <= ~as_DIA;									  
184 | 									  end
185 | 									  else begin
186 | 									  as_WEA <= 1;
187 | 									  as_DIA <= 36'h555555555;
188 | 									  as_state_go <= 1;
189 | 									  end									  									  
190 | 									  as_ADDRA <= as_ADDRA + 1'b1;
191 | 									  end
192 | 					8'b0000_0011: begin: up_write_inverse_checker_board					// Checkerboard Step 3
193 | 									  if (~as_ADDRA) begin
194 | 									  as_state_go <= 0;								  
195 | 									  end
196 | 									  else begin
197 | 									  as_state_go <= 1;
198 | 									  as_WEA <= 0;
199 | 									  end
200 | 									  as_DIA <= ~as_DIA;
201 | 									  as_ADDRA <= as_ADDRA + 1'b1;
202 | 									  end
203 | 					8'b0000_0100: begin: up_read_inverse_checker_board						// Checkerboard Step 4
204 | 									  if (~as_ADDRA) begin
205 | 									  as_state_go <= 0;
206 | 									  as_DIA <= ~as_DIA;
207 | 									  as_ADDRA <= as_ADDRA + 1'b1;
208 | 									  end
209 | 									  else begin									  
210 | 									  alg_cnt <= alg_cnt + 1;
211 | 									  alg_done <= 1;
212 | 									  as_check_ce <= 0;
213 | 									  as_cap <= 0;
214 | 									  end
215 | 									  end
216 | 									  
217 | 					8'b0000_0101: begin: initial_march_2									// Initial March 2
218 | 									  alg_done <= 0;
219 | 									  as_WEA <= 1;
220 | 									  as_ADDRA <= 0;
221 | 									  as_DIA <= 36'h000000000;
222 | 									  as_state_go <= 1;
223 | 									  as_check_ce <= 1;
224 | 									  as_cap <= 1;
225 | 									  end
226 | 					8'b0000_0110: begin: march_2_step_1									// March 2 Step 1 up - Write 0
227 | 									  if (~as_ADDRA) begin									  
228 | 									  as_state_go <= 0;									  
229 | 									  end
230 | 									  else begin
231 | 									  as_state_go <= 1;
232 | 									  as_WEA <= 0;									  
233 | 									  alg_march2_cnt <= 2'b00;
234 | 									  end								  
235 | 									  as_ADDRA <= as_ADDRA + 1'b1;
236 | 									  end
237 | 					8'b0000_0111: begin: march_2_step_2									// March 2 Step 2 up - Read 0, Write 1, Read 1									  
238 | 									  if (~as_ADDRA) begin									  
239 | 											as_state_go <= 0;									  
240 | 											end
241 | 									  else if (alg_march2_cnt == 2'b10) begin
242 | 											as_state_go <= 1;									  
243 | 											end
244 | 									  case (alg_march2_cnt)
245 | 											2'b00: begin
246 | 														as_WEA <= 1;
247 | 														as_DIA <= 36'hfffffffff;
248 | 													 end
249 | 											2'b01: begin
250 | 														as_WEA <= 0;														
251 | 													 end
252 | 											2'b10: begin
253 | 														as_ADDRA <= as_ADDRA + 1'b1;
254 | 														if (~as_ADDRA) as_DIA <= 36'h000000000;
255 | 													 end
256 | 									  endcase
257 | 									  if (alg_march2_cnt == 2'b10)
258 | 									  alg_march2_cnt <= 0;
259 | 									  else
260 | 									  alg_march2_cnt <= alg_march2_cnt + 1'b1;
261 | 									  end
262 | 					8'b0000_1000: begin: march_2_step_3									// March 2 Step 3 up - Read 1, Write 0, Read 0
263 | 									  if (~as_ADDRA) begin									  
264 | 											as_state_go <= 0;									  
265 | 											end
266 | 									  else if (alg_march2_cnt == 2'b10) begin
267 | 											as_state_go <= 1;									  
268 | 											end
269 | 									  case (alg_march2_cnt)
270 | 											2'b00: begin
271 | 														as_WEA <= 1;
272 | 														as_DIA <= 36'h000000000;
273 | 													 end
274 | 											2'b01: begin
275 | 														as_WEA <= 0;														
276 | 													 end
277 | 											2'b10: begin
278 | 														if (~as_ADDRA) begin
279 | 															as_DIA <= 36'hfffffffff;
280 | 															as_ADDRA <= as_ADDRA + 1'b1;
281 | 														end
282 | 													 end
283 | 									  endcase
284 | 									  if (alg_march2_cnt == 2'b10)
285 | 									  alg_march2_cnt <= 0;
286 | 									  else
287 | 									  alg_march2_cnt <= alg_march2_cnt + 1'b1;
288 | 									  end
289 | 					8'b0000_1001: begin: march_2_step_4									// March 2 Step 4 down - Read 0, Write 1, Read 1
290 | 									  if (as_ADDRA) begin									  
291 | 											as_state_go <= 0;									  
292 | 											end
293 | 									  else if (alg_march2_cnt == 2'b10) begin
294 | 											as_state_go <= 1;									  
295 | 											end
296 | 									  case (alg_march2_cnt)
297 | 											2'b00: begin
298 | 														as_WEA <= 1;
299 | 														as_DIA <= 36'hfffffffff;
300 | 													 end
301 | 											2'b01: begin
302 | 														as_WEA <= 0;														
303 | 													 end
304 | 											2'b10: begin
305 | 														as_ADDRA <= as_ADDRA - 1'b1;
306 | 														if (as_ADDRA) as_DIA <= 36'h000000000;
307 | 													 end
308 | 									  endcase
309 | 									  if (alg_march2_cnt == 2'b10)
310 | 									  alg_march2_cnt <= 0;
311 | 									  else
312 | 									  alg_march2_cnt <= alg_march2_cnt + 1'b1;
313 | 									  end									  
314 | 					8'b0000_1010: begin: march_2_step_5									// March 2 Step 5 down - Read 1, Write 0, Read 0
315 | 									  if (as_ADDRA) begin									  
316 | 											as_state_go <= 0;									  
317 | 											end
318 | 									  else if (alg_march2_cnt == 2'b10) begin
319 | 											as_state_go <= 1;									  
320 | 											end
321 | 									  case (alg_march2_cnt)
322 | 											2'b00: begin
323 | 														as_WEA <= 1;
324 | 														as_DIA <= 36'h000000000;
325 | 													 end
326 | 											2'b01: begin
327 | 														as_WEA <= 0;														
328 | 													 end
329 | 											2'b10: begin
330 | 														as_ADDRA <= as_ADDRA - 1'b1;
331 | 														if (as_ADDRA) as_DIA <= 36'hfffffffff;
332 | 													 end
333 | 									  endcase
334 | 									  if (alg_march2_cnt == 2'b10)
335 | 									  alg_march2_cnt <= 0;
336 | 									  else
337 | 									  alg_march2_cnt <= alg_march2_cnt + 1'b1;
338 | 									  end									  
339 | 					8'b0000_1011: begin: march_2_step_6									// March 2 Step 6 down - Read 0
340 | 									  if (as_ADDRA) begin
341 | 									  as_state_go <= 0;									  
342 | 									  as_ADDRA <= as_ADDRA - 1'b1;
343 | 									  end
344 | 									  else begin									  
345 | 									  alg_cnt <= alg_cnt + 1;
346 | 									  alg_done <= 1;
347 | 									  as_check_ce <= 0;
348 | 									  as_cap <= 0;
349 | 									  end 
350 | 									  end
351 | 									  
352 | 					8'b0000_1100: begin: algorithm_2_step_2									// Algorithm 2 Step 2
353 | 									   
354 | 									  end
355 | 					8'b0000_1101: begin: algorithm_2_step_3									// Algorithm 2 Step 3
356 | 									   
357 | 									  end
358 | 					8'b0000_1110: begin: algorithm_2_step_4									// Algorithm 2 Step 4
359 | 									   
360 | 									  end
361 | 									  
362 | 					8'b0000_1111: begin: initial_algorithm_3									// Initial Algorithm 3
363 | 									   
364 | 									  end
365 | 					8'b0001_0000: begin: algorithm_3_step_1									// Algorithm 3 Step 1
366 | 									   
367 | 									  end
368 | 					8'b0001_0001: begin: algorithm_3_step_2									// Algorithm 3 Step 2
369 | 									  
370 | 									  end
371 | 					8'b0001_0010: begin: algorithm_3_step_3									// Algorithm 3 Step 3
372 | 									   
373 | 									  end
374 | 					8'b0001_0011: begin: algorithm_3_step_4									// Algorithm 3 Step 4
375 | 									   
376 | 									  end
377 | 				endcase
378 | 			end
379 | 			else begin
380 | 				  if (alg_cnt == 2'b11) begin
381 | 						as_done <= 1;
382 | 						end
383 | 				  else begin
384 | 						alg_cnt <= alg_cnt + 1;
385 | 						alg_done <= 1;
386 | 						end
387 | 			end
388 | 		end
389 | 		else begin
390 | 			  alg_cap <= 1;
391 | 		end
392 | 		end
393 | 	end
394 | 			
395 | endmodule
396 | 


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