├── .gitignore ├── AUTHORS.md ├── AXI4.pro ├── Axi4 ├── Axi4.pro ├── RunAllTests.pro ├── RunAllTestsVti.pro ├── RunDemoTests.pro ├── RunDemoTestsVti.pro ├── RunDemoTests_GenericSignals.pro ├── TestCases │ ├── OsvvmTestCommonPkg.vhd │ ├── TbAxi4_AlertLogIDManager.vhd │ ├── TbAxi4_AlertLogIDMemory.vhd │ ├── TbAxi4_AlertLogIDSubordinate.vhd │ ├── TbAxi4_AxSizeManagerMemory1.vhd │ ├── TbAxi4_AxSizeManagerMemory2.vhd │ ├── TbAxi4_AxiIfOptionsManagerMemory.vhd │ ├── TbAxi4_AxiIfOptionsManagerSubordinate.vhd │ ├── TbAxi4_AxiManagerRandomTiming1.vhd │ ├── TbAxi4_AxiManagerRandomTiming2.vhd │ ├── TbAxi4_AxiMemoryRandomTiming1.vhd │ ├── TbAxi4_AxiMemoryRandomTiming2.vhd │ ├── TbAxi4_AxiSubordinateRandomTiming1.vhd │ ├── TbAxi4_AxiSubordinateRandomTiming2.vhd │ ├── TbAxi4_AxiXResp.vhd │ ├── TbAxi4_AxiXResp2_Enum.vhd │ ├── TbAxi4_AxiXResp3_slv.vhd │ ├── TbAxi4_BasicBurst.vhd │ ├── TbAxi4_BasicReadWrite.vhd │ ├── TbAxi4_DemoErrorMemoryReadWrite1.vhd │ ├── TbAxi4_DemoMemoryReadWrite1.vhd │ ├── TbAxi4_ManagerMemoryRandomTiming1.vhd │ ├── TbAxi4_ManagerRandomTiming1.vhd │ ├── TbAxi4_ManagerRandomTimingAsync1.vhd │ ├── TbAxi4_ManagerSubordinateRandomTiming1.vhd │ ├── TbAxi4_ManagerSubordinateRandomTimingAsync1.vhd │ ├── TbAxi4_MemoryAsync.vhd │ ├── TbAxi4_MemoryBurst1.vhd │ ├── TbAxi4_MemoryBurst2.vhd │ ├── TbAxi4_MemoryBurstAsync1.vhd │ ├── TbAxi4_MemoryBurstAsyncPattern1.vhd │ ├── TbAxi4_MemoryBurstAsyncPattern2.vhd │ ├── TbAxi4_MemoryBurstByte1.vhd │ ├── TbAxi4_MemoryBurstBytePattern1.vhd │ ├── TbAxi4_MemoryBurstPattern1.vhd │ ├── TbAxi4_MemoryBurstPattern2.vhd │ ├── TbAxi4_MemoryBurstSparse1.vhd │ ├── TbAxi4_MemoryRandomTiming1.vhd │ ├── TbAxi4_MemoryRandomTimingAsync1.vhd │ ├── TbAxi4_MemoryReadWrite1.vhd │ ├── TbAxi4_MemoryReadWrite2.vhd │ ├── TbAxi4_MemoryReadWriteDebug1.vhd │ ├── TbAxi4_MultipleDriversManager.vhd │ ├── TbAxi4_MultipleDriversMemory.vhd │ ├── TbAxi4_MultipleDriversSubordinate.vhd │ ├── TbAxi4_NoRandomTiming1.vhd │ ├── TbAxi4_RandomReadWrite.vhd │ ├── TbAxi4_RandomReadWriteByte1.vhd │ ├── TbAxi4_ReadWriteAsync1.vhd │ ├── TbAxi4_ReadWriteAsync2.vhd │ ├── TbAxi4_ReadWriteAsync3.vhd │ ├── TbAxi4_ReadWriteAsync4.vhd │ ├── TbAxi4_ReadyTimingManager.vhd │ ├── TbAxi4_ReadyTimingMemory.vhd │ ├── TbAxi4_ReadyTimingSubordinate.vhd │ ├── TbAxi4_ReleaseAcquireManager1.vhd │ ├── TbAxi4_ReleaseAcquireMemory1.vhd │ ├── TbAxi4_ReleaseAcquireSubordinate1.vhd │ ├── TbAxi4_SubordinateRandomTiming1.vhd │ ├── TbAxi4_SubordinateReadWrite1.vhd │ ├── TbAxi4_SubordinateReadWrite2.vhd │ ├── TbAxi4_SubordinateReadWrite3.vhd │ ├── TbAxi4_SubordinateReadWriteAsync1.vhd │ ├── TbAxi4_SubordinateReadWriteAsync2.vhd │ ├── TbAxi4_TimeOutManager.vhd │ ├── TbAxi4_TimeOutMemory.vhd │ ├── TbAxi4_TimeOutSubordinate.vhd │ ├── TbAxi4_TransactionApiManager.vhd │ ├── TbAxi4_TransactionApiManagerBurst.vhd │ ├── TbAxi4_TransactionApiMemory.vhd │ ├── TbAxi4_TransactionApiMemoryBurst.vhd │ ├── TbAxi4_TransactionApiSubordinate.vhd │ ├── TbAxi4_ValidTimingBurstManager.vhd │ ├── TbAxi4_ValidTimingBurstMemory.vhd │ ├── TbAxi4_ValidTimingManager.vhd │ ├── TbAxi4_ValidTimingMemory.vhd │ ├── TbAxi4_ValidTimingSubordinate.vhd │ ├── TestCases.pro │ ├── TestCasesWithError.pro │ ├── TestCases_Burst.pro │ └── TestCases_NoBurst.pro ├── src │ ├── Axi4ComponentPkg.vhd │ ├── Axi4ComponentVtiPkg.vhd │ ├── Axi4Context.vhd │ ├── Axi4GenericSignalsPkg.vhd │ ├── Axi4Manager.vhd │ ├── Axi4ManagerVti.vhd │ ├── Axi4Memory.vhd │ ├── Axi4MemoryVti.vhd │ ├── Axi4Monitor_dummy.vhd │ ├── Axi4PassThru.vhd │ ├── Axi4Subordinate.vhd │ ├── Axi4SubordinateVti.vhd │ ├── build.pro │ └── deprecated │ │ ├── Axi4Manager_xilinx.vhd │ │ └── Axi4Memory_xilinx.vhd ├── testbench │ ├── TbAxi4.vhd │ ├── TbAxi4Memory.vhd │ ├── TestCtrl_e.vhd │ └── testbench.pro ├── testbenchVti │ ├── TbAxi4.vhd │ ├── TbAxi4Memory.vhd │ ├── TestCtrl_e.vhd │ └── testbenchVti.pro ├── testbench_GenericSignals │ ├── TbAxi4.vhd │ ├── TbAxi4Memory.vhd │ ├── TestCtrl_e.vhd │ └── build.pro ├── testbench_MultipleMemory │ ├── TbAxi4_MultipleMemory.vhd │ ├── TbAxi4_MultipleMemory_Generate.vhd │ ├── TbAxi4_Separate1.vhd │ ├── TbAxi4_Shared1.vhd │ ├── TestCtrl_e.vhd │ ├── testbench_MultipleMemory.pro │ └── testbench_MultipleMemory_Generate.pro ├── testbench_interrupt │ ├── README.md │ ├── TbAxi4Memory.vhd │ ├── TbAxi4_Interrupt1.vhd │ ├── TbAxi4_Interrupt2.vhd │ ├── TbAxi4_InterruptBurst1.vhd │ ├── TbAxi4_InterruptBurst2.vhd │ ├── TbAxi4_InterruptNoHandler1.vhd │ ├── TbAxi4_InterruptNoHandler2.vhd │ ├── TestCtrl_e.vhd │ └── testbench_interrupt.pro └── testbench_xilinx │ ├── TbAxi4.vhd │ ├── TbAxi4Memory.vhd │ ├── TbAxi4_DemoMemoryReadWrite1.vhd │ ├── TestCtrl_e.vhd │ ├── build.pro │ └── build_one.pro ├── Axi4Lite ├── Axi4Lite.pro ├── RunAllTests.pro ├── RunDemoTests.pro ├── TestCases │ ├── RunAllTests.pro │ ├── RunDemoTests.pro │ ├── TbAxi4_AxiXResp.vhd │ ├── TbAxi4_AxiXResp2_Enum.vhd │ ├── TbAxi4_BasicReadWrite.vhd │ ├── TbAxi4_ManagerMemoryRandomTiming1.vhd │ ├── TbAxi4_ManagerRandomTiming1.vhd │ ├── TbAxi4_ManagerSubordinateRandomTiming1.vhd │ ├── TbAxi4_MemoryRandomTiming1.vhd │ ├── TbAxi4_MemoryReadWrite1.vhd │ ├── TbAxi4_NoRandomTiming1.vhd │ ├── TbAxi4_RandomReadWrite.vhd │ ├── TbAxi4_RandomReadWriteByte.vhd │ ├── TbAxi4_ReadWriteAsync1.vhd │ ├── TbAxi4_ReadWriteAsync2.vhd │ ├── TbAxi4_ReadWriteAsync3.vhd │ ├── TbAxi4_SubordinateRandomTiming1.vhd │ ├── TbAxi4_TimeOut.vhd │ ├── TbAxi4_WriteOptions.vhd │ └── archive │ │ ├── TbAxi4_BasicBurst.vhd │ │ └── TbAxi4_MemoryBurst1.vhd ├── src │ ├── Axi4LiteComponentPkg.vhd │ ├── Axi4LiteContext.vhd │ ├── Axi4LiteManager.vhd │ ├── Axi4LiteMemory.vhd │ ├── Axi4LiteMonitor_dummy.vhd │ ├── Axi4LitePassThru.vhd │ └── Axi4LiteSubordinate.vhd └── testbench │ ├── OsvvmTestCommonPkg.vhd │ ├── TbAxi4.vhd │ ├── TbAxi4Memory.vhd │ ├── TestCtrl_e.vhd │ └── build.pro ├── AxiStream ├── .gitignore ├── AxiStream.pro ├── RunAllTests.pro ├── RunAllTestsVti.pro ├── RunDemoTests.pro ├── RunDemoTestsVti.pro ├── TestCases │ ├── OsvvmTestCommonPkg.pro │ ├── OsvvmTestCommonPkg.vhd │ ├── TbStream_AxiBurstAsyncNoLast1.vhd │ ├── TbStream_AxiBurstNoLast1.vhd │ ├── TbStream_AxiLastOption1.vhd │ ├── TbStream_AxiLastOptionAsync1.vhd │ ├── TbStream_AxiLastParam1.vhd │ ├── TbStream_AxiLastParamAsync1.vhd │ ├── TbStream_AxiSendCheckBurstAsyncPattern1.vhd │ ├── TbStream_AxiSendCheckBurstAsyncPattern2.vhd │ ├── TbStream_AxiSendCheckBurstPattern1.vhd │ ├── TbStream_AxiSendCheckBurstPattern2.vhd │ ├── TbStream_AxiSendGet2.vhd │ ├── TbStream_AxiSendGetAsync2.vhd │ ├── TbStream_AxiSendGetBurst2.vhd │ ├── TbStream_AxiSendGetBurstAsync2.vhd │ ├── TbStream_AxiSendGetRandom1.vhd │ ├── TbStream_AxiSetOptions1.vhd │ ├── TbStream_AxiSetOptions2.vhd │ ├── TbStream_AxiSetOptionsAsync1.vhd │ ├── TbStream_AxiSetOptionsAsync2.vhd │ ├── TbStream_AxiSetOptionsBurst1.vhd │ ├── TbStream_AxiSetOptionsBurst2.vhd │ ├── TbStream_AxiSetOptionsBurst3.vhd │ ├── TbStream_AxiSetOptionsBurstAsync1.vhd │ ├── TbStream_AxiSetOptionsBurstAsync2.vhd │ ├── TbStream_AxiSetOptionsBurstAsync3.vhd │ ├── TbStream_AxiSetOptionsBurstByte2.vhd │ ├── TbStream_AxiSetOptionsBurstByteAsync2.vhd │ ├── TbStream_AxiSetOptionsBurstCheck3.vhd │ ├── TbStream_AxiSetOptionsBurstCheckAsync3.vhd │ ├── TbStream_AxiTiming1.vhd │ ├── TbStream_AxiTiming2.vhd │ ├── TbStream_AxiTimingBurst2.vhd │ ├── TbStream_AxiTxValidDelay1.vhd │ ├── TbStream_AxiTxValidDelayBurst1.vhd │ ├── TbStream_ByteHandling1.vhd │ ├── TbStream_ByteHandlingAsync1.vhd │ ├── TbStream_ByteHandlingBurst1.vhd │ ├── TbStream_ByteHandlingBurstAsync1.vhd │ ├── TbStream_ByteHandlingBurstByte1.vhd │ ├── TbStream_ByteHandlingBurstByteAsync1.vhd │ ├── TbStream_MultipleDriversReceiver1.vhd │ ├── TbStream_MultipleDriversTransmitter1.vhd │ ├── TbStream_ReleaseAcquireReceiver1.vhd │ ├── TbStream_ReleaseAcquireTransmitter1.vhd │ ├── TbStream_SendCheckBurst1.vhd │ ├── TbStream_SendCheckBurstAsync1.vhd │ ├── TbStream_SendCheckBurstAsyncPattern1.vhd │ ├── TbStream_SendCheckBurstAsyncPattern2.vhd │ ├── TbStream_SendCheckBurstByte1.vhd │ ├── TbStream_SendCheckBurstByteAsync1.vhd │ ├── TbStream_SendCheckBurstByteAsyncPattern1.vhd │ ├── TbStream_SendCheckBurstBytePattern1.vhd │ ├── TbStream_SendCheckBurstPattern1.vhd │ ├── TbStream_SendCheckBurstPattern2.vhd │ ├── TbStream_SendGet1.vhd │ ├── TbStream_SendGetAsync1.vhd │ ├── TbStream_SendGetBurst1.vhd │ ├── TbStream_SendGetBurstAsync1.vhd │ ├── TbStream_SendGetBurstByte1.vhd │ ├── TbStream_SendGetBurstByteAsync1.vhd │ ├── TbStream_SendGetDemo1.vhd │ ├── TbStream_SendGetPacketBurst1.vhd │ ├── TbStream_SendGetRandom1.vhd │ ├── TbStream_SendGetRandom2.vhd │ ├── TbStream_SendGetRandomDeprecated1.vhd │ ├── TbStream_WaitForGet1.vhd │ ├── TbStream_WaitForGet2.vhd │ ├── TbStream_WaitForGetAsync1.vhd │ ├── TestCases_NoBurst.pro │ ├── build.pro │ ├── build_demo.pro │ └── deprecated │ │ └── OsvvmTestCommonPkg_NoFilePath.vhd ├── ValidatedResults │ ├── TbStream_AxiBurstAsyncNoLast1.log │ ├── TbStream_AxiBurstNoLast1.log │ ├── TbStream_AxiLastOption1.log │ ├── TbStream_AxiLastOptionAsync1.log │ ├── TbStream_AxiLastParam1.log │ ├── TbStream_AxiLastParamAsync1.log │ ├── TbStream_AxiSendCheckBurstAsyncPattern1.log │ ├── TbStream_AxiSendCheckBurstAsyncPattern2.log │ ├── TbStream_AxiSendCheckBurstPattern1.log │ ├── TbStream_AxiSendCheckBurstPattern2.log │ ├── TbStream_AxiSendGet2.log │ ├── TbStream_AxiSendGetAsync2.log │ ├── TbStream_AxiSendGetBurst2.log │ ├── TbStream_AxiSendGetBurstAsync2.log │ ├── TbStream_AxiSetOptions1.log │ ├── TbStream_AxiSetOptions2.log │ ├── TbStream_AxiSetOptionsAsync1.log │ ├── TbStream_AxiSetOptionsAsync2.log │ ├── TbStream_AxiSetOptionsBurst1.log │ ├── TbStream_AxiSetOptionsBurst2.log │ ├── TbStream_AxiSetOptionsBurst3.log │ ├── TbStream_AxiSetOptionsBurstAsync1.log │ ├── TbStream_AxiSetOptionsBurstAsync2.log │ ├── TbStream_AxiSetOptionsBurstAsync3.log │ ├── TbStream_AxiSetOptionsBurstByte2.log │ ├── TbStream_AxiSetOptionsBurstByteAsync2.log │ ├── TbStream_AxiSetOptionsBurstCheck3.log │ ├── TbStream_AxiSetOptionsBurstCheckAsync3.log │ ├── TbStream_AxiTiming1.log │ ├── TbStream_AxiTiming2.log │ ├── TbStream_AxiTimingBurst2.log │ ├── TbStream_AxiTxValidDelay1.log │ ├── TbStream_AxiTxValidDelayBurst1.log │ ├── TbStream_ByteHandling1.log │ ├── TbStream_ByteHandlingAsync1.log │ ├── TbStream_ByteHandlingBurst1.log │ ├── TbStream_ByteHandlingBurstAsync1.log │ ├── TbStream_ByteHandlingBurstByte1.log │ ├── TbStream_ByteHandlingBurstByteAsync1.log │ ├── TbStream_MultipleDriversReceiver1.log │ ├── TbStream_MultipleDriversTransmitter1.log │ ├── TbStream_ReleaseAcquireReceiver1.log │ ├── TbStream_ReleaseAcquireTransmitter1.log │ ├── TbStream_SendCheckBurst1.log │ ├── TbStream_SendCheckBurstAsync1.log │ ├── TbStream_SendCheckBurstAsyncPattern1.log │ ├── TbStream_SendCheckBurstAsyncPattern2.log │ ├── TbStream_SendCheckBurstByte1.log │ ├── TbStream_SendCheckBurstByteAsync1.log │ ├── TbStream_SendCheckBurstByteAsyncPattern1.log │ ├── TbStream_SendCheckBurstBytePattern1.log │ ├── TbStream_SendCheckBurstPattern1.log │ ├── TbStream_SendCheckBurstPattern2.log │ ├── TbStream_SendGet1.log │ ├── TbStream_SendGetAsync1.log │ ├── TbStream_SendGetBurst1.log │ ├── TbStream_SendGetBurstAsync1.log │ ├── TbStream_SendGetBurstByte1.log │ ├── TbStream_SendGetBurstByteAsync1.log │ ├── TbStream_SendGetDemo1.log │ ├── TbStream_SendGetPacketBurst1.log │ ├── TbStream_SendGetRandom1.log │ ├── TbStream_SendGetRandom2.log │ ├── TbStream_WaitForGet1.log │ └── TbStream_WaitForGetAsync1.log ├── src │ ├── AxiStreamComponentPkg.vhd │ ├── AxiStreamContext.vhd │ ├── AxiStreamGenericSignalsPkg.vhd │ ├── AxiStreamOptionsArrayPkg.vhd │ ├── AxiStreamOptionsPkg.vhd │ ├── AxiStreamReceiver.vhd │ ├── AxiStreamReceiverVti.vhd │ ├── AxiStreamSignalsPkg_32.vhd │ ├── AxiStreamTbPkg.vhd │ ├── AxiStreamTransmitter.vhd │ ├── AxiStreamTransmitterVti.vhd │ ├── build.pro │ └── deprecated │ │ ├── AxiStreamReceiver_xilinx.vhd │ │ └── AxiStreamTransmitter_xilinx.vhd ├── testbench │ ├── AxiStreamDut.vhd │ ├── TbStream.vhd │ ├── TestCtrl_e.vhd │ └── build.pro ├── testbenchVti │ ├── TbStream.vhd │ ├── TestCtrl_e.vhd │ └── testbenchVti.pro ├── testbenchVti_Alt │ ├── README.md │ ├── TbStream.vhd │ ├── TestCtrl_e.vhd │ └── build.pro ├── testbench_GenericSignals │ ├── AxiStreamDut.vhd │ ├── TbStream.vhd │ ├── TestCtrl_e.vhd │ └── build.pro └── testbench_xilinx │ ├── AxiStreamDut.vhd │ ├── TbStream.vhd │ ├── TbStream_SendGet1.vhd │ ├── TbStream_SendGetDemo1.vhd │ ├── TbStream_Xilinx1.vhd │ ├── TestCtrl_e.vhd │ ├── build.pro │ └── build_demo.pro ├── CHANGELOG.md ├── CONTRIBUTORS.md ├── LICENSE.md ├── README.md ├── RunAllTests.pro ├── RunAllTestsVti.pro ├── RunDemoTests.pro └── common ├── common.pro └── src ├── Axi4CommonPkg.vhd ├── Axi4InterfaceCommonPkg.vhd ├── Axi4InterfacePkg.vhd ├── Axi4LiteInterfacePkg.vhd ├── Axi4ModelPkg.vhd ├── Axi4OptionsArrayPkg.vhd ├── Axi4OptionsPkg.vhd └── Axi4VersionCompatibilityPkg.vhd /.gitignore: -------------------------------------------------------------------------------- 1 | _update_notes.txt 2 | *_old 3 | 4 | -------------------------------------------------------------------------------- /AUTHORS.md: -------------------------------------------------------------------------------- 1 | ## OSVVM Project Authors - The people and/or organizations who own the copyrights 2 | 3 | #### [SynthWorks](https://SynthWorks.com) 4 | * Represented by Jim Lewis 5 | * Technical/Project lead 6 | * Maintainer / Contributor 7 | * email: jim (at) synthworks.com 8 | 9 | #### [Patrick Lehmann](https://opensource.ieee.org/patrick.lehmann) 10 | * Maintainer / Contributor 11 | 12 | ## OSVVM Project Contributors - The people who contribute to OSVVM 13 | 14 | #### [Jim Lewis](https://opensource.ieee.org/jim) 15 | * Technical/Project lead 16 | * Maintainer / Contributor 17 | * email: jim (at) synthworks.com 18 | 19 | #### [Patrick Lehmann](https://opensource.ieee.org/patrick.lehmann) 20 | * Maintainer / Contributor 21 | 22 | #### [Rob Gaddi](https://opensource.ieee.org/) 23 | * Contributor 24 | 25 | ### [Full contributors list](https://github.com/OSVVM/AXI4/graphs/contributors) 26 | 27 | ## Participating 28 | The OSVVM project welcomes your participation with either 29 | issue reports or pull requests. 30 | For details on [how to participate see](https://github.com/OSVVM/OsvvmLibraries/blob/main/CONTRIBUTING.md) 31 | 32 | 33 | 34 | #### Copyright and License 35 | Copyright (C) 2020 by [OSVVM Authors](AUTHORS.md) 36 | 37 | This file is part of OSVVM. 38 | 39 | Licensed under Apache License, Version 2.0 (the "License") 40 | You may not use this file except in compliance with the License. 41 | You may obtain a copy of the License at 42 | 43 | [http://www.apache.org/licenses/LICENSE-2.0](http://www.apache.org/licenses/LICENSE-2.0) 44 | 45 | Unless required by applicable law or agreed to in writing, software 46 | distributed under the License is distributed on an "AS IS" BASIS, 47 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 48 | See the License for the specific language governing permissions and 49 | limitations under the License. 50 | 51 | -------------------------------------------------------------------------------- /AXI4.pro: -------------------------------------------------------------------------------- 1 | # File Name: AXI4.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Build all OSVVM AXI4 Verification Components 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | include ./common/common.pro 41 | include ./Axi4Lite/Axi4Lite.pro 42 | include ./AxiStream/AxiStream.pro 43 | include ./Axi4/Axi4.pro 44 | -------------------------------------------------------------------------------- /Axi4/Axi4.pro: -------------------------------------------------------------------------------- 1 | # File Name: Axi4.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to compile the Axi4 models 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | include ./src 41 | -------------------------------------------------------------------------------- /Axi4/RunAllTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi4 tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | TestSuite Axi4Full 42 | library osvvm_TbAxi4 43 | 44 | if {$::osvvm::ToolNameVersion ne "XSIM-2023.2"} { 45 | include ./testbench 46 | include ./TestCases 47 | include ./testbench_MultipleMemory 48 | # include ./testbench_interrupt ; # moved to OsvvmLibraries/Common/TbInterrupt 49 | } else { 50 | SkipTest Axi4VC "AXI4 VC not working in XSIM" 51 | } 52 | 53 | -------------------------------------------------------------------------------- /Axi4/RunAllTestsVti.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTestsVti.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi4 tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | TestSuite Axi4Full_VTI 42 | library osvvm_TbAxi4Vti 43 | 44 | include ./testbenchVti 45 | include ./TestCases 46 | include ./testbench_MultipleMemory 47 | -------------------------------------------------------------------------------- /Axi4/RunDemoTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi4 tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | TestSuite Axi4Full 42 | library osvvm_TbAxi4 43 | 44 | if {$::osvvm::ToolNameVersion ne "XSIM-2023.2"} { 45 | include ./testbench 46 | 47 | # Make TestCases the frame of reference 48 | set ::osvvm::CurrentWorkingDirectory [file join $::osvvm::CurrentWorkingDirectory TestCases] 49 | RunTest TbAxi4_DemoMemoryReadWrite1.vhd 50 | RunTest TbAxi4_BasicReadWrite.vhd 51 | RunTest TbAxi4_ManagerRandomTiming1.vhd 52 | RunTest TbAxi4_ManagerMemoryRandomTiming1.vhd 53 | RunTest TbAxi4_MemoryBurstPattern1.vhd 54 | } else { 55 | SkipTest Axi4VC "AXI4 VC not working in XSIM" 56 | } 57 | 58 | 59 | 60 | -------------------------------------------------------------------------------- /Axi4/RunDemoTestsVti.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi4 tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | TestSuite Axi4Full_VTI 42 | library osvvm_TbAxi4Vti 43 | 44 | include ./testbenchVti 45 | 46 | # Make TestCases the frame of reference 47 | set ::osvvm::CurrentWorkingDirectory [file join $::osvvm::CurrentWorkingDirectory TestCases] 48 | 49 | RunTest TbAxi4_DemoMemoryReadWrite1.vhd 50 | RunTest TbAxi4_BasicReadWrite.vhd 51 | RunTest TbAxi4_ManagerRandomTiming1.vhd 52 | RunTest TbAxi4_ManagerMemoryRandomTiming1.vhd 53 | RunTest TbAxi4_MemoryBurstPattern1.vhd 54 | -------------------------------------------------------------------------------- /Axi4/RunDemoTests_GenericSignals.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi4 tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | TestSuite Axi4Full_GenericSignals 42 | library osvvm_TbAxi4_GenericSignals 43 | 44 | if {$::osvvm::ToolNameVersion ne "XSIM-2023.2"} { 45 | include ./testbench_GenericSignals 46 | 47 | # Make TestCases the frame of reference 48 | set ::osvvm::CurrentWorkingDirectory [file join $::osvvm::CurrentWorkingDirectory TestCases] 49 | RunTest TbAxi4_BasicReadWrite.vhd ; # TbAxi4 50 | RunTest TbAxi4_DemoMemoryReadWrite1.vhd ; # TbAxi4Memory 51 | # RunTest TbAxi4_ManagerRandomTiming1.vhd 52 | # RunTest TbAxi4_ManagerMemoryRandomTiming1.vhd 53 | # RunTest TbAxi4_MemoryBurstPattern1.vhd 54 | } else { 55 | SkipTest Axi4VC "AXI4 VC not working in XSIM" 56 | } 57 | 58 | 59 | 60 | -------------------------------------------------------------------------------- /Axi4/TestCases/OsvvmTestCommonPkg.vhd: -------------------------------------------------------------------------------- 1 | package OsvvmTestCommonPkg is 2 | constant OSVVM_RESULTS_DIR : string := "" ; 3 | constant OSVVM_PATH_TO_TESTS : string := "../../OsvvmLibraries/" ; 4 | end package OsvvmTestCommonPkg ; 5 | -------------------------------------------------------------------------------- /Axi4/TestCases/TbAxi4_MultipleDriversManager.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbAxi4_MultipleDriversManager.vhd 3 | -- Design Unit Name: Architecture of TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 12/2020 2020.12 Initial revision 23 | -- 24 | -- 25 | -- This file is part of OSVVM. 26 | -- 27 | -- Copyright (c) 2017 - 2021 by SynthWorks Design Inc. 28 | -- 29 | -- Licensed under the Apache License, Version 2.0 (the "License"); 30 | -- you may not use this file except in compliance with the License. 31 | -- You may obtain a copy of the License at 32 | -- 33 | -- https://www.apache.org/licenses/LICENSE-2.0 34 | -- 35 | -- Unless required by applicable law or agreed to in writing, software 36 | -- distributed under the License is distributed on an "AS IS" BASIS, 37 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | -- See the License for the specific language governing permissions and 39 | -- limitations under the License. 40 | -- 41 | 42 | architecture MultipleDriversManager of TestCtrl is 43 | 44 | signal TestDone, Sync : integer_barrier := 1 ; 45 | 46 | begin 47 | 48 | ------------------------------------------------------------ 49 | -- ControlProc 50 | -- Set up AlertLog and wait for end of test 51 | ------------------------------------------------------------ 52 | ControlProc : process 53 | begin 54 | -- Initialization of test 55 | SetTestName("TbAxi4_MultipleDriversManager") ; 56 | SetLogEnable(PASSED, TRUE) ; -- Enable PASSED logs 57 | SetLogEnable(INFO, TRUE) ; -- Enable INFO logs 58 | SetAlertStopCount(FAILURE, 2) ; -- Allow 2 FAILURE Alerts 59 | 60 | -- Wait for testbench initialization 61 | wait for 0 ns ; wait for 0 ns ; 62 | TranscriptOpen ; 63 | SetTranscriptMirror(TRUE) ; 64 | 65 | -- Wait for Design Reset 66 | wait until nReset = '1' ; 67 | ClearAlerts ; 68 | 69 | -- Wait for test to finish 70 | WaitForBarrier(TestDone, 35 ms) ; 71 | AlertIf(now >= 35 ms, "Test finished due to timeout") ; 72 | -- AlertIf(GetAffirmCount < 1, "Test is not Self-Checking"); 73 | 74 | AffirmIf(GetAlertCount = AlertCountType'(FAILURE => 1, ERROR => 0, WARNING => 0), "Expecting: (FAILURE => 1, ERROR => 0, WARNING => 0)") ; 75 | TranscriptClose ; 76 | -- Printing differs in different simulators due to differences in process order execution 77 | -- AlertIfDiff("./results/TbAxi4_MultipleDriversManager.txt", "../AXI4/Axi4/testbench/validated_results/TbAxi4_MultipleDriversManager.txt", "") ; 78 | 79 | EndOfTestReports(ExternalErrors => (FAILURE => -1, ERROR => 0, WARNING => 0)) ; 80 | std.env.stop ; 81 | wait ; 82 | end process ControlProc ; 83 | 84 | ------------------------------------------------------------ 85 | -- ManagerProc 86 | -- Generate transactions for AxiManager 87 | ------------------------------------------------------------ 88 | ManagerProc : process 89 | begin 90 | wait until nReset = '1' ; 91 | WaitForClock(ManagerRec, 2) ; 92 | WaitForClock(ManagerRec, 3) ; 93 | 94 | WaitForBarrier(TestDone) ; 95 | wait ; 96 | end process ManagerProc ; 97 | 98 | 99 | ------------------------------------------------------------ 100 | -- SubordinateProc 101 | -- Generate transactions for AxiSubordinate 102 | ------------------------------------------------------------ 103 | SubordinateProc : process 104 | begin 105 | wait until nReset = '1' ; 106 | WaitForClock(SubordinateRec, 2) ; 107 | WaitForClock(SubordinateRec, 2) ; 108 | WaitForClock(ManagerRec, 2) ; 109 | 110 | WaitForBarrier(TestDone) ; 111 | wait ; 112 | end process SubordinateProc ; 113 | 114 | 115 | end MultipleDriversManager ; 116 | 117 | Configuration TbAxi4_MultipleDriversManager of TbAxi4 is 118 | for TestHarness 119 | for TestCtrl_1 : TestCtrl 120 | use entity work.TestCtrl(MultipleDriversManager) ; 121 | end for ; 122 | end for ; 123 | end TbAxi4_MultipleDriversManager ; -------------------------------------------------------------------------------- /Axi4/TestCases/TbAxi4_MultipleDriversMemory.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbAxi4_MultipleDriversMemory.vhd 3 | -- Design Unit Name: Architecture of TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 12/2020 2020.12 Initial revision 23 | -- 24 | -- 25 | -- This file is part of OSVVM. 26 | -- 27 | -- Copyright (c) 2017 - 2021 by SynthWorks Design Inc. 28 | -- 29 | -- Licensed under the Apache License, Version 2.0 (the "License"); 30 | -- you may not use this file except in compliance with the License. 31 | -- You may obtain a copy of the License at 32 | -- 33 | -- https://www.apache.org/licenses/LICENSE-2.0 34 | -- 35 | -- Unless required by applicable law or agreed to in writing, software 36 | -- distributed under the License is distributed on an "AS IS" BASIS, 37 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | -- See the License for the specific language governing permissions and 39 | -- limitations under the License. 40 | -- 41 | 42 | architecture MultipleDriversMemory of TestCtrl is 43 | 44 | signal TestDone, Sync : integer_barrier := 1 ; 45 | 46 | begin 47 | 48 | ------------------------------------------------------------ 49 | -- ControlProc 50 | -- Set up AlertLog and wait for end of test 51 | ------------------------------------------------------------ 52 | ControlProc : process 53 | begin 54 | -- Initialization of test 55 | SetTestName("TbAxi4_MultipleDriversMemory") ; 56 | SetLogEnable(PASSED, TRUE) ; -- Enable PASSED logs 57 | SetLogEnable(INFO, TRUE) ; -- Enable INFO logs 58 | SetAlertStopCount(FAILURE, 2) ; -- Enable INFO logs 59 | 60 | -- Wait for testbench initialization 61 | wait for 0 ns ; wait for 0 ns ; 62 | TranscriptOpen ; 63 | SetTranscriptMirror(TRUE) ; 64 | 65 | -- Wait for Design Reset 66 | wait until nReset = '1' ; 67 | ClearAlerts ; 68 | 69 | -- Wait for test to finish 70 | WaitForBarrier(TestDone, 35 ms) ; 71 | AlertIf(now >= 35 ms, "Test finished due to timeout") ; 72 | -- AlertIf(GetAffirmCount < 1, "Test is not Self-Checking"); 73 | 74 | AffirmIf(GetAlertCount = AlertCountType'(FAILURE => 1, ERROR => 0, WARNING => 0), "Expecting: (FAILURE => 1, ERROR => 0, WARNING => 0)") ; 75 | TranscriptClose ; 76 | -- Printing differs in different simulators due to differences in process order execution 77 | -- AlertIfDiff("./results/TbAxi4_MultipleDriversMemory.txt", "../AXI4/Axi4/testbench/validated_results/TbAxi4_MultipleDriversMemory.txt", "") ; 78 | 79 | EndOfTestReports(ExternalErrors => (FAILURE => -1, ERROR => 0, WARNING => 0)) ; 80 | std.env.stop ; 81 | wait ; 82 | end process ControlProc ; 83 | 84 | ------------------------------------------------------------ 85 | -- ManagerProc 86 | -- Generate transactions for AxiManager 87 | ------------------------------------------------------------ 88 | ManagerProc : process 89 | variable Data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0) ; 90 | begin 91 | wait until nReset = '1' ; 92 | WaitForClock(ManagerRec, 2) ; 93 | WaitForClock(ManagerRec, 2) ; 94 | WaitForClock(SubordinateRec, 2) ; 95 | 96 | WaitForBarrier(TestDone) ; 97 | wait ; 98 | end process ManagerProc ; 99 | 100 | 101 | ------------------------------------------------------------ 102 | -- SubordinateProc 103 | -- Generate transactions for AxiSubordinate 104 | ------------------------------------------------------------ 105 | SubordinateProc : process 106 | variable Addr : std_logic_vector(AXI_ADDR_WIDTH-1 downto 0) ; 107 | variable Data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0) ; 108 | begin 109 | wait until nReset = '1' ; 110 | WaitForClock(SubordinateRec, 1) ; 111 | WaitForClock(SubordinateRec, 1) ; 112 | 113 | WaitForBarrier(TestDone) ; 114 | wait ; 115 | end process SubordinateProc ; 116 | 117 | 118 | end MultipleDriversMemory ; 119 | 120 | Configuration TbAxi4_MultipleDriversMemory of TbAxi4Memory is 121 | for TestHarness 122 | for TestCtrl_1 : TestCtrl 123 | use entity work.TestCtrl(MultipleDriversMemory) ; 124 | end for ; 125 | --!! for Subordinate_1 : Axi4Subordinate 126 | --!! use entity OSVVM_AXI4.Axi4Memory ; 127 | --!! end for ; 128 | end for ; 129 | end TbAxi4_MultipleDriversMemory ; -------------------------------------------------------------------------------- /Axi4/TestCases/TbAxi4_MultipleDriversSubordinate.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbAxi4_MultipleDriversSubordinate.vhd 3 | -- Design Unit Name: Architecture of TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 12/2020 2020.12 Initial revision 23 | -- 24 | -- 25 | -- This file is part of OSVVM. 26 | -- 27 | -- Copyright (c) 2017 - 2021 by SynthWorks Design Inc. 28 | -- 29 | -- Licensed under the Apache License, Version 2.0 (the "License"); 30 | -- you may not use this file except in compliance with the License. 31 | -- You may obtain a copy of the License at 32 | -- 33 | -- https://www.apache.org/licenses/LICENSE-2.0 34 | -- 35 | -- Unless required by applicable law or agreed to in writing, software 36 | -- distributed under the License is distributed on an "AS IS" BASIS, 37 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | -- See the License for the specific language governing permissions and 39 | -- limitations under the License. 40 | -- 41 | 42 | architecture MultipleDriversSubordinate of TestCtrl is 43 | 44 | signal TestDone, Sync : integer_barrier := 1 ; 45 | 46 | begin 47 | 48 | ------------------------------------------------------------ 49 | -- ControlProc 50 | -- Set up AlertLog and wait for end of test 51 | ------------------------------------------------------------ 52 | ControlProc : process 53 | begin 54 | -- Initialization of test 55 | SetTestName("TbAxi4_MultipleDriversSubordinate") ; 56 | SetLogEnable(PASSED, TRUE) ; -- Enable PASSED logs 57 | SetLogEnable(INFO, TRUE) ; -- Enable INFO logs 58 | SetAlertStopCount(FAILURE, 2) ; -- Enable INFO logs 59 | 60 | -- Wait for testbench initialization 61 | wait for 0 ns ; wait for 0 ns ; 62 | TranscriptOpen ; 63 | SetTranscriptMirror(TRUE) ; 64 | 65 | -- Wait for Design Reset 66 | wait until nReset = '1' ; 67 | ClearAlerts ; 68 | 69 | -- Wait for test to finish 70 | WaitForBarrier(TestDone, 35 ms) ; 71 | AlertIf(now >= 35 ms, "Test finished due to timeout") ; 72 | -- AlertIf(GetAffirmCount < 1, "Test is not Self-Checking"); 73 | 74 | AffirmIf(GetAlertCount = AlertCountType'(FAILURE => 1, ERROR => 0, WARNING => 0), "Expecting: (FAILURE => 1, ERROR => 0, WARNING => 0)") ; 75 | TranscriptClose ; 76 | -- Printing differs in different simulators due to differences in process order execution 77 | -- AlertIfDiff("./results/TbAxi4_MultipleDriversSubordinate.txt", "../AXI4/Axi4/testbench/validated_results/TbAxi4_MultipleDriversSubordinate.txt", "") ; 78 | 79 | EndOfTestReports(ExternalErrors => (FAILURE => -1, ERROR => 0, WARNING => 0)) ; 80 | std.env.stop ; 81 | wait ; 82 | end process ControlProc ; 83 | 84 | ------------------------------------------------------------ 85 | -- ManagerProc 86 | -- Generate transactions for AxiManager 87 | ------------------------------------------------------------ 88 | ManagerProc : process 89 | variable Data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0) ; 90 | begin 91 | wait until nReset = '1' ; 92 | WaitForClock(ManagerRec, 2) ; 93 | WaitForClock(ManagerRec, 2) ; 94 | WaitForClock(SubordinateRec, 2) ; 95 | 96 | WaitForBarrier(TestDone) ; 97 | wait ; 98 | end process ManagerProc ; 99 | 100 | 101 | ------------------------------------------------------------ 102 | -- SubordinateProc 103 | -- Generate transactions for AxiSubordinate 104 | ------------------------------------------------------------ 105 | SubordinateProc : process 106 | variable Addr : std_logic_vector(AXI_ADDR_WIDTH-1 downto 0) ; 107 | variable Data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0) ; 108 | begin 109 | wait until nReset = '1' ; 110 | WaitForClock(SubordinateRec, 1) ; 111 | WaitForClock(SubordinateRec, 1) ; 112 | 113 | WaitForBarrier(TestDone) ; 114 | wait ; 115 | end process SubordinateProc ; 116 | 117 | 118 | end MultipleDriversSubordinate ; 119 | 120 | Configuration TbAxi4_MultipleDriversSubordinate of TbAxi4 is 121 | for TestHarness 122 | for TestCtrl_1 : TestCtrl 123 | use entity work.TestCtrl(MultipleDriversSubordinate) ; 124 | end for ; 125 | end for ; 126 | end TbAxi4_MultipleDriversSubordinate ; -------------------------------------------------------------------------------- /Axi4/TestCases/TestCases.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi test cases 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 4/2025 2025.04 Added Tests 21 | # 1/2022 2022.01 Added Tests 22 | # 1/2020 2020.01 Updated Licenses to Apache 23 | # 24 | # 25 | # This file is part of OSVVM. 26 | # 27 | # Copyright (c) 2019 - 2025 by SynthWorks Design Inc. 28 | # 29 | # Licensed under the Apache License, Version 2.0 (the "License"); 30 | # you may not use this file except in compliance with the License. 31 | # You may obtain a copy of the License at 32 | # 33 | # https://www.apache.org/licenses/LICENSE-2.0 34 | # 35 | # Unless required by applicable law or agreed to in writing, software 36 | # distributed under the License is distributed on an "AS IS" BASIS, 37 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | # See the License for the specific language governing permissions and 39 | # limitations under the License. 40 | # 41 | 42 | ## 43 | ## runs in conjunction with either 44 | ## Testbench/Testbench.pro or TestbenchVTI/TestbenchVTI.pro 45 | ## Continuing with library set previously by the above 46 | ## 47 | ## 48 | RunTest TbAxi4_DemoMemoryReadWrite1.vhd 49 | 50 | include TestCases_NoBurst.pro 51 | include TestCases_Burst.pro 52 | 53 | # Both NoBurst and Burst 54 | RunTest TbAxi4_ManagerRandomTiming1.vhd 55 | RunTest TbAxi4_AxiManagerRandomTiming1.vhd 56 | RunTest TbAxi4_AxiManagerRandomTiming2.vhd 57 | RunTest TbAxi4_ManagerRandomTimingAsync1.vhd 58 | 59 | RunTest TbAxi4_MemoryRandomTiming1.vhd 60 | RunTest TbAxi4_AxiMemoryRandomTiming1.vhd 61 | RunTest TbAxi4_AxiMemoryRandomTiming2.vhd 62 | RunTest TbAxi4_MemoryRandomTimingAsync1.vhd 63 | 64 | RunTest TbAxi4_SubordinateRandomTiming1.vhd 65 | RunTest TbAxi4_AxiSubordinateRandomTiming1.vhd 66 | RunTest TbAxi4_AxiSubordinateRandomTiming2.vhd 67 | 68 | RunTest TbAxi4_ManagerMemoryRandomTiming1.vhd 69 | RunTest TbAxi4_ManagerSubordinateRandomTiming1.vhd 70 | RunTest TbAxi4_ManagerSubordinateRandomTimingAsync1.vhd 71 | RunTest TbAxi4_NoRandomTiming1.vhd 72 | 73 | -------------------------------------------------------------------------------- /Axi4/TestCases/TestCasesWithError.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2022 2022.01 Added Tests 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2022 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | ## 42 | ## runs in conjunction with either 43 | ## Testbench/Testbench.pro or TestbenchVTI/TestbenchVTI.pro 44 | ## Continuing with library set previously by the above 45 | ## 46 | ## 47 | RunTest TbAxi4_DemoMemoryReadWrite1.vhd 48 | 49 | RunTest TbAxi4_DemoErrorMemoryReadWrite1.vhd 50 | 51 | include TestCases_NoBurst.pro 52 | 53 | RunTest TbAxi4_DemoErrorMemoryReadWrite1.vhd 54 | include TestCases_Burst.pro 55 | 56 | RunTest TbAxi4_DemoErrorMemoryReadWrite1.vhd 57 | 58 | -------------------------------------------------------------------------------- /Axi4/TestCases/TestCases_Burst.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | ## 42 | ## runs in conjunction with either 43 | ## Testbench/Testbench.pro or TestbenchVTI/TestbenchVTI.pro 44 | ## Continuing with library set previously by the above 45 | ## 46 | ## 47 | 48 | ## Burst 49 | RunTest TbAxi4_MemoryBurst1.vhd 50 | RunTest TbAxi4_MemoryBurstAsync1.vhd 51 | RunTest TbAxi4_MemoryBurstByte1.vhd 52 | 53 | RunTest TbAxi4_MemoryBurstPattern1.vhd 54 | RunTest TbAxi4_MemoryBurstPattern2.vhd 55 | RunTest TbAxi4_MemoryBurstBytePattern1.vhd 56 | RunTest TbAxi4_MemoryBurstAsyncPattern1.vhd 57 | RunTest TbAxi4_MemoryBurstAsyncPattern2.vhd 58 | 59 | RunTest TbAxi4_MemoryBurstSparse1.vhd 60 | 61 | RunTest TbAxi4_ReleaseAcquireManager1.vhd 62 | 63 | RunTest TbAxi4_AxSizeManagerMemory1.vhd 64 | RunTest TbAxi4_AxSizeManagerMemory2.vhd 65 | 66 | RunTest TbAxi4_AxiIfOptionsManagerMemory.vhd 67 | 68 | RunTest TbAxi4_TransactionApiManagerBurst.vhd 69 | RunTest TbAxi4_TransactionApiMemoryBurst.vhd 70 | 71 | RunTest TbAxi4_ValidTimingBurstManager.vhd 72 | RunTest TbAxi4_ValidTimingBurstMemory.vhd 73 | 74 | 75 | -------------------------------------------------------------------------------- /Axi4/TestCases/TestCases_NoBurst.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | ## 42 | ## runs in conjunction with either 43 | ## Testbench/Testbench.pro or TestbenchVTI/TestbenchVTI.pro 44 | ## Continuing with library set previously by the above 45 | ## 46 | ## 47 | # Tests for any AXI4 MIT 48 | RunTest TbAxi4_BasicReadWrite.vhd 49 | RunTest TbAxi4_RandomReadWrite.vhd 50 | RunTest TbAxi4_RandomReadWriteByte1.vhd 51 | 52 | RunTest TbAxi4_SubordinateReadWrite1.vhd 53 | RunTest TbAxi4_SubordinateReadWrite2.vhd 54 | RunTest TbAxi4_SubordinateReadWrite3.vhd 55 | 56 | RunTest TbAxi4_ReadWriteAsync1.vhd 57 | RunTest TbAxi4_ReadWriteAsync2.vhd 58 | RunTest TbAxi4_ReadWriteAsync3.vhd 59 | RunTest TbAxi4_ReadWriteAsync4.vhd 60 | 61 | RunTest TbAxi4_SubordinateReadWriteAsync1.vhd 62 | RunTest TbAxi4_SubordinateReadWriteAsync2.vhd 63 | 64 | RunTest TbAxi4_MultipleDriversManager.vhd 65 | RunTest TbAxi4_MultipleDriversSubordinate.vhd 66 | 67 | RunTest TbAxi4_ReleaseAcquireSubordinate1.vhd 68 | 69 | RunTest TbAxi4_AlertLogIDManager.vhd 70 | RunTest TbAxi4_AlertLogIDSubordinate.vhd 71 | 72 | RunTest TbAxi4_TransactionApiSubordinate.vhd 73 | 74 | RunTest TbAxi4_ValidTimingManager.vhd 75 | RunTest TbAxi4_ValidTimingSubordinate.vhd 76 | 77 | RunTest TbAxi4_ReadyTimingSubordinate.vhd 78 | 79 | RunTest TbAxi4_AxiIfOptionsManagerSubordinate.vhd 80 | RunTest TbAxi4_AxiXResp.vhd 81 | RunTest TbAxi4_AxiXResp2_Enum.vhd 82 | RunTest TbAxi4_AxiXResp3_slv.vhd 83 | 84 | RunTest TbAxi4_TimeOutManager.vhd 85 | RunTest TbAxi4_TimeOutSubordinate.vhd 86 | 87 | ## Memory 88 | RunTest TbAxi4_MemoryReadWrite1.vhd 89 | RunTest TbAxi4_MemoryReadWrite2.vhd 90 | 91 | RunTest TbAxi4_MultipleDriversMemory.vhd 92 | 93 | RunTest TbAxi4_ReleaseAcquireMemory1.vhd 94 | 95 | RunTest TbAxi4_AlertLogIDMemory.vhd 96 | 97 | RunTest TbAxi4_TimeOutMemory.vhd 98 | 99 | RunTest TbAxi4_TransactionApiManager.vhd 100 | RunTest TbAxi4_TransactionApiMemory.vhd 101 | 102 | RunTest TbAxi4_ValidTimingMemory.vhd 103 | 104 | RunTest TbAxi4_ReadyTimingManager.vhd 105 | RunTest TbAxi4_ReadyTimingMemory.vhd 106 | 107 | RunTest TbAxi4_MemoryAsync.vhd 108 | 109 | -------------------------------------------------------------------------------- /Axi4/src/Axi4Context.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: Axi4Context.vhd 3 | -- Design Unit Name: Axi4Context 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- 8 | -- Description 9 | -- Context Declaration for using Axi4 models 10 | -- 11 | -- Developed by/for: 12 | -- SynthWorks Design Inc. 13 | -- VHDL Training Classes 14 | -- 11898 SW 128th Ave. Tigard, Or 97223 15 | -- http://www.SynthWorks.com 16 | -- 17 | -- Revision History: 18 | -- Date Version Description 19 | -- 11/2022 2022.11 Added Axi4OptionsArrayPkg 20 | -- 12/2020 2020.12 Restructured Component Packages 21 | -- 01/2020 2020.01 Updated license notice 22 | -- 03/2019 2019.03 Initial Revision 23 | -- 24 | -- 25 | -- This file is part of OSVVM. 26 | -- 27 | -- Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 28 | -- 29 | -- Licensed under the Apache License, Version 2.0 (the "License"); 30 | -- you may not use this file except in compliance with the License. 31 | -- You may obtain a copy of the License at 32 | -- 33 | -- https://www.apache.org/licenses/LICENSE-2.0 34 | -- 35 | -- Unless required by applicable law or agreed to in writing, software 36 | -- distributed under the License is distributed on an "AS IS" BASIS, 37 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | -- See the License for the specific language governing permissions and 39 | -- limitations under the License. 40 | -- 41 | 42 | context Axi4Context is 43 | library osvvm_common ; 44 | context osvvm_common.OsvvmCommonContext ; -- Address Bus Transactions 45 | 46 | library osvvm_axi4 ; 47 | 48 | use osvvm_axi4.Axi4CommonPkg.all ; -- AXI handshaking 49 | use osvvm_axi4.Axi4InterfaceCommonPkg.all ; 50 | use osvvm_axi4.Axi4InterfacePkg.all ; -- Interface definition 51 | 52 | use osvvm_axi4.Axi4OptionsPkg.all ; -- Model parameters 53 | use osvvm_axi4.Axi4OptionsArrayPkg.all ; -- Model parameters - for Array parameters 54 | use osvvm_axi4.Axi4ModelPkg.all ; -- Model support 55 | 56 | use osvvm_axi4.Axi4ComponentPkg.all ; -- Connected Transaction Interface 57 | use osvvm_axi4.Axi4ComponentVtiPkg.all ; -- Virtual Transaction Interface 58 | 59 | -- Temporary inclusion of Axi4 things that become deprecated with changes 60 | use osvvm_axi4.Axi4VersionCompatibilityPkg.all ; 61 | 62 | end context Axi4Context ; -------------------------------------------------------------------------------- /Axi4/src/Axi4Monitor_dummy.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: Axi4Monitor.vhd 3 | -- Design Unit Name: Axi4Monitor 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- AXI Lite Monitor dummy model 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 09/2017 2017 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | library ieee ; 43 | use ieee.std_logic_1164.all ; 44 | use ieee.numeric_std.all ; 45 | use ieee.numeric_std_unsigned.all ; 46 | 47 | library osvvm ; 48 | context osvvm.OsvvmContext ; 49 | 50 | use work.Axi4InterfaceCommonPkg.all ; 51 | use work.Axi4InterfacePkg.all ; 52 | use work.Axi4CommonPkg.all ; 53 | 54 | entity Axi4Monitor is 55 | port ( 56 | -- Globals 57 | Clk : in std_logic ; 58 | nReset : in std_logic ; 59 | 60 | -- AXI Manager Functional Interface 61 | AxiBus : in Axi4RecType 62 | ) ; 63 | 64 | end entity Axi4Monitor ; 65 | architecture Monitor of Axi4Monitor is 66 | 67 | -- alias AB : AxiBus'subtype is AxiBus ; 68 | -- alias AW is AxiBus.WriteAddress ; 69 | -- alias WD is AxiBus.WriteData ; 70 | -- alias WR is AxiBus.WriteResponse ; 71 | -- alias AR is AxiBus.ReadAddress ; 72 | -- alias RD is AxiBus.ReadData ; 73 | 74 | constant MODEL_INSTANCE_NAME : string := PathTail(to_lower(Axi4Monitor'PATH_NAME)) ; 75 | signal ModelID, ProtocolID, DataCheckID, BusFailedID : AlertLogIDType ; 76 | 77 | 78 | begin 79 | 80 | 81 | 82 | end architecture Monitor ; 83 | -------------------------------------------------------------------------------- /Axi4/src/build.pro: -------------------------------------------------------------------------------- 1 | # File Name: Axi4.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to compile the Axi4 models 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_axi4 41 | analyze Axi4ComponentPkg.vhd 42 | analyze Axi4ComponentVtiPkg.vhd 43 | analyze Axi4Context.vhd 44 | 45 | if {$::osvvm::ToolNameVersion ne "XSIM-2023.2"} { 46 | # for XSIM, VTI not supported in 2024.2 47 | analyze Axi4Manager.vhd 48 | analyze Axi4ManagerVti.vhd 49 | analyze Axi4Monitor_dummy.vhd 50 | analyze Axi4Subordinate.vhd 51 | analyze Axi4SubordinateVti.vhd 52 | analyze Axi4Memory.vhd 53 | analyze Axi4MemoryVti.vhd 54 | } else { 55 | # maybe comment all of these out as they do not work in 2023.2 56 | # 2024.2 supports the above 57 | analyze deprecated/Axi4Manager_xilinx.vhd 58 | analyze Axi4Monitor_dummy.vhd 59 | analyze deprecated/Axi4Memory_xilinx.vhd 60 | } 61 | 62 | analyze Axi4PassThru.vhd 63 | analyze Axi4GenericSignalsPkg.vhd 64 | -------------------------------------------------------------------------------- /Axi4/testbench/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 09/2017 2017.09 Initial revision 23 | -- 05/2019 2019.05 Added context reference 24 | -- 01/2020 2020.01 Updated license notice 25 | -- 12/2020 2020.12 Updated port names 26 | -- 27 | -- 28 | -- This file is part of OSVVM. 29 | -- 30 | -- Copyright (c) 2017 - 2020 by SynthWorks Design Inc. 31 | -- 32 | -- Licensed under the Apache License, Version 2.0 (the "License"); 33 | -- you may not use this file except in compliance with the License. 34 | -- You may obtain a copy of the License at 35 | -- 36 | -- https://www.apache.org/licenses/LICENSE-2.0 37 | -- 38 | -- Unless required by applicable law or agreed to in writing, software 39 | -- distributed under the License is distributed on an "AS IS" BASIS, 40 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | -- See the License for the specific language governing permissions and 42 | -- limitations under the License. 43 | -- 44 | 45 | library ieee ; 46 | use ieee.std_logic_1164.all ; 47 | use ieee.numeric_std.all ; 48 | use ieee.numeric_std_unsigned.all ; 49 | use ieee.math_real.all ; 50 | 51 | library OSVVM ; 52 | context OSVVM.OsvvmContext ; 53 | use osvvm.ScoreboardPkg_slv.all ; 54 | 55 | library OSVVM_AXI4 ; 56 | context OSVVM_AXI4.Axi4Context ; 57 | 58 | use work.OsvvmTestCommonPkg.all ; 59 | 60 | entity TestCtrl is 61 | port ( 62 | -- Global Signal Interface 63 | nReset : In std_logic ; 64 | 65 | -- Transaction Interfaces 66 | ManagerRec : inout AddressBusRecType ; 67 | SubordinateRec : inout AddressBusRecType 68 | ) ; 69 | 70 | -- Derive AXI interface properties from the ManagerRec 71 | constant AXI_ADDR_WIDTH : integer := ManagerRec.Address'length ; 72 | constant AXI_DATA_WIDTH : integer := ManagerRec.DataToModel'length ; 73 | constant AXI_DATA_BYTE_WIDTH : integer := AXI_DATA_WIDTH / 8 ; 74 | constant AXI_BYTE_ADDR_WIDTH : integer := integer(ceil(log2(real(AXI_DATA_BYTE_WIDTH)))) ; 75 | 76 | -- Simplifying access to Burst FIFOs using aliases 77 | alias WriteBurstFifo : ScoreboardIdType is ManagerRec.WriteBurstFifo ; 78 | alias ReadBurstFifo : ScoreboardIdType is ManagerRec.ReadBurstFifo ; 79 | 80 | end entity TestCtrl ; 81 | -------------------------------------------------------------------------------- /Axi4/testbench/testbench.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_TbAxi4 41 | 42 | analyze ../TestCases/OsvvmTestCommonPkg.vhd 43 | 44 | analyze TestCtrl_e.vhd 45 | analyze TbAxi4.vhd 46 | analyze TbAxi4Memory.vhd 47 | 48 | -------------------------------------------------------------------------------- /Axi4/testbenchVti/TbAxi4.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbAxi4.vhd 3 | -- Design Unit Name: TbAxi4 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Simple AXI Lite Manager Model 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 04/2018 2018 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 12/2020 2020.12 Updated signal and port names 25 | -- 26 | -- 27 | -- This file is part of OSVVM. 28 | -- 29 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 30 | -- 31 | -- Licensed under the Apache License, Version 2.0 (the "License"); 32 | -- you may not use this file except in compliance with the License. 33 | -- You may obtain a copy of the License at 34 | -- 35 | -- https://www.apache.org/licenses/LICENSE-2.0 36 | -- 37 | -- Unless required by applicable law or agreed to in writing, software 38 | -- distributed under the License is distributed on an "AS IS" BASIS, 39 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | -- See the License for the specific language governing permissions and 41 | -- limitations under the License. 42 | -- 43 | 44 | library ieee ; 45 | use ieee.std_logic_1164.all ; 46 | use ieee.numeric_std.all ; 47 | use ieee.numeric_std_unsigned.all ; 48 | 49 | library osvvm ; 50 | context osvvm.OsvvmContext ; 51 | 52 | library OSVVM_AXI4 ; 53 | context OSVVM_AXI4.Axi4Context ; 54 | 55 | entity TbAxi4 is 56 | end entity TbAxi4 ; 57 | architecture TestHarness of TbAxi4 is 58 | constant AXI_ADDR_WIDTH : integer := 32 ; 59 | constant AXI_DATA_WIDTH : integer := 32 ; 60 | constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH/8 ; 61 | 62 | 63 | constant tperiod_Clk : time := 10 ns ; 64 | constant tpd : time := 2 ns ; 65 | 66 | signal Clk : std_logic ; 67 | signal nReset : std_logic ; 68 | 69 | 70 | signal AxiBus : Axi4RecType( 71 | WriteAddress( 72 | Addr(AXI_ADDR_WIDTH-1 downto 0), 73 | ID(7 downto 0), 74 | User(7 downto 0) 75 | ), 76 | WriteData ( 77 | Data(AXI_DATA_WIDTH-1 downto 0), 78 | Strb(AXI_STRB_WIDTH-1 downto 0), 79 | User(7 downto 0), 80 | ID(7 downto 0) 81 | ), 82 | WriteResponse( 83 | ID(7 downto 0), 84 | User(7 downto 0) 85 | ), 86 | ReadAddress ( 87 | Addr(AXI_ADDR_WIDTH-1 downto 0), 88 | ID(7 downto 0), 89 | User(7 downto 0) 90 | ), 91 | ReadData ( 92 | Data(AXI_DATA_WIDTH-1 downto 0), 93 | ID(7 downto 0), 94 | User(7 downto 0) 95 | ) 96 | ) ; 97 | 98 | 99 | component TestCtrl is 100 | port ( 101 | -- Global Signal Interface 102 | nReset : In std_logic 103 | ) ; 104 | end component TestCtrl ; 105 | 106 | 107 | begin 108 | 109 | -- create Clock 110 | Osvvm.ClockResetPkg.CreateClock ( 111 | Clk => Clk, 112 | Period => Tperiod_Clk 113 | ) ; 114 | 115 | -- create nReset 116 | Osvvm.ClockResetPkg.CreateReset ( 117 | Reset => nReset, 118 | ResetActive => '0', 119 | Clk => Clk, 120 | Period => 7 * tperiod_Clk, 121 | tpd => tpd 122 | ) ; 123 | 124 | -- Behavioral model. Replaces DUT for labs 125 | Subordinate_1 : Axi4SubordinateVti 126 | port map ( 127 | -- Globals 128 | Clk => Clk, 129 | nReset => nReset, 130 | 131 | -- AXI Manager Functional Interface 132 | AxiBus => AxiBus 133 | ) ; 134 | 135 | Manager_1 : Axi4ManagerVti 136 | port map ( 137 | -- Globals 138 | Clk => Clk, 139 | nReset => nReset, 140 | 141 | -- AXI Manager Functional Interface 142 | AxiBus => AxiBus 143 | ) ; 144 | 145 | 146 | Monitor_1 : Axi4Monitor 147 | port map ( 148 | -- Globals 149 | Clk => Clk, 150 | nReset => nReset, 151 | 152 | -- AXI Manager Functional Interface 153 | AxiBus => AxiBus 154 | ) ; 155 | 156 | 157 | TestCtrl_1 : TestCtrl 158 | port map ( 159 | -- Globals 160 | nReset => nReset 161 | ) ; 162 | 163 | end architecture TestHarness ; -------------------------------------------------------------------------------- /Axi4/testbenchVti/TbAxi4Memory.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbAxi4Memory.vhd 3 | -- Design Unit Name: TbAxi4Memory 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Simple AXI Lite Manager Model 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 04/2018 2018 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 12/2020 2020.12 Updated signal and port names 25 | -- 26 | -- 27 | -- This file is part of OSVVM. 28 | -- 29 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 30 | -- 31 | -- Licensed under the Apache License, Version 2.0 (the "License"); 32 | -- you may not use this file except in compliance with the License. 33 | -- You may obtain a copy of the License at 34 | -- 35 | -- https://www.apache.org/licenses/LICENSE-2.0 36 | -- 37 | -- Unless required by applicable law or agreed to in writing, software 38 | -- distributed under the License is distributed on an "AS IS" BASIS, 39 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | -- See the License for the specific language governing permissions and 41 | -- limitations under the License. 42 | -- 43 | 44 | library ieee ; 45 | use ieee.std_logic_1164.all ; 46 | use ieee.numeric_std.all ; 47 | use ieee.numeric_std_unsigned.all ; 48 | 49 | library osvvm ; 50 | context osvvm.OsvvmContext ; 51 | 52 | library OSVVM_AXI4 ; 53 | context OSVVM_AXI4.Axi4Context ; 54 | 55 | entity TbAxi4Memory is 56 | end entity TbAxi4Memory ; 57 | architecture TestHarness of TbAxi4Memory is 58 | constant AXI_ADDR_WIDTH : integer := 32 ; 59 | constant AXI_DATA_WIDTH : integer := 32 ; 60 | constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH/8 ; 61 | 62 | 63 | constant tperiod_Clk : time := 10 ns ; 64 | constant tpd : time := 2 ns ; 65 | 66 | signal Clk : std_logic ; 67 | signal nReset : std_logic ; 68 | 69 | 70 | signal AxiBus : Axi4RecType( 71 | WriteAddress( 72 | Addr(AXI_ADDR_WIDTH-1 downto 0), 73 | ID(7 downto 0), 74 | User(7 downto 0) 75 | ), 76 | WriteData ( 77 | Data(AXI_DATA_WIDTH-1 downto 0), 78 | Strb(AXI_STRB_WIDTH-1 downto 0), 79 | User(7 downto 0), 80 | ID(7 downto 0) 81 | ), 82 | WriteResponse( 83 | ID(7 downto 0), 84 | User(7 downto 0) 85 | ), 86 | ReadAddress ( 87 | Addr(AXI_ADDR_WIDTH-1 downto 0), 88 | ID(7 downto 0), 89 | User(7 downto 0) 90 | ), 91 | ReadData ( 92 | Data(AXI_DATA_WIDTH-1 downto 0), 93 | ID(7 downto 0), 94 | User(7 downto 0) 95 | ) 96 | ) ; 97 | 98 | 99 | component TestCtrl is 100 | port ( 101 | -- Global Signal Interface 102 | nReset : In std_logic 103 | ) ; 104 | end component TestCtrl ; 105 | 106 | 107 | begin 108 | 109 | -- create Clock 110 | Osvvm.ClockResetPkg.CreateClock ( 111 | Clk => Clk, 112 | Period => Tperiod_Clk 113 | ) ; 114 | 115 | -- create nReset 116 | Osvvm.ClockResetPkg.CreateReset ( 117 | Reset => nReset, 118 | ResetActive => '0', 119 | Clk => Clk, 120 | Period => 7 * tperiod_Clk, 121 | tpd => tpd 122 | ) ; 123 | 124 | -- Behavioral model. Replaces DUT for labs 125 | Subordinate_1 : Axi4MemoryVti 126 | port map ( 127 | -- Globals 128 | Clk => Clk, 129 | nReset => nReset, 130 | 131 | -- AXI Manager Functional Interface 132 | AxiBus => AxiBus 133 | ) ; 134 | 135 | Manager_1 : Axi4ManagerVti 136 | port map ( 137 | -- Globals 138 | Clk => Clk, 139 | nReset => nReset, 140 | 141 | -- AXI Manager Functional Interface 142 | AxiBus => AxiBus 143 | ) ; 144 | 145 | 146 | Monitor_1 : Axi4Monitor 147 | port map ( 148 | -- Globals 149 | Clk => Clk, 150 | nReset => nReset, 151 | 152 | -- AXI Manager Functional Interface 153 | AxiBus => AxiBus 154 | ) ; 155 | 156 | 157 | TestCtrl_1 : TestCtrl 158 | port map ( 159 | -- Global Signal Interface 160 | nReset => nReset 161 | ) ; 162 | 163 | end architecture TestHarness ; -------------------------------------------------------------------------------- /Axi4/testbenchVti/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 09/2017 2017.09 Initial revision 23 | -- 05/2019 2019.05 Added context reference 24 | -- 01/2020 2020.01 Updated license notice 25 | -- 12/2020 2020.12 Updated port names 26 | -- 27 | -- 28 | -- This file is part of OSVVM. 29 | -- 30 | -- Copyright (c) 2017 - 2020 by SynthWorks Design Inc. 31 | -- 32 | -- Licensed under the Apache License, Version 2.0 (the "License"); 33 | -- you may not use this file except in compliance with the License. 34 | -- You may obtain a copy of the License at 35 | -- 36 | -- https://www.apache.org/licenses/LICENSE-2.0 37 | -- 38 | -- Unless required by applicable law or agreed to in writing, software 39 | -- distributed under the License is distributed on an "AS IS" BASIS, 40 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | -- See the License for the specific language governing permissions and 42 | -- limitations under the License. 43 | -- 44 | 45 | library ieee ; 46 | use ieee.std_logic_1164.all ; 47 | use ieee.numeric_std.all ; 48 | use ieee.numeric_std_unsigned.all ; 49 | use ieee.math_real.all ; 50 | 51 | library OSVVM ; 52 | context OSVVM.OsvvmContext ; 53 | use osvvm.ScoreboardPkg_slv.all ; 54 | 55 | library OSVVM_AXI4 ; 56 | context OSVVM_AXI4.Axi4Context ; 57 | 58 | use work.OsvvmTestCommonPkg.all ; 59 | 60 | entity TestCtrl is 61 | port ( 62 | -- Global Signal Interface 63 | nReset : In std_logic 64 | ) ; 65 | 66 | -- Connect transaction interfaces using external names 67 | alias ManagerRec is <> ; 68 | alias SubordinateRec is <> ; 69 | 70 | -- Derive AXI interface properties from the ManagerRec 71 | constant AXI_ADDR_WIDTH : integer := ManagerRec.Address'length ; 72 | constant AXI_DATA_WIDTH : integer := ManagerRec.DataToModel'length ; 73 | constant AXI_DATA_BYTE_WIDTH : integer := AXI_DATA_WIDTH / 8 ; 74 | constant AXI_BYTE_ADDR_WIDTH : integer := integer(ceil(log2(real(AXI_DATA_BYTE_WIDTH)))) ; 75 | 76 | -- Simplifying access to Burst FIFOs using aliases 77 | alias WriteBurstFifo : ScoreboardIdType is ManagerRec.WriteBurstFifo ; 78 | alias ReadBurstFifo : ScoreboardIdType is ManagerRec.ReadBurstFifo ; 79 | 80 | end entity TestCtrl ; 81 | -------------------------------------------------------------------------------- /Axi4/testbenchVti/testbenchVti.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_TbAxi4Vti 41 | 42 | analyze ../TestCases/OsvvmTestCommonPkg.vhd 43 | 44 | analyze TestCtrl_e.vhd 45 | analyze TbAxi4.vhd 46 | analyze TbAxi4Memory.vhd 47 | -------------------------------------------------------------------------------- /Axi4/testbench_GenericSignals/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 09/2017 2017.09 Initial revision 23 | -- 05/2019 2019.05 Added context reference 24 | -- 01/2020 2020.01 Updated license notice 25 | -- 12/2020 2020.12 Updated port names 26 | -- 27 | -- 28 | -- This file is part of OSVVM. 29 | -- 30 | -- Copyright (c) 2017 - 2020 by SynthWorks Design Inc. 31 | -- 32 | -- Licensed under the Apache License, Version 2.0 (the "License"); 33 | -- you may not use this file except in compliance with the License. 34 | -- You may obtain a copy of the License at 35 | -- 36 | -- https://www.apache.org/licenses/LICENSE-2.0 37 | -- 38 | -- Unless required by applicable law or agreed to in writing, software 39 | -- distributed under the License is distributed on an "AS IS" BASIS, 40 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | -- See the License for the specific language governing permissions and 42 | -- limitations under the License. 43 | -- 44 | 45 | library ieee ; 46 | use ieee.std_logic_1164.all ; 47 | use ieee.numeric_std.all ; 48 | use ieee.numeric_std_unsigned.all ; 49 | use ieee.math_real.all ; 50 | 51 | library OSVVM ; 52 | context OSVVM.OsvvmContext ; 53 | use osvvm.ScoreboardPkg_slv.all ; 54 | 55 | library OSVVM_AXI4 ; 56 | context OSVVM_AXI4.Axi4Context ; 57 | 58 | use work.OsvvmTestCommonPkg.all ; 59 | 60 | entity TestCtrl is 61 | port ( 62 | -- Global Signal Interface 63 | nReset : In std_logic ; 64 | 65 | -- Transaction Interfaces 66 | ManagerRec : inout AddressBusRecType ; 67 | SubordinateRec : inout AddressBusRecType 68 | ) ; 69 | 70 | -- Derive AXI interface properties from the ManagerRec 71 | constant AXI_ADDR_WIDTH : integer := ManagerRec.Address'length ; 72 | constant AXI_DATA_WIDTH : integer := ManagerRec.DataToModel'length ; 73 | constant AXI_DATA_BYTE_WIDTH : integer := AXI_DATA_WIDTH / 8 ; 74 | constant AXI_BYTE_ADDR_WIDTH : integer := integer(ceil(log2(real(AXI_DATA_BYTE_WIDTH)))) ; 75 | 76 | -- Simplifying access to Burst FIFOs using aliases 77 | alias WriteBurstFifo : ScoreboardIdType is ManagerRec.WriteBurstFifo ; 78 | alias ReadBurstFifo : ScoreboardIdType is ManagerRec.ReadBurstFifo ; 79 | end entity TestCtrl ; 80 | -------------------------------------------------------------------------------- /Axi4/testbench_GenericSignals/build.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | analyze ../TestCases/OsvvmTestCommonPkg.vhd 41 | 42 | analyze TestCtrl_e.vhd 43 | analyze TbAxi4.vhd 44 | analyze TbAxi4Memory.vhd 45 | 46 | -------------------------------------------------------------------------------- /Axi4/testbench_MultipleMemory/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 09/2017 2017.09 Initial revision 23 | -- 05/2019 2019.05 Added context reference 24 | -- 01/2020 2020.01 Updated license notice 25 | -- 12/2020 2020.12 Updated port names 26 | -- 27 | -- 28 | -- This file is part of OSVVM. 29 | -- 30 | -- Copyright (c) 2017 - 2020 by SynthWorks Design Inc. 31 | -- 32 | -- Licensed under the Apache License, Version 2.0 (the "License"); 33 | -- you may not use this file except in compliance with the License. 34 | -- You may obtain a copy of the License at 35 | -- 36 | -- https://www.apache.org/licenses/LICENSE-2.0 37 | -- 38 | -- Unless required by applicable law or agreed to in writing, software 39 | -- distributed under the License is distributed on an "AS IS" BASIS, 40 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | -- See the License for the specific language governing permissions and 42 | -- limitations under the License. 43 | -- 44 | 45 | library ieee ; 46 | use ieee.std_logic_1164.all ; 47 | use ieee.numeric_std.all ; 48 | use ieee.numeric_std_unsigned.all ; 49 | use ieee.math_real.all ; 50 | 51 | library OSVVM ; 52 | context OSVVM.OsvvmContext ; 53 | use osvvm.ScoreboardPkg_slv.all ; 54 | 55 | library OSVVM_AXI4 ; 56 | context OSVVM_AXI4.Axi4Context ; 57 | 58 | use work.OsvvmTestCommonPkg.all ; 59 | 60 | entity TestCtrl is 61 | port ( 62 | -- Global Signal Interface 63 | nReset : In std_logic ; 64 | 65 | -- Transaction Interfaces 66 | Manager1Rec : inout AddressBusRecType ; 67 | Subordinate1Rec : inout AddressBusRecType ; 68 | 69 | Manager2Rec : inout AddressBusRecType ; 70 | Subordinate2Rec : inout AddressBusRecType 71 | ) ; 72 | 73 | -- Derive AXI interface properties from the ManagerRec 74 | constant AXI_ADDR_WIDTH : integer := Manager1Rec.Address'length ; 75 | constant AXI_DATA_WIDTH : integer := Manager1Rec.DataToModel'length ; 76 | constant AXI_DATA_BYTE_WIDTH : integer := AXI_DATA_WIDTH / 8 ; 77 | constant AXI_BYTE_ADDR_WIDTH : integer := integer(ceil(log2(real(AXI_DATA_BYTE_WIDTH)))) ; 78 | 79 | -- Simplifying access to Burst FIFOs using aliases 80 | alias WriteBurstFifo1 : ScoreboardIdType is Manager1Rec.WriteBurstFifo ; 81 | alias ReadBurstFifo1 : ScoreboardIdType is Manager1Rec.ReadBurstFifo ; 82 | alias WriteBurstFifo2 : ScoreboardIdType is Manager2Rec.WriteBurstFifo ; 83 | alias ReadBurstFifo2 : ScoreboardIdType is Manager2Rec.ReadBurstFifo ; 84 | end entity TestCtrl ; 85 | -------------------------------------------------------------------------------- /Axi4/testbench_MultipleMemory/testbench_MultipleMemory.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_TbAxi4_MultipleMemory 41 | 42 | analyze ../TestCases/OsvvmTestCommonPkg.vhd 43 | 44 | analyze TestCtrl_e.vhd 45 | analyze TbAxi4_MultipleMemory.vhd 46 | 47 | RunTest TbAxi4_Shared1.vhd 48 | RunTest TbAxi4_Separate1.vhd -------------------------------------------------------------------------------- /Axi4/testbench_MultipleMemory/testbench_MultipleMemory_Generate.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_TbAxi4_MultipleMemory_G 41 | 42 | analyze ../TestCases/OsvvmTestCommonPkg.vhd 43 | 44 | analyze TestCtrl_e.vhd 45 | analyze TbAxi4_MultipleMemory_Generate.vhd 46 | 47 | # Will not work with current configuration 48 | # Working configuration is commented out 49 | RunTest TbAxi4_Shared1.vhd 50 | RunTest TbAxi4_Separate1.vhd -------------------------------------------------------------------------------- /Axi4/testbench_interrupt/README.md: -------------------------------------------------------------------------------- 1 | # Interrupt Tests are MOVING 2 | 3 | The tests have moved to OsvvmLibraries/Common/TbInterrupt 4 | Eventually the files here will be deleted. -------------------------------------------------------------------------------- /Axi4/testbench_interrupt/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 09/2017 2017.09 Initial revision 23 | -- 05/2019 2019.05 Added context reference 24 | -- 01/2020 2020.01 Updated license notice 25 | -- 12/2020 2020.12 Updated port names 26 | -- 27 | -- 28 | -- This file is part of OSVVM. 29 | -- 30 | -- Copyright (c) 2017 - 2020 by SynthWorks Design Inc. 31 | -- 32 | -- Licensed under the Apache License, Version 2.0 (the "License"); 33 | -- you may not use this file except in compliance with the License. 34 | -- You may obtain a copy of the License at 35 | -- 36 | -- https://www.apache.org/licenses/LICENSE-2.0 37 | -- 38 | -- Unless required by applicable law or agreed to in writing, software 39 | -- distributed under the License is distributed on an "AS IS" BASIS, 40 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | -- See the License for the specific language governing permissions and 42 | -- limitations under the License. 43 | -- 44 | 45 | library ieee ; 46 | use ieee.std_logic_1164.all ; 47 | use ieee.numeric_std.all ; 48 | use ieee.numeric_std_unsigned.all ; 49 | use ieee.math_real.all ; 50 | 51 | library OSVVM ; 52 | context OSVVM.OsvvmContext ; 53 | 54 | library OSVVM_AXI4 ; 55 | context OSVVM_AXI4.Axi4Context ; 56 | use osvvm.ScoreboardPkg_slv.all ; 57 | 58 | use work.OsvvmTestCommonPkg.all ; 59 | 60 | entity TestCtrl is 61 | port ( 62 | -- Global Signal Interface 63 | nReset : In std_logic ; 64 | 65 | -- Drive IntReq 66 | IntReq : Out std_logic := '0' ; 67 | 68 | -- Transaction Interfaces 69 | ManagerRec : inout AddressBusRecType ; 70 | InterruptRec : inout AddressBusRecType ; 71 | SubordinateRec : inout AddressBusRecType 72 | ) ; 73 | 74 | -- Derive AXI interface properties from the ManagerRec 75 | constant AXI_ADDR_WIDTH : integer := ManagerRec.Address'length ; 76 | constant AXI_DATA_WIDTH : integer := ManagerRec.DataToModel'length ; 77 | constant AXI_DATA_BYTE_WIDTH : integer := AXI_DATA_WIDTH / 8 ; 78 | constant AXI_BYTE_ADDR_WIDTH : integer := integer(ceil(log2(real(AXI_DATA_BYTE_WIDTH)))) ; 79 | 80 | end entity TestCtrl ; 81 | -------------------------------------------------------------------------------- /Axi4/testbench_interrupt/testbench_interrupt.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench_interrupt.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | TestSuite Axi4Full_Interrupt 41 | library Axi4Full_Interrupt 42 | 43 | analyze ../TestCases/OsvvmTestCommonPkg.vhd 44 | 45 | analyze TestCtrl_e.vhd 46 | # analyze TbAxi4.vhd 47 | analyze TbAxi4Memory.vhd 48 | 49 | RunTest TbAxi4_Interrupt1.vhd 50 | RunTest TbAxi4_Interrupt2.vhd 51 | RunTest TbAxi4_InterruptBurst1.vhd 52 | RunTest TbAxi4_InterruptBurst2.vhd 53 | 54 | RunTest TbAxi4_InterruptNoHandler1.vhd 55 | #RunTest TbAxi4_InterruptNoHandler2.vhd 56 | 57 | -------------------------------------------------------------------------------- /Axi4/testbench_xilinx/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 09/2017 2017.09 Initial revision 23 | -- 05/2019 2019.05 Added context reference 24 | -- 01/2020 2020.01 Updated license notice 25 | -- 12/2020 2020.12 Updated port names 26 | -- 27 | -- 28 | -- This file is part of OSVVM. 29 | -- 30 | -- Copyright (c) 2017 - 2020 by SynthWorks Design Inc. 31 | -- 32 | -- Licensed under the Apache License, Version 2.0 (the "License"); 33 | -- you may not use this file except in compliance with the License. 34 | -- You may obtain a copy of the License at 35 | -- 36 | -- https://www.apache.org/licenses/LICENSE-2.0 37 | -- 38 | -- Unless required by applicable law or agreed to in writing, software 39 | -- distributed under the License is distributed on an "AS IS" BASIS, 40 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | -- See the License for the specific language governing permissions and 42 | -- limitations under the License. 43 | -- 44 | 45 | library ieee ; 46 | use ieee.std_logic_1164.all ; 47 | use ieee.numeric_std.all ; 48 | use ieee.numeric_std_unsigned.all ; 49 | use ieee.math_real.all ; 50 | 51 | library OSVVM ; 52 | context OSVVM.OsvvmContext ; 53 | use osvvm.ScoreboardPkg_slv.all ; 54 | 55 | library OSVVM_AXI4 ; 56 | context OSVVM_AXI4.Axi4Context ; 57 | 58 | use work.OsvvmTestCommonPkg.all ; 59 | 60 | entity TestCtrl is 61 | port ( 62 | -- Global Signal Interface 63 | nReset : In std_logic ; 64 | 65 | -- Transaction Interfaces 66 | ManagerRec : inout AddressBusRecType ; 67 | SubordinateRec : inout AddressBusRecType 68 | ) ; 69 | 70 | -- Derive AXI interface properties from the ManagerRec 71 | --x constant AXI_ADDR_WIDTH : integer := ManagerRec.Address'length ; 72 | --x constant AXI_DATA_WIDTH : integer := ManagerRec.DataToModel'length ; 73 | constant AXI_ADDR_WIDTH : integer := 32 ; 74 | constant AXI_DATA_WIDTH : integer := 32 ; 75 | constant AXI_DATA_BYTE_WIDTH : integer := AXI_DATA_WIDTH / 8 ; 76 | constant AXI_BYTE_ADDR_WIDTH : integer := integer(ceil(log2(real(AXI_DATA_BYTE_WIDTH)))) ; 77 | 78 | -- Simplifying access to Burst FIFOs using aliases 79 | alias WriteBurstFifo : ScoreboardIdType is ManagerRec.WriteBurstFifo ; 80 | alias ReadBurstFifo : ScoreboardIdType is ManagerRec.ReadBurstFifo ; 81 | end entity TestCtrl ; 82 | -------------------------------------------------------------------------------- /Axi4/testbench_xilinx/build.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_TbAxi4_xilinx 41 | 42 | analyze ../TestCases/OsvvmTestCommonPkg.vhd 43 | 44 | analyze TestCtrl_e.vhd 45 | # analyze TbAxi4.vhd 46 | analyze TbAxi4Memory.vhd 47 | 48 | analyze TbAxi4_DemoMemoryReadWrite1.vhd 49 | TestName TbAxi4_DemoMemoryReadWrite1 50 | simulate TbAxi4Memory 51 | 52 | -------------------------------------------------------------------------------- /Axi4/testbench_xilinx/build_one.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_axi4 41 | analyze ../src/Axi4Manager_xilinx.vhd 42 | analyze ../src/Axi4Memory_xilinx.vhd 43 | 44 | library osvvm_TbAxi4_xilinx 45 | 46 | analyze TbAxi4Memory.vhd 47 | analyze TbAxi4_DemoMemoryReadWrite1.vhd 48 | TestName TbAxi4_DemoMemoryReadWrite1 49 | simulate TbAxi4Memory 50 | 51 | -------------------------------------------------------------------------------- /Axi4Lite/Axi4Lite.pro: -------------------------------------------------------------------------------- 1 | # File Name: Axi4Lite.pro 2 | # Revision: OSVVM MODELS STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to compile the Axi4 Lite models 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_axi4 41 | analyze ./src/Axi4LiteComponentPkg.vhd 42 | analyze ./src/Axi4LiteContext.vhd 43 | analyze ./src/Axi4LiteManager.vhd 44 | analyze ./src/Axi4LiteMonitor_dummy.vhd 45 | analyze ./src/Axi4LiteSubordinate.vhd 46 | analyze ./src/Axi4LiteMemory.vhd 47 | analyze ./src/Axi4LitePassThru.vhd 48 | 49 | -------------------------------------------------------------------------------- /Axi4Lite/RunAllTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: OSVVM MODELS STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi4 Lite tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | TestSuite Axi4Lite 41 | library osvvm_TbAxi4Lite 42 | 43 | 44 | if {$::osvvm::ToolNameVersion ne "XSIM-2023.2"} { 45 | include ./testbench/build.pro 46 | include ./TestCases/RunAllTests.pro 47 | } else { 48 | SkipTest Axi4VC "Axi4Lite VC not working in XSIM" 49 | } 50 | -------------------------------------------------------------------------------- /Axi4Lite/RunDemoTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: OSVVM MODELS STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi4 Lite tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | TestSuite Axi4Lite 41 | library osvvm_TbAxi4Lite 42 | 43 | include ./testbench/build.pro 44 | include ./TestCases/RunDemoTests.pro -------------------------------------------------------------------------------- /Axi4Lite/TestCases/RunAllTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: OSVVM MODELS STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 Lite test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | RunTest TbAxi4_BasicReadWrite.vhd 42 | RunTest TbAxi4_ReadWriteAsync1.vhd 43 | RunTest TbAxi4_ReadWriteAsync2.vhd 44 | RunTest TbAxi4_ReadWriteAsync3.vhd 45 | RunTest TbAxi4_RandomReadWrite.vhd 46 | RunTest TbAxi4_RandomReadWriteByte.vhd 47 | RunTest TbAxi4_TimeOut.vhd 48 | RunTest TbAxi4_WriteOptions.vhd 49 | RunTest TbAxi4_MemoryReadWrite1.vhd 50 | 51 | RunTest TbAxi4_AxiXResp.vhd 52 | RunTest TbAxi4_AxiXResp2_Enum.vhd 53 | 54 | # Testing Valid and Ready Randomization 55 | RunTest TbAxi4_NoRandomTiming1.vhd 56 | RunTest TbAxi4_ManagerRandomTiming1.vhd 57 | RunTest TbAxi4_MemoryRandomTiming1.vhd 58 | RunTest TbAxi4_SubordinateRandomTiming1.vhd 59 | RunTest TbAxi4_ManagerMemoryRandomTiming1.vhd 60 | RunTest TbAxi4_ManagerSubordinateRandomTiming1.vhd 61 | -------------------------------------------------------------------------------- /Axi4Lite/TestCases/RunDemoTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: OSVVM MODELS STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 Lite test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | RunTest TbAxi4_RandomReadWrite.vhd 42 | # RunTest TbAxi4_AxiXResp2_Enum.vhd 43 | 44 | # Testing Valid and Ready Randomization 45 | # RunTest TbAxi4_NoRandomTiming1.vhd 46 | # RunTest TbAxi4_ManagerRandomTiming1.vhd 47 | # RunTest TbAxi4_MemoryRandomTiming1.vhd 48 | # RunTest TbAxi4_SubordinateRandomTiming1.vhd 49 | # RunTest TbAxi4_ManagerMemoryRandomTiming1.vhd 50 | # RunTest TbAxi4_ManagerSubordinateRandomTiming1.vhd 51 | 52 | -------------------------------------------------------------------------------- /Axi4Lite/src/Axi4LiteContext.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: Axi4LiteContext.vhd 3 | -- Design Unit Name: Axi4LiteContext 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- 8 | -- Description 9 | -- Context Declaration for using Axi4 models 10 | -- 11 | -- Developed by/for: 12 | -- SynthWorks Design Inc. 13 | -- VHDL Training Classes 14 | -- 11898 SW 128th Ave. Tigard, Or 97223 15 | -- http://www.SynthWorks.com 16 | -- 17 | -- Revision History: 18 | -- Date Version Description 19 | -- 11/2022 2022.11 Added Axi4OptionsArrayPkg 20 | -- 01/2020 2020.01 Updated license notice 21 | -- 03/2019 2019.03 Initial Revision 22 | -- 23 | -- 24 | -- This file is part of OSVVM. 25 | -- 26 | -- Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | -- 28 | -- Licensed under the Apache License, Version 2.0 (the "License"); 29 | -- you may not use this file except in compliance with the License. 30 | -- You may obtain a copy of the License at 31 | -- 32 | -- https://www.apache.org/licenses/LICENSE-2.0 33 | -- 34 | -- Unless required by applicable law or agreed to in writing, software 35 | -- distributed under the License is distributed on an "AS IS" BASIS, 36 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | -- See the License for the specific language governing permissions and 38 | -- limitations under the License. 39 | -- 40 | 41 | context Axi4LiteContext is 42 | library osvvm_common ; 43 | context osvvm_common.OsvvmCommonContext ; 44 | 45 | library osvvm_Axi4 ; 46 | 47 | use osvvm_Axi4.Axi4CommonPkg.all ; 48 | use osvvm_Axi4.Axi4InterfaceCommonPkg.all ; 49 | use osvvm_Axi4.Axi4LiteInterfacePkg.all ; 50 | 51 | use osvvm_Axi4.Axi4OptionsPkg.all ; 52 | use osvvm_Axi4.Axi4OptionsArrayPkg.all ; 53 | use osvvm_Axi4.Axi4ModelPkg.all ; 54 | 55 | use osvvm_Axi4.Axi4LiteComponentPkg.all ; 56 | 57 | -- Temporary inclusion of Axi4 things that become deprecated with changes 58 | use osvvm_Axi4.Axi4VersionCompatibilityPkg.all ; 59 | 60 | end context Axi4LiteContext ; -------------------------------------------------------------------------------- /Axi4Lite/src/Axi4LiteMonitor_dummy.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: Axi4LiteMonitor.vhd 3 | -- Design Unit Name: Axi4LiteMonitor 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- AXI Lite Monitor dummy model 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 09/2017 2017 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | library ieee ; 43 | use ieee.std_logic_1164.all ; 44 | use ieee.numeric_std.all ; 45 | use ieee.numeric_std_unsigned.all ; 46 | 47 | library osvvm ; 48 | context osvvm.OsvvmContext ; 49 | 50 | use work.Axi4InterfaceCommonPkg.all ; 51 | use work.Axi4LiteInterfacePkg.all ; 52 | use work.Axi4CommonPkg.all ; 53 | 54 | entity Axi4LiteMonitor is 55 | port ( 56 | -- Globals 57 | Clk : in std_logic ; 58 | nReset : in std_logic ; 59 | 60 | -- AXI Master Functional Interface 61 | AxiBus : in Axi4LiteRecType 62 | ) ; 63 | 64 | end entity Axi4LiteMonitor ; 65 | architecture Monitor of Axi4LiteMonitor is 66 | 67 | -- alias AB : AxiBus'subtype is AxiBus ; 68 | -- alias AW is AB.WriteAddress ; 69 | -- alias WD is AB.WriteData ; 70 | -- alias WR is AB.WriteResponse ; 71 | -- alias AR is AB.ReadAddress ; 72 | -- alias RD is AB.ReadData ; 73 | 74 | constant MODEL_INSTANCE_NAME : string := PathTail(to_lower(Axi4LiteMonitor'PATH_NAME)) ; 75 | signal ModelID, ProtocolID, DataCheckID, BusFailedID : AlertLogIDType ; 76 | 77 | 78 | begin 79 | 80 | 81 | 82 | end architecture Monitor ; 83 | -------------------------------------------------------------------------------- /Axi4Lite/src/Axi4LitePassThru.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: Axi4LitePassThru.vhd 3 | -- Design Unit Name: Axi4LitePassThru 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- DUT pass thru for Axi4 VC testing 13 | -- Used to demonstrate DUT connections 14 | -- 15 | -- 16 | -- Developed by: 17 | -- SynthWorks Design Inc. 18 | -- VHDL Training Classes 19 | -- http://www.SynthWorks.com 20 | -- 21 | -- Revision History: 22 | -- Date Version Description 23 | -- 01/2023 2023.01 Initial 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2023 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | 43 | library ieee ; 44 | use ieee.std_logic_1164.all ; 45 | use ieee.numeric_std.all ; 46 | use ieee.numeric_std_unsigned.all ; 47 | use ieee.math_real.all ; 48 | 49 | library osvvm ; 50 | context osvvm.OsvvmContext ; 51 | 52 | use work.Axi4InterfaceCommonPkg.all ; 53 | use work.Axi4InterfacePkg.all ; 54 | 55 | entity Axi4LitePassThru is 56 | port ( 57 | -- AXI Manager Interface 58 | -- AXI Write Address Channel 59 | mAwAddr : out std_logic_vector ; 60 | mAwProt : out Axi4ProtType ; 61 | mAwValid : out std_logic ; 62 | mAwReady : in std_logic ; 63 | 64 | -- AXI Write Data Channel 65 | mWData : out std_logic_vector ; 66 | mWStrb : out std_logic_vector ; 67 | mWValid : out std_logic ; 68 | mWReady : in std_logic ; 69 | 70 | -- AXI Write Response Channel 71 | mBValid : in std_logic ; 72 | mBReady : out std_logic ; 73 | mBResp : in Axi4RespType ; 74 | 75 | -- AXI Read Address Channel 76 | mArAddr : out std_logic_vector ; 77 | mArProt : out Axi4ProtType ; 78 | mArValid : out std_logic ; 79 | mArReady : in std_logic ; 80 | 81 | -- AXI Read Data Channel 82 | mRData : in std_logic_vector ; 83 | mRResp : in Axi4RespType ; 84 | mRValid : in std_logic ; 85 | mRReady : out std_logic ; 86 | 87 | 88 | -- AXI Subordinate Interface 89 | -- AXI Write Address Channel 90 | sAwAddr : in std_logic_vector ; 91 | sAwProt : in Axi4ProtType ; 92 | sAwValid : in std_logic ; 93 | sAwReady : out std_logic ; 94 | 95 | -- AXI Write Data Channel 96 | sWData : in std_logic_vector ; 97 | sWStrb : in std_logic_vector ; 98 | sWValid : in std_logic ; 99 | sWReady : out std_logic ; 100 | 101 | -- AXI Write Response Channel 102 | sBValid : out std_logic ; 103 | sBReady : in std_logic ; 104 | sBResp : out Axi4RespType ; 105 | 106 | 107 | -- AXI Read Address Channel 108 | sArAddr : in std_logic_vector ; 109 | sArProt : in Axi4ProtType ; 110 | sArValid : in std_logic ; 111 | sArReady : out std_logic ; 112 | 113 | -- AXI Read Data Channel 114 | sRData : out std_logic_vector ; 115 | sRResp : out Axi4RespType ; 116 | sRValid : out std_logic ; 117 | sRReady : in std_logic 118 | ) ; 119 | end entity Axi4LitePassThru ; 120 | 121 | architecture FeedThru of Axi4LitePassThru is 122 | 123 | 124 | begin 125 | 126 | -- AXI Write Address Channel 127 | mAwAddr <= sAwAddr ; 128 | mAwProt <= sAwProt ; 129 | mAwValid <= sAwValid ; 130 | sAwReady <= mAwReady ; 131 | 132 | -- AXI Write Data Channel 133 | mWData <= sWData ; 134 | mWStrb <= sWStrb ; 135 | mWValid <= sWValid ; 136 | sWReady <= mWReady ; 137 | 138 | -- AXI Write Response Channel 139 | sBValid <= mBValid ; 140 | mBReady <= sBReady ; 141 | sBResp <= mBResp ; 142 | 143 | -- AXI Read Address Channel 144 | mArAddr <= sArAddr ; 145 | mArProt <= sArProt ; 146 | mArValid <= sArValid ; 147 | sArReady <= mArReady ; 148 | 149 | -- AXI Read Data Channel 150 | sRData <= mRData ; 151 | sRResp <= mRResp ; 152 | sRValid <= mRValid ; 153 | mRReady <= sRReady ; 154 | 155 | end architecture FeedThru ; 156 | -------------------------------------------------------------------------------- /Axi4Lite/testbench/OsvvmTestCommonPkg.vhd: -------------------------------------------------------------------------------- 1 | package OsvvmTestCommonPkg is 2 | constant OSVVM_RESULTS_DIR : string := "" ; 3 | constant OSVVM_PATH_TO_TESTS : string := "../../OsvvmLibraries/" ; 4 | end package OsvvmTestCommonPkg ; 5 | -------------------------------------------------------------------------------- /Axi4Lite/testbench/TbAxi4.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbAxi4.vhd 3 | -- Design Unit Name: TbAxi4 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Simple AXI Lite Manager Model 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 04/2018 2018 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 12/2020 2020.12 Updated signal and port names 25 | -- 26 | -- 27 | -- This file is part of OSVVM. 28 | -- 29 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 30 | -- 31 | -- Licensed under the Apache License, Version 2.0 (the "License"); 32 | -- you may not use this file except in compliance with the License. 33 | -- You may obtain a copy of the License at 34 | -- 35 | -- https://www.apache.org/licenses/LICENSE-2.0 36 | -- 37 | -- Unless required by applicable law or agreed to in writing, software 38 | -- distributed under the License is distributed on an "AS IS" BASIS, 39 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | -- See the License for the specific language governing permissions and 41 | -- limitations under the License. 42 | -- 43 | 44 | library ieee ; 45 | use ieee.std_logic_1164.all ; 46 | use ieee.numeric_std.all ; 47 | use ieee.numeric_std_unsigned.all ; 48 | 49 | library osvvm ; 50 | context osvvm.OsvvmContext ; 51 | 52 | library osvvm_Axi4 ; 53 | context osvvm_Axi4.Axi4LiteContext ; 54 | 55 | entity TbAxi4 is 56 | end entity TbAxi4 ; 57 | architecture TestHarness of TbAxi4 is 58 | constant AXI_ADDR_WIDTH : integer := 32 ; 59 | constant AXI_DATA_WIDTH : integer := 32 ; 60 | constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH/8 ; 61 | 62 | constant tperiod_Clk : time := 10 ns ; 63 | constant tpd : time := 2 ns ; 64 | 65 | signal Clk : std_logic ; 66 | signal nReset : std_logic ; 67 | 68 | signal ManagerRec, SubordinateRec : AddressBusRecType( 69 | Address(AXI_ADDR_WIDTH-1 downto 0), 70 | DataToModel(AXI_DATA_WIDTH-1 downto 0), 71 | DataFromModel(AXI_DATA_WIDTH-1 downto 0) 72 | ) ; 73 | 74 | -- -- AXI Manager Functional Interface 75 | signal AxiBus : Axi4LiteRecType( 76 | WriteAddress( Addr (AXI_ADDR_WIDTH-1 downto 0) ), 77 | WriteData ( Data (AXI_DATA_WIDTH-1 downto 0), Strb(AXI_STRB_WIDTH-1 downto 0) ), 78 | ReadAddress ( Addr (AXI_ADDR_WIDTH-1 downto 0) ), 79 | ReadData ( Data (AXI_DATA_WIDTH-1 downto 0) ) 80 | ) ; 81 | 82 | 83 | component TestCtrl is 84 | port ( 85 | -- Global Signal Interface 86 | Clk : In std_logic ; 87 | nReset : In std_logic ; 88 | 89 | -- Transaction Interfaces 90 | ManagerRec : inout AddressBusRecType ; 91 | SubordinateRec : inout AddressBusRecType 92 | ) ; 93 | end component TestCtrl ; 94 | 95 | 96 | begin 97 | 98 | -- create Clock 99 | Osvvm.ClockResetPkg.CreateClock ( 100 | Clk => Clk, 101 | Period => Tperiod_Clk 102 | ) ; 103 | 104 | -- create nReset 105 | Osvvm.ClockResetPkg.CreateReset ( 106 | Reset => nReset, 107 | ResetActive => '0', 108 | Clk => Clk, 109 | Period => 7 * tperiod_Clk, 110 | tpd => tpd 111 | ) ; 112 | 113 | -- Behavioral model. Replaces DUT for labs 114 | Subordinate_1 : Axi4LiteSubordinate 115 | port map ( 116 | -- Globals 117 | Clk => Clk, 118 | nReset => nReset, 119 | 120 | -- AXI Manager Functional Interface 121 | AxiBus => AxiBus, 122 | 123 | -- Testbench Transaction Interface 124 | TransRec => SubordinateRec 125 | ) ; 126 | 127 | Manager_1 : Axi4LiteManager 128 | port map ( 129 | -- Globals 130 | Clk => Clk, 131 | nReset => nReset, 132 | 133 | -- AXI Manager Functional Interface 134 | AxiBus => AxiBus, 135 | 136 | -- Testbench Transaction Interface 137 | TransRec => ManagerRec 138 | ) ; 139 | 140 | 141 | Monitor_1 : Axi4LiteMonitor 142 | port map ( 143 | -- Globals 144 | Clk => Clk, 145 | nReset => nReset, 146 | 147 | -- AXI Manager Functional Interface 148 | AxiBus => AxiBus 149 | ) ; 150 | 151 | 152 | TestCtrl_1 : TestCtrl 153 | port map ( 154 | -- Globals 155 | Clk => Clk, 156 | nReset => nReset, 157 | 158 | -- Testbench Transaction Interfaces 159 | ManagerRec => ManagerRec, 160 | SubordinateRec => SubordinateRec 161 | ) ; 162 | 163 | end architecture TestHarness ; -------------------------------------------------------------------------------- /Axi4Lite/testbench/TbAxi4Memory.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbAxi4Memory.vhd 3 | -- Design Unit Name: TbAxi4Memory 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Simple AXI Lite Manager Model 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 04/2018 2018 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 12/2020 2020.12 Updated signal and port names 25 | -- 26 | -- 27 | -- This file is part of OSVVM. 28 | -- 29 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 30 | -- 31 | -- Licensed under the Apache License, Version 2.0 (the "License"); 32 | -- you may not use this file except in compliance with the License. 33 | -- You may obtain a copy of the License at 34 | -- 35 | -- https://www.apache.org/licenses/LICENSE-2.0 36 | -- 37 | -- Unless required by applicable law or agreed to in writing, software 38 | -- distributed under the License is distributed on an "AS IS" BASIS, 39 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | -- See the License for the specific language governing permissions and 41 | -- limitations under the License. 42 | -- 43 | 44 | library ieee ; 45 | use ieee.std_logic_1164.all ; 46 | use ieee.numeric_std.all ; 47 | use ieee.numeric_std_unsigned.all ; 48 | 49 | library osvvm ; 50 | context osvvm.OsvvmContext ; 51 | 52 | library osvvm_Axi4 ; 53 | context osvvm_Axi4.Axi4LiteContext ; 54 | 55 | entity TbAxi4Memory is 56 | end entity TbAxi4Memory ; 57 | architecture TestHarness of TbAxi4Memory is 58 | constant AXI_ADDR_WIDTH : integer := 32 ; 59 | constant AXI_DATA_WIDTH : integer := 32 ; 60 | constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH/8 ; 61 | 62 | constant tperiod_Clk : time := 10 ns ; 63 | constant tpd : time := 2 ns ; 64 | 65 | signal Clk : std_logic ; 66 | signal nReset : std_logic ; 67 | 68 | signal ManagerRec, SubordinateRec : AddressBusRecType( 69 | Address(AXI_ADDR_WIDTH-1 downto 0), 70 | DataToModel(AXI_DATA_WIDTH-1 downto 0), 71 | DataFromModel(AXI_DATA_WIDTH-1 downto 0) 72 | ) ; 73 | 74 | -- -- AXI Manager Functional Interface 75 | signal AxiBus : Axi4LiteRecType( 76 | WriteAddress( Addr (AXI_ADDR_WIDTH-1 downto 0) ), 77 | WriteData ( Data (AXI_DATA_WIDTH-1 downto 0), Strb(AXI_STRB_WIDTH-1 downto 0) ), 78 | ReadAddress ( Addr (AXI_ADDR_WIDTH-1 downto 0) ), 79 | ReadData ( Data (AXI_DATA_WIDTH-1 downto 0) ) 80 | ) ; 81 | 82 | 83 | component TestCtrl is 84 | port ( 85 | -- Global Signal Interface 86 | Clk : In std_logic ; 87 | nReset : In std_logic ; 88 | 89 | -- Transaction Interfaces 90 | ManagerRec : inout AddressBusRecType ; 91 | SubordinateRec : inout AddressBusRecType 92 | ) ; 93 | end component TestCtrl ; 94 | 95 | 96 | begin 97 | 98 | -- create Clock 99 | Osvvm.ClockResetPkg.CreateClock ( 100 | Clk => Clk, 101 | Period => Tperiod_Clk 102 | ) ; 103 | 104 | -- create nReset 105 | Osvvm.ClockResetPkg.CreateReset ( 106 | Reset => nReset, 107 | ResetActive => '0', 108 | Clk => Clk, 109 | Period => 7 * tperiod_Clk, 110 | tpd => tpd 111 | ) ; 112 | 113 | -- Behavioral model. Replaces DUT for demonstration purposes 114 | Subordinate_1 : Axi4LiteMemory 115 | port map ( 116 | -- Globals 117 | Clk => Clk, 118 | nReset => nReset, 119 | 120 | -- AXI Manager Functional Interface 121 | AxiBus => AxiBus, 122 | 123 | -- Testbench Transaction Interface 124 | TransRec => SubordinateRec 125 | ) ; 126 | 127 | Manager_1 : Axi4LiteManager 128 | port map ( 129 | -- Globals 130 | Clk => Clk, 131 | nReset => nReset, 132 | 133 | -- AXI Manager Functional Interface 134 | AxiBus => AxiBus, 135 | 136 | -- Testbench Transaction Interface 137 | TransRec => ManagerRec 138 | ) ; 139 | 140 | 141 | Monitor_1 : Axi4LiteMonitor 142 | port map ( 143 | -- Globals 144 | Clk => Clk, 145 | nReset => nReset, 146 | 147 | -- AXI Manager Functional Interface 148 | AxiBus => AxiBus 149 | ) ; 150 | 151 | 152 | TestCtrl_1 : TestCtrl 153 | port map ( 154 | -- Globals 155 | Clk => Clk, 156 | nReset => nReset, 157 | 158 | -- Testbench Transaction Interfaces 159 | ManagerRec => ManagerRec, 160 | SubordinateRec => SubordinateRec 161 | ) ; 162 | 163 | end architecture TestHarness ; -------------------------------------------------------------------------------- /Axi4Lite/testbench/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 09/2017 2017.09 Initial revision 23 | -- 05/2019 2019.05 Added context reference 24 | -- 01/2020 2020.01 Updated license notice 25 | -- 12/2020 2020.12 Updated port names 26 | -- 27 | -- 28 | -- This file is part of OSVVM. 29 | -- 30 | -- Copyright (c) 2017 - 2020 by SynthWorks Design Inc. 31 | -- 32 | -- Licensed under the Apache License, Version 2.0 (the "License"); 33 | -- you may not use this file except in compliance with the License. 34 | -- You may obtain a copy of the License at 35 | -- 36 | -- https://www.apache.org/licenses/LICENSE-2.0 37 | -- 38 | -- Unless required by applicable law or agreed to in writing, software 39 | -- distributed under the License is distributed on an "AS IS" BASIS, 40 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | -- See the License for the specific language governing permissions and 42 | -- limitations under the License. 43 | -- 44 | 45 | library ieee ; 46 | use ieee.std_logic_1164.all ; 47 | use ieee.numeric_std.all ; 48 | use ieee.numeric_std_unsigned.all ; 49 | 50 | library OSVVM ; 51 | context OSVVM.OsvvmContext ; 52 | 53 | library osvvm_Axi4 ; 54 | context osvvm_Axi4.Axi4LiteContext ; 55 | 56 | use work.OsvvmTestCommonPkg.all ; 57 | 58 | entity TestCtrl is 59 | port ( 60 | -- Global Signal Interface 61 | Clk : In std_logic ; 62 | nReset : In std_logic ; 63 | 64 | -- Transaction Interfaces 65 | ManagerRec : inout AddressBusRecType ; 66 | SubordinateRec : inout AddressBusRecType 67 | 68 | ) ; 69 | constant AXI_ADDR_WIDTH : integer := ManagerRec.Address'length ; 70 | constant AXI_DATA_WIDTH : integer := ManagerRec.DataToModel'length ; 71 | 72 | -- Not currently used in the Axi4Lite model - future use for Axi4Lite Burst Emulation modes 73 | -- alias WriteBurstFifo is <> ; 74 | -- alias ReadBurstFifo is <> ; 75 | end entity TestCtrl ; 76 | -------------------------------------------------------------------------------- /Axi4Lite/testbench/build.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: OSVVM MODELS STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi4 Lite test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | library osvvm_TbAxi4Lite 42 | 43 | analyze OsvvmTestCommonPkg.vhd 44 | 45 | analyze TestCtrl_e.vhd 46 | analyze TbAxi4.vhd 47 | analyze TbAxi4Memory.vhd 48 | 49 | -------------------------------------------------------------------------------- /AxiStream/.gitignore: -------------------------------------------------------------------------------- 1 | /ValidatedResults_2023/ 2 | -------------------------------------------------------------------------------- /AxiStream/AxiStream.pro: -------------------------------------------------------------------------------- 1 | # File Name: AxiStream.pro 2 | # Revision: OSVVM MODELS STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to compile the Axi Stream models 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | include src 41 | -------------------------------------------------------------------------------- /AxiStream/RunAllTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi Stream tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | # Run AxiStream Tests 42 | TestSuite AxiStream 43 | library osvvm_TbAxiStream 44 | 45 | if {$::osvvm::ToolNameVersion ne "XSIM-2023.2"} { 46 | include testbench 47 | include TestCases 48 | } else { 49 | include testbench_xilinx 50 | } -------------------------------------------------------------------------------- /AxiStream/RunAllTestsVti.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTestsVti.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi Stream tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | TestSuite AxiStream_VTI 42 | library osvvm_TbAxiStreamVti 43 | 44 | include ./testbenchVti 45 | include ./TestCases 46 | -------------------------------------------------------------------------------- /AxiStream/RunDemoTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi Stream tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | # Run AxiStream Tests 42 | TestSuite AxiStream 43 | library osvvm_TbAxiStream 44 | 45 | if {$::osvvm::ToolNameVersion ne "XSIM-2023.2"} { 46 | include testbench 47 | include TestCases/build_demo.pro 48 | } else { 49 | include testbench_xilinx/build_demo.pro 50 | } 51 | 52 | -------------------------------------------------------------------------------- /AxiStream/RunDemoTestsVti.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run all Axi Stream tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | # Run AxiStream Tests 42 | TestSuite AxiStream_VTI 43 | library osvvm_TbAxiStreamVti 44 | 45 | include ./testbenchVti 46 | 47 | RunTest ./TestCases/TbStream_SendGetDemo1.vhd 48 | 49 | # RunTest ./TestCases/TbStream_SendCheckBurstByte1.vhd 50 | # RunTest ./TestCases/TbStream_SendGetBurstByte1.vhd 51 | 52 | # RunTest ./TestCases/TbStream_SendGetPacketBurst1.vhd 53 | 54 | # RunTest ./TestCases/TbStream_WaitForGet1.vhd 55 | # RunTest ./TestCases/TbStream_WaitForGetAsync1.vhd 56 | 57 | # RunTest ./TestCases/TbStream_SendCheckBurstPattern1.vhd 58 | # RunTest ./TestCases/TbStream_SendCheckBurstPattern2.vhd 59 | # RunTest ./TestCases/TbStream_SendCheckBurstBytePattern1.vhd 60 | # RunTest ./TestCases/TbStream_SendCheckBurstAsyncPattern2.vhd 61 | # RunTest ./TestCases/TbStream_SendCheckBurstAsyncPattern1.vhd 62 | # RunTest ./TestCases/TbStream_SendCheckBurstByteAsyncPattern1.vhd 63 | # 64 | # RunTest ./TestCases/TbStream_AxiSendCheckBurstPattern1.vhd 65 | # RunTest ./TestCases/TbStream_AxiSendCheckBurstPattern2.vhd 66 | # RunTest ./TestCases/TbStream_AxiSendCheckBurstAsyncPattern1.vhd 67 | # RunTest ./TestCases/TbStream_AxiSendCheckBurstAsyncPattern2.vhd 68 | -------------------------------------------------------------------------------- /AxiStream/TestCases/OsvvmTestCommonPkg.pro: -------------------------------------------------------------------------------- 1 | # File Name: OsvvmTestCommonPkg.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Compile OsvvmTestCommonPkg.vhd 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 02/2025 2025.02 Initial 21 | # 22 | # 23 | # This file is part of OSVVM. 24 | # 25 | # Copyright (c) 2025 by SynthWorks Design Inc. 26 | # 27 | # Licensed under the Apache License, Version 2.0 (the "License"); 28 | # you may not use this file except in compliance with the License. 29 | # You may obtain a copy of the License at 30 | # 31 | # https://www.apache.org/licenses/LICENSE-2.0 32 | # 33 | # Unless required by applicable law or agreed to in writing, software 34 | # distributed under the License is distributed on an "AS IS" BASIS, 35 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 36 | # See the License for the specific language governing permissions and 37 | # limitations under the License. 38 | # 39 | 40 | analyze ../TestCases/OsvvmTestCommonPkg.vhd 41 | 42 | # if {$::osvvm::Support2019FilePath} { 43 | # analyze ../TestCases/OsvvmTestCommonPkg.vhd 44 | # } else { 45 | # # Need for NVC. NVC has implemented implemented FILE_PATH, however its implementation is incorrect 46 | # analyze ../TestCases/deprecated/OsvvmTestCommonPkg_NoFilePath.vhd 47 | # } 48 | -------------------------------------------------------------------------------- /AxiStream/TestCases/OsvvmTestCommonPkg.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: OsvvmTestCommonPkg.vhd 3 | -- Design Unit Name: Architecture of TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Locate the directory for the Validated Results 13 | -- Alternately set CHECK_TRANSCRIPT to FALSE and Validated Results is not necessary 14 | -- 15 | -- 16 | -- Developed by: 17 | -- SynthWorks Design Inc. 18 | -- VHDL Training Classes 19 | -- http://www.SynthWorks.com 20 | -- 21 | -- Revision History: 22 | -- Date Version Description 23 | -- 02/2025 2025.02 Static paths break. Using VHDL-2019 FILE_PATH 24 | -- 10/2020 2020.10 Initial revision 25 | -- 26 | -- 27 | -- This file is part of OSVVM. 28 | -- 29 | -- Copyright (c) 2020 by SynthWorks Design Inc. 30 | -- 31 | -- Licensed under the Apache License, Version 2.0 (the "License"); 32 | -- you may not use this file except in compliance with the License. 33 | -- You may obtain a copy of the License at 34 | -- 35 | -- https://www.apache.org/licenses/LICENSE-2.0 36 | -- 37 | -- Unless required by applicable law or agreed to in writing, software 38 | -- distributed under the License is distributed on an "AS IS" BASIS, 39 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | -- See the License for the specific language governing permissions and 41 | -- limitations under the License. 42 | -- 43 | 44 | library OSVVM ; 45 | context OSVVM.OsvvmContext ; 46 | -- use std.env.all ; -- see osvvm/FileLinePathPkg.vhd 47 | 48 | package OsvvmTestCommonPkg is 49 | constant RESULTS_DIR : string := "" ; 50 | constant PATH_TO_OsvvmTestCommonPkg : string := FILE_PATH ; 51 | constant AXISTREAM_VALIDATED_RESULTS_DIR : string := PATH_TO_OsvvmTestCommonPkg & "/../ValidatedResults" ; 52 | -- constant AXISTREAM_VALIDATED_RESULTS_DIR : string := std.env.FILE_PATH & "/../ValidatedResults" ; 53 | constant CHECK_TRANSCRIPT : boolean := PATH_TO_OsvvmTestCommonPkg'length > 0 ; 54 | end package OsvvmTestCommonPkg ; 55 | -------------------------------------------------------------------------------- /AxiStream/TestCases/TbStream_MultipleDriversReceiver1.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbStream_MultipleDriversReceiver1.vhd 3 | -- Design Unit Name: Architecture of TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Validates Multiple Driver detection works 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 02/2021 2021.02 Initial revision 23 | -- 24 | -- 25 | -- This file is part of OSVVM. 26 | -- 27 | -- Copyright (c) 2021 by SynthWorks Design Inc. 28 | -- 29 | -- Licensed under the Apache License, Version 2.0 (the "License"); 30 | -- you may not use this file except in compliance with the License. 31 | -- You may obtain a copy of the License at 32 | -- 33 | -- https://www.apache.org/licenses/LICENSE-2.0 34 | -- 35 | -- Unless required by applicable law or agreed to in writing, software 36 | -- distributed under the License is distributed on an "AS IS" BASIS, 37 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | -- See the License for the specific language governing permissions and 39 | -- limitations under the License. 40 | -- 41 | architecture MultipleDriversReceiver1 of TestCtrl is 42 | 43 | signal TestDone : integer_barrier := 1 ; 44 | 45 | begin 46 | 47 | ------------------------------------------------------------ 48 | -- ControlProc 49 | -- Set up AlertLog and wait for end of test 50 | ------------------------------------------------------------ 51 | ControlProc : process 52 | begin 53 | -- Initialization of test 54 | SetTestName("TbStream_MultipleDriversReceiver1") ; 55 | SetLogEnable(PASSED, TRUE) ; -- Enable PASSED logs 56 | SetLogEnable(INFO, TRUE) ; -- Enable INFO logs 57 | SetAlertStopCount(FAILURE, 12) ; -- Allow 2 FAILURE Alerts 58 | 59 | -- Wait for testbench initialization 60 | wait for 0 ns ; wait for 0 ns ; 61 | TranscriptOpen ; 62 | SetTranscriptMirror(TRUE) ; 63 | 64 | -- Wait for Design Reset 65 | wait until nReset = '1' ; 66 | ClearAlerts ; 67 | 68 | -- Wait for test to finish 69 | WaitForBarrier(TestDone, 35 ms) ; 70 | AlertIf(now >= 35 ms, "Test finished due to timeout") ; 71 | -- AlertIf(GetAffirmCount < 1, "Test is not Self-Checking"); 72 | 73 | AffirmIf(GetAlertCount = AlertCountType'(FAILURE => 1, ERROR => 0, WARNING => 0), "Expecting: (FAILURE => 1, ERROR => 0, WARNING => 0)") ; 74 | TranscriptClose ; 75 | if CHECK_TRANSCRIPT then 76 | AffirmIfTranscriptsMatch(AXISTREAM_VALIDATED_RESULTS_DIR) ; 77 | end if ; 78 | 79 | 80 | 81 | EndOfTestReports(ExternalErrors => (FAILURE => -1, ERROR => 0, WARNING => 0)) ; 82 | std.env.stop ; 83 | wait ; 84 | end process ControlProc ; 85 | 86 | 87 | ------------------------------------------------------------ 88 | -- TransmitterProc 89 | -- Generate transactions for Transmitter 90 | ------------------------------------------------------------ 91 | TransmitterProc : process 92 | begin 93 | wait until nReset = '1' ; 94 | WaitForClock(StreamTxRec, 2) ; 95 | WaitForClock(StreamTxRec, 2) ; 96 | WaitForClock(StreamRxRec, 2) ; 97 | 98 | WaitForBarrier(TestDone) ; 99 | wait ; 100 | end process TransmitterProc ; 101 | 102 | 103 | ------------------------------------------------------------ 104 | -- ReceiverProc 105 | -- Generate transactions for Receiver 106 | ------------------------------------------------------------ 107 | ReceiverProc : process 108 | begin 109 | wait until nReset = '1' ; 110 | WaitForClock(StreamRxRec, 2) ; 111 | WaitForClock(StreamRxRec, 3) ; 112 | 113 | WaitForBarrier(TestDone) ; 114 | wait ; 115 | end process ReceiverProc ; 116 | 117 | end MultipleDriversReceiver1 ; 118 | 119 | Configuration TbStream_MultipleDriversReceiver1 of TbStream is 120 | for TestHarness 121 | for TestCtrl_1 : TestCtrl 122 | use entity work.TestCtrl(MultipleDriversReceiver1) ; 123 | end for ; 124 | end for ; 125 | end TbStream_MultipleDriversReceiver1 ; -------------------------------------------------------------------------------- /AxiStream/TestCases/TbStream_MultipleDriversTransmitter1.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbStream_MultipleDriversTransmitter1.vhd 3 | -- Design Unit Name: Architecture of TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Validates Multiple Driver detection works 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 02/2021 2021.02 Initial revision 23 | -- 24 | -- 25 | -- This file is part of OSVVM. 26 | -- 27 | -- Copyright (c) 2021 by SynthWorks Design Inc. 28 | -- 29 | -- Licensed under the Apache License, Version 2.0 (the "License"); 30 | -- you may not use this file except in compliance with the License. 31 | -- You may obtain a copy of the License at 32 | -- 33 | -- https://www.apache.org/licenses/LICENSE-2.0 34 | -- 35 | -- Unless required by applicable law or agreed to in writing, software 36 | -- distributed under the License is distributed on an "AS IS" BASIS, 37 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | -- See the License for the specific language governing permissions and 39 | -- limitations under the License. 40 | -- 41 | architecture MultipleDriversTransmitter1 of TestCtrl is 42 | 43 | signal TestDone : integer_barrier := 1 ; 44 | 45 | begin 46 | 47 | ------------------------------------------------------------ 48 | -- ControlProc 49 | -- Set up AlertLog and wait for end of test 50 | ------------------------------------------------------------ 51 | ControlProc : process 52 | begin 53 | -- Initialization of test 54 | SetTestName("TbStream_MultipleDriversTransmitter1") ; 55 | SetLogEnable(PASSED, TRUE) ; -- Enable PASSED logs 56 | SetLogEnable(INFO, TRUE) ; -- Enable INFO logs 57 | SetAlertStopCount(FAILURE, 12) ; -- Allow 2 FAILURE Alerts 58 | 59 | -- Wait for testbench initialization 60 | wait for 0 ns ; wait for 0 ns ; 61 | TranscriptOpen ; 62 | SetTranscriptMirror(TRUE) ; 63 | 64 | -- Wait for Design Reset 65 | wait until nReset = '1' ; 66 | ClearAlerts ; 67 | 68 | -- Wait for test to finish 69 | WaitForBarrier(TestDone, 35 ms) ; 70 | AlertIf(now >= 35 ms, "Test finished due to timeout") ; 71 | -- AlertIf(GetAffirmCount < 1, "Test is not Self-Checking"); 72 | 73 | AffirmIf(GetAlertCount = AlertCountType'(FAILURE => 1, ERROR => 0, WARNING => 0), "Expecting: (FAILURE => 1, ERROR => 0, WARNING => 0)") ; 74 | TranscriptClose ; 75 | if CHECK_TRANSCRIPT then 76 | AffirmIfTranscriptsMatch(AXISTREAM_VALIDATED_RESULTS_DIR) ; 77 | end if ; 78 | 79 | EndOfTestReports(ExternalErrors => (FAILURE => -1, ERROR => 0, WARNING => 0)) ; 80 | std.env.stop ; 81 | wait ; 82 | end process ControlProc ; 83 | 84 | 85 | ------------------------------------------------------------ 86 | -- TransmitterProc 87 | -- Generate transactions for Transmitter 88 | ------------------------------------------------------------ 89 | TransmitterProc : process 90 | begin 91 | wait until nReset = '1' ; 92 | WaitForClock(StreamTxRec, 2) ; 93 | WaitForClock(StreamTxRec, 3) ; 94 | 95 | WaitForBarrier(TestDone) ; 96 | wait ; 97 | end process TransmitterProc ; 98 | 99 | 100 | ------------------------------------------------------------ 101 | -- ReceiverProc 102 | -- Generate transactions for Receiver 103 | ------------------------------------------------------------ 104 | ReceiverProc : process 105 | begin 106 | wait until nReset = '1' ; 107 | WaitForClock(StreamRxRec, 2) ; 108 | WaitForClock(StreamRxRec, 2) ; 109 | WaitForClock(StreamTxRec, 2) ; 110 | 111 | WaitForBarrier(TestDone) ; 112 | wait ; 113 | end process ReceiverProc ; 114 | 115 | end MultipleDriversTransmitter1 ; 116 | 117 | Configuration TbStream_MultipleDriversTransmitter1 of TbStream is 118 | for TestHarness 119 | for TestCtrl_1 : TestCtrl 120 | use entity work.TestCtrl(MultipleDriversTransmitter1) ; 121 | end for ; 122 | end for ; 123 | end TbStream_MultipleDriversTransmitter1 ; -------------------------------------------------------------------------------- /AxiStream/TestCases/TbStream_WaitForGet2.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbStream_WaitForGet2.vhd 3 | -- Design Unit Name: Architecture of TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Validates RECEIVE_READY_WAIT_FOR_GET with 13 | -- word and burst receive transactions 14 | -- 15 | -- 16 | -- Developed by: 17 | -- SynthWorks Design Inc. 18 | -- VHDL Training Classes 19 | -- http://www.SynthWorks.com 20 | -- 21 | -- Revision History: 22 | -- Date Version Description 23 | -- 01/2022 2022.01 Initial revision 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2022 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | architecture WaitForGet2 of TestCtrl is 43 | 44 | signal Sync : integer_barrier := 1 ; 45 | 46 | begin 47 | 48 | ------------------------------------------------------------ 49 | -- ControlProc 50 | -- Set up AlertLog and wait for end of test 51 | ------------------------------------------------------------ 52 | ControlProc : process 53 | begin 54 | -- Initialization of test 55 | SetTestName("TbStream_WaitForGet2") ; 56 | SetLogEnable(PASSED, TRUE) ; -- Enable PASSED logs 57 | SetLogEnable(INFO, TRUE) ; -- Enable INFO logs 58 | 59 | -- Wait for simulation elaboration/initialization 60 | wait for 0 ns ; wait for 0 ns ; 61 | TranscriptOpen ; 62 | SetTranscriptMirror(TRUE) ; 63 | 64 | -- Wait for Design Reset 65 | wait until nReset = '1' ; 66 | ClearAlerts ; 67 | 68 | -- Wait for test to finish 69 | WaitForBarrier(TestDone, 35 ms) ; 70 | AlertIf(now >= 35 ms, "Test finished due to timeout") ; 71 | AlertIf(GetAffirmCount < 1, "Test is not Self-Checking"); 72 | 73 | TranscriptClose ; 74 | if CHECK_TRANSCRIPT then 75 | -- AffirmIfTranscriptsMatch(AXISTREAM_VALIDATED_RESULTS_DIR) ; 76 | end if ; 77 | 78 | EndOfTestReports(ExternalErrors => (0, 0, 0)) ; 79 | std.env.stop ; 80 | wait ; 81 | end process ControlProc ; 82 | 83 | 84 | ------------------------------------------------------------ 85 | -- AxiTransmitterProc 86 | -- Generate transactions for AxiTransmitter 87 | ------------------------------------------------------------ 88 | TransmitterProc : process 89 | variable CoverID : CoverageIdType ; 90 | begin 91 | 92 | WaitForClock(StreamTxRec, 2) ; 93 | 94 | -- Send and Get 95 | BlankLine(2) ; 96 | log("Send and Get: Transmit 4 words") ; 97 | for I in 0 to 3 loop 98 | Send( StreamTxRec, X"0000_1000" + I ) ; 99 | end loop ; 100 | 101 | -- Wait for outputs to propagate and signal TestDone 102 | WaitForClock(StreamTxRec, 2) ; 103 | WaitForBarrier(TestDone) ; 104 | wait ; 105 | end process TransmitterProc ; 106 | 107 | 108 | ------------------------------------------------------------ 109 | -- AxiReceiverProc 110 | -- Generate transactions for AxiReceiver 111 | ------------------------------------------------------------ 112 | ReceiverProc : process 113 | variable RxData : std_logic_vector(DATA_WIDTH-1 downto 0) ; 114 | variable NumWords : integer ; 115 | variable GetStartTime : time ; 116 | begin 117 | WaitForClock(StreamRxRec, 6) ; 118 | SetAxiStreamOptions(StreamRxRec, RECEIVE_READY_WAIT_FOR_GET, TRUE) ; 119 | 120 | WaitForBarrier(VcInit) ; 121 | 122 | for I in 0 to 3 loop 123 | Check(StreamRxRec, X"0000_1000" + I) ; 124 | WaitForClock(StreamRxRec, 2) ; 125 | end loop ; 126 | 127 | -- Wait for outputs to propagate and signal TestDone 128 | WaitForClock(StreamRxRec, 2) ; 129 | WaitForBarrier(TestDone) ; 130 | wait ; 131 | end process ReceiverProc ; 132 | 133 | end WaitForGet2 ; 134 | 135 | Configuration TbStream_WaitForGet2 of TbStream is 136 | for TestHarness 137 | for TestCtrl_1 : TestCtrl 138 | use entity work.TestCtrl(WaitForGet2) ; 139 | end for ; 140 | end for ; 141 | end TbStream_WaitForGet2 ; -------------------------------------------------------------------------------- /AxiStream/TestCases/TestCases_NoBurst.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 5/2021 2021.05 Start of Refactoring TestCases 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 1/2019 2019.01 Compile Script for OSVVM 23 | # 24 | # 25 | # This file is part of OSVVM. 26 | # 27 | # Copyright (c) 2019 - 2021 by SynthWorks Design Inc. 28 | # 29 | # Licensed under the Apache License, Version 2.0 (the "License"); 30 | # you may not use this file except in compliance with the License. 31 | # You may obtain a copy of the License at 32 | # 33 | # https://www.apache.org/licenses/LICENSE-2.0 34 | # 35 | # Unless required by applicable law or agreed to in writing, software 36 | # distributed under the License is distributed on an "AS IS" BASIS, 37 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | # See the License for the specific language governing permissions and 39 | # limitations under the License. 40 | # 41 | 42 | ## 43 | ## run in conjunction with either 44 | ## Testbench/Testbench.pro or TestbenchVTI/TestbenchVTI.pro 45 | ## Continuing with library set previously by the above 46 | ## 47 | 48 | ## ============================================= 49 | ## MIT Record Checks Single Transfer Tests - only test once for all 50 | RunTest TbStream_MultipleDriversTransmitter1.vhd 51 | RunTest TbStream_MultipleDriversReceiver1.vhd 52 | 53 | 54 | ## ============================================= 55 | ## MIT Checks that apply to all streaming models 56 | ## MIT Blocking, Single Transfers 57 | RunTest TbStream_SendGet1.vhd 58 | RunTest TbStream_ByteHandling1.vhd 59 | 60 | ## MIT Asynchronous, Single Transfers 61 | RunTest TbStream_SendGetAsync1.vhd 62 | RunTest TbStream_ByteHandlingAsync1.vhd 63 | 64 | 65 | # ## MIT Blocking Burst Transfers 66 | # RunTest TbStream_SendGetBurst1.vhd 67 | # # RunTest TbStream_SendGetBurstByte1.vhd 68 | # # RunTest TbStream_ByteHandlingBurst1.vhd 69 | # # RunTest TbStream_ByteHandlingBurstByte1.vhd 70 | # 71 | # ## MIT Blocking Burst that use BurstFifo also as scoreboard 72 | # RunTest TbStream_SendCheckBurst1.vhd 73 | # # RunTest TbStream_SendCheckBurstByte1.vhd 74 | # 75 | # ## MIT Asynchronous Burst Transfers 76 | # RunTest TbStream_SendGetBurstAsync1.vhd 77 | # # RunTest TbStream_SendGetBurstByteAsync1.vhd 78 | # # RunTest TbStream_ByteHandlingBurstAsync1.vhd 79 | # # RunTest TbStream_ByteHandlingBurstByteAsync1.vhd 80 | # 81 | # ## MIT Asynchronous Burst that use BurstFifo also as scoreboard 82 | # RunTest TbStream_SendCheckBurstAsync1.vhd 83 | # # RunTest TbStream_SendCheckBurstByteAsync1.vhd 84 | # 85 | # ## ============================================= 86 | # ## MIT Record Checks Burst Transfer Tests - only test once for all 87 | # RunTest TbStream_ReleaseAcquireTransmitter1.vhd 88 | # # RunTest TbStream_ReleaseAcquireReceiver1.vhd 89 | # 90 | 91 | ## ============================================= 92 | ## AxiStream Specific Tests 93 | ## AxiStream Blocking, Single Transfers 94 | RunTest TbStream_AxiSendGet2.vhd 95 | RunTest TbStream_AxiSetOptions1.vhd 96 | RunTest TbStream_AxiTxValidDelay1.vhd 97 | RunTest TbStream_AxiTiming1.vhd 98 | RunTest TbStream_AxiTiming2.vhd 99 | RunTest TbStream_AxiSetOptions2.vhd 100 | 101 | ## AxiStream Asynchronous, Single Transfers 102 | RunTest TbStream_AxiSendGetAsync2.vhd 103 | RunTest TbStream_AxiSetOptionsAsync1.vhd 104 | RunTest TbStream_AxiSetOptionsAsync2.vhd 105 | 106 | 107 | # ## AxiStream Blocking Burst Transfers 108 | # RunTest TbStream_AxiSendGetBurst2.vhd 109 | # # RunTest TbStream_AxiLastParam1.vhd 110 | # # RunTest TbStream_AxiLastOption1.vhd 111 | # # RunTest TbStream_AxiSetOptionsBurst1.vhd 112 | # # RunTest TbStream_AxiTxValidDelayBurst1.vhd 113 | # # RunTest TbStream_AxiTimingBurst2.vhd 114 | # # RunTest TbStream_AxiSetOptionsBurst2.vhd 115 | # # RunTest TbStream_AxiSetOptionsBurstByte2.vhd 116 | # # RunTest TbStream_AxiSetOptionsBurst3.vhd 117 | # # RunTest TbStream_AxiBurstNoLast1.vhd 118 | # 119 | # RunTest TbStream_AxiSetOptionsBurstCheck3.vhd 120 | # 121 | 122 | # ## AxiStream Asynchronous Burst Transfers 123 | # RunTest TbStream_AxiSendGetBurstAsync2.vhd 124 | # # RunTest TbStream_AxiLastParamAsync1.vhd 125 | # # RunTest TbStream_AxiLastOptionAsync1.vhd 126 | # # RunTest TbStream_AxiSetOptionsBurstAsync1.vhd 127 | # # RunTest TbStream_AxiSetOptionsBurstAsync2.vhd 128 | # # RunTest TbStream_AxiSetOptionsBurstByteAsync2.vhd 129 | # # RunTest TbStream_AxiSetOptionsBurstAsync3.vhd 130 | # # RunTest TbStream_AxiBurstAsyncNoLast1.vhd 131 | # 132 | # RunTest TbStream_AxiSetOptionsBurstCheckAsync3.vhd 133 | # -------------------------------------------------------------------------------- /AxiStream/TestCases/build_demo.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2022 2022.01 Added Tests 21 | # 9/2021 2021.09 RunTest replacing analyze + simulate 22 | # 5/2021 2021.05 Start of Refactoring TestCases 23 | # 1/2020 2020.01 Updated Licenses to Apache 24 | # 1/2019 2019.01 Compile Script for OSVVM 25 | # 26 | # 27 | # This file is part of OSVVM. 28 | # 29 | # Copyright (c) 2019 - 2022 by SynthWorks Design Inc. 30 | # 31 | # Licensed under the Apache License, Version 2.0 (the "License"); 32 | # you may not use this file except in compliance with the License. 33 | # You may obtain a copy of the License at 34 | # 35 | # https://www.apache.org/licenses/LICENSE-2.0 36 | # 37 | # Unless required by applicable law or agreed to in writing, software 38 | # distributed under the License is distributed on an "AS IS" BASIS, 39 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | # See the License for the specific language governing permissions and 41 | # limitations under the License. 42 | # 43 | 44 | ## 45 | ## Runs in conjunction with either 46 | ## Testbench/Testbench.pro or TestbenchVTI/TestbenchVTI.pro 47 | ## Continuing with library set previously by the above 48 | ## 49 | 50 | ## ============================================= 51 | ## Run Demo 52 | RunTest TbStream_SendGetDemo1.vhd ; # Demo of Send, Get, and Check of words and bursts 53 | RunTest TbStream_SendGetPacketBurst1.vhd ; # Prototype of burst packetization with FIFO in Byte and then Word mode 54 | RunTest TbStream_SendGetRandom1.vhd ; # Demo of Send, Get, and Check of words and bursts 55 | RunTest TbStream_SendGetRandom2.vhd ; # Demo of Send, Get, and Check of packets with Valid/Ready randomization 56 | -------------------------------------------------------------------------------- /AxiStream/TestCases/deprecated/OsvvmTestCommonPkg_NoFilePath.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: OsvvmTestCommonPkg.vhd 3 | -- Design Unit Name: Architecture of TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Locate the directory for the Validated Results 13 | -- Alternately set CHECK_TRANSCRIPT to FALSE and Validated Results is not necessary 14 | -- 15 | -- 16 | -- Developed by: 17 | -- SynthWorks Design Inc. 18 | -- VHDL Training Classes 19 | -- http://www.SynthWorks.com 20 | -- 21 | -- Revision History: 22 | -- Date Version Description 23 | -- 02/2025 2025.02 Static paths break. Using VHDL-2019 FILE_PATH 24 | -- 10/2020 2020.10 Initial revision 25 | -- 26 | -- 27 | -- This file is part of OSVVM. 28 | -- 29 | -- Copyright (c) 2020 by SynthWorks Design Inc. 30 | -- 31 | -- Licensed under the Apache License, Version 2.0 (the "License"); 32 | -- you may not use this file except in compliance with the License. 33 | -- You may obtain a copy of the License at 34 | -- 35 | -- https://www.apache.org/licenses/LICENSE-2.0 36 | -- 37 | -- Unless required by applicable law or agreed to in writing, software 38 | -- distributed under the License is distributed on an "AS IS" BASIS, 39 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | -- See the License for the specific language governing permissions and 41 | -- limitations under the License. 42 | -- 43 | 44 | library OSVVM ; 45 | context OSVVM.OsvvmContext ; 46 | package OsvvmTestCommonPkg is 47 | constant RESULTS_DIR : string := "" ; 48 | constant AXISTREAM_VALIDATED_RESULTS_DIR : string := "" ; 49 | constant CHECK_TRANSCRIPT : boolean := FALSE ; 50 | end package OsvvmTestCommonPkg ; 51 | -------------------------------------------------------------------------------- /AxiStream/ValidatedResults/TbStream_AxiTiming1.log: -------------------------------------------------------------------------------- 1 | %% 110 ns Log ALWAYS in Default, Transmit Ready TimeOut test. Trigger Ready TimeOut twice. 2 | %% 130 ns Log INFO in transmitter_1, Axi Stream Send. TData: 00010010 TStrb: 1111 TKeep: 1111 TID: 00 TDest: 0 TUser: 0 TLast: 0 Operation# 1 3 | %% 140 ns Log INFO in receiver_1, Word Receive. Operation# 1 Data: 00010010 TID: 00 TDest: 0 TUser: 0 TLast: 0 4 | %% 140 ns Log PASSED in Default, Get Data: Received : 00010010 5 | 6 | 7 | %% 240 ns Log INFO in transmitter_1, Axi Stream Send. TData: BAD00010 TStrb: 1111 TKeep: 1111 TID: 00 TDest: 0 TUser: 0 TLast: 0 Operation# 2 8 | %% 290 ns Alert FAILURE in transmitter_1: No response, AXI Stream Send Operation # 2. Ready: 0 Expected: 1 9 | %% 300 ns Alert FAILURE in receiver_1, Valid (0) deasserted before Ready asserted (0) 10 | %% 310 ns Log INFO in receiver_1, Word Receive. Operation# 2 Data: 452FFFEF TID: 01 TDest: 1 TUser: F TLast: 0 11 | %% 310 ns Alert ERROR in Default, Get Data: Received : 452FFFEF ?= Expected : BAD00010 12 | 13 | 14 | %% 400 ns Log INFO in transmitter_1, Axi Stream Send. TData: 00020020 TStrb: 1111 TKeep: 1111 TID: 00 TDest: 0 TUser: 0 TLast: 0 Operation# 3 15 | %% 490 ns Log INFO in receiver_1, Word Receive. Operation# 3 Data: 00020020 TID: 00 TDest: 0 TUser: 0 TLast: 0 16 | %% 490 ns Log PASSED in Default, Get Data: Received : 00020020 17 | 18 | 19 | %% 590 ns Log INFO in transmitter_1, Axi Stream Send. TData: BAD00020 TStrb: 1111 TKeep: 1111 TID: 00 TDest: 0 TUser: 0 TLast: 0 Operation# 4 20 | %% 640 ns Alert FAILURE in transmitter_1: No response, AXI Stream Send Operation # 4. Ready: 0 Expected: 1 21 | %% 650 ns Alert FAILURE in receiver_1, Valid (0) deasserted before Ready asserted (0) 22 | %% 660 ns Log INFO in receiver_1, Word Receive. Operation# 4 Data: 452FFFDF TID: 01 TDest: 1 TUser: F TLast: 0 23 | %% 660 ns Alert ERROR in Default, Get Data: Received : 452FFFDF ?= Expected : BAD00020 24 | 25 | 26 | %% 750 ns Log INFO in transmitter_1, Axi Stream Send. TData: 00030030 TStrb: 1111 TKeep: 1111 TID: 00 TDest: 0 TUser: 0 TLast: 0 Operation# 5 27 | %% 840 ns Log INFO in receiver_1, Word Receive. Operation# 5 Data: 00030030 TID: 00 TDest: 0 TUser: 0 TLast: 0 28 | %% 840 ns Log PASSED in Default, Get Data: Received : 00030030 29 | 30 | 31 | -------------------------------------------------------------------------------- /AxiStream/ValidatedResults/TbStream_MultipleDriversReceiver1.log: -------------------------------------------------------------------------------- 1 | %% 140 ns Alert FAILURE in receiver_1, Multiple Drivers on Transaction Record. Transaction # 3 2 | %% 140 ns Log PASSED in Default, Expecting: (FAILURE => 1, ERROR => 0, WARNING => 0) 3 | -------------------------------------------------------------------------------- /AxiStream/ValidatedResults/TbStream_MultipleDriversTransmitter1.log: -------------------------------------------------------------------------------- 1 | %% 140 ns Alert FAILURE in transmitter_1, Multiple Drivers on Transaction Record. Transaction # 3 2 | %% 140 ns Log PASSED in Default, Expecting: (FAILURE => 1, ERROR => 0, WARNING => 0) 3 | -------------------------------------------------------------------------------- /AxiStream/src/AxiStreamContext.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: AxiStreamContext.vhd 3 | -- Design Unit Name: AxiStreamContext 4 | -- Revision: STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- 8 | -- Description 9 | -- Context Declaration for AxiStream packages 10 | -- 11 | -- Developed by/for: 12 | -- SynthWorks Design Inc. 13 | -- VHDL Training Classes 14 | -- 11898 SW 128th Ave. Tigard, Or 97223 15 | -- http://www.SynthWorks.com 16 | -- 17 | -- Revision History: 18 | -- Date Version Description 19 | -- 01/2020 2020.01 Updated license notice 20 | -- 01/2019 2019.01 Initial Revision 21 | -- 22 | -- 23 | -- This file is part of OSVVM. 24 | -- 25 | -- Copyright (c) 2019 - 2021 by SynthWorks Design Inc. 26 | -- 27 | -- Licensed under the Apache License, Version 2.0 (the "License"); 28 | -- you may not use this file except in compliance with the License. 29 | -- You may obtain a copy of the License at 30 | -- 31 | -- https://www.apache.org/licenses/LICENSE-2.0 32 | -- 33 | -- Unless required by applicable law or agreed to in writing, software 34 | -- distributed under the License is distributed on an "AS IS" BASIS, 35 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 36 | -- See the License for the specific language governing permissions and 37 | -- limitations under the License. 38 | -- 39 | 40 | context AxiStreamContext is 41 | library osvvm_common ; 42 | context osvvm_common.OsvvmCommonContext ; 43 | 44 | library osvvm_axi4 ; 45 | use osvvm_axi4.AxiStreamOptionsPkg.all ; 46 | use osvvm_axi4.AxiStreamOptionsArrayPkg.all ; 47 | use osvvm_axi4.Axi4CommonPkg.all ; 48 | use osvvm_axi4.AxiStreamComponentPkg.all ; 49 | end context AxiStreamContext ; 50 | 51 | -------------------------------------------------------------------------------- /AxiStream/src/AxiStreamGenericSignalsPkg.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: AxiStreamGenericSignalsPkg.vhd 3 | -- Design Unit Name: AxiStreamGenericSignalsPkg 4 | -- Revision: STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- 8 | -- Description 9 | -- Context Declaration for OSVVM packages 10 | -- 11 | -- Developed by/for: 12 | -- SynthWorks Design Inc. 13 | -- VHDL Training Classes 14 | -- 11898 SW 128th Ave. Tigard, Or 97223 15 | -- http://www.SynthWorks.com 16 | -- 17 | -- Revision History: 18 | -- Date Version Description 19 | -- 01/2010 2019.01 Initial Revision 20 | -- 01/2020 2020.01 Updated license notice 21 | -- 22 | -- 23 | -- This file is part of OSVVM. 24 | -- 25 | -- Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 26 | -- 27 | -- Licensed under the Apache License, Version 2.0 (the "License"); 28 | -- you may not use this file except in compliance with the License. 29 | -- You may obtain a copy of the License at 30 | -- 31 | -- https://www.apache.org/licenses/LICENSE-2.0 32 | -- 33 | -- Unless required by applicable law or agreed to in writing, software 34 | -- distributed under the License is distributed on an "AS IS" BASIS, 35 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 36 | -- See the License for the specific language governing permissions and 37 | -- limitations under the License. 38 | -- 39 | 40 | library ieee ; 41 | use ieee.std_logic_1164.all ; 42 | use ieee.numeric_std.all ; 43 | 44 | library osvvm ; 45 | context osvvm.OsvvmContext ; 46 | 47 | library osvvm_common ; 48 | context osvvm_common.OsvvmCommonContext ; 49 | 50 | library osvvm_axi4 ; 51 | context osvvm_axi4.AxiStreamContext ; 52 | 53 | package AxiStreamGenericSignalsPkg is 54 | generic ( 55 | constant AXI_DATA_WIDTH : integer := 32 ; 56 | constant AXI_BYTE_WIDTH : integer := AXI_DATA_WIDTH/8 ; 57 | constant TID_MAX_WIDTH : integer := 8 ; 58 | constant TDEST_MAX_WIDTH : integer := 4 ; 59 | constant TUSER_MAX_WIDTH : integer := 1 * AXI_BYTE_WIDTH 60 | ) ; 61 | 62 | constant INIT_ID : std_logic_vector(TID_MAX_WIDTH-1 downto 0) := (others => '0') ; 63 | constant INIT_DEST : std_logic_vector(TDEST_MAX_WIDTH-1 downto 0) := (others => '0') ; 64 | constant INIT_USER : std_logic_vector(TUSER_MAX_WIDTH-1 downto 0) := (others => '0') ; 65 | 66 | constant AXI_PARAM_WIDTH : integer := TID_MAX_WIDTH + TDEST_MAX_WIDTH + TUSER_MAX_WIDTH + 1 ; 67 | 68 | --! Issue: with multiple interfaces, need to use a selected name with package 69 | --! PackageInstanceName.TValid 70 | --! Interesting in that it works just like a record - except you cannot collectively refer to them 71 | signal TValid : std_logic ; 72 | signal TReady : std_logic ; 73 | signal TID : std_logic_vector(TID_MAX_WIDTH-1 downto 0) ; 74 | signal TDest : std_logic_vector(TDEST_MAX_WIDTH-1 downto 0) ; 75 | signal TUser : std_logic_vector(TUSER_MAX_WIDTH-1 downto 0) ; 76 | signal TData : std_logic_vector(AXI_DATA_WIDTH-1 downto 0) ; 77 | signal TStrb : std_logic_vector(AXI_BYTE_WIDTH-1 downto 0) ; 78 | signal TKeep : std_logic_vector(AXI_BYTE_WIDTH-1 downto 0) ; 79 | signal TLast : std_logic ; 80 | 81 | signal TransRec : StreamRecType( 82 | DataToModel (AXI_DATA_WIDTH-1 downto 0), 83 | DataFromModel (AXI_DATA_WIDTH-1 downto 0), 84 | ParamToModel (AXI_PARAM_WIDTH-1 downto 0), 85 | ParamFromModel(AXI_PARAM_WIDTH-1 downto 0) 86 | ) ; 87 | end package AxiStreamGenericSignalsPkg ; 88 | 89 | -------------------------------------------------------------------------------- /AxiStream/src/AxiStreamSignalsPkg_32.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: AxiStreamGenericSignalsPkg.vhd 3 | -- Design Unit Name: AxiStreamGenericSignalsPkg 4 | -- Revision: STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- 8 | -- Description 9 | -- Context Declaration for OSVVM packages 10 | -- 11 | -- Developed by/for: 12 | -- SynthWorks Design Inc. 13 | -- VHDL Training Classes 14 | -- 11898 SW 128th Ave. Tigard, Or 97223 15 | -- http://www.SynthWorks.com 16 | -- 17 | -- Revision History: 18 | -- Date Version Description 19 | -- 01/2010 2019.01 Initial Revision 20 | -- 01/2020 2020.01 Updated license notice 21 | -- 22 | -- 23 | -- This file is part of OSVVM. 24 | -- 25 | -- Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 26 | -- 27 | -- Licensed under the Apache License, Version 2.0 (the "License"); 28 | -- you may not use this file except in compliance with the License. 29 | -- You may obtain a copy of the License at 30 | -- 31 | -- https://www.apache.org/licenses/LICENSE-2.0 32 | -- 33 | -- Unless required by applicable law or agreed to in writing, software 34 | -- distributed under the License is distributed on an "AS IS" BASIS, 35 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 36 | -- See the License for the specific language governing permissions and 37 | -- limitations under the License. 38 | -- 39 | 40 | library ieee ; 41 | use ieee.std_logic_1164.all ; 42 | use ieee.numeric_std.all ; 43 | 44 | library osvvm ; 45 | context osvvm.OsvvmContext ; 46 | 47 | library osvvm_axi4 ; 48 | context osvvm_axi4.AxiStreamContext ; 49 | 50 | package AxiStreamSignalsPkg_32 is new work.AxiStreamGenericSignalsPkg 51 | generic map ( 52 | AXI_DATA_WIDTH => 32, 53 | AXI_BYTE_WIDTH => 32/8, 54 | TID_MAX_WIDTH => 8, 55 | TDEST_MAX_WIDTH => 4, 56 | TUSER_MAX_WIDTH => 1 * 32/8 57 | ) ; 58 | -------------------------------------------------------------------------------- /AxiStream/src/AxiStreamTbPkg.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: AxiStreamTbPkg.vhd 3 | -- Design Unit Name: AxiStreamTbPkg 4 | -- OSVVM Release: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Defines types, constants, and subprograms used by 13 | -- OSVVM Axi4 Transaction Based Models (aka: TBM, TLM, VVC) 14 | -- 15 | -- 16 | -- Developed by: 17 | -- SynthWorks Design Inc. 18 | -- VHDL Training Classes 19 | -- http://www.SynthWorks.com 20 | -- 21 | -- Revision History: 22 | -- Date Version Description 23 | -- 2018.05 2018.05 Initial revision released as AxiStreamTransactionPkg 24 | -- 01/2020 2020.01 Updated license notice 25 | -- 26 | -- 27 | -- This file is part of OSVVM. 28 | -- 29 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 30 | -- 31 | -- Licensed under the Apache License, Version 2.0 (the "License"); 32 | -- you may not use this file except in compliance with the License. 33 | -- You may obtain a copy of the License at 34 | -- 35 | -- https://www.apache.org/licenses/LICENSE-2.0 36 | -- 37 | -- Unless required by applicable law or agreed to in writing, software 38 | -- distributed under the License is distributed on an "AS IS" BASIS, 39 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | -- See the License for the specific language governing permissions and 41 | -- limitations under the License. 42 | -- 43 | 44 | library ieee ; 45 | use ieee.std_logic_1164.all ; 46 | use ieee.numeric_std.all ; 47 | use ieee.numeric_std_unsigned.all ; 48 | use ieee.math_real.all ; 49 | 50 | use std.textio.all ; 51 | 52 | library OSVVM ; 53 | context OSVVM.OsvvmContext ; 54 | 55 | 56 | package AxiStreamTbPkg is 57 | ------------------------------------------------------------ 58 | function UpdateOptions ( 59 | ------------------------------------------------------------ 60 | Param : std_logic_vector ; 61 | ParamID : std_logic_vector ; 62 | ParamDest : std_logic_vector ; 63 | ParamUser : std_logic_vector ; 64 | ParamLast : integer ; 65 | Count : integer 66 | ) return std_logic_vector ; 67 | 68 | 69 | end AxiStreamTbPkg ; 70 | 71 | package body AxiStreamTbPkg is 72 | 73 | ------------------------------------------------------------ 74 | function UpdateOptions ( 75 | ------------------------------------------------------------ 76 | Param : std_logic_vector ; 77 | ParamID : std_logic_vector ; 78 | ParamDest : std_logic_vector ; 79 | ParamUser : std_logic_vector ; 80 | ParamLast : integer ; 81 | Count : integer 82 | ) return std_logic_vector is 83 | constant PARAM_LEN : integer := Param'length ; 84 | constant ID_LEN : integer := ParamID'length ; 85 | constant DEST_LEN : integer := ParamDest'length ; 86 | constant USER_LEN : integer := ParamUser'length ; 87 | variable ResultParam : std_logic_vector(PARAM_LEN -1 downto 0) ; 88 | 89 | constant ID_RIGHT : integer := DEST_LEN + USER_LEN + 1 ; 90 | constant DEST_RIGHT : integer := USER_LEN + 1 ; 91 | constant USER_RIGHT : integer := 1 ; 92 | alias Last : std_logic is ResultParam(0) ; 93 | begin 94 | ResultParam := Param ; 95 | 96 | if ID_LEN > 0 and ResultParam(ID_RIGHT) = '-' then 97 | ResultParam(PARAM_LEN-1 downto ID_RIGHT) := ParamID ; 98 | end if ; 99 | 100 | if DEST_LEN > 0 and ResultParam(DEST_RIGHT) = '-' then 101 | ResultParam(ID_RIGHT-1 downto DEST_RIGHT) := ParamDest ; 102 | end if ; 103 | 104 | if USER_LEN > 0 and ResultParam(USER_RIGHT) = '-' then 105 | ResultParam(DEST_RIGHT-1 downto USER_RIGHT) := ParamUser ; 106 | end if ; 107 | 108 | -- Calculate Last. 109 | if Last = '-' then -- use defaults 110 | if ParamLast <= 1 then 111 | Last := '1' when ParamLast = 1 else '0' ; 112 | else 113 | -- generate last once every ParamLast cycles 114 | Last := '1' when (Count mod ParamLast) = 0 else '0' ; 115 | end if ; 116 | end if ; 117 | return ResultParam ; 118 | end function UpdateOptions ; 119 | 120 | end AxiStreamTbPkg ; 121 | -------------------------------------------------------------------------------- /AxiStream/src/build.pro: -------------------------------------------------------------------------------- 1 | # File Name: build.pro 2 | # Revision: OSVVM MODELS STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to compile the Axi Stream models 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_axi4 41 | analyze AxiStreamOptionsPkg.vhd 42 | analyze AxiStreamOptionsArrayPkg.vhd 43 | analyze AxiStreamTbPkg.vhd 44 | 45 | if {$::osvvm::ToolNameVersion ne "XSIM-2023.2"} { 46 | analyze AxiStreamTransmitter.vhd 47 | analyze AxiStreamTransmitterVti.vhd 48 | analyze AxiStreamReceiver.vhd 49 | analyze AxiStreamReceiverVti.vhd 50 | } else { 51 | analyze AxiStreamTransmitter_xilinx.vhd 52 | # analyze AxiStreamTransmitterVti_xilinx.vhd 53 | analyze AxiStreamReceiver_xilinx.vhd 54 | # analyze AxiStreamReceiverVti_xilinx.vhd 55 | } 56 | 57 | analyze AxiStreamComponentPkg.vhd 58 | analyze AxiStreamContext.vhd 59 | 60 | if {$::osvvm::ToolSupportsGenericPackages} { 61 | analyze AxiStreamGenericSignalsPkg.vhd 62 | analyze AxiStreamSignalsPkg_32.vhd 63 | } -------------------------------------------------------------------------------- /AxiStream/testbench/AxiStreamDut.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: AxiStreamDut.vhd 3 | -- Design Unit Name: AxiStreamDut 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- DUT pass thru for AxiStream VC testing 13 | -- Used to demonstrate DUT connections 14 | -- 15 | -- 16 | -- Developed by: 17 | -- SynthWorks Design Inc. 18 | -- VHDL Training Classes 19 | -- http://www.SynthWorks.com 20 | -- 21 | -- Revision History: 22 | -- Date Version Description 23 | -- 01/2023 2023.01 Initial 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2023 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | 43 | library ieee ; 44 | use ieee.std_logic_1164.all ; 45 | use ieee.numeric_std.all ; 46 | use ieee.numeric_std_unsigned.all ; 47 | use ieee.math_real.all ; 48 | 49 | library osvvm ; 50 | context osvvm.OsvvmContext ; 51 | 52 | entity AxiStreamDut is 53 | port ( 54 | -- AXI Transmitter Functional Interface 55 | TxTValid : out std_logic ; 56 | TxTReady : in std_logic ; 57 | TxTID : out std_logic_vector ; 58 | TxTDest : out std_logic_vector ; 59 | TxTUser : out std_logic_vector ; 60 | TxTData : out std_logic_vector ; 61 | TxTStrb : out std_logic_vector ; 62 | TxTKeep : out std_logic_vector ; 63 | TxTLast : out std_logic ; 64 | 65 | -- AXI Receiver Functional Interface 66 | RxTValid : in std_logic ; 67 | RxTReady : out std_logic ; 68 | RxTID : in std_logic_vector ; 69 | RxTDest : in std_logic_vector ; 70 | RxTUser : in std_logic_vector ; 71 | RxTData : in std_logic_vector ; 72 | RxTStrb : in std_logic_vector ; 73 | RxTKeep : in std_logic_vector ; 74 | RxTLast : in std_logic 75 | ) ; 76 | end entity AxiStreamDut ; 77 | architecture DUT of AxiStreamDut is 78 | begin 79 | 80 | TxTValid <= RxTValid; 81 | RxTReady <= TxTReady; 82 | TxTID <= RxTID ; 83 | TxTDest <= RxTDest ; 84 | TxTUser <= RxTUser ; 85 | TxTData <= RxTData ; 86 | TxTStrb <= RxTStrb ; 87 | TxTKeep <= RxTKeep ; 88 | TxTLast <= RxTLast ; 89 | 90 | end architecture DUT ; 91 | -------------------------------------------------------------------------------- /AxiStream/testbench/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 05/2018 2018.05 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | library ieee ; 43 | use ieee.std_logic_1164.all ; 44 | use ieee.numeric_std.all ; 45 | use ieee.numeric_std_unsigned.all ; 46 | 47 | library OSVVM ; 48 | context OSVVM.OsvvmContext ; 49 | use osvvm.ScoreboardPkg_slv.all ; 50 | 51 | library osvvm_AXI4 ; 52 | context osvvm_AXI4.AxiStreamContext ; 53 | 54 | use work.OsvvmTestCommonPkg.all ; 55 | 56 | entity TestCtrl is 57 | generic ( 58 | ID_LEN : integer ; 59 | DEST_LEN : integer ; 60 | USER_LEN : integer 61 | ) ; 62 | port ( 63 | -- Global Signal Interface 64 | nReset : In std_logic ; 65 | 66 | -- Transaction Interfaces 67 | StreamTxRec : InOut StreamRecType ; 68 | StreamRxRec : InOut StreamRecType 69 | 70 | ) ; 71 | 72 | -- Derive AXI interface properties from the StreamTxRec 73 | constant DATA_WIDTH : integer := StreamTxRec.DataToModel'length ; 74 | constant DATA_BYTES : integer := DATA_WIDTH/8 ; 75 | 76 | -- Simplifying access to Burst FIFOs using aliases 77 | alias TxBurstFifo : ScoreboardIdType is StreamTxRec.BurstFifo ; 78 | alias RxBurstFifo : ScoreboardIdType is StreamRxRec.BurstFifo ; 79 | end entity TestCtrl ; 80 | -------------------------------------------------------------------------------- /AxiStream/testbench/build.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | library osvvm_TbAxiStream 42 | 43 | include ../TestCases/OsvvmTestCommonPkg.pro 44 | 45 | analyze TestCtrl_e.vhd 46 | analyze AxiStreamDut.vhd 47 | analyze TbStream.vhd 48 | -------------------------------------------------------------------------------- /AxiStream/testbenchVti/TbStream.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TbStream.vhd 3 | -- Design Unit Name: TbStream 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Top level testbench for AxiStreamTransmitter and AxiStreamReceiver 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 07/2024 2024.07 Updated CreateClock 23 | -- 10/2020 2020.10 Updated name to be TbStream.vhd in conjunction with Model Indepenedent Transactions 24 | -- 01/2020 2020.01 Updated license notice 25 | -- 05/2018 2018.05 Initial revision 26 | -- 27 | -- 28 | -- This file is part of OSVVM. 29 | -- 30 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 31 | -- 32 | -- Licensed under the Apache License, Version 2.0 (the "License"); 33 | -- you may not use this file except in compliance with the License. 34 | -- You may obtain a copy of the License at 35 | -- 36 | -- https://www.apache.org/licenses/LICENSE-2.0 37 | -- 38 | -- Unless required by applicable law or agreed to in writing, software 39 | -- distributed under the License is distributed on an "AS IS" BASIS, 40 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | -- See the License for the specific language governing permissions and 42 | -- limitations under the License. 43 | -- 44 | library ieee ; 45 | use ieee.std_logic_1164.all ; 46 | use ieee.numeric_std.all ; 47 | use ieee.numeric_std_unsigned.all ; 48 | 49 | library osvvm ; 50 | context osvvm.OsvvmContext ; 51 | 52 | library osvvm_AXI4 ; 53 | context osvvm_AXI4.AxiStreamContext ; 54 | use osvvm_AXI4.AxiStreamSignalsPkg_32.all ; 55 | 56 | entity TbStream is 57 | end entity TbStream ; 58 | architecture TestHarness of TbStream is 59 | 60 | constant tperiod_Clk : time := 10 ns ; 61 | constant tpd : time := 2 ns ; 62 | 63 | signal Clk : std_logic := '1' ; 64 | signal nReset : std_logic ; 65 | 66 | 67 | component TestCtrl is 68 | generic ( 69 | ID_LEN : integer ; 70 | DEST_LEN : integer ; 71 | USER_LEN : integer 72 | ) ; 73 | port ( 74 | -- Global Signal Interface 75 | nReset : In std_logic 76 | ) ; 77 | end component TestCtrl ; 78 | 79 | 80 | begin 81 | 82 | -- create Clock 83 | Osvvm.ClockResetPkg.CreateClock ( 84 | Clk => Clk, 85 | Period => Tperiod_Clk 86 | ) ; 87 | 88 | -- create nReset 89 | Osvvm.ClockResetPkg.CreateReset ( 90 | Reset => nReset, 91 | ResetActive => '0', 92 | Clk => Clk, 93 | Period => 7 * tperiod_Clk, 94 | tpd => tpd 95 | ) ; 96 | 97 | Transmitter_1 : AxiStreamTransmitterVti 98 | generic map ( 99 | INIT_ID => INIT_ID , 100 | INIT_DEST => INIT_DEST, 101 | INIT_USER => INIT_USER, 102 | INIT_LAST => 0, 103 | 104 | tperiod_Clk => tperiod_Clk, 105 | 106 | tpd_Clk_TValid => tpd, 107 | tpd_Clk_TID => tpd, 108 | tpd_Clk_TDest => tpd, 109 | tpd_Clk_TUser => tpd, 110 | tpd_Clk_TData => tpd, 111 | tpd_Clk_TStrb => tpd, 112 | tpd_Clk_TKeep => tpd, 113 | tpd_Clk_TLast => tpd 114 | ) 115 | port map ( 116 | -- Globals 117 | Clk => Clk, 118 | nReset => nReset, 119 | 120 | -- AXI Stream Interface 121 | TValid => TValid, 122 | TReady => TReady, 123 | TID => TID , 124 | TDest => TDest , 125 | TUser => TUser , 126 | TData => TData , 127 | TStrb => TStrb , 128 | TKeep => TKeep , 129 | TLast => TLast 130 | ) ; 131 | 132 | Receiver_1 : AxiStreamReceiverVti 133 | generic map ( 134 | tperiod_Clk => tperiod_Clk, 135 | INIT_ID => INIT_ID , 136 | INIT_DEST => INIT_DEST, 137 | INIT_USER => INIT_USER, 138 | INIT_LAST => 0, 139 | 140 | tpd_Clk_TReady => tpd 141 | ) 142 | port map ( 143 | -- Globals 144 | Clk => Clk, 145 | nReset => nReset, 146 | 147 | -- AXI Stream Interface 148 | TValid => TValid, 149 | TReady => TReady, 150 | TID => TID , 151 | TDest => TDest , 152 | TUser => TUser , 153 | TData => TData , 154 | TStrb => TStrb , 155 | TKeep => TKeep , 156 | TLast => TLast 157 | ) ; 158 | 159 | 160 | TestCtrl_1 : TestCtrl 161 | generic map ( 162 | ID_LEN => TID'length, 163 | DEST_LEN => TDest'length, 164 | USER_LEN => TUser'length 165 | ) 166 | port map ( 167 | -- Globals 168 | nReset => nReset 169 | ) ; 170 | 171 | end architecture TestHarness ; -------------------------------------------------------------------------------- /AxiStream/testbenchVti/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 05/2018 2018.05 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | library ieee ; 43 | use ieee.std_logic_1164.all ; 44 | use ieee.numeric_std.all ; 45 | use ieee.numeric_std_unsigned.all ; 46 | 47 | library OSVVM ; 48 | context OSVVM.OsvvmContext ; 49 | use osvvm.ScoreboardPkg_slv.all ; 50 | 51 | library osvvm_AXI4 ; 52 | context osvvm_AXI4.AxiStreamContext ; 53 | 54 | use work.OsvvmTestCommonPkg.all ; 55 | 56 | entity TestCtrl is 57 | generic ( 58 | ID_LEN : integer ; 59 | DEST_LEN : integer ; 60 | USER_LEN : integer 61 | ) ; 62 | port ( 63 | -- Global Signal Interface 64 | nReset : In std_logic 65 | ) ; 66 | -- Connect transaction interfaces using external names 67 | alias StreamTxRec is <> ; 68 | alias StreamRxRec is <> ; 69 | 70 | -- Derive AXI interface properties from the StreamTxRec 71 | constant DATA_WIDTH : integer := StreamTxRec.DataToModel'length ; 72 | constant DATA_BYTES : integer := DATA_WIDTH/8 ; 73 | 74 | -- Simplifying access to Burst FIFOs using aliases 75 | alias TxBurstFifo : ScoreboardIdType is StreamTxRec.BurstFifo ; 76 | alias RxBurstFifo : ScoreboardIdType is StreamRxRec.BurstFifo ; 77 | 78 | end entity TestCtrl ; 79 | -------------------------------------------------------------------------------- /AxiStream/testbenchVti/testbenchVti.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | library osvvm_TbAxiStreamVti 42 | 43 | include ../TestCases/OsvvmTestCommonPkg.pro 44 | 45 | analyze TestCtrl_e.vhd 46 | analyze TbStream.vhd 47 | -------------------------------------------------------------------------------- /AxiStream/testbenchVti_Alt/README.md: -------------------------------------------------------------------------------- 1 | # testbenchVti_Alt 2 | Implements external names in TbStream (TestHarness) rather than in TestCtrl. -------------------------------------------------------------------------------- /AxiStream/testbenchVti_Alt/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 05/2018 2018.05 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | library ieee ; 43 | use ieee.std_logic_1164.all ; 44 | use ieee.numeric_std.all ; 45 | use ieee.numeric_std_unsigned.all ; 46 | 47 | library OSVVM ; 48 | context OSVVM.OsvvmContext ; 49 | use osvvm.ScoreboardPkg_slv.all ; 50 | 51 | library osvvm_AXI4 ; 52 | context osvvm_AXI4.AxiStreamContext ; 53 | 54 | use work.OsvvmTestCommonPkg.all ; 55 | 56 | entity TestCtrl is 57 | generic ( 58 | ID_LEN : integer ; 59 | DEST_LEN : integer ; 60 | USER_LEN : integer 61 | ) ; 62 | port ( 63 | -- Global Signal Interface 64 | nReset : In std_logic ; 65 | 66 | -- Transaction Interfaces 67 | StreamTxRec : InOut StreamRecType ; 68 | StreamRxRec : InOut StreamRecType 69 | 70 | ) ; 71 | constant DATA_WIDTH : integer := StreamTxRec.DataToModel'length ; 72 | constant DATA_BYTES : integer := DATA_WIDTH/8 ; 73 | 74 | -- Simplifying access to Burst FIFOs using aliases 75 | alias TxBurstFifo : ScoreboardIdType is StreamTxRec.BurstFifo ; 76 | alias RxBurstFifo : ScoreboardIdType is StreamRxRec.BurstFifo ; 77 | end entity TestCtrl ; 78 | -------------------------------------------------------------------------------- /AxiStream/testbenchVti_Alt/build.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_TbAxiStreamVti_Alt 41 | 42 | include ../TestCases/OsvvmTestCommonPkg.pro 43 | 44 | analyze TestCtrl_e.vhd 45 | analyze TbStream.vhd 46 | 47 | #include ../TestCases 48 | RunTest ../TestCases/TbStream_SendGetDemo1.vhd 49 | -------------------------------------------------------------------------------- /AxiStream/testbench_GenericSignals/AxiStreamDut.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: AxiStreamDut.vhd 3 | -- Design Unit Name: AxiStreamDut 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- DUT pass thru for AxiStream VC testing 13 | -- Used to demonstrate DUT connections 14 | -- 15 | -- 16 | -- Developed by: 17 | -- SynthWorks Design Inc. 18 | -- VHDL Training Classes 19 | -- http://www.SynthWorks.com 20 | -- 21 | -- Revision History: 22 | -- Date Version Description 23 | -- 01/2023 2023.01 Initial 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2023 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | 43 | library ieee ; 44 | use ieee.std_logic_1164.all ; 45 | use ieee.numeric_std.all ; 46 | use ieee.numeric_std_unsigned.all ; 47 | use ieee.math_real.all ; 48 | 49 | library osvvm ; 50 | context osvvm.OsvvmContext ; 51 | 52 | entity AxiStreamDut is 53 | port ( 54 | -- AXI Transmitter Functional Interface 55 | TxTValid : out std_logic ; 56 | TxTReady : in std_logic ; 57 | TxTID : out std_logic_vector ; 58 | TxTDest : out std_logic_vector ; 59 | TxTUser : out std_logic_vector ; 60 | TxTData : out std_logic_vector ; 61 | TxTStrb : out std_logic_vector ; 62 | TxTKeep : out std_logic_vector ; 63 | TxTLast : out std_logic ; 64 | 65 | -- AXI Receiver Functional Interface 66 | RxTValid : in std_logic ; 67 | RxTReady : out std_logic ; 68 | RxTID : in std_logic_vector ; 69 | RxTDest : in std_logic_vector ; 70 | RxTUser : in std_logic_vector ; 71 | RxTData : in std_logic_vector ; 72 | RxTStrb : in std_logic_vector ; 73 | RxTKeep : in std_logic_vector ; 74 | RxTLast : in std_logic 75 | ) ; 76 | end entity AxiStreamDut ; 77 | architecture DUT of AxiStreamDut is 78 | begin 79 | 80 | TxTValid <= RxTValid; 81 | RxTReady <= TxTReady; 82 | TxTID <= RxTID ; 83 | TxTDest <= RxTDest ; 84 | TxTUser <= RxTUser ; 85 | TxTData <= RxTData ; 86 | TxTStrb <= RxTStrb ; 87 | TxTKeep <= RxTKeep ; 88 | TxTLast <= RxTLast ; 89 | 90 | end architecture DUT ; 91 | -------------------------------------------------------------------------------- /AxiStream/testbench_GenericSignals/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 05/2018 2018.05 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | library ieee ; 43 | use ieee.std_logic_1164.all ; 44 | use ieee.numeric_std.all ; 45 | use ieee.numeric_std_unsigned.all ; 46 | 47 | library OSVVM ; 48 | context OSVVM.OsvvmContext ; 49 | use osvvm.ScoreboardPkg_slv.all ; 50 | 51 | library osvvm_AXI4 ; 52 | context osvvm_AXI4.AxiStreamContext ; 53 | 54 | use work.OsvvmTestCommonPkg.all ; 55 | 56 | entity TestCtrl is 57 | generic ( 58 | ID_LEN : integer ; 59 | DEST_LEN : integer ; 60 | USER_LEN : integer 61 | ) ; 62 | port ( 63 | -- Global Signal Interface 64 | nReset : In std_logic ; 65 | 66 | -- Transaction Interfaces 67 | StreamTxRec : InOut StreamRecType ; 68 | StreamRxRec : InOut StreamRecType 69 | 70 | ) ; 71 | 72 | -- Derive AXI interface properties from the StreamTxRec 73 | constant DATA_WIDTH : integer := StreamTxRec.DataToModel'length ; 74 | constant DATA_BYTES : integer := DATA_WIDTH/8 ; 75 | 76 | -- Simplifying access to Burst FIFOs using aliases 77 | alias TxBurstFifo : ScoreboardIdType is StreamTxRec.BurstFifo ; 78 | alias RxBurstFifo : ScoreboardIdType is StreamRxRec.BurstFifo ; 79 | end entity TestCtrl ; 80 | -------------------------------------------------------------------------------- /AxiStream/testbench_GenericSignals/build.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | library osvvm_TbAxiStream_GenericSignals 42 | TestSuite TbAxiStream_GenericSignals 43 | 44 | include ../TestCases/OsvvmTestCommonPkg.pro 45 | 46 | analyze TestCtrl_e.vhd 47 | analyze AxiStreamDut.vhd 48 | analyze TbStream.vhd 49 | 50 | include ../TestCases/build_demo.pro 51 | -------------------------------------------------------------------------------- /AxiStream/testbench_xilinx/AxiStreamDut.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: AxiStreamDut.vhd 3 | -- Design Unit Name: AxiStreamDut 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- DUT pass thru for AxiStream VC testing 13 | -- Used to demonstrate DUT connections 14 | -- 15 | -- 16 | -- Developed by: 17 | -- SynthWorks Design Inc. 18 | -- VHDL Training Classes 19 | -- http://www.SynthWorks.com 20 | -- 21 | -- Revision History: 22 | -- Date Version Description 23 | -- 01/2023 2023.01 Initial 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2023 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | 43 | library ieee ; 44 | use ieee.std_logic_1164.all ; 45 | use ieee.numeric_std.all ; 46 | use ieee.numeric_std_unsigned.all ; 47 | use ieee.math_real.all ; 48 | 49 | library osvvm ; 50 | context osvvm.OsvvmContext ; 51 | 52 | entity AxiStreamDut is 53 | port ( 54 | -- AXI Transmitter Functional Interface 55 | TxTValid : out std_logic ; 56 | TxTReady : in std_logic ; 57 | TxTID : out std_logic_vector ; 58 | TxTDest : out std_logic_vector ; 59 | TxTUser : out std_logic_vector ; 60 | TxTData : out std_logic_vector ; 61 | TxTStrb : out std_logic_vector ; 62 | TxTKeep : out std_logic_vector ; 63 | TxTLast : out std_logic ; 64 | 65 | -- AXI Receiver Functional Interface 66 | RxTValid : in std_logic ; 67 | RxTReady : out std_logic ; 68 | RxTID : in std_logic_vector ; 69 | RxTDest : in std_logic_vector ; 70 | RxTUser : in std_logic_vector ; 71 | RxTData : in std_logic_vector ; 72 | RxTStrb : in std_logic_vector ; 73 | RxTKeep : in std_logic_vector ; 74 | RxTLast : in std_logic 75 | ) ; 76 | end entity AxiStreamDut ; 77 | architecture DUT of AxiStreamDut is 78 | begin 79 | 80 | TxTValid <= RxTValid; 81 | RxTReady <= TxTReady; 82 | TxTID <= RxTID ; 83 | TxTDest <= RxTDest ; 84 | TxTUser <= RxTUser ; 85 | TxTData <= RxTData ; 86 | TxTStrb <= RxTStrb ; 87 | TxTKeep <= RxTKeep ; 88 | TxTLast <= RxTLast ; 89 | 90 | end architecture DUT ; 91 | -------------------------------------------------------------------------------- /AxiStream/testbench_xilinx/TestCtrl_e.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: TestCtrl_e.vhd 3 | -- Design Unit Name: TestCtrl 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Test transaction source 13 | -- 14 | -- 15 | -- Developed by: 16 | -- SynthWorks Design Inc. 17 | -- VHDL Training Classes 18 | -- http://www.SynthWorks.com 19 | -- 20 | -- Revision History: 21 | -- Date Version Description 22 | -- 05/2018 2018.05 Initial revision 23 | -- 01/2020 2020.01 Updated license notice 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | library ieee ; 43 | use ieee.std_logic_1164.all ; 44 | use ieee.numeric_std.all ; 45 | use ieee.numeric_std_unsigned.all ; 46 | 47 | library OSVVM ; 48 | context OSVVM.OsvvmContext ; 49 | use osvvm.ScoreboardPkg_slv.all ; 50 | 51 | library osvvm_AXI4 ; 52 | context osvvm_AXI4.AxiStreamContext ; 53 | 54 | use work.OsvvmTestCommonPkg.all ; 55 | 56 | entity TestCtrl is 57 | generic ( 58 | ID_LEN : integer ; 59 | DEST_LEN : integer ; 60 | USER_LEN : integer 61 | ) ; 62 | port ( 63 | -- Global Signal Interface 64 | nReset : In std_logic ; 65 | 66 | -- Transaction Interfaces 67 | StreamTxRec : InOut StreamRecType ; 68 | StreamRxRec : InOut StreamRecType 69 | 70 | ) ; 71 | 72 | -- Derive AXI interface properties from the StreamTxRec 73 | constant DATA_WIDTH : integer := StreamTxRec.DataToModel'length ; 74 | constant DATA_BYTES : integer := DATA_WIDTH/8 ; 75 | 76 | -- Simplifying access to Burst FIFOs using aliases 77 | alias TxBurstFifo : ScoreboardIdType is StreamTxRec.BurstFifo ; 78 | alias RxBurstFifo : ScoreboardIdType is StreamRxRec.BurstFifo ; 79 | end entity TestCtrl ; 80 | -------------------------------------------------------------------------------- /AxiStream/testbench_xilinx/build.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_TbAxiStream 41 | 42 | include ../TestCases/OsvvmTestCommonPkg.pro 43 | 44 | analyze TestCtrl_e.vhd 45 | analyze AxiStreamDut.vhd 46 | analyze TbStream.vhd 47 | 48 | analyze TbStream_SendGet1.vhd 49 | TestName TbStream_SendGet1 50 | simulate TbStream 51 | 52 | analyze TbStream_SendGetDemo1.vhd 53 | TestName TbStream_SendGetDemo1 54 | simulate TbStream 55 | -------------------------------------------------------------------------------- /AxiStream/testbench_xilinx/build_demo.pro: -------------------------------------------------------------------------------- 1 | # File Name: testbench.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Script to run one Axi Stream test 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | library osvvm_TbAxiStream 41 | 42 | include ../TestCases/OsvvmTestCommonPkg.pro 43 | 44 | analyze TestCtrl_e.vhd 45 | analyze AxiStreamDut.vhd 46 | analyze TbStream.vhd 47 | 48 | # analyze TbStream_Xilinx1.vhd 49 | # TestName TbStream_Xilinx1 50 | # simulate TbStream 51 | 52 | analyze TbStream_SendGetDemo1.vhd 53 | TestName TbStream_SendGetDemo1 54 | simulate TbStream 55 | 56 | -------------------------------------------------------------------------------- /CONTRIBUTORS.md: -------------------------------------------------------------------------------- 1 | This file is deprecated. 2 | See [AUTHORS](AUTHORS.md). -------------------------------------------------------------------------------- /RunAllTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Run all OSVVM AXI4 Verification Component tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | # if {$::osvvm::ToolVendor ne "GHDL"} { puts Abc } 41 | 42 | include ./Axi4Lite/RunAllTests.pro 43 | include ./Axi4/RunAllTests.pro 44 | include ./AxiStream/RunAllTests.pro 45 | -------------------------------------------------------------------------------- /RunAllTestsVti.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Run all OSVVM AXI4 Verification Component tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | if {$::osvvm::ToolVendor ne "GHDL" && $::osvvm::ToolName ne "XSIM" } { 41 | include ./Axi4/RunAllTestsVti.pro 42 | include ./AxiStream/RunAllTestsVti.pro 43 | # include ./Axi4Lite/RunAllTestsVti.pro 44 | } 45 | -------------------------------------------------------------------------------- /RunDemoTests.pro: -------------------------------------------------------------------------------- 1 | # File Name: RunAllTests.pro 2 | # Revision: STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Run all OSVVM AXI4 Verification Component tests 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 1/2019 2019.01 Compile Script for OSVVM 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 23 | # 24 | # This file is part of OSVVM. 25 | # 26 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 27 | # 28 | # Licensed under the Apache License, Version 2.0 (the "License"); 29 | # you may not use this file except in compliance with the License. 30 | # You may obtain a copy of the License at 31 | # 32 | # https://www.apache.org/licenses/LICENSE-2.0 33 | # 34 | # Unless required by applicable law or agreed to in writing, software 35 | # distributed under the License is distributed on an "AS IS" BASIS, 36 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | # See the License for the specific language governing permissions and 38 | # limitations under the License. 39 | # 40 | 41 | # if {$::osvvm::ToolVendor ne "GHDL"} { 42 | # # Has failures. Keep it commented out until Axi4Lite updated 43 | # include ./Axi4Lite/RunDemoTests.pro 44 | # } 45 | include ./Axi4/RunDemoTests.pro 46 | include ./Axi4Lite/RunDemoTests.pro 47 | include ./AxiStream/RunDemoTests.pro 48 | -------------------------------------------------------------------------------- /common/common.pro: -------------------------------------------------------------------------------- 1 | # File Name: common.pro 2 | # Revision: OSVVM MODELS STANDARD VERSION 3 | # 4 | # Maintainer: Jim Lewis email: jim@synthworks.com 5 | # Contributor(s): 6 | # Jim Lewis jim@synthworks.com 7 | # 8 | # 9 | # Description: 10 | # Top level script to compile the Axi4 common packages 11 | # 12 | # Developed for: 13 | # SynthWorks Design Inc. 14 | # VHDL Training Classes 15 | # 11898 SW 128th Ave. Tigard, Or 97223 16 | # http://www.SynthWorks.com 17 | # 18 | # Revision History: 19 | # Date Version Description 20 | # 11/2022 2022.11 Added Axi4OptionsArrayPkg 21 | # 1/2020 2020.01 Updated Licenses to Apache 22 | # 1/2019 2019.01 Compile Script for OSVVM 23 | # 24 | # 25 | # This file is part of OSVVM. 26 | # 27 | # Copyright (c) 2019 - 2020 by SynthWorks Design Inc. 28 | # 29 | # Licensed under the Apache License, Version 2.0 (the "License"); 30 | # you may not use this file except in compliance with the License. 31 | # You may obtain a copy of the License at 32 | # 33 | # https://www.apache.org/licenses/LICENSE-2.0 34 | # 35 | # Unless required by applicable law or agreed to in writing, software 36 | # distributed under the License is distributed on an "AS IS" BASIS, 37 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | # See the License for the specific language governing permissions and 39 | # limitations under the License. 40 | # 41 | library osvvm_axi4 42 | ChangeWorkingDirectory ./src 43 | analyze Axi4InterfaceCommonPkg.vhd 44 | analyze Axi4LiteInterfacePkg.vhd 45 | analyze Axi4InterfacePkg.vhd 46 | analyze Axi4CommonPkg.vhd 47 | analyze Axi4ModelPkg.vhd 48 | analyze Axi4OptionsPkg.vhd 49 | analyze Axi4OptionsArrayPkg.vhd 50 | analyze Axi4VersionCompatibilityPkg.vhd -------------------------------------------------------------------------------- /common/src/Axi4InterfaceCommonPkg.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: Axi4InterfaceCommonPkg.vhd 3 | -- Design Unit Name: Axi4InterfaceCommonPkg 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Defines types, constants, and subprograms to support the Axi4Lite interface to DUT 13 | -- These are currently only intended for testbench models. 14 | -- When VHDL-2018 intefaces gain popular support, these will be changed to support them. 15 | -- 16 | -- 17 | -- Developed by: 18 | -- SynthWorks Design Inc. 19 | -- VHDL Training Classes 20 | -- http://www.SynthWorks.com 21 | -- 22 | -- Revision History: 23 | -- Date Version Description 24 | -- 03/2022 2022.03 Factored out of Axi4InterfacePkg/Axi4LiteInterfacePkg 25 | -- 01/2020 2020.01 Updated license notice 26 | -- 09/2017 2017 Initial revision 27 | -- 28 | -- 29 | -- This file is part of OSVVM. 30 | -- 31 | -- Copyright (c) 2017 - 2022 by SynthWorks Design Inc. 32 | -- 33 | -- Licensed under the Apache License, Version 2.0 (the "License"); 34 | -- you may not use this file except in compliance with the License. 35 | -- You may obtain a copy of the License at 36 | -- 37 | -- https://www.apache.org/licenses/LICENSE-2.0 38 | -- 39 | -- Unless required by applicable law or agreed to in writing, software 40 | -- distributed under the License is distributed on an "AS IS" BASIS, 41 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 42 | -- See the License for the specific language governing permissions and 43 | -- limitations under the License. 44 | -- 45 | 46 | library ieee ; 47 | use ieee.std_logic_1164.all ; 48 | 49 | 50 | package Axi4InterfaceCommonPkg is 51 | subtype Axi4RespType is std_logic_vector(1 downto 0) ; 52 | constant AXI4_RESP_OKAY : Axi4RespType := "00" ; 53 | constant AXI4_RESP_EXOKAY : Axi4RespType := "01" ; -- Not for Lite 54 | constant AXI4_RESP_SLVERR : Axi4RespType := "10" ; 55 | constant AXI4_RESP_DECERR : Axi4RespType := "11" ; 56 | constant AXI4_RESP_INIT : Axi4RespType := "ZZ" ; 57 | 58 | subtype Axi4ProtType is std_logic_vector(2 downto 0) ; 59 | -- [0] 0 Unprivileged access 60 | -- 1 Privileged access 61 | -- [1] 0 Secure access 62 | -- 1 Non-secure access 63 | -- [2] 0 Data access 64 | -- 1 Instruction access 65 | constant AXI4_PROT_INIT : Axi4ProtType := "ZZZ" ; 66 | 67 | end package Axi4InterfaceCommonPkg ; 68 | 69 | 70 | 71 | 72 | -------------------------------------------------------------------------------- /common/src/Axi4VersionCompatibilityPkg.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- File Name: Axi4LiteVersionCompatibilityPkg.vhd 3 | -- Design Unit Name: Axi4LiteVersionCompatibilityPkg 4 | -- Revision: OSVVM MODELS STANDARD VERSION 5 | -- 6 | -- Maintainer: Jim Lewis email: jim@synthworks.com 7 | -- Contributor(s): 8 | -- Jim Lewis jim@synthworks.com 9 | -- 10 | -- 11 | -- Description: 12 | -- Defines types, constants, and subprograms used to 13 | -- facilitate backward compatibility with AXI4 Models 14 | -- 15 | -- 16 | -- Developed by: 17 | -- SynthWorks Design Inc. 18 | -- VHDL Training Classes 19 | -- http://www.SynthWorks.com 20 | -- 21 | -- Revision History: 22 | -- Date Version Description 23 | -- 01/2020 2020.02 Refactored from Axi4SlaveTransactionPkg.vhd 24 | -- 25 | -- 26 | -- This file is part of OSVVM. 27 | -- 28 | -- Copyright (c) 2017 - 2020 by SynthWorks Design Inc. 29 | -- 30 | -- Licensed under the Apache License, Version 2.0 (the "License"); 31 | -- you may not use this file except in compliance with the License. 32 | -- You may obtain a copy of the License at 33 | -- 34 | -- https://www.apache.org/licenses/LICENSE-2.0 35 | -- 36 | -- Unless required by applicable law or agreed to in writing, software 37 | -- distributed under the License is distributed on an "AS IS" BASIS, 38 | -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | -- See the License for the specific language governing permissions and 40 | -- limitations under the License. 41 | -- 42 | 43 | library osvvm ; 44 | context osvvm.OsvvmContext ; 45 | 46 | library osvvm_common ; 47 | context osvvm_common.OsvvmCommonContext ; 48 | 49 | package Axi4VersionCompatibilityPkg is 50 | 51 | -- Translate from Axi4Lite interface names to new name: AddressBusTransactionRecType 52 | alias MasterTransactionRecType is AddressBusTransactionRecType ; 53 | alias Axi4LiteMasterTransactionRecType is AddressBusTransactionRecType ; 54 | 55 | -- Translate from Axi4Lite interface names to new name: AddressBusTransactionRecType 56 | alias Axi4LiteSlaveTransactionRecType is AddressBusTransactionRecType ; 57 | 58 | end package Axi4VersionCompatibilityPkg ; 59 | 60 | --------------------------------------------------------------------------------