├── .gitignore ├── .gitmodules ├── LICENSE.md └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | Scripts/results/* 2 | !Scripts/results/README.md 3 | Scripts/logs/* 4 | Scripts/VHDL_LIBS 5 | Scripts/modelsim.ini 6 | Scripts/vsim.wlf 7 | Scripts/dataset.* 8 | Scripts/library.cfg 9 | Scripts/compile 10 | sim 11 | sim/* 12 | Docs 13 | Docs/* 14 | UART/plan 15 | UART/plan/* -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "AXI4"] 2 | path = AXI4 3 | url = https://github.com/OSVVM/AXI4.git 4 | [submodule "Scripts"] 5 | path = Scripts 6 | url = https://github.com/OSVVM/OSVVM-Scripts.git 7 | [submodule "UART"] 8 | path = UART 9 | url = https://github.com/OSVVM/UART.git 10 | [submodule "Common"] 11 | path = Common 12 | url = https://github.com/OSVVM/OSVVM-Common.git 13 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | This is a local copy of the Apache License Version 2.0. 2 | The original can be obtained here: [http://www.apache.org/licenses/LICENSE-2.0](http://www.apache.org/licenses/LICENSE-2.0) 3 | 4 | -------------------------------------------------------------------------------- 5 | 6 | # Apache License 7 | 8 | Version 2.0, January 2004 9 | 10 | ## TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 11 | 12 | ### 1. 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The text should be enclosed in the appropriate comment syntax for the file format. We also recommend that a file or class name and description of purpose be included on the same "printed page" as the copyright notice for easier identification within third-party archives. 69 | 70 | Copyright [yyyy] [name of copyright owner] 71 | 72 | Licensed under the Apache License, Version 2.0 (the "License"); 73 | you may not use this file except in compliance with the License. 74 | You may obtain a copy of the License at 75 | 76 | http://www.apache.org/licenses/LICENSE-2.0 77 | 78 | Unless required by applicable law or agreed to in writing, software 79 | distributed under the License is distributed on an "AS IS" BASIS, 80 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 81 | See the License for the specific language governing permissions and 82 | limitations under the License. 83 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Deprecated: Please see [OSVVM Libraries](https://github.com/OSVVM/OsvvmLibraries) 2 | Change is inevitable. Sometimes sooner than expected. 3 | The Verification IP repository has been replaced by the 4 | OsvvmLibraries repository. 5 | 6 | See: [OSVVM Libraries](https://github.com/OSVVM/OsvvmLibraries) 7 | 8 | "Git" the entire OSVVM model library using git clone with the "--recursive" flag: 9 | `git clone --recursive https://github.com/OSVVM/OsvvmLibraries.git` 10 | 11 | # Verification IP Library 12 | This repository is current through the 2020.07 release. 13 | 14 | Why deprecate? 15 | With OsvvmLibraries includes the 16 | OSVVM utility, documentation, scripts, and verification component repositories 17 | as submodules. 18 | 19 | The Verification IP library includes just the 20 | OSVVM scripts and verification component repositories 21 | as submodules. 22 | 23 | It is easier to manage a single repository rather than 24 | having separate repositories. 25 | 26 | ## About OSVVM 27 | [OSVVM](https://OSVVM.github.io) provides 28 | [utility](https://github.com/OSVVM/OSVVM) and model libraries that simplify 29 | your FPGA and ASIC verification tasks. 30 | Using these libraries you can create a simple, readable, and 31 | powerful testbench that is suitable for either a simple FPGA block 32 | or a complex ASIC. 33 | 34 | ## Current Models - Submodules 35 | - [AXI4 Full](https://github.com/OSVVM/AXI4) 36 | - Master - includes burst support 37 | - Memory Responder model - includes burst support 38 | - Transaction Responder model - but it does not support bursts 39 | - [AXI4 Lite](https://github.com/OSVVM/AXI4) 40 | - Master 41 | - Transaction Responder model 42 | - [AXI Stream](https://github.com/OSVVM/AXI4) 43 | - Master 44 | - Slave 45 | - [UART](https://github.com/OSVVM/AXI4) 46 | - Transmitter (aka master) - with error injection 47 | - Receiver (aka slave) - with error injection 48 | - [OSVVM Common - Required](https://github.com/OSVVM/OSVVM-Common) 49 | - Shared transcript interfaces 50 | - [OSVVM Scripts](https://github.com/OSVVM/OSVVM-Scripts) 51 | - Recommended. Script layer on top of tcl 52 | - Common simulator compilation and execution methodology 53 | 54 | 55 | ## Models vs TBM vs VVC vs BFM 56 | We use the word models as short hand for 57 | Transaction Based Models (TBM). 58 | They are simply an entity and architecture coded in 59 | an effective manner for verification. 60 | Some use other terminology such as 61 | VHDL verification components (VVC) - 62 | these are the same thing. 63 | Historically we called the models 64 | Bus Functional Models (BFM). - which in they are. 65 | However, recently we abandoned BFM due to others using BFM to 66 | refer to their own lesser capable subprogram based approach. 67 | 68 | ## OSVVM Interfaces 69 | OSVVM models use records for the transaction interfaces, 70 | so connecting them to your testbench is simple - 71 | connect only a single signal. 72 | 73 | Currently this methodology requires that the records 74 | use element types with resolution functions. 75 | See the OSVVM Utility library package, 76 | ResolutionPkg.vhd. 77 | 78 | When VHDL-2019 is implemented, we plan to 79 | transition to the new interface feature. 80 | This feature is also based on records and for OSVVM only requires the addition of a mode 81 | view declaration in the package and an update to the model port declarations. 82 | 83 | ## Model Testbenches are Included 84 | 85 | Testbenches are in the Git repository, so you can 86 | run a simulation and see a live example 87 | of how to use the models. 88 | --------------------------------------------------------------------------------