├── LICENSE ├── README.md ├── build ├── .gitignore ├── README.md ├── bsub_batch ├── bsub_run ├── build.lsf ├── clean_all.sh ├── clean_ice.sh ├── create_ip_ice.tcl ├── edit_ip.tcl ├── gen_bitstream.tcl ├── gen_simout.tcl ├── get_image.sh ├── implement.tcl ├── insert_ila.tcl ├── print_warnings_ice.sh ├── run ├── run_ice.sh ├── synthesize.tcl ├── waived_warnings.txt └── write_git_meta.sh ├── ibm ├── std_ulogic_function_support.vhdl ├── std_ulogic_support.vhdl ├── std_ulogic_unsigned.vhdl └── synthesis_support.vhdl ├── ice ├── doc │ └── ICE_workbook_openPower.odt └── src │ ├── board │ └── gemini │ │ ├── ice_top.vhdl │ │ ├── ila.xdc │ │ ├── pins.xdc │ │ └── timing.xdc │ ├── csv │ └── custom_parts_ddr4_mt_x8_16Gb_2133mhz.csv │ ├── dlx │ ├── ocx_bram_infer.v │ ├── ocx_dlx_crc.v │ ├── ocx_dlx_crc16.v │ ├── ocx_dlx_rx_bs.v │ ├── ocx_dlx_rx_lane.v │ ├── ocx_dlx_rx_lane_66.v │ ├── ocx_dlx_rx_main.v │ ├── ocx_dlx_rxdf.v │ ├── ocx_dlx_top.v │ ├── ocx_dlx_tx_ctl.v │ ├── ocx_dlx_tx_flt.v │ ├── ocx_dlx_tx_gbx.v │ ├── ocx_dlx_tx_que.v │ ├── ocx_dlx_txdf.v │ └── ocx_dlx_xlx_if.v │ ├── headers │ ├── cfg_func0_init.v │ └── cfg_func_init.v │ ├── verilog │ ├── .gitkeep │ ├── cfg_cmdfifo.v │ ├── cfg_descriptor.v │ ├── cfg_func.v │ ├── cfg_func0.v │ ├── cfg_respfifo.v │ ├── cfg_seq.v │ ├── cfg_top.v │ ├── ice_tlx_6x16_fifo.v │ ├── ice_tlx_framer.v │ ├── iram_1r1w1ck_64x112.v │ ├── iram_1r1w1ck_64x16.v │ ├── iram_1r1w1ck_64x32.v │ ├── iram_1r1w1ck_64x518.v │ ├── iram_1r1w1ck_64x519.v │ ├── iram_1r1w1ck_64x85.v │ ├── ocx_leaf_inferd_regfile.v │ ├── ocx_tlx_514x16_fifo.v │ ├── ocx_tlx_fifo_cntlr.v │ ├── ocx_tlx_framer_cmd_fifo.v │ └── ocx_tlx_framer_rsp_fifo.v │ └── vhdl │ ├── .gitignore │ ├── .gitkeep │ ├── axi_pkg.vhdl │ ├── axi_regs_32.vhdl │ ├── counter.vhdl │ ├── gemini_tlx_pkg.vhdl │ ├── ice_afu_cfg.vhdl │ ├── ice_afu_cmd_fifo.vhdl │ ├── ice_afu_mac.vhdl │ ├── ice_afu_main.vhdl │ ├── ice_afu_ui.vhdl │ ├── ice_cal_retry.vhdl │ ├── ice_cfg_reg.vhdl │ ├── ice_core.vhdl │ ├── ice_err_reg.vhdl │ ├── ice_errrpt_intrp.vhdl │ ├── ice_func.vhdl │ ├── ice_gmc_arb.vhdl │ ├── ice_gmc_asynclat.vhdl │ ├── ice_gmc_dpull.vhdl │ ├── ice_gmc_etrap.vhdl │ ├── ice_gmc_func_pkg.vhdl │ ├── ice_gmc_mc_eng.vhdl │ ├── ice_gmc_ram.vhdl │ ├── ice_gmc_top.vhdl │ ├── ice_gmc_xfifo.vhdl │ ├── ice_i2c_control_mac.vhdl │ ├── ice_mc_top.vhdl │ ├── ice_mem_init.vhdl │ ├── ice_mmio_fifo.vhdl │ ├── ice_mmio_mac.vhdl │ ├── ice_pervasive.vhdl │ ├── ice_regs.vhdl │ ├── ice_tlx_rcv.vhdl │ ├── ice_tlx_top.vhdl │ ├── ice_trap_reg.vhdl │ ├── iram_fifo_64x112.vhdl │ ├── iram_fifo_64x16.vhdl │ ├── iram_fifo_64x32.vhdl │ ├── iram_fifo_64x518.vhdl │ ├── iram_fifo_64x85.vhdl │ ├── iram_input_fifo.vhdl │ └── tlx_fifo.vhdl ├── scripts ├── adding_fire1 ├── adding_fire2 ├── adding_fire3 ├── adding_fire4 ├── adding_fire5 ├── adding_ice1 ├── adding_ice2 ├── adding_ice3 ├── adding_ice4 ├── adding_ice5 ├── adding_ice6 ├── adding_ice7 ├── all_shells4fire.sh ├── all_shells4ice.sh ├── gtwiz_bit_sync.sh ├── gtwiz_example_top2phy_wrap_prep1.sh ├── gtwiz_example_top2phy_wrap_prep2.sh ├── gtwiz_init_dlx.sh ├── gtwiz_phy2wrap_ref_4ice.sh ├── gtwiz_reset.sh ├── gtwiz_userclk_tx_dlx.sh ├── gtwiz_wrap_ref2wrap0_4ice.sh ├── gtwiz_wrapper.sh └── gtwiz_wrapper0_4ice.sh └── support └── logic_support_pkg.vhdl /README.md: -------------------------------------------------------------------------------- 1 | # License 2 | 3 | Copyright 2019 International Business Machines 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use the files in this repository except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | The patent license granted to you in Section 3 of the License, as applied 11 | to the "Work," hereby includes implementations of the Work in physical form. 12 | 13 | Unless required by applicable law or agreed to in writing, the reference design 14 | distributed under the License is distributed on an "AS IS" BASIS, 15 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | See the License for the specific language governing permissions and 17 | limitations under the License. 18 | 19 | The background Specification upon which this is based is managed by and available from 20 | the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | 22 | # Purpose 23 | 24 | This ICE design contains the FPGA code of an OMI host. It has all the features needed to 25 | configure, initialize, train and test an OMI DDIMM through OMI links. 26 | 27 | OMI stands for Open Memory Interface. Check OMI web site at https://openmemoryinterface.org 28 | 29 | Friendly documentation providing reference documentation, design and enablement code 30 | can also be found at https://opencapi.github.io/omi-doc/ 31 | 32 | # Hardware requirements 33 | 34 | As of today, this ICE design targets only 1 board: 35 | * __Gemini__ board which is a lab experimentation board (not for distribution) 36 | * AMD/Xilinx FPGA __XCZU19EG__ 37 | * 1 port (x8 OMI links) enabled in this design 38 | 39 | Any new board or additional ports can be easily added. Board specific files can be found in ~/ice/src/board/ 40 | 41 | I2C communication with these boards can be done with a Rasberry Pi. 42 | 43 | AMD/Xilinx Vivado 2021.2 is used to build the FPGA binary images. 44 | 45 | Code is designed for AMD/Xilinx UltraScale+ FPGA family. 46 | 47 | More about enablement on https://opencapi.github.io/omi-doc/blocs/enablement 48 | 49 | # FPGA Build Scripts 50 | 51 | The /build directory contains the various scripts needed to synthesize and 52 | implement RTL, as well as generate a bitstream, for an FPGA using the 53 | Fire design. (it was targeting fire (host) and ice (device) but 54 | only fire is available yet) 55 | 56 | To quickly get started, the sequence is (`$design` is fire ): 57 | 58 | ``` 59 | cd build 60 | ./run $design synthesize.tcl 61 | ./run $design implement.tcl 62 | ./run $design gen_bitstream.tcl 63 | ``` 64 | 65 | The following command launches for the entire process, with some optimization choices: 66 | 67 | ``` 68 | ./run_ice.sh 69 | ``` 70 | 71 | ## Main Scripts and Directories 72 | 73 | __run__: Takes a TCL script file and a design as an argument, and runs 74 | that TCL script on that design using Vivado 2018.3 in the terminal (no 75 | GUI). The command output is written to `$design/$command.log`, and 76 | also colorized and printed to the screen. Output files are saved in 77 | the `$design/` directory, including a design checkpoint (.dcp file). 78 | 79 | __run_ice.sh__: Runs the main synthesize, then implement using strategy 17, 80 | and gen_bitstream with implementation strategy result 17. This number will be 81 | adapted depending on the design and the WNS result displayed at the end of 82 | the place and route phase. If run on 83 | a machine with a `bsub` binary found (aka LSF is installed), then the 84 | commands are dispatched via LSF. Additionally, 16 implementation 85 | strategies are launched in parallel, and the timing results are 86 | checked on completed runs. The first completed implementation strategy 87 | that meets timing is used for the bitstream. Also in this mode, the 88 | "important" output files are copied to the `$design_deploy/` directory. 89 | 90 | __ice/__ : Contain all output files from Vivado. Each 91 | command outputs to a log stored in the top-level directory, and other 92 | files are stored in a sub-directory per command. 93 | 94 | ## Vivado TCL Scripts 95 | 96 | __synthesize.tcl__: Load libraries and read RTL and constraint files, 97 | recompile IP (if needed), synthesize the design, and add the ILA IP. 98 | 99 | __insert_ila.tcl__: Helper script for synthesize.tcl that adds all 100 | signals marked with the mark_debug to a correctly clocked Integrated 101 | Logic Analyzer (ILA) (Trace Array in IBM speak). 102 | 103 | __implement.tcl__: Implements a synthesized design, and creates 104 | various reports. Takes an argument to select the implementation 105 | strategy used (uses strategy 1 if not given). 106 | 107 | __gen_bitstream.tcl__: Generate the bistream and debug probes for an 108 | implemented design. Takes an argument to select the implementation 109 | strategy used (uses strategy 1 if not given). 110 | 111 | __edit_ip.tcl__: Open all the IP in `src/ip/` for editing in the Vivado 112 | GUI (not in a project). Also used to add new IP. 113 | 114 | ## LSF Wrappers and Configurations 115 | 116 | __bsub_run__: Same as run, but run a command via `bsub` and print 117 | output to the screen. 118 | 119 | __bsub_batch__: Same as run, but run a command via `bsub` and run in 120 | background. 121 | 122 | __build.lsf__: LSF configuration used for all commands submitted via `bsub`. 123 | 124 | __clean_all.sh__: clean the whole project removing all files generated by scripts. 125 | 126 | __clean_ice.sh__: clean the whole ice project removing all files generated by scripts. 127 | 128 | ## Work-In-Progress 129 | 130 | These files are either a work-in-progress or stale, and should not be 131 | used. 132 | 133 | __waived_warnings.txt__: List of warnings that are known and 134 | acceptable. 135 | 136 | __print_warnings_ice.sh__: Print all the warnings in run.log that are not 137 | waived in waived_warnings.txt. 138 | -------------------------------------------------------------------------------- /build/.gitignore: -------------------------------------------------------------------------------- 1 | # Xilinx output files 2 | /fire* 3 | /ice/ 4 | /.Xil/ 5 | usage_statistics_webtalk.* 6 | *.log 7 | # IP creation marker file 8 | .OMI_IPs* 9 | -------------------------------------------------------------------------------- /build/README.md: -------------------------------------------------------------------------------- 1 | # FPGA Build Scripts 2 | 3 | This directory contains the various scripts needed to synthesize and 4 | implement RTL, as well as generate a bitstream, for an FPGA using the 5 | Ice design. 6 | 7 | The following command launches for the entire process, with some parallelization: 8 | 9 | ``` 10 | ./run_ice.sh 11 | ``` 12 | 13 | ## Main Scripts and Directories 14 | 15 | __run__: Takes a TCL script file and a design as an argument, and runs 16 | that TCL script on that design using Vivado 2018.3 in the terminal (no 17 | GUI). The command output is written to `$design/$command.log`, and 18 | also colorized and printed to the screen. Output files are saved in 19 | the `$design/` directory, including a design checkpoint (.dcp file). 20 | 21 | __run_ice.sh__: Runs the build image process for ice. Runs the main 22 | synthesize, implement, and gen_bitstream loop sequentially. If run on 23 | a machine with a `bsub` binary found (aka LSF is installed), then the 24 | commands are dispatched via LSF. Additionally, 16 implementation 25 | strategies are launched in parallel, and the timing results are 26 | checked on completed runs. The first completed implementation strategy 27 | that meets timing is used for the bitstream. Also in this mode, the 28 | "important" output files are copied to the `$design_deploy/` directory. 29 | 30 | __ice/__ : Contain all output files from Vivado. Each 31 | command outputs to a log stored in the top-level directory, and other 32 | files are stored in a sub-directory per command. 33 | 34 | ## Vivado TCL Scripts 35 | 36 | __synthesize.tcl__: Load libraries and read RTL and constraint files, 37 | recompile IP (if needed), synthesize the design, and add the ILA IP. 38 | 39 | __insert_ila.tcl__: Helper script for synthesize.tcl that adds all 40 | signals marked with the mark_debug to a correctly clocked Integrated 41 | Logic Analyzer (ILA) (Trace Array in IBM speak). 42 | 43 | __implement.tcl__: Implements a synthesized design, and creates 44 | various reports. Takes an argument to select the implementation 45 | strategy used (uses strategy 1 if not given). 46 | 47 | __gen_bitstream.tcl__: Generate the bistream and debug probes for an 48 | implemented design. Takes an argument to select the implementation 49 | strategy used (uses strategy 1 if not given). 50 | 51 | __edit_ip.tcl__: Open all the IP in `src/ip/` for editing in the Vivado 52 | GUI (not in a project). Also used to add new IP. 53 | 54 | ## LSF Wrappers and Configurations 55 | 56 | __bsub_run__: Same as run, but run a command via `bsub` and print 57 | output to the screen. 58 | 59 | __bsub_batch__: Same as run, but run a command via `bsub` and run in 60 | background. 61 | 62 | __build.lsf__: LSF configuration used for all commands submitted via `bsub`. 63 | 64 | ## Work-In-Progress 65 | 66 | These files are either a work-in-progress or stale, and should not be 67 | used. 68 | 69 | __waived_warnings.txt__: List of warnings that are known and 70 | acceptable. 71 | 72 | __print_warnings.sh__: Print all the warnings in run.log that are not 73 | waived in waived_warnings.txt. 74 | -------------------------------------------------------------------------------- /build/bsub_batch: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | 24 | set -e 25 | 26 | CWD=$(dirname "$(readlink -f "$0")") 27 | 28 | # Don't call with -Is so we can call several in parallel 29 | CMD="./run $@" bsub -cwd $CWD < $CWD/build.lsf 30 | -------------------------------------------------------------------------------- /build/bsub_run: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | 24 | set -e 25 | 26 | CWD=$(dirname "$(readlink -f "$0")") 27 | 28 | # Call with -Is so the output is printed to the screen 29 | CMD="./run $@" bsub -Is -cwd $CWD < $CWD/build.lsf 30 | -------------------------------------------------------------------------------- /build/build.lsf: -------------------------------------------------------------------------------- 1 | #BSUB -q normal # Queue (see `bqueues` or `bqueues -l queueName`) 2 | #BSUB -G ocmb # Group (see `bugroup`) 3 | #BSUB -P ocmb # Project 4 | 5 | #BSUB -n 1 # set the number of cpus this job will need 6 | #BSUB -M 4 # set the memory in GB this job will need. 7 | 8 | # Start on any X86_64 processor architecture machine. 9 | #BSUB -R "select[type==X86_64]" 10 | 11 | # Execute $CMD from env 12 | $CMD 13 | -------------------------------------------------------------------------------- /build/clean_all.sh: -------------------------------------------------------------------------------- 1 | ## 2 | ## Copyright 2022 International Business Machines 3 | ## 4 | ## Licensed under the Apache License, Version 2.0 (the "License"); 5 | ## you may not use this file except in compliance with the License. 6 | ## You may obtain a copy of the License at 7 | ## http://www.apache.org/licenses/LICENSE-2.0 8 | ## 9 | ## The patent license granted to you in Section 3 of the License, as applied 10 | ## to the "Work," hereby includes implementations of the Work in physical form. 11 | ## 12 | ## Unless required by applicable law or agreed to in writing, the reference design 13 | ## distributed under the License is distributed on an "AS IS" BASIS, 14 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | ## See the License for the specific language governing permissions and 16 | ## limitations under the License. 17 | ## 18 | ## The background Specification upon which this is based is managed by and available from 19 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | ## 21 | 22 | rm -rf .cache/ 23 | rm -rf .Xil 24 | rm -rf .ip_user_files 25 | rm -rf ip_dir 26 | rm *.log 27 | rm *.jou 28 | rm vivado*.str 29 | rm iter* 30 | rm usage_statistics_webtalk.* 31 | rm tight_setup_hold_pins.txt 32 | rm -rf ./.tmpCRC 33 | source ./clean_fire.sh 34 | source ./clean_ice.sh 35 | -------------------------------------------------------------------------------- /build/clean_ice.sh: -------------------------------------------------------------------------------- 1 | 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | rm .OMI_IPs_ice* 24 | rm -rf ../ip_created_for_ice 25 | rm -rf ice* 26 | rm -rf ../ice/src/ip/managed_ip_project 27 | rm ../ice/src/verilog/DLx* 28 | rm ../ice/src/verilog/dlx* 29 | rm ../ice/src/headers/DLx_phy_example_wrapper_functions.v 30 | rm ../ice/src/vhdl/meta_pkg.vhdl 31 | -------------------------------------------------------------------------------- /build/edit_ip.tcl: -------------------------------------------------------------------------------- 1 | 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | ################################################################################ 24 | # Project Settings 25 | ################################################################################ 26 | 27 | # Target FPGA 28 | variable XILINX_PART $::env(XILINX_PART) 29 | variable DESIGN $::env(DESIGN) 30 | 31 | # Output Directory 32 | variable OUTPUT_DIR $::env(SRC_DIR)/ip 33 | 34 | ################################################################################ 35 | # Create Project 36 | ################################################################################ 37 | create_project managed_ip_project $OUTPUT_DIR/managed_ip_project -part $XILINX_PART -ip -force 38 | add_files -norecurse [ glob $OUTPUT_DIR/../../../ip_created_for_$DESIGN/*/*.xci ] 39 | start_gui 40 | -------------------------------------------------------------------------------- /build/gen_bitstream.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Copyright 2022 International Business Machines 3 | ## 4 | ## Licensed under the Apache License, Version 2.0 (the "License"); 5 | ## you may not use this file except in compliance with the License. 6 | ## You may obtain a copy of the License at 7 | ## http://www.apache.org/licenses/LICENSE-2.0 8 | ## 9 | ## The patent license granted to you in Section 3 of the License, as applied 10 | ## to the "Work," hereby includes implementations of the Work in physical form. 11 | ## 12 | ## Unless required by applicable law or agreed to in writing, the reference design 13 | ## distributed under the License is distributed on an "AS IS" BASIS, 14 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | ## See the License for the specific language governing permissions and 16 | ## limitations under the License. 17 | ## 18 | ## The background Specification upon which this is based is managed by and available from 19 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | ## 21 | 22 | ################################################################################ 23 | # Arguments 24 | ################################################################################ 25 | # Pick results from an implementation strategy 26 | if {$argc > 0} { 27 | variable strategy_index [lindex $argv 0] 28 | puts " Running with results from implementation strategy $strategy_index." 29 | } else { 30 | variable strategy_index 1 31 | puts " Running with results from default implementation strategy $strategy_index." 32 | } 33 | 34 | ################################################################################ 35 | # Project Settings 36 | ################################################################################ 37 | # Source Directory 38 | # Path to source directory containing vhdl/ and verilog/ directories 39 | variable SRC_DIR $::env(SRC_DIR) 40 | 41 | # Output Directory 42 | variable OUTPUT_DIR $::env(OUTPUT_PREFIX) 43 | 44 | # Design Selected 45 | variable DESIGN $::env(DESIGN) 46 | set cwd [file dirname [file normalize [info script]]] 47 | variable TRACE_MODE $::env(TRACE_MODE) 48 | #if {( $TRACE_MODE == "no")} { 49 | set logfile $cwd/$DESIGN/gen_bitstream_script.log 50 | #} 51 | # 52 | ################################################################################ 53 | # Open Routing Checkpoint 54 | ################################################################################ 55 | puts " Opening post route design checkpoint ./impl_$strategy_index/post_route.dcp" 56 | open_checkpoint $OUTPUT_DIR/impl_$strategy_index/post_route.dcp >> $logfile 57 | 58 | ################################################################################ 59 | # Generate Bitstream 60 | ################################################################################ 61 | puts " Writing bitstream " 62 | write_bitstream -force $OUTPUT_DIR/$DESIGN.bit >> $logfile 63 | puts " Writing debug probes" 64 | write_debug_probes -force $OUTPUT_DIR/$DESIGN.ltx >> $logfile 65 | -------------------------------------------------------------------------------- /build/gen_simout.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Copyright 2022 International Business Machines 3 | ## 4 | ## Licensed under the Apache License, Version 2.0 (the "License"); 5 | ## you may not use this file except in compliance with the License. 6 | ## You may obtain a copy of the License at 7 | ## http://www.apache.org/licenses/LICENSE-2.0 8 | ## 9 | ## The patent license granted to you in Section 3 of the License, as applied 10 | ## to the "Work," hereby includes implementations of the Work in physical form. 11 | ## 12 | ## Unless required by applicable law or agreed to in writing, the reference design 13 | ## distributed under the License is distributed on an "AS IS" BASIS, 14 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | ## See the License for the specific language governing permissions and 16 | ## limitations under the License. 17 | ## 18 | ## The background Specification upon which this is based is managed by and available from 19 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | ## 21 | 22 | ################################################################################ 23 | # Project Settings 24 | ################################################################################ 25 | 26 | # Target FPGA 27 | variable XILINX_PART $::env(XILINX_PART) 28 | 29 | # Output Directory 30 | variable OUTPUT_DIR $::env(SRC_DIR)/ip 31 | 32 | ################################################################################ 33 | # Create Project 34 | ################################################################################ 35 | create_project -in_memory -part $XILINX_PART 36 | read_ip [ glob $OUTPUT_DIR/*/*.xci ] 37 | foreach ip [get_ips] { 38 | reset_target simulation $ip 39 | generate_target simulation $ip 40 | } 41 | -------------------------------------------------------------------------------- /build/get_image.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | 24 | jfrog rt download sys-memdev-astra-generic-local/fire.bit 25 | jfrog rt download sys-memdev-astra-generic-local/fire.ltx 26 | -------------------------------------------------------------------------------- /build/insert_ila.tcl: -------------------------------------------------------------------------------- 1 | # Source: https://forums.xilinx.com/t5/Vivado-TCL-Community/Vivado-TCL-script-to-insert-ILA/td-p/421619 2 | ###################################################################### 3 | # Automatically inserts ILA instances 4 | 5 | 6 | proc insert_ila {} { 7 | 8 | variable DESIGN 9 | set cwd [file dirname [file normalize [info script]]] 10 | set logfile $cwd/$DESIGN/insert_ila.log 11 | 12 | ################################################################## 13 | # sequence through debug nets and organize them by clock in the 14 | # clock_list array. Also create max and min array for bus indices 15 | set dbgs [get_nets -hierarchical -filter {MARK_DEBUG}] 16 | if {[llength $dbgs] == 0} { 17 | return 18 | } 19 | 20 | #temporarily limit warining messages to 10 21 | set_msg_config -id {[Timing 38-164]} -limit 10 22 | set_msg_config -id {[Vivado 12-975]} -limit 10 23 | 24 | puts "----------------------- adding debug nets -----------------------" 25 | foreach d $dbgs { 26 | # name is root name of a bus, index is the bit index in the 27 | # bus 28 | set name [regsub {\[[[:digit:]]+\]$} $d {}] 29 | set index [regsub {^.*\[([[:digit:]]+)\]$} $d {\1}] 30 | if {[string is integer -strict $index]} { 31 | if {![info exists max($name)]} { 32 | set max($name) $index 33 | set min($name) $index 34 | } elseif {$index > $max($name)} { 35 | set max($name) $index 36 | } elseif {$index < $min($name)} { 37 | set min($name) $index 38 | } 39 | } else { 40 | set max($name) -1 41 | } 42 | if {![info exists clocks($name)]} { 43 | set paths [get_timing_paths -through $d] 44 | if {[llength $paths] > 0} { 45 | set clocks($name) [get_property ENDPOINT_CLOCK [lindex $paths 0]] 46 | if {![info exists clock_list($clocks($name))]} { 47 | # found a new clock 48 | set clock_list($clocks($name)) [list $name] 49 | } else { 50 | lappend clock_list($clocks($name)) $name 51 | } 52 | } 53 | } 54 | } 55 | 56 | set_msg_config -id {[Timing 38-164]} -limit 100 57 | set_msg_config -id {[Vivado 12-975]} -limit 100 58 | 59 | foreach c [array names clock_list] { 60 | set clk [get_clocks $c] 61 | if {$clk ne ""} { 62 | set name [regsub {\[[[:digit:]]+\]} $clk {}] 63 | set ila_inst u_ila_$name 64 | set clk_net [get_nets -of_objects [get_pins [get_property SOURCE_PINS $clk]]] 65 | if {$ila_inst eq "u_ila_txoutclk_out_1"} { 66 | break 67 | } 68 | puts " Creating ILA $ila_inst" 69 | ################################################################## 70 | # create ILA and connect its clock 71 | create_debug_core $ila_inst ila >> $logfile 72 | set_property C_DATA_DEPTH 2048 [get_debug_cores $ila_inst] 73 | set_property C_INPUT_PIPE_STAGES 2 [get_debug_cores $ila_inst] 74 | set_property port_width 1 [get_debug_ports $ila_inst/clk] 75 | # CRITICAL WARNING: [Chipscope 16-3] Cannot debug net 'hss0/hss_phy/example_wrapper_inst/DLx_phy_inst/inst/gen_gtwizard_gtye4_top.gtwizard_ultrascale_0_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[6].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[0]'; it is connected with RX/TXOUTCLK pins of GTH/Y cell, which can only drive BUFG_GT load and is not debuggable. 76 | if {$clk_net eq "hss0/hss_phy/example_wrapper_inst/DLx_phy_inst/inst/gen_gtwizard_gtye4_top.gtwizard_ultrascale_0_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[6].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/txoutclk_out[0]"} { 77 | set clk_net cclk_a 78 | } 79 | connect_debug_port $ila_inst/clk $clk_net 80 | ################################################################## 81 | # add probes 82 | set nprobes 0 83 | foreach n [lsort $clock_list($c)] { 84 | puts " Connecting net $n" 85 | set nets {} 86 | if {$max($n) < 0} { 87 | lappend nets [get_nets $n] 88 | } else { 89 | # n is a bus name 90 | for {set i $min($n)} {$i <= $max($n)} {incr i} { 91 | lappend nets [get_nets $n[$i]] 92 | } 93 | } 94 | set prb probe$nprobes 95 | if {$nprobes > 0} { 96 | create_debug_port $ila_inst probe >> $logfile 97 | } 98 | set_property port_width [llength $nets] [get_debug_ports $ila_inst/$prb] 99 | connect_debug_port $ila_inst/$prb $nets >> $logfile 100 | incr nprobes 101 | } 102 | } else { 103 | puts " Cannot find ILA clock" 104 | foreach n [lsort $clock_list($c)] { 105 | puts " Skipping net $n" 106 | } 107 | } 108 | } 109 | } 110 | -------------------------------------------------------------------------------- /build/print_warnings_ice.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | 24 | echo '##############################################################################################' 25 | echo '## Waived errors not found in ice/synthesize.log ############################################' 26 | echo '##############################################################################################' 27 | while read p; do 28 | if ! grep -Fq "$p" ice/synthesize.log; then 29 | echo "$p" | sed -ue 's/^.*$/\x1b[41m&\x1b[m/g' 30 | fi 31 | done < waived_warnings.txt 32 | 33 | declare -a logs=("synthesize.log" "implement_*.log") 34 | 35 | for log_file in "${logs[@]}" 36 | do 37 | echo "##############################################################################################" 38 | echo "## Unwaived errors and warnings in $log_file" 39 | echo "##############################################################################################" 40 | grep "^WARNING: " ice/${log_file} | grep -Fvf waived_warnings.txt | sed -ue 's/^WARNING.*$/\x1b[33m&\x1b[m/g' 41 | grep "^CRITICAL WARNING: " ice/${log_file} | grep -Fvf waived_warnings.txt | sed -ue 's/^CRITICAL WARNING.*$/\x1b[45m&\x1b[m/g' 42 | grep "^ERROR: " ice/${log_file} | sed -ue 's/^ERROR.*$/\x1b[41m&\x1b[m/g' 43 | done 44 | -------------------------------------------------------------------------------- /build/run: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | set -eu 23 | 24 | usage() { 25 | echo "Need to provide design and script to pass to vivado" 26 | echo $0 " " 27 | exit 1 28 | } 29 | 30 | if [[ $# -lt 2 ]] ; then 31 | usage 32 | fi 33 | 34 | # By default we were using 2018.3 but now process has been updated and tested with 2021.2 35 | # Some chips might be stuck on an older version, so override if needed. 36 | #XILINX_VERSION=2018.2 37 | #XILINX_VERSION=2018.3.1 38 | XILINX_VERSION=2021.2 39 | 40 | #---------------------------- 41 | # if TRACE_MODE = yes then vivado will be run in trace mode (to debug script) 42 | # By default all calls to vivado have been called with "-notrace" and results are sent into _script.log 43 | # if DEBUG_MODE = yes then project and associated .xpr file will be created. 44 | # GUI can then be launched calling this .xpr file. 45 | # WARNING: GUI process doesn't follow our scripts directory architecture. 46 | # to view the ip created you can use ./run edit_ip.tcl 47 | export DEBUG_MODE="no" 48 | export TRACE_MODE="no" 49 | #---------------------------- 50 | 51 | #---------------------------- 52 | #-- CONFIGURATION FOR FIRE -- 53 | #---------------------------- 54 | if [[ "$1" == "fire" ]] ; then 55 | # Choose the board 56 | # Choose vcu128 or apollo 57 | export BOARD="vcu128" 58 | # export BOARD="apollo" 59 | 60 | # Choose the frequency 61 | # OMI_FREQ is set to 333 for internal logic at 333MHz and OMI links at 21.33GHz 62 | # OMI_FREQ is set to 400 for internal logic at 400MHz and OMI links at 25.60GHz (still timing closure issues) 63 | export OMI_FREQ="333" 64 | #export OMI_FREQ="400" 65 | 66 | #---------------------------- 67 | #-- CONFIGURATION FOR ICE -- 68 | #---------------------------- 69 | elif [[ "$1" == "ice" ]] ; then 70 | # Choose the board 71 | export BOARD="gemini" 72 | 73 | # Choose the frequency 74 | # OMI_FREQ is set to 333 for internal logic at 333MHz and OMI links at 21.33GHz 75 | # OMI_FREQ is set to 400 for internal logic at 400MHz and OMI links at 25.60GHz (still timing closure issues) 76 | export OMI_FREQ="333" 77 | #export OMI_FREQ="400" 78 | 79 | else 80 | echo "First argument must be 'fire' or 'ice'; was '$1'" 81 | exit 1 82 | fi 83 | 84 | #-------------------------- 85 | if [[ $BOARD == "vcu128" ]] ; then 86 | export XILINX_PART="xcvu37p-fsvh2892-2-e" 87 | export OMI_PORTS="2" 88 | 89 | elif [[ $BOARD == "apollo" ]] ; then 90 | export XILINX_PART="xcvu7p-flvc2104-2-e" 91 | export OMI_PORTS="4" 92 | 93 | elif [[ $BOARD == "gemini" ]] ; then 94 | export XILINX_PART="xczu19eg-ffvc1760-2-i" 95 | export OMI_PORTS="1" 96 | 97 | else 98 | echo " card not recognzed" 99 | exit 1 100 | fi 101 | # Other defined parameters 102 | CWD=$(dirname $(readlink -f $0)) 103 | export XILINX_VERSION=$XILINX_VERSION 104 | export DESIGN="$1" 105 | export TOP_LEVEL="$1""_top" 106 | export BRD_DIR="$CWD/../$DESIGN/src/board/$BOARD" 107 | export SRC_DIR="$CWD/../$DESIGN/src" 108 | export DLX_DIR="$CWD/../$DESIGN/src/dlx" 109 | export OUTPUT_PREFIX="$CWD/$DESIGN" 110 | #-------------------------- 111 | 112 | if [[ -r $2 ]] ; then 113 | # export XILINXD_LICENSE_FILE=insert_license_file_server_here 114 | if ! which vivado 2>/dev/null >/dev/null; then 115 | export PATH=$PATH:/afs/apd/func/vlsi/cte/tools/xilinx/$XILINX_VERSION/Vivado/$XILINX_VERSION/bin 116 | fi 117 | export vivado_major_release=$(vivado -nolog -nojournal -version | grep "Vivado v" | cut -d "." -f1 | tr -d "Vivado ") 118 | export vivado_minor_release=$(vivado -nolog -nojournal -version | grep "Vivado v" | cut -d "." -f2 | cut -d " " -f1) 119 | export vivado_release=$vivado_major_release.$vivado_minor_release 120 | 121 | if ! vivado -nolog -nojournal -version | grep -q "Vivado v${XILINX_VERSION} (64-bit)"; then 122 | echo "Vivado version ${vivado_release} detected while ${XILINX_VERSION} is recommended" 123 | export XILINX_VERSION=${vivado_release} 124 | #exit 125 | fi 126 | 127 | # Output to a log names after the script name and the script args, 128 | # with spaces replaced by '_', to tell all the logs apart. If 129 | # there are no args, delete the last _ so we don't end up with 130 | # synthesize_.log 131 | LOGNAME=$(echo "${2%.*} ${@:3}.log" | sed 's/ /_/g' | sed 's/_\.log/.log/g') 132 | mkdir -p $OUTPUT_PREFIX 133 | 134 | # Color code the different warning levels, and the commented 135 | # commands, as we print to the screen 136 | echo "Launching vivado by sourcing file $2" 137 | # use following command to debug the script 138 | if [[ $TRACE_MODE == "yes" ]] ; then 139 | vivado -mode batch -source $2 -quiet -nolog -nojournal -tclargs ${@:3} 2>&1 | \ 140 | sed -ue 's/^WARNING.*$/\x1b[33m&\x1b[m/g' | \ 141 | sed -ue 's/^INFO.*$/\x1b[34m&\x1b[m/g' | \ 142 | sed -ue 's/^CRITICAL WARNING.*$/\x1b[45m&\x1b[m/g' | \ 143 | sed -ue 's/^#.*$/\x1b[32m&\x1b[m/g' | \ 144 | sed -ue 's/^ERROR.*$/\x1b[41m&\x1b[m/g' | tee $OUTPUT_PREFIX/$LOGNAME 145 | else 146 | vivado -mode batch -source $2 -quiet -notrace -nolog -nojournal -tclargs ${@:3} 2>&1 | \ 147 | sed -ue 's/^WARNING.*$/\x1b[33m&\x1b[m/g' | \ 148 | sed -ue 's/^INFO.*$/\x1b[34m&\x1b[m/g' | \ 149 | sed -ue 's/^CRITICAL WARNING.*$/\x1b[45m&\x1b[m/g' | \ 150 | sed -ue 's/^#.*$/\x1b[32m&\x1b[m/g' | \ 151 | sed -ue 's/^ERROR.*$/\x1b[41m&\x1b[m/g' | tee $OUTPUT_PREFIX/$LOGNAME 152 | fi 153 | # Strip color codes out of the log for reading with an editor 154 | sed -i -r "s/\x1B\[([0-9]{1,2}(;[0-9]{1,2})?)?[m|K]//g" $OUTPUT_PREFIX/$LOGNAME 155 | echo "$2 completed" 156 | else 157 | echo "Cannot find '$2'" 158 | exit 1 159 | fi 160 | -------------------------------------------------------------------------------- /build/run_ice.sh: -------------------------------------------------------------------------------- 1 | ## 2 | ## Copyright 2022 International Business Machines 3 | ## 4 | ## Licensed under the Apache License, Version 2.0 (the "License"); 5 | ## you may not use this file except in compliance with the License. 6 | ## You may obtain a copy of the License at 7 | ## http://www.apache.org/licenses/LICENSE-2.0 8 | ## 9 | ## The patent license granted to you in Section 3 of the License, as applied 10 | ## to the "Work," hereby includes implementations of the Work in physical form. 11 | ## 12 | ## Unless required by applicable law or agreed to in writing, the reference design 13 | ## distributed under the License is distributed on an "AS IS" BASIS, 14 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | ## See the License for the specific language governing permissions and 16 | ## limitations under the License. 17 | ## 18 | ## The background Specification upon which this is based is managed by and available from 19 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | ## 21 | 22 | #================= 23 | DESIGN=ice 24 | STRATEGY_INDEX=17 25 | #================= 26 | START=$(date +%s) 27 | echo "Process starting on $(date)" 28 | 29 | #start by removing impl_$STRATEGY_INDEX directpry so that a synthesis failure will stop the process 30 | echo "Erasing previously built ./$DESIGN/synth_1 directory (if any)." 31 | rm -rf $DESIGN/synth_1 32 | 33 | ./run $DESIGN synthesize.tcl 34 | if [ $(ls .OMI_IPs_$DESIGN* 2>/dev/null | wc -l) -gt 0 ]; then 35 | #echo "file .OMI_IPs_$DESIGN* exists => IP have been created successfully" 36 | if [ $(ls ./$DESIGN/synth_1/post_synth.dcp 2>/dev/null | wc -l) -gt 0 ]; then 37 | #echo "synthesis was succesful" 38 | echo "Erasing previously built ./$DESIGN/impl_$STRATEGY_INDEX directory (if any)." 39 | rm -rf $DESIGN/impl_$STRATEGY_INDEX 40 | ./run $DESIGN implement.tcl $STRATEGY_INDEX 41 | 42 | if [ $(ls ./$DESIGN/impl_$STRATEGY_INDEX/post_route.dcp 2>/dev/null | wc -l) -gt 0 ]; then 43 | ./run $DESIGN gen_bitstream.tcl $STRATEGY_INDEX 44 | else 45 | echo "Errors during implementation Please check ERRORS in ./$DESIGN/implement_script.log" 46 | exit 47 | fi 48 | else 49 | echo "Errors during synthesis. Please check ERRORS in ./$DESIGN/synthesize_script.log" 50 | exit 51 | fi 52 | else 53 | echo "No .OMI_IPs_$DESIGN* file, erasing incomplete ../ip_created_for_$DESIGN directory!" 54 | echo "Errors during IP creation. Please check ERRORS in ./$DESIGN/create_ip.log" 55 | rm -rf ../ip_created_for_$DESIGN dir 56 | exit 57 | fi 58 | 59 | #grep -A2 -m1 WNS $DESIGN/impl_$STRATEGY_INDEX/post_route_timing_summary.rpt 60 | WNS_info=$(grep -A2 -m1 WNS $DESIGN/impl_$STRATEGY_INDEX/post_route_timing_summary.rpt| head -3 | tail -1 | awk '{print $1;}') 61 | echo "======================" 62 | echo "WNS_info is: $WNS_info" 63 | 64 | complete_path=$(find * -name "$DESIGN.bit") 65 | path=$(dirname $complete_path) 66 | file_ext=$(basename $complete_path) # get the filename from the complete path to rename it 67 | file=`echo "$file_ext" | cut -d'.' -f1` # Removing file extension 68 | #echo " ./$path/${file}.*" 69 | pref=$(ls .OMI_IPs_$DESIGN*) 70 | prefix="${pref:9}" # Removing ".OMI_IPs_" from name 71 | git_version=$(git log --oneline | awk '{print $1;}'|head -n 1) # get 1st word of 1st line containing short git version 72 | newfilename=${prefix}_${git_version}_${WNS_info} 73 | mv $path/$file.bit $path/$newfilename.bit 74 | mv $path/$file.ltx $path/$newfilename.ltx 75 | echo "======================" 76 | echo "= bitstream file for this run is available at:" 77 | echo "= $path/$newfilename.bit (and .ltx for probes)" 78 | #ls -al $DESIGN 79 | echo "= All bistreams available for $DESIGN are now at:" 80 | find * -name '*.bit'|grep $DESIGN 81 | echo "======================" 82 | echo "Suggested command: run ./print_warnings_$DESIGN.sh" 83 | END=$(date +%s) 84 | echo "Process ended on $(date)" 85 | echo -n "Process took " 86 | echo $((END-START)) | awk '{printf "%d hrs %02d mins %02d secs", $1/3600, ($1/60)%60, $1%60}' 87 | echo "" 88 | 89 | -------------------------------------------------------------------------------- /build/waived_warnings.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenCAPI/omi_device_ice/34311b44c8158a4313999e92e975a26f2851f202/build/waived_warnings.txt -------------------------------------------------------------------------------- /build/write_git_meta.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | 24 | # This script auto-generates registers to capture the git version in 25 | # VHDL and Verilog designs. This is primarily useful to compare 26 | # generated HW with a specific source. 27 | 28 | set -eu 29 | 30 | # cd to the directory containing this script 31 | cd $(dirname "$(readlink -f "$0")") 32 | 33 | # Grab 28 bits of hash 34 | SHORT_HASH=$(git rev-parse --short=7 HEAD) 35 | echo -n " Writing meta files for commit ${SHORT_HASH}" 36 | 37 | # Check if there are any modified or staged files 38 | if ! git diff-index --quiet HEAD --; then 39 | DIRTY=1 40 | echo -n "-dirty" 41 | else 42 | DIRTY=0 43 | #echo # Complete newline 44 | fi 45 | 46 | # Meta Version Register: 47 | # BIT 31:29 = was Reserved but are now defined to enter frequency into design code 48 | # Bit 31:29 = 001=21.33GBPS - 010=23.46GBPS - 011=25.6GBPS 49 | # - 000 + 100 to 111=unsupported 50 | # Bit 28 = dirty (1 if repository has untracked or staged changes, 0 otherwise) 51 | # Bits 27:0 = 7 character git hash 52 | echo " for frequency ${OMI_FREQ} MHz" 53 | if [ ${OMI_FREQ} -eq 333 ]; then 54 | #Bit 31:29 = 001=21.33GBPS > SPEED_FIELD=2 (1 <<1) 55 | SPEED_FIELD=2 56 | else 57 | #Bit 31:29 = 011=25.6GBPS > SPEED_FIELD=6 (4 <<1) 58 | SPEED_FIELD=6 59 | fi 60 | DIRTY_FIELD=${SPEED_FIELD}+${DIRTY} 61 | QUALIFIER_FIELD=$(printf "%x" $((DIRTY_FIELD * 1))) 62 | META_REGISTER_VALUE="${QUALIFIER_FIELD}${SHORT_HASH}" 63 | 64 | META_REGISTER_VERILOG_DEFINE="\`define FIRE_ICE_META_VERSION 32'h${META_REGISTER_VALUE}" 65 | #echo 66 | #echo "Adding in # VERILOG" 67 | #echo "${META_REGISTER_VERILOG_DEFINE}" 68 | 69 | read -r -d '' META_REGISTER_VHDL_CONSTANT< $file 91 | echo "${META_REGISTER_VHDL_CONSTANT}" >> $file 92 | echo " Updated ${file}" 93 | done 94 | 95 | -------------------------------------------------------------------------------- /ice/doc/ICE_workbook_openPower.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenCAPI/omi_device_ice/34311b44c8158a4313999e92e975a26f2851f202/ice/doc/ICE_workbook_openPower.odt -------------------------------------------------------------------------------- /ice/src/csv/custom_parts_ddr4_mt_x8_16Gb_2133mhz.csv: -------------------------------------------------------------------------------- 1 | Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length 2 | Components,DDR4_CUSTOM,2,1,0,1,17,16,10,2,2,2,2,2,1,93,16Gb,8Gb,8,8,8,1.2V,72,938,1600,5000 ps,21000 ps,0,8 tck,33000 ps,15000 ps,7800000 ps,350000 ps,0,15000 ps,3700 ps,5300 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,16,11,8 3 | UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8 4 | SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8 5 | RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8 6 | RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8 7 | RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8 8 | LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8 -------------------------------------------------------------------------------- /ice/src/dlx/ocx_bram_infer.v: -------------------------------------------------------------------------------- 1 | // *!*************************************************************************** 2 | // *! Copyright 2019 International Business Machines 3 | // *! 4 | // *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | // *! you may not use this file except in compliance with the License. 6 | // *! You may obtain a copy of the License at 7 | // *! http://www.apache.org/licenses/LICENSE-2.0 8 | // *! 9 | // *! The patent license granted to you in Section 3 of the License, as applied 10 | // *! to the "Work," hereby includes implementations of the Work in physical form. 11 | // *! 12 | // *! Unless required by applicable law or agreed to in writing, the reference design 13 | // *! distributed under the License is distributed on an "AS IS" BASIS, 14 | // *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // *! See the License for the specific language governing permissions and 16 | // *! limitations under the License. 17 | // *! 18 | // *! The background Specification upon which this is based is managed by and available from 19 | // *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | // *!*************************************************************************** 21 | 22 | `timescale 1ns / 1ps 23 | 24 | 25 | module ocx_bram_infer( 26 | input clka, 27 | input clkb, 28 | input ena, 29 | input enb, 30 | input wea, 31 | input rstb, 32 | //input regceb, 33 | input [6:0] addra, 34 | input [6:0] addrb, 35 | input [512-1:0] dina, 36 | output [512-1:0] doutb, 37 | output sbiterr, 38 | output dbiterr, 39 | output wire [6:0] rdaddrecc 40 | ); 41 | 42 | (* ram_style="block" *) 43 | // wizard generated memory has 2 clocks, use clka for both ports 44 | wire clk; 45 | assign clk = clka; 46 | //wire rstb; 47 | wire regceb; 48 | //assign rstb = 1'b0; 49 | assign regceb = 1'b1; 50 | assign sbiterr = 1'b0; 51 | assign dbiterr = 1'b0; 52 | assign rdaddrecc = {7{1'b0}}; 53 | 54 | // Xilinx Simple Dual Port Single Clock RAM 55 | // This code implements a parameterizable SDP single clock memory. 56 | // If a reset or enable is not necessary, it may be tied off or removed from the code. 57 | 58 | parameter RAM_WIDTH = 512; // Specify RAM data width 59 | parameter RAM_DEPTH = 128; 60 | parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE"; // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 61 | parameter INIT_FILE = ""; // Specify name/location of RAM initialization file if using one (leave blank if not) 62 | 63 | reg [RAM_WIDTH-1:0] ram_sdp [RAM_DEPTH-1:0]; 64 | reg [RAM_WIDTH-1:0] ram_sdp_data = {RAM_WIDTH{1'b0}}; 65 | 66 | // The following code either initializes the memory values to a specified file or to all zeros to match hardware 67 | generate 68 | if (INIT_FILE != "") begin: use_init_file 69 | initial 70 | $readmemh(INIT_FILE, ram_sdp, 0, RAM_DEPTH-1); 71 | end else begin: init_bram_to_zero 72 | integer ram_index; 73 | initial 74 | for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1) 75 | ram_sdp[ram_index] = {RAM_WIDTH{1'b0}}; 76 | end 77 | endgenerate 78 | 79 | always @(posedge clk) begin 80 | if (wea) 81 | ram_sdp[addra] <= dina; 82 | if (enb) 83 | ram_sdp_data <= ram_sdp[addrb]; 84 | end 85 | 86 | // The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register) 87 | generate 88 | if (RAM_PERFORMANCE == "LOW______LATENCY") begin: no_output_register 89 | 90 | // The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing 91 | assign doutb = ram_sdp_data; 92 | 93 | end else begin: output_register 94 | 95 | // The following is a 2 clock cycle read latency with improve clock-to-out timing 96 | 97 | reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}}; 98 | 99 | always @(posedge clk) 100 | if (rstb) 101 | doutb_reg <= {RAM_WIDTH{1'b0}}; 102 | else if (regceb) 103 | doutb_reg <= ram_sdp_data; 104 | 105 | assign doutb = doutb_reg; 106 | 107 | end 108 | endgenerate 109 | 110 | // The following function calculates the address width based on specified RAM depth 111 | function integer clogb2; 112 | input integer depth; 113 | for (clogb2=0; depth>0; clogb2=clogb2+1) 114 | depth = depth >> 1; 115 | endfunction 116 | 117 | 118 | endmodule 119 | -------------------------------------------------------------------------------- /ice/src/dlx/ocx_dlx_tx_que.v: -------------------------------------------------------------------------------- 1 | // *!*************************************************************************** 2 | // *! Copyright 2019 International Business Machines 3 | // *! 4 | // *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | // *! you may not use this file except in compliance with the License. 6 | // *! You may obtain a copy of the License at 7 | // *! http://www.apache.org/licenses/LICENSE-2.0 8 | // *! 9 | // *! The patent license granted to you in Section 3 of the License, as applied 10 | // *! to the "Work," hereby includes implementations of the Work in physical form. 11 | // *! 12 | // *! Unless required by applicable law or agreed to in writing, the reference design 13 | // *! distributed under the License is distributed on an "AS IS" BASIS, 14 | // *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // *! See the License for the specific language governing permissions and 16 | // *! limitations under the License. 17 | // *! 18 | // *! The background Specification upon which this is based is managed by and available from 19 | // *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | // *!*************************************************************************** 21 | 22 | `timescale 1ns / 1ps 23 | 24 | 25 | module ocx_dlx_tx_que ( 26 | 27 | ctl_que_lane // -- < input [2:0] 28 | 29 | ,ctl_que_reset // -- < input // ---- run and valid need to be set to get clock gating to work when reset is active. 30 | ,ctl_que_stall // -- < input // ---- run and valid need to be set to get clock gating to work when reset is active. 31 | 32 | ,flt_que_data // -- < input [63:0] 33 | 34 | ,ctl_que_use_neighbor // -- < input 35 | ,neighbor1_in_data // -- < input [63:0] 36 | ,neighbor2_in_data // -- < input [63:0] 37 | ,neighbor3_in_data // -- < input [63:0] 38 | ,neighbor_out_data // -- > output [63:0] 39 | 40 | // ---- training signals 41 | ,ctl_que_tx_ts0 // -- < input // ---- control header with all zero data. 42 | ,ctl_que_tx_ts1 // -- < input 43 | ,ctl_que_tx_ts2 // -- < input 44 | ,ctl_que_tx_ts3 // -- < input 45 | ,ctl_que_good_lanes // -- < input [15:0] 46 | ,ctl_que_deskew // -- < input [23:0] 47 | ,ctl_que_lane_scrambler // -- < input [63:0] 48 | 49 | ,que_gb_data // -- > output [63:0] 50 | ,que_gb_odd // -- > output 51 | 52 | //-- ,gnd // -- <> inout 53 | //-- ,vdn // -- <> inout 54 | ,dlx_clk // -- < input 55 | ); 56 | 57 | input [2:0] ctl_que_lane; 58 | 59 | input ctl_que_reset; 60 | input ctl_que_stall; 61 | 62 | input [63:0] flt_que_data; 63 | 64 | output [63:0] que_gb_data; 65 | output que_gb_odd; 66 | 67 | input [3:1] ctl_que_use_neighbor; 68 | input [63:0] neighbor1_in_data; 69 | input [63:0] neighbor2_in_data; 70 | input [63:0] neighbor3_in_data; 71 | output [63:0] neighbor_out_data; 72 | 73 | // ---- traing signals 74 | input ctl_que_tx_ts0; 75 | input ctl_que_tx_ts1; 76 | input ctl_que_tx_ts2; 77 | input ctl_que_tx_ts3; 78 | input [15:0] ctl_que_good_lanes; 79 | input [23:0] ctl_que_deskew; 80 | input [63:0] ctl_que_lane_scrambler; 81 | 82 | input dlx_clk; 83 | //-- inout gnd; 84 | 85 | //-- (* GROUND_PIN="1" *) 86 | //-- wire gnd; 87 | 88 | //-- inout vdn; 89 | //-- (* POWER_PIN="1" *) 90 | //-- wire vdn; 91 | 92 | function [7:0] reverse8 (input [7:0] forward); 93 | integer i; 94 | for (i=0; i<=7; i=i+1) 95 | reverse8[7-i] = forward[i]; 96 | endfunction 97 | // -- begin logic here 98 | wire [63:0] dl_train_pattern; 99 | wire [63:0] dl_train_pattern_rev; 100 | wire [63:0] next_data; 101 | wire [4:0] ts_count_din; 102 | reg [4:0] ts_count_q; 103 | wire dl_training; 104 | wire tp_deskew; // -- training pattern of deskew 105 | 106 | assign ts_count_din[4:0] = ctl_que_reset ? 5'b00000 : //-- reset training count to zero when the link is reset 107 | ctl_que_stall ? ts_count_q[4:0] : //-- stall counter when gearbox needs to catch up 108 | ts_count_q[4:0] + 5'b00001 ; 109 | 110 | assign tp_deskew = ts_count_q[4:0] == 5'b11111; //-- send deskew pattern every 32 training set patterns 111 | 112 | 113 | assign dl_train_pattern[63:0] = tp_deskew ? {40'h4B1E1E1E1E, ctl_que_deskew[23:5], 2'b00, ctl_que_lane[2:0]} : // -- deskew pattern 114 | ctl_que_tx_ts1 ? 64'h4B4A4A4A4A4A4A4A : // -- TS1 pattern 115 | ctl_que_tx_ts2 ? {48'h4B4545454545, ctl_que_good_lanes[15:0]} : // -- TS2 pattern 116 | ctl_que_tx_ts3 ? {48'h4B4141414141, ctl_que_good_lanes[15:0]} : // -- TS3 pattern 117 | 64'h0000000000000000 ; 118 | 119 | assign dl_train_pattern_rev[63:0] = {dl_train_pattern[7:0] ,dl_train_pattern[15:8] ,dl_train_pattern[23:16],dl_train_pattern[31:24], 120 | dl_train_pattern[39:32],dl_train_pattern[47:40],dl_train_pattern[55:48],dl_train_pattern[63:56]}; 121 | 122 | assign next_data[63:0] = dl_training ? dl_train_pattern_rev[63:0] : //-- training patterns 123 | ctl_que_use_neighbor[1]? neighbor1_in_data[63:0] : //-- x4 degradation mode -- steal from neighbors location 124 | ctl_que_use_neighbor[2]? neighbor2_in_data[63:0] : // -- x2 degradation mode -- steal from further neighbors 125 | ctl_que_use_neighbor[3]? neighbor3_in_data[63:0] : // -- x2 degradation mode -- steal from further neighbors 126 | flt_que_data[63:0]; 127 | 128 | assign dl_training = ctl_que_tx_ts1 | ctl_que_tx_ts2 | ctl_que_tx_ts3 | ctl_que_tx_ts0; 129 | 130 | assign neighbor_out_data[63:0] = flt_que_data[63:0]; 131 | 132 | assign que_gb_data[63:0] = {reverse8(next_data[ 7: 0]), 133 | reverse8(next_data[15: 8]), 134 | reverse8(next_data[23:16]), 135 | reverse8(next_data[31:24]), 136 | reverse8(next_data[39:32]), 137 | reverse8(next_data[47:40]), 138 | reverse8(next_data[55:48]), 139 | reverse8(next_data[63:56])} ^ ctl_que_lane_scrambler[63:0]; //-- reverse each byte and then scramble 140 | 141 | assign que_gb_odd = ^next_data[63:0]; 142 | 143 | always @(posedge (dlx_clk)) begin 144 | ts_count_q[4:0] <= ts_count_din[4:0]; 145 | end 146 | 147 | endmodule // -- ocx_dlx_tx_que 148 | -------------------------------------------------------------------------------- /ice/src/verilog/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenCAPI/omi_device_ice/34311b44c8158a4313999e92e975a26f2851f202/ice/src/verilog/.gitkeep -------------------------------------------------------------------------------- /ice/src/verilog/ice_tlx_6x16_fifo.v: -------------------------------------------------------------------------------- 1 | // *!*************************************************************************** 2 | // *! Copyright 2019 International Business Machines 3 | // *! 4 | // *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | // *! you may not use this file except in compliance with the License. 6 | // *! You may obtain a copy of the License at 7 | // *! http://www.apache.org/licenses/LICENSE-2.0 8 | // *! 9 | // *! The patent license granted to you in Section 3 of the License, as applied 10 | // *! to the "Work," hereby includes implementations of the Work in physical form. 11 | // *! 12 | // *! Unless required by applicable law or agreed to in writing, the reference design 13 | // *! distributed under the License is distributed on an "AS IS" BASIS, 14 | // *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // *! See the License for the specific language governing permissions and 16 | // *! limitations under the License. 17 | // *! 18 | // *! The background Specification upon which this is based is managed by and available from 19 | // *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | // *!*************************************************************************** 21 | 22 | 23 | 24 | `timescale 1ns / 10ps 25 | `define IBM_SIM 26 | 27 | 28 | module ice_tlx_6x16_fifo 29 | ( 30 | // ----------------------------------- 31 | // Miscellaneous Ports 32 | // ----------------------------------- 33 | data_in , 34 | wr_enable , 35 | data_out , 36 | rd_done , 37 | use_min_fifo_depth , 38 | 39 | data_look_ahead , 40 | data_available , 41 | underflow_error , 42 | overflow_error , 43 | 44 | clock , 45 | reset_n 46 | ) ; 47 | 48 | 49 | // ============================================================================================================================== 50 | // @@@ Parameters (These can be overwritten by module instatiation.) 51 | // ============================================================================================================================== 52 | 53 | 54 | // ============================================================================================================================== 55 | // @@@ Port Declarations 56 | // ============================================================================================================================== 57 | 58 | // ----------------------------------- 59 | // Miscellaneous Ports 60 | // ----------------------------------- 61 | input [5:0] data_in ; 62 | input wr_enable ; 63 | output [5:0] data_out ; 64 | input rd_done ; 65 | input use_min_fifo_depth ; 66 | 67 | output data_look_ahead ; 68 | output data_available ; 69 | output underflow_error ; 70 | output overflow_error ; 71 | 72 | input clock ; 73 | input reset_n ; 74 | 75 | 76 | // ============================================================================================================================== 77 | // @@@ Wires and Variables (Regs) 78 | // ============================================================================================================================== 79 | 80 | wire [4:0] ram_wr_addr ; 81 | wire [4:0] ram_rd_addr ; 82 | wire ram_wr_enable ; 83 | wire rd_data_capture ; 84 | 85 | 86 | // ============================================================================================================================== 87 | // @@@ DistributedRAM Inferrence and Instantiation 88 | // ============================================================================================================================== 89 | `ifdef IBM_SIM 90 | // ---------------- 91 | // INFERRED REGFILE 92 | // ---------------- 93 | // RAM Inferrence (To work with IBM cycle simulators.) 94 | ocx_leaf_inferd_regfile # ( 95 | 96 | // Parameters (Can be used to overwrite the lower-level file.) 97 | .REGFILE_DEPTH (32), //positive integer 98 | .REGFILE_WIDTH (6), //positive integer 99 | .ADDR_WIDTH (5) //positive integer 100 | 101 | ) fifo_memory_inst ( 102 | 103 | // Port A module ports (This is a WRITE-ONLY port.) 104 | .clka ( clock ), 105 | .ena ( ram_wr_enable ), 106 | .addra ( ram_wr_addr ), 107 | .dina ( data_in ), 108 | 109 | // Port B module ports (This is a READ-ONLY port.) 110 | .clkb ( clock ), 111 | .rstb_n ( reset_n ), 112 | .enb ( rd_data_capture ), 113 | .addrb ( ram_rd_addr ), 114 | .doutb ( data_out ) 115 | ); // End of inferred regfile instance 116 | 117 | `else 118 | // --------------------- 119 | // INSTANTIATED DIST-RAM 120 | // --------------------- 121 | // Xilinx Distributed RAM Instantiation 122 | // xpm_memory_dpdistram: Dual Port distributed RAM 123 | // Xilinx Parameterized Macro, Version 2016.2 124 | xpm_memory_dpdistram # ( 125 | 126 | // Common module parameters 127 | .MEMORY_SIZE (128), //positive integer 128 | .CLOCKING_MODE ("common_clock"), //string; "common_clock", "independent_clock" 129 | .MEMORY_INIT_FILE ("none"), //string; "none" or ".mem" 130 | .MEMORY_INIT_PARAM ("" ), //string; 131 | .USE_MEM_INIT (1), //integer; 0,1 132 | .MESSAGE_CONTROL (0), //integer; 0,1 133 | 134 | // Port A module parameters 135 | .WRITE_DATA_WIDTH_A (6), //positive integer 136 | .READ_DATA_WIDTH_A (6), //positive integer 137 | .BYTE_WRITE_WIDTH_A (6), //integer; 8, 9, or WRITE_DATA_WIDTH_A value 138 | .ADDR_WIDTH_A (5), //positive integer 139 | .READ_reset_n_VALUE_A ("0"), //string 140 | .READ_LATENCY_A (0), //non-negative integer 141 | 142 | // Port B module parameters 143 | .READ_DATA_WIDTH_B (6), //positive integer 144 | .ADDR_WIDTH_B (5), //positive integer 145 | .READ_reset_n_VALUE_B ("0"), //string 146 | .READ_LATENCY_B (1) //non-negative integer 147 | 148 | ) fifo_memory_inst ( 149 | 150 | // Port A module ports 151 | .clka ( clock ), 152 | .rsta ( reset_n ), 153 | .ena ( ram_wr_enable ), 154 | .regcea ( 1'b1 ), 155 | .wea ( ram_wr_enable ), 156 | .addra ( ram_wr_addr ), 157 | .dina ( data_in ), 158 | .douta ( douta ), 159 | 160 | // Port B module ports 161 | .clkb ( clock ), 162 | .rstb ( reset_n ), 163 | .enb ( rd_data_capture ), 164 | .regceb ( 1'b1 ), 165 | .addrb ( ram_rd_addr ), 166 | .doutb ( data_out ) 167 | ); // End of xpm_memory_dpdistram instance declaration 168 | `endif 169 | 170 | 171 | // ============================================================================================================================== 172 | // @@@ FIFO Controller Instantiation 173 | // ============================================================================================================================== 174 | ocx_tlx_fifo_cntlr 175 | #( 176 | // Note: The FIFO will be *built* using the size specified by these parameters (or as overwritten by instantiation.) 177 | .FIFO_ADDR_WIDTH ( 5 ) 178 | ) 179 | FIFO_CNTLR 180 | ( 181 | // ----------------------------------- 182 | // Miscellaneous Ports 183 | // ----------------------------------- 184 | .fifo_wr ( wr_enable ) , 185 | .fifo_rd_done ( rd_done ) , 186 | 187 | .ram_wr_addr ( ram_wr_addr ) , // [FIFO_ADDR_WIDTH-1:0] 188 | .ram_wr_enable ( ram_wr_enable ) , 189 | .ram_rd_addr ( ram_rd_addr ) , // [FIFO_ADDR_WIDTH-1:0] 190 | .rd_data_capture ( rd_data_capture ) , 191 | 192 | .fifo_data_look_ahead ( data_look_ahead ) , 193 | .fifo_data_available ( data_available ) , 194 | .fifo_underflow_error ( underflow_error ) , 195 | .fifo_overflow_error ( overflow_error ) , 196 | 197 | .clock ( clock ) , 198 | .reset_n ( reset_n ) 199 | ) ; 200 | 201 | 202 | endmodule // ocx_tlx_6x16_fifo 203 | -------------------------------------------------------------------------------- /ice/src/verilog/iram_1r1w1ck_64x112.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // RAM (BRAM) with 1 read port one write port and one clock 3 | // Intended for synthesis to xilinx BRAM (especially if big) 4 | // From: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf 5 | // page 104 "Simple Dual-Port Block RAM with Single Clock Verilog Coding Example" 6 | 7 | module iram_1r1w1ck_64x112 8 | (clk,ena,enb,wea,addra,addrb,dia,dob); 9 | input clk,ena,enb,wea; 10 | input [5:0] addra,addrb; 11 | input [111:0] dia; 12 | output [111:0] dob; 13 | reg[111:0] ram [63:0]; 14 | reg[111:0] dob; 15 | 16 | always @(posedge clk) begin 17 | if (ena) begin 18 | if (wea) 19 | ram[addra] <= dia; 20 | end 21 | end 22 | 23 | always @(posedge clk) begin 24 | if (enb) 25 | dob <= ram[addrb]; 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /ice/src/verilog/iram_1r1w1ck_64x16.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // RAM (BRAM) with 1 read port one write port and one clock 3 | // Intended for synthesis to xilinx BRAM (especially if big) 4 | // From: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf 5 | // page 104 "Simple Dual-Port Block RAM with Single Clock Verilog Coding Example" 6 | 7 | module iram_1r1w1ck_64x16 8 | (clk,ena,enb,wea,addra,addrb,dia,dob); 9 | input clk,ena,enb,wea; 10 | input [5:0] addra,addrb; 11 | input [15:0] dia; 12 | output [15:0] dob; 13 | reg[15:0] ram [63:0]; 14 | reg[15:0] dob; 15 | 16 | always @(posedge clk) begin 17 | if (ena) begin 18 | if (wea) 19 | ram[addra] <= dia; 20 | end 21 | end 22 | 23 | always @(posedge clk) begin 24 | if (enb) 25 | dob <= ram[addrb]; 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /ice/src/verilog/iram_1r1w1ck_64x32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // RAM (BRAM) with 1 read port one write port and one clock 3 | // Intended for synthesis to xilinx BRAM (especially if big) 4 | // From: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf 5 | // page 104 "Simple Dual-Port Block RAM with Single Clock Verilog Coding Example" 6 | 7 | module iram_1r1w1ck_64x32 8 | (clk,ena,enb,wea,addra,addrb,dia,dob); 9 | input clk,ena,enb,wea; 10 | input [5:0] addra,addrb; 11 | input [31:0] dia; 12 | output [31:0] dob; 13 | reg[31:0] ram [63:0]; 14 | reg[31:0] dob; 15 | 16 | always @(posedge clk) begin 17 | if (ena) begin 18 | if (wea) 19 | ram[addra] <= dia; 20 | end 21 | end 22 | 23 | always @(posedge clk) begin 24 | if (enb) 25 | dob <= ram[addrb]; 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /ice/src/verilog/iram_1r1w1ck_64x518.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // RAM (BRAM) with 1 read port one write port and one clock 3 | // Intended for synthesis to xilinx BRAM (especially if big) 4 | // From: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf 5 | // page 104 "Simple Dual-Port Block RAM with Single Clock Verilog Coding Example" 6 | 7 | module iram_1r1w1ck_64x518 8 | (clk,ena,enb,wea,addra,addrb,dia,dob); 9 | input clk,ena,enb,wea; 10 | input [5:0] addra,addrb; 11 | input [517:0] dia; 12 | output [517:0] dob; 13 | reg[517:0] ram [63:0]; 14 | reg[517:0] dob; 15 | 16 | always @(posedge clk) begin 17 | if (ena) begin 18 | if (wea) 19 | ram[addra] <= dia; 20 | end 21 | end 22 | 23 | always @(posedge clk) begin 24 | if (enb) 25 | dob <= ram[addrb]; 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /ice/src/verilog/iram_1r1w1ck_64x519.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // RAM (BRAM) with 1 read port one write port and one clock 3 | // Intended for synthesis to xilinx BRAM (especially if big) 4 | // From: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf 5 | // page 104 "Simple Dual-Port Block RAM with Single Clock Verilog Coding Example" 6 | 7 | module iram_1r1w1ck_64x519 8 | (clk,ena,enb,wea,addra,addrb,dia,dob); 9 | input clk,ena,enb,wea; 10 | input [5:0] addra,addrb; 11 | input [518:0] dia; 12 | output [518:0] dob; 13 | reg[518:0] ram [63:0]; 14 | reg[518:0] dob; 15 | 16 | always @(posedge clk) begin 17 | if (ena) begin 18 | if (wea) 19 | ram[addra] <= dia; 20 | end 21 | end 22 | 23 | always @(posedge clk) begin 24 | if (enb) 25 | dob <= ram[addrb]; 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /ice/src/verilog/iram_1r1w1ck_64x85.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // RAM (BRAM) with 1 read port one write port and one clock 3 | // Intended for synthesis to xilinx BRAM (especially if big) 4 | // From: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf 5 | // page 104 "Simple Dual-Port Block RAM with Single Clock Verilog Coding Example" 6 | 7 | module iram_1r1w1ck_64x85 8 | (clk,ena,enb,wea,addra,addrb,dia,dob); 9 | input clk,ena,enb,wea; 10 | input [5:0] addra,addrb; 11 | input [84:0] dia; 12 | output [84:0] dob; 13 | reg[84:0] ram [63:0]; 14 | reg[84:0] dob; 15 | 16 | always @(posedge clk) begin 17 | if (ena) begin 18 | if (wea) 19 | ram[addra] <= dia; 20 | end 21 | end 22 | 23 | always @(posedge clk) begin 24 | if (enb) 25 | dob <= ram[addrb]; 26 | end 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /ice/src/verilog/ocx_leaf_inferd_regfile.v: -------------------------------------------------------------------------------- 1 | // *!*************************************************************************** 2 | // *! Copyright 2019 International Business Machines 3 | // *! 4 | // *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | // *! you may not use this file except in compliance with the License. 6 | // *! You may obtain a copy of the License at 7 | // *! http://www.apache.org/licenses/LICENSE-2.0 8 | // *! 9 | // *! The patent license granted to you in Section 3 of the License, as applied 10 | // *! to the "Work," hereby includes implementations of the Work in physical form. 11 | // *! 12 | // *! Unless required by applicable law or agreed to in writing, the reference design 13 | // *! distributed under the License is distributed on an "AS IS" BASIS, 14 | // *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // *! See the License for the specific language governing permissions and 16 | // *! limitations under the License. 17 | // *! 18 | // *! The background Specification upon which this is based is managed by and available from 19 | // *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | // *!*************************************************************************** 21 | 22 | 23 | 24 | `timescale 1ns / 10ps 25 | 26 | module ocx_leaf_inferd_regfile 27 | ( 28 | // Port A module ports (This is a WRITE-ONLY port.) 29 | clka , 30 | ena , 31 | addra , 32 | dina , 33 | 34 | // Port B module ports (This is a READ-ONLY port.) 35 | clkb , 36 | rstb_n , 37 | enb , 38 | addrb , 39 | doutb 40 | ) ; 41 | 42 | 43 | // ============================================================================================================================== 44 | // @@@ Parameters (These can be overwritten by module instatiation.) 45 | // ============================================================================================================================== 46 | 47 | parameter REGFILE_DEPTH = 16 ; //positive integer 48 | parameter REGFILE_WIDTH = 576 ; //positive integer 49 | parameter ADDR_WIDTH = 4 ; //positive integer 50 | 51 | 52 | // ============================================================================================================================== 53 | // @@@ Port Declarations 54 | // ============================================================================================================================== 55 | 56 | // Port A module ports (This is a WRITE-ONLY port.) 57 | input clka ; 58 | input ena ; 59 | input [ADDR_WIDTH-1:0] addra ; 60 | input [REGFILE_WIDTH-1:0] dina ; 61 | 62 | // Port B module ports (This is a READ-ONLY port.) 63 | input clkb ; 64 | input rstb_n ; 65 | input enb ; 66 | input [ADDR_WIDTH-1:0] addrb ; 67 | output [REGFILE_WIDTH-1:0] doutb ; 68 | 69 | 70 | 71 | // ============================================================================================================================== 72 | // @@@ Wires and Variables (Regs) 73 | // ============================================================================================================================== 74 | 75 | (* RAM_STYLE="DISTRIBUTED" *) 76 | reg [REGFILE_WIDTH-1:0] regfile [REGFILE_DEPTH-1:0] ; 77 | reg [REGFILE_WIDTH-1:0] output_reg ; 78 | 79 | 80 | // ============================================================================================================================== 81 | // @@@ ocx_leaf_inferd_regfile Logic 82 | // ============================================================================================================================== 83 | 84 | // Regfile memory array 85 | always @ (posedge clka) begin 86 | if(ena) begin regfile[addra] <= dina; end 87 | end 88 | 89 | // Output register 90 | always @ (posedge clkb) begin 91 | if (!rstb_n) begin output_reg <= {REGFILE_WIDTH{1'b0}}; end 92 | else if (enb) begin output_reg <= regfile[addrb]; end 93 | end 94 | 95 | assign doutb = output_reg ; 96 | 97 | 98 | endmodule // ocx_leaf_inferd_regfile 99 | -------------------------------------------------------------------------------- /ice/src/verilog/ocx_tlx_framer_rsp_fifo.v: -------------------------------------------------------------------------------- 1 | // *!*************************************************************************** 2 | // *! Copyright 2019 International Business Machines 3 | // *! 4 | // *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | // *! you may not use this file except in compliance with the License. 6 | // *! You may obtain a copy of the License at 7 | // *! http://www.apache.org/licenses/LICENSE-2.0 8 | // *! 9 | // *! The patent license granted to you in Section 3 of the License, as applied 10 | // *! to the "Work," hereby includes implementations of the Work in physical form. 11 | // *! 12 | // *! Unless required by applicable law or agreed to in writing, the reference design 13 | // *! distributed under the License is distributed on an "AS IS" BASIS, 14 | // *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // *! See the License for the specific language governing permissions and 16 | // *! limitations under the License. 17 | // *! 18 | // *! The background Specification upon which this is based is managed by and available from 19 | // *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | // *!*************************************************************************** 21 | 22 | 23 | 24 | `timescale 1ns / 10ps 25 | 26 | module ocx_tlx_framer_rsp_fifo 27 | ( 28 | data_in , 29 | wr_enable , 30 | data_out , 31 | rd_done , 32 | 33 | data_available , 34 | valid_entry_count , 35 | underflow_error , 36 | overflow_error , 37 | 38 | clock , 39 | reset_n 40 | ) ; 41 | 42 | 43 | // ============================================================================================================================== 44 | // @@@ Parameters (These can be overwritten by module instatiation.) 45 | // ============================================================================================================================== 46 | 47 | // Note: The FIFO will be *built* using the size specified by these parameters (or as overwritten by instantiation.) 48 | parameter REGFILE_DEPTH = 32 ; //positive integer 49 | parameter REGFILE_WIDTH = 59 ; //positive integer 50 | parameter FIFO_ADDR_WIDTH = 5 ; 51 | parameter PTR_INC = 5'b00001 ; 52 | parameter CNTR_0 = 6'b000000 ; 53 | parameter CNTR_1 = 6'b000001 ; 54 | parameter CNTR_MAX = 6'b100000 ; 55 | 56 | 57 | // ============================================================================================================================== 58 | // @@@ Port Declarations 59 | // ============================================================================================================================== 60 | 61 | input [ 58:0] data_in ; 62 | input wr_enable ; 63 | output [ 58:0] data_out ; 64 | input rd_done ; 65 | 66 | output data_available ; 67 | output [FIFO_ADDR_WIDTH :0] valid_entry_count ; 68 | output underflow_error ; 69 | output overflow_error ; 70 | 71 | input clock ; 72 | input reset_n ; 73 | 74 | 75 | // ============================================================================================================================== 76 | // @@@ Wires and Variables (Regs) 77 | // ============================================================================================================================== 78 | 79 | (* RAM_STYLE="DISTRIBUTED" *) 80 | reg [REGFILE_WIDTH-1:0] regfile [REGFILE_DEPTH-1:0] ; 81 | 82 | reg [FIFO_ADDR_WIDTH-1:0] wr_addr_pointer_nxt ; // Next state of write address pointer 83 | reg [FIFO_ADDR_WIDTH-1:0] wr_addr_pointer ; // Write address pointer 84 | reg [FIFO_ADDR_WIDTH-1:0] rd_addr_pointer_nxt ; // Next state of read address pointer 85 | reg [FIFO_ADDR_WIDTH-1:0] rd_addr_pointer ; // Read address pointer 86 | reg [FIFO_ADDR_WIDTH :0] valid_entry_cntr_nxt ; // 87 | reg [FIFO_ADDR_WIDTH :0] valid_entry_counter ; // Number of valid enries in FIFO: zero=empty, 100=full 88 | 89 | reg data_available_int ; 90 | reg underflow_error_int ; 91 | reg overflow_error_int ; 92 | 93 | 94 | // ============================================================================================================================== 95 | // @@@ ocx_tlx_framer_rsp_fifo Logic 96 | // ============================================================================================================================== 97 | 98 | // --------------------- 99 | // Register File 100 | // --------------------- 101 | always @ (posedge clock) begin 102 | if(wr_enable) regfile[wr_addr_pointer] <= data_in; 103 | end 104 | assign data_out = regfile[rd_addr_pointer] ; 105 | 106 | 107 | // --------------------- 108 | // Write Address Pointer 109 | // --------------------- 110 | // Write the data into the register array and increment the pointer to point to the next slot. 111 | always @ (*) begin 112 | if ( wr_enable ) begin wr_addr_pointer_nxt = wr_addr_pointer + PTR_INC ; end 113 | else begin wr_addr_pointer_nxt = wr_addr_pointer ; end 114 | end 115 | always @ (posedge clock) begin 116 | if (!reset_n) begin wr_addr_pointer <= {FIFO_ADDR_WIDTH{1'b0}}; end 117 | else begin wr_addr_pointer <= wr_addr_pointer_nxt; end 118 | end 119 | 120 | 121 | // --------------------- 122 | // Read Address Pointer 123 | // --------------------- 124 | // This logic reads the register array and captures the output into the output reg 125 | always @ (*) begin 126 | if ( rd_done ) begin rd_addr_pointer_nxt = rd_addr_pointer + PTR_INC ; end 127 | else begin rd_addr_pointer_nxt = rd_addr_pointer ; end 128 | end 129 | always @ (posedge clock) begin 130 | if (!reset_n) begin rd_addr_pointer <= {FIFO_ADDR_WIDTH{1'b0}}; end 131 | else begin rd_addr_pointer <= rd_addr_pointer_nxt; end 132 | end 133 | 134 | 135 | // --------------------- 136 | // Valid Entry Counter 137 | // --------------------- 138 | // This counter keeps track of the number of FIFO slots that are currently being used for valid data. 139 | 140 | always @ (*) begin 141 | if ( !wr_enable && !rd_done ) begin valid_entry_cntr_nxt = valid_entry_counter ; end // No Change 142 | else if ( !wr_enable && rd_done ) begin valid_entry_cntr_nxt = valid_entry_counter - CNTR_1 ; end // Read 143 | else if ( wr_enable && !rd_done ) begin valid_entry_cntr_nxt = valid_entry_counter + CNTR_1 ; end // Write 144 | else begin valid_entry_cntr_nxt = valid_entry_counter ; end // Write and Read 145 | end 146 | always @ (posedge clock) begin 147 | if (!reset_n) begin valid_entry_counter <= {FIFO_ADDR_WIDTH+1{1'b0}}; end 148 | else begin valid_entry_counter <= valid_entry_cntr_nxt; end 149 | end 150 | assign valid_entry_count = valid_entry_counter; 151 | 152 | 153 | 154 | always @ (*) begin 155 | if ( valid_entry_counter > CNTR_0 ) begin data_available_int = 1'b1; end 156 | else begin data_available_int = 1'b0; end 157 | if ( (valid_entry_counter == CNTR_0) && rd_done ) begin underflow_error_int = 1'b1; end 158 | else begin underflow_error_int = 1'b0; end 159 | if ( (valid_entry_counter == CNTR_MAX) && wr_enable && !rd_done ) begin overflow_error_int = 1'b1; end 160 | else begin overflow_error_int = 1'b0; end 161 | end 162 | assign data_available = data_available_int; 163 | assign underflow_error = underflow_error_int; 164 | assign overflow_error = overflow_error_int; 165 | 166 | 167 | endmodule // ocx_tlx_framer_rsp_fifo 168 | -------------------------------------------------------------------------------- /ice/src/vhdl/.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore autogenerated version file 2 | meta_pkg.vhdl 3 | -------------------------------------------------------------------------------- /ice/src/vhdl/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenCAPI/omi_device_ice/34311b44c8158a4313999e92e975a26f2851f202/ice/src/vhdl/.gitkeep -------------------------------------------------------------------------------- /ice/src/vhdl/axi_pkg.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | library ieee; 26 | use ieee.std_logic_1164.all; 27 | 28 | package axi_pkg is 29 | 30 | --------------------------------------------------------------------------- 31 | -- Type Aliases for AXI4-Lite Interface 32 | --------------------------------------------------------------------------- 33 | type t_AXI4_LITE_SLAVE_INPUT is record 34 | -- Global 35 | s0_axi_aresetn : std_ulogic; 36 | 37 | -- Write Address Channel 38 | s0_axi_awvalid : std_ulogic; 39 | s0_axi_awaddr : std_ulogic_vector(63 downto 0); 40 | s0_axi_awprot : std_ulogic_vector(2 downto 0); 41 | 42 | -- Write Data Channel 43 | s0_axi_wvalid : std_ulogic; 44 | s0_axi_wdata : std_ulogic_vector(31 downto 0); 45 | s0_axi_wstrb : std_ulogic_vector(3 downto 0); 46 | 47 | -- Write Response Channel 48 | s0_axi_bready : std_ulogic; 49 | 50 | -- Read Address Channel 51 | s0_axi_arvalid : std_ulogic; 52 | s0_axi_araddr : std_ulogic_vector(63 downto 0); 53 | s0_axi_arprot : std_ulogic_vector(2 downto 0); 54 | 55 | -- Read Data Channel 56 | s0_axi_rready : std_ulogic; 57 | end record t_AXI4_LITE_SLAVE_INPUT; 58 | 59 | type t_AXI4_LITE_SLAVE_OUTPUT is record 60 | -- Global 61 | 62 | -- Write Address Channel 63 | s0_axi_awready : std_ulogic; 64 | 65 | -- Write Data Channel 66 | s0_axi_wready : std_ulogic; 67 | 68 | -- Write Response Channel 69 | s0_axi_bvalid : std_ulogic; 70 | s0_axi_bresp : std_ulogic_vector(1 downto 0); 71 | 72 | -- Read Address Channel 73 | s0_axi_arready : std_ulogic; 74 | 75 | -- Read Data Channel 76 | s0_axi_rvalid : std_ulogic; 77 | s0_axi_rdata : std_ulogic_vector(31 downto 0); 78 | s0_axi_rresp : std_ulogic_vector(1 downto 0); 79 | end record t_AXI4_LITE_SLAVE_OUTPUT; 80 | 81 | type t_AXI4_LITE_MASTER_OUTPUT is record 82 | -- Global 83 | m0_axi_aresetn : std_ulogic; 84 | 85 | -- Write Address Channel 86 | m0_axi_awvalid : std_ulogic; 87 | m0_axi_awaddr : std_ulogic_vector(63 downto 0); 88 | m0_axi_awprot : std_ulogic_vector(2 downto 0); 89 | 90 | -- Write Data Channel 91 | m0_axi_wvalid : std_ulogic; 92 | m0_axi_wdata : std_ulogic_vector(31 downto 0); 93 | m0_axi_wstrb : std_ulogic_vector(3 downto 0); 94 | 95 | -- Write Response Channel 96 | m0_axi_bready : std_ulogic; 97 | 98 | -- Read Address Channel 99 | m0_axi_arvalid : std_ulogic; 100 | m0_axi_araddr : std_ulogic_vector(63 downto 0); 101 | m0_axi_arprot : std_ulogic_vector(2 downto 0); 102 | 103 | -- Read Data Channel 104 | m0_axi_rready : std_ulogic; 105 | end record t_AXI4_LITE_MASTER_OUTPUT; 106 | 107 | type t_AXI4_LITE_MASTER_INPUT is record 108 | -- Global 109 | 110 | -- Write Address Channel 111 | m0_axi_awready : std_ulogic; 112 | 113 | -- Write Data Channel 114 | m0_axi_wready : std_ulogic; 115 | 116 | -- Write Response Channel 117 | m0_axi_bvalid : std_ulogic; 118 | m0_axi_bresp : std_ulogic_vector(1 downto 0); 119 | 120 | -- Read Address Channel 121 | m0_axi_arready : std_ulogic; 122 | 123 | -- Read Data Channel 124 | m0_axi_rvalid : std_ulogic; 125 | m0_axi_rdata : std_ulogic_vector(31 downto 0); 126 | m0_axi_rresp : std_ulogic_vector(1 downto 0); 127 | end record t_AXI4_LITE_MASTER_INPUT; 128 | 129 | --------------------------------------------------------------------------- 130 | -- Functions to Connect Master and Slaves 131 | --------------------------------------------------------------------------- 132 | function axi4_lite_master_slave_connect ( 133 | i : in t_AXI4_LITE_SLAVE_OUTPUT 134 | ) return t_AXI4_LITE_MASTER_INPUT; 135 | 136 | function axi4_lite_master_slave_connect ( 137 | i : in t_AXI4_LITE_MASTER_OUTPUT 138 | ) return t_AXI4_LITE_SLAVE_INPUT; 139 | 140 | end package axi_pkg; 141 | 142 | package body axi_pkg is 143 | 144 | function axi4_lite_master_slave_connect ( 145 | i : in t_AXI4_LITE_SLAVE_OUTPUT 146 | ) return t_AXI4_LITE_MASTER_INPUT is 147 | variable o : t_AXI4_LITE_MASTER_INPUT; 148 | begin 149 | o.m0_axi_awready := i.s0_axi_awready; 150 | o.m0_axi_wready := i.s0_axi_wready; 151 | o.m0_axi_bvalid := i.s0_axi_bvalid; 152 | o.m0_axi_bresp := i.s0_axi_bresp; 153 | o.m0_axi_arready := i.s0_axi_arready; 154 | o.m0_axi_rvalid := i.s0_axi_rvalid; 155 | o.m0_axi_rdata := i.s0_axi_rdata; 156 | o.m0_axi_rresp := i.s0_axi_rresp; 157 | return o; 158 | end; 159 | 160 | function axi4_lite_master_slave_connect ( 161 | i : in t_AXI4_LITE_MASTER_OUTPUT 162 | ) return t_AXI4_LITE_SLAVE_INPUT is 163 | variable o : t_AXI4_LITE_SLAVE_INPUT; 164 | 165 | begin 166 | o.s0_axi_aresetn := i.m0_axi_aresetn; 167 | o.s0_axi_awvalid := i.m0_axi_awvalid; 168 | o.s0_axi_awaddr := i.m0_axi_awaddr; 169 | o.s0_axi_awprot := i.m0_axi_awprot; 170 | o.s0_axi_wvalid := i.m0_axi_wvalid; 171 | o.s0_axi_wdata := i.m0_axi_wdata; 172 | o.s0_axi_wstrb := i.m0_axi_wstrb; 173 | o.s0_axi_bready := i.m0_axi_bready; 174 | o.s0_axi_arvalid := i.m0_axi_arvalid; 175 | o.s0_axi_araddr := i.m0_axi_araddr; 176 | o.s0_axi_arprot := i.m0_axi_arprot; 177 | o.s0_axi_rready := i.m0_axi_rready; 178 | return o; 179 | end; 180 | 181 | end package body axi_pkg; 182 | -------------------------------------------------------------------------------- /ice/src/vhdl/counter.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | library ieee, support, ibm, work; 26 | use ieee.std_logic_1164.all; 27 | use work.axi_pkg.all; 28 | use work.ice_func.all; 29 | 30 | entity counter is 31 | port ( 32 | clock : in std_ulogic; 33 | reset : in std_ulogic; 34 | tsm_state6_to_1 : out std_ulogic 35 | ); 36 | end counter; 37 | 38 | architecture counter of counter is 39 | 40 | SIGNAL count_0_q : std_ulogic_vector(25 downto 0); 41 | SIGNAL reset_q : STD_ULOGIC := '0'; 42 | signal tsm_state6_to_1_q : std_ulogic; 43 | 44 | attribute mark_debug : string; 45 | attribute mark_debug of count_0_q : signal is "true"; 46 | 47 | begin 48 | 49 | process (clock) 50 | begin 51 | if clock'event and clock = '1' then 52 | reset_q <= reset; 53 | tsm_state6_to_1_q <= (count_0_q(25 DOWNTO 2) = x"FFFFFF"); 54 | if (reset = '0' and reset_q = '1') OR (count_0_q /= 0) then 55 | count_0_q <= count_0_q + 1; 56 | end if; 57 | end if; 58 | end process; 59 | 60 | tsm_state6_to_1 <= tsm_state6_to_1_q; 61 | 62 | end counter; 63 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_afu_cmd_fifo.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | LIBRARY ieee, work; 26 | USE ieee.std_logic_1164.ALL; 27 | USE ieee.numeric_std.ALL; 28 | LIBRARY work; 29 | USE work.ice_func.ALL; 30 | 31 | ENTITY ice_afu_cmd_fifo IS 32 | GENERIC ( 33 | width : NATURAL := 64; 34 | depth : NATURAL := 16); 35 | PORT ( 36 | clock : IN STD_ULOGIC; --pulse 37 | reset_n : IN STD_ULOGIC; --pulse 38 | cmd_fifo_wr : IN STD_ULOGIC; 39 | cmd_fifo_dat_in : IN STD_ULOGIC_VECTOR(0 TO width - 1); 40 | cmd_fifo_full : out STD_ULOGIC; 41 | cmd_fifo_rd : IN STD_ULOGIC; -- pulse; 42 | cmd_fifo_dat_out : OUT STD_ULOGIC_VECTOR(0 TO width - 1); 43 | cmd_fifo_dat_out_val : OUT STD_ULOGIC; 44 | cmd_fifo_err : OUT STD_ULOGIC_VECTOR(0 TO 1) 45 | ); 46 | END ENTITY; 47 | 48 | ARCHITECTURE ice_afu_cmd_fifo OF ice_afu_cmd_fifo IS 49 | 50 | TYPE mem IS ARRAY(NATURAL RANGE<>) OF STD_ULOGIC_VECTOR(0 TO width+2-1); 51 | 52 | SIGNAL wr : STD_ULOGIC; 53 | SIGNAL rd : STD_ULOGIC; 54 | SIGNAL din : STD_ULOGIC_VECTOR(0 TO width - 1); 55 | SIGNAL dout : STD_ULOGIC_VECTOR(0 TO width - 1); 56 | SIGNAL full : STD_ULOGIC; 57 | SIGNAL empty : STD_ULOGIC; 58 | SIGNAL valid_perr : STD_ULOGIC; 59 | SIGNAL overflow_e : STD_ULOGIC; 60 | SIGNAL underflow_e : STD_ULOGIC; 61 | SIGNAL entry_valid : STD_ULOGIC_VECTOR(0 TO depth - 1); 62 | SIGNAL next_entry : STD_ULOGIC_VECTOR(0 TO depth - 1); 63 | SIGNAL next_entry_shift : STD_ULOGIC_VECTOR(0 TO depth - 1); 64 | SIGNAL wr_vec : STD_ULOGIC_VECTOR(0 TO depth - 1); 65 | SIGNAL hold_vec : STD_ULOGIC_VECTOR(0 TO depth - 1); 66 | SIGNAL shift_entry : STD_ULOGIC_VECTOR(0 TO depth - 1); 67 | SIGNAL entry_shift : mem(0 TO depth-1); 68 | SIGNAL entry_d : mem(0 TO depth-1); 69 | SIGNAL entry_q : mem(0 TO depth-1); 70 | signal cmd_fifo_err_d : STD_ULOGIC_VECTOR(0 TO 1); 71 | signal cmd_fifo_err_q : STD_ULOGIC_VECTOR(0 TO 1); 72 | BEGIN 73 | 74 | 75 | wr <= cmd_fifo_wr; 76 | rd <= cmd_fifo_rd; 77 | 78 | din(0 TO width -1) <= cmd_fifo_dat_in(0 TO width - 1); 79 | 80 | 81 | cmd_fifo_dat_out_val <= entry_q(0)(width) AND entry_q(0)(width+1); 82 | cmd_fifo_full <= full; 83 | cmd_fifo_dat_out(0 TO width - 1) <= dout(0 TO width - 1); 84 | 85 | 86 | next_entry(0 TO depth - 1) <= NOT entry_valid(0 TO depth - 1) AND ('1' & entry_valid(0 TO depth - 2)); 87 | next_entry_shift(0 TO depth - 1) <= next_entry(1 TO depth - 1) & '0'; 88 | wr_vec(0 TO depth - 1) <= gate(next_entry(0 TO depth - 1), wr AND NOT rd) OR 89 | gate(next_entry_shift(0 TO depth - 1), wr AND rd); 90 | shift_loop : FOR i IN 0 TO depth - 2 GENERATE 91 | entry_shift(i)(0 TO width + 2 - 1) <= entry_q(i+1)(0 TO width + 2 - 1); 92 | END GENERATE shift_loop; 93 | entry_shift(depth-1)(0 TO width + 2 - 1) <= (OTHERS => '0'); 94 | 95 | main_loop : FOR i IN 0 TO depth - 1 GENERATE 96 | entry_valid(i) <= entry_q(i)(width); 97 | entry_d(i)(0 TO width-1) <= gate(entry_q(i)(0 TO width-1), hold_vec(i)) OR gate(din(0 TO width - 1), wr_vec(i)) OR gate(entry_shift(i)(0 TO width -1), shift_entry(i)); 98 | --need to clear valid bits during reset 99 | entry_d(i)(width TO width+2 - 1) <= gate(entry_q(i)(width TO width+2-1), hold_vec(i)) OR gate("11", wr_vec(i) AND reset_n) OR gate(entry_shift(i)(width TO width+2-1), shift_entry(i) AND reset_n); 100 | END GENERATE main_loop; 101 | 102 | shift_entry(0 TO depth - 1) <= gate(entry_valid(0 TO depth - 1), rd); 103 | 104 | hold_vec(0 TO depth - 1) <= NOT (wr_vec(0 TO depth - 1) OR shift_entry(0 TO depth -1)) AND (0 TO depth - 1 => reset_n); --out of reset 105 | 106 | dout(0 TO width - 1) <= entry_q(0)(0 TO width - 1); 107 | empty <= NOT entry_q(0)(width); 108 | full <= entry_q(depth-1)(width); 109 | valid_perr <= entry_q(0)(width) XOR entry_q(0)(width+1); 110 | -- Bit 0: FIFO overflow 111 | -- Bit 1: FIFO underflow 112 | -- overload bit0 and bit 1 for valid parity error 113 | overflow_e <= (wr AND full) OR valid_perr; 114 | underflow_e <= (rd AND empty) OR valid_perr; 115 | 116 | cmd_fifo_err_d <= overflow_e & underflow_e; 117 | cmd_fifo_err <= cmd_fifo_err_q; 118 | 119 | latch : PROCESS 120 | BEGIN 121 | WAIT UNTIL clock'event AND clock = '1'; 122 | entry_q <= entry_d; 123 | cmd_fifo_err_q <= cmd_fifo_err_d; 124 | END PROCESS; 125 | 126 | END ARCHITECTURE; 127 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_cal_retry.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | 26 | Library Ieee, Work; 27 | Use Ieee.Std_logic_1164.All; 28 | Use Ieee.Numeric_std.All; 29 | Use Ieee.Std_logic_arith.All; 30 | Use Work.Ice_func.All; 31 | 32 | ENTITY ice_cal_retry IS 33 | PORT 34 | ( 35 | clock : IN STD_ULOGIC; 36 | force_recal : IN STD_ULOGIC; 37 | auto_recal_disable : IN STD_ULOGIC; 38 | mig_reset_n : IN STD_ULOGIC; 39 | c0_init_calib_complete : IN STD_ULOGIC; 40 | c1_init_calib_complete : IN STD_ULOGIC; 41 | o_init_calib_complete : OUT STD_ULOGIC_VECTOR(1 DOWNTO 0); 42 | cal_retry_cnt : out STD_ULOGIC_VECTOR(7 DOWNTO 0); 43 | cal_reset_n : out STD_ULOGIC 44 | 45 | ); 46 | END ice_cal_retry; 47 | 48 | ARCHITECTURE ice_cal_retry OF ice_cal_retry IS 49 | signal cal_good_d : STD_ULOGIC; 50 | signal cal_good_q : STD_ULOGIC; 51 | signal cal_good_dly_d : STD_ULOGIC_VECTOR(3 DOWNTO 0); 52 | signal cal_good_dly_q : STD_ULOGIC_VECTOR(3 DOWNTO 0); 53 | signal init_calib_complete : STD_ULOGIC_VECTOR(1 DOWNTO 0); 54 | signal cal_resetn_d : STD_ULOGIC; 55 | signal cal_resetn_q : STD_ULOGIC := '1'; 56 | signal resetn_sync_400mhz : STD_ULOGIC; 57 | signal count_q : STD_ULOGIC_VECTOR(29 DOWNTO 0); 58 | signal retry_cnt_q : STD_ULOGIC_VECTOR(7 DOWNTO 0); 59 | signal i_init_calib_complete : STD_ULOGIC_VECTOR(1 DOWNTO 0); 60 | 61 | attribute mark_debug : string; 62 | attribute mark_debug of cal_resetn_q : signal is "true"; 63 | attribute mark_debug of init_calib_complete : signal is "true"; 64 | attribute mark_debug of resetn_sync_400mhz : signal is "true"; 65 | attribute mark_debug of retry_cnt_q : signal is "true"; 66 | attribute mark_debug of count_q : signal is "true"; 67 | 68 | BEGIN 69 | 70 | cal_reset_n <= cal_resetn_q; 71 | cal_retry_cnt <= retry_cnt_q; 72 | i_init_calib_complete <= c0_init_calib_complete & c1_init_calib_complete; 73 | o_init_calib_complete <= init_calib_complete; 74 | 75 | cal_sync : ENTITY work.ice_gmc_asynclat 76 | PORT MAP ( 77 | i_clk => clock, 78 | i_data => i_init_calib_complete(1 DOWNTO 0), 79 | o_data => init_calib_complete(1 DOWNTO 0)); 80 | 81 | reset_sync : ENTITY work.ice_gmc_asynclat 82 | PORT MAP ( 83 | i_clk => clock, 84 | i_data(0) => mig_reset_n, 85 | o_data(0) => resetn_sync_400mhz); 86 | 87 | cal_good_d <= init_calib_complete(1) AND init_calib_complete(0); 88 | 89 | cal_resetn_d <= (count_q(29 DOWNTO 6) /= x"FFFFFF") AND NOT force_recal; 90 | 91 | process (clock) 92 | begin 93 | if clock'event and clock = '1' then 94 | 95 | if resetn_sync_400mhz = '0' OR cal_good_q = '1' OR force_recal = '1' OR auto_recal_disable = '1' then 96 | count_q <= (OTHERS => '0'); 97 | elsif cal_good_q = '0' then 98 | count_q <= count_q + 1; 99 | end if; 100 | 101 | if resetn_sync_400mhz = '0' then 102 | retry_cnt_q <= x"00"; 103 | elsif cal_resetn_d = '1' AND cal_resetn_q = '0' AND retry_cnt_q /= x"FF" then 104 | retry_cnt_q <= retry_cnt_q + 1; 105 | END if; 106 | 107 | cal_good_q <= cal_good_d; 108 | cal_resetn_q <= cal_resetn_d; 109 | end if; 110 | end process; 111 | 112 | END ice_cal_retry; 113 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_cfg_reg.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | library ieee, work; 26 | Use Ieee.Std_logic_1164.All; 27 | Use Ieee.Numeric_std.All; 28 | Use Ieee.Std_logic_arith.All; 29 | Use Work.Ice_func.All; 30 | 31 | entity ice_cfg_reg is 32 | generic 33 | ( 34 | 35 | ------------------------------------------------------------------------- 36 | addr_bit_index : natural := 0; --address index of the register 37 | num_addr_bits : natural := 54; --address width 38 | ------------------------------------------------------------------------- 39 | -- Register Definition Setup 40 | ------------------------------------------------------------------------- 41 | --Making config reg width configurable in case you don't want to use a 42 | --full 8 Bytes 43 | reg_width : natural := 64; --Width of register in bits 44 | 45 | --The following is the reset value for the instantiated register and are 46 | --hard-coded to 64 bit vectors, which sets the max reg_width value at 64. 47 | --This is done to conincide with the default SCOM register width of 64 bits. 48 | --If the user implements reg_width < 64, the default reset value for the 49 | --register below will come from the range (0 to ((reg_width) - 1)) and the 50 | --lower order values will be ingnored. 51 | reg_reset_value : std_ulogic_vector(0 to 63) := X"0000000000000000" 52 | 53 | ); 54 | port 55 | ( 56 | --CLOCKS 57 | clock_400mhz : in std_ulogic; 58 | reset_n : in STD_ULOGIC; --connect the latch version of syncr 59 | 60 | 61 | sc_addr_v : in std_ulogic_vector(0 to (num_addr_bits - 1)); 62 | --If the user implements reg_width < 64, the scom write data for the 63 | --register will come from the range (0 to ((reg_width) - 1)) and the 64 | --lower order values will be ingnored. 65 | sc_wdata : in std_ulogic_vector(0 to 63); -- Write data delivered from SCOM satellite for a write request 66 | sc_wparity : in std_ulogic; -- Write data parity bit over sc_wdata 67 | sc_wr : in std_ulogic; -- write pulse 68 | 69 | 70 | --REGISTER OUTPUTS 71 | cfg_reg : out std_ulogic_vector(0 to ((reg_width) - 1)); --configuration register output value 72 | cfg_reg_p : out std_ulogic; 73 | cfg_reg_perr : out std_ulogic; --internal parity error reporting for this register instantiation 74 | sc_wr_pulse : out std_ulogic -- single-cycle pulse indicating this reg is being written (address hit, etc.) 75 | ); 76 | 77 | end ice_cfg_reg; 78 | 79 | 80 | architecture ice_cfg_reg of ice_cfg_reg is 81 | 82 | signal cfg_reg_d : std_ulogic_vector(0 to reg_width-1); --configuration register output value 83 | SIGNAL cfg_reg_p_d : std_ulogic; 84 | 85 | signal cfg_reg_q : std_ulogic_vector(0 to ((REG_WIDTH)-1)) := reg_reset_value(0 TO (reg_width-1)); --configuration register output value 86 | SIGNAL cfg_reg_p_q : std_ulogic; 87 | SIGNAL cfg_reg_perr_d : std_ulogic; 88 | SIGNAL cfg_reg_perr_q : std_ulogic; 89 | SIGNAL act_cfg : std_ulogic; 90 | SIGNAL cfg_reg_wr : std_ulogic; 91 | SIGNAL sc_wr_pulse_q : std_ulogic; 92 | SIGNAL sc_wr_pulse_d : std_ulogic; 93 | 94 | begin 95 | 96 | 97 | act_cfg <= cfg_reg_wr; 98 | cfg_reg_wr <= sc_wr AND sc_addr_v(addr_bit_index); 99 | 100 | genP64 : IF reg_width = 64 GENERATE 101 | cfg_reg_d <= gate(sc_wdata, cfg_reg_wr) OR 102 | gate(cfg_reg_q, NOT cfg_reg_wr); 103 | cfg_reg_p_d <= (sc_wparity AND cfg_reg_wr) OR (cfg_reg_p_q and NOT cfg_reg_wr); 104 | 105 | END GENERATE genP64; 106 | 107 | genP_not64 : IF reg_width < 64 GENERATE 108 | cfg_reg_d <= gate(sc_wdata(0 TO reg_width-1), cfg_reg_wr) OR 109 | gate(cfg_reg_q(0 TO reg_width-1), NOT cfg_reg_wr); 110 | cfg_reg_p_d <= ((sc_wparity XOR xor_reduce(sc_wdata(reg_width TO 63))) AND cfg_reg_wr) OR (cfg_reg_p_q and NOT cfg_reg_wr); 111 | END GENERATE genP_not64; 112 | 113 | cfg_reg_perr <= cfg_reg_perr_q; 114 | cfg_reg_perr_d <= xor_reduce(cfg_reg_q) XOR cfg_reg_p_q; 115 | 116 | cfg_reg <= cfg_reg_q; 117 | cfg_reg_p <= cfg_reg_p_q; 118 | 119 | 120 | sc_wr_pulse <= sc_wr_pulse_q; 121 | sc_wr_pulse_d <= cfg_reg_wr; 122 | 123 | 124 | 125 | process (clock_400mhz) 126 | begin 127 | if clock_400mhz'EVENT and clock_400mhz = '1' then 128 | if reset_n='0' then 129 | cfg_reg_q <= REG_RESET_VALUE; 130 | cfg_reg_p_q <= xor_reduce(REG_RESET_VALUE); 131 | sc_wr_pulse_q <= '0'; 132 | else 133 | if act_cfg = '1' then 134 | cfg_reg_q <= cfg_reg_d; 135 | cfg_reg_p_q <= cfg_reg_p_d; 136 | end if; 137 | sc_wr_pulse_q <= sc_wr_pulse_d; 138 | end if; 139 | cfg_reg_perr_q <= cfg_reg_perr_d; 140 | end if; 141 | end process; 142 | 143 | end ice_cfg_reg; 144 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_gmc_arb.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | library ieee; 25 | use ieee.std_logic_1164.all; 26 | use work.ice_gmc_func_pkg.all; 27 | 28 | -- N input round robin arbiter with weights. 29 | -- if win with priority, priority is held until weight expires. 30 | 31 | entity ice_gmc_arb is 32 | generic( 33 | gN : natural := 4; -- number of requesters 34 | gS : natural := 2 -- size of weight (log2) 35 | ); 36 | port( 37 | i_clk : in std_ulogic; 38 | i_reset : in std_ulogic; 39 | i_yield : in std_ulogic_vector(0 to gN-1) := (others => '0'); 40 | i_req : in std_ulogic_vector(0 to gN-1); 41 | i_wt : in std_ulogic_vector(0 to gS*gN-1) := (others => '0'); 42 | i_en : in std_ulogic := '1'; 43 | o_win : out std_ulogic_vector(0 to gN-1) 44 | ); 45 | end ice_gmc_arb; 46 | 47 | architecture ice_gmc_arb of ice_gmc_arb is 48 | type wt_v is array(natural range <>) of std_ulogic_vector(1 downto 0); 49 | signal wt_d, wt_q : wt_v(0 to gN-1); 50 | signal win_d, win_q : std_ulogic_vector(0 to gN-1); 51 | signal pri_d, pri_q : std_ulogic_vector(0 to gN-1); 52 | signal req : std_ulogic_vector(0 to gN-1); 53 | begin 54 | 55 | req <= i_req and not(win_q) and not(i_yield); 56 | 57 | o_win <= win_q; 58 | 59 | pArb : process(all) 60 | variable np : std_ulogic; -- next priority 61 | begin 62 | 63 | wt_d <= wt_q; 64 | win_d <= RRarb(req,pri_q); 65 | pri_d <= pri_q; 66 | np := '0'; 67 | 68 | if i_reset='1' then 69 | pri_d <= (others => '0'); pri_d(0) <='1'; 70 | win_d <= (others => '0'); 71 | for i in 0 to gS-1 loop 72 | wt_d(i) <= i_wt(gS*i to gS*(i+1)-1); 73 | end loop; 74 | elsif req=0 then win_d <= (others => '0'); 75 | else for i in 0 to gN-1 loop 76 | if win_d(i)='1' and pri_q(i)='1' then 77 | if wt_q(i)=0 then 78 | wt_d(i) <= i_wt(2*i to 2*i+1); 79 | np:='1'; 80 | else 81 | wt_d(i) <= wt_q(i)-1; 82 | end if; 83 | else 84 | np:='1'; 85 | end if; 86 | end loop; 87 | end if; 88 | if np='1' then pri_d <= pri_q rol 1; end if; 89 | -- note.. due to a severe timing restriction in the placement of the arrays 90 | -- there will be a gap between consequtive requests from the same source 91 | -- due to the latch delay of win_q. 92 | end process; 93 | 94 | pLatch:process 95 | begin 96 | wait until rising_edge(i_clk); 97 | win_q <= win_d; 98 | if i_en='1' or i_reset='1' then 99 | pri_q <= pri_d; 100 | wt_q <= wt_d; 101 | end if; 102 | end process; 103 | 104 | 105 | end ice_gmc_arb; 106 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_gmc_asynclat.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | library ieee; 25 | use ieee.std_logic_1164.all; 26 | use work.ice_gmc_func_pkg.all; 27 | 28 | 29 | entity ice_gmc_asynclat is 30 | port( 31 | i_clk : in std_ulogic; 32 | i_data : in std_ulogic_vector; 33 | o_data : out std_ulogic_vector 34 | ); 35 | end ice_gmc_asynclat; 36 | 37 | architecture ice_gmc_asynclat of ice_gmc_asynclat is 38 | attribute async_reg : string; 39 | signal meta_1q, meta_2q : std_ulogic_vector(i_data'range); 40 | attribute async_reg of meta_1q : signal is "TRUE"; 41 | attribute async_reg of meta_2q : signal is "TRUE"; 42 | begin 43 | 44 | pw:process 45 | begin 46 | wait until rising_edge(i_clk); 47 | meta_1q <= i_data; 48 | meta_2q <= meta_1q; 49 | end process; 50 | 51 | o_data <= meta_2q; 52 | 53 | end ice_gmc_asynclat; 54 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_gmc_dpull.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | library ieee; 25 | use ieee.std_logic_1164.all; 26 | use work.ice_gmc_func_pkg.all; 27 | 28 | entity ice_gmc_dpull is 29 | port( 30 | i_clk : in std_ulogic; 31 | i_reset : in std_ulogic; 32 | i_dp : in std_ulogic; -- dataphase ? 33 | -- fifo interfaces, rsp/data 34 | i_sfc : in std_ulogic_vector(9 downto 0); 35 | i_dfc : in std_ulogic_vector(9 downto 0); 36 | i_sdat : in std_ulogic_vector(17 downto 0); 37 | i_ddat : in std_ulogic_vector(575 downto 0); 38 | o_spull : out std_ulogic; 39 | o_dpull : out std_ulogic; 40 | -- arb intf 41 | o_req : out std_ulogic; 42 | i_gnt : in std_ulogic; 43 | -- 44 | o_rd_data : out std_ulogic_vector(575 downto 0); 45 | o_rs_data : out std_ulogic_vector(17 downto 0) 46 | ); 47 | end ice_gmc_dpull; 48 | 49 | architecture ice_gmc_dpull of ice_gmc_dpull is 50 | signal s0 : std_ulogic_vector(0 to 11); 51 | signal s1 : std_ulogic_vector(0 to 4); 52 | signal s_q, s_d : std_ulogic_vector(0 to 0); 53 | signal size : std_ulogic; 54 | signal spull, dpull : std_ulogic; 55 | signal rsp_cr_q, rsp_cr_d : std_ulogic_vector(i_sfc'range); 56 | signal dat_cr_q, dat_cr_d : std_ulogic_vector(i_dfc'range); 57 | begin 58 | 59 | size <= i_sdat(16); 60 | o_rd_data <= i_ddat; 61 | 62 | s0(0) <= s_q=0; 63 | s0(1 to 2) <= choice(s0(0), rsp_cr_q /= 0); 64 | s0(3 to 4) <= choice(s0(1), dat_cr_q /= 0); 65 | s0(5 to 6) <= choice(s0(3), size and not(i_dp)); 66 | s0(7 to 8) <= choice(s0(6), i_gnt); 67 | s0(9) <= s0(5) or s0(7); 68 | s0(10 to 11) <= choice(s0(9), size); 69 | 70 | s1(0) <= s_q=1; 71 | s1(1 to 2) <= choice(s1(0), dat_cr_q /= 0); 72 | s1(3 to 4) <= choice(s1(1), i_gnt); 73 | 74 | s_d(0) <= '0' when i_reset='1' 75 | else s0(10) or s1(2) or s1(4); 76 | 77 | o_req <= s0(6) or s1(1); 78 | 79 | spull <= s0(11) or s1(3); -- defer pull to keep tag out on 2beat transfer. 80 | dpull <= s0(9) or s1(3); -- pull each beat. 81 | 82 | o_spull <= spull; 83 | o_dpull <= dpull; 84 | 85 | o_rs_data(15 downto 0) <= i_sdat(15 downto 0); 86 | o_rs_data(16) <= size; 87 | o_rs_data(17) <= s1(0); -- offs. 88 | 89 | rsp_cr_d <= (others => '0') when i_reset='1' 90 | else crAdj(rsp_cr_q, i_sfc, '0' & spull); 91 | 92 | dat_cr_d <= (others => '0') when i_reset='1' 93 | else crAdj(dat_cr_q, i_dfc, '0' & dpull); 94 | 95 | 96 | pLatch:process 97 | begin 98 | wait until rising_edge(i_clk); 99 | rsp_cr_q <= rsp_cr_d; 100 | dat_cr_q <= dat_cr_d; 101 | s_q <= s_d; 102 | end process; 103 | 104 | 105 | end ice_gmc_dpull; 106 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_gmc_etrap.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | library ieee; 25 | use ieee.std_logic_1164.all; 26 | use work.ice_gmc_func_pkg.all; 27 | 28 | entity ice_gmc_etrap is 29 | port( 30 | i_reset : in std_ulogic; 31 | i_clk : in std_ulogic; 32 | i_eTrig : in std_ulogic_vector; 33 | o_error : out std_ulogic_vector 34 | ); 35 | end ice_gmc_etrap; 36 | 37 | architecture ice_gmc_etrap of ice_gmc_etrap is 38 | signal err_q : std_ulogic_vector(i_eTrig'range); 39 | begin 40 | 41 | pError: process 42 | begin 43 | wait until rising_edge(i_clk); 44 | if i_reset='1' then err_q <= (others => '0'); 45 | else err_q <= i_eTrig; 46 | end if; 47 | end process; 48 | o_error <= err_q; 49 | 50 | assert err_q=0 or i_reset='1' 51 | report "error assert " & tconv(err_q,0) severity error; 52 | 53 | end ice_gmc_etrap; 54 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_gmc_ram.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | library ieee; 25 | use ieee.std_logic_1164.all; 26 | use work.ice_gmc_func_pkg.all; 27 | 28 | entity ice_gmc_ram is 29 | generic( 30 | gS : natural := 5; 31 | gW : natural := 64; 32 | gA : string := "BLOCK" -- or Distributed. 33 | ); 34 | port( 35 | i_wclk : in std_ulogic; 36 | i_waddr : in std_ulogic_vector(gS-1 downto 0); 37 | i_we : in std_ulogic; 38 | i_wdata : in std_ulogic_vector(gW-1 downto 0); 39 | i_rclk : in std_ulogic; 40 | i_raddr : in std_ulogic_vector(gS-1 downto 0); 41 | i_rden : in std_ulogic := '1'; 42 | i_rdmsk : in std_ulogic := '0'; 43 | o_rdata : out std_ulogic_vector(gW-1 downto 0) 44 | ); 45 | end ice_gmc_ram; 46 | 47 | architecture ice_gmc_ram of ice_gmc_ram is 48 | type texsim_array_update_policy is (RW, WR); 49 | attribute array_update : texsim_array_update_policy; 50 | attribute ram_style : string; 51 | 52 | type mem_t is array(0 to 2**gS-1) of std_ulogic_vector(gW-1 downto 0); 53 | signal MEM_q : mem_t; 54 | signal rdata_q : std_ulogic_vector(o_rdata'range); 55 | attribute array_update of MEM_Q : signal is RW; -- never WR when a signal 56 | attribute ram_style of mem_q : signal is gA; 57 | begin 58 | 59 | pw:process 60 | begin 61 | wait until rising_edge(i_wclk); 62 | if i_we='1' then MEM_q(tconv(i_waddr)) <= i_wdata; end if; 63 | end process; 64 | 65 | pr:process 66 | begin 67 | wait until rising_edge(i_rclk); 68 | if i_rden='1' then rdata_q <= MEM_q(tconv(i_raddr)); end if; 69 | end process; 70 | 71 | o_rdata <= rdata_q when i_rdmsk='0' else (others => '0'); 72 | 73 | 74 | end ice_gmc_ram; 75 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_gmc_xfifo.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | library ieee; 25 | use ieee.std_logic_1164.all; 26 | use work.ice_gmc_func_pkg.all; 27 | 28 | -- Async crossing Fifo 29 | 30 | entity ice_gmc_xfifo is 31 | generic( 32 | gM : boolean := TRUE; -- metastable pointer cross ? 33 | gS : natural := 9; 34 | gW : natural := 72; 35 | gA : string := "BLOCK" -- or Distributed. 36 | ); 37 | port( 38 | i_reset : in std_ulogic; 39 | -- 40 | i_wclk : in std_ulogic; 41 | i_push : in std_ulogic; 42 | i_data : in std_ulogic_vector(gW-1 downto 0); 43 | o_wfc : out std_ulogic_vector(gS downto 0); 44 | o_wcap : out std_ulogic_vector(gS downto 0); 45 | o_werror : out std_ulogic_vector(0 to 0); 46 | -- 47 | i_rclk : in std_ulogic; 48 | i_pull : in std_ulogic; 49 | o_data : out std_ulogic_vector(gW-1 downto 0); 50 | o_rfc : out std_ulogic_vector(gS downto 0); 51 | o_rcap : out std_ulogic_vector(gS downto 0); 52 | o_rerror : out std_ulogic_vector(0 to 0) 53 | ); 54 | end ice_gmc_xfifo; 55 | 56 | architecture ice_gmc_xfifo of ice_gmc_xfifo is 57 | signal rd_q, rd_d : std_ulogic_vector(gW-1 downto 0); 58 | signal ra_q, ra_d : std_ulogic_vector(gS downto 0); 59 | signal we_q, we_d : std_ulogic; 60 | signal wd_q, wd_d : std_ulogic_vector(gW-1 downto 0); 61 | signal wa_q, wa_d : std_ulogic_vector(gS downto 0); 62 | signal xRa, xWa : std_ulogic_vector(gS downto 0); 63 | signal ram_rdata : std_ulogic_vector(gW-1 downto 0); 64 | signal rReset,wReset : std_ulogic; 65 | signal rcap, wcap : std_ulogic_vector(gS downto 0); 66 | begin 67 | 68 | 69 | bWrite : block ------------------------------------------ 70 | signal xRa_q, xRa_d : std_ulogic_vector(gS downto 0); 71 | signal etrig : std_ulogic_vector(0 to 0); 72 | begin 73 | wd_d <= i_data; 74 | we_d <= i_push; 75 | wa_d <= (others => '0') when wreset='1' 76 | else wa_q + we_q; 77 | 78 | xRa_d <= xRa; 79 | o_wfc <= xRa - xRa_q; 80 | wcap <= wa_q - xRa_q; 81 | o_wcap <= wcap; 82 | 83 | etrig(0) <= wcap(gS) and or_reduce(wcap(gS-1 downto 0)); 84 | 85 | ETRAP: entity work.ice_gmc_etrap 86 | port map( 87 | i_reset => wreset 88 | ,i_clk => i_wclk 89 | ,i_eTrig => etrig 90 | ,o_error => o_werror 91 | ); 92 | 93 | 94 | 95 | pCLK : process 96 | begin 97 | wait until rising_edge(i_wclk); 98 | we_q <= we_d; 99 | wd_q <= wd_d; 100 | wa_q <= wa_d; 101 | xRa_q <= xRa_d; 102 | end process; 103 | end block; 104 | 105 | 106 | gMtrue : if gM generate 107 | ------ BEGIN METASTABLE !!!!! ----------- 108 | signal Meta_Ra_q, Meta_Ra_d : std_ulogic_vector(gS downto 0); 109 | signal Meta_Wa_q, Meta_Wa_d : std_ulogic_vector(gS downto 0); 110 | signal Meta_Ra, Meta_Wa : std_ulogic_vector(gS downto 0); 111 | begin 112 | -- metastabilize the resets. 113 | RMETAW : entity work.ice_gmc_asynclat 114 | port map(i_clk => i_wclk, i_data(0) => i_reset, o_data(0) => wreset); -- @WCLK 115 | RMETAR: entity work.ice_gmc_asynclat 116 | port map(i_clk => i_rclk, i_data(0) => i_reset, o_data(0) => rreset); -- @RCLK 117 | 118 | -- read address pointer to write side. 119 | Meta_Ra_d <= b2g(ra_q); -- @RCLK 120 | pRCLK : process 121 | begin 122 | wait until rising_edge(i_rclk); 123 | Meta_Ra_q <= Meta_Ra_d; 124 | end process; 125 | RAMETA : entity work.ice_gmc_asynclat 126 | port map(i_clk => i_wclk, i_data => Meta_ra_q, o_data => Meta_Ra); 127 | xRa <= g2b(Meta_Ra); -- @WCLK 128 | 129 | -- write address pointer to read side. 130 | Meta_Wa_d <= b2g(wa_q); -- @WCLK 131 | pWCLK : process 132 | begin 133 | wait until rising_edge(i_wclk); 134 | Meta_Wa_q <= Meta_Wa_d; 135 | end process; 136 | WAMETA : entity work.ice_gmc_asynclat 137 | port map(i_clk => i_rclk, i_data => Meta_wa_q, o_data => Meta_Wa); 138 | xWa <= g2b(Meta_Wa); -- @RCLK 139 | end generate; 140 | ------ END METASTABLE ----------------- 141 | 142 | gMfalse : if not(gM) generate 143 | signal xWa_q : std_ulogic_vector(gS downto 0); 144 | begin 145 | wreset <= i_reset; 146 | rreset <= i_reset; 147 | -- latch the cross pointers once to model the 1 cycle latency through the ram. 148 | pClk : process(all) 149 | begin 150 | if rising_edge(i_rclk) then xWa_q <= wa_q; end if; xWa <= xWa_q; 151 | -- using rclk to be consistant... in synchr mode, wclk=rclk 152 | end process; 153 | xRa <= ra_q; -- we used the ra_d on the ram, so relatching here is not needed. 154 | -- we use wa_q on the write side so the ram can be pushed far from the write side unit. 155 | end generate; 156 | 157 | ----- Read -------------------------- 158 | bRead : block 159 | signal xWa_q, xWa_d : std_ulogic_vector(gS downto 0); 160 | signal rAdv, rEmpty : std_ulogic; 161 | signal pref_d, pref_q : std_ulogic; --- prefetch sm. 162 | signal etrig : std_ulogic_vector(0 to 0); 163 | begin 164 | 165 | rEmpty <= ra_q = xWa; 166 | rAdv <= '0' when rEmpty='1' 167 | else '1' when i_pull='1' 168 | else not(pref_q); 169 | 170 | pref_d <= '0' when rreset='1' 171 | else '1' when rAdv='1' 172 | else '0' when i_pull='1' 173 | else pref_q; 174 | 175 | rd_d <= ram_rdata when rAdv='1' else rd_q; 176 | ra_d <= (others => '0') when rreset='1' 177 | else ra_q + rAdv; 178 | 179 | o_data <= rd_q; 180 | 181 | xWa_d <= xWa; 182 | o_rfc <= xWa - xWa_q; 183 | rcap <= xWa_q - ra_q; 184 | o_rcap <= rcap; 185 | 186 | etrig(0) <= rcap(gS) and or_reduce(rcap(gS-1 downto 0)); 187 | 188 | ETRAP: entity work.ice_gmc_etrap 189 | port map( 190 | i_reset => rreset 191 | ,i_clk => i_rclk 192 | ,i_eTrig => etrig 193 | ,o_error => o_rerror 194 | ); 195 | 196 | pRCLK : process 197 | begin 198 | wait until rising_edge(i_rclk); 199 | pref_q <= pref_d; 200 | xWa_q <= xWa_d; 201 | rd_q <= rd_d; 202 | ra_q <= ra_d; 203 | end process; 204 | end block; 205 | 206 | 207 | RAM: entity work.ice_gmc_ram 208 | generic map( 209 | gS => gS 210 | ,gW => gW 211 | ,gA => "BLOCK" 212 | ) 213 | port map( 214 | i_wclk => i_wclk 215 | ,i_waddr => wa_q(gS-1 downto 0) -- all three relatched inside ram. 216 | ,i_we => we_q 217 | ,i_wdata => wd_q 218 | ,i_rclk => i_rclk 219 | ,i_raddr => ra_d(gS-1 downto 0) -- latched inside ram. 220 | ,o_rdata => ram_rdata -- in phase with ra_q. 221 | ); 222 | 223 | end ice_gmc_xfifo; 224 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_mmio_fifo.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | 26 | library ieee, work; 27 | use ieee.std_logic_1164.all; 28 | use ieee.numeric_std.all; 29 | use work.Ice_func.all; 30 | use work.gemini_tlx_pkg.all; 31 | 32 | entity ice_mmio_fifo is 33 | generic ( 34 | width : positive range 2 to 1024; 35 | depth : positive range 2 to 512 36 | ); 37 | port ( 38 | clock : in std_ulogic; 39 | reset : in std_ulogic; -- synchronous. clears control bits not the array (maybe xilinx does that anyway ? (don't care really)) 40 | data_in : in std_ulogic_vector(width-1 downto 0); 41 | write : in std_ulogic; 42 | read : in std_ulogic; -- reads next (output is valid in same cycle as read) 43 | data_out : out std_ulogic_vector(width-1 downto 0); 44 | empty : out std_ulogic; 45 | full : out std_ulogic; 46 | overflow : out std_ulogic; 47 | underflow : out std_ulogic 48 | ); 49 | end ice_mmio_fifo ; 50 | 51 | architecture ice_mmio_fifo of ice_mmio_fifo is 52 | 53 | type fifo_type is array(depth downto 1) of std_ulogic_vector(width - 1 downto 0); -- stages numbered depth downto 1 54 | 55 | signal farray : fifo_type; -- the array 56 | signal fifo_state : std_ulogic_vector(depth downto 1); -- one "valid" bit per stage, shifting right so stage 0 is the output; 57 | 58 | begin 59 | 60 | func: process(clock) is 61 | begin 62 | if rising_edge(clock) then 63 | 64 | f_gen: for i in 1 to depth loop -- for each stage gererate the full bits then do the dataflow/array contents. first and last stages have to be done separately 65 | if i = 1 then 66 | fifo_state(i) <= (fifo_state(i) or (not fifo_state(i+1) and not fifo_state(i) and not read and write)) and 67 | (fifo_state(i+1) or not fifo_state(i) or not read or write) and 68 | (not reset); 69 | 70 | farray(i) <= GATE(farray(i), fifo_state(i) and not read) or 71 | GATE(data_in, not fifo_state(i+1) and write and (not (read xor fifo_state(i)))) or 72 | GATE(farray(i+1),fifo_state(i+1) and fifo_state(i) and read); 73 | 74 | elsif i = depth then 75 | fifo_state(i) <= (fifo_state(i) or (not fifo_state(i) and fifo_state(i-1) and not read and write)) and -- reset to all invalid - ie fifo is empty 76 | (not fifo_state(i) or not fifo_state(i-1) or not read or write) and 77 | (not reset); 78 | 79 | farray(i) <= GATE(farray(i), fifo_state(i) and fifo_state(i-1) and not read) or 80 | GATE(data_in, fifo_state(i-1) and write and (not (read xor fifo_state(i)))); 81 | 82 | else --- all the bits that are not first or last 83 | fifo_state(i) <= (fifo_state(i) or (not fifo_state(i+1) and not fifo_state(i) and fifo_state(i-1) and not read and write)) and 84 | (fifo_state(i+1) or not fifo_state(i) or not fifo_state(i-1) or not read or write) and 85 | (not reset); 86 | 87 | farray(i) <= GATE(farray(i), fifo_state(i) and fifo_state(i-1) and not read) or 88 | GATE(data_in, not fifo_state(i+1) and fifo_state(i-1) and write and (not (read xor fifo_state(i)))) or 89 | GATE(farray(i+1),fifo_state(i+1) and fifo_state(i) and fifo_state(i-1) and read); 90 | end if; 91 | 92 | end loop f_gen; 93 | end if; 94 | end process func; 95 | 96 | -- form the outputs 97 | data_out <= farray(1); 98 | empty <= not fifo_state(1); 99 | full <= fifo_state(depth); 100 | overflow <= write and not read and fifo_state(depth); 101 | underflow <= read and not fifo_state(1); 102 | 103 | end ice_mmio_fifo; 104 | -------------------------------------------------------------------------------- /ice/src/vhdl/ice_trap_reg.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | library ieee, work; 26 | Use Ieee.Std_logic_1164.All; 27 | Use Ieee.Numeric_std.All; 28 | Use Ieee.Std_logic_arith.All; 29 | Use Work.Ice_func.All; 30 | 31 | entity ice_trap_reg is 32 | generic 33 | ( 34 | --Making config reg width configurable in case you don't want to use a 35 | --full 8 Bytes 36 | reg_width : natural := 64 --Width of register in bits 37 | ); 38 | port 39 | ( 40 | --CLOCKS 41 | clock_400mhz : in std_ulogic; 42 | reset_n : in STD_ULOGIC; --connect the latch version of syncr 43 | 44 | 45 | --STATUS Inputs 46 | trap_input_bus : in std_ulogic_vector(0 to reg_width - 1); 47 | 48 | --This input will cause the trap register value to grab the value on 49 | --trap_input_bus when asserted. 50 | trap_update : in STD_ULOGIC := '1'; 51 | --clear trap 52 | trap_clear : in std_ulogic := '0'; 53 | 54 | --REGISTER OUTPUTS 55 | trap_reg : out std_ulogic_vector(0 to reg_width-1); --trap register output value 56 | trap_reg_p : out std_ulogic; 57 | trap_reg_perr : out std_ulogic --internal parity error reporting for this register instantiation 58 | 59 | ); 60 | 61 | end ice_trap_reg; 62 | 63 | 64 | architecture ice_trap_reg of ice_trap_reg is 65 | SIGNAL act_trap : std_ulogic; 66 | SIGNAL trap_reg_p_d : std_ulogic; 67 | SIGNAL trap_reg_p_q : std_ulogic; 68 | SIGNAL trap_reg_perr_d : std_ulogic; 69 | SIGNAL trap_reg_perr_q : std_ulogic; 70 | SIGNAL trap_reg_d : std_ulogic_vector(0 to reg_width-1); 71 | SIGNAL trap_reg_q : std_ulogic_vector(0 to reg_width-1); 72 | 73 | begin 74 | 75 | act_trap <= trap_update OR trap_clear; 76 | 77 | trap_reg_d <= gate(trap_input_bus, trap_update AND NOT trap_clear) OR 78 | gate(trap_reg_q, NOT trap_update AND NOT trap_clear); 79 | 80 | trap_reg_p_d <= (xor_reduce(trap_input_bus) AND trap_update AND NOT trap_clear) OR 81 | (trap_reg_p_q AND NOT trap_update AND NOT trap_clear); 82 | 83 | trap_reg_perr <= trap_reg_perr_q; 84 | trap_reg_perr_d <= xor_reduce(trap_reg_q) XOR trap_reg_p_q; 85 | trap_reg <= trap_reg_q; 86 | trap_reg_p <= trap_reg_p_q; 87 | 88 | 89 | 90 | process (clock_400mhz) 91 | begin 92 | if clock_400mhz'EVENT and clock_400mhz = '1' then 93 | if reset_n='0' then 94 | trap_reg_q <= (others => '0'); 95 | trap_reg_p_q <= '0'; 96 | else 97 | if act_trap = '1' then 98 | trap_reg_q <= trap_reg_d; 99 | trap_reg_p_q <= trap_reg_p_d; 100 | end if; 101 | end if; 102 | trap_reg_perr_q <= trap_reg_perr_d; 103 | end if; 104 | end process; 105 | 106 | end ice_trap_reg; 107 | -------------------------------------------------------------------------------- /ice/src/vhdl/iram_fifo_64x112.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | library ieee, Work; 26 | Use Ieee.Std_logic_1164.All; 27 | Use Ieee.Numeric_std.All; 28 | Use Ieee.Std_logic_arith.All; 29 | Use Work.Ice_func.All; 30 | use work.gemini_tlx_pkg.all; 31 | 32 | --for all: use entity .[()] 33 | entity iram_fifo_64x112 is 34 | port ( 35 | clock : in std_ulogic; 36 | reset : in std_ulogic; -- synchronous. clears control bits not the array (maybe xilinx does that anyway ? (don't care really)) 37 | data_in : in std_ulogic_vector(111 downto 0); 38 | write : in std_ulogic; 39 | read : in std_ulogic; -- reads next (output is valid in same cycle as read) 40 | data_out : out std_ulogic_vector(111 downto 0); 41 | empty : out std_ulogic; 42 | full : out std_ulogic; 43 | overflow : out std_ulogic; 44 | underflow : out std_ulogic 45 | ); 46 | end iram_fifo_64x112 ; 47 | 48 | architecture iram_fifo_64x112 of iram_fifo_64x112 is 49 | 50 | signal wptr_d,wptr_q,rptr_d,rptr_q : std_ulogic_vector (6 downto 0); -- one too many gives empty-full distinction 51 | signal bram_out : std_ulogic_vector (111 downto 0); 52 | signal bram_valid_d,bram_valid_q : std_ulogic; 53 | signal inc_rptr,full_int,empty_int : std_ulogic; 54 | signal write_fifo : std_ulogic; 55 | constant unity : std_ulogic_vector := "0000001"; -- (log2(depth) downto 1 => '0') & '1'; 56 | begin 57 | 58 | bulk_bram : component iram_1r1w1ck_64x112 59 | port map ( 60 | clk => clock, 61 | ena => '1', 62 | enb => '1', 63 | wea => write, 64 | dia => data_in, 65 | addra => wptr_q(5 downto 0), 66 | addrb => rptr_q(5 downto 0), 67 | dob => bram_out 68 | ); 69 | 70 | streaming_fifo: entity work.tlx_fifo 71 | generic map ( 72 | width => 112, 73 | depth => 2 74 | ) 75 | port map ( 76 | clock => clock, 77 | reset => reset, 78 | data_in => bram_out, 79 | write => write_fifo, 80 | read => read, 81 | data_out => data_out, 82 | empty => empty_int, 83 | full => full_int, 84 | overflow => open, 85 | underflow => underflow 86 | ); 87 | 88 | full <= full_int; 89 | empty <= empty_int; 90 | overflow <= AND_REDUCE( (wptr_q(5 downto 0) xnor rptr_q(5 downto 0)) & (wptr_q(6) xor rptr_q(6)) & write); 91 | 92 | inc_rptr <= '1' when (wptr_q /= rptr_q ) and ( read or empty_int or (not full_int and not write_fifo)) = '1' else '0'; 93 | 94 | write_fifo <= bram_valid_q and not full_int; 95 | 96 | bram_valid_d <= '1' when (wptr_q /= rptr_q ) else '0'; -- bram_valid_q will say when bram output is valid 97 | 98 | wptr_d <= GATE(wptr_q + unity, not reset and write) or 99 | GATE(wptr_q , not reset and not write); 100 | 101 | rptr_d <= GATE(rptr_q + unity , not reset and inc_rptr) or 102 | GATE(rptr_q , not reset and not inc_rptr); 103 | 104 | 105 | latches : process(clock) 106 | begin 107 | if clock 'event and clock = '1' then 108 | bram_valid_q <= bram_valid_d and not reset; 109 | wptr_q <= wptr_d; 110 | rptr_q <= rptr_d; 111 | end if; 112 | end process; 113 | 114 | end architecture; 115 | 116 | 117 | -------------------------------------------------------------------------------- /ice/src/vhdl/iram_fifo_64x16.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | library ieee, Work; 26 | Use Ieee.Std_logic_1164.All; 27 | Use Ieee.Numeric_std.All; 28 | Use Ieee.Std_logic_arith.All; 29 | Use Work.Ice_func.All; 30 | use work.gemini_tlx_pkg.all; 31 | 32 | --for all: use entity .[()] 33 | entity iram_fifo_64x16 is 34 | port ( 35 | clock : in std_ulogic; 36 | reset : in std_ulogic; -- synchronous. clears control bits not the array (maybe xilinx does that anyway ? (don't care really)) 37 | data_in : in std_ulogic_vector(15 downto 0); 38 | write : in std_ulogic; 39 | read : in std_ulogic; -- reads next (output is valid in same cycle as read) 40 | data_out : out std_ulogic_vector(15 downto 0); 41 | empty : out std_ulogic; 42 | full : out std_ulogic; 43 | overflow : out std_ulogic; 44 | underflow : out std_ulogic 45 | ); 46 | end iram_fifo_64x16 ; 47 | 48 | architecture iram_fifo_64x16 of iram_fifo_64x16 is 49 | 50 | signal wptr_d,wptr_q,rptr_d,rptr_q : std_ulogic_vector (6 downto 0); -- one too many gives empty-full distinction 51 | signal bram_out : std_ulogic_vector (15 downto 0); 52 | signal bram_valid_d,bram_valid_q : std_ulogic; 53 | signal inc_rptr,full_int,empty_int : std_ulogic; 54 | signal write_fifo : std_ulogic; 55 | constant unity : std_ulogic_vector := "0000001"; -- (log2(depth) downto 1 => '0') & '1'; 56 | begin 57 | 58 | bulk_bram : component iram_1r1w1ck_64x16 59 | port map ( 60 | clk => clock, 61 | ena => '1', 62 | enb => '1', 63 | wea => write, 64 | dia => data_in, 65 | addra => wptr_q(5 downto 0), 66 | addrb => rptr_q(5 downto 0), 67 | dob => bram_out 68 | ); 69 | 70 | streaming_fifo: entity work.tlx_fifo 71 | generic map ( 72 | width => 16, 73 | depth => 2 74 | ) 75 | port map ( 76 | clock => clock, 77 | reset => reset, 78 | data_in => bram_out, 79 | write => write_fifo, 80 | read => read, 81 | data_out => data_out, 82 | empty => empty_int, 83 | full => full_int, 84 | overflow => open, 85 | underflow => underflow 86 | ); 87 | 88 | full <= full_int; 89 | empty <= empty_int; 90 | overflow <= AND_REDUCE( (wptr_q(5 downto 0) xnor rptr_q(5 downto 0)) & (wptr_q(6) xor rptr_q(6)) & write); 91 | 92 | inc_rptr <= '1' when (wptr_q /= rptr_q ) and ( read or empty_int or (not full_int and not write_fifo)) = '1' else '0'; 93 | 94 | write_fifo <= bram_valid_q and not full_int; 95 | 96 | bram_valid_d <= '1' when (wptr_q /= rptr_q ) else '0'; -- bram_valid_q will say when bram output is valid 97 | 98 | wptr_d <= GATE(wptr_q + unity, not reset and write) or 99 | GATE(wptr_q , not reset and not write); 100 | 101 | rptr_d <= GATE(rptr_q + unity , not reset and inc_rptr) or 102 | GATE(rptr_q , not reset and not inc_rptr); 103 | 104 | 105 | 106 | latches : process(clock) 107 | begin 108 | if clock 'event and clock = '1' then 109 | bram_valid_q <= bram_valid_d and not reset; 110 | wptr_q <= wptr_d; 111 | rptr_q <= rptr_d; 112 | end if; 113 | end process; 114 | 115 | end architecture; 116 | 117 | 118 | -------------------------------------------------------------------------------- /ice/src/vhdl/iram_fifo_64x32.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | library ieee, Work; 26 | Use Ieee.Std_logic_1164.All; 27 | Use Ieee.Numeric_std.All; 28 | Use Ieee.Std_logic_arith.All; 29 | Use Work.Ice_func.All; 30 | use work.gemini_tlx_pkg.all; 31 | 32 | --for all: use entity .[()] 33 | entity iram_fifo_64x32 is 34 | port ( 35 | clock : in std_ulogic; 36 | reset : in std_ulogic; -- synchronous. clears control bits not the array (maybe xilinx does that anyway ? (don't care really)) 37 | data_in : in std_ulogic_vector(31 downto 0); 38 | write : in std_ulogic; 39 | read : in std_ulogic; -- reads next (output is valid in same cycle as read) 40 | data_out : out std_ulogic_vector(31 downto 0); 41 | empty : out std_ulogic; 42 | full : out std_ulogic; 43 | overflow : out std_ulogic; 44 | underflow : out std_ulogic 45 | ); 46 | end iram_fifo_64x32 ; 47 | 48 | architecture iram_fifo_64x32 of iram_fifo_64x32 is 49 | 50 | signal wptr_d,wptr_q,rptr_d,rptr_q : std_ulogic_vector (6 downto 0); -- one too many gives empty-full distinction 51 | signal bram_out : std_ulogic_vector (31 downto 0); 52 | signal bram_valid_d,bram_valid_q : std_ulogic; 53 | signal inc_rptr,full_int,empty_int : std_ulogic; 54 | signal write_fifo : std_ulogic; 55 | constant unity : std_ulogic_vector := "0000001"; -- (log2(depth) downto 1 => '0') & '1'; 56 | begin 57 | 58 | bulk_bram : component iram_1r1w1ck_64x32 59 | port map ( 60 | clk => clock, 61 | ena => '1', 62 | enb => '1', 63 | wea => write, 64 | dia => data_in, 65 | addra => wptr_q(5 downto 0), 66 | addrb => rptr_q(5 downto 0), 67 | dob => bram_out 68 | ); 69 | 70 | streaming_fifo: entity work.tlx_fifo 71 | generic map ( 72 | width => 32, 73 | depth => 2 74 | ) 75 | port map ( 76 | clock => clock, 77 | reset => reset, 78 | data_in => bram_out, 79 | write => write_fifo, 80 | read => read, 81 | data_out => data_out, 82 | empty => empty_int, 83 | full => full_int, 84 | overflow => open, 85 | underflow => underflow 86 | ); 87 | 88 | full <= full_int; 89 | empty <= empty_int; 90 | overflow <= AND_REDUCE( (wptr_q(5 downto 0) xnor rptr_q(5 downto 0)) & (wptr_q(6) xor rptr_q(6)) & write); 91 | 92 | 93 | inc_rptr <= '1' when (wptr_q /= rptr_q ) and ( read or empty_int or (not full_int and not write_fifo)) = '1' else '0'; 94 | 95 | write_fifo <= bram_valid_q and not full_int; 96 | 97 | bram_valid_d <= '1' when (wptr_q /= rptr_q ) else '0'; -- bram_valid_q will say when bram output is valid 98 | 99 | wptr_d <= GATE(wptr_q + unity, not reset and write) or 100 | GATE(wptr_q , not reset and not write); 101 | 102 | rptr_d <= GATE(rptr_q + unity , not reset and inc_rptr) or 103 | GATE(rptr_q , not reset and not inc_rptr); 104 | 105 | 106 | latches : process(clock) 107 | begin 108 | if clock 'event and clock = '1' then 109 | bram_valid_q <= bram_valid_d and not reset; 110 | wptr_q <= wptr_d; 111 | rptr_q <= rptr_d; 112 | end if; 113 | end process; 114 | 115 | end architecture; 116 | 117 | 118 | -------------------------------------------------------------------------------- /ice/src/vhdl/iram_fifo_64x518.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | library ieee, Work; 26 | Use Ieee.Std_logic_1164.All; 27 | Use Ieee.Numeric_std.All; 28 | Use Ieee.Std_logic_arith.All; 29 | Use Work.Ice_func.All; 30 | use work.gemini_tlx_pkg.all; 31 | 32 | --for all: use entity .[()] 33 | entity iram_fifo_64x518 is 34 | port ( 35 | clock : in std_ulogic; 36 | reset : in std_ulogic; -- synchronous. clears control bits not the array (maybe xilinx does that anyway ? (don't care really)) 37 | data_in : in std_ulogic_vector(517 downto 0); 38 | write : in std_ulogic; 39 | read : in std_ulogic; -- reads next (output is valid in same cycle as read) 40 | data_out : out std_ulogic_vector(517 downto 0); 41 | empty : out std_ulogic; 42 | full : out std_ulogic; 43 | overflow : out std_ulogic; 44 | underflow : out std_ulogic 45 | ); 46 | end iram_fifo_64x518 ; 47 | 48 | architecture iram_fifo_64x518 of iram_fifo_64x518 is 49 | 50 | signal wptr_d,wptr_q,rptr_d,rptr_q : std_ulogic_vector (6 downto 0); -- one too many gives empty-full distinction 51 | signal bram_out : std_ulogic_vector (517 downto 0); 52 | signal bram_valid_d,bram_valid_q : std_ulogic; 53 | signal inc_rptr,full_int,empty_int : std_ulogic; 54 | signal write_fifo : std_ulogic; 55 | constant unity : std_ulogic_vector := "0000001"; -- (log2(depth) downto 1 => '0') & '1'; 56 | begin 57 | 58 | bulk_bram : component iram_1r1w1ck_64x518 59 | port map ( 60 | clk => clock, 61 | ena => '1', 62 | enb => '1', 63 | wea => write, 64 | dia => data_in, 65 | addra => wptr_q(5 downto 0), 66 | addrb => rptr_q(5 downto 0), 67 | dob => bram_out 68 | ); 69 | 70 | streaming_fifo: entity work.tlx_fifo 71 | generic map ( 72 | width => 518, 73 | depth => 2 74 | ) 75 | port map ( 76 | clock => clock, 77 | reset => reset, 78 | data_in => bram_out, 79 | write => write_fifo, 80 | read => read, 81 | data_out => data_out, 82 | empty => empty_int, 83 | full => full_int, 84 | overflow => open, 85 | underflow => underflow 86 | ); 87 | 88 | full <= full_int; 89 | empty <= empty_int; 90 | overflow <= AND_REDUCE( (wptr_q(5 downto 0) xnor rptr_q(5 downto 0)) & (wptr_q(6) xor rptr_q(6)) & write); 91 | 92 | inc_rptr <= '1' when (wptr_q /= rptr_q ) and ( read or empty_int or (not full_int and not write_fifo)) = '1' else '0'; 93 | 94 | write_fifo <= bram_valid_q and not full_int; 95 | 96 | bram_valid_d <= '1' when (wptr_q /= rptr_q ) else '0'; -- bram_valid_q will say when bram output is valid 97 | 98 | wptr_d <= GATE(wptr_q + unity, not reset and write) or 99 | GATE(wptr_q , not reset and not write); 100 | 101 | rptr_d <= GATE(rptr_q + unity , not reset and inc_rptr) or 102 | GATE(rptr_q , not reset and not inc_rptr); 103 | 104 | 105 | latches : process(clock) 106 | begin 107 | if clock 'event and clock = '1' then 108 | bram_valid_q <= bram_valid_d and not reset; 109 | wptr_q <= wptr_d; 110 | rptr_q <= rptr_d; 111 | end if; 112 | end process; 113 | 114 | end architecture; 115 | 116 | 117 | -------------------------------------------------------------------------------- /ice/src/vhdl/iram_fifo_64x85.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | library ieee, Work; 26 | Use Ieee.Std_logic_1164.All; 27 | Use Ieee.Numeric_std.All; 28 | Use Ieee.Std_logic_arith.All; 29 | Use Work.Ice_func.All; 30 | use work.gemini_tlx_pkg.all; 31 | 32 | --for all: use entity .[()] 33 | entity iram_fifo_64x85 is 34 | port ( 35 | clock : in std_ulogic; 36 | reset : in std_ulogic; -- synchronous. clears control bits not the array (maybe xilinx does that anyway ? (don't care really)) 37 | data_in : in std_ulogic_vector(84 downto 0); 38 | write : in std_ulogic; 39 | read : in std_ulogic; -- reads next (output is valid in same cycle as read) 40 | data_out : out std_ulogic_vector(84 downto 0); 41 | empty : out std_ulogic; 42 | full : out std_ulogic; 43 | overflow : out std_ulogic; 44 | underflow : out std_ulogic 45 | ); 46 | end iram_fifo_64x85 ; 47 | 48 | architecture iram_fifo_64x85 of iram_fifo_64x85 is 49 | 50 | signal wptr_d,wptr_q,rptr_d,rptr_q : std_ulogic_vector (6 downto 0); -- one too many gives empty-full distinction 51 | signal bram_out : std_ulogic_vector (84 downto 0); 52 | signal bram_valid_d,bram_valid_q : std_ulogic; 53 | signal inc_rptr,full_int,empty_int : std_ulogic; 54 | signal write_fifo : std_ulogic; 55 | constant unity : std_ulogic_vector := "0000001"; -- (log2(depth) downto 1 => '0') & '1'; 56 | begin 57 | 58 | bulk_bram : component iram_1r1w1ck_64x85 59 | port map ( 60 | clk => clock, 61 | ena => '1', 62 | enb => '1', 63 | wea => write, 64 | dia => data_in, 65 | addra => wptr_q(5 downto 0), 66 | addrb => rptr_q(5 downto 0), 67 | dob => bram_out 68 | ); 69 | 70 | streaming_fifo: entity work.tlx_fifo 71 | generic map ( 72 | width => 85, 73 | depth => 2 74 | ) 75 | port map ( 76 | clock => clock, 77 | reset => reset, 78 | data_in => bram_out, 79 | write => write_fifo, 80 | read => read, 81 | data_out => data_out, 82 | empty => empty_int, 83 | full => full_int, 84 | overflow => open, 85 | underflow => underflow 86 | ); 87 | 88 | full <= full_int; 89 | empty <= empty_int; 90 | overflow <= AND_REDUCE( (wptr_q(5 downto 0) xnor rptr_q(5 downto 0)) & (wptr_q(6) xor rptr_q(6)) & write); 91 | 92 | 93 | inc_rptr <= '1' when (wptr_q /= rptr_q ) and ( read or empty_int or (not full_int and not write_fifo)) = '1' else '0'; 94 | 95 | write_fifo <= bram_valid_q and not full_int; 96 | 97 | bram_valid_d <= '1' when (wptr_q /= rptr_q ) else '0'; -- bram_valid_q will say when bram output is valid 98 | 99 | wptr_d <= GATE(wptr_q + unity, not reset and write) or 100 | GATE(wptr_q , not reset and not write); 101 | 102 | rptr_d <= GATE(rptr_q + unity , not reset and inc_rptr) or 103 | GATE(rptr_q , not reset and not inc_rptr); 104 | 105 | 106 | latches : process(clock) 107 | begin 108 | if clock 'event and clock = '1' then 109 | bram_valid_q <= bram_valid_d and not reset; 110 | wptr_q <= wptr_d; 111 | rptr_q <= rptr_d; 112 | end if; 113 | end process; 114 | 115 | end architecture; 116 | 117 | 118 | -------------------------------------------------------------------------------- /ice/src/vhdl/tlx_fifo.vhdl: -------------------------------------------------------------------------------- 1 | -- *!*************************************************************************** 2 | -- *! Copyright 2019 International Business Machines 3 | -- *! 4 | -- *! Licensed under the Apache License, Version 2.0 (the "License"); 5 | -- *! you may not use this file except in compliance with the License. 6 | -- *! You may obtain a copy of the License at 7 | -- *! http://www.apache.org/licenses/LICENSE-2.0 8 | -- *! 9 | -- *! The patent license granted to you in Section 3 of the License, as applied 10 | -- *! to the "Work," hereby includes implementations of the Work in physical form. 11 | -- *! 12 | -- *! Unless required by applicable law or agreed to in writing, the reference design 13 | -- *! distributed under the License is distributed on an "AS IS" BASIS, 14 | -- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | -- *! See the License for the specific language governing permissions and 16 | -- *! limitations under the License. 17 | -- *! 18 | -- *! The background Specification upon which this is based is managed by and available from 19 | -- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org. 20 | -- *!*************************************************************************** 21 | 22 | 23 | 24 | 25 | Library Ieee, Work; 26 | Use Ieee.Std_logic_1164.All; 27 | Use Ieee.Numeric_std.All; 28 | Use Ieee.Std_logic_arith.All; 29 | Use Work.Ice_func.All; 30 | use work.gemini_tlx_pkg.all; 31 | 32 | entity tlx_fifo is 33 | generic ( 34 | width : positive range 2 to 1024; 35 | depth : positive range 2 to 512 36 | ); 37 | port ( 38 | clock : in std_ulogic; 39 | reset : in std_ulogic; -- synchronous. clears control bits not the array (maybe xilinx does that anyway ? (don't care really)) 40 | data_in : in std_ulogic_vector(width-1 downto 0); 41 | write : in std_ulogic; 42 | read : in std_ulogic; -- reads next (output is valid in same cycle as read) 43 | data_out : out std_ulogic_vector(width-1 downto 0); 44 | empty : out std_ulogic; 45 | full : out std_ulogic; 46 | overflow : out std_ulogic; 47 | underflow : out std_ulogic 48 | ); 49 | end tlx_fifo ; 50 | 51 | architecture tlx_fifo of tlx_fifo is 52 | 53 | type fifo_type is array(depth downto 1) of std_ulogic_vector(width - 1 downto 0); -- stages numbered depth downto 1 54 | 55 | signal farray : fifo_type; -- the array 56 | signal fifo_state : std_ulogic_vector(depth downto 1); -- one "valid" bit per stage, shifting right so stage 0 is the output; 57 | 58 | begin 59 | 60 | func: process(clock) is 61 | begin 62 | if rising_edge(clock) then 63 | 64 | f_gen: for i in 1 to depth loop -- for each stage gererate the full bits then do the dataflow/array contents. first and last stages have to be done separately 65 | if i = 1 then 66 | fifo_state(i) <= (fifo_state(i) or (not fifo_state(i+1) and not fifo_state(i) and not read and write)) and 67 | (fifo_state(i+1) or not fifo_state(i) or not read or write) and 68 | (not reset); 69 | 70 | farray(i) <= GATE(farray(i), fifo_state(i) and not read) or 71 | GATE(data_in, not fifo_state(i+1) and write and (not (read xor fifo_state(i)))) or 72 | GATE(farray(i+1),fifo_state(i+1) and fifo_state(i) and read); 73 | 74 | elsif i = depth then 75 | fifo_state(i) <= (fifo_state(i) or (not fifo_state(i) and fifo_state(i-1) and not read and write)) and -- reset to all invalid - ie fifo is empty 76 | (not fifo_state(i) or not fifo_state(i-1) or not read or write) and 77 | (not reset); 78 | 79 | farray(i) <= GATE(farray(i), fifo_state(i) and fifo_state(i-1) and not read) or 80 | GATE(data_in, fifo_state(i-1) and write and (not (read xor fifo_state(i)))); 81 | 82 | else --- all the bits that are not first or last 83 | fifo_state(i) <= (fifo_state(i) or (not fifo_state(i+1) and not fifo_state(i) and fifo_state(i-1) and not read and write)) and 84 | (fifo_state(i+1) or not fifo_state(i) or not fifo_state(i-1) or not read or write) and 85 | (not reset); 86 | 87 | farray(i) <= GATE(farray(i), fifo_state(i) and fifo_state(i-1) and not read) or 88 | GATE(data_in, not fifo_state(i+1) and fifo_state(i-1) and write and (not (read xor fifo_state(i)))) or 89 | GATE(farray(i+1),fifo_state(i+1) and fifo_state(i) and fifo_state(i-1) and read); 90 | end if; 91 | 92 | end loop f_gen; 93 | end if; 94 | end process func; 95 | 96 | -- form the outputs 97 | data_out <= farray(1); 98 | empty <= not fifo_state(1); 99 | full <= AND_REDUCE(fifo_state); 100 | overflow <= write and not read and fifo_state(depth); 101 | underflow <= read and not fifo_state(1); 102 | 103 | end tlx_fifo; 104 | 105 | -------------------------------------------------------------------------------- /scripts/adding_fire1: -------------------------------------------------------------------------------- 1 | // ------------------------------------------------------------------------------------------------------------------- 2 | // Transmitter buffer bypass controller helper block 3 | // ------------------------------------------------------------------------------------------------------------------- 4 | wire gtwiz_buffbypass_tx_resetdone_int; 5 | 6 | assign gtwiz_buffbypass_tx_resetdone_int = gtwiz_reset_tx_done_out; 7 | 8 | wire gtwiz_buffbypass_rx_resetdone_int; 9 | 10 | assign gtwiz_buffbypass_rx_resetdone_int = gtwiz_reset_rx_done_out; 11 | 12 | wire [7:0] txphaligndone_int; 13 | wire [7:0] txphinitdone_int; 14 | wire [7:0] txdlysresetdone_int; 15 | wire [7:0] txsyncout_int; 16 | wire [7:0] txsyncdone_int; 17 | wire [7:0] txphdlyreset_int; 18 | wire [7:0] txphalign_int; 19 | wire [7:0] txphalignen_int; 20 | wire [7:0] txphdlypd_int; 21 | wire [7:0] txphinit_int; 22 | wire [7:0] txphovrden_int; 23 | wire [7:0] txdlysreset_int; 24 | wire [7:0] txdlybypass_int; 25 | wire [7:0] txdlyen_int; 26 | wire [7:0] txdlyovrden_int; 27 | wire [7:0] txphdlytstclk_int; 28 | wire [7:0] txdlyhold_int; 29 | wire [7:0] txdlyupdown_int; 30 | wire [7:0] txsyncmode_int; 31 | wire [7:0] txsyncallin_int; 32 | wire [7:0] txsyncin_int; 33 | 34 | wire [7:0] rxphaligndone_int; 35 | wire [7:0] rxdlysresetdone_int; 36 | wire [7:0] rxsyncout_int; 37 | wire [7:0] rxsyncdone_int; 38 | wire [7:0] rxphdlyreset_int; 39 | wire [7:0] rxphalign_int; 40 | wire [7:0] rxphalignen_int; 41 | wire [7:0] rxphdlypd_int; 42 | wire [7:0] rxphovrden_int; 43 | wire [7:0] rxdlysreset_int; 44 | wire [7:0] rxdlybypass_int; 45 | wire [7:0] rxdlyen_int; 46 | wire [7:0] rxdlyovrden_int; 47 | wire [7:0] rxsyncmode_int; 48 | wire [7:0] rxsyncallin_int; 49 | wire [7:0] rxsyncin_int; 50 | 51 | 52 | -------------------------------------------------------------------------------- /scripts/adding_fire2: -------------------------------------------------------------------------------- 1 | // TX Interface 2 | input wire [1:0] ch0_txheader, 3 | input wire [1:0] ch1_txheader, 4 | input wire [1:0] ch2_txheader, 5 | input wire [1:0] ch3_txheader, 6 | input wire [1:0] ch4_txheader, 7 | input wire [1:0] ch5_txheader, 8 | input wire [1:0] ch6_txheader, 9 | input wire [1:0] ch7_txheader, 10 | input wire [5:0] ch0_txsequence, 11 | input wire [5:0] ch1_txsequence, 12 | input wire [5:0] ch2_txsequence, 13 | input wire [5:0] ch3_txsequence, 14 | input wire [5:0] ch4_txsequence, 15 | input wire [5:0] ch5_txsequence, 16 | input wire [5:0] ch6_txsequence, 17 | input wire [5:0] ch7_txsequence, 18 | input wire [63:0] hb0_gtwiz_userdata_tx, 19 | input wire [63:0] hb1_gtwiz_userdata_tx, 20 | input wire [63:0] hb2_gtwiz_userdata_tx, 21 | input wire [63:0] hb3_gtwiz_userdata_tx, 22 | input wire [63:0] hb4_gtwiz_userdata_tx, 23 | input wire [63:0] hb5_gtwiz_userdata_tx, 24 | input wire [63:0] hb6_gtwiz_userdata_tx, 25 | input wire [63:0] hb7_gtwiz_userdata_tx, 26 | 27 | // RX Interface 28 | output wire [0:0] ch0_rxdatavalid, 29 | output wire [0:0] ch1_rxdatavalid, 30 | output wire [0:0] ch2_rxdatavalid, 31 | output wire [0:0] ch3_rxdatavalid, 32 | output wire [0:0] ch4_rxdatavalid, 33 | output wire [0:0] ch5_rxdatavalid, 34 | output wire [0:0] ch6_rxdatavalid, 35 | output wire [0:0] ch7_rxdatavalid, 36 | output wire [1:0] ch0_rxheader, 37 | output wire [1:0] ch1_rxheader, 38 | output wire [1:0] ch2_rxheader, 39 | output wire [1:0] ch3_rxheader, 40 | output wire [1:0] ch4_rxheader, 41 | output wire [1:0] ch5_rxheader, 42 | output wire [1:0] ch6_rxheader, 43 | output wire [1:0] ch7_rxheader, 44 | input wire [0:0] ch0_rxgearboxslip, 45 | input wire [0:0] ch1_rxgearboxslip, 46 | input wire [0:0] ch2_rxgearboxslip, 47 | input wire [0:0] ch3_rxgearboxslip, 48 | input wire [0:0] ch4_rxgearboxslip, 49 | input wire [0:0] ch5_rxgearboxslip, 50 | input wire [0:0] ch6_rxgearboxslip, 51 | input wire [0:0] ch7_rxgearboxslip, 52 | output wire [63:0] hb0_gtwiz_userdata_rx, 53 | output wire [63:0] hb1_gtwiz_userdata_rx, 54 | output wire [63:0] hb2_gtwiz_userdata_rx, 55 | output wire [63:0] hb3_gtwiz_userdata_rx, 56 | output wire [63:0] hb4_gtwiz_userdata_rx, 57 | output wire [63:0] hb5_gtwiz_userdata_rx, 58 | output wire [63:0] hb6_gtwiz_userdata_rx, 59 | output wire [63:0] hb7_gtwiz_userdata_rx, 60 | 61 | // DL Reset 62 | output wire gtwiz_buffbypass_rx_done_in, 63 | output wire gtwiz_buffbypass_tx_done_in, 64 | input wire gtwiz_reset_all_out, 65 | input wire gtwiz_reset_rx_datapath_out, 66 | output wire gtwiz_reset_rx_done_in, 67 | output wire gtwiz_reset_tx_done_in, 68 | output wire gtwiz_userclk_rx_active_in, 69 | output wire gtwiz_userclk_tx_active_in, 70 | output wire hb_gtwiz_reset_all_in, 71 | 72 | // output hb0_gtwiz_userclk_rx_usrclk2_int, 73 | output init_done_int, 74 | output [3:0] init_retry_ctr_int, 75 | output [0:0] gtwiz_reset_tx_done_vio_sync, 76 | output [0:0] gtwiz_reset_rx_done_vio_sync, 77 | output [0:0] gtwiz_buffbypass_tx_done_vio_sync, 78 | output [0:0] gtwiz_buffbypass_rx_done_vio_sync, 79 | output [0:0] gtwiz_buffbypass_tx_error_vio_sync, 80 | output [0:0] gtwiz_buffbypass_rx_error_vio_sync, 81 | 82 | // IBERT Logic 83 | input [79:0] drpaddr_in, 84 | input [7:0] drpclk_in, 85 | input [127:0] drpdi_in, 86 | input [7:0] drpen_in, 87 | input [7:0] drpwe_in, 88 | input [7:0] eyescanreset_in, 89 | input [7:0] rxlpmen_in, 90 | input [23:0] rxrate_in, 91 | input [39:0] txdiffctrl_in, 92 | input [39:0] txpostcursor_in, 93 | input [39:0] txprecursor_in, 94 | output [127:0] drpdo_out, 95 | output [7:0] drprdy_out 96 | 97 | -------------------------------------------------------------------------------- /scripts/adding_fire3: -------------------------------------------------------------------------------- 1 | 2 | //-------------------------------------------------------------------------------------------------------------------- 3 | wire [0:0] gtwiz_buffbypass_rx_reset_int; 4 | wire [0:0] hb0_gtwiz_buffbypass_rx_reset_int; 5 | assign gtwiz_buffbypass_rx_reset_int[0:0] = hb0_gtwiz_buffbypass_rx_reset_int; 6 | 7 | //-------------------------------------------------------------------------------------------------------------------- 8 | wire [0:0] gtwiz_buffbypass_rx_start_user_int; 9 | wire [0:0] hb0_gtwiz_buffbypass_rx_start_user_int = 1'b0; 10 | assign gtwiz_buffbypass_rx_start_user_int[0:0] = hb0_gtwiz_buffbypass_rx_start_user_int; 11 | 12 | //-------------------------------------------------------------------------------------------------------------------- 13 | wire [0:0] gtwiz_buffbypass_rx_done_int; 14 | wire [0:0] hb0_gtwiz_buffbypass_rx_done_int; 15 | assign hb0_gtwiz_buffbypass_rx_done_int = gtwiz_buffbypass_rx_done_int[0:0]; 16 | 17 | //-------------------------------------------------------------------------------------------------------------------- 18 | wire [0:0] gtwiz_buffbypass_rx_error_int; 19 | wire [0:0] hb0_gtwiz_buffbypass_rx_error_int; 20 | assign hb0_gtwiz_buffbypass_rx_error_int = gtwiz_buffbypass_rx_error_int[0:0]; 21 | 22 | 23 | -------------------------------------------------------------------------------- /scripts/adding_fire4: -------------------------------------------------------------------------------- 1 | 2 | DLx_phy_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_rx_done_0_inst ( 3 | .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), 4 | .i_in (gtwiz_reset_rx_done_int[0]), 5 | .o_out (gtwiz_buffbypass_rx_done_vio_sync[0]) 6 | ); 7 | -------------------------------------------------------------------------------- /scripts/adding_fire5: -------------------------------------------------------------------------------- 1 | assign cclk = gtwiz_userclk_tx_usrclk2_int; 2 | assign rclk = hb_gtwiz_reset_clk_freerun_buf_int; 3 | 4 | // DLx INSTANCE 5 | // =================================================================================================================== 6 | wire gtwiz_userclk_tx_usrclk3_int; 7 | //wire tx_clk_402MHz; 8 | wire tx_clk_201MHz; 9 | assign tx_clk_402MHz = gtwiz_userclk_tx_usrclk2_int; // Clock is used by DLx and DLx drivers 10 | assign tx_clk_201MHz = gtwiz_userclk_tx_usrclk3_int; // Clock is used by DLx and DLx drivers 11 | 12 | assign opt_gckn = gtwiz_userclk_tx_usrclk2_int; 13 | assign clk_156_25MHz = hb_gtwiz_reset_clk_freerun_buf_int; 14 | // wire gnd; 15 | // wire vdn; 16 | // assign gnd = 1'b0; 17 | // assign vdn = 1'b1; 18 | 19 | // wire [23:0] rxbufstatus_out; 20 | // wire [7:0] rxbufreset_in; 21 | // assign rxbufreset_in =8'b00000000; 22 | 23 | assign gtwiz_userclk_rx_active_in = gtwiz_userclk_rx_active_int; 24 | assign gtwiz_userclk_tx_active_in = gtwiz_userclk_tx_active_int; 25 | assign hb_gtwiz_reset_all_DLx_reset = gtwiz_reset_all_out; 26 | assign hb_gtwiz_reset_rx_datapath_DLx_int = gtwiz_reset_rx_datapath_out; 27 | assign gtwiz_reset_rx_done_in = gtwiz_reset_rx_done_int; 28 | assign gtwiz_reset_tx_done_in = gtwiz_reset_tx_done_int; 29 | assign gtwiz_buffbypass_rx_done_in = gtwiz_reset_rx_done_int; 30 | assign gtwiz_buffbypass_tx_done_in = gtwiz_buffbypass_tx_done_int; 31 | assign hb_gtwiz_reset_all_in = hb_gtwiz_reset_all_int; 32 | -------------------------------------------------------------------------------- /scripts/adding_ice1: -------------------------------------------------------------------------------- 1 | // output hb0_gtwiz_userclk_rx_usrclk2_int, 2 | output hb_gtwiz_reset_clk_freerun_buf_int, 3 | output init_done_int, 4 | output [3:0] init_retry_ctr_int, 5 | output [0:0] gtwiz_reset_tx_done_vio_sync, 6 | output [0:0] gtwiz_reset_rx_done_vio_sync, 7 | output [0:0] gtwiz_buffbypass_tx_done_vio_sync, 8 | output [0:0] gtwiz_buffbypass_rx_done_vio_sync, 9 | output [0:0] gtwiz_buffbypass_tx_error_vio_sync, 10 | output [0:0] gtwiz_buffbypass_rx_error_vio_sync, 11 | input [0:0] hb_gtwiz_reset_all_vio_int, 12 | input [0:0] hb0_gtwiz_reset_tx_pll_and_datapath_int, 13 | input [0:0] hb0_gtwiz_reset_tx_datapath_int, 14 | input [0:0] hb_gtwiz_reset_rx_pll_and_datapath_vio_int, 15 | input [0:0] hb_gtwiz_reset_rx_datapath_vio_int, 16 | 17 | 18 | // --@ Josh Andersen added port declarations to interface with DLx drivers 19 | output wire [31:0] dlx_config_info, 20 | output wire [31:0] ro_dlx_version, 21 | output wire [2:0] dlx_tlx_init_flit_depth, 22 | output wire [511:0] dlx_tlx_flit, 23 | output wire dlx_tlx_flit_crc_err, 24 | output wire dlx_tlx_flit_credit, 25 | output wire dlx_tlx_flit_valid, 26 | output wire dlx_tlx_link_up, 27 | input wire [3:0] tlx_dlx_debug_encode, 28 | input wire [31:0] tlx_dlx_debug_info, 29 | input wire [511:0] tlx_dlx_flit, 30 | input wire tlx_dlx_flit_valid, 31 | input wire send_first, 32 | input wire ocde, 33 | output wire tx_clk_402MHz, 34 | output wire tx_clk_201MHz, 35 | 36 | input wire [31:0] reg_04_val, 37 | output wire reg_04_hwwe, 38 | output wire [31:0] reg_04_update, 39 | output wire reg_05_hwwe, 40 | output wire [31:0] reg_05_update, 41 | output wire reg_06_hwwe, 42 | output wire [31:0] reg_06_update, 43 | output wire reg_07_hwwe, 44 | output wire [31:0] reg_07_update, 45 | 46 | input wire tsm_state2_to_3, 47 | input wire tsm_state4_to_5, 48 | input wire tsm_state6_to_1, 49 | 50 | // IBERT Logic 51 | input [79:0] drpaddr_in, 52 | input [7:0] drpclk_in, 53 | input [127:0] drpdi_in, 54 | input [7:0] drpen_in, 55 | input [7:0] drpwe_in, 56 | input [7:0] eyescanreset_in, 57 | input [7:0] rxlpmen_in, 58 | input [23:0] rxrate_in, 59 | input [39:0] txdiffctrl_in, 60 | input [39:0] txpostcursor_in, 61 | input [39:0] txprecursor_in, 62 | output [127:0] drpdo_out, 63 | output [7:0] drprdy_out 64 | 65 | -------------------------------------------------------------------------------- /scripts/adding_ice2: -------------------------------------------------------------------------------- 1 | wire [0:0] gtwiz_buffbypass_tx_reset_int; 2 | wire [0:0] hb0_gtwiz_buffbypass_tx_reset_int; 3 | assign gtwiz_buffbypass_tx_reset_int[0:0] = hb0_gtwiz_buffbypass_tx_reset_int; 4 | 5 | //-------------------------------------------------------------------------------------------------------------------- 6 | wire [0:0] gtwiz_buffbypass_tx_start_user_int; 7 | wire [0:0] hb0_gtwiz_buffbypass_tx_start_user_int = 1'b0; 8 | assign gtwiz_buffbypass_tx_start_user_int[0:0] = hb0_gtwiz_buffbypass_tx_start_user_int; 9 | 10 | //-------------------------------------------------------------------------------------------------------------------- 11 | wire [0:0] gtwiz_buffbypass_tx_done_int; 12 | wire [0:0] hb0_gtwiz_buffbypass_tx_done_int; 13 | assign hb0_gtwiz_buffbypass_tx_done_int = gtwiz_buffbypass_tx_done_int[0:0]; 14 | 15 | //-------------------------------------------------------------------------------------------------------------------- 16 | wire [0:0] gtwiz_buffbypass_tx_error_int; 17 | wire [0:0] hb0_gtwiz_buffbypass_tx_error_int; 18 | assign hb0_gtwiz_buffbypass_tx_error_int = gtwiz_buffbypass_tx_error_int[0:0]; 19 | 20 | //-------------------------------------------------------------------------------------------------------------------- 21 | wire [0:0] gtwiz_buffbypass_rx_reset_int; 22 | wire [0:0] hb0_gtwiz_buffbypass_rx_reset_int; 23 | assign gtwiz_buffbypass_rx_reset_int[0:0] = hb0_gtwiz_buffbypass_rx_reset_int; 24 | 25 | //-------------------------------------------------------------------------------------------------------------------- 26 | wire [0:0] gtwiz_buffbypass_rx_start_user_int; 27 | wire [0:0] hb0_gtwiz_buffbypass_rx_start_user_int = 1'b0; 28 | assign gtwiz_buffbypass_rx_start_user_int[0:0] = hb0_gtwiz_buffbypass_rx_start_user_int; 29 | 30 | //-------------------------------------------------------------------------------------------------------------------- 31 | wire [0:0] gtwiz_buffbypass_rx_done_int; 32 | wire [0:0] hb0_gtwiz_buffbypass_rx_done_int; 33 | assign hb0_gtwiz_buffbypass_rx_done_int = gtwiz_buffbypass_rx_done_int[0:0]; 34 | 35 | //-------------------------------------------------------------------------------------------------------------------- 36 | wire [0:0] gtwiz_buffbypass_rx_error_int; 37 | wire [0:0] hb0_gtwiz_buffbypass_rx_error_int; 38 | assign hb0_gtwiz_buffbypass_rx_error_int = gtwiz_buffbypass_rx_error_int[0:0]; 39 | 40 | //-------------------------------------------------------------------------------------------------------------------- 41 | -------------------------------------------------------------------------------- /scripts/adding_ice3: -------------------------------------------------------------------------------- 1 | // Output of IO Differential Buffer 2 | wire freerun_clk; // 300 MHz 3 | assign freerun_clk_out = freerun_clk; //LIF added for i2c clock 4 | //--LIF 4/17`define DLX_FREERUN_BUFG_GT 5 | `ifdef DLX_FREERUN_BUFG_GT 6 | 7 | // 250Mhz on bermuda 8 | IBUFDS_GTE4 #( 9 | .REFCLK_HROW_CK_SEL(2'b00) // ODIV2 = O 10 | ) u_refclk ( 11 | .I (freerun_clk_p), 12 | .IB (freerun_clk_n), 13 | .CEB (1'b0), 14 | .O (), 15 | .ODIV2 (freerun_clk) 16 | ); 17 | 18 | 19 | // INIT_CLK = GT_REFCLK / 2 20 | BUFG_GT u_init_clk ( 21 | .CE (1'b1), 22 | .CEMASK (1'b0), 23 | .CLR (1'b0), 24 | .CLRMASK (1'b0), 25 | .DIV (3'd1), 26 | .I (freerun_clk), 27 | .O (hb_gtwiz_reset_clk_freerun_buf_int) 28 | ); 29 | 30 | `else 31 | // BUFGCE_DIV: General Clock Buffer with Divide Function 32 | // Virtex UltraScale+ 33 | // Xilinx HDL Language Template, version 2017.1 34 | BUFGCE_DIV #( 35 | .BUFGCE_DIVIDE(2), // 1-8 36 | // Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins 37 | .IS_CE_INVERTED(1'b0), // Optional inversion for CE 38 | .IS_CLR_INVERTED(1'b0), // Optional inversion for CLR 39 | .IS_I_INVERTED(1'b0) // Optional inversion for I 40 | ) 41 | BUFGCE_DIV_inst ( 42 | .O (hb_gtwiz_reset_clk_freerun_buf_int), // 1-bit output: Buffer 43 | .CE (1'b1), // 1-bit input: Buffer enable 44 | .CLR (1'b0), // 1-bit input: Asynchronous clear 45 | .I (freerun_clk) // 1-bit input: Buffer 46 | ); 47 | 48 | 49 | 50 | IBUFDS #( 51 | .DQS_BIAS("FALSE") // (FALSE, TRUE) 52 | ) 53 | IBUFDS_freerun ( 54 | .O (freerun_clk), // 1-bit output: Buffer output 55 | .I (freerun_clk_p), // 1-bit input: Diff_p buffer input (connect directly to top-level port) 56 | .IB (freerun_clk_n) // 1-bit input: Diff_n buffer input (connect directly to top-level port) 57 | ); 58 | `endif 59 | -------------------------------------------------------------------------------- /scripts/adding_ice4: -------------------------------------------------------------------------------- 1 | // BUFFER BYPASS CONTROLLER RESETS 2 | // =================================================================================================================== 3 | 4 | // The TX buffer bypass controller helper block should be held in reset until the TX user clocking network helper 5 | // block which drives it is active 6 | // (* DONT_TOUCH = "TRUE" *) 7 | // DLx_phy_example_reset_synchronizer reset_synchronizer_gtwiz_buffbypass_tx_reset_inst ( 8 | // .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), 9 | // .rst_in (~hb0_gtwiz_userclk_tx_active_int), 10 | // .rst_out (hb0_gtwiz_buffbypass_tx_reset_int) 11 | // ); 12 | 13 | // The RX buffer bypass controller helper block should be held in reset until the RX user clocking network helper 14 | // block which drives it is active and the TX buffer bypass sequence has completed for this loopback configuration 15 | // (* DONT_TOUCH = "TRUE" *) 16 | // DLx_phy_example_reset_synchronizer reset_synchronizer_gtwiz_buffbypass_rx_reset_inst ( 17 | // .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), 18 | // //.clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), 19 | // .rst_in (~hb0_gtwiz_userclk_rx_active_int || ~hb0_gtwiz_buffbypass_tx_done_int), 20 | // .rst_out (hb0_gtwiz_buffbypass_rx_reset_int) 21 | // ); 22 | 23 | -------------------------------------------------------------------------------- /scripts/adding_ice6: -------------------------------------------------------------------------------- 1 | ,.rxgearboxslip_in (rxgearboxslip_int) 2 | ,.rxpolarity_in (rxpolarity_int) 3 | ,.txheader_in (txheader_int) 4 | ,.txsequence_in (txsequence_int) 5 | ,.rxdatavalid_out (rxdatavalid_int) 6 | ,.rxheader_out (rxheader_int) 7 | ,.rxheadervalid_out (rxheadervalid_int) 8 | ,.rxpmaresetdone_out (rxpmaresetdone_int) 9 | ,.rxstartofseq_out (rxstartofseq_int) 10 | ,.txpmaresetdone_out (txpmaresetdone_int) 11 | //,.txprgdivresetdone_out (txprgdivresetdone_int) 12 | //,.rxbufstatus_ (outrxbufstatus_out) 13 | //,.rxbufreset_in (rxbufreset_in) 14 | 15 | 16 | ,.drpaddr_in (drpaddr_in) 17 | ,.drpclk_in (drpclk_in) 18 | ,.drpdi_in (drpdi_in) 19 | ,.drpen_in (drpen_in) 20 | ,.drpwe_in (drpwe_in) 21 | ,.eyescanreset_in (eyescanreset_in) 22 | ,.rxlpmen_in (rxlpmen_in) 23 | ,.rxrate_in (rxrate_in) 24 | ,.txdiffctrl_in (txdiffctrl_in) 25 | ,.txpostcursor_in (txpostcursor_in) 26 | ,.txprecursor_in (txprecursor_in) 27 | ,.drpdo_out (drpdo_out) 28 | ,.drprdy_out (drprdy_out) 29 | ); 30 | 31 | 32 | -------------------------------------------------------------------------------- /scripts/adding_ice7: -------------------------------------------------------------------------------- 1 | */ 2 | assign rxusrclk_int = {8{1'b0}}; 3 | assign rxusrclk2_int = {8{1'b0}}; 4 | assign gtwiz_userclk_rx_active_out = gtwiz_userclk_tx_active_int; 5 | // ------------------------------------------------------------------------------------------------------------------- 6 | // Transmitter buffer bypass controller helper block 7 | // ------------------------------------------------------------------------------------------------------------------- 8 | wire gtwiz_buffbypass_tx_resetdone_int; 9 | 10 | assign gtwiz_buffbypass_tx_resetdone_int = gtwiz_reset_tx_done_out; 11 | 12 | wire gtwiz_buffbypass_rx_resetdone_int; 13 | 14 | assign gtwiz_buffbypass_rx_resetdone_int = gtwiz_reset_rx_done_out; 15 | 16 | wire [7:0] txphaligndone_int; 17 | wire [7:0] txphinitdone_int; 18 | wire [7:0] txdlysresetdone_int; 19 | wire [7:0] txsyncout_int; 20 | wire [7:0] txsyncdone_int; 21 | wire [7:0] txphdlyreset_int; 22 | wire [7:0] txphalign_int; 23 | wire [7:0] txphalignen_int; 24 | wire [7:0] txphdlypd_int; 25 | wire [7:0] txphinit_int; 26 | wire [7:0] txphovrden_int; 27 | wire [7:0] txdlysreset_int; 28 | wire [7:0] txdlybypass_int; 29 | wire [7:0] txdlyen_int; 30 | wire [7:0] txdlyovrden_int; 31 | wire [7:0] txphdlytstclk_int; 32 | wire [7:0] txdlyhold_int; 33 | wire [7:0] txdlyupdown_int; 34 | wire [7:0] txsyncmode_int; 35 | wire [7:0] txsyncallin_int; 36 | wire [7:0] txsyncin_int; 37 | 38 | wire [7:0] rxphaligndone_int; 39 | wire [7:0] rxdlysresetdone_int; 40 | wire [7:0] rxsyncout_int; 41 | wire [7:0] rxsyncdone_int; 42 | wire [7:0] rxphdlyreset_int; 43 | wire [7:0] rxphalign_int; 44 | wire [7:0] rxphalignen_int; 45 | wire [7:0] rxphdlypd_int; 46 | wire [7:0] rxphovrden_int; 47 | wire [7:0] rxdlysreset_int; 48 | wire [7:0] rxdlybypass_int; 49 | wire [7:0] rxdlyen_int; 50 | wire [7:0] rxdlyovrden_int; 51 | wire [7:0] rxsyncmode_int; 52 | wire [7:0] rxsyncallin_int; 53 | wire [7:0] rxsyncin_int; 54 | 55 | 56 | 57 | wire [7:0] gtpowergood_out; 58 | wire [7:0] txprgdivresetdone_out; 59 | -------------------------------------------------------------------------------- /scripts/all_shells4fire.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | # This executes several scripts. They assume Xilinx example has been prepared and will create the corresponding host FIRE files. 24 | ./gtwiz_example_top2phy_wrap_prep1.sh 25 | ./gtwiz_example_top2phy_wrap_prep2.sh 26 | ./gtwiz_reset.sh 27 | ./gtwiz_userclk_tx_dlx.sh 28 | ./gtwiz_bit_sync.sh 29 | ./gtwiz_init_dlx.sh 30 | ./gtwiz_wrapper.sh 31 | -------------------------------------------------------------------------------- /scripts/all_shells4ice.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | # This executes several scripts. They assume Xilinx example has been prepared and will create the corresponding device ICE files. 24 | ./gtwiz_phy2wrap_ref_4ice.sh 25 | ./gtwiz_wrap_ref2wrap0_4ice.sh 26 | ./gtwiz_reset.sh 27 | ./gtwiz_userclk_tx_dlx.sh 28 | ./gtwiz_bit_sync.sh 29 | ./gtwiz_init_dlx.sh 30 | ./gtwiz_wrapper0_4ice.sh 31 | -------------------------------------------------------------------------------- /scripts/gtwiz_bit_sync.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | sed -e 's/gtwizard_ultrascale_0/DLx_phy/g' \ 24 | ./gtwizard_ultrascale_0_example_bit_sync.v > DLx_phy_example_bit_sync.v 25 | -------------------------------------------------------------------------------- /scripts/gtwiz_example_top2phy_wrap_prep2.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | # Preparing first DDIMM attachment 24 | sed -e 's/DLx_phy_example_wrapper/DLx_phy_example_wrapper0/' \ 25 | -e 's/module DLx_phy_example_top /module dlx_phy_wrap0/' ./dlx_phy_wrap_ref.v > dlx_phy_wrap0.v 26 | 27 | # Preparing second DDIMM attachment 28 | if [ -d "../../gtwizard_ultrascale_1" ]; then 29 | sed -e 's/DLx_phy_example_wrapper/DLx_phy_example_wrapper1/' \ 30 | -e 's/module DLx_phy_example_top /module dlx_phy_wrap1/' ./dlx_phy_wrap_ref.v > dlx_phy_wrap1.v 31 | fi 32 | 33 | if [ -d "../../gtwizard_ultrascale_2" ]; then 34 | # Preparing third DDIMM attachment if any 35 | sed -e 's/DLx_phy_example_wrapper/DLx_phy_example_wrapper2/' \ 36 | -e 's/module DLx_phy_example_top /module dlx_phy_wrap2/' ./dlx_phy_wrap_ref.v > dlx_phy_wrap2.v 37 | fi 38 | 39 | if [ -d "../../gtwizard_ultrascale_3" ]; then 40 | # Preparing forth DDIMM attachment if any 41 | sed -e 's/DLx_phy_example_wrapper/DLx_phy_example_wrapper3/' \ 42 | -e 's/module DLx_phy_example_top /module dlx_phy_wrap3/' ./dlx_phy_wrap_ref.v > dlx_phy_wrap3.v 43 | fi 44 | -------------------------------------------------------------------------------- /scripts/gtwiz_init_dlx.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | sed -e 's/gtwizard_ultrascale_0/DLx_phy/g' -e '/parameter real P_FREERUN_FREQUENCY/ c \ parameter real P_FREERUN_FREQUENCY = 195.3125,' ./gtwizard_ultrascale_0_example_init.v > DLx_phy_example_init.v 24 | -------------------------------------------------------------------------------- /scripts/gtwiz_reset.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | sed -e 's/gtwizard_ultrascale_0/DLx_phy/g' \ 24 | ./gtwizard_ultrascale_0_example_reset_sync.v > DLx_phy_example_reset_sync.v 25 | -------------------------------------------------------------------------------- /scripts/gtwiz_userclk_tx_dlx.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | sed -e 's/gtwizard_ultrascale_0/DLx_phy/g' \ 24 | -e '/parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1/ c \ parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1,\n parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK3 = 2' \ 25 | -e '64 a \ parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK3 = 2' \ 26 | -e '/output wire gtwiz_userclk_tx_usrclk2_out,/ a \ output wire gtwiz_userclk_tx_usrclk3_out,' \ 27 | -e '/P_USRCLK2_DIV =/ a\ localparam integer P_USRCLK3_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK3) - 1;\n localparam [2:0] P_USRCLK3_DIV = P_USRCLK3_INT_DIV[2:0];' \ 28 | -e "124 i \ if (P_FREQ_RATIO_USRCLK_TO_USRCLK3 == 1)\n\ 29 | assign gtwiz_userclk_tx_usrclk3_out = gtwiz_userclk_tx_usrclk_out;\n\ 30 | else begin\n\ 31 | BUFG_GT bufg_gt_usrclk3_inst (\n\ 32 | .CE (1'b1),\n\ 33 | .CEMASK (1'b0),\n\ 34 | .CLR (gtwiz_userclk_tx_reset_in),\n\ 35 | .CLRMASK (1'b0),\n\ 36 | .DIV (P_USRCLK3_DIV),\n\ 37 | .I (gtwiz_userclk_tx_srcclk_in),\n\ 38 | .O (gtwiz_userclk_tx_usrclk3_out)\n\ 39 | );\n\ 40 | end\n" ./gtwizard_ultrascale_0_example_gtwiz_userclk_tx.v > DLx_phy_example_gtwiz_userclk_tx.v 41 | -------------------------------------------------------------------------------- /scripts/gtwiz_wrap_ref2wrap0_4ice.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | # the following already appears later in the file 24 | # sed -i "/bit_synchronizer_vio_gtwiz_reset_tx_done_0_inst/{N;N;N;N; a \ \n\ 25 | # \/\/ Synchronize gtwiz_buffbypass_rx_done into the free-running clock domain for VIO usage\n\ 26 | # wire [0:0] gtwiz_buffbypass_rx_done_vio_sync;\n\ 27 | #\n\ 28 | # DLx_phy_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_rx_done_0_inst (\n\ 29 | # \.clk_in (hb_gtwiz_reset_clk_freerun_buf_int),\n\ 30 | # \.i_in (gtwiz_reset_rx_done_int[0]),\n\ 31 | # \.o_out (gtwiz_buffbypass_rx_done_vio_sync[0])\n\ 32 | # );\n 33 | #} " dlx_phy_wrap_ref.v 34 | 35 | # Preparing ICE DDIMM attachment 36 | # \nparameter GEMINI_NOT_APOLLO = 0\n) ( 37 | sed -e 's/DLx_phy_example_wrapper/DLx_phy_example_wrapper0/' \ 38 | -e 's/module DLx_phy_example_top /module dlx_phy_wrap0 #(\nparameter GEMINI_NOT_APOLLO = 0\n) /' ./dlx_phy_wrap_ref.v > dlx_phy_wrap0.v 39 | -------------------------------------------------------------------------------- /scripts/gtwiz_wrapper.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | # First we generate a reference file, that will be used to create a wrapper for each DDIMM port 24 | # Before outputing, removing the comma helps avoids misinterpretation 25 | # We also need to escape : "," "[" with an "\" otherwise we can't replace the desired lines. 26 | # when appending, before the appended string a "\" is required to take into account the space of the line beginning 27 | # firt we make a general replacement 28 | # then we "append" (a) the clk3 line 29 | # comment the rx section 30 | # remove the gtpowergood "wire" line 31 | # we use " instead of ' when we already use ' in strings ! 32 | # finally save created file into a reference wrapper file. 33 | 34 | echo "Creating DLx_phy_example_wrapper_ref.v" 35 | sed -e 's/gtwizard_ultrascale_0/DLx_phy/g' \ 36 | -e '/output wire \[0\:0\] gtwiz_userclk_tx_usrclk2_out/a\ ,output wire \[0\:0\] gtwiz_userclk_tx_usrclk3_out'\ 37 | -e '/output wire \[0\:0\] gtwiz_userclk_rx_usrclk_out/s/^/\/\//'\ 38 | -e '/output wire \[0\:0\] gtwiz_userclk_rx_usrclk2_out/s/^/\/\//'\ 39 | -e '/output wire \[7\:0\] gtpowergood_out/d'\ 40 | -e '/output wire \[7\:0\] txprgdivresetdone_out/s/^/\/\//'\ 41 | -e '/example_gtwiz_userclk_rx/,+6 s/^/\/\//' \ 42 | -e "s/.*localparam \[191\:0\] P_CHANNEL_ENABLE = 192.*/ localparam \[191\:0\] P_CHANNEL_ENABLE = 192\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000;/"\ 43 | -e 's/calc_pk_mc_idx(31)/calc_pk_mc_idx(16)/'\ 44 | -e "/wire \[7\:0\] txoutclk_int/a\ wire gtwiz_userclk_tx_active_int;"\ 45 | -e "/gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out),/a\ .gtwiz_userclk_tx_usrclk3_out (gtwiz_userclk_tx_usrclk3_out),\n .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_int)"\ 46 | -e '/gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out)/d'\ 47 | -e '/.gtwiz_userclk_tx_usrclk3_out (gtwiz_userclk_tx_usrclk3_out),/c\ .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_int)/'\ 48 | -e "/assign txusrclk2_int = {8{gtwiz_userclk_tx_usrclk2_out}}/a\ assign gtwiz_userclk_tx_active_out = gtwiz_userclk_tx_active_int;"\ 49 | -e 's/rxoutclk_int\[P_RX_MASTER_CH_PACKED_IDX\]/txoutclk_int\[P_RX_MASTER_CH_PACKED_IDX\]/'\ 50 | -e '/Drive RXUSRCLK and RXUSRCLK2/a \ /*'\ 51 | -e "/= {8{gtwiz_userclk_rx_usrclk2_out}}/a\ *\/\n\ 52 | assign rxusrclk_int = \{8\{1\'b0\}\}; \n\ 53 | assign rxusrclk2_int = \{8\{1\'b0\}\}; \n\ 54 | assign gtwiz_userclk_rx_active_out = gtwiz_userclk_tx_active_int;\n\n"\ 55 | -e '/Required assignment to expose the GTPOWERGOOD/,+1 s/^/\/\//' \ 56 | -e "/wire \[7\:\0] gtpowergood_int;/a\ wire [7:0] txprgdivresetdone_out;"\ 57 | -e "/,.gtwiz_userclk_tx_active_in /a\ ,.gtpowergood_out (gtpowergood_out)"\ 58 | -e "s/active_in (gtwiz_userclk_rx_active_out)/active_in (gtwiz_userclk_tx_active_int)/"\ 59 | -e '/gtpowergood_out (gtpowergood_int)/d'\ 60 | -e 's/(rxusrclk/(txusrclk/'\ 61 | -e '/txprgdivresetdone_out (txprgdivresetdone_out)/d'\ 62 | ./gtwizard_ultrascale_0_example_wrapper.v > DLx_phy_example_wrapper_ref.v 63 | 64 | # -e '/(rxrate_in)/ s/^/\/\//' \ 65 | # -e "/,.gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_out)/s/^/\/\//"\ 66 | # -e '/txprgdivresetdone_out (txprgdivresetdone_out)/d';a\,.rxpolarity_in (rxpolarity_in)\ 67 | 68 | sed -i '/assign gtwiz_userclk_rx_active_out = gtwiz_userclk_tx_active_int;/r adding_fire1' DLx_phy_example_wrapper_ref.v 69 | echo "ref wrapper written" 70 | 71 | # -e "/txoutclk_int/a wire gtwiz_userclk_tx_active_int"\ 72 | # Tuning the reference wrapper for port 0 73 | sed -e 's/module DLx_phy_example_wrapper/module DLx_phy_example_wrapper0/'\ 74 | -e 's/DLx_phy DLx_phy_inst (/gtwizard_ultrascale_0 DLx_phy_inst (/g' \ 75 | DLx_phy_example_wrapper_ref.v > ./DLx_phy_example_wrapper0.v 76 | 77 | # Tuning the reference wrapper for port 1 78 | if [ -d "../../gtwizard_ultrascale_1" ]; then 79 | sed -e 's/module DLx_phy_example_wrapper/module DLx_phy_example_wrapper1/'\ 80 | -e 's/DLx_phy DLx_phy_inst (/gtwizard_ultrascale_1 DLx_phy_inst (/g' \ 81 | DLx_phy_example_wrapper_ref.v > ./DLx_phy_example_wrapper1.v 82 | fi 83 | 84 | # Tuning the reference wrapper for port 2 85 | if [ -d "../../gtwizard_ultrascale_2" ]; then 86 | sed -e 's/module DLx_phy_example_wrapper/module DLx_phy_example_wrapper2/'\ 87 | -e 's/DLx_phy DLx_phy_inst (/gtwizard_ultrascale_2 DLx_phy_inst (/g' \ 88 | DLx_phy_example_wrapper_ref.v > ./DLx_phy_example_wrapper2.v 89 | fi 90 | # Tuning the reference wrapper for port 3 91 | if [ -d "../../gtwizard_ultrascale_3" ]; then 92 | sed -e 's/module DLx_phy_example_wrapper/module DLx_phy_example_wrapper3/'\ 93 | -e 's/DLx_phy DLx_phy_inst (/gtwizard_ultrascale_3 DLx_phy_inst (/g' \ 94 | DLx_phy_example_wrapper_ref.v > ./DLx_phy_example_wrapper3.v 95 | fi 96 | 97 | # AC : the following is actually just a simple copy 98 | sed -e 's/gtwizard_ultrascale_0/DLx_phy/g' \ 99 | ./gtwizard_ultrascale_0_example_wrapper_functions.v > DLx_phy_example_wrapper_functions.v 100 | -------------------------------------------------------------------------------- /scripts/gtwiz_wrapper0_4ice.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## 3 | ## Copyright 2022 International Business Machines 4 | ## 5 | ## Licensed under the Apache License, Version 2.0 (the "License"); 6 | ## you may not use this file except in compliance with the License. 7 | ## You may obtain a copy of the License at 8 | ## http://www.apache.org/licenses/LICENSE-2.0 9 | ## 10 | ## The patent license granted to you in Section 3 of the License, as applied 11 | ## to the "Work," hereby includes implementations of the Work in physical form. 12 | ## 13 | ## Unless required by applicable law or agreed to in writing, the reference design 14 | ## distributed under the License is distributed on an "AS IS" BASIS, 15 | ## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | ## See the License for the specific language governing permissions and 17 | ## limitations under the License. 18 | ## 19 | ## The background Specification upon which this is based is managed by and available from 20 | ## the OpenCAPI Consortium. More information can be found at https://opencapi.org. 21 | ## 22 | 23 | # First we generate a reference file, that will be used to create a wrapper for the device port 24 | # Before output, removing the comma helps avoiding misinterpretation 25 | # We also need to escape : "," "[" with an "\" otherwise we can't replace the desired lines. 26 | # When appending, before the appended string a "\" is required to take into account the space of the line beginning 27 | # First we make a general replacement 28 | # Then we "append" (a) the clk3 line 29 | # Comment the rx section 30 | # Remove the gtpowergood "wire" line 31 | # We use " char instead of ' char when we already use ' char in strings ! 32 | # We finally save created file into a reference wrapper file. 33 | 34 | echo "Creating DLx_phy_example_wrapper_ref.v" 35 | sed -e 's/gtwizard_ultrascale_0/DLx_phy/g' \ 36 | -e "s/gtrefclk00/gtrefclk01/g" \ 37 | -e "s/qpll0/qpll1/g" \ 38 | -e '/output wire \[0\:0\] gtwiz_userclk_tx_usrclk2_out/a\ ,output wire \[0\:0\] gtwiz_userclk_tx_usrclk3_out'\ 39 | -e '/output wire \[0\:0\] gtwiz_userclk_rx_usrclk_out/s/^/\/\//'\ 40 | -e '/output wire \[0\:0\] gtwiz_userclk_rx_usrclk2_out/s/^/\/\//'\ 41 | -e '/output wire \[7\:0\] gtpowergood_out/d'\ 42 | -e '/output wire \[7\:0\] txprgdivresetdone_out/s/^/\/\//'\ 43 | -e '/example_gtwiz_userclk_rx/,+6 s/^/\/\//' \ 44 | -e "s/.*localparam \[191\:0\] P_CHANNEL_ENABLE = 192.*/ localparam \[191\:0\] P_CHANNEL_ENABLE = 192\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000;/"\ 45 | -e 's/calc_pk_mc_idx(7)/calc_pk_mc_idx(16)/'\ 46 | -e "/wire \[7\:0\] txoutclk_int/a\ wire gtwiz_userclk_tx_active_int;"\ 47 | -e "/gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out),/a\ .gtwiz_userclk_tx_usrclk3_out (gtwiz_userclk_tx_usrclk3_out),\n .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_int)"\ 48 | -e '/gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out)/d'\ 49 | -e '/.gtwiz_userclk_tx_usrclk3_out (gtwiz_userclk_tx_usrclk3_out),/c\ .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_int)/'\ 50 | -e "/assign txusrclk2_int = {8{gtwiz_userclk_tx_usrclk2_out}}/a\ assign gtwiz_userclk_tx_active_out = gtwiz_userclk_tx_active_int;"\ 51 | -e 's/rxoutclk_int\[P_RX_MASTER_CH_PACKED_IDX\]/txoutclk_int\[P_RX_MASTER_CH_PACKED_IDX\]/'\ 52 | -e '/Drive RXUSRCLK and RXUSRCLK2/a \ /*'\ 53 | -e "/wire \[7:0\] gtpowergood_int;/d"\ 54 | -e '/Required assignment to expose the GTPOWERGOOD/,+1 s/^/\/\//' \ 55 | -e "/wire \[7\:\0] gtpowergood_int;/a\ wire [7:0] txprgdivresetdone_out;"\ 56 | -e "/,.gtwiz_userclk_tx_active_in /a\ ,.gtpowergood_out (gtpowergood_out)"\ 57 | -e "s/active_in (gtwiz_userclk_rx_active_out)/active_in (gtwiz_userclk_tx_active_int)/"\ 58 | -e '/gtpowergood_out (gtpowergood_int)/d'\ 59 | -e 's/(rxusrclk/(txusrclk/'\ 60 | -e "/,.gtrefclk01_in (gtrefclk01_in)/,+2 d"\ 61 | -e "/,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out)/a\ ,.gtrefclk00_in (gtrefclk01_in)\n\ 62 | ,.qpll0outclk_out (qpll1outclk_out)\n\ 63 | ,.qpll0outrefclk_out (qpll1outrefclk_out)"\ 64 | -e "/wire \[7:0\] gtpowergood_out;/a\ wire \[7:0\] txprgdivresetdone_out;\n"\ 65 | ./gtwizard_ultrascale_0_example_wrapper.v > DLx_phy_example_wrapper_ref.v 66 | 67 | # -e '/(rxrate_in)/ s/^/\/\//' \ 68 | # -e "/,.gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_out)/s/^/\/\//"\ 69 | # -e '/txprgdivresetdone_out (txprgdivresetdone_out)/d';a\,.rxpolarity_in (rxpolarity_in)\ 70 | 71 | sed -i '/assign gtwiz_userclk_rx_active_out = gtwiz_userclk_tx_active_int;/r adding_fire1' DLx_phy_example_wrapper_ref.v 72 | sed -i '/assign rxusrclk2_int = {8{gtwiz_userclk_rx_usrclk2_out}}/r adding_ice7' DLx_phy_example_wrapper_ref.v 73 | #echo "Reference wrapper written" 74 | 75 | # -e "/txoutclk_int/a wire gtwiz_userclk_tx_active_int"\ 76 | # Tuning the reference wrapper for port 0 77 | sed -e 's/module DLx_phy_example_wrapper/module DLx_phy_example_wrapper0/'\ 78 | -e 's/ DLx_phy DLx_phy_inst (/gtwizard_ultrascale_0 DLx_phy (/g' \ 79 | DLx_phy_example_wrapper_ref.v > ./DLx_phy_example_wrapper0.v 80 | 81 | 82 | # AC : the following is actually just a simple copy 83 | sed -e 's/gtwizard_ultrascale_0/DLx_phy/g' \ 84 | ./gtwizard_ultrascale_0_example_wrapper_functions.v > DLx_phy_example_wrapper_functions.v 85 | 86 | --------------------------------------------------------------------------------