├── README.md ├── aic_load_fw ├── aicwf_txq_prealloc.h ├── .gitignore ├── Kconfig ├── rwnx_version_gen.h ├── aicwf_rx_prealloc.h ├── aicwf_debug.h ├── aicbluetooth.h ├── md5.h ├── aicwf_txq_prealloc.c ├── aic_compat_8800d80x2.h ├── aic_bluetooth_main.c ├── aic_compat_8800d80.h ├── aicwf_rx_prealloc.c ├── Makefile ├── md5.c ├── aic_txrxif.h └── aicwf_usb.h ├── fw ├── aic8800 │ ├── fmacfw.bin │ ├── fw_adid.bin │ ├── m2d_ota.bin │ ├── fmacfw_m2d.bin │ ├── fmacfw_rf.bin │ ├── fw_adid_rf.bin │ ├── fw_patch.bin │ ├── fw_adid_u03.bin │ ├── fw_ble_scan.bin │ ├── fw_patch_rf.bin │ ├── fw_patch_u03.bin │ ├── fw_patch_table.bin │ ├── fmacfw_no_msg_ep.bin │ ├── fmacfw_no_msg_ep_rf.bin │ ├── fw_patch_table_u03.bin │ ├── fw_ble_scan_ad_filter_ldo.bin │ ├── fw_ble_scan_ad_filter_dcdc.bin │ └── aic_userconfig.txt ├── aic8800D80 │ ├── calibmode_8800d80.bin │ ├── fmacfw_8800d80_u02.bin │ ├── fw_adid_8800d80_u02.bin │ ├── fmacfw_8800d80_h_u02.bin │ ├── fmacfw_8800d80_u02_ipc.bin │ ├── fw_ble_scan_ad_filter.bin │ ├── fw_patch_8800d80_u02.bin │ ├── lmacfw_rf_8800d80_u02.bin │ ├── fw_patch_8800d80_u02_ext0.bin │ ├── fw_patch_table_8800d80_u02.bin │ ├── aic_powerlimit_8800d80.txt │ └── aic_userconfig_8800d80.txt ├── aic8800DC │ ├── fw_adid_8800dc_u02.bin │ ├── lmacfw_rf_8800dc.bin │ ├── fw_adid_8800dc_u02h.bin │ ├── fw_patch_8800dc_u02.bin │ ├── fw_patch_8800dc_u02h.bin │ ├── fmacfw_calib_8800dc_u02.bin │ ├── fmacfw_patch_8800dc_u02.bin │ ├── fmacfw_calib_8800dc_h_u02.bin │ ├── fmacfw_patch_8800dc_h_u02.bin │ ├── fw_patch_table_8800dc_u02.bin │ ├── fmacfw_patch_8800dc_ipc_u02.bin │ ├── fmacfw_patch_tbl_8800dc_u02.bin │ ├── fw_patch_table_8800dc_u02h.bin │ ├── fmacfw_patch_tbl_8800dc_h_u02.bin │ ├── fmacfw_patch_tbl_8800dc_ipc_u02.bin │ ├── aic_powerlimit_8800dc.txt │ ├── aic_powerlimit_8800dw.txt │ ├── aic_userconfig_8800dc.txt │ └── aic_userconfig_8800dw.txt └── aic8800D80X2 │ ├── fmacfw_8800d80x2.bin │ ├── lmacfw_rf_8800d80x2.bin │ ├── fw_adid_8800d80x2_u03.bin │ ├── fw_patch_8800d80x2_u03.bin │ ├── fw_patch_table_8800d80x2_u03.bin │ ├── aic_powerlimit_8800d80x2.txt │ └── aic_userconfig_8800d80x2.txt ├── aic8800_fdrv ├── .gitignore ├── rwnx_version_gen.h ├── rwnx_version.h ├── aicwf_compat_8800d80.h ├── aicwf_wext_linux.h ├── aicwf_compat_8800d80x2.h ├── rwnx_gki.h ├── rwnx_pci.h ├── rwnx_gki.c ├── rwnx_v7.h ├── rwnx_irqs.h ├── rwnx_dini.h ├── rwnx_msg_rx.h ├── rwnx_main.h ├── rwnx_wakelock.h ├── aicwf_rx_prealloc.h ├── aic_priv_cmd.h ├── rwnx_fw_trace.h ├── rwnx_strs.h ├── ipc_compat.h ├── rwnx_utils.c ├── Kconfig ├── rwnx_cfgfile.h ├── aicwf_debug.h ├── rwnx_mesh.c ├── rwnx_fw_trace.c ├── rwnx_mesh.h ├── sdio_host.h ├── usb_host.h ├── md5.h ├── rwnx_tdls.h ├── lmac_types.h ├── rwnx_mod_params.h ├── rwnx_irqs.c ├── rwnx_testmode.h ├── aicwf_compat_8800dc.h ├── aic_br_ext.h ├── rwnx_pci.c ├── rwnx_wakelock.c ├── aicwf_compat_8800d80.c ├── aicwf_tcp_ack.h ├── aicwf_compat_8800d80x2.c ├── rwnx_bfmer.c ├── rwnx_utils.h ├── aicwf_sdio.h ├── rwnx_bfmer.h ├── rwnx_cmds.h ├── rwnx_prof.h ├── sdio_host.c ├── aicwf_usb.h ├── rwnx_radar.h ├── rwnx_platform.h ├── usb_host.c ├── rwnx_v7.c ├── rwnx_mu_group.h ├── md5.c ├── reg_access.h ├── rwnx_tx.h └── rwnx_testmode.c ├── Kconfig └── Makefile /README.md: -------------------------------------------------------------------------------- 1 | # aic8800 2 | The aic8800 WiFi diver 3 | -------------------------------------------------------------------------------- /aic_load_fw/aicwf_txq_prealloc.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | void aicwf_prealloc_txq_free(void); 4 | 5 | -------------------------------------------------------------------------------- /fw/aic8800/fmacfw.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenIPC/aic8800/master/fw/aic8800/fmacfw.bin -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/OpenIPC/aic8800/master/fw/aic8800D80X2/fw_patch_table_8800d80x2_u03.bin -------------------------------------------------------------------------------- /fw/aic8800DC/fmacfw_patch_tbl_8800dc_ipc_u02.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenIPC/aic8800/master/fw/aic8800DC/fmacfw_patch_tbl_8800dc_ipc_u02.bin -------------------------------------------------------------------------------- /aic_load_fw/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.ko 3 | *.order 4 | *.symvers 5 | *.o.d 6 | *.o.cmd 7 | *.ko.cmd 8 | *.mod 9 | *.mod.c* 10 | 11 | .tmp_versions/ 12 | -------------------------------------------------------------------------------- /aic_load_fw/Kconfig: -------------------------------------------------------------------------------- 1 | config AIC_LOADFW_SUPPORT 2 | tristate "AIC8800 Load Firmware Support" 3 | help 4 | This is support for aic load firmware driver. 5 | 6 | -------------------------------------------------------------------------------- /aic_load_fw/rwnx_version_gen.h: -------------------------------------------------------------------------------- 1 | #define RWNX_VERS_REV "1a4b0054d2M (master)" 2 | #define RWNX_VERS_MOD "6.4.3.0" 3 | #define RWNX_VERS_BANNER "rwnx v6.4.3.0 - 1a4b0054d2M (master)" 4 | #define RELEASE_DATE "2024_0929_2e313139" 5 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_version_gen.h: -------------------------------------------------------------------------------- 1 | #define RWNX_VERS_REV "1a4b0054d2M (master)" 2 | #define RWNX_VERS_MOD "6.4.3.0" 3 | #define RWNX_VERS_BANNER "rwnx v6.4.3.0 - 1a4b0054d2M (master)" 4 | #define RELEASE_DATE "2024_0929_2e313139" 5 | 6 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_version.h: -------------------------------------------------------------------------------- 1 | #ifndef _RWNX_VERSION_H_ 2 | #define _RWNX_VERSION_H_ 3 | 4 | #include "rwnx_version_gen.h" 5 | 6 | static inline void rwnx_print_version(void) 7 | { 8 | AICWFDBG(LOGINFO, RWNX_VERS_BANNER"\n"); 9 | } 10 | 11 | #endif /* _RWNX_VERSION_H_ */ 12 | -------------------------------------------------------------------------------- /Kconfig: -------------------------------------------------------------------------------- 1 | config AIC_WLAN_SUPPORT 2 | bool "AIC wireless Support" 3 | default n 4 | help 5 | This is support for aic wireless chip. 6 | 7 | if AIC_WLAN_SUPPORT 8 | source "drivers/net/wireless/aic8800/aic8800_fdrv/Kconfig" 9 | source "drivers/net/wireless/aic8800/aic_load_fw/Kconfig" 10 | endif 11 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_compat_8800d80.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int rwnx_plat_userconfig_load_8800d80(struct rwnx_hw *rwnx_hw); 4 | #ifdef CONFIG_POWER_LIMIT 5 | int rwnx_plat_powerlimit_load_8800d80(struct rwnx_hw *rwnx_hw); 6 | #endif 7 | int aicwf_set_rf_config_8800d80(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm); 8 | 9 | 10 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_wext_linux.h: -------------------------------------------------------------------------------- 1 | 2 | struct scanu_result_wext{ 3 | struct list_head scanu_re_list; 4 | struct cfg80211_bss *bss; 5 | struct scanu_result_ind *ind; 6 | u32_l *payload; 7 | }; 8 | 9 | void aicwf_set_wireless_ext( struct net_device *ndev, struct rwnx_hw *rwnx_hw); 10 | void aicwf_scan_complete_event(struct net_device *dev); 11 | 12 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_compat_8800d80x2.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int rwnx_plat_userconfig_load_8800d80x2(struct rwnx_hw *rwnx_hw); 4 | #ifdef CONFIG_POWER_LIMIT 5 | int rwnx_plat_powerlimit_load_8800d80x2(struct rwnx_hw *rwnx_hw); 6 | #endif 7 | int aicwf_set_rf_config_8800d80x2(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm); 8 | 9 | 10 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_gki.h: -------------------------------------------------------------------------------- 1 | #ifndef __RWNX_GKI_H 2 | #define __RWNX_GKI_H 3 | 4 | #ifdef CONFIG_GKI 5 | void rwnx_gki_skb_append(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list); 6 | #define rwnx_skb_append rwnx_gki_skb_append 7 | #else 8 | #define rwnx_skb_append skb_append 9 | #endif//CONFIG_GKI 10 | 11 | #endif 12 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_pci.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_pci.h 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | 11 | #ifndef _RWNX_PCI_H_ 12 | #define _RWNX_PCI_H_ 13 | 14 | int rwnx_pci_register_drv(void); 15 | void rwnx_pci_unregister_drv(void); 16 | 17 | #endif /* _RWNX_PCI_H_ */ 18 | -------------------------------------------------------------------------------- /fw/aic8800DC/aic_powerlimit_8800dc.txt: -------------------------------------------------------------------------------- 1 | # AIC POWERLIMIT 2024/0311/1456 2 | # Max tx power reference: Linux wireless regulatory database for CRDA 3 | # https://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git/tree/db.txt 4 | 5 | # Table 1: 6 | ## 2.4G,#2# 7 | ## START 8 | ## CN US 9 | CH01 15 18 10 | CH02 15 18 11 | CH03 15 18 12 | CH04 15 18 13 | CH05 15 18 14 | CH06 15 18 15 | CH07 15 18 16 | CH08 15 18 17 | CH09 15 18 18 | CH10 15 18 19 | CH11 15 18 20 | CH12 12 NA 21 | CH13 12 NA 22 | CH14 NA NA 23 | ## END 24 | 25 | -------------------------------------------------------------------------------- /fw/aic8800DC/aic_powerlimit_8800dw.txt: -------------------------------------------------------------------------------- 1 | # AIC POWERLIMIT 2024/0311/1456 2 | # Max tx power reference: Linux wireless regulatory database for CRDA 3 | # https://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git/tree/db.txt 4 | 5 | # Table 1: 6 | ## 2.4G,#2# 7 | ## START 8 | ## CN US 9 | CH01 15 18 10 | CH02 15 18 11 | CH03 15 18 12 | CH04 15 18 13 | CH05 15 18 14 | CH06 15 18 15 | CH07 15 18 16 | CH08 15 18 17 | CH09 15 18 18 | CH10 15 18 19 | CH11 15 18 20 | CH12 12 NA 21 | CH13 12 NA 22 | CH14 NA NA 23 | ## END 24 | 25 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_gki.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | 5 | void rwnx_gki_skb_append(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list) 6 | { 7 | unsigned long flags; 8 | struct sk_buff *prev = old; 9 | struct sk_buff *next = prev->next; 10 | spin_lock_irqsave(&list->lock, flags); 11 | WRITE_ONCE(newsk->next, next); 12 | WRITE_ONCE(newsk->prev, prev); 13 | WRITE_ONCE(next->prev, newsk); 14 | WRITE_ONCE(prev->next, newsk); 15 | list->qlen++; 16 | spin_unlock_irqrestore(&list->lock, flags); 17 | } 18 | 19 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_v7.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_v7.h 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | 11 | #ifndef _RWNX_V7_H_ 12 | #define _RWNX_V7_H_ 13 | 14 | #include 15 | #include "rwnx_platform.h" 16 | 17 | int rwnx_v7_platform_init(struct pci_dev *pci_dev, 18 | struct rwnx_plat **rwnx_plat); 19 | 20 | #endif /* _RWNX_V7_H_ */ 21 | -------------------------------------------------------------------------------- /fw/aic8800/aic_userconfig.txt: -------------------------------------------------------------------------------- 1 | # AIC USERCONFIG 2021/0911/2127 2 | 3 | # txpwr_idx 4 | enable=1 5 | dsss=9 6 | ofdmlowrate_2g4=10 7 | ofdm64qam_2g4=10 8 | ofdm256qam_2g4=9 9 | ofdm1024qam_2g4=8 10 | ofdmlowrate_5g=10 11 | ofdm64qam_5g=9 12 | ofdm256qam_5g=9 13 | ofdm1024qam_5g=8 14 | 15 | # txpwr_ofst 16 | ofst_enable=0 17 | ofst_chan_1_4=0 18 | ofst_chan_5_9=0 19 | ofst_chan_10_13=0 20 | ofst_chan_36_64=0 21 | ofst_chan_100_120=0 22 | ofst_chan_122_140=0 23 | ofst_chan_142_165=0 24 | 25 | # xtal cap 26 | xtal_enable=0 27 | xtal_cap=24 28 | xtal_cap_fine=31 29 | 30 | # END -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_irqs.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_irqs.h 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | #ifndef _RWNX_IRQS_H_ 11 | #define _RWNX_IRQS_H_ 12 | 13 | #include 14 | 15 | /* IRQ handler to be registered by platform driver */ 16 | irqreturn_t rwnx_irq_hdlr(int irq, void *dev_id); 17 | 18 | void rwnx_task(unsigned long data); 19 | 20 | #endif /* _RWNX_IRQS_H_ */ 21 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_dini.h: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file rwnx_dini.h 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | 11 | #ifndef _RWNX_DINI_H_ 12 | #define _RWNX_DINI_H_ 13 | 14 | #include 15 | #include "rwnx_platform.h" 16 | 17 | int rwnx_dini_platform_init(struct pci_dev *pci_dev, 18 | struct rwnx_plat **rwnx_plat); 19 | 20 | #endif /* _RWNX_DINI_H_ */ 21 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_msg_rx.h: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file rwnx_msg_rx.h 5 | * 6 | * @brief RX function declarations 7 | * 8 | * Copyright (C) RivieraWaves 2012-2019 9 | * 10 | **************************************************************************************** 11 | */ 12 | 13 | #ifndef _RWNX_MSG_RX_H_ 14 | #define _RWNX_MSG_RX_H_ 15 | 16 | void rwnx_rx_handle_msg(struct rwnx_hw *rwnx_hw, struct ipc_e2a_msg *msg); 17 | void rwnx_rx_handle_print(struct rwnx_hw *rwnx_hw, u8 *msg, u32 len); 18 | 19 | #endif /* _RWNX_MSG_RX_H_ */ 20 | -------------------------------------------------------------------------------- /aic_load_fw/aicwf_rx_prealloc.h: -------------------------------------------------------------------------------- 1 | #ifndef _AICWF_RX_PREALLOC_H_ 2 | #define _AICWF_RX_PREALLOC_H_ 3 | 4 | #ifdef CONFIG_PREALLOC_RX_SKB 5 | 6 | struct rx_buff { 7 | struct list_head queue; 8 | unsigned char *data; 9 | u32 len; 10 | uint8_t *start; 11 | uint8_t *end; 12 | uint8_t *read; 13 | }; 14 | 15 | struct aicwf_rx_buff_list { 16 | struct list_head rxbuff_list; 17 | atomic_t rxbuff_list_len; 18 | }; 19 | 20 | struct rx_buff *aicwf_prealloc_rxbuff_alloc(spinlock_t *lock); 21 | void aicwf_prealloc_rxbuff_free(struct rx_buff *rxbuff, spinlock_t *lock); 22 | int aicwf_prealloc_init(void); 23 | void aicwf_prealloc_exit(void); 24 | int aicwf_rxbuff_size_get(void); 25 | #endif 26 | #endif /* _AICWF_RX_PREALLOC_H_ */ -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_main.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_main.h 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | 11 | #ifndef _RWNX_MAIN_H_ 12 | #define _RWNX_MAIN_H_ 13 | 14 | #include "rwnx_defs.h" 15 | 16 | int rwnx_cfg80211_init(struct rwnx_plat *rwnx_plat, void **platform_data); 17 | void rwnx_cfg80211_deinit(struct rwnx_hw *rwnx_hw); 18 | extern int testmode; 19 | extern u8 chip_id; 20 | extern u8 chip_sub_id; 21 | extern u8 chip_mcu_id; 22 | 23 | #define CHIP_ID_H_MASK 0xC0 24 | #define IS_CHIP_ID_H() ((chip_id & CHIP_ID_H_MASK) == CHIP_ID_H_MASK) 25 | 26 | #endif /* _RWNX_MAIN_H_ */ 27 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_wakelock.h: -------------------------------------------------------------------------------- 1 | #ifndef __RWNX_WAKELOCK_H 2 | #define __RWNX_WAKELOCK_H 3 | 4 | #include 5 | #include 6 | #include 7 | 8 | struct wakeup_source *rwnx_wakeup_init(const char *name); 9 | void rwnx_wakeup_deinit(struct wakeup_source *ws); 10 | 11 | struct wakeup_source *rwnx_wakeup_register(struct device *dev, const char *name); 12 | void rwnx_wakeup_unregister(struct wakeup_source *ws); 13 | 14 | void rwnx_wakeup_lock(struct wakeup_source *ws); 15 | void rwnx_wakeup_unlock(struct wakeup_source *ws); 16 | void rwnx_wakeup_lock_timeout(struct wakeup_source *ws, unsigned int msec); 17 | 18 | void aicwf_wakeup_lock_init(struct rwnx_hw *rwnx_hw); 19 | void aicwf_wakeup_lock_deinit(struct rwnx_hw *rwnx_hw); 20 | 21 | #endif 22 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_rx_prealloc.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _AICWF_RX_PREALLOC_H_ 3 | #define _AICWF_RX_PREALLOC_H_ 4 | 5 | #ifdef CONFIG_PREALLOC_RX_SKB 6 | 7 | struct rx_buff { 8 | struct list_head queue; 9 | unsigned char *data; 10 | u32 len; 11 | uint8_t *start; 12 | uint8_t *end; 13 | uint8_t *read; 14 | }; 15 | 16 | struct aicwf_rx_buff_list { 17 | struct list_head rxbuff_list; 18 | atomic_t rxbuff_list_len; 19 | }; 20 | 21 | extern struct rx_buff *aicwf_prealloc_rxbuff_alloc(spinlock_t *lock); 22 | extern void aicwf_prealloc_rxbuff_free(struct rx_buff *rxbuff, spinlock_t *lock); 23 | extern int aicwf_prealloc_init(void); 24 | extern void aicwf_prealloc_exit(void); 25 | extern int aicwf_rxbuff_size_get(void); 26 | #endif 27 | #endif /* _AICWF_RX_PREALLOC_H_ */ 28 | -------------------------------------------------------------------------------- /aic8800_fdrv/aic_priv_cmd.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file private_cmd.h 5 | * 6 | * Copyright (C) Aicsemi 2018-2024 7 | * 8 | ****************************************************************************** 9 | */ 10 | 11 | #ifndef _AIC_PRIV_CMD_H_ 12 | #define _AIC_PRIV_CMD_H_ 13 | 14 | #include "rwnx_defs.h" 15 | 16 | typedef struct _android_wifi_priv_cmd { 17 | char *buf; 18 | int used_len; 19 | int total_len; 20 | } android_wifi_priv_cmd; 21 | 22 | #ifdef CONFIG_COMPAT 23 | typedef struct _compat_android_wifi_priv_cmd { 24 | compat_caddr_t buf; 25 | int used_len; 26 | int total_len; 27 | } compat_android_wifi_priv_cmd; 28 | #endif /* CONFIG_COMPAT */ 29 | 30 | int android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd); 31 | 32 | #endif /* _AIC_PRIV_CMD_H_ */ 33 | 34 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_fw_trace.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * rwnx_fw_trace.h 5 | * 6 | * Copyright (C) RivieraWaves 2017-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | 11 | #ifndef _RWNX_FW_TRACE_H_ 12 | #define _RWNX_FW_TRACE_H_ 13 | 14 | #include 15 | #include 16 | #include 17 | 18 | #define FW_LOG_SIZE (10240) 19 | 20 | struct rwnx_fw_log_buf { 21 | uint8_t *data; 22 | uint8_t *start; 23 | uint8_t *end; 24 | uint8_t *dataend; 25 | uint32_t size; 26 | }; 27 | 28 | struct rwnx_fw_log { 29 | struct rwnx_fw_log_buf buf; 30 | spinlock_t lock; 31 | }; 32 | 33 | int rwnx_fw_log_init(struct rwnx_fw_log *fw_log); 34 | void rwnx_fw_log_deinit(struct rwnx_fw_log *fw_log); 35 | #endif /* _RWNX_FW_TRACE_H_ */ 36 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_strs.h: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file rwnx_strs.h 5 | * 6 | * @brief Miscellaneous debug strings 7 | * 8 | * Copyright (C) RivieraWaves 2014-2019 9 | * 10 | **************************************************************************************** 11 | */ 12 | 13 | #ifndef _RWNX_STRS_H_ 14 | #define _RWNX_STRS_H_ 15 | 16 | #ifdef CONFIG_RWNX_FHOST 17 | 18 | #define RWNX_ID2STR(tag) "Cmd" 19 | 20 | #else 21 | #include "lmac_msg.h" 22 | 23 | #define RWNX_ID2STR(tag) (((MSG_T(tag) < ARRAY_SIZE(rwnx_id2str)) && \ 24 | (rwnx_id2str[MSG_T(tag)]) && \ 25 | ((rwnx_id2str[MSG_T(tag)])[MSG_I(tag)])) ? \ 26 | (rwnx_id2str[MSG_T(tag)])[MSG_I(tag)] : "unknown") 27 | 28 | extern const char *const *rwnx_id2str[TASK_LAST_EMB + 1]; 29 | #endif /* CONFIG_RWNX_FHOST */ 30 | 31 | #endif /* _RWNX_STRS_H_ */ 32 | -------------------------------------------------------------------------------- /aic8800_fdrv/ipc_compat.h: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file ipc_compat.h 5 | * 6 | * Copyright (C) RivieraWaves 2011-2019 7 | * 8 | **************************************************************************************** 9 | */ 10 | 11 | #ifndef _IPC_H_ 12 | #define _IPC_H_ 13 | 14 | #define __INLINE static __attribute__((__always_inline__)) inline 15 | 16 | #define __ALIGN4 __aligned(4) 17 | 18 | #define ASSERT_ERR(condition) \ 19 | do { \ 20 | if (unlikely(!(condition))) { \ 21 | printk(KERN_ERR "%s:%d:ASSERT_ERR(" #condition ")\n", __FILE__, __LINE__); \ 22 | } \ 23 | } while(0) 24 | 25 | #endif /* _IPC_H_ */ 26 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_utils.c: -------------------------------------------------------------------------------- 1 | /** 2 | * rwnx_utils.c 3 | * 4 | * IPC utility function definitions 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | */ 8 | #include "rwnx_utils.h" 9 | #include "rwnx_defs.h" 10 | #include "rwnx_rx.h" 11 | #include "rwnx_tx.h" 12 | #include "rwnx_msg_rx.h" 13 | #include "rwnx_debugfs.h" 14 | #include "rwnx_prof.h" 15 | #include "ipc_host.h" 16 | 17 | 18 | extern int get_testmode(void); 19 | extern void get_fw_path(char* fw_path); 20 | extern int testmode; 21 | extern char aic_fw_path[200]; 22 | 23 | int rwnx_init_aic(struct rwnx_hw *rwnx_hw) 24 | { 25 | RWNX_DBG(RWNX_FN_ENTRY_STR); 26 | #ifdef AICWF_SDIO_SUPPORT 27 | aicwf_sdio_host_init(&(rwnx_hw->sdio_env), NULL, NULL, rwnx_hw); 28 | #else 29 | aicwf_usb_host_init(&(rwnx_hw->usb_env), NULL, NULL, rwnx_hw); 30 | #endif 31 | rwnx_cmd_mgr_init(rwnx_hw->cmd_mgr); 32 | 33 | testmode = get_testmode(); 34 | memset(aic_fw_path, 0, 200); 35 | get_fw_path(aic_fw_path); 36 | 37 | return 0; 38 | } 39 | 40 | -------------------------------------------------------------------------------- /fw/aic8800D80/aic_powerlimit_8800d80.txt: -------------------------------------------------------------------------------- 1 | # AIC POWERLIMIT 2024/0218/1206 2 | # Max tx power reference: Linux wireless regulatory database for CRDA 3 | # https://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git/tree/db.txt 4 | 5 | # Table 1: 6 | ## 2.4G,#2# 7 | ## START 8 | ## CN US 9 | CH01 15 18 10 | CH02 15 18 11 | CH03 15 18 12 | CH04 15 18 13 | CH05 15 18 14 | CH06 15 18 15 | CH07 15 18 16 | CH08 15 18 17 | CH09 15 18 18 | CH10 15 18 19 | CH11 15 18 20 | CH12 12 NA 21 | CH13 12 NA 22 | CH14 NA NA 23 | ## END 24 | 25 | # Table 2: 26 | ## 5G,#2# 27 | ## START 28 | ## CN US 29 | # 5G Band 1 30 | CH36 15 18 31 | CH40 15 18 32 | CH44 15 18 33 | CH48 15 18 34 | # 5G Band 2 35 | CH52 15 19 36 | CH56 15 19 37 | CH60 15 19 38 | CH64 15 19 39 | # 5G Band 3 40 | CH100 NA 19 41 | CH104 NA 19 42 | CH108 NA 19 43 | CH112 NA 19 44 | CH116 NA 19 45 | CH120 NA 19 46 | CH124 NA 19 47 | CH128 NA 19 48 | CH132 NA 19 49 | CH136 NA 19 50 | CH140 NA 19 51 | CH144 NA NA 52 | # 5G Band 4 53 | CH149 19 19 54 | CH153 19 19 55 | CH157 19 19 56 | CH161 19 19 57 | CH165 19 19 58 | ## END 59 | 60 | -------------------------------------------------------------------------------- /fw/aic8800D80X2/aic_powerlimit_8800d80x2.txt: -------------------------------------------------------------------------------- 1 | # AIC POWERLIMIT 2024/0218/1206 2 | # Max tx power reference: Linux wireless regulatory database for CRDA 3 | # https://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git/tree/db.txt 4 | 5 | # Table 1: 6 | ## 2.4G,#2# 7 | ## START 8 | ## CN US 9 | CH01 15 18 10 | CH02 15 18 11 | CH03 15 18 12 | CH04 15 18 13 | CH05 15 18 14 | CH06 15 18 15 | CH07 15 18 16 | CH08 15 18 17 | CH09 15 18 18 | CH10 15 18 19 | CH11 15 18 20 | CH12 12 NA 21 | CH13 12 NA 22 | CH14 NA NA 23 | ## END 24 | 25 | # Table 2: 26 | ## 5G,#2# 27 | ## START 28 | ## CN US 29 | # 5G Band 1 30 | CH36 15 18 31 | CH40 15 18 32 | CH44 15 18 33 | CH48 15 18 34 | # 5G Band 2 35 | CH52 15 19 36 | CH56 15 19 37 | CH60 15 19 38 | CH64 15 19 39 | # 5G Band 3 40 | CH100 NA 19 41 | CH104 NA 19 42 | CH108 NA 19 43 | CH112 NA 19 44 | CH116 NA 19 45 | CH120 NA 19 46 | CH124 NA 19 47 | CH128 NA 19 48 | CH132 NA 19 49 | CH136 NA 19 50 | CH140 NA 19 51 | CH144 NA NA 52 | # 5G Band 4 53 | CH149 19 19 54 | CH153 19 19 55 | CH157 19 19 56 | CH161 19 19 57 | CH165 19 19 58 | ## END 59 | 60 | -------------------------------------------------------------------------------- /aic8800_fdrv/Kconfig: -------------------------------------------------------------------------------- 1 | config AIC8800_WLAN_SUPPORT 2 | tristate "AIC8800 wlan Support" 3 | help 4 | This is support for aic wifi driver. 5 | 6 | #choice 7 | # depends on AIC8800_WLAN_SUPPORT 8 | # prompt "Select 8800 support platform" 9 | # 10 | # config PLATFORM_ROCHCHIP 11 | # bool "PLATFORM_ROCHCHIP" 12 | # depends on AIC8800_WLAN_SUPPORT 13 | # 14 | # config PLATFORM_ALLWINNER 15 | # bool "PLATFORM_ALLWINNER" 16 | # depends on AIC8800_WLAN_SUPPORT 17 | # 18 | # config PLATFORM_AMLOGIC 19 | # bool "PLATFORM_AMLOGIC" 20 | # depends on AIC8800_WLAN_SUPPORT 21 | # 22 | # config PLATFORM_UBUNTU 23 | # bool "PLATFORM_UBUNTU" 24 | # depends on AIC8800_WLAN_SUPPORT 25 | # 26 | #endchoice 27 | # 28 | #config USE_5G 29 | # bool "AIC8800 force enable 5G" 30 | # ---help--- 31 | # This is parameter that force enable 5G. 32 | # 33 | #config HE_FOR_OLD_KERNEL 34 | # bool "AIC8800 support AX for old kernel" 35 | # ---help--- 36 | # This is parameter that enable AX for old kernel. 37 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_cfgfile.h: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file rwnx_cfgfile.h 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | **************************************************************************************** 9 | */ 10 | 11 | #ifndef _RWNX_CFGFILE_H_ 12 | #define _RWNX_CFGFILE_H_ 13 | 14 | /* 15 | * Structure used to retrieve information from the Config file used at Initialization time 16 | */ 17 | struct rwnx_conf_file { 18 | u8 mac_addr[ETH_ALEN]; 19 | }; 20 | 21 | /* 22 | * Structure used to retrieve information from the PHY Config file used at Initialization time 23 | */ 24 | struct rwnx_phy_conf_file { 25 | struct phy_trd_cfg_tag trd; 26 | struct phy_karst_cfg_tag karst; 27 | }; 28 | 29 | int rwnx_parse_configfile(struct rwnx_hw *rwnx_hw, const char *filename, 30 | struct rwnx_conf_file *config); 31 | 32 | int rwnx_parse_phy_configfile(struct rwnx_hw *rwnx_hw, const char *filename, 33 | struct rwnx_phy_conf_file *config, int path); 34 | 35 | #endif /* _RWNX_CFGFILE_H_ */ 36 | -------------------------------------------------------------------------------- /aic_load_fw/aicwf_debug.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | #define RWNX_FN_ENTRY_STR ">>> %s()\n", __func__ 4 | 5 | 6 | 7 | /* message levels */ 8 | #define LOGERROR 0x0001 9 | #define LOGINFO 0x0002 10 | #define LOGTRACE 0x0004 11 | #define LOGDEBUG 0x0008 12 | #define LOGDATA 0x0010 13 | 14 | extern int aicwf_dbg_level; 15 | void rwnx_data_dump(char* tag, void* data, unsigned long len); 16 | 17 | #define AICWF_LOG "AICWFDBG(" 18 | 19 | #define AICWFDBG(level, args, arg...) \ 20 | do { \ 21 | if (aicwf_dbg_level & level) { \ 22 | printk(AICWF_LOG#level")\t" args, ##arg); \ 23 | } \ 24 | } while (0) 25 | 26 | #define RWNX_DBG(fmt, ...) \ 27 | do { \ 28 | if (aicwf_dbg_level & LOGTRACE) { \ 29 | printk(AICWF_LOG"LOGTRACE)\t"fmt , ##__VA_ARGS__); \ 30 | } \ 31 | } while (0) 32 | 33 | 34 | 35 | #if 0 36 | #define RWNX_DBG(fmt, ...) \ 37 | do { \ 38 | if (aicwf_dbg_level & LOGTRACE) { \ 39 | printk(AICWF_LOG"LOGTRACE"")\t" fmt, ##__VA_ARGS__); \ 40 | } \ 41 | } while (0) 42 | #define AICWFDBG(args, level) \ 43 | do { \ 44 | if (aicwf_dbg_level & level) { \ 45 | printk(AICWF_LOG"(%s)\t" ,#level); \ 46 | printf args; \ 47 | } \ 48 | } while (0) 49 | #endif 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_debug.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | #define RWNX_FN_ENTRY_STR ">>> %s()\n", __func__ 4 | 5 | 6 | 7 | /* message levels */ 8 | #define LOGERROR 0x0001 9 | #define LOGINFO 0x0002 10 | #define LOGTRACE 0x0004 11 | #define LOGDEBUG 0x0008 12 | #define LOGDATA 0x0010 13 | 14 | extern int aicwf_dbg_level; 15 | void rwnx_data_dump(char* tag, void* data, unsigned long len); 16 | 17 | #define AICWF_LOG "AICWFDBG(" 18 | 19 | #define AICWFDBG(level, args, arg...) \ 20 | do { \ 21 | if (aicwf_dbg_level & level) { \ 22 | printk(AICWF_LOG#level")\t" args, ##arg); \ 23 | } \ 24 | } while (0) 25 | 26 | #define RWNX_DBG(fmt, ...) \ 27 | do { \ 28 | if (aicwf_dbg_level & LOGTRACE) { \ 29 | printk(AICWF_LOG"LOGTRACE)\t"fmt , ##__VA_ARGS__); \ 30 | } \ 31 | } while (0) 32 | 33 | 34 | 35 | #if 0 36 | #define RWNX_DBG(fmt, ...) \ 37 | do { \ 38 | if (aicwf_dbg_level & LOGTRACE) { \ 39 | printk(AICWF_LOG"LOGTRACE"")\t" fmt, ##__VA_ARGS__); \ 40 | } \ 41 | } while (0) 42 | #define AICWFDBG(args, level) \ 43 | do { \ 44 | if (aicwf_dbg_level & level) { \ 45 | printk(AICWF_LOG"(%s)\t" ,#level); \ 46 | printf args; \ 47 | } \ 48 | } while (0) 49 | #endif 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_mesh.c: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file rwnx_mesh.c 5 | * 6 | * Copyright (C) RivieraWaves 2016-2019 7 | * 8 | **************************************************************************************** 9 | */ 10 | 11 | /** 12 | * INCLUDE FILES 13 | **************************************************************************************** 14 | */ 15 | 16 | #include "rwnx_mesh.h" 17 | 18 | /** 19 | * FUNCTION DEFINITIONS 20 | **************************************************************************************** 21 | */ 22 | 23 | struct rwnx_mesh_proxy *rwnx_get_mesh_proxy_info(struct rwnx_vif *p_rwnx_vif, u8 *p_sta_addr, bool local) 24 | { 25 | struct rwnx_mesh_proxy *p_mesh_proxy = NULL; 26 | struct rwnx_mesh_proxy *p_cur_proxy; 27 | 28 | /* Look for proxied devices with provided address */ 29 | list_for_each_entry(p_cur_proxy, &p_rwnx_vif->ap.proxy_list, list) { 30 | if (p_cur_proxy->local != local) { 31 | continue; 32 | } 33 | 34 | if (!memcmp(&p_cur_proxy->ext_sta_addr, p_sta_addr, ETH_ALEN)) { 35 | p_mesh_proxy = p_cur_proxy; 36 | break; 37 | } 38 | } 39 | 40 | /* Return the found information */ 41 | return p_mesh_proxy; 42 | } 43 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_fw_trace.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_fw_trace.c 5 | * 6 | * Copyright (C) RivieraWaves 2017-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include "rwnx_fw_trace.h" 18 | 19 | int rwnx_fw_log_init(struct rwnx_fw_log *fw_log) 20 | { 21 | u8 *buf = kmalloc(FW_LOG_SIZE, GFP_KERNEL); 22 | if (!buf) 23 | return -ENOMEM; 24 | 25 | fw_log->buf.data = buf; 26 | fw_log->buf.start = fw_log->buf.data; 27 | fw_log->buf.size = 0; 28 | fw_log->buf.end = fw_log->buf.data; 29 | fw_log->buf.dataend = fw_log->buf.data + FW_LOG_SIZE; 30 | spin_lock_init(&fw_log->lock); 31 | 32 | printk("fw_log_init: %lx, %lx\n", (unsigned long)fw_log->buf.start, (unsigned long)(fw_log->buf.dataend)); 33 | return 0; 34 | } 35 | 36 | void rwnx_fw_log_deinit(struct rwnx_fw_log *fw_log) 37 | { 38 | if (!fw_log) 39 | return; 40 | 41 | if (fw_log->buf.data) 42 | kfree(fw_log->buf.data); 43 | fw_log->buf.start = NULL; 44 | fw_log->buf.end = NULL; 45 | fw_log->buf.size = 0; 46 | } 47 | 48 | -------------------------------------------------------------------------------- /fw/aic8800DC/aic_userconfig_8800dc.txt: -------------------------------------------------------------------------------- 1 | # AIC USERCONFIG 2022/0803/1707 2 | 3 | # txpwr_lvl 4 | enable=1 5 | lvl_11b_11ag_1m_2g4=20 6 | lvl_11b_11ag_2m_2g4=20 7 | lvl_11b_11ag_5m5_2g4=20 8 | lvl_11b_11ag_11m_2g4=20 9 | lvl_11b_11ag_6m_2g4=20 10 | lvl_11b_11ag_9m_2g4=20 11 | lvl_11b_11ag_12m_2g4=20 12 | lvl_11b_11ag_18m_2g4=20 13 | lvl_11b_11ag_24m_2g4=18 14 | lvl_11b_11ag_36m_2g4=18 15 | lvl_11b_11ag_48m_2g4=16 16 | lvl_11b_11ag_54m_2g4=16 17 | lvl_11n_11ac_mcs0_2g4=20 18 | lvl_11n_11ac_mcs1_2g4=20 19 | lvl_11n_11ac_mcs2_2g4=20 20 | lvl_11n_11ac_mcs3_2g4=20 21 | lvl_11n_11ac_mcs4_2g4=18 22 | lvl_11n_11ac_mcs5_2g4=18 23 | lvl_11n_11ac_mcs6_2g4=16 24 | lvl_11n_11ac_mcs7_2g4=16 25 | lvl_11n_11ac_mcs8_2g4=16 26 | lvl_11n_11ac_mcs9_2g4=16 27 | lvl_11ax_mcs0_2g4=20 28 | lvl_11ax_mcs1_2g4=20 29 | lvl_11ax_mcs2_2g4=20 30 | lvl_11ax_mcs3_2g4=20 31 | lvl_11ax_mcs4_2g4=18 32 | lvl_11ax_mcs5_2g4=18 33 | lvl_11ax_mcs6_2g4=16 34 | lvl_11ax_mcs7_2g4=16 35 | lvl_11ax_mcs8_2g4=16 36 | lvl_11ax_mcs9_2g4=16 37 | lvl_11ax_mcs10_2g4=15 38 | lvl_11ax_mcs11_2g4=15 39 | 40 | # txpwr_loss 41 | loss_enable=0 42 | loss_value=2 43 | 44 | # txpwr_ofst 45 | ofst_enable=0 46 | ofst_chan_1_4=0 47 | ofst_chan_5_9=0 48 | ofst_chan_10_13=0 49 | ofst_chan_36_64=0 50 | ofst_chan_100_120=0 51 | ofst_chan_122_140=0 52 | ofst_chan_142_165=0 53 | 54 | # xtal cap 55 | xtal_enable=0 56 | xtal_cap=24 57 | xtal_cap_fine=31 58 | 59 | 60 | 61 | -------------------------------------------------------------------------------- /fw/aic8800DC/aic_userconfig_8800dw.txt: -------------------------------------------------------------------------------- 1 | # AIC USERCONFIG 2022/0803/1707 2 | 3 | # txpwr_lvl 4 | enable=1 5 | lvl_11b_11ag_1m_2g4=20 6 | lvl_11b_11ag_2m_2g4=20 7 | lvl_11b_11ag_5m5_2g4=20 8 | lvl_11b_11ag_11m_2g4=20 9 | lvl_11b_11ag_6m_2g4=20 10 | lvl_11b_11ag_9m_2g4=20 11 | lvl_11b_11ag_12m_2g4=20 12 | lvl_11b_11ag_18m_2g4=20 13 | lvl_11b_11ag_24m_2g4=18 14 | lvl_11b_11ag_36m_2g4=18 15 | lvl_11b_11ag_48m_2g4=16 16 | lvl_11b_11ag_54m_2g4=16 17 | lvl_11n_11ac_mcs0_2g4=20 18 | lvl_11n_11ac_mcs1_2g4=20 19 | lvl_11n_11ac_mcs2_2g4=20 20 | lvl_11n_11ac_mcs3_2g4=20 21 | lvl_11n_11ac_mcs4_2g4=18 22 | lvl_11n_11ac_mcs5_2g4=18 23 | lvl_11n_11ac_mcs6_2g4=16 24 | lvl_11n_11ac_mcs7_2g4=16 25 | lvl_11n_11ac_mcs8_2g4=16 26 | lvl_11n_11ac_mcs9_2g4=16 27 | lvl_11ax_mcs0_2g4=20 28 | lvl_11ax_mcs1_2g4=20 29 | lvl_11ax_mcs2_2g4=20 30 | lvl_11ax_mcs3_2g4=20 31 | lvl_11ax_mcs4_2g4=18 32 | lvl_11ax_mcs5_2g4=18 33 | lvl_11ax_mcs6_2g4=16 34 | lvl_11ax_mcs7_2g4=16 35 | lvl_11ax_mcs8_2g4=16 36 | lvl_11ax_mcs9_2g4=16 37 | lvl_11ax_mcs10_2g4=15 38 | lvl_11ax_mcs11_2g4=15 39 | 40 | # txpwr_loss 41 | loss_enable=0 42 | loss_value=2 43 | 44 | # txpwr_ofst 45 | ofst_enable=0 46 | ofst_chan_1_4=0 47 | ofst_chan_5_9=0 48 | ofst_chan_10_13=0 49 | ofst_chan_36_64=0 50 | ofst_chan_100_120=0 51 | ofst_chan_122_140=0 52 | ofst_chan_142_165=0 53 | 54 | # xtal cap 55 | xtal_enable=0 56 | xtal_cap=24 57 | xtal_cap_fine=31 58 | 59 | 60 | 61 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_mesh.h: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file rwnx_mesh.h 5 | * 6 | * @brief VHT Beamformer function declarations 7 | * 8 | * Copyright (C) RivieraWaves 2016-2019 9 | * 10 | **************************************************************************************** 11 | */ 12 | 13 | #ifndef _RWNX_MESH_H_ 14 | #define _RWNX_MESH_H_ 15 | 16 | /** 17 | * INCLUDE FILES 18 | **************************************************************************************** 19 | */ 20 | 21 | #include "rwnx_defs.h" 22 | 23 | /** 24 | * DEFINES 25 | **************************************************************************************** 26 | */ 27 | 28 | /** 29 | * TYPE DEFINITIONS 30 | **************************************************************************************** 31 | */ 32 | 33 | /** 34 | * FUNCTION DECLARATIONS 35 | **************************************************************************************** 36 | */ 37 | 38 | /** 39 | **************************************************************************************** 40 | * @brief TODO [LT] 41 | **************************************************************************************** 42 | */ 43 | struct rwnx_mesh_proxy *rwnx_get_mesh_proxy_info(struct rwnx_vif *p_rwnx_vif, u8 *p_sta_addr, bool local); 44 | 45 | #endif /* _RWNX_MESH_H_ */ 46 | -------------------------------------------------------------------------------- /aic8800_fdrv/sdio_host.h: -------------------------------------------------------------------------------- 1 | /** 2 | * sdio_host.h 3 | * 4 | * SDIO host function declarations 5 | * 6 | * Copyright (C) AICSemi 2018-2020 7 | */ 8 | 9 | 10 | #ifndef _SDIO_HOST_H_ 11 | #define _SDIO_HOST_H_ 12 | 13 | #include "lmac_types.h" 14 | #include "aicwf_sdio.h" 15 | 16 | #define SDIO_TXQUEUE_CNT NX_TXQ_CNT 17 | #define SDIO_TXDESC_CNT NX_TXDESC_CNT 18 | 19 | 20 | /// Definition of the IPC Host environment structure. 21 | struct sdio_host_env_tag 22 | { 23 | // Index used that points to the first free TX desc 24 | uint32_t txdesc_free_idx[SDIO_TXQUEUE_CNT]; 25 | // Index used that points to the first used TX desc 26 | uint32_t txdesc_used_idx[SDIO_TXQUEUE_CNT]; 27 | // Array storing the currently pushed host ids, per IPC queue 28 | uint64_t tx_host_id[SDIO_TXQUEUE_CNT][SDIO_TXDESC_CNT]; 29 | 30 | /// Pointer to the attached object (used in callbacks and register accesses) 31 | void *pthis; 32 | }; 33 | 34 | extern void aicwf_sdio_host_init(struct sdio_host_env_tag *env, 35 | void *cb, void *shared_env_ptr, void *pthis); 36 | 37 | extern void aicwf_sdio_host_txdesc_push(struct sdio_host_env_tag *env, const int queue_idx, const uint64_t host_id); 38 | 39 | extern void aicwf_sdio_host_tx_cfm_handler(struct sdio_host_env_tag *env, u32 *data); 40 | extern int aicwf_rwnx_sdio_platform_init(struct aic_sdio_dev *sdiodev); 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /aic8800_fdrv/usb_host.h: -------------------------------------------------------------------------------- 1 | /** 2 | * usb_host.h 3 | * 4 | * USB host function declarations 5 | * 6 | * Copyright (C) AICSemi 2018-2020 7 | */ 8 | 9 | 10 | #ifndef _USB_HOST_H_ 11 | #define _USB_HOST_H_ 12 | 13 | #include "lmac_types.h" 14 | #include "aicwf_usb.h" 15 | 16 | #define USB_TXQUEUE_CNT NX_TXQ_CNT 17 | #define USB_TXDESC_CNT NX_TXDESC_CNT 18 | 19 | 20 | /// Definition of the IPC Host environment structure. 21 | struct usb_host_env_tag 22 | { 23 | // Index used that points to the first free TX desc 24 | uint32_t txdesc_free_idx[USB_TXQUEUE_CNT]; 25 | // Index used that points to the first used TX desc 26 | uint32_t txdesc_used_idx[USB_TXQUEUE_CNT]; 27 | // Array storing the currently pushed host ids, per IPC queue 28 | //uint64_t tx_host_id[USB_TXQUEUE_CNT][USB_TXDESC_CNT]; 29 | unsigned long tx_host_id[USB_TXQUEUE_CNT][USB_TXDESC_CNT]; 30 | 31 | /// Pointer to the attached object (used in callbacks and register accesses) 32 | void *pthis; 33 | }; 34 | 35 | extern void aicwf_usb_host_init(struct usb_host_env_tag *env, 36 | void *cb, void *shared_env_ptr, void *pthis); 37 | 38 | extern void aicwf_usb_host_txdesc_push(struct usb_host_env_tag *env, const int queue_idx, const uint64_t host_id); 39 | 40 | extern void aicwf_usb_host_tx_cfm_handler(struct usb_host_env_tag *env, u32 *data); 41 | extern int aicwf_rwnx_usb_platform_init(struct aic_usb_dev *usbdev); 42 | 43 | #endif 44 | -------------------------------------------------------------------------------- /aic_load_fw/aicbluetooth.h: -------------------------------------------------------------------------------- 1 | #ifndef _AICBLUETOOTH_H 2 | #define _AICBLUETOOTH_H 3 | 4 | struct aicbt_patch_table { 5 | char *name; 6 | uint32_t type; 7 | uint32_t *data; 8 | uint32_t len; 9 | struct aicbt_patch_table *next; 10 | }; 11 | 12 | 13 | int aic_bt_platform_init(struct aic_usb_dev *sdiodev); 14 | 15 | void aic_bt_platform_deinit(struct aic_usb_dev *sdiodev); 16 | 17 | int rwnx_plat_bin_fw_upload_android(struct aic_usb_dev *sdiodev, u32 fw_addr, 18 | char *filename); 19 | 20 | int rwnx_plat_m2d_flash_ota_android(struct aic_usb_dev *usbdev, char *filename); 21 | 22 | int rwnx_plat_m2d_flash_ota_check(struct aic_usb_dev *usbdev, char *filename); 23 | 24 | int rwnx_plat_bin_fw_patch_table_upload_android(struct aic_usb_dev *usbdev, char *filename); 25 | 26 | int rwnx_plat_userconfig_upload_android(struct aic_usb_dev *usbdev, char *filename); 27 | int rwnx_plat_flash_bin_upload_android(struct aic_usb_dev *usbdev, u32 fw_addr, char *filename); 28 | 29 | int8_t rwnx_atoi(char *value); 30 | uint32_t rwnx_atoli(char *value); 31 | int aicbt_patch_table_free(struct aicbt_patch_table *head); 32 | struct aicbt_patch_table *aicbt_patch_table_alloc(struct aic_usb_dev *usbdev, const char *filename); 33 | int aicbt_patch_info_unpack(struct aicbt_patch_info_t *patch_info, struct aicbt_patch_table *head_t); 34 | int aicbt_patch_table_load(struct aic_usb_dev *usbdev, struct aicbt_patch_table *_head); 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /aic_load_fw/md5.h: -------------------------------------------------------------------------------- 1 | #ifndef MD5_H 2 | #define MD5_H 3 | 4 | typedef struct 5 | { 6 | unsigned int count[2]; 7 | unsigned int state[4]; 8 | unsigned char buffer[64]; 9 | }MD5_CTX; 10 | 11 | 12 | #define F(x,y,z) ((x & y) | (~x & z)) 13 | #define G(x,y,z) ((x & z) | (y & ~z)) 14 | #define H(x,y,z) (x^y^z) 15 | #define I(x,y,z) (y ^ (x | ~z)) 16 | #define ROTATE_LEFT(x,n) ((x << n) | (x >> (32-n))) 17 | #define FF(a,b,c,d,x,s,ac) \ 18 | { \ 19 | a += F(b,c,d) + x + ac; \ 20 | a = ROTATE_LEFT(a,s); \ 21 | a += b; \ 22 | } 23 | #define GG(a,b,c,d,x,s,ac) \ 24 | { \ 25 | a += G(b,c,d) + x + ac; \ 26 | a = ROTATE_LEFT(a,s); \ 27 | a += b; \ 28 | } 29 | #define HH(a,b,c,d,x,s,ac) \ 30 | { \ 31 | a += H(b,c,d) + x + ac; \ 32 | a = ROTATE_LEFT(a,s); \ 33 | a += b; \ 34 | } 35 | #define II(a,b,c,d,x,s,ac) \ 36 | { \ 37 | a += I(b,c,d) + x + ac; \ 38 | a = ROTATE_LEFT(a,s); \ 39 | a += b; \ 40 | } 41 | void MD5Init(MD5_CTX *context); 42 | void MD5Update(MD5_CTX *context,unsigned char *input,unsigned int inputlen); 43 | void MD5Final(MD5_CTX *context,unsigned char digest[16]); 44 | void MD5Transform(unsigned int state[4],unsigned char block[64]); 45 | void MD5Encode(unsigned char *output,unsigned int *input,unsigned int len); 46 | void MD5Decode(unsigned int *output,unsigned char *input,unsigned int len); 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /aic8800_fdrv/md5.h: -------------------------------------------------------------------------------- 1 | #ifndef MD5_H 2 | #define MD5_H 3 | 4 | typedef struct 5 | { 6 | unsigned int count[2]; 7 | unsigned int state[4]; 8 | unsigned char buffer[64]; 9 | }MD5_CTX; 10 | 11 | 12 | #define F(x,y,z) ((x & y) | (~x & z)) 13 | #define G(x,y,z) ((x & z) | (y & ~z)) 14 | #define H(x,y,z) (x^y^z) 15 | #define I(x,y,z) (y ^ (x | ~z)) 16 | #define ROTATE_LEFT(x,n) ((x << n) | (x >> (32-n))) 17 | #define FF(a,b,c,d,x,s,ac) \ 18 | { \ 19 | a += F(b,c,d) + x + ac; \ 20 | a = ROTATE_LEFT(a,s); \ 21 | a += b; \ 22 | } 23 | #define GG(a,b,c,d,x,s,ac) \ 24 | { \ 25 | a += G(b,c,d) + x + ac; \ 26 | a = ROTATE_LEFT(a,s); \ 27 | a += b; \ 28 | } 29 | #define HH(a,b,c,d,x,s,ac) \ 30 | { \ 31 | a += H(b,c,d) + x + ac; \ 32 | a = ROTATE_LEFT(a,s); \ 33 | a += b; \ 34 | } 35 | #define II(a,b,c,d,x,s,ac) \ 36 | { \ 37 | a += I(b,c,d) + x + ac; \ 38 | a = ROTATE_LEFT(a,s); \ 39 | a += b; \ 40 | } 41 | void MD5Init(MD5_CTX *context); 42 | void MD5Update(MD5_CTX *context,unsigned char *input,unsigned int inputlen); 43 | void MD5Final(MD5_CTX *context,unsigned char digest[16]); 44 | void MD5Transform(unsigned int state[4],unsigned char block[64]); 45 | void MD5Encode(unsigned char *output,unsigned int *input,unsigned int len); 46 | void MD5Decode(unsigned int *output,unsigned char *input,unsigned int len); 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_tdls.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_tdls.h 5 | * 6 | * @brief TDLS function declarations 7 | * 8 | * Copyright (C) RivieraWaves 2012-2019 9 | * 10 | ****************************************************************************** 11 | */ 12 | 13 | #ifndef RWNX_TDLS_H_ 14 | #define RWNX_TDLS_H_ 15 | 16 | #include "rwnx_defs.h" 17 | 18 | struct ieee_types_header { 19 | u8 element_id; 20 | u8 len; 21 | } __packed; 22 | 23 | struct ieee_types_bss_co_2040 { 24 | struct ieee_types_header ieee_hdr; 25 | u8 bss_2040co; 26 | } __packed; 27 | 28 | struct ieee_types_extcap { 29 | struct ieee_types_header ieee_hdr; 30 | u8 ext_capab[8]; 31 | } __packed; 32 | 33 | struct ieee_types_vht_cap { 34 | struct ieee_types_header ieee_hdr; 35 | struct ieee80211_vht_cap vhtcap; 36 | } __packed; 37 | 38 | struct ieee_types_vht_oper { 39 | struct ieee_types_header ieee_hdr; 40 | struct ieee80211_vht_operation vhtoper; 41 | } __packed; 42 | 43 | struct ieee_types_aid { 44 | struct ieee_types_header ieee_hdr; 45 | u16 aid; 46 | } __packed; 47 | 48 | int rwnx_tdls_send_mgmt_packet_data(struct rwnx_hw *rwnx_hw, struct rwnx_vif *rwnx_vif, 49 | const u8 *peer, u8 action_code, u8 dialog_token, 50 | u16 status_code, u32 peer_capability, bool initiator, 51 | const u8 *extra_ies, size_t extra_ies_len, u8 oper_class, 52 | struct cfg80211_chan_def *chandef); 53 | 54 | #endif /* RWNX_TDLS_H_ */ 55 | -------------------------------------------------------------------------------- /aic8800_fdrv/lmac_types.h: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file co_types.h 5 | * 6 | * @brief This file replaces the need to include stdint or stdbool typical headers, 7 | * which may not be available in all toolchains, and adds new types 8 | * 9 | * Copyright (C) RivieraWaves 2009-2019 10 | * 11 | * $Rev: $ 12 | * 13 | **************************************************************************************** 14 | */ 15 | 16 | #ifndef _LMAC_INT_H_ 17 | #define _LMAC_INT_H_ 18 | 19 | 20 | /** 21 | **************************************************************************************** 22 | * @addtogroup CO_INT 23 | * @ingroup COMMON 24 | * @brief Common integer standard types (removes use of stdint) 25 | * 26 | * @{ 27 | **************************************************************************************** 28 | */ 29 | 30 | 31 | /* 32 | * DEFINES 33 | **************************************************************************************** 34 | */ 35 | 36 | #include 37 | #include 38 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) 39 | #include 40 | #else 41 | #include 42 | #endif 43 | 44 | #ifdef CONFIG_RWNX_TL4 45 | typedef uint16_t u8_l; 46 | typedef int16_t s8_l; 47 | typedef uint16_t bool_l; 48 | #else 49 | typedef uint8_t u8_l; 50 | typedef int8_t s8_l; 51 | typedef bool bool_l; 52 | #endif 53 | typedef uint16_t u16_l; 54 | typedef int16_t s16_l; 55 | typedef uint32_t u32_l; 56 | typedef int32_t s32_l; 57 | typedef uint64_t u64_l; 58 | 59 | 60 | 61 | /// @} CO_INT 62 | #endif // _LMAC_INT_H_ 63 | -------------------------------------------------------------------------------- /aic_load_fw/aicwf_txq_prealloc.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "aicwf_debug.h" 3 | 4 | struct prealloc_txq{ 5 | int prealloced; 6 | void *txq; 7 | size_t size; 8 | }; 9 | 10 | struct prealloc_txq prealloc_txq; 11 | #define MAX_TXQ_SIZE 100 * 1024 12 | 13 | void *aicwf_prealloc_txq_alloc(size_t size) 14 | { 15 | 16 | BUG_ON(size > MAX_TXQ_SIZE); 17 | 18 | //check prealloc_txq.size 19 | if((int)prealloc_txq.size != (int)size) 20 | { 21 | AICWFDBG(LOGINFO, "%s size is diff will to be kzalloc \r\n", __func__); 22 | 23 | if(prealloc_txq.txq != NULL) 24 | { 25 | AICWFDBG(LOGINFO, "%s txq to kfree \r\n", __func__); 26 | kfree(prealloc_txq.txq); 27 | prealloc_txq.txq = NULL; 28 | } 29 | 30 | prealloc_txq.size = size; 31 | prealloc_txq.prealloced = 0; 32 | } 33 | 34 | //check prealloc or not 35 | if(!prealloc_txq.prealloced) 36 | { 37 | prealloc_txq.txq = kzalloc(size, GFP_KERNEL); 38 | if(!prealloc_txq.txq){ 39 | AICWFDBG(LOGERROR, "%s txq kzalloc fail \r\n", __func__); 40 | }else{ 41 | AICWFDBG(LOGINFO, "%s txq kzalloc successful \r\n", __func__); 42 | prealloc_txq.prealloced = 1; 43 | } 44 | }else{ 45 | AICWFDBG(LOGINFO, "%s txq not need to kzalloc \r\n", __func__); 46 | } 47 | 48 | return prealloc_txq.txq; 49 | } 50 | void aicwf_prealloc_txq_free(void) 51 | { 52 | if(prealloc_txq.txq != NULL) 53 | { 54 | AICWFDBG(LOGINFO, "%s txq to kfree \r\n", __func__); 55 | kfree(prealloc_txq.txq); 56 | prealloc_txq.txq = NULL; 57 | } 58 | } 59 | 60 | EXPORT_SYMBOL(aicwf_prealloc_txq_alloc); 61 | 62 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_mod_params.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_mod_params.h 5 | * 6 | * @brief Declaration of module parameters 7 | * 8 | * Copyright (C) RivieraWaves 2012-2019 9 | * 10 | ****************************************************************************** 11 | */ 12 | 13 | #ifndef _RWNX_MOD_PARAM_H_ 14 | #define _RWNX_MOD_PARAM_H_ 15 | 16 | struct rwnx_mod_params { 17 | bool ht_on; 18 | bool vht_on; 19 | bool he_on; 20 | int mcs_map; 21 | int he_mcs_map; 22 | bool he_ul_on; 23 | bool ldpc_on; 24 | bool stbc_on; 25 | bool gf_rx_on; 26 | int phy_cfg; 27 | int uapsd_timeout; 28 | bool ap_uapsd_on; 29 | bool sgi; 30 | bool sgi80; 31 | bool use_2040; 32 | bool use_80; 33 | bool custregd; 34 | bool custchan; 35 | int nss; 36 | int amsdu_rx_max; 37 | bool bfmee; 38 | bool bfmer; 39 | bool mesh; 40 | bool murx; 41 | bool mutx; 42 | bool mutx_on; 43 | unsigned int roc_dur_max; 44 | int listen_itv; 45 | bool listen_bcmc; 46 | int lp_clk_ppm; 47 | bool ps_on; 48 | int tx_lft; 49 | int amsdu_maxnb; 50 | int uapsd_queues; 51 | bool tdls; 52 | bool uf; 53 | bool auto_reply; 54 | char *ftl; 55 | bool dpsm; 56 | #ifdef CONFIG_RWNX_FULLMAC 57 | bool ant_div; 58 | #endif /* CONFIG_RWNX_FULLMAC */ 59 | }; 60 | 61 | extern struct rwnx_mod_params rwnx_mod_params; 62 | 63 | struct rwnx_hw; 64 | struct wiphy; 65 | int rwnx_handle_dynparams(struct rwnx_hw *rwnx_hw, struct wiphy *wiphy); 66 | void rwnx_custregd(struct rwnx_hw *rwnx_hw, struct wiphy *wiphy); 67 | void rwnx_enable_wapi(struct rwnx_hw *rwnx_hw); 68 | void rwnx_enable_mfp(struct rwnx_hw *rwnx_hw); 69 | 70 | #endif /* _RWNX_MOD_PARAM_H_ */ 71 | -------------------------------------------------------------------------------- /aic_load_fw/aic_compat_8800d80x2.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include "aicwf_usb.h" 3 | 4 | #define USB_DEVICE_ID_AIC_8800D80X2 0x8D90 5 | #define USB_DEVICE_ID_AIC_8800D81X2 0x8D91 6 | #define USB_DEVICE_ID_AIC_8800D89X2 0x8D99 7 | 8 | 9 | #define FW_BASE_NAME_8800D80X2 "fmacfw_8800d80x2.bin" 10 | #define FW_RF_BASE_NAME_8800D80X2 "lmacfw_rf_8800d80x2.bin" 11 | 12 | #define FW_PATCH_BASE_NAME_8800D80X2_U03 "fw_patch_8800d80x2_u03.bin" 13 | #define FW_PATCH_BASE_NAME_8800D80X2_U03_EXT "fw_patch_8800d80x2_u03_ext" 14 | #define FW_ADID_BASE_NAME_8800D80X2_U03 "fw_adid_8800d80x2_u03.bin" 15 | #define FW_PATCH_TABLE_NAME_8800D80X2_U03 "fw_patch_table_8800d80x2_u03.bin" 16 | 17 | #define FW_PATCH_BASE_NAME_8800D80X2_U05 "fw_patch_8800d80x2_u05.bin" 18 | #define FW_PATCH_BASE_NAME_8800D80X2_U05_EXT "fw_patch_8800d80x2_u05_ext" 19 | #define FW_ADID_BASE_NAME_8800D80X2_U05 "fw_adid_8800d80x2_u05.bin" 20 | #define FW_PATCH_TABLE_NAME_8800D80X2_U05 "fw_patch_table_8800d80x2_u05.bin" 21 | 22 | #define FLASH_BIN_8800M80X2 "host_wb_8800m80x2.bin" 23 | 24 | #define FW_USERCONFIG_NAME_8800D80X2 "aic_userconfig_8800d80x2.txt" 25 | 26 | #define RAM_FMAC_FW_ADDR_8800D80X2 0x120000 27 | #define RAM_FMAC_RF_FW_ADDR_8800D80X2 0x120000 28 | 29 | #define FW_RAM_ADID_BASE_ADDR_8800D80X2_U03 0x003018f8 30 | #define FW_RAM_PATCH_BASE_ADDR_8800D80X2_U03 0x0030b494 31 | 32 | #define FW_RAM_ADID_BASE_ADDR_8800D80X2_U05 0x003018f8 33 | #define FW_RAM_PATCH_BASE_ADDR_8800D80X2_U05 0x0030b494 34 | 35 | #define FLASH_BIN_ADDR_8800M80X2 0x8000000 36 | 37 | 38 | int aicwf_patch_config_8800d80x2(struct aic_usb_dev *usb_dev); 39 | int rwnx_plat_userconfig_load_8800d80x2(struct aic_usb_dev *usbdev); 40 | int system_config_8800d80x2(struct aic_usb_dev *usb_dev); 41 | int aicfw_download_fw_8800d80x2(struct aic_usb_dev *usb_dev); 42 | 43 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_irqs.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_irqs.c 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | #include 11 | 12 | #include "rwnx_defs.h" 13 | #include "ipc_host.h" 14 | #include "rwnx_prof.h" 15 | 16 | /** 17 | * rwnx_irq_hdlr - IRQ handler 18 | * 19 | * Handler registerd by the platform driver 20 | */ 21 | irqreturn_t rwnx_irq_hdlr(int irq, void *dev_id) 22 | { 23 | struct rwnx_hw *rwnx_hw = (struct rwnx_hw *)dev_id; 24 | disable_irq_nosync(irq); 25 | tasklet_schedule(&rwnx_hw->task); 26 | return IRQ_HANDLED; 27 | } 28 | 29 | /** 30 | * rwnx_task - Bottom half for IRQ handler 31 | * 32 | * Read irq status and process accordingly 33 | */ 34 | void rwnx_task(unsigned long data) 35 | { 36 | struct rwnx_hw *rwnx_hw = (struct rwnx_hw *)data; 37 | REG_SW_SET_PROFILING(rwnx_hw, SW_PROF_RWNX_IPC_IRQ_HDLR); 38 | 39 | #if 0 40 | struct rwnx_plat *rwnx_plat = rwnx_hw->plat; 41 | u32 status, statuses = 0; 42 | 43 | /* Ack unconditionnally in case ipc_host_get_status does not see the irq */ 44 | rwnx_plat->ack_irq(rwnx_plat); 45 | 46 | while ((status = ipc_host_get_status(rwnx_hw->ipc_env))) { 47 | statuses |= status; 48 | /* All kinds of IRQs will be handled in one shot (RX, MSG, DBG, ...) 49 | * this will ack IPC irqs not the cfpga irqs */ 50 | ipc_host_irq(rwnx_hw->ipc_env, status); 51 | 52 | rwnx_plat->ack_irq(rwnx_plat); 53 | } 54 | #endif 55 | //if (statuses & IPC_IRQ_E2A_RXDESC) 56 | // rwnx_hw->stats.last_rx = now; 57 | //if (statuses & IPC_IRQ_E2A_TXCFM) 58 | // rwnx_hw->stats.last_tx = now; 59 | AICWFDBG(LOGTRACE, "rwnx_task\n"); 60 | spin_lock_bh(&rwnx_hw->tx_lock); 61 | rwnx_hwq_process_all(rwnx_hw); 62 | spin_unlock_bh(&rwnx_hw->tx_lock); 63 | #if 0 64 | enable_irq(rwnx_platform_get_irq(rwnx_plat)); 65 | #endif 66 | REG_SW_CLEAR_PROFILING(rwnx_hw, SW_PROF_RWNX_IPC_IRQ_HDLR); 67 | } 68 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_testmode.h: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file rwnx_testmode.h 5 | * 6 | * @brief Test mode function declarations 7 | * 8 | * Copyright (C) RivieraWaves 2012-2019 9 | * 10 | **************************************************************************************** 11 | */ 12 | 13 | #ifndef RWNX_TESTMODE_H_ 14 | #define RWNX_TESTMODE_H_ 15 | 16 | #include 17 | #include 18 | 19 | /* Commands from user space to kernel space(RWNX_TM_CMD_APP2DEV_XX) and 20 | * from and kernel space to user space(RWNX_TM_CMD_DEV2APP_XX). 21 | * The command ID is carried with RWNX_TM_ATTR_COMMAND. 22 | */ 23 | enum rwnx_tm_cmd_t { 24 | /* commands from user application to access register */ 25 | RWNX_TM_CMD_APP2DEV_REG_READ = 1, 26 | RWNX_TM_CMD_APP2DEV_REG_WRITE, 27 | 28 | /* commands from user application to select the Debug levels */ 29 | RWNX_TM_CMD_APP2DEV_SET_DBGMODFILTER, 30 | RWNX_TM_CMD_APP2DEV_SET_DBGSEVFILTER, 31 | 32 | /* commands to access registers without sending messages to LMAC layer, 33 | * this must be used when LMAC FW is stuck. */ 34 | RWNX_TM_CMD_APP2DEV_REG_READ_DBG, 35 | RWNX_TM_CMD_APP2DEV_REG_WRITE_DBG, 36 | 37 | RWNX_TM_CMD_MAX, 38 | }; 39 | 40 | enum rwnx_tm_attr_t { 41 | RWNX_TM_ATTR_NOT_APPLICABLE = 0, 42 | 43 | RWNX_TM_ATTR_COMMAND, 44 | 45 | /* When RWNX_TM_ATTR_COMMAND is RWNX_TM_CMD_APP2DEV_REG_XXX, 46 | * The mandatory fields are: 47 | * RWNX_TM_ATTR_REG_OFFSET for the offset of the target register; 48 | * RWNX_TM_ATTR_REG_VALUE32 for value */ 49 | RWNX_TM_ATTR_REG_OFFSET, 50 | RWNX_TM_ATTR_REG_VALUE32, 51 | 52 | /* When RWNX_TM_ATTR_COMMAND is RWNX_TM_CMD_APP2DEV_SET_DBGXXXFILTER, 53 | * The mandatory field is RWNX_TM_ATTR_REG_FILTER. */ 54 | RWNX_TM_ATTR_REG_FILTER, 55 | 56 | RWNX_TM_ATTR_MAX, 57 | }; 58 | 59 | /***********************************************************************/ 60 | int rwnx_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb); 61 | int rwnx_testmode_dbg_filter(struct ieee80211_hw *hw, struct nlattr **tb); 62 | int rwnx_testmode_reg_dbg(struct ieee80211_hw *hw, struct nlattr **tb); 63 | 64 | #endif /* RWNX_TESTMODE_H_ */ 65 | -------------------------------------------------------------------------------- /aic_load_fw/aic_bluetooth_main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #include "aicwf_usb.h" 6 | #include "rwnx_version_gen.h" 7 | #include "aicwf_rx_prealloc.h" 8 | #include "aicwf_debug.h" 9 | #include "aicwf_txq_prealloc.h" 10 | 11 | 12 | #define DRV_CONFIG_FW_NAME "fw.bin" 13 | #define DRV_DESCRIPTION "AIC BLUETOOTH" 14 | #define DRV_COPYRIGHT "Copyright(c) 2015-2020 AICSemi" 15 | #define DRV_AUTHOR "AICSemi" 16 | #define DRV_VERS_MOD "1.0" 17 | 18 | int testmode = FW_NORMAL_MODE; 19 | int adap_test = 0; 20 | char paringid[100]; 21 | int n_para = 1; 22 | int ble_scan_wakeup_reboot_time = 1000; 23 | int aicwf_dbg_level = LOGERROR|LOGINFO|LOGDEBUG|LOGTRACE; 24 | int flash_erase_len = 0x400000; 25 | uint32_t ad_data_filter_mask = 0; 26 | uint32_t gpio_num = 2;//default select gpiob2 for fw_wakeup_host 27 | uint32_t gpio_dft_lvl = 0;//0:defalut pull down, 1:default pull up 28 | 29 | module_param(aicwf_dbg_level, int, 0660); 30 | module_param(ble_scan_wakeup_reboot_time, int, 0660); 31 | module_param(testmode, int, 0660); 32 | module_param(adap_test, int, 0660); 33 | module_param_string(paringid, paringid, 100, 0660); 34 | module_param(flash_erase_len, int, 0660); 35 | 36 | 37 | static void aicsmac_driver_register(void) 38 | { 39 | aicwf_usb_register(); 40 | } 41 | 42 | static int __init aic_bluetooth_mod_init(void) 43 | { 44 | printk("%s \n", __func__); 45 | printk("RELEASE DATE:%s \r\n", RELEASE_DATE); 46 | #ifdef CONFIG_PREALLOC_RX_SKB 47 | aicwf_prealloc_init(); 48 | #endif 49 | 50 | aicsmac_driver_register(); 51 | return 0; 52 | } 53 | 54 | static void __exit aic_bluetooth_mod_exit(void) 55 | { 56 | printk("%s\n", __func__); 57 | aicwf_usb_exit(); 58 | 59 | #ifdef CONFIG_PREALLOC_RX_SKB 60 | aicwf_prealloc_exit(); 61 | #endif 62 | 63 | #ifdef CONFIG_PREALLOC_TXQ 64 | aicwf_prealloc_txq_free(); 65 | #endif 66 | } 67 | 68 | 69 | module_init(aic_bluetooth_mod_init); 70 | module_exit(aic_bluetooth_mod_exit); 71 | 72 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0) 73 | MODULE_IMPORT_NS(VFS_internal_I_am_really_a_filesystem_and_am_NOT_a_driver); 74 | #endif 75 | 76 | MODULE_FIRMWARE(DRV_CONFIG_FW_NAME); 77 | MODULE_DESCRIPTION(DRV_DESCRIPTION); 78 | MODULE_VERSION(DRV_VERS_MOD); 79 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); 80 | MODULE_LICENSE("GPL"); 81 | 82 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_compat_8800dc.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB) 4 | typedef struct { 5 | uint32_t bit_mask[3]; 6 | uint32_t reserved; 7 | uint32_t dpd_high[96]; 8 | uint32_t dpd_11b[96]; 9 | uint32_t dpd_low[96]; 10 | uint32_t idac_11b[48]; 11 | uint32_t idac_high[48]; 12 | uint32_t idac_low[48]; 13 | uint32_t loft_res[18]; 14 | uint32_t rx_iqim_res[16]; 15 | } rf_misc_ram_t; 16 | 17 | typedef struct { 18 | uint32_t bit_mask[4]; 19 | uint32_t dpd_high[96]; 20 | uint32_t loft_res[18]; 21 | } rf_misc_ram_lite_t; 22 | 23 | #define MEMBER_SIZE(type, member) sizeof(((type *)0)->member) 24 | #define DPD_RESULT_SIZE_8800DC sizeof(rf_misc_ram_lite_t) 25 | #endif 26 | 27 | #ifdef CONFIG_DPD 28 | extern rf_misc_ram_lite_t dpd_res; 29 | #endif 30 | 31 | #ifdef CONFIG_LOFT_CALIB 32 | extern rf_misc_ram_lite_t loft_res_local; 33 | #endif 34 | 35 | int aicwf_patch_table_load(struct rwnx_hw *rwnx_hw, char *filename); 36 | void aicwf_patch_config_8800dc(struct rwnx_hw *rwnx_hw); 37 | int aicwf_set_rf_config_8800dc(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm); 38 | int aicwf_misc_ram_init_8800dc(struct rwnx_hw *rwnx_hw); 39 | #if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB) 40 | int aicwf_misc_ram_valid_check_8800dc(struct rwnx_hw *rwnx_hw, int *valid_out); 41 | int aicwf_plat_calib_load_8800dc(struct rwnx_hw *rwnx_hw); 42 | #endif 43 | #ifdef CONFIG_DPD 44 | int aicwf_dpd_calib_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *dpd_res); 45 | int aicwf_dpd_result_apply_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *dpd_res); 46 | #ifndef CONFIG_FORCE_DPD_CALIB 47 | int aicwf_dpd_result_load_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *dpd_res); 48 | int aicwf_dpd_result_write_8800dc(void *buf, int buf_len); 49 | #endif 50 | #endif 51 | #ifdef CONFIG_LOFT_CALIB 52 | int aicwf_loft_calib_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *loft_res); 53 | int aicwf_loft_result_apply_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *loft_res); 54 | #endif 55 | int aicwf_plat_patch_load_8800dc(struct rwnx_hw *rwnx_hw); 56 | int aicwf_plat_rftest_load_8800dc(struct rwnx_hw *rwnx_hw); 57 | int rwnx_plat_userconfig_load_8800dc(struct rwnx_hw *rwnx_hw); 58 | int rwnx_plat_userconfig_load_8800dw(struct rwnx_hw *rwnx_hw); 59 | #ifdef CONFIG_POWER_LIMIT 60 | int rwnx_plat_powerlimit_load_8800dcdw(struct rwnx_hw *rwnx_hw, uint16_t chip_id); 61 | #endif 62 | void system_config_8800dc(struct rwnx_hw *rwnx_hw); 63 | -------------------------------------------------------------------------------- /aic8800_fdrv/aic_br_ext.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright(c) 2007 - 2017 Realtek Corporation. 4 | * 5 | * This program is free software; you can redistribute it and/or modify it 6 | * under the terms of version 2 of the GNU General Public License as 7 | * published by the Free Software Foundation. 8 | * 9 | * This program is distributed in the hope that it will be useful, but WITHOUT 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 | * more details. 13 | * 14 | *****************************************************************************/ 15 | #ifndef _AIC_BR_EXT_H_ 16 | #define _AIC_BR_EXT_H_ 17 | 18 | #define CL_IPV6_PASS 1 19 | #define MACADDRLEN 6 20 | #define WLAN_ETHHDR_LEN 14 21 | 22 | #define NAT25_HASH_BITS 4 23 | #define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS) 24 | #define NAT25_AGEING_TIME 300 25 | 26 | #define NDEV_FMT "%s" 27 | #define NDEV_ARG(ndev) ndev->name 28 | #define ADPT_FMT "%s" 29 | //#define ADPT_ARG(adapter) (adapter->pnetdev ? adapter->pnetdev->name : NULL) 30 | #define FUNC_NDEV_FMT "%s(%s)" 31 | #define FUNC_NDEV_ARG(ndev) __func__, ndev->name 32 | #define FUNC_ADPT_FMT "%s(%s)" 33 | //#define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL) 34 | #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" 35 | #define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] 36 | 37 | 38 | #ifdef CL_IPV6_PASS 39 | #define MAX_NETWORK_ADDR_LEN 17 40 | #else 41 | #define MAX_NETWORK_ADDR_LEN 11 42 | #endif 43 | 44 | struct nat25_network_db_entry { 45 | struct nat25_network_db_entry *next_hash; 46 | struct nat25_network_db_entry **pprev_hash; 47 | atomic_t use_count; 48 | unsigned char macAddr[6]; 49 | unsigned long ageing_timer; 50 | unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; 51 | }; 52 | 53 | enum NAT25_METHOD { 54 | NAT25_MIN, 55 | NAT25_CHECK, 56 | NAT25_INSERT, 57 | NAT25_LOOKUP, 58 | NAT25_PARSE, 59 | NAT25_MAX 60 | }; 61 | 62 | struct br_ext_info { 63 | unsigned int nat25_disable; 64 | unsigned int macclone_enable; 65 | unsigned int dhcp_bcst_disable; 66 | int addPPPoETag; /* 1: Add PPPoE relay-SID, 0: disable */ 67 | unsigned char nat25_dmzMac[MACADDRLEN]; 68 | unsigned int nat25sc_disable; 69 | }; 70 | 71 | void nat25_db_cleanup(struct rwnx_vif *vif); 72 | 73 | #endif /* _AIC_BR_EXT_H_ */ 74 | -------------------------------------------------------------------------------- /aic_load_fw/aic_compat_8800d80.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include "aicwf_usb.h" 3 | 4 | #define USB_DEVICE_ID_AIC_8800D80 0x8D80 5 | #define USB_DEVICE_ID_AIC_8800D81 0x8D81 6 | #define USB_DEVICE_ID_AIC_8800D40 0x8D40 7 | #define USB_DEVICE_ID_AIC_8800D41 0x8D41 8 | 9 | #define FW_BASE_NAME_8800D80 "fmacfw_8800d80.bin" 10 | #define FW_RF_BASE_NAME_8800D80 "fmacfw_rf_8800d80.bin" 11 | #define FW_PATCH_BASE_NAME_8800D80 "fw_patch_8800d80.bin" 12 | #define FW_ADID_BASE_NAME_8800D80 "fw_adid_8800d80.bin" 13 | #define FW_PATCH_TABLE_NAME_8800D80 "fw_patch_table_8800d80.bin" 14 | 15 | #ifdef CONFIG_FOR_IPCAM 16 | #define FW_BASE_NAME_8800D80_U02 "fmacfw_8800d80_u02_ipc.bin" 17 | #define FW_BASE_NAME_8800D80_H_U02 "fmacfw_8800d80_h_u02_ipc.bin" 18 | 19 | #else 20 | #define FW_BASE_NAME_8800D80_U02 "fmacfw_8800d80_u02.bin" 21 | #define FW_BASE_NAME_8800D80_H_U02 "fmacfw_8800d80_h_u02.bin" 22 | #endif 23 | #define FW_RF_BASE_NAME_8800D80_U02 "lmacfw_rf_8800d80_u02.bin" 24 | #define FW_PATCH_BASE_NAME_8800D80_U02 "fw_patch_8800d80_u02.bin" 25 | #define FW_PATCH_BASE_NAME_8800D80_U02_EXT "fw_patch_8800d80_u02_ext" 26 | #define FW_ADID_BASE_NAME_8800D80_U02 "fw_adid_8800d80_u02.bin" 27 | #define FW_CALIBMODE_NAME_8800D80_U02 "calibmode_8800d80.bin" 28 | #define FW_PATCH_TABLE_NAME_8800D80_U02 "fw_patch_table_8800d80_u02.bin" 29 | 30 | #define FLASH_BIN_8800M80 "host_wb_8800m80.bin" 31 | 32 | #define FW_USERCONFIG_NAME_8800D80 "aic_userconfig_8800d80.txt" 33 | 34 | #define RAM_FMAC_FW_ADDR_8800D80 0x100000 35 | #define RAM_FMAC_RF_FW_ADDR_8800D80 0x110000 36 | #define FW_RAM_ADID_BASE_ADDR_8800D80 0x002017E0 37 | #define FW_RAM_PATCH_BASE_ADDR_8800D80 0x0020B2B0 38 | 39 | #define RAM_FMAC_FW_ADDR_8800D80_U02 0x120000 40 | #define RAM_FMAC_RF_FW_ADDR_8800D80_U02 0x120000 41 | #define FW_RAM_ADID_BASE_ADDR_8800D80_U02 0x00201940 42 | #define FW_RAM_CALIBMODE_ADDR_8800D80_U02 0x1e0000 43 | #define FW_RAM_PATCH_BASE_ADDR_8800D80_U02 0x0020B43c 44 | 45 | #define FLASH_BIN_ADDR_8800M80 0x8000000 46 | 47 | #define CHIP_ID_H_MASK 0xC0 48 | #define IS_CHIP_ID_H() ((chip_id & CHIP_ID_H_MASK) == CHIP_ID_H_MASK) 49 | 50 | int aicwf_patch_config_8800d80(struct aic_usb_dev *usb_dev); 51 | int rwnx_plat_userconfig_load_8800d80(struct aic_usb_dev *usbdev); 52 | int system_config_8800d80(struct aic_usb_dev *usb_dev); 53 | int aicfw_download_fw_8800d80(struct aic_usb_dev *usb_dev); 54 | 55 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_pci.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_pci.c 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | #include 11 | #include 12 | 13 | #include "rwnx_defs.h" 14 | #include "rwnx_dini.h" 15 | #include "rwnx_v7.h" 16 | 17 | #define PCI_VENDOR_ID_DINIGROUP 0x17DF 18 | #define PCI_DEVICE_ID_DINIGROUP_DNV6_F2PCIE 0x1907 19 | 20 | #define PCI_DEVICE_ID_XILINX_CEVA_VIRTEX7 0x7011 21 | 22 | static const struct pci_device_id rwnx_pci_ids[] = { 23 | {PCI_DEVICE(PCI_VENDOR_ID_DINIGROUP, PCI_DEVICE_ID_DINIGROUP_DNV6_F2PCIE)}, 24 | {PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_XILINX_CEVA_VIRTEX7)}, 25 | {0,} 26 | }; 27 | 28 | 29 | /* Uncomment this for depmod to create module alias */ 30 | /* We don't want this on development platform */ 31 | //MODULE_DEVICE_TABLE(pci, rwnx_pci_ids); 32 | 33 | static int rwnx_pci_probe(struct pci_dev *pci_dev, 34 | const struct pci_device_id *pci_id) 35 | { 36 | struct rwnx_plat *rwnx_plat = NULL; 37 | void *drvdata; 38 | int ret = -ENODEV; 39 | 40 | RWNX_DBG(RWNX_FN_ENTRY_STR); 41 | 42 | if (pci_id->vendor == PCI_VENDOR_ID_DINIGROUP) { 43 | ret = rwnx_dini_platform_init(pci_dev, &rwnx_plat); 44 | } else if (pci_id->vendor == PCI_VENDOR_ID_XILINX) { 45 | ret = rwnx_v7_platform_init(pci_dev, &rwnx_plat); 46 | } 47 | 48 | if (ret) 49 | return ret; 50 | 51 | rwnx_plat->pci_dev = pci_dev; 52 | 53 | ret = rwnx_platform_init(rwnx_plat, &drvdata); 54 | pci_set_drvdata(pci_dev, drvdata); 55 | 56 | if (ret) 57 | rwnx_plat->deinit(rwnx_plat); 58 | 59 | return ret; 60 | } 61 | 62 | static void rwnx_pci_remove(struct pci_dev *pci_dev) 63 | { 64 | struct rwnx_hw *rwnx_hw; 65 | struct rwnx_plat *rwnx_plat; 66 | 67 | RWNX_DBG(RWNX_FN_ENTRY_STR); 68 | 69 | rwnx_hw = pci_get_drvdata(pci_dev); 70 | rwnx_plat = rwnx_hw->plat; 71 | 72 | rwnx_platform_deinit(rwnx_hw); 73 | rwnx_plat->deinit(rwnx_plat); 74 | 75 | pci_set_drvdata(pci_dev, NULL); 76 | } 77 | 78 | static struct pci_driver rwnx_pci_drv = { 79 | .name = KBUILD_MODNAME, 80 | .id_table = rwnx_pci_ids, 81 | .probe = rwnx_pci_probe, 82 | .remove = rwnx_pci_remove 83 | }; 84 | 85 | int rwnx_pci_register_drv(void) 86 | { 87 | return pci_register_driver(&rwnx_pci_drv); 88 | } 89 | 90 | void rwnx_pci_unregister_drv(void) 91 | { 92 | pci_unregister_driver(&rwnx_pci_drv); 93 | } 94 | 95 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_wakelock.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0) 5 | #include 6 | #else 7 | #include 8 | #endif 9 | #include "rwnx_defs.h" 10 | #include "rwnx_wakelock.h" 11 | 12 | struct wakeup_source *rwnx_wakeup_init(const char *name) 13 | { 14 | struct wakeup_source *ws; 15 | ws = wakeup_source_create(name); 16 | wakeup_source_add(ws); 17 | return ws; 18 | } 19 | 20 | void rwnx_wakeup_deinit(struct wakeup_source *ws) 21 | { 22 | if (ws && ws->active) 23 | __pm_relax(ws); 24 | wakeup_source_remove(ws); 25 | wakeup_source_destroy(ws); 26 | } 27 | 28 | struct wakeup_source *rwnx_wakeup_register(struct device *dev, const char *name) 29 | { 30 | 31 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0) 32 | return wakeup_source_register(dev, name); 33 | #else 34 | 35 | #if defined(CONFIG_PLATFORM_ROCKCHIP2) || defined(CONFIG_PLATFORM_ROCKCHIP) 36 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0) 37 | return wakeup_source_register(dev, name); 38 | #else 39 | return wakeup_source_register(name); 40 | #endif 41 | 42 | #else 43 | return wakeup_source_register(name); 44 | #endif//#if defined(CONFIG_PLATFORM_ROCKCHIP2) || defined(CONFIG_PLATFORM_ROCKCHIP) 45 | 46 | #endif//LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0) 47 | } 48 | 49 | void rwnx_wakeup_unregister(struct wakeup_source *ws) 50 | { 51 | if (ws && ws->active) 52 | __pm_relax(ws); 53 | wakeup_source_unregister(ws); 54 | } 55 | 56 | void rwnx_wakeup_lock(struct wakeup_source *ws) 57 | { 58 | AICWFDBG(LOGDEBUG, "%s enter \r\n", __func__); 59 | __pm_stay_awake(ws); 60 | } 61 | 62 | void rwnx_wakeup_unlock(struct wakeup_source *ws) 63 | { 64 | AICWFDBG(LOGDEBUG, "%s enter \r\n", __func__); 65 | __pm_relax(ws); 66 | } 67 | 68 | void rwnx_wakeup_lock_timeout(struct wakeup_source *ws, unsigned int msec) 69 | { 70 | __pm_wakeup_event(ws, msec); 71 | } 72 | 73 | void aicwf_wakeup_lock_init(struct rwnx_hw *rwnx_hw) 74 | { 75 | rwnx_hw->ws_tx = rwnx_wakeup_init("rwnx_tx_wakelock"); 76 | rwnx_hw->ws_rx = rwnx_wakeup_init("rwnx_rx_wakelock"); 77 | rwnx_hw->ws_irqrx = rwnx_wakeup_init("rwnx_irqrx_wakelock"); 78 | rwnx_hw->ws_pwrctrl = rwnx_wakeup_init("rwnx_pwrcrl_wakelock"); 79 | } 80 | 81 | void aicwf_wakeup_lock_deinit(struct rwnx_hw *rwnx_hw) 82 | { 83 | rwnx_wakeup_deinit(rwnx_hw->ws_tx); 84 | rwnx_wakeup_deinit(rwnx_hw->ws_rx); 85 | rwnx_wakeup_deinit(rwnx_hw->ws_irqrx); 86 | rwnx_wakeup_deinit(rwnx_hw->ws_pwrctrl); 87 | rwnx_hw->ws_tx = NULL; 88 | rwnx_hw->ws_rx = NULL; 89 | rwnx_hw->ws_irqrx = NULL; 90 | rwnx_hw->ws_pwrctrl = NULL; 91 | } 92 | 93 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_compat_8800d80.c: -------------------------------------------------------------------------------- 1 | #include "rwnx_main.h" 2 | #include "rwnx_msg_tx.h" 3 | #include "reg_access.h" 4 | 5 | #define FW_USERCONFIG_NAME_8800D80 "aic_userconfig_8800d80.txt" 6 | #define FW_POWERLIMIT_NAME_8800D80 "aic_powerlimit_8800d80.txt" 7 | 8 | extern char aic_fw_path[200]; 9 | 10 | int rwnx_request_firmware_common(struct rwnx_hw *rwnx_hw, 11 | u32** buffer, const char *filename); 12 | void rwnx_plat_userconfig_parsing(char *buffer, int size); 13 | void rwnx_release_firmware_common(u32** buffer); 14 | 15 | 16 | int aicwf_set_rf_config_8800d80(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm) 17 | { 18 | int ret = 0; 19 | 20 | if ((ret = rwnx_send_txpwr_lvl_v3_req(rwnx_hw))) { 21 | return -1; 22 | } 23 | if ((ret = rwnx_send_txpwr_lvl_adj_req(rwnx_hw))) { 24 | return -1; 25 | } 26 | if ((ret = rwnx_send_txpwr_ofst2x_req(rwnx_hw))) { 27 | return -1; 28 | } 29 | if ((ret = rwnx_send_rf_calib_req(rwnx_hw, cfm))) { 30 | return -1; 31 | } 32 | return 0 ; 33 | } 34 | 35 | 36 | int rwnx_plat_userconfig_load_8800d80(struct rwnx_hw *rwnx_hw){ 37 | int size; 38 | u32 *dst=NULL; 39 | char *filename = FW_USERCONFIG_NAME_8800D80; 40 | 41 | #ifndef ANDROID_PLATFORM 42 | sprintf(aic_fw_path, "%s/%s", aic_fw_path, "aic8800D80"); 43 | #endif 44 | 45 | AICWFDBG(LOGINFO, "userconfig file path:%s \r\n", filename); 46 | 47 | /* load file */ 48 | size = rwnx_request_firmware_common(rwnx_hw, &dst, filename); 49 | if (size <= 0) { 50 | AICWFDBG(LOGERROR, "wrong size of firmware file\n"); 51 | dst = NULL; 52 | return 0; 53 | } 54 | 55 | /* Copy the file on the Embedded side */ 56 | AICWFDBG(LOGINFO, "### Load file done: %s, size=%d\n", filename, size); 57 | 58 | rwnx_plat_userconfig_parsing((char *)dst, size); 59 | 60 | rwnx_release_firmware_common(&dst); 61 | 62 | AICWFDBG(LOGINFO, "userconfig download complete\n\n"); 63 | return 0; 64 | 65 | } 66 | 67 | #ifdef CONFIG_POWER_LIMIT 68 | extern char country_code[]; 69 | int rwnx_plat_powerlimit_load_8800d80(struct rwnx_hw *rwnx_hw) 70 | { 71 | int size; 72 | u32 *dst=NULL; 73 | char *filename = FW_POWERLIMIT_NAME_8800D80; 74 | 75 | AICWFDBG(LOGINFO, "powerlimit file path:%s \r\n", filename); 76 | 77 | /* load file */ 78 | size = rwnx_request_firmware_common(rwnx_hw, &dst, filename); 79 | if (size <= 0) { 80 | AICWFDBG(LOGERROR, "wrong size of cfg file\n"); 81 | dst = NULL; 82 | return 0; 83 | } 84 | 85 | AICWFDBG(LOGINFO, "### Load file done: %s, size=%d\n", filename, size); 86 | 87 | /* parsing the file */ 88 | rwnx_plat_powerlimit_parsing((char *)dst, size, country_code); 89 | 90 | rwnx_release_firmware_common(&dst); 91 | 92 | AICWFDBG(LOGINFO, "powerlimit download complete\n\n"); 93 | return 0; 94 | } 95 | #endif 96 | 97 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_tcp_ack.h: -------------------------------------------------------------------------------- 1 | #ifndef _AICWF_TCP_ACK_H_ 2 | #define _AICWF_TCP_ACK_H_ 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | 12 | 13 | #define TCP_ACK_NUM 32 14 | #define TCP_ACK_EXIT_VAL 0x800 15 | #define TCP_ACK_DROP_CNT 10 16 | 17 | #define ACK_OLD_TIME 4000 18 | #define U32_BEFORE(a, b) ((__s32)((__u32)a - (__u32)b) <= 0) 19 | 20 | #define MAX_TCP_ACK 200 21 | /*min window size in KB, it's 256KB*/ 22 | #define MIN_WIN 256 23 | #define SIZE_KB 1024 24 | 25 | 26 | struct msg_buf { 27 | //struct list_head list; 28 | struct sk_buff *skb; 29 | struct rwnx_vif *rwnx_vif; 30 | 31 | /* data just tx cmd use,not include the head */ 32 | /*void *data; 33 | void *tran_data; 34 | unsigned long pcie_addr; 35 | u8 type; 36 | u8 mode; 37 | u16 len; 38 | unsigned long timeout;*/ 39 | 40 | /*unsigned int fifo_id; 41 | struct sprdwl_msg_list *msglist;*/ 42 | 43 | /*unsigned char buffer_type; 44 | struct sprdwl_xmit_msg_list *xmit_msg_list; 45 | unsigned char msg_type; 46 | 47 | unsigned long last_time; 48 | u8 ctxt_id;*/ 49 | 50 | }; 51 | 52 | struct tcp_ack_msg { 53 | u16 source; 54 | u16 dest; 55 | s32 saddr; 56 | s32 daddr; 57 | u32 seq; 58 | u16 win; 59 | }; 60 | 61 | 62 | struct tcp_ack_info { 63 | int ack_info_num; 64 | int busy; 65 | int drop_cnt; 66 | int psh_flag; 67 | u32 psh_seq; 68 | u16 win_scale; 69 | /* seqlock for ack info */ 70 | seqlock_t seqlock; 71 | unsigned long last_time; 72 | unsigned long timeout; 73 | struct timer_list timer; 74 | struct msg_buf *msgbuf; 75 | struct msg_buf *in_send_msg; 76 | struct tcp_ack_msg ack_msg; 77 | }; 78 | 79 | struct tcp_ack_manage { 80 | /* 1 filter */ 81 | atomic_t enable; 82 | int max_num; 83 | int free_index; 84 | unsigned long last_time; 85 | unsigned long timeout; 86 | atomic_t max_drop_cnt; 87 | /* lock for tcp ack alloc and free */ 88 | spinlock_t lock; 89 | struct rwnx_hw *priv; 90 | struct tcp_ack_info ack_info[TCP_ACK_NUM]; 91 | /*size in KB*/ 92 | unsigned int ack_winsize; 93 | }; 94 | 95 | struct msg_buf *intf_tcp_alloc_msg(struct msg_buf *msg); 96 | 97 | void tcp_ack_init(struct rwnx_hw *priv); 98 | 99 | void tcp_ack_deinit(struct rwnx_hw *priv); 100 | 101 | 102 | int is_drop_tcp_ack(struct tcphdr *tcphdr, int tcp_tot_len, unsigned short *win_scale); 103 | 104 | int is_tcp_ack(struct sk_buff *skb, unsigned short *win_scale); 105 | 106 | int filter_send_tcp_ack(struct rwnx_hw *priv, struct msg_buf *msgbuf,unsigned char *buf, unsigned int plen); 107 | 108 | void filter_rx_tcp_ack(struct rwnx_hw *priv,unsigned char *buf, unsigned plen); 109 | 110 | void move_tcpack_msg(struct rwnx_hw *priv, struct msg_buf * msg); 111 | #endif 112 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_compat_8800d80x2.c: -------------------------------------------------------------------------------- 1 | #include "rwnx_main.h" 2 | #include "rwnx_msg_tx.h" 3 | #include "reg_access.h" 4 | 5 | #define FW_USERCONFIG_NAME_8800D80X2 "aic_userconfig_8800d80x2.txt" 6 | #define FW_POWERLIMIT_NAME_8800D80X2 "aic_powerlimit_8800d80x2.txt" 7 | 8 | extern char aic_fw_path[200]; 9 | 10 | int rwnx_request_firmware_common(struct rwnx_hw *rwnx_hw, 11 | u32** buffer, const char *filename); 12 | void rwnx_plat_userconfig_parsing_8800d80x2(char *buffer, int size); 13 | void rwnx_plat_userconfig_parsing(char *buffer, int size); 14 | void rwnx_release_firmware_common(u32** buffer); 15 | 16 | 17 | int aicwf_set_rf_config_8800d80x2(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm) 18 | { 19 | int ret = 0; 20 | 21 | if ((ret = rwnx_send_txpwr_lvl_v4_req(rwnx_hw))) { 22 | return -1; 23 | } 24 | if ((ret = rwnx_send_txpwr_lvl_adj_req(rwnx_hw))) { 25 | return -1; 26 | } 27 | if ((ret = rwnx_send_txpwr_ofst2x_v2_req(rwnx_hw))) { 28 | return -1; 29 | } 30 | if ((ret = rwnx_send_rf_calib_req(rwnx_hw, cfm))) { 31 | return -1; 32 | } 33 | return 0 ; 34 | } 35 | 36 | 37 | int rwnx_plat_userconfig_load_8800d80x2(struct rwnx_hw *rwnx_hw){ 38 | int size; 39 | u32 *dst=NULL; 40 | char *filename = FW_USERCONFIG_NAME_8800D80X2; 41 | 42 | #ifndef ANDROID_PLATFORM 43 | sprintf(aic_fw_path, "%s/%s", aic_fw_path, "aic8800D80X2"); 44 | #endif 45 | 46 | AICWFDBG(LOGINFO, "userconfig file path:%s \r\n", filename); 47 | 48 | /* load file */ 49 | size = rwnx_request_firmware_common(rwnx_hw, &dst, filename); 50 | if (size <= 0) { 51 | AICWFDBG(LOGERROR, "wrong size of firmware file\n"); 52 | dst = NULL; 53 | return 0; 54 | } 55 | 56 | /* Copy the file on the Embedded side */ 57 | AICWFDBG(LOGINFO, "### Load file done: %s, size=%d\n", filename, size); 58 | 59 | rwnx_plat_userconfig_parsing_8800d80x2((char *)dst, size); 60 | 61 | rwnx_release_firmware_common(&dst); 62 | 63 | AICWFDBG(LOGINFO, "userconfig download complete\n\n"); 64 | return 0; 65 | 66 | } 67 | 68 | #ifdef CONFIG_POWER_LIMIT 69 | extern char default_ccode[]; 70 | int rwnx_plat_powerlimit_load_8800d80x2(struct rwnx_hw *rwnx_hw) 71 | { 72 | int size; 73 | u32 *dst=NULL; 74 | char *filename = FW_POWERLIMIT_NAME_8800D80X2; 75 | 76 | AICWFDBG(LOGINFO, "powerlimit file path:%s \r\n", filename); 77 | 78 | /* load file */ 79 | size = rwnx_request_firmware_common(rwnx_hw, &dst, filename); 80 | if (size <= 0) { 81 | AICWFDBG(LOGERROR, "wrong size of cfg file\n"); 82 | dst = NULL; 83 | return 0; 84 | } 85 | 86 | AICWFDBG(LOGINFO, "### Load file done: %s, size=%d\n", filename, size); 87 | 88 | /* parsing the file */ 89 | rwnx_plat_powerlimit_parsing((char *)dst, size, default_ccode); 90 | 91 | rwnx_release_firmware_common(&dst); 92 | 93 | AICWFDBG(LOGINFO, "powerlimit download complete\n\n"); 94 | return 0; 95 | } 96 | #endif 97 | 98 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_bfmer.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_bfmer.c 5 | * 6 | * @brief VHT Beamformer function definitions 7 | * 8 | * Copyright (C) RivieraWaves 2016-2019 9 | * 10 | ****************************************************************************** 11 | */ 12 | 13 | /** 14 | * INCLUDE FILES 15 | ****************************************************************************** 16 | */ 17 | 18 | #include 19 | #include "rwnx_bfmer.h" 20 | 21 | /** 22 | * FUNCTION DEFINITIONS 23 | ****************************************************************************** 24 | */ 25 | 26 | int rwnx_bfmer_report_add(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta, 27 | unsigned int length) 28 | { 29 | gfp_t flags; 30 | struct rwnx_bfmer_report *bfm_report ; 31 | 32 | if (in_softirq()) 33 | flags = GFP_ATOMIC; 34 | else 35 | flags = GFP_KERNEL; 36 | 37 | /* Allocate a structure that will contain the beamforming report */ 38 | bfm_report = kmalloc(sizeof(*bfm_report) + length, flags); 39 | 40 | 41 | /* Check report allocation */ 42 | if (!bfm_report) { 43 | /* Do not use beamforming */ 44 | return -1; 45 | } 46 | 47 | /* Store report length */ 48 | bfm_report->length = length; 49 | 50 | /* 51 | * Need to provide a Virtual Address to the MAC so that it can 52 | * upload the received Beamforming Report in driver memory 53 | */ 54 | bfm_report->dma_addr = dma_map_single(rwnx_hw->dev, &bfm_report->report[0], 55 | length, DMA_FROM_DEVICE); 56 | 57 | /* Check DMA mapping result */ 58 | if (dma_mapping_error(rwnx_hw->dev, bfm_report->dma_addr)) { 59 | /* Free allocated report */ 60 | kfree(bfm_report); 61 | /* And leave */ 62 | return -1; 63 | } 64 | 65 | /* Store report structure */ 66 | rwnx_sta->bfm_report = bfm_report; 67 | 68 | return 0; 69 | } 70 | 71 | void rwnx_bfmer_report_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta) 72 | { 73 | /* Verify if a report has been allocated */ 74 | if (rwnx_sta->bfm_report) { 75 | struct rwnx_bfmer_report *bfm_report = rwnx_sta->bfm_report; 76 | 77 | /* Unmap DMA region */ 78 | dma_unmap_single(rwnx_hw->dev, bfm_report->dma_addr, 79 | bfm_report->length, DMA_BIDIRECTIONAL); 80 | 81 | /* Free allocated report structure and clean the pointer */ 82 | kfree(bfm_report); 83 | rwnx_sta->bfm_report = NULL; 84 | } 85 | } 86 | 87 | #ifdef CONFIG_RWNX_FULLMAC 88 | u8 rwnx_bfmer_get_rx_nss(const struct ieee80211_vht_cap *vht_capa) 89 | { 90 | int i; 91 | u8 rx_nss = 0; 92 | u16 rx_mcs_map = le16_to_cpu(vht_capa->supp_mcs.rx_mcs_map); 93 | 94 | for (i = 7; i >= 0; i--) { 95 | u8 mcs = (rx_mcs_map >> (2 * i)) & 3; 96 | 97 | if (mcs != IEEE80211_VHT_MCS_NOT_SUPPORTED) { 98 | rx_nss = i + 1; 99 | break; 100 | } 101 | } 102 | 103 | return rx_nss; 104 | } 105 | #endif /* CONFIG_RWNX_FULLMAC */ 106 | -------------------------------------------------------------------------------- /fw/aic8800D80/aic_userconfig_8800d80.txt: -------------------------------------------------------------------------------- 1 | # AIC USERCONFIG 2022/0803/1707 2 | 3 | # txpwr_lvl 4 | enable=1 5 | lvl_11b_11ag_1m_2g4=18 6 | lvl_11b_11ag_2m_2g4=18 7 | lvl_11b_11ag_5m5_2g4=18 8 | lvl_11b_11ag_11m_2g4=18 9 | lvl_11b_11ag_6m_2g4=18 10 | lvl_11b_11ag_9m_2g4=18 11 | lvl_11b_11ag_12m_2g4=18 12 | lvl_11b_11ag_18m_2g4=18 13 | lvl_11b_11ag_24m_2g4=16 14 | lvl_11b_11ag_36m_2g4=16 15 | lvl_11b_11ag_48m_2g4=15 16 | lvl_11b_11ag_54m_2g4=15 17 | lvl_11n_11ac_mcs0_2g4=18 18 | lvl_11n_11ac_mcs1_2g4=18 19 | lvl_11n_11ac_mcs2_2g4=18 20 | lvl_11n_11ac_mcs3_2g4=18 21 | lvl_11n_11ac_mcs4_2g4=16 22 | lvl_11n_11ac_mcs5_2g4=16 23 | lvl_11n_11ac_mcs6_2g4=15 24 | lvl_11n_11ac_mcs7_2g4=15 25 | lvl_11n_11ac_mcs8_2g4=14 26 | lvl_11n_11ac_mcs9_2g4=14 27 | lvl_11ax_mcs0_2g4=18 28 | lvl_11ax_mcs1_2g4=18 29 | lvl_11ax_mcs2_2g4=18 30 | lvl_11ax_mcs3_2g4=18 31 | lvl_11ax_mcs4_2g4=16 32 | lvl_11ax_mcs5_2g4=16 33 | lvl_11ax_mcs6_2g4=15 34 | lvl_11ax_mcs7_2g4=15 35 | lvl_11ax_mcs8_2g4=14 36 | lvl_11ax_mcs9_2g4=14 37 | lvl_11ax_mcs10_2g4=13 38 | lvl_11ax_mcs11_2g4=13 39 | lvl_11a_6m_5g=18 40 | lvl_11a_9m_5g=18 41 | lvl_11a_12m_5g=18 42 | lvl_11a_18m_5g=18 43 | lvl_11a_24m_5g=16 44 | lvl_11a_36m_5g=16 45 | lvl_11a_48m_5g=15 46 | lvl_11a_54m_5g=15 47 | lvl_11n_11ac_mcs0_5g=18 48 | lvl_11n_11ac_mcs1_5g=18 49 | lvl_11n_11ac_mcs2_5g=18 50 | lvl_11n_11ac_mcs3_5g=18 51 | lvl_11n_11ac_mcs4_5g=16 52 | lvl_11n_11ac_mcs5_5g=16 53 | lvl_11n_11ac_mcs6_5g=15 54 | lvl_11n_11ac_mcs7_5g=15 55 | lvl_11n_11ac_mcs8_5g=14 56 | lvl_11n_11ac_mcs9_5g=14 57 | lvl_11ax_mcs0_5g=18 58 | lvl_11ax_mcs1_5g=18 59 | lvl_11ax_mcs2_5g=18 60 | lvl_11ax_mcs3_5g=18 61 | lvl_11ax_mcs4_5g=16 62 | lvl_11ax_mcs5_5g=16 63 | lvl_11ax_mcs6_5g=14 64 | lvl_11ax_mcs7_5g=14 65 | lvl_11ax_mcs8_5g=13 66 | lvl_11ax_mcs9_5g=13 67 | lvl_11ax_mcs10_5g=12 68 | lvl_11ax_mcs11_5g=12 69 | 70 | # txpwr_lvl_adj 71 | lvl_adj_enable=0 72 | lvl_adj_2g4_chan_1_4=0 73 | lvl_adj_2g4_chan_5_9=0 74 | lvl_adj_2g4_chan_10_13=0 75 | lvl_adj_5g_chan_42=0 76 | lvl_adj_5g_chan_58=0 77 | lvl_adj_5g_chan_106=0 78 | lvl_adj_5g_chan_122=0 79 | lvl_adj_5g_chan_138=0 80 | lvl_adj_5g_chan_155=0 81 | 82 | # txpwr_loss 83 | loss_enable=0 84 | loss_value=2 85 | 86 | # txpwr_ofst 87 | ofst_enable=0 88 | ofst_2g4_11b_chan_1_4=0 89 | ofst_2g4_11b_chan_5_9=0 90 | ofst_2g4_11b_chan_10_13=0 91 | ofst_2g4_ofdm_highrate_chan_1_4=0 92 | ofst_2g4_ofdm_highrate_chan_5_9=0 93 | ofst_2g4_ofdm_highrate_chan_10_13=0 94 | ofst_2g4_ofdm_lowrate_chan_1_4=0 95 | ofst_2g4_ofdm_lowrate_chan_5_9=0 96 | ofst_2g4_ofdm_lowrate_chan_10_13=0 97 | ofst_5g_ofdm_lowrate_chan_42=0 98 | ofst_5g_ofdm_lowrate_chan_58=0 99 | ofst_5g_ofdm_lowrate_chan_106=0 100 | ofst_5g_ofdm_lowrate_chan_122=0 101 | ofst_5g_ofdm_lowrate_chan_138=0 102 | ofst_5g_ofdm_lowrate_chan_155=0 103 | ofst_5g_ofdm_highrate_chan_42=0 104 | ofst_5g_ofdm_highrate_chan_58=0 105 | ofst_5g_ofdm_highrate_chan_106=0 106 | ofst_5g_ofdm_highrate_chan_122=0 107 | ofst_5g_ofdm_highrate_chan_138=0 108 | ofst_5g_ofdm_highrate_chan_155=0 109 | ofst_5g_ofdm_midrate_chan_42=0 110 | ofst_5g_ofdm_midrate_chan_58=0 111 | ofst_5g_ofdm_midrate_chan_106=0 112 | ofst_5g_ofdm_midrate_chan_122=0 113 | ofst_5g_ofdm_midrate_chan_138=0 114 | ofst_5g_ofdm_midrate_chan_155=0 115 | 116 | # xtal cap 117 | xtal_enable=0 118 | xtal_cap=24 119 | xtal_cap_fine=31 120 | 121 | 122 | 123 | -------------------------------------------------------------------------------- /fw/aic8800D80X2/aic_userconfig_8800d80x2.txt: -------------------------------------------------------------------------------- 1 | # AIC USERCONFIG 2022/0803/1707 2 | 3 | # txpwr_lvl 4 | enable=1 5 | lvl_11b_11ag_1m_2g4=18 6 | lvl_11b_11ag_2m_2g4=18 7 | lvl_11b_11ag_5m5_2g4=18 8 | lvl_11b_11ag_11m_2g4=18 9 | lvl_11b_11ag_6m_2g4=18 10 | lvl_11b_11ag_9m_2g4=18 11 | lvl_11b_11ag_12m_2g4=18 12 | lvl_11b_11ag_18m_2g4=18 13 | lvl_11b_11ag_24m_2g4=16 14 | lvl_11b_11ag_36m_2g4=16 15 | lvl_11b_11ag_48m_2g4=15 16 | lvl_11b_11ag_54m_2g4=15 17 | lvl_11n_11ac_mcs0_2g4=18 18 | lvl_11n_11ac_mcs1_2g4=18 19 | lvl_11n_11ac_mcs2_2g4=18 20 | lvl_11n_11ac_mcs3_2g4=18 21 | lvl_11n_11ac_mcs4_2g4=16 22 | lvl_11n_11ac_mcs5_2g4=16 23 | lvl_11n_11ac_mcs6_2g4=15 24 | lvl_11n_11ac_mcs7_2g4=15 25 | lvl_11n_11ac_mcs8_2g4=14 26 | lvl_11n_11ac_mcs9_2g4=14 27 | lvl_11ax_mcs0_2g4=18 28 | lvl_11ax_mcs1_2g4=18 29 | lvl_11ax_mcs2_2g4=18 30 | lvl_11ax_mcs3_2g4=18 31 | lvl_11ax_mcs4_2g4=16 32 | lvl_11ax_mcs5_2g4=16 33 | lvl_11ax_mcs6_2g4=15 34 | lvl_11ax_mcs7_2g4=15 35 | lvl_11ax_mcs8_2g4=14 36 | lvl_11ax_mcs9_2g4=14 37 | lvl_11ax_mcs10_2g4=13 38 | lvl_11ax_mcs11_2g4=13 39 | lvl_11a_6m_5g=18 40 | lvl_11a_9m_5g=18 41 | lvl_11a_12m_5g=18 42 | lvl_11a_18m_5g=18 43 | lvl_11a_24m_5g=16 44 | lvl_11a_36m_5g=16 45 | lvl_11a_48m_5g=15 46 | lvl_11a_54m_5g=15 47 | lvl_11n_11ac_mcs0_5g=18 48 | lvl_11n_11ac_mcs1_5g=18 49 | lvl_11n_11ac_mcs2_5g=18 50 | lvl_11n_11ac_mcs3_5g=18 51 | lvl_11n_11ac_mcs4_5g=16 52 | lvl_11n_11ac_mcs5_5g=16 53 | lvl_11n_11ac_mcs6_5g=15 54 | lvl_11n_11ac_mcs7_5g=15 55 | lvl_11n_11ac_mcs8_5g=14 56 | lvl_11n_11ac_mcs9_5g=14 57 | lvl_11ax_mcs0_5g=18 58 | lvl_11ax_mcs1_5g=18 59 | lvl_11ax_mcs2_5g=18 60 | lvl_11ax_mcs3_5g=18 61 | lvl_11ax_mcs4_5g=16 62 | lvl_11ax_mcs5_5g=16 63 | lvl_11ax_mcs6_5g=14 64 | lvl_11ax_mcs7_5g=14 65 | lvl_11ax_mcs8_5g=13 66 | lvl_11ax_mcs9_5g=13 67 | lvl_11ax_mcs10_5g=12 68 | lvl_11ax_mcs11_5g=12 69 | 70 | # txpwr_lvl_adj 71 | lvl_adj_enable=0 72 | lvl_adj_2g4_chan_1_4=0 73 | lvl_adj_2g4_chan_5_9=0 74 | lvl_adj_2g4_chan_10_13=0 75 | lvl_adj_5g_chan_42=0 76 | lvl_adj_5g_chan_58=0 77 | lvl_adj_5g_chan_106=0 78 | lvl_adj_5g_chan_122=0 79 | lvl_adj_5g_chan_138=0 80 | lvl_adj_5g_chan_155=0 81 | 82 | # txpwr_loss 83 | loss_enable=0 84 | loss_value=2 85 | 86 | # txpwr_ofst 87 | ofst_enable=0 88 | ofst_2g4_ant0_11b_chan_1_4=0 89 | ofst_2g4_ant0_11b_chan_5_9=0 90 | ofst_2g4_ant0_11b_chan_10_13=0 91 | ofst_2g4_ant0_ofdm_highrate_chan_1_4=0 92 | ofst_2g4_ant0_ofdm_highrate_chan_5_9=0 93 | ofst_2g4_ant0_ofdm_highrate_chan_10_13=0 94 | ofst_2g4_ant1_11b_chan_1_4=0 95 | ofst_2g4_ant1_11b_chan_5_9=0 96 | ofst_2g4_ant1_11b_chan_10_13=0 97 | ofst_2g4_ant1_ofdm_highrate_chan_1_4=0 98 | ofst_2g4_ant1_ofdm_highrate_chan_5_9=0 99 | ofst_2g4_ant1_ofdm_highrate_chan_10_13=0 100 | ofst_5g_ant0_ofdm_highrate_chan_42=0 101 | ofst_5g_ant0_ofdm_highrate_chan_58=0 102 | ofst_5g_ant0_ofdm_highrate_chan_106=0 103 | ofst_5g_ant0_ofdm_highrate_chan_122=0 104 | ofst_5g_ant0_ofdm_highrate_chan_138=0 105 | ofst_5g_ant0_ofdm_highrate_chan_155=0 106 | ofst_5g_ant1_ofdm_highrate_chan_42=0 107 | ofst_5g_ant1_ofdm_highrate_chan_58=0 108 | ofst_5g_ant1_ofdm_highrate_chan_106=0 109 | ofst_5g_ant1_ofdm_highrate_chan_122=0 110 | ofst_5g_ant1_ofdm_highrate_chan_138=0 111 | ofst_5g_ant1_ofdm_highrate_chan_155=0 112 | 113 | # xtal cap 114 | xtal_enable=0 115 | xtal_cap=24 116 | xtal_cap_fine=31 117 | 118 | 119 | 120 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | CONFIG_AIC_LOADFW_SUPPORT := m 2 | CONFIG_AIC8800_WLAN_SUPPORT := m 3 | 4 | obj-$(CONFIG_AIC_LOADFW_SUPPORT) += aic_load_fw/ 5 | obj-$(CONFIG_AIC8800_WLAN_SUPPORT) += aic8800_fdrv/ 6 | 7 | ########## config option ########## 8 | export CONFIG_USE_FW_REQUEST = n 9 | export CONFIG_PREALLOC_RX_SKB = y 10 | export CONFIG_PREALLOC_TXQ = y 11 | ################################### 12 | 13 | ########## platform support list ########## 14 | export CONFIG_PLATFORM_ROCKCHIP = n 15 | export CONFIG_PLATFORM_ALLWINNER = n 16 | export CONFIG_PLATFORM_AMLOGIC = n 17 | export CONFIG_PLATFORM_HI = n 18 | export CONFIG_PLATFORM_UBUNTU = y 19 | 20 | ifeq ($(CONFIG_PLATFORM_ROCKCHIP), y) 21 | ARCH = arm64 22 | KDIR = /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/kernel 23 | CROSS_COMPILE = /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu- 24 | ccflags-y += -DANDROID_PLATFORM 25 | endif 26 | 27 | ifeq ($(CONFIG_PLATFORM_ALLWINNER), y) 28 | KDIR = /home/yaya/E/Allwinner/R818/R818/AndroidQ/lichee/kernel/linux-4.9 29 | ARCH = arm64 30 | CROSS_COMPILE = /home/yaya/E/Allwinner/R818/R818/AndroidQ/lichee/out/gcc-linaro-5.3.1-2016.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu- 31 | ccflags-y += -DANDROID_PLATFORM 32 | endif 33 | 34 | ifeq ($(CONFIG_PLATFORM_AMLOGIC), y) 35 | ccflags-y += -DANDROID_PLATFORM 36 | ARCH = arm 37 | CROSS_COMPILE = /home/yaya/D/Workspace/CyberQuantum/JinHaoYue/amls905x3/SDK/20191101-0tt-asop/android9.0/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.9/bin/arm-linux-androidkernel- 38 | KDIR = /home/yaya/D/Workspace/CyberQuantum/JinHaoYue/amls905x3/SDK/20191101-0tt-asop/android9.0/out/target/product/u202/obj/KERNEL_OBJ/ 39 | endif 40 | 41 | ifeq ($(CONFIG_PLATFORM_HI), y) 42 | ccflags-y += -DANDROID_PLATFORM 43 | ARCH = arm 44 | CROSS_COMPILE = /home/yaya/D/Workspace/CyberQuantum/JinHaoYue/amls905x3/SDK/20191101-0tt-asop/android9.0/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.9/bin/arm-linux-androidkernel- 45 | KDIR = /home/yaya/D/Workspace/CyberQuantum/JinHaoYue/amls905x3/SDK/20191101-0tt-asop/android9.0/out/target/product/u202/obj/KERNEL_OBJ/ 46 | endif 47 | 48 | ifeq ($(CONFIG_PLATFORM_UBUNTU), y) 49 | KDIR = /lib/modules/$(shell uname -r)/build 50 | PWD = $(shell pwd) 51 | KVER = $(shell uname -r) 52 | MODDESTDIR = /lib/modules/$(KVER)/kernel/drivers/net/wireless/aic8800 53 | SUBARCH = $(shell uname -m | sed -e s/i.86/i386/ -e s/armv.l/arm/ -e s/aarch64/arm64/) 54 | ARCH ?= $(SUBARCH) 55 | CROSS_COMPILE ?= 56 | endif 57 | 58 | ########################################### 59 | 60 | MAKEFLAGS +=-j$(shell nproc) 61 | 62 | all: modules 63 | modules: 64 | make -C $(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules 65 | 66 | install: 67 | mkdir -p $(MODDESTDIR) 68 | install -p -m 644 aic_load_fw/aic_load_fw.ko $(MODDESTDIR)/ 69 | install -p -m 644 aic8800_fdrv/aic8800_fdrv.ko $(MODDESTDIR)/ 70 | /sbin/depmod -a ${KVER} 71 | 72 | uninstall: 73 | rm -rfv $(MODDESTDIR)/aic_load_fw.ko 74 | rm -rfv $(MODDESTDIR)/aic8800_fdrv.ko 75 | /sbin/depmod -a ${KVER} 76 | 77 | clean: 78 | cd aic_load_fw/;make clean;cd .. 79 | cd aic8800_fdrv/;make clean;cd .. 80 | rm -rf modules.order Module.symvers .modules.order.cmd .Module.symvers.cmd .tmp_versions/ 81 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_utils.h: -------------------------------------------------------------------------------- 1 | /** 2 | * rwnx_ipc_utils.h 3 | * 4 | * IPC utility function declarations 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | */ 8 | #ifndef _RWNX_IPC_UTILS_H_ 9 | #define _RWNX_IPC_UTILS_H_ 10 | 11 | #include 12 | #include 13 | #include 14 | 15 | #include "lmac_msg.h" 16 | #include "aicwf_debug.h" 17 | 18 | 19 | #if 0 20 | #ifdef CONFIG_RWNX_DBG 21 | /* #define RWNX_DBG(format, arg...) pr_warn(format, ## arg) */ 22 | #define RWNX_DBG printk 23 | #else 24 | #define RWNX_DBG(a...) do {} while (0) 25 | #endif 26 | #endif 27 | 28 | 29 | 30 | enum rwnx_dev_flag { 31 | RWNX_DEV_RESTARTING, 32 | RWNX_DEV_STACK_RESTARTING, 33 | RWNX_DEV_STARTED, 34 | }; 35 | 36 | struct rwnx_hw; 37 | struct rwnx_sta; 38 | 39 | /** 40 | * struct rwnx_ipc_elem - Generic IPC buffer of fixed size 41 | * 42 | * @addr: Host address of the buffer. 43 | * @dma_addr: DMA address of the buffer. 44 | */ 45 | struct rwnx_ipc_elem { 46 | void *addr; 47 | dma_addr_t dma_addr; 48 | }; 49 | 50 | /** 51 | * struct rwnx_ipc_elem_pool - Generic pool of IPC buffers of fixed size 52 | * 53 | * @nb: Number of buffers currenlty allocated in the pool 54 | * @buf: Array of buffers (size of array is @nb) 55 | * @pool: DMA pool in which buffers have been allocated 56 | */ 57 | struct rwnx_ipc_elem_pool { 58 | int nb; 59 | struct rwnx_ipc_elem *buf; 60 | struct dma_pool *pool; 61 | }; 62 | 63 | /** 64 | * struct rwnx_ipc_elem - Generic IPC buffer of variable size 65 | * 66 | * @addr: Host address of the buffer. 67 | * @dma_addr: DMA address of the buffer. 68 | * @size: Size, in bytes, of the buffer 69 | */ 70 | struct rwnx_ipc_elem_var { 71 | void *addr; 72 | dma_addr_t dma_addr; 73 | size_t size; 74 | }; 75 | 76 | /** 77 | * struct rwnx_ipc_dbgdump_elem - IPC buffer for debug dump 78 | * 79 | * @mutex: Mutex to protect access to debug dump 80 | * @buf: IPC buffer 81 | */ 82 | struct rwnx_ipc_dbgdump_elem { 83 | struct mutex mutex; 84 | struct rwnx_ipc_elem_var buf; 85 | }; 86 | 87 | static const u32 rwnx_rxbuff_pattern = 0xCAFEFADE; 88 | 89 | /* 90 | * Maximum Length of Radiotap header vendor specific data(in bytes) 91 | */ 92 | #define RADIOTAP_HDR_VEND_MAX_LEN 16 93 | 94 | /* 95 | * Maximum Radiotap Header Length without vendor specific data (in bytes) 96 | */ 97 | #define RADIOTAP_HDR_MAX_LEN 80 98 | 99 | /* 100 | * Unsupported HT Frame data length (in bytes) 101 | */ 102 | #define UNSUP_RX_VEC_DATA_LEN 2 103 | 104 | /** 105 | * struct rwnx_ipc_skb_elem - IPC buffer for SKB element 106 | * 107 | * @skb: Pointer to the skb buffer allocated 108 | * @dma_addr: DMA address of the data buffer fo skb 109 | * 110 | */ 111 | struct rwnx_ipc_skb_elem { 112 | struct sk_buff *skb; 113 | dma_addr_t dma_addr; 114 | }; 115 | 116 | #ifdef CONFIG_RWNX_FULLMAC 117 | 118 | /* Maximum number of rx buffer the fw may use at the same time */ 119 | #define RWNX_RXBUFF_MAX (64 * NX_REMOTE_STA_MAX) 120 | 121 | /** 122 | * struct rwnx_ipc_rxbuf_elems - IPC buffers for RX 123 | * 124 | * @skb: Array of buffer push to FW. 125 | * @idx: Index of the last pushed skb.(Use to find the next free entry quicker) 126 | * 127 | * Note: contrary to softmac version, dma_addr are stored inside skb->cb. 128 | * (cf &struct rwnx_skb_cb) 129 | */ 130 | struct rwnx_ipc_rxbuf_elems { 131 | struct sk_buff *skb[RWNX_RXBUFF_MAX]; 132 | int idx; 133 | }; 134 | 135 | #endif /* CONFIG_RWNX_FULLMAC */ 136 | #endif /* _RWNX_IPC_UTILS_H_ */ 137 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_sdio.h: -------------------------------------------------------------------------------- 1 | /** 2 | * aicwf_sdio.h 3 | * 4 | * SDIO function declarations 5 | * 6 | * Copyright (C) AICSemi 2018-2020 7 | */ 8 | 9 | #ifndef _AICWF_SDMMC_H_ 10 | #define _AICWF_SDMMC_H_ 11 | 12 | #ifdef AICWF_SDIO_SUPPORT 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include "rwnx_cmds.h" 18 | #define AICWF_SDIO_NAME "aicwf_sdio" 19 | #define SDIOWIFI_FUNC_BLOCKSIZE 512 20 | 21 | #define SDIO_VENDOR_ID_AIC 0x8800 22 | #define SDIO_DEVICE_ID_AIC 0x0001 23 | #define SDIOWIFI_BYTEMODE_LEN_REG 0x02 24 | #define SDIOWIFI_INTR_CONFIG_REG 0x04 25 | #define SDIOWIFI_SLEEP_REG 0x05 26 | #define SDIOWIFI_WAKEUP_REG 0x09 27 | #define SDIOWIFI_FLOW_CTRL_REG 0x0A 28 | #define SDIOWIFI_REGISTER_BLOCK 0x0B 29 | #define SDIOWIFI_BYTEMODE_ENABLE_REG 0x11 30 | #define SDIOWIFI_BLOCK_CNT_REG 0x12 31 | #define SDIOWIFI_FLOWCTRL_MASK_REG 0x7F 32 | 33 | #define SDIOWIFI_PWR_CTRL_INTERVAL 30 34 | #define FLOW_CTRL_RETRY_COUNT 50 35 | #define BUFFER_SIZE 1536 36 | #define TAIL_LEN 4 37 | #define TXQLEN (2048*4) 38 | 39 | #define SDIO_SLEEP_ST 0 40 | #define SDIO_ACTIVE_ST 1 41 | 42 | typedef enum { 43 | SDIO_TYPE_DATA = 0X00, 44 | SDIO_TYPE_CFG = 0X10, 45 | SDIO_TYPE_CFG_CMD_RSP = 0X11, 46 | SDIO_TYPE_CFG_DATA_CFM = 0X12 47 | } sdio_type; 48 | 49 | struct rwnx_hw; 50 | 51 | 52 | struct aic_sdio_dev { 53 | struct rwnx_hw *rwnx_hw; 54 | struct sdio_func *func; 55 | struct device *dev; 56 | struct aicwf_bus *bus_if; 57 | struct rwnx_cmd_mgr cmd_mgr; 58 | 59 | struct aicwf_rx_priv *rx_priv; 60 | struct aicwf_tx_priv *tx_priv; 61 | u32 state; 62 | 63 | //for sdio pwr ctrl 64 | struct timer_list timer; 65 | uint active_duration; 66 | struct completion pwrctrl_trgg; 67 | struct task_struct *pwrctl_tsk; 68 | spinlock_t pwrctl_lock; 69 | struct semaphore pwrctl_wakeup_sema; 70 | }; 71 | int aicwf_sdio_writeb(struct aic_sdio_dev *sdiodev, uint regaddr, u8 val); 72 | void aicwf_sdio_hal_irqhandler(struct sdio_func *func); 73 | void aicwf_sdio_pwrctl_timer(struct aic_sdio_dev *sdiodev, uint duration); 74 | int aicwf_sdio_pwr_stctl(struct aic_sdio_dev *sdiodev, uint target); 75 | int aicwf_sdio_func_init(struct aic_sdio_dev *sdiodev); 76 | void aicwf_sdio_func_deinit(struct aic_sdio_dev *sdiodev); 77 | int aicwf_sdio_flow_ctrl(struct aic_sdio_dev *sdiodev); 78 | int aicwf_sdio_recv_pkt(struct aic_sdio_dev *sdiodev, struct sk_buff *skbbuf, u32 size); 79 | int aicwf_sdio_send_pkt(struct aic_sdio_dev *sdiodev, u8 *buf, uint count); 80 | void *aicwf_sdio_bus_init(struct aic_sdio_dev *sdiodev); 81 | void aicwf_sdio_release(struct aic_sdio_dev *sdiodev); 82 | void aicwf_sdio_exit(void); 83 | void aicwf_sdio_register(void); 84 | int aicwf_sdio_txpkt(struct aic_sdio_dev *sdiodev, struct sk_buff *pkt); 85 | int sdio_bustx_thread(void *data); 86 | int sdio_busrx_thread(void *data); 87 | int aicwf_sdio_aggr(struct aicwf_tx_priv *tx_priv, struct sk_buff *pkt); 88 | int aicwf_sdio_send(struct aicwf_tx_priv *tx_priv); 89 | void aicwf_sdio_aggr_send(struct aicwf_tx_priv *tx_priv); 90 | void aicwf_sdio_aggrbuf_reset(struct aicwf_tx_priv* tx_priv); 91 | extern void aicwf_hostif_ready(void); 92 | #ifdef CONFIG_PLATFORM_NANOPI 93 | extern void extern_wifi_set_enable(int is_on); 94 | extern void sdio_reinit(void); 95 | #endif /*CONFIG_PLATFORM_NANOPI*/ 96 | 97 | #endif /* AICWF_SDIO_SUPPORT */ 98 | 99 | #endif /*_AICWF_SDMMC_H_*/ 100 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_bfmer.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_bfmer.h 5 | * 6 | * @brief VHT Beamformer function declarations 7 | * 8 | * Copyright (C) RivieraWaves 2016-2019 9 | * 10 | ****************************************************************************** 11 | */ 12 | 13 | #ifndef _RWNX_BFMER_H_ 14 | #define _RWNX_BFMER_H_ 15 | 16 | /** 17 | * INCLUDE FILES 18 | ****************************************************************************** 19 | */ 20 | 21 | #include "rwnx_defs.h" 22 | 23 | /** 24 | * DEFINES 25 | ****************************************************************************** 26 | */ 27 | 28 | /// Maximal supported report length (in bytes) 29 | #define RWNX_BFMER_REPORT_MAX_LEN 2048 30 | 31 | /// Size of the allocated report space (twice the maximum report length) 32 | #define RWNX_BFMER_REPORT_SPACE_SIZE (RWNX_BFMER_REPORT_MAX_LEN * 2) 33 | 34 | /** 35 | * TYPE DEFINITIONS 36 | ****************************************************************************** 37 | */ 38 | 39 | /* 40 | * Structure used to store a beamforming report. 41 | */ 42 | struct rwnx_bfmer_report { 43 | dma_addr_t dma_addr; /* Virtual address provided to MAC for 44 | DMA transfer of the Beamforming Report */ 45 | unsigned int length; /* Report Length */ 46 | u8 report[1]; /* Report to be used for VHT TX Beamforming */ 47 | }; 48 | 49 | /** 50 | * FUNCTION DECLARATIONS 51 | ****************************************************************************** 52 | */ 53 | 54 | /** 55 | ****************************************************************************** 56 | * @brief Allocate memory aiming to contains the Beamforming Report received 57 | * from a Beamformee capable capable. 58 | * The providing length shall be large enough to contain the VHT Compressed 59 | * Beaforming Report and the MU Exclusive part. 60 | * It also perform a DMA Mapping providing an address to be provided to the HW 61 | * responsible for the DMA transfer of the report. 62 | * If successful a struct rwnx_bfmer_report object is allocated, it's address 63 | * is stored in rwnx_sta->bfm_report. 64 | * 65 | * @param[in] rwnx_hw PHY Information 66 | * @param[in] rwnx_sta Peer STA Information 67 | * @param[in] length Memory size to be allocated 68 | * 69 | * @return 0 if operation is successful, else -1. 70 | ****************************************************************************** 71 | */ 72 | int rwnx_bfmer_report_add(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta, 73 | unsigned int length); 74 | 75 | /** 76 | ****************************************************************************** 77 | * @brief Free a previously allocated memory intended to be used for 78 | * Beamforming Reports. 79 | * 80 | * @param[in] rwnx_hw PHY Information 81 | * @param[in] rwnx_sta Peer STA Information 82 | * 83 | ****************************************************************************** 84 | */ 85 | void rwnx_bfmer_report_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta); 86 | 87 | #ifdef CONFIG_RWNX_FULLMAC 88 | /** 89 | ****************************************************************************** 90 | * @brief Parse a Rx VHT-MCS map in order to deduce the maximum number of 91 | * Spatial Streams supported by a beamformee. 92 | * 93 | * @param[in] vht_capa Received VHT Capability field. 94 | * 95 | ****************************************************************************** 96 | */ 97 | u8 rwnx_bfmer_get_rx_nss(const struct ieee80211_vht_cap *vht_capa); 98 | #endif /* CONFIG_RWNX_FULLMAC */ 99 | 100 | #endif /* _RWNX_BFMER_H_ */ 101 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_cmds.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * rwnx_cmds.h 5 | * 6 | * Copyright (C) RivieraWaves 2014-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | 11 | #ifndef _RWNX_CMDS_H_ 12 | #define _RWNX_CMDS_H_ 13 | 14 | #include 15 | #include 16 | #include 17 | #include "lmac_msg.h" 18 | 19 | #ifdef CONFIG_RWNX_SDM 20 | #define RWNX_80211_CMD_TIMEOUT_MS (20 * 300) 21 | #elif defined(CONFIG_RWNX_FHOST) 22 | #define RWNX_80211_CMD_TIMEOUT_MS (10000) 23 | #else 24 | #define RWNX_80211_CMD_TIMEOUT_MS 4000//500//300 25 | #endif 26 | 27 | #define RWNX_CMD_FLAG_NONBLOCK BIT(0) 28 | #define RWNX_CMD_FLAG_REQ_CFM BIT(1) 29 | #define RWNX_CMD_FLAG_WAIT_PUSH BIT(2) 30 | #define RWNX_CMD_FLAG_WAIT_ACK BIT(3) 31 | #define RWNX_CMD_FLAG_WAIT_CFM BIT(4) 32 | #define RWNX_CMD_FLAG_DONE BIT(5) 33 | /* ATM IPC design makes it possible to get the CFM before the ACK, 34 | * otherwise this could have simply been a state enum */ 35 | #define RWNX_CMD_WAIT_COMPLETE(flags) \ 36 | (!(flags & (RWNX_CMD_FLAG_WAIT_ACK | RWNX_CMD_FLAG_WAIT_CFM))) 37 | 38 | #define RWNX_CMD_MAX_QUEUED 16//8 AIDEN 39 | 40 | #ifdef CONFIG_RWNX_FHOST 41 | #include "ipc_fhost.h" 42 | #define rwnx_cmd_e2amsg ipc_fhost_msg 43 | #define rwnx_cmd_a2emsg ipc_fhost_msg 44 | #define RWNX_CMD_A2EMSG_LEN(m) (m->param_len) 45 | #define RWNX_CMD_E2AMSG_LEN_MAX IPC_FHOST_MSG_BUF_SIZE 46 | struct rwnx_term_stream; 47 | 48 | #else /* !CONFIG_RWNX_FHOST*/ 49 | #include "ipc_shared.h" 50 | #define rwnx_cmd_e2amsg ipc_e2a_msg 51 | #define rwnx_cmd_a2emsg lmac_msg 52 | #define RWNX_CMD_A2EMSG_LEN(m) (sizeof(struct lmac_msg) + m->param_len) 53 | #define RWNX_CMD_E2AMSG_LEN_MAX (IPC_E2A_MSG_PARAM_SIZE * 4) 54 | 55 | #endif /* CONFIG_RWNX_FHOST*/ 56 | 57 | struct rwnx_hw; 58 | struct rwnx_cmd; 59 | typedef int (*msg_cb_fct)(struct rwnx_hw *rwnx_hw, struct rwnx_cmd *cmd, 60 | struct rwnx_cmd_e2amsg *msg); 61 | static inline void put_u16(u8 *buf, u16 data) 62 | { 63 | buf[0] = (u8)(data&0x00ff); 64 | buf[1] = (u8)((data >> 8)&0x00ff); 65 | } 66 | 67 | enum rwnx_cmd_mgr_state { 68 | RWNX_CMD_MGR_STATE_DEINIT, 69 | RWNX_CMD_MGR_STATE_INITED, 70 | RWNX_CMD_MGR_STATE_CRASHED, 71 | }; 72 | 73 | struct rwnx_cmd { 74 | struct list_head list; 75 | lmac_msg_id_t id; 76 | lmac_msg_id_t reqid; 77 | struct rwnx_cmd_a2emsg *a2e_msg; 78 | char *e2a_msg; 79 | u32 tkn; 80 | u16 flags; 81 | 82 | struct completion complete; 83 | u32 result; 84 | u8 used; 85 | int array_id; 86 | #ifdef CONFIG_RWNX_FHOST 87 | struct rwnx_term_stream *stream; 88 | #endif 89 | }; 90 | 91 | struct rwnx_cmd_mgr { 92 | enum rwnx_cmd_mgr_state state; 93 | spinlock_t lock; 94 | u32 next_tkn; 95 | u32 queue_sz; 96 | u32 max_queue_sz; 97 | 98 | struct list_head cmds; 99 | 100 | int (*queue)(struct rwnx_cmd_mgr *, struct rwnx_cmd *); 101 | int (*llind)(struct rwnx_cmd_mgr *, struct rwnx_cmd *); 102 | int (*msgind)(struct rwnx_cmd_mgr *, struct rwnx_cmd_e2amsg *, msg_cb_fct); 103 | void (*print)(struct rwnx_cmd_mgr *); 104 | void (*drain)(struct rwnx_cmd_mgr *); 105 | 106 | struct work_struct cmdWork; 107 | struct workqueue_struct *cmd_wq; 108 | }; 109 | 110 | #define WAKE_CMD_WORK(cmd_mgr) \ 111 | do { \ 112 | queue_work((cmd_mgr)->cmd_wq, &cmd_mgr->cmdWork); \ 113 | } while (0) 114 | 115 | void rwnx_cmd_mgr_init(struct rwnx_cmd_mgr *cmd_mgr); 116 | void rwnx_cmd_mgr_deinit(struct rwnx_cmd_mgr *cmd_mgr); 117 | int cmd_mgr_queue_force_defer(struct rwnx_cmd_mgr *cmd_mgr, struct rwnx_cmd *cmd); 118 | void aicwf_set_cmd_tx(void *dev, struct lmac_msg *msg, uint len); 119 | 120 | #endif /* _RWNX_CMDS_H_ */ 121 | -------------------------------------------------------------------------------- /aic_load_fw/aicwf_rx_prealloc.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include "aicwf_rx_prealloc.h" 7 | #include "aicwf_debug.h" 8 | 9 | #ifdef CONFIG_PREALLOC_RX_SKB 10 | 11 | struct aicwf_rx_buff_list aic_rx_buff_list; 12 | 13 | int aic_rxbuff_num_max = 1000; 14 | #ifdef CONFIG_PLATFORM_HI 15 | int aic_rxbuff_size = (4 * 512) * 1; 16 | #else 17 | int aic_rxbuff_size = (4 * 512) * 10; 18 | #endif 19 | 20 | int rx_buff_list_ava = 0; 21 | 22 | module_param(rx_buff_list_ava, int, 0660); 23 | 24 | int aicwf_rxbuff_size_get(void) 25 | { 26 | return aic_rxbuff_size; 27 | } 28 | 29 | struct rx_buff *aicwf_prealloc_rxbuff_alloc(spinlock_t *lock) 30 | { 31 | unsigned long flags; 32 | struct rx_buff *rxbuff = NULL; 33 | 34 | spin_lock_irqsave(lock, flags); 35 | rx_buff_list_ava = atomic_read(&aic_rx_buff_list.rxbuff_list_len); 36 | if(rx_buff_list_ava < 10){ 37 | AICWFDBG(LOGERROR, "%s WARNING rxbuff is running out %d\r\n", __func__, 38 | rx_buff_list_ava); 39 | //msleep(10); 40 | mdelay(10); 41 | } 42 | 43 | if (list_empty(&aic_rx_buff_list.rxbuff_list)) { 44 | spin_unlock_irqrestore(lock, flags); 45 | AICWFDBG(LOGERROR, "%s %d, rxbuff list is empty\r\n", __func__, __LINE__); 46 | return NULL; 47 | } else { 48 | rxbuff = list_first_entry(&aic_rx_buff_list.rxbuff_list, 49 | struct rx_buff, queue); 50 | list_del_init(&rxbuff->queue); 51 | atomic_dec(&aic_rx_buff_list.rxbuff_list_len); 52 | } 53 | spin_unlock_irqrestore(lock, flags); 54 | //printk("len:%d\n", aic_rx_buff_list.rxbuff_list_len); 55 | memset(rxbuff->data, 0, aic_rxbuff_size); 56 | rxbuff->len = 0; 57 | rxbuff->start = NULL; 58 | rxbuff->read = NULL; 59 | rxbuff->end = NULL; 60 | 61 | return rxbuff; 62 | } 63 | 64 | void aicwf_prealloc_rxbuff_free(struct rx_buff *rxbuff, spinlock_t *lock) 65 | { 66 | unsigned long flags; 67 | 68 | spin_lock_irqsave(lock, flags); 69 | list_add_tail(&rxbuff->queue, &aic_rx_buff_list.rxbuff_list); 70 | atomic_inc(&aic_rx_buff_list.rxbuff_list_len); 71 | rx_buff_list_ava = atomic_read(&aic_rx_buff_list.rxbuff_list_len); 72 | spin_unlock_irqrestore(lock, flags); 73 | } 74 | 75 | int aicwf_prealloc_init(void) 76 | { 77 | struct rx_buff *rxbuff; 78 | int i = 0; 79 | 80 | AICWFDBG(LOGINFO, "%s enter\n", __func__); 81 | INIT_LIST_HEAD(&aic_rx_buff_list.rxbuff_list); 82 | 83 | for (i = 0 ; i < aic_rxbuff_num_max ; i++) { 84 | rxbuff = kzalloc(sizeof(struct rx_buff), GFP_KERNEL); 85 | if (rxbuff) { 86 | rxbuff->data = kzalloc(aic_rxbuff_size, GFP_KERNEL); 87 | if (rxbuff->data == NULL) { 88 | AICWFDBG(LOGERROR, "failed to alloc rxbuff data\n"); 89 | kfree(rxbuff); 90 | continue; 91 | } 92 | rxbuff->len = 0; 93 | rxbuff->start = NULL; 94 | rxbuff->read = NULL; 95 | rxbuff->end = NULL; 96 | list_add_tail(&rxbuff->queue, &aic_rx_buff_list.rxbuff_list); 97 | atomic_inc(&aic_rx_buff_list.rxbuff_list_len); 98 | rx_buff_list_ava = atomic_read(&aic_rx_buff_list.rxbuff_list_len); 99 | } 100 | } 101 | 102 | AICWFDBG(LOGINFO, "pre alloc rxbuff list len: %d\n", (int)atomic_read(&aic_rx_buff_list.rxbuff_list_len)); 103 | return 0; 104 | } 105 | 106 | void aicwf_prealloc_exit(void) 107 | { 108 | struct rx_buff *rxbuff; 109 | struct rx_buff *pos; 110 | 111 | AICWFDBG(LOGINFO, "%s enter\n", __func__); 112 | 113 | AICWFDBG(LOGINFO, "free pre alloc rxbuff list %d\n", (int)atomic_read(&aic_rx_buff_list.rxbuff_list_len)); 114 | list_for_each_entry_safe(rxbuff, pos, &aic_rx_buff_list.rxbuff_list, queue) { 115 | list_del_init(&rxbuff->queue); 116 | kfree(rxbuff->data); 117 | kfree(rxbuff); 118 | } 119 | } 120 | 121 | EXPORT_SYMBOL(aicwf_rxbuff_size_get); 122 | EXPORT_SYMBOL(aicwf_prealloc_rxbuff_alloc); 123 | EXPORT_SYMBOL(aicwf_prealloc_rxbuff_free); 124 | 125 | #endif 126 | 127 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_prof.h: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file rwnx_prof.h 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | **************************************************************************************** 9 | */ 10 | 11 | #ifndef _RWNX_PROF_H_ 12 | #define _RWNX_PROF_H_ 13 | 14 | #include "reg_access.h" 15 | #include "rwnx_platform.h" 16 | 17 | static inline void rwnx_prof_set(struct rwnx_hw *rwnx_hw, int val) 18 | { 19 | struct rwnx_plat *rwnx_plat = rwnx_hw->plat; 20 | RWNX_REG_WRITE(val, rwnx_plat, RWNX_ADDR_SYSTEM, NXMAC_SW_SET_PROFILING_ADDR); 21 | } 22 | 23 | static inline void rwnx_prof_clear(struct rwnx_hw *rwnx_hw, int val) 24 | { 25 | struct rwnx_plat *rwnx_plat = rwnx_hw->plat; 26 | RWNX_REG_WRITE(val, rwnx_plat, RWNX_ADDR_SYSTEM, NXMAC_SW_CLEAR_PROFILING_ADDR); 27 | } 28 | 29 | #if 0 30 | /* Defines for SW Profiling registers values */ 31 | enum { 32 | TX_IPC_IRQ, 33 | TX_IPC_EVT, 34 | TX_PREP_EVT, 35 | TX_DMA_IRQ, 36 | TX_MAC_IRQ, 37 | TX_PAYL_HDL, 38 | TX_CFM_EVT, 39 | TX_IPC_CFM, 40 | RX_MAC_IRQ, // 8 41 | RX_TRIGGER_EVT, 42 | RX_DMA_IRQ, 43 | RX_DMA_EVT, 44 | RX_IPC_IND, 45 | RX_MPDU_XFER, 46 | DBG_PROF_MAX 47 | }; 48 | #endif 49 | 50 | enum { 51 | SW_PROF_HOSTBUF_IDX = 12, 52 | /****** IPC IRQs related signals ******/ 53 | /* E2A direction */ 54 | SW_PROF_IRQ_E2A_RXDESC = 16, // to make sure we let 16 bits available for LMAC FW 55 | SW_PROF_IRQ_E2A_TXCFM, 56 | SW_PROF_IRQ_E2A_DBG, 57 | SW_PROF_IRQ_E2A_MSG, 58 | SW_PROF_IPC_MSGPUSH, 59 | SW_PROF_MSGALLOC, 60 | SW_PROF_MSGIND, 61 | SW_PROF_DBGIND, 62 | 63 | /* A2E direction */ 64 | SW_PROF_IRQ_A2E_TXCFM_BACK, 65 | 66 | /****** Driver functions related signals ******/ 67 | SW_PROF_WAIT_QUEUE_STOP, 68 | SW_PROF_WAIT_QUEUE_WAKEUP, 69 | SW_PROF_RWNXDATAIND, 70 | SW_PROF_RWNX_IPC_IRQ_HDLR, 71 | SW_PROF_RWNX_IPC_THR_IRQ_HDLR, 72 | SW_PROF_IEEE80211RX, 73 | SW_PROF_RWNX_PATTERN, 74 | SW_PROF_MAX 75 | }; 76 | 77 | // [LT]For debug purpose only 78 | #if (0) 79 | #define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (21) 80 | #define SW_PROF_CHAN_CTXT_CFM_BIT (22) 81 | #define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (23) 82 | #define SW_PROF_CHAN_CTXT_PUSH_BIT (24) 83 | #define SW_PROF_CHAN_CTXT_QUEUE_BIT (25) 84 | #define SW_PROF_CHAN_CTXT_TX_BIT (26) 85 | #define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (27) 86 | #define SW_PROF_CHAN_CTXT_PSWTCH_BIT (28) 87 | #define SW_PROF_CHAN_CTXT_SWTCH_BIT (29) 88 | 89 | // TO DO: update this 90 | 91 | #define REG_SW_SET_PROFILING_CHAN(env, bit) \ 92 | rwnx_prof_set((struct rwnx_hw*)env, BIT(bit)) 93 | 94 | #define REG_SW_CLEAR_PROFILING_CHAN(env, bit) \ 95 | rwnx_prof_clear((struct rwnx_hw*)env, BIT(bit)) 96 | 97 | #else 98 | #define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (0) 99 | #define SW_PROF_CHAN_CTXT_CFM_BIT (0) 100 | #define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (0) 101 | #define SW_PROF_CHAN_CTXT_PUSH_BIT (0) 102 | #define SW_PROF_CHAN_CTXT_QUEUE_BIT (0) 103 | #define SW_PROF_CHAN_CTXT_TX_BIT (0) 104 | #define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (0) 105 | #define SW_PROF_CHAN_CTXT_PSWTCH_BIT (0) 106 | #define SW_PROF_CHAN_CTXT_SWTCH_BIT (0) 107 | 108 | #define REG_SW_SET_PROFILING_CHAN(env, bit) do {} while (0) 109 | #define REG_SW_CLEAR_PROFILING_CHAN(env, bit) do {} while (0) 110 | #endif 111 | 112 | #ifdef CONFIG_RWNX_SW_PROFILING 113 | /* Macros for SW PRofiling registers access */ 114 | #define REG_SW_SET_PROFILING(env, bit) \ 115 | rwnx_prof_set((struct rwnx_hw*)env, BIT(bit)) 116 | 117 | #define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) \ 118 | rwnx_prof_set((struct rwnx_hw*)env, val<<(SW_PROF_HOSTBUF_IDX)) 119 | 120 | #define REG_SW_CLEAR_PROFILING(env, bit) \ 121 | rwnx_prof_clear((struct rwnx_hw*)env, BIT(bit)) 122 | 123 | #define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) \ 124 | rwnx_prof_clear((struct rwnx_hw*)env,0x0F<<(SW_PROF_HOSTBUF_IDX)) 125 | 126 | #else 127 | #define REG_SW_SET_PROFILING(env, value) do {} while (0) 128 | #define REG_SW_CLEAR_PROFILING(env, value) do {} while (0) 129 | #define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) do {} while (0) 130 | #define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) do {} while (0) 131 | #endif 132 | 133 | #endif /* _RWNX_PROF_H_ */ 134 | -------------------------------------------------------------------------------- /aic_load_fw/Makefile: -------------------------------------------------------------------------------- 1 | CONFIG_USB_SUPPORT =y 2 | CONFIG_RFTEST =y 3 | CONFIG_USB_BT =y 4 | CONFIG_USB_MSG_EP = y 5 | CONFIG_USB_NO_TRANS_DMA_MAP = n 6 | CONFIG_M2D_OTA_AUTO_SUPPORT = n 7 | CONFIG_LINK_DET_5G = y 8 | CONFIG_FOR_IPCAM = n 9 | CONFIG_USB_SUSPEND_REBOOT_TIME = n 10 | CONFIG_SUPPORT_USB_SUSP = n 11 | 12 | 13 | # Need to set fw path in BOARD_KERNEL_CMDLINE 14 | CONFIG_USE_FW_REQUEST ?= n 15 | CONFIG_PREALLOC_RX_SKB ?= n 16 | CONFIG_PREALLOC_TXQ ?= y 17 | 18 | # Platform support list 19 | CONFIG_PLATFORM_ROCKCHIP ?= n 20 | CONFIG_PLATFORM_ALLWINNER ?= n 21 | CONFIG_PLATFORM_AMLOGIC ?= n 22 | CONFIG_PLATFORM_HI ?= n 23 | CONFIG_PLATFORM_UBUNTU ?= y 24 | 25 | CONFIG_AIC_LOADFW_SUPPORT = m 26 | MODULE_NAME = aic_load_fw 27 | # CONFIG_AIC_FW_PATH = "/vendor/etc/firmware" 28 | # export CONFIG_AIC_FW_PATH 29 | 30 | ifeq ($(CONFIG_USB_SUPPORT), y) 31 | ccflags-y += -DAICWF_USB_SUPPORT 32 | endif 33 | ccflags-$(CONFIG_RFTEST) += -DCONFIG_RFTEST 34 | ccflags-$(CONFIG_USB_BT) += -DCONFIG_USB_BT 35 | ccflags-$(CONFIG_USB_MSG_EP) += -DCONFIG_USB_MSG_EP 36 | ccflags-$(CONFIG_USB_NO_TRANS_DMA_MAP) += -DCONFIG_USB_NO_TRANS_DMA_MAP 37 | ccflags-$(CONFIG_M2D_OTA_AUTO_SUPPORT) += -DCONFIG_M2D_OTA_AUTO_SUPPORT 38 | ccflags-$(CONFIG_LINK_DET_5G) += -DCONFIG_LINK_DET_5G 39 | ccflags-$(CONFIG_FOR_IPCAM) += -DCONFIG_FOR_IPCAM 40 | ccflags-$(CONFIG_USE_FW_REQUEST) += -DCONFIG_USE_FW_REQUEST 41 | ccflags-$(CONFIG_PREALLOC_RX_SKB) += -DCONFIG_PREALLOC_RX_SKB 42 | ccflags-$(CONFIG_PREALLOC_TXQ) += -DCONFIG_PREALLOC_TXQ 43 | ccflags-$(CONFIG_USB_SUSPEND_REBOOT_TIME) += -DCONFIG_USB_SUSPEND_REBOOT_TIME 44 | ccflags-$(CONFIG_SUPPORT_USB_SUSP) += -DCONFIG_SUPPORT_USB_SUSP 45 | 46 | 47 | obj-$(CONFIG_AIC_LOADFW_SUPPORT) := $(MODULE_NAME).o 48 | $(MODULE_NAME)-y := aic_bluetooth_main.o \ 49 | aicbluetooth.o \ 50 | aicwf_usb.o \ 51 | aic_txrxif.o \ 52 | aicbluetooth_cmds.o \ 53 | aic_compat_8800d80.o \ 54 | aic_compat_8800d80x2.o \ 55 | md5.o 56 | 57 | $(MODULE_NAME)-$(CONFIG_PREALLOC_RX_SKB) += aicwf_rx_prealloc.o 58 | $(MODULE_NAME)-$(CONFIG_PREALLOC_TXQ) += aicwf_txq_prealloc.o 59 | 60 | 61 | 62 | ifeq ($(CONFIG_PLATFORM_ROCKCHIP), y) 63 | ccflags-$(CONFIG_PLATFORM_ROCKCHIP) += -DCONFIG_PLATFORM_ROCKCHIP 64 | #KDIR := /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/kernel 65 | #ARCH ?= arm 66 | #CROSS_COMPILE ?= /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- 67 | KDIR := /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/kernel 68 | ARCH ?= arm 69 | CROSS_COMPILE ?= /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/prebuilts/gcc/linux-x86/arm/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf- 70 | #KDIR := /home/yaya/E/Rockchip/3399/rk3399-android-10/kernel 71 | #ARCH ?= arm64 72 | #CROSS_COMPILE ?= /home/yaya/E/Rockchip/3399/rk3399-android-10/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu- 73 | endif 74 | 75 | ifeq ($(CONFIG_PLATFORM_ALLWINNER), y) 76 | ccflags-$(CONFIG_PLATFORM_ALLWINNER) += -DCONFIG_PLATFORM_ALLWINNER 77 | KDIR := /home/yaya/E/Allwinner/R818/R818/AndroidQ/lichee/kernel/linux-4.9 78 | ARCH ?= arm64 79 | CROSS_COMPILE ?= /home/yaya/E/Allwinner/R818/R818/AndroidQ/lichee/out/gcc-linaro-5.3.1-2016.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu- 80 | endif 81 | 82 | ifeq ($(CONFIG_PLATFORM_AMLOGIC), y) 83 | ccflags-$(CONFIG_PLATFORM_AMLOGIC) += -DCONFIG_PLATFORM_AMLOGIC 84 | ARCH := arm 85 | CROSS_COMPILE := /home/yaya/D/Workspace/CyberQuantum/JinHaoYue/amls905x3/SDK/20191101-0tt-asop/android9.0/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.9/bin/arm-linux-androidkernel- 86 | KDIR := /home/yaya/D/Workspace/CyberQuantum/JinHaoYue/amls905x3/SDK/20191101-0tt-asop/android9.0/out/target/product/u202/obj/KERNEL_OBJ/ 87 | 88 | endif 89 | 90 | ifeq ($(CONFIG_PLATFORM_UBUNTU), y) 91 | ccflags-$(CONFIG_PLATFORM_UBUNTU) += -DCONFIG_PLATFORM_UBUNTU 92 | KDIR := /lib/modules/$(shell uname -r)/build 93 | PWD := $(shell pwd) 94 | KVER := $(shell uname -r) 95 | MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/aic8800 96 | SUBARCH = $(shell uname -m | sed -e s/i.86/i386/ -e s/armv.l/arm/ -e s/aarch64/arm64/) 97 | ARCH ?= $(SUBARCH) 98 | CROSS_COMPILE := 99 | endif 100 | 101 | 102 | all: modules 103 | modules: 104 | make -C $(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules 105 | 106 | install: 107 | mkdir -p $(MODDESTDIR) 108 | install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR)/ 109 | /sbin/depmod -a ${KVER} 110 | 111 | uninstall: 112 | rm -rfv $(MODDESTDIR)/$(MODULE_NAME).ko 113 | /sbin/depmod -a ${KVER} 114 | 115 | clean: 116 | rm -rf *.o *.ko *.o.* *.mod.* modules.* Module.* .a* .o* .*.o.* *.mod .tmp* .cache.mk .modules.order.cmd .Module.symvers.cmd 117 | -------------------------------------------------------------------------------- /aic8800_fdrv/sdio_host.c: -------------------------------------------------------------------------------- 1 | /** 2 | * sdio_host.c 3 | * 4 | * SDIO host function declarations 5 | * 6 | * Copyright (C) AICSemi 2018-2020 7 | */ 8 | 9 | 10 | #include "sdio_host.h" 11 | //#include "ipc_compat.h" 12 | #include "rwnx_tx.h" 13 | #include "rwnx_platform.h" 14 | 15 | /** 16 | **************************************************************************************** 17 | */ 18 | void aicwf_sdio_host_init(struct sdio_host_env_tag *env, 19 | void *cb, 20 | void *shared_env_ptr, 21 | void *pthis) 22 | { 23 | // Reset the environments 24 | 25 | // Reset the Host environment 26 | memset(env, 0, sizeof(struct sdio_host_env_tag)); 27 | // Save the pointer to the register base 28 | env->pthis = pthis; 29 | } 30 | 31 | /** 32 | **************************************************************************************** 33 | */ 34 | volatile struct txdesc_host *aicwf_sdio_host_txdesc_get(struct sdio_host_env_tag *env, const int queue_idx) 35 | { 36 | // struct ipc_shared_env_tag *shared_env_ptr = env->shared; 37 | volatile struct txdesc_host *txdesc_free; 38 | uint32_t used_idx = env->txdesc_used_idx[queue_idx]; 39 | uint32_t free_idx = env->txdesc_free_idx[queue_idx]; 40 | 41 | // ASSERT_ERR(queue_idx < SDIO_TXQUEUE_CNT); 42 | // ASSERT_ERR((free_idx - used_idx) <= SDIO_TXDESC_CNT); 43 | 44 | // Check if a free descriptor is available 45 | if (free_idx != (used_idx + SDIO_TXDESC_CNT)) 46 | { 47 | // Get the pointer to the first free descriptor 48 | // txdesc_free = shared_env_ptr->txdesc[queue_idx] + (free_idx % IPC_TXDESC_CNT); 49 | } 50 | else 51 | { 52 | txdesc_free = NULL; 53 | } 54 | 55 | return txdesc_free; 56 | } 57 | 58 | /** 59 | **************************************************************************************** 60 | */ 61 | void aicwf_sdio_host_txdesc_push(struct sdio_host_env_tag *env, const int queue_idx, const uint64_t host_id) 62 | { 63 | //printk("push, %d, %d, 0x%llx \r\n", queue_idx, env->txdesc_free_idx[queue_idx], host_id); 64 | // Save the host id in the environment 65 | env->tx_host_id[queue_idx][env->txdesc_free_idx[queue_idx] % SDIO_TXDESC_CNT] = host_id; 66 | 67 | // Increment the index 68 | env->txdesc_free_idx[queue_idx]++; 69 | if(env->txdesc_free_idx[queue_idx]==0x40000000) 70 | env->txdesc_free_idx[queue_idx] = 0; 71 | } 72 | 73 | /** 74 | **************************************************************************************** 75 | */ 76 | void aicwf_sdio_host_tx_cfm_handler(struct sdio_host_env_tag *env, u32 *data) 77 | { 78 | u32 queue_idx = 0;// data[0]; 79 | //struct rwnx_hw *rwnx_hw = (struct rwnx_hw *)env->pthis; 80 | struct sk_buff *skb = NULL; 81 | struct rwnx_txhdr *txhdr; 82 | 83 | // TX confirmation descriptors have been received 84 | // REG_SW_SET_PROFILING(env->pthis, SW_PROF_IRQ_E2A_TXCFM); 85 | //while (1) 86 | { 87 | // Get the used index and increase it. We do the increase before knowing if the 88 | // current buffer is confirmed because the callback function may call the 89 | // ipc_host_txdesc_get() in case flow control was enabled and the index has to be 90 | // already at the good value to ensure that the test of FIFO full is correct 91 | //uint32_t used_idx = env->txdesc_used_idx[queue_idx]++; 92 | uint32_t used_idx = data[1]; 93 | uint32_t host_id = env->tx_host_id[queue_idx][used_idx % SDIO_TXDESC_CNT]; 94 | 95 | // Reset the host id in the array 96 | env->tx_host_id[queue_idx][used_idx % SDIO_TXDESC_CNT] = 0; 97 | 98 | // call the external function to indicate that a TX packet is freed 99 | if (host_id == 0) 100 | { 101 | // No more confirmations, so put back the used index at its initial value 102 | env->txdesc_used_idx[queue_idx] = used_idx; 103 | printk("ERROR:No more confirmations\r\n"); 104 | //break; 105 | } 106 | // set the cfm status 107 | skb = (struct sk_buff *)(uint32_t)host_id; 108 | txhdr = (struct rwnx_txhdr *)skb->data; 109 | txhdr->hw_hdr.cfm.status = (union rwnx_hw_txstatus)data[0]; 110 | printk("sdio_host_tx_cfm_handler:used_idx=%d, 0x%p, status=%x\r\n",used_idx, env->pthis, txhdr->hw_hdr.cfm.status.value); 111 | //if (env->cb.send_data_cfm(env->pthis, host_id) != 0) 112 | if (rwnx_txdatacfm(env->pthis, (void *)host_id) != 0) 113 | { 114 | // No more confirmations, so put back the used index at its initial value 115 | env->txdesc_used_idx[queue_idx] = used_idx; 116 | env->tx_host_id[queue_idx][used_idx % SDIO_TXDESC_CNT] = host_id; 117 | // and exit the loop 118 | printk("ERROR:rwnx_txdatacfm,\r\n"); 119 | // break; 120 | } 121 | 122 | } 123 | } 124 | 125 | int aicwf_rwnx_sdio_platform_init(struct aic_sdio_dev *sdiodev) 126 | { 127 | struct rwnx_plat *rwnx_plat = NULL; 128 | void *drvdata; 129 | int ret = -ENODEV; 130 | 131 | rwnx_plat = kzalloc(sizeof(struct rwnx_plat), GFP_KERNEL); 132 | 133 | if (!rwnx_plat) { 134 | return -ENOMEM; 135 | } 136 | 137 | rwnx_plat->sdiodev = sdiodev; 138 | ret = rwnx_platform_init(rwnx_plat, &drvdata); 139 | 140 | return ret; 141 | } 142 | 143 | -------------------------------------------------------------------------------- /aic8800_fdrv/aicwf_usb.h: -------------------------------------------------------------------------------- 1 | /** 2 | * aicwf_usb.h 3 | * 4 | * USB function declarations 5 | * 6 | * Copyright (C) AICSemi 2018-2020 7 | */ 8 | 9 | #ifndef _AICWF_USB_H_ 10 | #define _AICWF_USB_H_ 11 | 12 | #include 13 | #include "rwnx_cmds.h" 14 | 15 | #ifdef AICWF_USB_SUPPORT 16 | 17 | /* USB Device ID */ 18 | #define USB_VENDOR_ID_AIC 0xA69C 19 | #define USB_VENDOR_ID_AIC_V2 0x368B 20 | 21 | #ifndef CONFIG_USB_BT 22 | #define USB_PRODUCT_ID_AIC8800 0x8800 23 | #define USB_PRODUCT_ID_AIC8801 0x8801 24 | #define USB_PRODUCT_ID_AIC8800DC 0x88dc 25 | #define USB_PRODUCT_ID_AIC8800DW 0x88dd 26 | #define USB_PRODUCT_ID_AIC8800D81 0x8d81 27 | #define USB_PRODUCT_ID_AIC8800D81X2 0x8d91 28 | #define USB_PRODUCT_ID_AIC8800D89X2 0x8d99 29 | #else 30 | #define USB_PRODUCT_ID_AIC8801 0x8801 31 | #define USB_PRODUCT_ID_AIC8800DC 0x88dc 32 | #define USB_PRODUCT_ID_AIC8800DW 0x88dd 33 | #define USB_PRODUCT_ID_AIC8800D81 0x8d81 34 | #define USB_PRODUCT_ID_AIC8800D41 0x8d41 35 | #define USB_PRODUCT_ID_AIC8800D81X2 0x8d91 36 | #define USB_PRODUCT_ID_AIC8800D89X2 0x8d99 37 | #endif 38 | 39 | enum AICWF_IC{ 40 | PRODUCT_ID_AIC8801 = 0, 41 | PRODUCT_ID_AIC8800DC, 42 | PRODUCT_ID_AIC8800DW, 43 | PRODUCT_ID_AIC8800D81, 44 | PRODUCT_ID_AIC8800D81X2, 45 | PRODUCT_ID_AIC8800D89X2 46 | }; 47 | 48 | 49 | #define AICWF_USB_RX_URBS (20)//(200) 50 | #ifdef CONFIG_USB_MSG_IN_EP 51 | #define AICWF_USB_MSG_RX_URBS (100) 52 | #endif 53 | #ifdef CONFIG_USB_TX_AGGR 54 | #define TXQLEN (2048*4) 55 | #define AICWF_USB_TX_URBS (50) 56 | #else 57 | #define AICWF_USB_TX_URBS 200//(100) 58 | #endif 59 | #define AICWF_USB_TX_LOW_WATER (AICWF_USB_TX_URBS/4)//25% 60 | #define AICWF_USB_TX_HIGH_WATER (AICWF_USB_TX_LOW_WATER*3)//75% 61 | #ifdef CONFIG_PLATFORM_HI 62 | #define AICWF_USB_AGGR_MAX_PKT_SIZE (2048*1) 63 | #else 64 | #define AICWF_USB_AGGR_MAX_PKT_SIZE (2048*10) 65 | #endif 66 | #define AICWF_USB_MSG_MAX_PKT_SIZE (2048) 67 | #define AICWF_USB_MAX_PKT_SIZE (2048) 68 | #define AICWF_USB_FC_PERSTA_HIGH_WATER 64 69 | #define AICWF_USB_FC_PERSTA_LOW_WATER 16 70 | 71 | 72 | typedef enum { 73 | USB_TYPE_DATA = 0X00, 74 | USB_TYPE_CFG = 0X10, 75 | USB_TYPE_CFG_CMD_RSP = 0X11, 76 | USB_TYPE_CFG_DATA_CFM = 0X12, 77 | USB_TYPE_CFG_PRINT = 0X13 78 | } usb_type; 79 | 80 | enum aicwf_usb_state { 81 | USB_DOWN_ST, 82 | USB_UP_ST, 83 | USB_SLEEP_ST 84 | }; 85 | 86 | struct aicwf_usb_buf { 87 | struct list_head list; 88 | struct aic_usb_dev *usbdev; 89 | struct urb *urb; 90 | struct sk_buff *skb; 91 | #ifdef CONFIG_PREALLOC_RX_SKB 92 | struct rx_buff *rx_buff; 93 | #endif 94 | #ifdef CONFIG_USB_NO_TRANS_DMA_MAP 95 | u8 *data_buf; 96 | dma_addr_t data_dma_trans_addr; 97 | #endif 98 | bool cfm; 99 | #ifdef CONFIG_USB_TX_AGGR 100 | u8 aggr_cnt; 101 | #endif 102 | u8* usb_align_data; 103 | }; 104 | 105 | struct aic_usb_dev { 106 | struct rwnx_hw *rwnx_hw; 107 | struct aicwf_bus *bus_if; 108 | struct usb_device *udev; 109 | struct device *dev; 110 | struct aicwf_rx_priv* rx_priv; 111 | enum aicwf_usb_state state; 112 | struct rwnx_cmd_mgr cmd_mgr; 113 | 114 | #ifdef CONFIG_USB_TX_AGGR 115 | struct aicwf_tx_priv *tx_priv; 116 | #endif 117 | 118 | struct usb_anchor rx_submitted; 119 | struct work_struct rx_urb_work; 120 | #ifdef CONFIG_USB_MSG_IN_EP 121 | struct usb_anchor msg_rx_submitted; 122 | struct work_struct msg_rx_urb_work; 123 | #endif 124 | 125 | spinlock_t rx_free_lock; 126 | spinlock_t tx_free_lock; 127 | spinlock_t tx_post_lock; 128 | spinlock_t tx_flow_lock; 129 | #ifdef CONFIG_USB_MSG_IN_EP 130 | spinlock_t msg_rx_free_lock; 131 | #endif 132 | 133 | struct list_head rx_free_list; 134 | struct list_head tx_free_list; 135 | struct list_head tx_post_list; 136 | #ifdef CONFIG_USB_MSG_IN_EP 137 | struct list_head msg_rx_free_list; 138 | #endif 139 | 140 | uint bulk_in_pipe; 141 | uint bulk_out_pipe; 142 | #ifdef CONFIG_USB_MSG_OUT_EP 143 | uint msg_out_pipe; 144 | #endif 145 | #ifdef CONFIG_USB_MSG_IN_EP 146 | uint msg_in_pipe; 147 | #endif 148 | 149 | int tx_free_count; 150 | int tx_post_count; 151 | bool rx_prepare_ready; 152 | #if 0 153 | struct aicwf_usb_buf usb_tx_buf[AICWF_USB_TX_URBS]; 154 | struct aicwf_usb_buf usb_rx_buf[AICWF_USB_RX_URBS]; 155 | #else 156 | struct aicwf_usb_buf *usb_tx_buf; 157 | struct aicwf_usb_buf *usb_rx_buf; 158 | #endif 159 | 160 | #ifdef CONFIG_USB_MSG_IN_EP 161 | struct aicwf_usb_buf usb_msg_rx_buf[AICWF_USB_MSG_RX_URBS]; 162 | #endif 163 | 164 | int msg_finished; 165 | wait_queue_head_t msg_wait; 166 | ulong msg_busy; 167 | struct urb *msg_out_urb; 168 | #ifdef CONFIG_USB_NO_TRANS_DMA_MAP 169 | dma_addr_t cmd_dma_trans_addr; 170 | #endif 171 | 172 | #ifdef CONFIG_RX_TASKLET//AIDEN tasklet 173 | struct tasklet_struct recv_tasklet; 174 | #endif 175 | #ifdef CONFIG_TX_TASKLET//AIDEN tasklet 176 | struct tasklet_struct xmit_tasklet; 177 | #endif 178 | u16 chipid; 179 | bool tbusy; 180 | }; 181 | 182 | extern void aicwf_usb_exit(void); 183 | extern void aicwf_usb_register(void); 184 | extern void aicwf_usb_tx_flowctrl(struct rwnx_hw *rwnx_hw, bool state); 185 | #ifdef CONFIG_USB_MSG_IN_EP 186 | int usb_msg_busrx_thread(void *data); 187 | #endif 188 | int usb_bustx_thread(void *data); 189 | int usb_busrx_thread(void *data); 190 | 191 | 192 | extern void aicwf_hostif_ready(void); 193 | 194 | #endif /* AICWF_USB_SUPPORT */ 195 | #endif /* _AICWF_USB_H_ */ 196 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_radar.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_radar.h 5 | * 6 | * @brief Functions to handle radar detection 7 | * 8 | * 9 | * Copyright (C) RivieraWaves 2012-2019 10 | * 11 | ****************************************************************************** 12 | */ 13 | #ifndef _RWNX_RADAR_H_ 14 | #define _RWNX_RADAR_H_ 15 | 16 | #include 17 | 18 | struct rwnx_vif; 19 | struct rwnx_hw; 20 | 21 | enum rwnx_radar_chain { 22 | RWNX_RADAR_RIU = 0, 23 | RWNX_RADAR_FCU, 24 | RWNX_RADAR_LAST 25 | }; 26 | 27 | enum rwnx_radar_detector { 28 | RWNX_RADAR_DETECT_DISABLE = 0, /* Ignore radar pulses */ 29 | RWNX_RADAR_DETECT_ENABLE = 1, /* Process pattern detection but do not 30 | report radar to upper layer (for test) */ 31 | RWNX_RADAR_DETECT_REPORT = 2 /* Process pattern detection and report 32 | radar to upper layer. */ 33 | }; 34 | 35 | #ifdef CONFIG_RWNX_RADAR 36 | #include 37 | #include 38 | 39 | #define RWNX_RADAR_PULSE_MAX 32 40 | 41 | /** 42 | * struct rwnx_radar_pulses - List of pulses reported by HW 43 | * @index: write index 44 | * @count: number of valid pulses 45 | * @buffer: buffer of pulses 46 | */ 47 | struct rwnx_radar_pulses { 48 | /* Last radar pulses received */ 49 | int index; 50 | int count; 51 | u32 buffer[RWNX_RADAR_PULSE_MAX]; 52 | }; 53 | 54 | /** 55 | * struct dfs_pattern_detector - DFS pattern detector 56 | * @region: active DFS region, NL80211_DFS_UNSET until set 57 | * @num_radar_types: number of different radar types 58 | * @last_pulse_ts: time stamp of last valid pulse in usecs 59 | * @prev_jiffies: 60 | * @radar_detector_specs: array of radar detection specs 61 | * @channel_detectors: list connecting channel_detector elements 62 | */ 63 | struct dfs_pattern_detector { 64 | u8 enabled; 65 | enum nl80211_dfs_regions region; 66 | u8 num_radar_types; 67 | u64 last_pulse_ts; 68 | u32 prev_jiffies; 69 | const struct radar_detector_specs *radar_spec; 70 | struct list_head detectors[]; 71 | }; 72 | 73 | #define NX_NB_RADAR_DETECTED 4 74 | 75 | /** 76 | * struct rwnx_radar_detected - List of radar detected 77 | */ 78 | struct rwnx_radar_detected { 79 | u16 index; 80 | u16 count; 81 | s64 time[NX_NB_RADAR_DETECTED]; 82 | s16 freq[NX_NB_RADAR_DETECTED]; 83 | }; 84 | 85 | 86 | struct rwnx_radar { 87 | struct rwnx_radar_pulses pulses[RWNX_RADAR_LAST]; 88 | struct dfs_pattern_detector *dpd[RWNX_RADAR_LAST]; 89 | struct rwnx_radar_detected detected[RWNX_RADAR_LAST]; 90 | struct work_struct detection_work; /* Work used to process radar pulses */ 91 | spinlock_t lock; /* lock for pulses processing */ 92 | 93 | /* In softmac cac is handled by mac80211 */ 94 | #ifdef CONFIG_RWNX_FULLMAC 95 | struct delayed_work cac_work; /* Work used to handle CAC */ 96 | struct rwnx_vif *cac_vif; /* vif on which we started CAC */ 97 | #endif 98 | }; 99 | 100 | bool rwnx_radar_detection_init(struct rwnx_radar *radar); 101 | void rwnx_radar_detection_deinit(struct rwnx_radar *radar); 102 | bool rwnx_radar_set_domain(struct rwnx_radar *radar, 103 | enum nl80211_dfs_regions region); 104 | void rwnx_radar_detection_enable(struct rwnx_radar *radar, u8 enable, u8 chain); 105 | bool rwnx_radar_detection_is_enable(struct rwnx_radar *radar, u8 chain); 106 | void rwnx_radar_start_cac(struct rwnx_radar *radar, u32 cac_time_ms, 107 | struct rwnx_vif *vif); 108 | void rwnx_radar_cancel_cac(struct rwnx_radar *radar); 109 | void rwnx_radar_detection_enable_on_cur_channel(struct rwnx_hw *rwnx_hw); 110 | int rwnx_radar_dump_pattern_detector(char *buf, size_t len, 111 | struct rwnx_radar *radar, u8 chain); 112 | int rwnx_radar_dump_radar_detected(char *buf, size_t len, 113 | struct rwnx_radar *radar, u8 chain); 114 | 115 | #else 116 | 117 | struct rwnx_radar { 118 | }; 119 | 120 | static inline bool rwnx_radar_detection_init(struct rwnx_radar *radar) 121 | {return true;} 122 | 123 | static inline void rwnx_radar_detection_deinit(struct rwnx_radar *radar) 124 | {} 125 | 126 | static inline bool rwnx_radar_set_domain(struct rwnx_radar *radar, 127 | enum nl80211_dfs_regions region) 128 | {return true;} 129 | 130 | static inline void rwnx_radar_detection_enable(struct rwnx_radar *radar, 131 | u8 enable, u8 chain) 132 | {} 133 | 134 | static inline bool rwnx_radar_detection_is_enable(struct rwnx_radar *radar, 135 | u8 chain) 136 | {return false;} 137 | 138 | static inline void rwnx_radar_start_cac(struct rwnx_radar *radar, 139 | u32 cac_time_ms, struct rwnx_vif *vif) 140 | {} 141 | 142 | static inline void rwnx_radar_cancel_cac(struct rwnx_radar *radar) 143 | {} 144 | 145 | static inline void rwnx_radar_detection_enable_on_cur_channel(struct rwnx_hw *rwnx_hw) 146 | {} 147 | 148 | static inline int rwnx_radar_dump_pattern_detector(char *buf, size_t len, 149 | struct rwnx_radar *radar, 150 | u8 chain) 151 | {return 0;} 152 | 153 | static inline int rwnx_radar_dump_radar_detected(char *buf, size_t len, 154 | struct rwnx_radar *radar, 155 | u8 chain) 156 | {return 0;} 157 | 158 | #endif /* CONFIG_RWNX_RADAR */ 159 | 160 | #endif // _RWNX_RADAR_H_ 161 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_platform.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_platorm.h 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | 11 | #ifndef _RWNX_PLATFORM_H_ 12 | #define _RWNX_PLATFORM_H_ 13 | 14 | #include 15 | #include "lmac_msg.h" 16 | 17 | 18 | #define RWNX_CONFIG_FW_NAME "rwnx_settings.ini" 19 | #define RWNX_PHY_CONFIG_TRD_NAME "rwnx_trident.ini" 20 | #define RWNX_PHY_CONFIG_KARST_NAME "rwnx_karst.ini" 21 | #define RWNX_AGC_FW_NAME "agcram.bin" 22 | #define RWNX_LDPC_RAM_NAME "ldpcram.bin" 23 | #ifdef CONFIG_RWNX_FULLMAC 24 | #define RWNX_MAC_FW_BASE_NAME "fmacfw" 25 | #elif defined CONFIG_RWNX_FHOST 26 | #define RWNX_MAC_FW_BASE_NAME "fhostfw" 27 | #endif /* CONFIG_RWNX_FULLMAC */ 28 | 29 | #ifdef CONFIG_RWNX_TL4 30 | #define RWNX_MAC_FW_NAME RWNX_MAC_FW_BASE_NAME".hex" 31 | #else 32 | #define RWNX_MAC_FW_NAME RWNX_MAC_FW_BASE_NAME".ihex" 33 | #define RWNX_MAC_FW_NAME2 RWNX_MAC_FW_BASE_NAME".bin" 34 | #endif 35 | 36 | #define RWNX_FCU_FW_NAME "fcuram.bin" 37 | #if (defined(CONFIG_DPD) && !defined(CONFIG_FORCE_DPD_CALIB)) 38 | #define FW_DPDRESULT_NAME_8800DC "aic_dpdresult_lite_8800dc.bin" 39 | #endif 40 | 41 | #define POWER_LEVEL_INVALID_VAL (127) 42 | 43 | enum { 44 | FW_NORMAL_MODE = 0, 45 | FW_RFTEST_MODE = 1, 46 | FW_BLE_SCAN_WAKEUP_MODE = 2, 47 | FW_M2D_OTA_MODE = 3, 48 | FW_DPDCALIB_MODE = 4, 49 | FW_BLE_SCAN_AD_FILTER_MODE = 5, 50 | }; 51 | 52 | 53 | /** 54 | * Type of memory to access (cf rwnx_plat.get_address) 55 | * 56 | * @RWNX_ADDR_CPU To access memory of the embedded CPU 57 | * @RWNX_ADDR_SYSTEM To access memory/registers of one subsystem of the 58 | * embedded system 59 | * 60 | */ 61 | enum rwnx_platform_addr { 62 | RWNX_ADDR_CPU, 63 | RWNX_ADDR_SYSTEM, 64 | RWNX_ADDR_MAX, 65 | }; 66 | 67 | struct rwnx_hw; 68 | 69 | /** 70 | * struct rwnx_plat - Operation pointers for RWNX PCI platform 71 | * 72 | * @pci_dev: pointer to pci dev 73 | * @enabled: Set if embedded platform has been enabled (i.e. fw loaded and 74 | * ipc started) 75 | * @enable: Configure communication with the fw (i.e. configure the transfers 76 | * enable and register interrupt) 77 | * @disable: Stop communication with the fw 78 | * @deinit: Free all ressources allocated for the embedded platform 79 | * @get_address: Return the virtual address to access the requested address on 80 | * the platform. 81 | * @ack_irq: Acknowledge the irq at link level. 82 | * @get_config_reg: Return the list (size + pointer) of registers to restore in 83 | * order to reload the platform while keeping the current configuration. 84 | * 85 | * @priv Private data for the link driver 86 | */ 87 | struct rwnx_plat { 88 | struct pci_dev *pci_dev; 89 | 90 | #ifdef AICWF_SDIO_SUPPORT 91 | struct aic_sdio_dev *sdiodev; 92 | #endif 93 | 94 | #ifdef AICWF_USB_SUPPORT 95 | struct aic_usb_dev *usbdev; 96 | #endif 97 | bool enabled; 98 | bool wait_disconnect_cb; 99 | 100 | int (*enable)(struct rwnx_hw *rwnx_hw); 101 | int (*disable)(struct rwnx_hw *rwnx_hw); 102 | void (*deinit)(struct rwnx_plat *rwnx_plat); 103 | u8* (*get_address)(struct rwnx_plat *rwnx_plat, int addr_name, 104 | unsigned int offset); 105 | void (*ack_irq)(struct rwnx_plat *rwnx_plat); 106 | int (*get_config_reg)(struct rwnx_plat *rwnx_plat, const u32 **list); 107 | 108 | u8 priv[0] __aligned(sizeof(void *)); 109 | }; 110 | 111 | #define RWNX_ADDR(plat, base, offset) \ 112 | plat->get_address(plat, base, offset) 113 | 114 | #define RWNX_REG_READ(plat, base, offset) \ 115 | readl(plat->get_address(plat, base, offset)) 116 | 117 | #define RWNX_REG_WRITE(val, plat, base, offset) \ 118 | writel(val, plat->get_address(plat, base, offset)) 119 | 120 | extern struct rwnx_plat *g_rwnx_plat; 121 | 122 | int rwnx_platform_init(struct rwnx_plat *rwnx_plat, void **platform_data); 123 | void rwnx_platform_deinit(struct rwnx_hw *rwnx_hw); 124 | 125 | int rwnx_platform_on(struct rwnx_hw *rwnx_hw, void *config); 126 | void rwnx_platform_off(struct rwnx_hw *rwnx_hw, void **config); 127 | 128 | int is_file_exist(char* name); 129 | void get_userconfig_txpwr_lvl_in_fdrv(txpwr_lvl_conf_t *txpwr_lvl); 130 | void get_userconfig_txpwr_lvl_v2_in_fdrv(txpwr_lvl_conf_v2_t *txpwr_lvl_v2); 131 | void get_userconfig_txpwr_lvl_v3_in_fdrv(txpwr_lvl_conf_v3_t *txpwr_lvl_v3); 132 | void get_userconfig_txpwr_lvl_v4_in_fdrv(txpwr_lvl_conf_v4_t *txpwr_lvl_v4); 133 | void get_userconfig_txpwr_lvl_adj_in_fdrv(txpwr_lvl_adj_conf_t *txpwr_lvl_adj); 134 | void get_userconfig_txpwr_ofst_in_fdrv(txpwr_ofst_conf_t *txpwr_ofst); 135 | void get_userconfig_txpwr_ofst2x_in_fdrv(txpwr_ofst2x_conf_t *txpwr_ofst2x); 136 | void get_userconfig_txpwr_ofst2x_v2_in_fdrv(txpwr_ofst2x_conf_v2_t *txpwr_ofst2x_v2); 137 | void get_userconfig_txpwr_loss(txpwr_loss_conf_t *txpwr_loss); 138 | void rwnx_plat_userconfig_parsing(char *buffer, int size); 139 | #ifdef CONFIG_POWER_LIMIT 140 | void rwnx_plat_powerlimit_parsing(char *buffer, int size, char *cc); 141 | int8_t get_powerlimit_by_freq(uint8_t band, uint16_t freq); 142 | int8_t get_powerlimit_by_chnum(uint8_t chnum); 143 | #endif 144 | int rwnx_platform_register_drv(void); 145 | void rwnx_platform_unregister_drv(void); 146 | 147 | extern struct device *rwnx_platform_get_dev(struct rwnx_plat *rwnx_plat); 148 | 149 | static inline unsigned int rwnx_platform_get_irq(struct rwnx_plat *rwnx_plat) 150 | { 151 | return rwnx_plat->pci_dev->irq; 152 | } 153 | 154 | #endif /* _RWNX_PLATFORM_H_ */ 155 | -------------------------------------------------------------------------------- /aic8800_fdrv/usb_host.c: -------------------------------------------------------------------------------- 1 | /** 2 | * usb_host.c 3 | * 4 | * USB host function declarations 5 | * 6 | * Copyright (C) AICSemi 2018-2020 7 | */ 8 | 9 | 10 | #include "usb_host.h" 11 | //#include "ipc_compat.h" 12 | #include "rwnx_tx.h" 13 | #include "rwnx_platform.h" 14 | #include "aicwf_debug.h" 15 | 16 | /** 17 | **************************************************************************************** 18 | */ 19 | void aicwf_usb_host_init(struct usb_host_env_tag *env, 20 | void *cb, 21 | void *shared_env_ptr, 22 | void *pthis) 23 | { 24 | // Reset the environments 25 | 26 | // Reset the Host environment 27 | memset(env, 0, sizeof(struct usb_host_env_tag)); 28 | // Save the pointer to the register base 29 | env->pthis = pthis; 30 | } 31 | 32 | /** 33 | **************************************************************************************** 34 | */ 35 | volatile struct txdesc_host *aicwf_usb_host_txdesc_get(struct usb_host_env_tag *env, const int queue_idx) 36 | { 37 | // struct ipc_shared_env_tag *shared_env_ptr = env->shared; 38 | volatile struct txdesc_host *txdesc_free = NULL; 39 | uint32_t used_idx = env->txdesc_used_idx[queue_idx]; 40 | uint32_t free_idx = env->txdesc_free_idx[queue_idx]; 41 | 42 | // ASSERT_ERR(queue_idx < SDIO_TXQUEUE_CNT); 43 | // ASSERT_ERR((free_idx - used_idx) <= USB_TXDESC_CNT); 44 | 45 | // Check if a free descriptor is available 46 | if (free_idx != (used_idx + USB_TXDESC_CNT)) 47 | { 48 | // Get the pointer to the first free descriptor 49 | // txdesc_free = shared_env_ptr->txdesc[queue_idx] + (free_idx % IPC_TXDESC_CNT); 50 | } 51 | else 52 | { 53 | //txdesc_free = NULL; 54 | } 55 | 56 | return txdesc_free; 57 | } 58 | 59 | /** 60 | **************************************************************************************** 61 | */ 62 | void aicwf_usb_host_txdesc_push(struct usb_host_env_tag *env, const int queue_idx, const uint64_t host_id) 63 | { 64 | //printk("push, %d, %d, 0x%llx \r\n", queue_idx, env->txdesc_free_idx[queue_idx], host_id); 65 | // Save the host id in the environment 66 | env->tx_host_id[queue_idx][env->txdesc_free_idx[queue_idx] % USB_TXDESC_CNT] = host_id; 67 | 68 | // Increment the index 69 | env->txdesc_free_idx[queue_idx]++; 70 | if(env->txdesc_free_idx[queue_idx]==0x40000000) 71 | env->txdesc_free_idx[queue_idx] = 0; 72 | } 73 | 74 | /** 75 | **************************************************************************************** 76 | */ 77 | void aicwf_usb_host_tx_cfm_handler(struct usb_host_env_tag *env, u32 *data) 78 | { 79 | u32 queue_idx = 0;//data[0]; 80 | //struct rwnx_hw *rwnx_hw = (struct rwnx_hw *)env->pthis; 81 | struct sk_buff *skb = NULL; 82 | struct rwnx_txhdr *txhdr; 83 | AICWFDBG(LOGTRACE, "%s Enter \n", __func__); 84 | //printk("sdio_host_tx_cfm_handler, %d, 0x%08x\r\n", queue_idx, data[1]); 85 | // TX confirmation descriptors have been received 86 | // REG_SW_SET_PROFILING(env->pthis, SW_PROF_IRQ_E2A_TXCFM); 87 | //while (1) 88 | { 89 | // Get the used index and increase it. We do the increase before knowing if the 90 | // current buffer is confirmed because the callback function may call the 91 | // ipc_host_txdesc_get() in case flow control was enabled and the index has to be 92 | // already at the good value to ensure that the test of FIFO full is correct 93 | //uint32_t used_idx = env->txdesc_used_idx[queue_idx]++; 94 | uint32_t used_idx = data[1]; 95 | //uint64_t host_id = env->tx_host_id[queue_idx][used_idx % USB_TXDESC_CNT]; 96 | unsigned long host_id = env->tx_host_id[queue_idx][used_idx % USB_TXDESC_CNT]; 97 | 98 | // Reset the host id in the array 99 | env->tx_host_id[queue_idx][used_idx % USB_TXDESC_CNT] = 0; 100 | 101 | // call the external function to indicate that a TX packet is freed 102 | if (host_id == 0) 103 | { 104 | // No more confirmations, so put back the used index at its initial value 105 | env->txdesc_used_idx[queue_idx] = used_idx; 106 | AICWFDBG(LOGERROR, "ERROR:No more confirmations\r\n"); 107 | return; 108 | //break; 109 | } 110 | AICWFDBG(LOGINFO, "usb_host_tx_cfm_handler:used_idx=%d, hostid=%p, 0x%p, status=%x\r\n",used_idx, (void *)host_id, env->pthis, data[0]); 111 | 112 | // set the cfm status 113 | skb = (struct sk_buff *)host_id; 114 | txhdr = (struct rwnx_txhdr *)skb->data; 115 | txhdr->hw_hdr.cfm.status = (union rwnx_hw_txstatus)data[0]; 116 | //txhdr->hw_hdr.status = data[1]; 117 | //if (env->cb.send_data_cfm(env->pthis, host_id) != 0) 118 | if (rwnx_txdatacfm(env->pthis, (void *)host_id) != 0) 119 | { 120 | // No more confirmations, so put back the used index at its initial value 121 | env->txdesc_used_idx[queue_idx] = used_idx; 122 | env->tx_host_id[queue_idx][used_idx % USB_TXDESC_CNT] = host_id; 123 | // and exit the loop 124 | AICWFDBG(LOGERROR, "ERROR:rwnx_txdatacfm,\r\n"); 125 | // break; 126 | } 127 | 128 | } 129 | } 130 | 131 | int aicwf_rwnx_usb_platform_init(struct aic_usb_dev *usbdev) 132 | { 133 | struct rwnx_plat *rwnx_plat = NULL; 134 | void *drvdata; 135 | int ret = -ENODEV; 136 | 137 | rwnx_plat = kzalloc(sizeof(struct rwnx_plat), GFP_KERNEL); 138 | 139 | if (!rwnx_plat) 140 | return -ENOMEM; 141 | 142 | // rwnx_plat->pci_dev = pci_dev; 143 | rwnx_plat->usbdev = usbdev; 144 | 145 | ret = rwnx_platform_init(rwnx_plat, &drvdata); 146 | #if 0 147 | pci_set_drvdata(pci_dev, drvdata); 148 | 149 | if (ret) 150 | rwnx_plat->deinit(rwnx_plat); 151 | #endif 152 | return ret; 153 | } 154 | 155 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_v7.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_v7.c - Support for v7 platform 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | 11 | #include "rwnx_v7.h" 12 | #include "rwnx_defs.h" 13 | #include "rwnx_irqs.h" 14 | #include "reg_access.h" 15 | #include "hal_desc.h" 16 | 17 | struct rwnx_v7 18 | { 19 | u8 *pci_bar0_vaddr; 20 | u8 *pci_bar1_vaddr; 21 | }; 22 | 23 | static int rwnx_v7_platform_enable(struct rwnx_hw *rwnx_hw) 24 | { 25 | int ret; 26 | 27 | /* sched_setscheduler on ONESHOT threaded irq handler for BCNs ? */ 28 | ret = request_irq(rwnx_hw->plat->pci_dev->irq, rwnx_irq_hdlr, 0, 29 | "rwnx", rwnx_hw); 30 | return ret; 31 | } 32 | 33 | static int rwnx_v7_platform_disable(struct rwnx_hw *rwnx_hw) 34 | { 35 | free_irq(rwnx_hw->plat->pci_dev->irq, rwnx_hw); 36 | return 0; 37 | } 38 | 39 | static void rwnx_v7_platform_deinit(struct rwnx_plat *rwnx_plat) 40 | { 41 | #ifdef CONFIG_PCI 42 | struct rwnx_v7 *rwnx_v7 = (struct rwnx_v7 *)rwnx_plat->priv; 43 | 44 | pci_disable_device(rwnx_plat->pci_dev); 45 | iounmap(rwnx_v7->pci_bar0_vaddr); 46 | iounmap(rwnx_v7->pci_bar1_vaddr); 47 | pci_release_regions(rwnx_plat->pci_dev); 48 | pci_clear_master(rwnx_plat->pci_dev); 49 | pci_disable_msi(rwnx_plat->pci_dev); 50 | #endif 51 | kfree(rwnx_plat); 52 | } 53 | 54 | static u8* rwnx_v7_get_address(struct rwnx_plat *rwnx_plat, int addr_name, 55 | unsigned int offset) 56 | { 57 | struct rwnx_v7 *rwnx_v7 = (struct rwnx_v7 *)rwnx_plat->priv; 58 | 59 | if (WARN(addr_name >= RWNX_ADDR_MAX, "Invalid address %d", addr_name)) 60 | return NULL; 61 | 62 | if (addr_name == RWNX_ADDR_CPU) 63 | return rwnx_v7->pci_bar0_vaddr + offset; 64 | else 65 | return rwnx_v7->pci_bar1_vaddr + offset; 66 | } 67 | 68 | static void rwnx_v7_ack_irq(struct rwnx_plat *rwnx_plat) 69 | { 70 | 71 | } 72 | 73 | static const u32 rwnx_v7_config_reg[] = { 74 | NXMAC_DEBUG_PORT_SEL_ADDR, 75 | SYSCTRL_DIAG_CONF_ADDR, 76 | SYSCTRL_PHYDIAG_CONF_ADDR, 77 | SYSCTRL_RIUDIAG_CONF_ADDR, 78 | RF_V7_DIAGPORT_CONF1_ADDR, 79 | }; 80 | 81 | static const u32 rwnx_v7_he_config_reg[] = { 82 | SYSCTRL_DIAG_CONF0, 83 | SYSCTRL_DIAG_CONF1, 84 | SYSCTRL_DIAG_CONF2, 85 | SYSCTRL_DIAG_CONF3, 86 | }; 87 | 88 | static int rwnx_v7_get_config_reg(struct rwnx_plat *rwnx_plat, const u32 **list) 89 | { 90 | u32 fpga_sign; 91 | 92 | if (!list) 93 | return 0; 94 | 95 | fpga_sign = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, SYSCTRL_SIGNATURE_ADDR); 96 | if (__FPGA_TYPE(fpga_sign) == 0xc0ca) { 97 | *list = rwnx_v7_he_config_reg; 98 | return ARRAY_SIZE(rwnx_v7_he_config_reg); 99 | } else { 100 | *list = rwnx_v7_config_reg; 101 | return ARRAY_SIZE(rwnx_v7_config_reg); 102 | } 103 | } 104 | 105 | 106 | /** 107 | * rwnx_v7_platform_init - Initialize the DINI platform 108 | * 109 | * @pci_dev PCI device 110 | * @rwnx_plat Pointer on struct rwnx_stat * to be populated 111 | * 112 | * @return 0 on success, < 0 otherwise 113 | * 114 | * Allocate and initialize a rwnx_plat structure for the dini platform. 115 | */ 116 | int rwnx_v7_platform_init(struct pci_dev *pci_dev, struct rwnx_plat **rwnx_plat) 117 | { 118 | struct rwnx_v7 *rwnx_v7; 119 | u16 pci_cmd; 120 | int ret = 0; 121 | 122 | *rwnx_plat = kzalloc(sizeof(struct rwnx_plat) + sizeof(struct rwnx_v7), 123 | GFP_KERNEL); 124 | if (!*rwnx_plat) 125 | return -ENOMEM; 126 | 127 | rwnx_v7 = (struct rwnx_v7 *)(*rwnx_plat)->priv; 128 | 129 | /* Hotplug fixups */ 130 | pci_read_config_word(pci_dev, PCI_COMMAND, &pci_cmd); 131 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 132 | pci_write_config_word(pci_dev, PCI_COMMAND, pci_cmd); 133 | pci_write_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES >> 2); 134 | 135 | if ((ret = pci_enable_device(pci_dev))) { 136 | dev_err(&(pci_dev->dev), "pci_enable_device failed\n"); 137 | goto out_enable; 138 | } 139 | 140 | pci_set_master(pci_dev); 141 | 142 | if ((ret = pci_request_regions(pci_dev, KBUILD_MODNAME))) { 143 | dev_err(&(pci_dev->dev), "pci_request_regions failed\n"); 144 | goto out_request; 145 | } 146 | 147 | #ifdef CONFIG_PCI 148 | if (pci_enable_msi(pci_dev)) 149 | { 150 | dev_err(&(pci_dev->dev), "pci_enable_msi failed\n"); 151 | goto out_msi; 152 | 153 | } 154 | #endif 155 | 156 | if (!(rwnx_v7->pci_bar0_vaddr = (u8 *)pci_ioremap_bar(pci_dev, 0))) { 157 | dev_err(&(pci_dev->dev), "pci_ioremap_bar(%d) failed\n", 0); 158 | ret = -ENOMEM; 159 | goto out_bar0; 160 | } 161 | if (!(rwnx_v7->pci_bar1_vaddr = (u8 *)pci_ioremap_bar(pci_dev, 1))) { 162 | dev_err(&(pci_dev->dev), "pci_ioremap_bar(%d) failed\n", 1); 163 | ret = -ENOMEM; 164 | goto out_bar1; 165 | } 166 | 167 | (*rwnx_plat)->enable = rwnx_v7_platform_enable; 168 | (*rwnx_plat)->disable = rwnx_v7_platform_disable; 169 | (*rwnx_plat)->deinit = rwnx_v7_platform_deinit; 170 | (*rwnx_plat)->get_address = rwnx_v7_get_address; 171 | (*rwnx_plat)->ack_irq = rwnx_v7_ack_irq; 172 | (*rwnx_plat)->get_config_reg = rwnx_v7_get_config_reg; 173 | 174 | return 0; 175 | 176 | out_bar1: 177 | iounmap(rwnx_v7->pci_bar0_vaddr); 178 | out_bar0: 179 | #ifdef CONFIG_PCI 180 | pci_disable_msi(pci_dev); 181 | out_msi: 182 | #endif 183 | pci_release_regions(pci_dev); 184 | out_request: 185 | #ifdef CONFIG_PCI 186 | pci_clear_master(pci_dev); 187 | #endif 188 | pci_disable_device(pci_dev); 189 | out_enable: 190 | kfree(*rwnx_plat); 191 | return ret; 192 | } 193 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_mu_group.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_mu_group.h 5 | * 6 | * Copyright (C) RivieraWaves 2016-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | #ifndef _RWNX_MU_GROUP_H_ 11 | #define _RWNX_MU_GROUP_H_ 12 | 13 | #include 14 | #include 15 | 16 | struct rwnx_hw; 17 | struct rwnx_sta; 18 | 19 | #ifdef CONFIG_RWNX_MUMIMO_TX 20 | 21 | /** 22 | * struct rwnx_sta_group_info - Group Information for a STA 23 | * 24 | * @active: node for @mu->active_sta list 25 | * @update: node for @mu->update_sta list 26 | * @cnt: Number of groups the STA belongs to 27 | * @map: Bitfield of groups the sta belongs to 28 | * @traffic: Number of buffers sent since previous group selection 29 | * @group: Id of the group selected by previous group selection 30 | * (cf @rwnx_mu_group_sta_select) 31 | */ 32 | struct rwnx_sta_group_info { 33 | struct list_head active; 34 | struct list_head update; 35 | u16 last_update; 36 | int cnt; 37 | u64 map; 38 | int traffic; 39 | u8 group; 40 | }; 41 | 42 | /** 43 | * struct mu_group_info - Information about the users of a group 44 | * 45 | * @list: node for mu->active_groups 46 | * @group_id: Group identifier 47 | * @user_cnt: Number of the users in the group 48 | * @users: Pointer to the sta, ordered by user position 49 | */ 50 | struct rwnx_mu_group { 51 | struct list_head list; 52 | int group_id; 53 | int user_cnt; 54 | struct rwnx_sta *users[CONFIG_USER_MAX]; 55 | }; 56 | 57 | /** 58 | * struct rwnx_mu_info - Information about all MU group 59 | * 60 | * @active_groups: List of all possible groups. Ordered from the most recently 61 | * used one to the least one (and possibly never used) 62 | * @active_sta: List of MU beamformee sta that have been active (since previous 63 | * group update). Ordered from the most recently active. 64 | * @update_sta: List of sta whose group information has changed and need to be 65 | * updated at fw level 66 | * @groups: Table of all groups 67 | * @group_work: Work item used to schedule group update 68 | * @update_count: Counter used to identify the last group formation update. 69 | * (cf rwnx_sta_group_info.last_update) 70 | * @lock: Lock taken during group update. If tx happens lock is taken, then tx 71 | * will not used MU. 72 | * @next_group_assign: Next time the group selection should be run 73 | * (ref @rwnx_mu_group_sta_select) 74 | * @group_cnt: Number of group created 75 | */ 76 | struct rwnx_mu_info { 77 | struct list_head active_groups; 78 | struct list_head active_sta; 79 | struct list_head update_sta; 80 | struct rwnx_mu_group groups[NX_MU_GROUP_MAX]; 81 | struct delayed_work group_work; 82 | u16 update_count; 83 | struct semaphore lock; 84 | unsigned long next_group_select; 85 | u8 group_cnt; 86 | }; 87 | 88 | #define RWNX_SU_GROUP BIT_ULL(0) 89 | #define RWNX_MU_GROUP_MASK 0x7ffffffffffffffeULL 90 | #define RWNX_MU_GROUP_INTERVAL 200 /* in ms */ 91 | #define RWNX_MU_GROUP_SELECT_INTERVAL 100 /* in ms */ 92 | // minimum traffic in a RWNX_MU_GROUP_SELECT_INTERVAL to consider the sta 93 | #define RWNX_MU_GROUP_MIN_TRAFFIC 50 /* in number of packet */ 94 | 95 | 96 | #define RWNX_GET_FIRST_GROUP_ID(map) (fls64(map) - 1) 97 | 98 | #define group_sta_for_each(sta, id, map) \ 99 | map = sta->group_info.map & RWNX_MU_GROUP_MASK; \ 100 | for (id = (fls64(map) - 1) ; id > 0 ; \ 101 | map &= ~(u64)BIT_ULL(id), id = (fls64(map) - 1)) 102 | 103 | #define group_for_each(id, map) \ 104 | for (id = (fls64(map) - 1) ; id > 0 ; \ 105 | map &= ~(u64)BIT_ULL(id), id = (fls64(map) - 1)) 106 | 107 | #define RWNX_MUMIMO_INFO_POS_ID(info) (((info) >> 6) & 0x3) 108 | #define RWNX_MUMIMO_INFO_GROUP_ID(info) ((info) & 0x3f) 109 | 110 | static inline 111 | struct rwnx_mu_group *rwnx_mu_group_from_id(struct rwnx_mu_info *mu, int id) 112 | { 113 | if (id > NX_MU_GROUP_MAX) 114 | return NULL; 115 | 116 | return &mu->groups[id - 1]; 117 | } 118 | 119 | 120 | void rwnx_mu_group_sta_init(struct rwnx_sta *sta, 121 | const struct ieee80211_vht_cap *vht_cap); 122 | void rwnx_mu_group_sta_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta); 123 | u64 rwnx_mu_group_sta_get_map(struct rwnx_sta *sta); 124 | int rwnx_mu_group_sta_get_pos(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta, 125 | int group_id); 126 | 127 | void rwnx_mu_group_init(struct rwnx_hw *rwnx_hw); 128 | 129 | void rwnx_mu_set_active_sta(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta, 130 | int traffic); 131 | void rwnx_mu_set_active_group(struct rwnx_hw *rwnx_hw, int group_id); 132 | void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw); 133 | 134 | 135 | #else /* ! CONFIG_RWNX_MUMIMO_TX */ 136 | 137 | static inline 138 | void rwnx_mu_group_sta_init(struct rwnx_sta *sta, 139 | const struct ieee80211_vht_cap *vht_cap) 140 | {} 141 | 142 | static inline 143 | void rwnx_mu_group_sta_del(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta) 144 | {} 145 | 146 | static inline 147 | u64 rwnx_mu_group_sta_get_map(struct rwnx_sta *sta) 148 | { 149 | return 0; 150 | } 151 | 152 | static inline 153 | int rwnx_mu_group_sta_get_pos(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta, 154 | int group_id) 155 | { 156 | return 0; 157 | } 158 | 159 | static inline 160 | void rwnx_mu_group_init(struct rwnx_hw *rwnx_hw) 161 | {} 162 | 163 | static inline 164 | void rwnx_mu_set_active_sta(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta, 165 | int traffic) 166 | {} 167 | 168 | static inline 169 | void rwnx_mu_set_active_group(struct rwnx_hw *rwnx_hw, int group_id) 170 | {} 171 | 172 | static inline 173 | void rwnx_mu_group_sta_select(struct rwnx_hw *rwnx_hw) 174 | {} 175 | 176 | #endif /* CONFIG_RWNX_MUMIMO_TX */ 177 | 178 | #endif /* _RWNX_MU_GROUP_H_ */ 179 | 180 | -------------------------------------------------------------------------------- /aic8800_fdrv/md5.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "md5.h" 3 | 4 | unsigned char PADDING[]={0x80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 5 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 6 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 7 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; 8 | 9 | void MD5Init(MD5_CTX *context) 10 | { 11 | context->count[0] = 0; 12 | context->count[1] = 0; 13 | context->state[0] = 0x67452301; 14 | context->state[1] = 0xEFCDAB89; 15 | context->state[2] = 0x98BADCFE; 16 | context->state[3] = 0x10325476; 17 | } 18 | void MD5Update(MD5_CTX *context,unsigned char *input,unsigned int inputlen) 19 | { 20 | unsigned int i = 0,index = 0,partlen = 0; 21 | index = (context->count[0] >> 3) & 0x3F; 22 | partlen = 64 - index; 23 | context->count[0] += inputlen << 3; 24 | if(context->count[0] < (inputlen << 3)) 25 | context->count[1]++; 26 | context->count[1] += inputlen >> 29; 27 | 28 | if(inputlen >= partlen) 29 | { 30 | memcpy(&context->buffer[index],input,partlen); 31 | MD5Transform(context->state,context->buffer); 32 | for(i = partlen;i+64 <= inputlen;i+=64) 33 | MD5Transform(context->state,&input[i]); 34 | index = 0; 35 | } 36 | else 37 | { 38 | i = 0; 39 | } 40 | memcpy(&context->buffer[index],&input[i],inputlen-i); 41 | } 42 | void MD5Final(MD5_CTX *context,unsigned char digest[16]) 43 | { 44 | unsigned int index = 0,padlen = 0; 45 | unsigned char bits[8]; 46 | index = (context->count[0] >> 3) & 0x3F; 47 | padlen = (index < 56)?(56-index):(120-index); 48 | MD5Encode(bits,context->count,8); 49 | MD5Update(context,PADDING,padlen); 50 | MD5Update(context,bits,8); 51 | MD5Encode(digest,context->state,16); 52 | } 53 | void MD5Encode(unsigned char *output,unsigned int *input,unsigned int len) 54 | { 55 | unsigned int i = 0,j = 0; 56 | while(j < len) 57 | { 58 | output[j] = input[i] & 0xFF; 59 | output[j+1] = (input[i] >> 8) & 0xFF; 60 | output[j+2] = (input[i] >> 16) & 0xFF; 61 | output[j+3] = (input[i] >> 24) & 0xFF; 62 | i++; 63 | j+=4; 64 | } 65 | } 66 | void MD5Decode(unsigned int *output,unsigned char *input,unsigned int len) 67 | { 68 | unsigned int i = 0,j = 0; 69 | while(j < len) 70 | { 71 | output[i] = (input[j]) | 72 | (input[j+1] << 8) | 73 | (input[j+2] << 16) | 74 | (input[j+3] << 24); 75 | i++; 76 | j+=4; 77 | } 78 | } 79 | void MD5Transform(unsigned int state[4],unsigned char block[64]) 80 | { 81 | unsigned int a = state[0]; 82 | unsigned int b = state[1]; 83 | unsigned int c = state[2]; 84 | unsigned int d = state[3]; 85 | unsigned int x[64]; 86 | MD5Decode(x,block,64); 87 | FF(a, b, c, d, x[ 0], 7, 0xd76aa478); /* 1 */ 88 | FF(d, a, b, c, x[ 1], 12, 0xe8c7b756); /* 2 */ 89 | FF(c, d, a, b, x[ 2], 17, 0x242070db); /* 3 */ 90 | FF(b, c, d, a, x[ 3], 22, 0xc1bdceee); /* 4 */ 91 | FF(a, b, c, d, x[ 4], 7, 0xf57c0faf); /* 5 */ 92 | FF(d, a, b, c, x[ 5], 12, 0x4787c62a); /* 6 */ 93 | FF(c, d, a, b, x[ 6], 17, 0xa8304613); /* 7 */ 94 | FF(b, c, d, a, x[ 7], 22, 0xfd469501); /* 8 */ 95 | FF(a, b, c, d, x[ 8], 7, 0x698098d8); /* 9 */ 96 | FF(d, a, b, c, x[ 9], 12, 0x8b44f7af); /* 10 */ 97 | FF(c, d, a, b, x[10], 17, 0xffff5bb1); /* 11 */ 98 | FF(b, c, d, a, x[11], 22, 0x895cd7be); /* 12 */ 99 | FF(a, b, c, d, x[12], 7, 0x6b901122); /* 13 */ 100 | FF(d, a, b, c, x[13], 12, 0xfd987193); /* 14 */ 101 | FF(c, d, a, b, x[14], 17, 0xa679438e); /* 15 */ 102 | FF(b, c, d, a, x[15], 22, 0x49b40821); /* 16 */ 103 | 104 | /* Round 2 */ 105 | GG(a, b, c, d, x[ 1], 5, 0xf61e2562); /* 17 */ 106 | GG(d, a, b, c, x[ 6], 9, 0xc040b340); /* 18 */ 107 | GG(c, d, a, b, x[11], 14, 0x265e5a51); /* 19 */ 108 | GG(b, c, d, a, x[ 0], 20, 0xe9b6c7aa); /* 20 */ 109 | GG(a, b, c, d, x[ 5], 5, 0xd62f105d); /* 21 */ 110 | GG(d, a, b, c, x[10], 9, 0x2441453); /* 22 */ 111 | GG(c, d, a, b, x[15], 14, 0xd8a1e681); /* 23 */ 112 | GG(b, c, d, a, x[ 4], 20, 0xe7d3fbc8); /* 24 */ 113 | GG(a, b, c, d, x[ 9], 5, 0x21e1cde6); /* 25 */ 114 | GG(d, a, b, c, x[14], 9, 0xc33707d6); /* 26 */ 115 | GG(c, d, a, b, x[ 3], 14, 0xf4d50d87); /* 27 */ 116 | GG(b, c, d, a, x[ 8], 20, 0x455a14ed); /* 28 */ 117 | GG(a, b, c, d, x[13], 5, 0xa9e3e905); /* 29 */ 118 | GG(d, a, b, c, x[ 2], 9, 0xfcefa3f8); /* 30 */ 119 | GG(c, d, a, b, x[ 7], 14, 0x676f02d9); /* 31 */ 120 | GG(b, c, d, a, x[12], 20, 0x8d2a4c8a); /* 32 */ 121 | 122 | /* Round 3 */ 123 | HH(a, b, c, d, x[ 5], 4, 0xfffa3942); /* 33 */ 124 | HH(d, a, b, c, x[ 8], 11, 0x8771f681); /* 34 */ 125 | HH(c, d, a, b, x[11], 16, 0x6d9d6122); /* 35 */ 126 | HH(b, c, d, a, x[14], 23, 0xfde5380c); /* 36 */ 127 | HH(a, b, c, d, x[ 1], 4, 0xa4beea44); /* 37 */ 128 | HH(d, a, b, c, x[ 4], 11, 0x4bdecfa9); /* 38 */ 129 | HH(c, d, a, b, x[ 7], 16, 0xf6bb4b60); /* 39 */ 130 | HH(b, c, d, a, x[10], 23, 0xbebfbc70); /* 40 */ 131 | HH(a, b, c, d, x[13], 4, 0x289b7ec6); /* 41 */ 132 | HH(d, a, b, c, x[ 0], 11, 0xeaa127fa); /* 42 */ 133 | HH(c, d, a, b, x[ 3], 16, 0xd4ef3085); /* 43 */ 134 | HH(b, c, d, a, x[ 6], 23, 0x4881d05); /* 44 */ 135 | HH(a, b, c, d, x[ 9], 4, 0xd9d4d039); /* 45 */ 136 | HH(d, a, b, c, x[12], 11, 0xe6db99e5); /* 46 */ 137 | HH(c, d, a, b, x[15], 16, 0x1fa27cf8); /* 47 */ 138 | HH(b, c, d, a, x[ 2], 23, 0xc4ac5665); /* 48 */ 139 | 140 | /* Round 4 */ 141 | II(a, b, c, d, x[ 0], 6, 0xf4292244); /* 49 */ 142 | II(d, a, b, c, x[ 7], 10, 0x432aff97); /* 50 */ 143 | II(c, d, a, b, x[14], 15, 0xab9423a7); /* 51 */ 144 | II(b, c, d, a, x[ 5], 21, 0xfc93a039); /* 52 */ 145 | II(a, b, c, d, x[12], 6, 0x655b59c3); /* 53 */ 146 | II(d, a, b, c, x[ 3], 10, 0x8f0ccc92); /* 54 */ 147 | II(c, d, a, b, x[10], 15, 0xffeff47d); /* 55 */ 148 | II(b, c, d, a, x[ 1], 21, 0x85845dd1); /* 56 */ 149 | II(a, b, c, d, x[ 8], 6, 0x6fa87e4f); /* 57 */ 150 | II(d, a, b, c, x[15], 10, 0xfe2ce6e0); /* 58 */ 151 | II(c, d, a, b, x[ 6], 15, 0xa3014314); /* 59 */ 152 | II(b, c, d, a, x[13], 21, 0x4e0811a1); /* 60 */ 153 | II(a, b, c, d, x[ 4], 6, 0xf7537e82); /* 61 */ 154 | II(d, a, b, c, x[11], 10, 0xbd3af235); /* 62 */ 155 | II(c, d, a, b, x[ 2], 15, 0x2ad7d2bb); /* 63 */ 156 | II(b, c, d, a, x[ 9], 21, 0xeb86d391); /* 64 */ 157 | state[0] += a; 158 | state[1] += b; 159 | state[2] += c; 160 | state[3] += d; 161 | } 162 | -------------------------------------------------------------------------------- /aic_load_fw/md5.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "md5.h" 3 | 4 | unsigned char PADDING[]={0x80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 5 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 6 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 7 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; 8 | 9 | void MD5Init(MD5_CTX *context) 10 | { 11 | context->count[0] = 0; 12 | context->count[1] = 0; 13 | context->state[0] = 0x67452301; 14 | context->state[1] = 0xEFCDAB89; 15 | context->state[2] = 0x98BADCFE; 16 | context->state[3] = 0x10325476; 17 | } 18 | void MD5Update(MD5_CTX *context,unsigned char *input,unsigned int inputlen) 19 | { 20 | unsigned int i = 0,index = 0,partlen = 0; 21 | index = (context->count[0] >> 3) & 0x3F; 22 | partlen = 64 - index; 23 | context->count[0] += inputlen << 3; 24 | if(context->count[0] < (inputlen << 3)) 25 | context->count[1]++; 26 | context->count[1] += inputlen >> 29; 27 | 28 | if(inputlen >= partlen) 29 | { 30 | memcpy(&context->buffer[index],input,partlen); 31 | MD5Transform(context->state,context->buffer); 32 | for(i = partlen;i+64 <= inputlen;i+=64) 33 | MD5Transform(context->state,&input[i]); 34 | index = 0; 35 | } 36 | else 37 | { 38 | i = 0; 39 | } 40 | memcpy(&context->buffer[index],&input[i],inputlen-i); 41 | } 42 | void MD5Final(MD5_CTX *context,unsigned char digest[16]) 43 | { 44 | unsigned int index = 0,padlen = 0; 45 | unsigned char bits[8]; 46 | index = (context->count[0] >> 3) & 0x3F; 47 | padlen = (index < 56)?(56-index):(120-index); 48 | MD5Encode(bits,context->count,8); 49 | MD5Update(context,PADDING,padlen); 50 | MD5Update(context,bits,8); 51 | MD5Encode(digest,context->state,16); 52 | } 53 | void MD5Encode(unsigned char *output,unsigned int *input,unsigned int len) 54 | { 55 | unsigned int i = 0,j = 0; 56 | while(j < len) 57 | { 58 | output[j] = input[i] & 0xFF; 59 | output[j+1] = (input[i] >> 8) & 0xFF; 60 | output[j+2] = (input[i] >> 16) & 0xFF; 61 | output[j+3] = (input[i] >> 24) & 0xFF; 62 | i++; 63 | j+=4; 64 | } 65 | } 66 | void MD5Decode(unsigned int *output,unsigned char *input,unsigned int len) 67 | { 68 | unsigned int i = 0,j = 0; 69 | while(j < len) 70 | { 71 | output[i] = (input[j]) | 72 | (input[j+1] << 8) | 73 | (input[j+2] << 16) | 74 | (input[j+3] << 24); 75 | i++; 76 | j+=4; 77 | } 78 | } 79 | void MD5Transform(unsigned int state[4],unsigned char block[64]) 80 | { 81 | unsigned int a = state[0]; 82 | unsigned int b = state[1]; 83 | unsigned int c = state[2]; 84 | unsigned int d = state[3]; 85 | unsigned int x[64]; 86 | MD5Decode(x,block,64); 87 | FF(a, b, c, d, x[ 0], 7, 0xd76aa478); /* 1 */ 88 | FF(d, a, b, c, x[ 1], 12, 0xe8c7b756); /* 2 */ 89 | FF(c, d, a, b, x[ 2], 17, 0x242070db); /* 3 */ 90 | FF(b, c, d, a, x[ 3], 22, 0xc1bdceee); /* 4 */ 91 | FF(a, b, c, d, x[ 4], 7, 0xf57c0faf); /* 5 */ 92 | FF(d, a, b, c, x[ 5], 12, 0x4787c62a); /* 6 */ 93 | FF(c, d, a, b, x[ 6], 17, 0xa8304613); /* 7 */ 94 | FF(b, c, d, a, x[ 7], 22, 0xfd469501); /* 8 */ 95 | FF(a, b, c, d, x[ 8], 7, 0x698098d8); /* 9 */ 96 | FF(d, a, b, c, x[ 9], 12, 0x8b44f7af); /* 10 */ 97 | FF(c, d, a, b, x[10], 17, 0xffff5bb1); /* 11 */ 98 | FF(b, c, d, a, x[11], 22, 0x895cd7be); /* 12 */ 99 | FF(a, b, c, d, x[12], 7, 0x6b901122); /* 13 */ 100 | FF(d, a, b, c, x[13], 12, 0xfd987193); /* 14 */ 101 | FF(c, d, a, b, x[14], 17, 0xa679438e); /* 15 */ 102 | FF(b, c, d, a, x[15], 22, 0x49b40821); /* 16 */ 103 | 104 | /* Round 2 */ 105 | GG(a, b, c, d, x[ 1], 5, 0xf61e2562); /* 17 */ 106 | GG(d, a, b, c, x[ 6], 9, 0xc040b340); /* 18 */ 107 | GG(c, d, a, b, x[11], 14, 0x265e5a51); /* 19 */ 108 | GG(b, c, d, a, x[ 0], 20, 0xe9b6c7aa); /* 20 */ 109 | GG(a, b, c, d, x[ 5], 5, 0xd62f105d); /* 21 */ 110 | GG(d, a, b, c, x[10], 9, 0x2441453); /* 22 */ 111 | GG(c, d, a, b, x[15], 14, 0xd8a1e681); /* 23 */ 112 | GG(b, c, d, a, x[ 4], 20, 0xe7d3fbc8); /* 24 */ 113 | GG(a, b, c, d, x[ 9], 5, 0x21e1cde6); /* 25 */ 114 | GG(d, a, b, c, x[14], 9, 0xc33707d6); /* 26 */ 115 | GG(c, d, a, b, x[ 3], 14, 0xf4d50d87); /* 27 */ 116 | GG(b, c, d, a, x[ 8], 20, 0x455a14ed); /* 28 */ 117 | GG(a, b, c, d, x[13], 5, 0xa9e3e905); /* 29 */ 118 | GG(d, a, b, c, x[ 2], 9, 0xfcefa3f8); /* 30 */ 119 | GG(c, d, a, b, x[ 7], 14, 0x676f02d9); /* 31 */ 120 | GG(b, c, d, a, x[12], 20, 0x8d2a4c8a); /* 32 */ 121 | 122 | /* Round 3 */ 123 | HH(a, b, c, d, x[ 5], 4, 0xfffa3942); /* 33 */ 124 | HH(d, a, b, c, x[ 8], 11, 0x8771f681); /* 34 */ 125 | HH(c, d, a, b, x[11], 16, 0x6d9d6122); /* 35 */ 126 | HH(b, c, d, a, x[14], 23, 0xfde5380c); /* 36 */ 127 | HH(a, b, c, d, x[ 1], 4, 0xa4beea44); /* 37 */ 128 | HH(d, a, b, c, x[ 4], 11, 0x4bdecfa9); /* 38 */ 129 | HH(c, d, a, b, x[ 7], 16, 0xf6bb4b60); /* 39 */ 130 | HH(b, c, d, a, x[10], 23, 0xbebfbc70); /* 40 */ 131 | HH(a, b, c, d, x[13], 4, 0x289b7ec6); /* 41 */ 132 | HH(d, a, b, c, x[ 0], 11, 0xeaa127fa); /* 42 */ 133 | HH(c, d, a, b, x[ 3], 16, 0xd4ef3085); /* 43 */ 134 | HH(b, c, d, a, x[ 6], 23, 0x4881d05); /* 44 */ 135 | HH(a, b, c, d, x[ 9], 4, 0xd9d4d039); /* 45 */ 136 | HH(d, a, b, c, x[12], 11, 0xe6db99e5); /* 46 */ 137 | HH(c, d, a, b, x[15], 16, 0x1fa27cf8); /* 47 */ 138 | HH(b, c, d, a, x[ 2], 23, 0xc4ac5665); /* 48 */ 139 | 140 | /* Round 4 */ 141 | II(a, b, c, d, x[ 0], 6, 0xf4292244); /* 49 */ 142 | II(d, a, b, c, x[ 7], 10, 0x432aff97); /* 50 */ 143 | II(c, d, a, b, x[14], 15, 0xab9423a7); /* 51 */ 144 | II(b, c, d, a, x[ 5], 21, 0xfc93a039); /* 52 */ 145 | II(a, b, c, d, x[12], 6, 0x655b59c3); /* 53 */ 146 | II(d, a, b, c, x[ 3], 10, 0x8f0ccc92); /* 54 */ 147 | II(c, d, a, b, x[10], 15, 0xffeff47d); /* 55 */ 148 | II(b, c, d, a, x[ 1], 21, 0x85845dd1); /* 56 */ 149 | II(a, b, c, d, x[ 8], 6, 0x6fa87e4f); /* 57 */ 150 | II(d, a, b, c, x[15], 10, 0xfe2ce6e0); /* 58 */ 151 | II(c, d, a, b, x[ 6], 15, 0xa3014314); /* 59 */ 152 | II(b, c, d, a, x[13], 21, 0x4e0811a1); /* 60 */ 153 | II(a, b, c, d, x[ 4], 6, 0xf7537e82); /* 61 */ 154 | II(d, a, b, c, x[11], 10, 0xbd3af235); /* 62 */ 155 | II(c, d, a, b, x[ 2], 15, 0x2ad7d2bb); /* 63 */ 156 | II(b, c, d, a, x[ 9], 21, 0xeb86d391); /* 64 */ 157 | state[0] += a; 158 | state[1] += b; 159 | state[2] += c; 160 | state[3] += d; 161 | } 162 | -------------------------------------------------------------------------------- /aic_load_fw/aic_txrxif.h: -------------------------------------------------------------------------------- 1 | /** 2 | * aicwf_txrxif.h 3 | * 4 | * bus function declarations 5 | * 6 | * Copyright (C) AICSemi 2018-2020 7 | */ 8 | 9 | #ifndef _AICWF_TXRXIF_H_ 10 | #define _AICWF_TXRXIF_H_ 11 | 12 | #include 13 | #include 14 | //#include "aicsdio.h" 15 | #include "aicwf_usb.h" 16 | 17 | #define CMD_BUF_MAX 1536 18 | #define DATA_BUF_MAX 2048 19 | #define TXPKT_BLOCKSIZE 512 20 | #define MAX_AGGR_TXPKT_LEN (1536*32) 21 | #define CMD_TX_TIMEOUT 5000 22 | #define TX_ALIGNMENT 4 23 | 24 | #define RX_HWHRD_LEN 60 //58->60 word allined 25 | #define CCMP_OR_WEP_INFO 8 26 | #define MAX_RXQLEN 2000 27 | #define RX_ALIGNMENT 4 28 | 29 | #define DEBUG_ERROR_LEVEL 0 30 | #define DEBUG_DEBUG_LEVEL 1 31 | #define DEBUG_INFO_LEVEL 2 32 | 33 | #define DBG_LEVEL DEBUG_DEBUG_LEVEL 34 | 35 | #define txrx_err(fmt, ...) pr_err("txrx_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__) 36 | #define sdio_err(fmt, ...) pr_err("sdio_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__) 37 | #define usb_err(fmt, ...) pr_err("usb_err:<%s,%d>: " fmt, __func__, __LINE__, ##__VA_ARGS__) 38 | #if DBG_LEVEL >= DEBUG_DEBUG_LEVEL 39 | #define sdio_dbg(fmt, ...) printk("aicbt: " fmt, ##__VA_ARGS__) 40 | #define usb_dbg(fmt, ...) printk("aicbt: " fmt, ##__VA_ARGS__) 41 | #else 42 | #define sdio_dbg(fmt, ...) 43 | #define usb_dbg(fmt, ...) 44 | #endif 45 | #if DBG_LEVEL >= DEBUG_INFO_LEVEL 46 | #define sdio_info(fmt, ...) printk("aicbt: " fmt, ##__VA_ARGS__) 47 | #define usb_info(fmt, ...) printk("aicbt: " fmt, ##__VA_ARGS__) 48 | #else 49 | #define sdio_info(fmt, ...) 50 | #define usb_info(fmt, ...) 51 | #endif 52 | 53 | enum aicwf_bus_state { 54 | BUS_DOWN_ST, 55 | BUS_UP_ST 56 | }; 57 | 58 | struct aicwf_bus_ops { 59 | int (*start) (struct device * dev); 60 | void (*stop) (struct device * dev); 61 | int (*txdata) (struct device * dev, struct sk_buff * skb); 62 | int (*txmsg) (struct device * dev, u8 * msg, uint len); 63 | }; 64 | 65 | struct frame_queue { 66 | u16 num_prio; 67 | u16 hi_prio; 68 | u16 qmax; /* max number of queued frames */ 69 | u16 qcnt; 70 | struct sk_buff_head queuelist[8]; 71 | }; 72 | 73 | struct aicwf_bus { 74 | union { 75 | struct aic_sdio_dev *sdio; 76 | struct aic_usb_dev *usb; 77 | } bus_priv; 78 | struct device *dev; 79 | struct aicwf_bus_ops *ops; 80 | enum aicwf_bus_state state; 81 | u8 *cmd_buf; 82 | struct completion bustx_trgg; 83 | struct completion busrx_trgg; 84 | struct task_struct *bustx_thread; 85 | struct task_struct *busrx_thread; 86 | }; 87 | 88 | struct aicwf_tx_priv { 89 | #ifdef AICWF_SDIO_SUPPORT 90 | struct aic_sdio_dev *sdiodev; 91 | int fw_avail_bufcnt; 92 | //for cmd tx 93 | u8 *cmd_buf; 94 | uint cmd_len; 95 | bool cmd_txstate; 96 | bool cmd_tx_succ; 97 | struct semaphore cmd_txsema; 98 | wait_queue_head_t cmd_txdone_wait; 99 | //for data tx 100 | atomic_t tx_pktcnt; 101 | 102 | struct frame_queue txq; 103 | spinlock_t txqlock; 104 | struct semaphore txctl_sema; 105 | #endif 106 | #ifdef AICWF_USB_SUPPORT 107 | struct aic_usb_dev *usbdev; 108 | #endif 109 | struct sk_buff *aggr_buf; 110 | atomic_t aggr_count; 111 | u8 *head; 112 | u8 *tail; 113 | }; 114 | 115 | 116 | #define MAX_REORD_RXFRAME 250 117 | #define REORDER_UPDATE_TIME 50 118 | #define AICWF_REORDER_WINSIZE 64 119 | #define SN_LESS(a, b) (((a-b)&0x800)!=0) 120 | #define SN_EQUAL(a, b) (a == b) 121 | 122 | struct reord_ctrl { 123 | struct aicwf_rx_priv *rx_priv; 124 | u8 enable; 125 | u16 ind_sn; 126 | u8 wsize_b; 127 | spinlock_t reord_list_lock; 128 | struct list_head reord_list; 129 | struct timer_list reord_timer; 130 | struct work_struct reord_timer_work; 131 | }; 132 | 133 | struct reord_ctrl_info { 134 | u8 mac_addr[6]; 135 | struct reord_ctrl preorder_ctrl[8]; 136 | struct list_head list; 137 | }; 138 | 139 | struct recv_msdu { 140 | struct sk_buff *pkt; 141 | u8 tid; 142 | u16 seq_num; 143 | uint len; 144 | u8 *rx_data; 145 | //for pending rx reorder list 146 | struct list_head reord_pending_list; 147 | //for total frame list, when rxframe from busif, dequeue, when submit frame to net, enqueue 148 | struct list_head rxframe_list; 149 | struct reord_ctrl *preorder_ctrl; 150 | }; 151 | 152 | struct aicwf_rx_priv { 153 | struct aic_usb_dev *usbdev; 154 | void *rwnx_vif; 155 | atomic_t rx_cnt; 156 | u32 data_len; 157 | spinlock_t rxqlock; 158 | struct frame_queue rxq; 159 | 160 | spinlock_t freeq_lock; 161 | struct list_head rxframes_freequeue; 162 | struct list_head stas_reord_list; 163 | spinlock_t stas_reord_lock; 164 | struct recv_msdu *recv_frames; 165 | }; 166 | 167 | static inline int aicwf_bus_start(struct aicwf_bus *bus) 168 | { 169 | return bus->ops->start(bus->dev); 170 | } 171 | 172 | static inline void aicwf_bus_stop(struct aicwf_bus *bus) 173 | { 174 | bus->ops->stop(bus->dev); 175 | } 176 | 177 | static inline int aicwf_bus_txdata(struct aicwf_bus *bus, struct sk_buff *skb) 178 | { 179 | return bus->ops->txdata(bus->dev, skb); 180 | } 181 | 182 | static inline int aicwf_bus_txmsg(struct aicwf_bus *bus, u8 *msg, uint len) 183 | { 184 | return bus->ops->txmsg(bus->dev, msg, len); 185 | } 186 | 187 | static inline void aicwf_sched_timeout(u32 millisec) 188 | { 189 | ulong timeout = 0, expires = 0; 190 | expires = jiffies + msecs_to_jiffies(millisec); 191 | timeout = millisec; 192 | 193 | while (timeout) { 194 | timeout = schedule_timeout(timeout); 195 | if (time_after(jiffies, expires)) 196 | break; 197 | } 198 | } 199 | 200 | int aicwf_bus_init(uint bus_hdrlen, struct device *dev); 201 | void aicwf_bus_deinit(struct device *dev); 202 | void aicwf_tx_deinit(struct aicwf_tx_priv* tx_priv); 203 | void aicwf_rx_deinit(struct aicwf_rx_priv* rx_priv); 204 | struct aicwf_tx_priv* aicwf_tx_init(void *arg); 205 | struct aicwf_rx_priv* aicwf_rx_init(void *arg); 206 | void aicwf_frame_queue_init(struct frame_queue *pq, int num_prio, int max_len); 207 | void aicwf_frame_queue_flush(struct frame_queue *pq); 208 | bool aicwf_frame_enq(struct device *dev, struct frame_queue *q, struct sk_buff *pkt, int prio); 209 | bool aicwf_rxframe_enqueue(struct device *dev, struct frame_queue *q, struct sk_buff *pkt); 210 | bool aicwf_is_framequeue_empty(struct frame_queue *pq); 211 | void aicwf_frame_tx(void *dev, struct sk_buff *skb); 212 | void aicwf_dev_skb_free(struct sk_buff *skb); 213 | struct sk_buff *aicwf_frame_dequeue(struct frame_queue *pq); 214 | struct sk_buff *aicwf_frame_queue_peek_tail(struct frame_queue *pq, int *prio_out); 215 | 216 | #endif /* _AICWF_TXRXIF_H_ */ 217 | -------------------------------------------------------------------------------- /aic8800_fdrv/reg_access.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file reg_access.h 5 | * 6 | * @brief Definitions and macros for MAC HW and platform register accesses 7 | * 8 | * Copyright (C) RivieraWaves 2011-2019 9 | * 10 | ****************************************************************************** 11 | */ 12 | 13 | #ifndef REG_ACCESS_H_ 14 | #define REG_ACCESS_H_ 15 | 16 | /***************************************************************************** 17 | * Addresses within RWNX_ADDR_CPU 18 | *****************************************************************************/ 19 | #define RAM_LMAC_FW_ADDR 0x00150000 20 | 21 | #define ROM_FMAC_FW_ADDR 0x00010000 22 | #define RAM_FMAC_FW_ADDR 0x00120000 23 | #define ROM_FMAC_PATCH_ADDR 0x00180000 24 | #if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB) 25 | #define ROM_FMAC_CALIB_ADDR 0x00130000 26 | #endif 27 | 28 | 29 | /***************************************************************************** 30 | * Addresses within RWNX_ADDR_SYSTEM 31 | *****************************************************************************/ 32 | /* Shard RAM */ 33 | #define SHARED_RAM_START_ADDR 0x00000000 34 | 35 | /* IPC registers */ 36 | #define IPC_REG_BASE_ADDR 0x00800000 37 | 38 | /* System Controller Registers */ 39 | #define SYSCTRL_SIGNATURE_ADDR 0x00900000 40 | // old diag register name 41 | #define SYSCTRL_DIAG_CONF_ADDR 0x00900068 42 | #define SYSCTRL_PHYDIAG_CONF_ADDR 0x00900074 43 | #define SYSCTRL_RIUDIAG_CONF_ADDR 0x00900078 44 | // new diag register name 45 | #define SYSCTRL_DIAG_CONF0 0x00900064 46 | #define SYSCTRL_DIAG_CONF1 0x00900068 47 | #define SYSCTRL_DIAG_CONF2 0x00900074 48 | #define SYSCTRL_DIAG_CONF3 0x00900078 49 | #define SYSCTRL_MISC_CNTL_ADDR 0x009000E0 50 | #define BOOTROM_ENABLE BIT(4) 51 | #define FPGA_B_RESET BIT(1) 52 | #define SOFT_RESET BIT(0) 53 | 54 | /* MAC platform */ 55 | #define NXMAC_VERSION_1_ADDR 0x00B00004 56 | #define NXMAC_MU_MIMO_TX_BIT BIT(19) 57 | #define NXMAC_BFMER_BIT BIT(18) 58 | #define NXMAC_BFMEE_BIT BIT(17) 59 | #define NXMAC_MAC_80211MH_FORMAT_BIT BIT(16) 60 | #define NXMAC_COEX_BIT BIT(14) 61 | #define NXMAC_WAPI_BIT BIT(13) 62 | #define NXMAC_TPC_BIT BIT(12) 63 | #define NXMAC_VHT_BIT BIT(11) 64 | #define NXMAC_HT_BIT BIT(10) 65 | #define NXMAC_RCE_BIT BIT(8) 66 | #define NXMAC_CCMP_BIT BIT(7) 67 | #define NXMAC_TKIP_BIT BIT(6) 68 | #define NXMAC_WEP_BIT BIT(5) 69 | #define NXMAC_SECURITY_BIT BIT(4) 70 | #define NXMAC_SME_BIT BIT(3) 71 | #define NXMAC_HCCA_BIT BIT(2) 72 | #define NXMAC_EDCA_BIT BIT(1) 73 | #define NXMAC_QOS_BIT BIT(0) 74 | 75 | #define NXMAC_RX_CNTRL_ADDR 0x00B00060 76 | #define NXMAC_EN_DUPLICATE_DETECTION_BIT BIT(31) 77 | #define NXMAC_ACCEPT_UNKNOWN_BIT BIT(30) 78 | #define NXMAC_ACCEPT_OTHER_DATA_FRAMES_BIT BIT(29) 79 | #define NXMAC_ACCEPT_QO_S_NULL_BIT BIT(28) 80 | #define NXMAC_ACCEPT_QCFWO_DATA_BIT BIT(27) 81 | #define NXMAC_ACCEPT_Q_DATA_BIT BIT(26) 82 | #define NXMAC_ACCEPT_CFWO_DATA_BIT BIT(25) 83 | #define NXMAC_ACCEPT_DATA_BIT BIT(24) 84 | #define NXMAC_ACCEPT_OTHER_CNTRL_FRAMES_BIT BIT(23) 85 | #define NXMAC_ACCEPT_CF_END_BIT BIT(22) 86 | #define NXMAC_ACCEPT_ACK_BIT BIT(21) 87 | #define NXMAC_ACCEPT_CTS_BIT BIT(20) 88 | #define NXMAC_ACCEPT_RTS_BIT BIT(19) 89 | #define NXMAC_ACCEPT_PS_POLL_BIT BIT(18) 90 | #define NXMAC_ACCEPT_BA_BIT BIT(17) 91 | #define NXMAC_ACCEPT_BAR_BIT BIT(16) 92 | #define NXMAC_ACCEPT_OTHER_MGMT_FRAMES_BIT BIT(15) 93 | #define NXMAC_ACCEPT_BFMEE_FRAMES_BIT BIT(14) 94 | #define NXMAC_ACCEPT_ALL_BEACON_BIT BIT(13) 95 | #define NXMAC_ACCEPT_NOT_EXPECTED_BA_BIT BIT(12) 96 | #define NXMAC_ACCEPT_DECRYPT_ERROR_FRAMES_BIT BIT(11) 97 | #define NXMAC_ACCEPT_BEACON_BIT BIT(10) 98 | #define NXMAC_ACCEPT_PROBE_RESP_BIT BIT(9) 99 | #define NXMAC_ACCEPT_PROBE_REQ_BIT BIT(8) 100 | #define NXMAC_ACCEPT_MY_UNICAST_BIT BIT(7) 101 | #define NXMAC_ACCEPT_UNICAST_BIT BIT(6) 102 | #define NXMAC_ACCEPT_ERROR_FRAMES_BIT BIT(5) 103 | #define NXMAC_ACCEPT_OTHER_BSSID_BIT BIT(4) 104 | #define NXMAC_ACCEPT_BROADCAST_BIT BIT(3) 105 | #define NXMAC_ACCEPT_MULTICAST_BIT BIT(2) 106 | #define NXMAC_DONT_DECRYPT_BIT BIT(1) 107 | #define NXMAC_EXC_UNENCRYPTED_BIT BIT(0) 108 | 109 | #define NXMAC_DEBUG_PORT_SEL_ADDR 0x00B00510 110 | #define NXMAC_SW_SET_PROFILING_ADDR 0x00B08564 111 | #define NXMAC_SW_CLEAR_PROFILING_ADDR 0x00B08568 112 | 113 | /* Modem Status */ 114 | #define MDM_HDMCONFIG_ADDR 0x00C00000 115 | 116 | /* Clock gating configuration */ 117 | #define MDM_MEMCLKCTRL0_ADDR 0x00C00848 118 | #define MDM_CLKGATEFCTRL0_ADDR 0x00C00874 119 | #define CRM_CLKGATEFCTRL0_ADDR 0x00940010 120 | 121 | /* AGC (trident) */ 122 | #define AGC_RWNXAGCCNTL_ADDR 0x00C02060 123 | 124 | /* LDPC RAM*/ 125 | #define PHY_LDPC_RAM_ADDR 0x00C09000 126 | 127 | /* FCU (elma )*/ 128 | #define FCU_RWNXFCAGCCNTL_ADDR 0x00C09034 129 | 130 | /* AGC RAM */ 131 | #define PHY_AGC_UCODE_ADDR 0x00C0A000 132 | 133 | /* RIU */ 134 | #define RIU_RWNXVERSION_ADDR 0x00C0B000 135 | #define RIU_RWNXDYNAMICCONFIG_ADDR 0x00C0B008 136 | #define RIU_AGCMEMBISTSTAT_ADDR 0x00C0B238 137 | #define RIU_AGCMEMSIGNATURESTAT_ADDR 0x00C0B23C 138 | #define RIU_RWNXAGCCNTL_ADDR 0x00C0B390 139 | 140 | /* FCU RAM */ 141 | #define PHY_FCU_UCODE_ADDR 0x00C0E000 142 | 143 | /* RF ITF */ 144 | #define FPGAB_MPIF_SEL_ADDR 0x00C10030 145 | #define RF_V6_DIAGPORT_CONF1_ADDR 0x00C10010 146 | #define RF_v6_PHYDIAG_CONF1_ADDR 0x00C10018 147 | 148 | #define RF_V7_DIAGPORT_CONF1_ADDR 0x00F10010 149 | #define RF_v7_PHYDIAG_CONF1_ADDR 0x00F10018 150 | 151 | /***************************************************************************** 152 | * Macros for generated register files 153 | *****************************************************************************/ 154 | /* Macros for IPC registers access (used in reg_ipc_app.h) */ 155 | #define REG_IPC_APP_RD(env, INDEX) \ 156 | (*(volatile u32*)((u8*)env + IPC_REG_BASE_ADDR + 4*(INDEX))) 157 | 158 | #define REG_IPC_APP_WR(env, INDEX, value) \ 159 | (*(volatile u32*)((u8*)env + IPC_REG_BASE_ADDR + 4*(INDEX)) = value) 160 | 161 | #endif /* REG_ACCESS_H_ */ 162 | -------------------------------------------------------------------------------- /aic_load_fw/aicwf_usb.h: -------------------------------------------------------------------------------- 1 | /** 2 | * aicwf_usb.h 3 | * 4 | * USB function declarations 5 | * 6 | * Copyright (C) AICSemi 2018-2020 7 | */ 8 | 9 | #ifndef _AICWF_USB_H_ 10 | #define _AICWF_USB_H_ 11 | 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | 18 | #include "aicbluetooth_cmds.h" 19 | 20 | #ifdef AICWF_USB_SUPPORT 21 | 22 | /* USB Device ID */ 23 | #define USB_VENDOR_ID_AIC 0xA69C 24 | #define USB_VENDOR_ID_AIC_V2 0x368B 25 | #define USB_DEVICE_ID_AIC 0x8800 26 | #define USB_DEVICE_ID_AIC_8801 0x8801 27 | 28 | #define CHIP_REV_U01 0x1 29 | #define CHIP_REV_U02 0x3 30 | #define CHIP_REV_U03 0x7 31 | #define CHIP_REV_U04 0xf 32 | #define CHIP_REV_U05 0x1f 33 | #define CHIP_SUB_REV_U04 0x20 34 | 35 | enum AICWF_IC{ 36 | PRODUCT_ID_AIC8800 = 0, 37 | PRODUCT_ID_AIC8801, 38 | PRODUCT_ID_AIC8800DC, 39 | PRODUCT_ID_AIC8800DW, 40 | PRODUCT_ID_AIC8800D80, 41 | PRODUCT_ID_AIC8800D81, 42 | PRODUCT_ID_AIC8800D80X2, 43 | PRODUCT_ID_AIC8800D81X2, 44 | PRODUCT_ID_AIC8800D89X2, 45 | }; 46 | 47 | 48 | #define AICWF_USB_RX_URBS (20) 49 | #define AICWF_USB_TX_URBS (100) 50 | #define AICWF_USB_TX_LOW_WATER (AICWF_USB_TX_URBS/4) 51 | #define AICWF_USB_TX_HIGH_WATER (AICWF_USB_TX_LOW_WATER*3) 52 | #define AICWF_USB_MAX_PKT_SIZE (2048) 53 | 54 | #ifdef CONFIG_RFTEST 55 | #define FW_RF_PATCH_BASE_NAME "fw_patch.bin" 56 | #define FW_RF_ADID_BASE_NAME "fw_adid.bin" 57 | #define FW_RF_BASE_NAME "fmacfw_rf.bin" 58 | #define FW_PATCH_BASE_NAME "fw_patch.bin" 59 | #define FW_ADID_BASE_NAME "fw_adid.bin" 60 | #define FW_BASE_NAME "fmacfw.bin" 61 | #define FW_BLE_SCAN_WAKEUP_NAME "fw_ble_scan.bin" 62 | #define FW_BLE_SCAN_AD_FILTER_NAME "fw_ble_scan_ad_filter.bin" 63 | 64 | #define FW_PATCH_BASE_NAME_PC "fw_patch.bin" 65 | #define FW_ADID_BASE_NAME_PC "fw_adid.bin" 66 | #define FW_BASE_NAME_PC "fmacfw.bin" 67 | #define FW_RF_PATCH_BASE_NAME_PC "fw_patch.bin" 68 | #define FW_RF_ADID_BASE_NAME_PC "fw_adid.bin" 69 | #define FW_RF_BASE_NAME_PC "fmacfw_rf.bin" 70 | #define FW_PATCH_TEST_BASE_NAME "fw_patch_test.bin" 71 | #define FW_PATCH_BASE_NAME_U03 "fw_patch_u03.bin" 72 | #define FW_ADID_BASE_NAME_U03 "fw_adid_u03.bin" 73 | 74 | #else 75 | #define FW_PATCH_BASE_NAME "fw_patch.bin" 76 | #define FW_ADID_BASE_NAME "fw_adid.bin" 77 | #define FW_BASE_NAME "fmacfw.bin" 78 | #endif 79 | 80 | #define FW_PATCH_TABLE_NAME "fw_patch_table.bin" 81 | #define FW_PATCH_TABLE_NAME_U03 "fw_patch_table_u03.bin" 82 | #define FW_USERCONFIG_NAME "aic_userconfig.txt" 83 | #define FW_M2D_OTA_NAME "m2d_ota.bin" 84 | 85 | /*8800 use 0x100000, 8800D80 use 0x160000*/ 86 | #define RAM_FW_BLE_SCAN_WAKEUP_ADDR_8800D80 0x00160000 87 | #define RAM_FW_BLE_SCAN_WAKEUP_ADDR 0x00100000 88 | #define RAM_FW_ADDR 0x00110000 89 | #define FW_RAM_ADID_BASE_ADDR 0x00161928 90 | #define FW_RAM_PATCH_BASE_ADDR 0x00100000 91 | #define FW_RAM_PATCH_BASE_ADDR_U03 0x00100000 92 | #define FW_PATCH_TEST_BASE_ADDR 0x00100000 93 | 94 | enum { 95 | FW_NORMAL_MODE, 96 | FW_TEST_MODE, 97 | FW_BLE_SCAN_WAKEUP_MODE, 98 | FW_M2D_OTA_MODE, 99 | FW_DPDCALIB_MODE, 100 | FW_BLE_SCAN_AD_FILTER_MODE, 101 | }; 102 | 103 | 104 | #if 0 105 | #define FW_NAME2 FW_BASE_NAME".bin" 106 | #define FW_PATCH_BIN_NAME FW_PATCH_BASE_NAME".bin" 107 | #define FW_ADID_BIN_NAME FW_ADID_BASE_NAME".bin" 108 | #endif 109 | 110 | typedef enum { 111 | USB_TYPE_DATA = 0X00, 112 | USB_TYPE_CFG = 0X10, 113 | USB_TYPE_CFG_CMD_RSP = 0X11, 114 | USB_TYPE_CFG_DATA_CFM = 0X12 115 | } usb_type; 116 | 117 | enum aicwf_usb_state { 118 | USB_DOWN_ST, 119 | USB_UP_ST, 120 | USB_SLEEP_ST 121 | }; 122 | 123 | #define MAX_AD_FILTER_NUM 5// Max AD Filter num 124 | #define MAX_GPIO_TRIGGER_NUM 2// Max user config num of gpio 125 | #define MAX_ROLE_COMNO_IDX_NUM 2// Max num of ad role type combo,form( enum gpio_combo_idx) 126 | 127 | #define AD_ROLE_FLAG 0x0f 128 | #define ROLE_COMBO_IDX_FLAG 0xf0 129 | 130 | enum ad_role_type { 131 | ROLE_ONLY,// ROLE_ONLY will trigger wake up immediately. 132 | ROLE_COMBO,//ROLE_COMBO will trigger When all the conditions (ad_role == ROLE_COMBO,and ad_filter is matching)are met. 133 | }; 134 | 135 | enum gpio_combo_idx { 136 | COMBO_0, 137 | COMBO_1, 138 | }; 139 | 140 | enum gpio_trigger_bit { 141 | TG_IDX_0 = (1<<0), 142 | TG_IDX_1 = (1<<1), 143 | }; 144 | 145 | struct wakeup_ad_data_filter { 146 | uint32_t ad_data_mask; 147 | uint8_t gpio_trigger_idx; 148 | uint8_t ad_role;//from enum ad_role_type 149 | uint8_t ad_len; 150 | uint8_t ad_type; 151 | uint8_t ad_data[31]; 152 | }; 153 | 154 | struct ble_wakeup_param_t { 155 | uint32_t magic_num;// "BLES" = 0x53454C42 156 | uint32_t delay_scan_to;// timeout for start scan in ms 157 | uint32_t reboot_to;// timeout for reboot in ms 158 | uint32_t gpio_num[MAX_GPIO_TRIGGER_NUM]; 159 | uint32_t gpio_dft_lvl[MAX_GPIO_TRIGGER_NUM]; 160 | struct wakeup_ad_data_filter ad_filter[MAX_AD_FILTER_NUM]; 161 | }; 162 | 163 | struct aicwf_usb_buf { 164 | struct list_head list; 165 | struct aic_usb_dev *usbdev; 166 | struct urb *urb; 167 | struct sk_buff *skb; 168 | #ifdef CONFIG_USB_NO_TRANS_DMA_MAP 169 | u8 *data_buf; 170 | dma_addr_t data_dma_trans_addr; 171 | #endif 172 | bool cfm; 173 | }; 174 | 175 | struct aic_usb_dev { 176 | struct rwnx_cmd_mgr cmd_mgr; 177 | struct aicwf_bus *bus_if; 178 | struct usb_device *udev; 179 | struct device *dev; 180 | struct aicwf_rx_priv* rx_priv; 181 | enum aicwf_usb_state state; 182 | 183 | struct usb_anchor rx_submitted; 184 | struct work_struct rx_urb_work; 185 | 186 | spinlock_t rx_free_lock; 187 | spinlock_t tx_free_lock; 188 | spinlock_t tx_post_lock; 189 | spinlock_t tx_flow_lock; 190 | 191 | struct list_head rx_free_list; 192 | struct list_head tx_free_list; 193 | struct list_head tx_post_list; 194 | 195 | uint bulk_in_pipe; 196 | uint bulk_out_pipe; 197 | #ifdef CONFIG_USB_MSG_EP 198 | uint msg_out_pipe; 199 | uint use_msg_ep; 200 | #endif 201 | 202 | int tx_free_count; 203 | int tx_post_count; 204 | 205 | struct aicwf_usb_buf usb_tx_buf[AICWF_USB_TX_URBS]; 206 | struct aicwf_usb_buf usb_rx_buf[AICWF_USB_RX_URBS]; 207 | 208 | int msg_finished; 209 | wait_queue_head_t msg_wait; 210 | ulong msg_busy; 211 | struct urb *msg_out_urb; 212 | #ifdef CONFIG_USB_NO_TRANS_DMA_MAP 213 | dma_addr_t cmd_dma_trans_addr; 214 | #endif 215 | 216 | u16 chipid; 217 | bool tbusy; 218 | bool app_cmp; 219 | u32 fw_version_uint; 220 | }; 221 | 222 | extern void aicwf_usb_exit(void); 223 | extern void aicwf_usb_register(void); 224 | extern void aicwf_usb_tx_flowctrl(struct aic_usb_dev *usb_dev, bool state); 225 | int usb_bustx_thread(void *data); 226 | int usb_busrx_thread(void *data); 227 | int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv); 228 | 229 | #endif /* AICWF_USB_SUPPORT */ 230 | #endif /* _AICWF_USB_H_ */ 231 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_tx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * 4 | * @file rwnx_tx.h 5 | * 6 | * Copyright (C) RivieraWaves 2012-2019 7 | * 8 | ****************************************************************************** 9 | */ 10 | #ifndef _RWNX_TX_H_ 11 | #define _RWNX_TX_H_ 12 | 13 | #include 14 | #include 15 | #include 16 | #include "lmac_types.h" 17 | #include "ipc_shared.h" 18 | #include "rwnx_txq.h" 19 | #include "hal_desc.h" 20 | 21 | #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0) 22 | #define IEEE80211_NUM_TIDS 16 23 | #endif 24 | 25 | #define RWNX_HWQ_BK 0 26 | #define RWNX_HWQ_BE 1 27 | #define RWNX_HWQ_VI 2 28 | #define RWNX_HWQ_VO 3 29 | #define RWNX_HWQ_BCMC 4 30 | #define RWNX_HWQ_NB NX_TXQ_CNT 31 | #define RWNX_HWQ_ALL_ACS (RWNX_HWQ_BK | RWNX_HWQ_BE | RWNX_HWQ_VI | RWNX_HWQ_VO) 32 | #define RWNX_HWQ_ALL_ACS_BIT ( BIT(RWNX_HWQ_BK) | BIT(RWNX_HWQ_BE) | \ 33 | BIT(RWNX_HWQ_VI) | BIT(RWNX_HWQ_VO) ) 34 | 35 | #define RWNX_TX_LIFETIME_MS 1000 36 | #define RWNX_TX_MAX_RATES NX_TX_MAX_RATES 37 | 38 | #define RWNX_SWTXHDR_ALIGN_SZ 4 39 | #define RWNX_SWTXHDR_ALIGN_MSK (RWNX_SWTXHDR_ALIGN_SZ - 1) 40 | #define RWNX_SWTXHDR_ALIGN_PADS(x) \ 41 | ((RWNX_SWTXHDR_ALIGN_SZ - ((x) & RWNX_SWTXHDR_ALIGN_MSK)) \ 42 | & RWNX_SWTXHDR_ALIGN_MSK) 43 | #if RWNX_SWTXHDR_ALIGN_SZ & RWNX_SWTXHDR_ALIGN_MSK 44 | #error bad RWNX_SWTXHDR_ALIGN_SZ 45 | #endif 46 | 47 | #define AMSDU_PADDING(x) ((4 - ((x) & 0x3)) & 0x3) 48 | 49 | #define TXU_CNTRL_RETRY BIT(0) 50 | #define TXU_CNTRL_MORE_DATA BIT(2) 51 | #define TXU_CNTRL_MGMT BIT(3) 52 | #define TXU_CNTRL_MGMT_NO_CCK BIT(4) 53 | #define TXU_CNTRL_AMSDU BIT(6) 54 | #define TXU_CNTRL_MGMT_ROBUST BIT(7) 55 | #define TXU_CNTRL_USE_4ADDR BIT(8) 56 | #define TXU_CNTRL_EOSP BIT(9) 57 | #define TXU_CNTRL_MESH_FWD BIT(10) 58 | #define TXU_CNTRL_TDLS BIT(11) 59 | 60 | extern const int rwnx_tid2hwq[IEEE80211_NUM_TIDS]; 61 | 62 | /** 63 | * struct rwnx_amsdu_txhdr - Structure added in skb headroom (instead of 64 | * rwnx_txhdr) for amsdu subframe buffer (except for the first subframe 65 | * that has a normal rwnx_txhdr) 66 | * 67 | * @list List of other amsdu subframe (rwnx_sw_txhdr.amsdu.hdrs) 68 | * @map_len Length to be downloaded for this subframe 69 | * @dma_addr Buffer address form embedded point of view 70 | * @skb skb 71 | * @pad padding added before this subframe 72 | * (only use when amsdu must be dismantled) 73 | * @msdu_len Size, in bytes, of the MSDU (without padding nor amsdu header) 74 | */ 75 | struct rwnx_amsdu_txhdr { 76 | struct list_head list; 77 | size_t map_len; 78 | dma_addr_t dma_addr; 79 | struct sk_buff *skb; 80 | u16 pad; 81 | u16 msdu_len; 82 | }; 83 | 84 | /** 85 | * struct rwnx_amsdu - Structure to manage creation of an A-MSDU, updated 86 | * only In the first subframe of an A-MSDU 87 | * 88 | * @hdrs List of subframe of rwnx_amsdu_txhdr 89 | * @len Current size for this A-MDSU (doesn't take padding into account) 90 | * 0 means that no amsdu is in progress 91 | * @nb Number of subframe in the amsdu 92 | * @pad Padding to add before adding a new subframe 93 | */ 94 | struct rwnx_amsdu { 95 | struct list_head hdrs; 96 | u16 len; 97 | u8 nb; 98 | u8 pad; 99 | }; 100 | 101 | /** 102 | * struct rwnx_sw_txhdr - Software part of tx header 103 | * 104 | * @rwnx_sta sta to which this buffer is addressed 105 | * @rwnx_vif vif that send the buffer 106 | * @txq pointer to TXQ used to send the buffer 107 | * @hw_queue Index of the HWQ used to push the buffer. 108 | * May be different than txq->hwq->id on confirmation. 109 | * @frame_len Size of the frame (doesn't not include mac header) 110 | * (Only used to update stat, can't we use skb->len instead ?) 111 | * @headroom Headroom added in skb to add rwnx_txhdr 112 | * (Only used to remove it before freeing skb, is it needed ?) 113 | * @amsdu Description of amsdu whose first subframe is this buffer 114 | * (amsdu.nb = 0 means this buffer is not part of amsdu) 115 | * @skb skb received from transmission 116 | * @map_len Length mapped for DMA (only rwnx_hw_txhdr and data are mapped) 117 | * @dma_addr DMA address after mapping 118 | * @desc Buffer description that will be copied in shared mem for FW 119 | */ 120 | struct rwnx_sw_txhdr { 121 | struct rwnx_sta *rwnx_sta; 122 | struct rwnx_vif *rwnx_vif; 123 | struct rwnx_txq *txq; 124 | u8 hw_queue; 125 | u16 frame_len; 126 | u16 headroom; 127 | #ifdef CONFIG_RWNX_AMSDUS_TX 128 | struct rwnx_amsdu amsdu; 129 | #endif 130 | u32 need_cfm; 131 | struct sk_buff *skb; 132 | 133 | size_t map_len; 134 | dma_addr_t dma_addr; 135 | struct txdesc_api desc; 136 | u8 raw_frame; 137 | u8 fixed_rate; 138 | u16 rate_config; 139 | }; 140 | 141 | /** 142 | * struct rwnx_txhdr - Stucture to control transimission of packet 143 | * (Added in skb headroom) 144 | * 145 | * @sw_hdr: Information from driver 146 | * @cache_guard: 147 | * @hw_hdr: Information for/from hardware 148 | */ 149 | struct rwnx_txhdr { 150 | struct rwnx_sw_txhdr *sw_hdr; 151 | char cache_guard[L1_CACHE_BYTES]; 152 | struct rwnx_hw_txhdr hw_hdr; 153 | }; 154 | 155 | u16 rwnx_select_txq(struct rwnx_vif *rwnx_vif, struct sk_buff *skb); 156 | netdev_tx_t rwnx_start_xmit(struct sk_buff *skb, struct net_device *dev); 157 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) 158 | int rwnx_start_mgmt_xmit(struct rwnx_vif *vif, struct rwnx_sta *sta, 159 | struct cfg80211_mgmt_tx_params *params, bool offchan, 160 | u64 *cookie); 161 | #else 162 | int rwnx_start_mgmt_xmit(struct rwnx_vif *vif, struct rwnx_sta *sta, 163 | struct ieee80211_channel *channel, bool offchan, 164 | unsigned int wait, const u8* buf, size_t len, 165 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) 166 | bool no_cck, 167 | #endif 168 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) 169 | bool dont_wait_for_ack, 170 | #endif 171 | u64 *cookie); 172 | #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) */ 173 | #ifdef CONFIG_RWNX_MON_XMIT 174 | int rwnx_start_monitor_if_xmit(struct sk_buff *skb, struct net_device *dev); 175 | #endif 176 | int rwnx_txdatacfm(void *pthis, void *host_id); 177 | 178 | struct rwnx_hw; 179 | struct rwnx_sta; 180 | void rwnx_set_traffic_status(struct rwnx_hw *rwnx_hw, 181 | struct rwnx_sta *sta, 182 | bool available, 183 | u8 ps_id); 184 | void rwnx_ps_bh_enable(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta, 185 | bool enable); 186 | void rwnx_ps_bh_traffic_req(struct rwnx_hw *rwnx_hw, struct rwnx_sta *sta, 187 | u16 pkt_req, u8 ps_id); 188 | 189 | void rwnx_switch_vif_sta_txq(struct rwnx_sta *sta, struct rwnx_vif *old_vif, 190 | struct rwnx_vif *new_vif); 191 | 192 | int rwnx_dbgfs_print_sta(char *buf, size_t size, struct rwnx_sta *sta, 193 | struct rwnx_hw *rwnx_hw); 194 | void rwnx_txq_credit_update(struct rwnx_hw *rwnx_hw, int sta_idx, u8 tid, 195 | s8 update); 196 | void rwnx_tx_push(struct rwnx_hw *rwnx_hw, struct rwnx_txhdr *txhdr, int flags); 197 | 198 | #endif /* _RWNX_TX_H_ */ 199 | -------------------------------------------------------------------------------- /aic8800_fdrv/rwnx_testmode.c: -------------------------------------------------------------------------------- 1 | /** 2 | **************************************************************************************** 3 | * 4 | * @file rwnx_testmode.c 5 | * 6 | * @brief Test mode function definitions 7 | * 8 | * Copyright (C) RivieraWaves 2012-2019 9 | * 10 | **************************************************************************************** 11 | */ 12 | 13 | #include 14 | #include 15 | 16 | #include "rwnx_testmode.h" 17 | #include "rwnx_msg_tx.h" 18 | #include "rwnx_dini.h" 19 | #include "reg_access.h" 20 | 21 | /* 22 | * This function handles the user application commands for register access. 23 | * 24 | * It retrieves command ID carried with RWNX_TM_ATTR_COMMAND and calls to the 25 | * handlers respectively. 26 | * 27 | * If it's an unknown commdn ID, -ENOSYS is returned; or -ENOMSG if the 28 | * mandatory fields(RWNX_TM_ATTR_REG_OFFSET,RWNX_TM_ATTR_REG_VALUE32) 29 | * are missing; Otherwise 0 is replied indicating the success of the command execution. 30 | * 31 | * If RWNX_TM_ATTR_COMMAND is RWNX_TM_CMD_APP2DEV_REG_READ, the register read 32 | * value is returned with RWNX_TM_ATTR_REG_VALUE32. 33 | * 34 | * @hw: ieee80211_hw object that represents the device 35 | * @tb: general message fields from the user space 36 | */ 37 | int rwnx_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb) 38 | { 39 | struct rwnx_hw *rwnx_hw = hw->priv; 40 | u32 mem_addr, val32; 41 | struct sk_buff *skb; 42 | int status = 0; 43 | 44 | /* First check if register address is there */ 45 | if (!tb[RWNX_TM_ATTR_REG_OFFSET]) { 46 | printk("Error finding register offset\n"); 47 | return -ENOMSG; 48 | } 49 | 50 | mem_addr = nla_get_u32(tb[RWNX_TM_ATTR_REG_OFFSET]); 51 | 52 | switch (nla_get_u32(tb[RWNX_TM_ATTR_COMMAND])) { 53 | case RWNX_TM_CMD_APP2DEV_REG_READ: 54 | { 55 | struct dbg_mem_read_cfm mem_read_cfm; 56 | 57 | /*** Send the command to the LMAC ***/ 58 | if ((status = rwnx_send_dbg_mem_read_req(rwnx_hw, mem_addr, &mem_read_cfm))) 59 | return status; 60 | 61 | /* Allocate the answer message */ 62 | skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20); 63 | if (!skb) { 64 | printk("Error allocating memory\n"); 65 | return -ENOMEM; 66 | } 67 | 68 | val32 = mem_read_cfm.memdata; 69 | if (nla_put_u32(skb, RWNX_TM_ATTR_REG_VALUE32, val32)) 70 | goto nla_put_failure; 71 | 72 | /* Send the answer to upper layer */ 73 | status = cfg80211_testmode_reply(skb); 74 | if (status < 0) 75 | printk("Error sending msg : %d\n", status); 76 | } 77 | break; 78 | 79 | case RWNX_TM_CMD_APP2DEV_REG_WRITE: 80 | { 81 | if (!tb[RWNX_TM_ATTR_REG_VALUE32]) { 82 | printk("Error finding value to write\n"); 83 | return -ENOMSG; 84 | } else { 85 | val32 = nla_get_u32(tb[RWNX_TM_ATTR_REG_VALUE32]); 86 | /* Send the command to the LMAC */ 87 | if ((status = rwnx_send_dbg_mem_write_req(rwnx_hw, mem_addr, val32))) 88 | return status; 89 | } 90 | } 91 | break; 92 | 93 | default: 94 | printk("Unknown testmode register command ID\n"); 95 | return -ENOSYS; 96 | } 97 | 98 | return status; 99 | 100 | nla_put_failure: 101 | kfree_skb(skb); 102 | return -EMSGSIZE; 103 | } 104 | 105 | /* 106 | * This function handles the user application commands for Debug filter settings. 107 | * 108 | * @hw: ieee80211_hw object that represents the device 109 | * @tb: general message fields from the user space 110 | */ 111 | int rwnx_testmode_dbg_filter(struct ieee80211_hw *hw, struct nlattr **tb) 112 | { 113 | struct rwnx_hw *rwnx_hw = hw->priv; 114 | u32 filter; 115 | int status = 0; 116 | 117 | /* First check if the filter is there */ 118 | if (!tb[RWNX_TM_ATTR_REG_FILTER]) { 119 | printk("Error finding filter value\n"); 120 | return -ENOMSG; 121 | } 122 | 123 | filter = nla_get_u32(tb[RWNX_TM_ATTR_REG_FILTER]); 124 | RWNX_DBG("testmode debug filter, setting: 0x%x\n", filter); 125 | 126 | switch (nla_get_u32(tb[RWNX_TM_ATTR_COMMAND])) { 127 | case RWNX_TM_CMD_APP2DEV_SET_DBGMODFILTER: 128 | { 129 | /* Send the command to the LMAC */ 130 | if ((status = rwnx_send_dbg_set_mod_filter_req(rwnx_hw, filter))) 131 | return status; 132 | } 133 | break; 134 | case RWNX_TM_CMD_APP2DEV_SET_DBGSEVFILTER: 135 | { 136 | /* Send the command to the LMAC */ 137 | if ((status = rwnx_send_dbg_set_sev_filter_req(rwnx_hw, filter))) 138 | return status; 139 | } 140 | break; 141 | 142 | default: 143 | printk("Unknown testmode register command ID\n"); 144 | return -ENOSYS; 145 | } 146 | 147 | return status; 148 | } 149 | 150 | /* 151 | * This function handles the user application commands for register access without using 152 | * the normal LMAC messaging way. 153 | * This time register access will be done through direct PCI BAR windows. This can be used 154 | * to access registers even when the :AMC FW is stuck. 155 | * 156 | * @hw: ieee80211_hw object that represents the device 157 | * @tb: general message fields from the user space 158 | */ 159 | int rwnx_testmode_reg_dbg(struct ieee80211_hw *hw, struct nlattr **tb) 160 | { 161 | struct rwnx_hw *rwnx_hw = hw->priv; 162 | struct rwnx_plat *rwnx_plat = rwnx_hw->plat; 163 | u32 mem_addr; 164 | struct sk_buff *skb; 165 | int status = 0; 166 | volatile unsigned int reg_value = 0; 167 | unsigned int offset; 168 | 169 | /* First check if register address is there */ 170 | if (!tb[RWNX_TM_ATTR_REG_OFFSET]) { 171 | printk("Error finding register offset\n"); 172 | return -ENOMSG; 173 | } 174 | 175 | mem_addr = nla_get_u32(tb[RWNX_TM_ATTR_REG_OFFSET]); 176 | offset = mem_addr & 0x00FFFFFF; 177 | 178 | switch (nla_get_u32(tb[RWNX_TM_ATTR_COMMAND])) { 179 | case RWNX_TM_CMD_APP2DEV_REG_READ_DBG: 180 | { 181 | /*** Send the command to the LMAC ***/ 182 | reg_value = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, offset); 183 | 184 | /* Allocate the answer message */ 185 | skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20); 186 | if (!skb) { 187 | printk("Error allocating memory\n"); 188 | return -ENOMEM; 189 | } 190 | 191 | if (nla_put_u32(skb, RWNX_TM_ATTR_REG_VALUE32, reg_value)) 192 | goto nla_put_failure; 193 | 194 | /* Send the answer to upper layer */ 195 | status = cfg80211_testmode_reply(skb); 196 | if (status < 0) 197 | printk("Error sending msg : %d\n", status); 198 | } 199 | break; 200 | 201 | case RWNX_TM_CMD_APP2DEV_REG_WRITE_DBG: 202 | { 203 | if (!tb[RWNX_TM_ATTR_REG_VALUE32]) { 204 | printk("Error finding value to write\n"); 205 | return -ENOMSG; 206 | } else { 207 | reg_value = nla_get_u32(tb[RWNX_TM_ATTR_REG_VALUE32]); 208 | 209 | /* Send the command to the LMAC */ 210 | RWNX_REG_WRITE(reg_value, rwnx_plat, RWNX_ADDR_SYSTEM, 211 | offset); 212 | } 213 | } 214 | break; 215 | 216 | default: 217 | printk("Unknown testmode register command ID\n"); 218 | return -ENOSYS; 219 | } 220 | 221 | return status; 222 | 223 | nla_put_failure: 224 | kfree_skb(skb); 225 | return -EMSGSIZE; 226 | } 227 | --------------------------------------------------------------------------------