├── Non-Augmented_Data ├── README.md ├── Prompt-Script │ ├── README.md │ ├── DB_Dataset.xlsx │ └── Flow_Dataset.xlsx └── Question-Answer │ ├── README.md │ └── Question-Answer_Dataset.xlsx ├── .gitmodules ├── Augmented_Data ├── Prompt-Script │ ├── DB │ │ ├── query.xlsx │ │ └── circuit_modification.xlsx │ └── Flow │ │ └── flow.xlsx └── Question-Answer │ ├── Flow │ ├── Flow.xlsx │ └── Flow.csv │ ├── Tools │ ├── Tools.xlsx │ └── Tools.csv │ ├── General │ ├── General.xlsx │ └── General.csv │ └── README.md ├── README.md └── LICENSE /Non-Augmented_Data/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Non-Augmented_Data/Prompt-Script/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Non-Augmented_Data/Question-Answer/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "OpenROAD"] 2 | path = OpenROAD 3 | url = https://github.com/The-OpenROAD-Project/OpenROAD.git 4 | -------------------------------------------------------------------------------- /Augmented_Data/Prompt-Script/DB/query.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenROAD-Assistant/EDA-Corpus/HEAD/Augmented_Data/Prompt-Script/DB/query.xlsx -------------------------------------------------------------------------------- /Augmented_Data/Prompt-Script/Flow/flow.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenROAD-Assistant/EDA-Corpus/HEAD/Augmented_Data/Prompt-Script/Flow/flow.xlsx -------------------------------------------------------------------------------- /Augmented_Data/Question-Answer/Flow/Flow.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenROAD-Assistant/EDA-Corpus/HEAD/Augmented_Data/Question-Answer/Flow/Flow.xlsx -------------------------------------------------------------------------------- /Augmented_Data/Question-Answer/Tools/Tools.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenROAD-Assistant/EDA-Corpus/HEAD/Augmented_Data/Question-Answer/Tools/Tools.xlsx -------------------------------------------------------------------------------- /Non-Augmented_Data/Prompt-Script/DB_Dataset.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenROAD-Assistant/EDA-Corpus/HEAD/Non-Augmented_Data/Prompt-Script/DB_Dataset.xlsx -------------------------------------------------------------------------------- /Augmented_Data/Question-Answer/General/General.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenROAD-Assistant/EDA-Corpus/HEAD/Augmented_Data/Question-Answer/General/General.xlsx -------------------------------------------------------------------------------- /Non-Augmented_Data/Prompt-Script/Flow_Dataset.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenROAD-Assistant/EDA-Corpus/HEAD/Non-Augmented_Data/Prompt-Script/Flow_Dataset.xlsx -------------------------------------------------------------------------------- /Augmented_Data/Prompt-Script/DB/circuit_modification.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenROAD-Assistant/EDA-Corpus/HEAD/Augmented_Data/Prompt-Script/DB/circuit_modification.xlsx -------------------------------------------------------------------------------- /Non-Augmented_Data/Question-Answer/Question-Answer_Dataset.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenROAD-Assistant/EDA-Corpus/HEAD/Non-Augmented_Data/Question-Answer/Question-Answer_Dataset.xlsx -------------------------------------------------------------------------------- /Augmented_Data/Question-Answer/README.md: -------------------------------------------------------------------------------- 1 | ### This is the Question-Answer format Large Language Model EDA Dataset for OpenROAD 2 | 3 | This dataset has been divided into 3 categories: 4 | 5 | 1. **OR General** 6 | 2. **OR Tools** 7 | 3. **OR Flow** 8 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # EDA Corpus 2 | EDA Corpus is a data corpus for Electronic Design Automation (EDA) Large Language Model (LLM) research. In particular, the datapoints are tailored to [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD) and [OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). The corpus contains datasets for both question-answering and prompt-scripting for OpenROAD to improve user productivity. 3 | 4 | ## Background 5 | Recent works have shown that LLMs have tremendous potential in the chip design area in terms of writing code/script for hardware description language (HDL) or electronic design automation (EDA) flow. However, many of these works rely on data which are not publicly available and/or not permissively licensed for use in LLM training and distribution, especially in the EDA domain. To foster research in LLM-assisted physical design, we introduce EDA Corpus, a curated dataset for physical design automation tasks. EDA Corpus is based on OpenROAD, a widely utilized open-source EDA tool for automated place and route tasks. Leveraging OpenROAD mitigates obstacles associated with proprietary EDA tools, enabling the public release of our dataset and facilitating its use with LLMs without licensing constraints. 6 | 7 | ## Dataset Description 8 | EDA Corpus consists of two types of data: (1) question-answer (QA) pairs and (2) prompt-script (PS) pairs 9 | 10 | | **Dataset** | **Description** | **Non-augmented** | **Augmented**\* | 11 | |--------------------|-----------------|-------------------|-----------------| 12 | | `eda-corpus-qa-v1` | Question-answer | 198 data pairs | 590 data pairs | 13 | | `eda-corpus-ps-v1` | Prompt-script | 395 data pairs | 943 data pairs | 14 | | `eda-corpus-v1` | Combined QA/PS | 593 data pairs | 1533 data pairs | 15 | 16 | \* The augmented dataset is a superset of non-augmented 17 | 18 | ### Question-answer (QA) dataset 19 | - Contains pairs of question prompts and prose answers which are collected from The OpenROAD Project's GitHub issues, discussions, and documentation 20 | - Datapoints are categorized into three categories: OpenROAD general, OpenROAD tool, and OpenROAD flow 21 | - CSV file format and Microsoft Excel file format provided 22 | 23 | An example question-answer pair: 24 | **Question:** 25 | 26 | ***What does the SKIP_PIN_SWAP variable in Clock Tree Synthesis indicate?*** 27 | 28 | **Answer:** 29 | 30 | ***Do not use pin swapping as a transform to fix timing violations (default: use pin swapping)*** 31 | 32 | #### Augmentation 33 | The augmented dataset includes data pairs formed through paraphrasing questions and answers in order to enhance semantic diversity. 34 | 35 | ### Prompt-script (PS) dataset 36 | - Contains pairs of scripting prompts and OpenROAD Python scripts 37 | - Data points are categorized into two three categories: flow scripts and database (DB) scripts 38 | - CSV file format and Microsoft Excel file format provided 39 | 40 | While Tcl is the normal interface for OpenROAD, leveraging Python allows the reuse of pretrained LLMs for Python code generation. It is worth noting that Python code examples are significantly more prevalent, hence the focus on Python-based scripts. 41 | 42 | An example prompt-script pair: 43 | **Prompt:** 44 | 45 | ***Show me how I can read a Verilog file into OpenROAD.*** 46 | 47 | **Script:** 48 | 49 | #### Augmentation 50 | While each augmented datapoint is distinct, the augmented points may perform similar functions with script parameter variations. For instance, the augmented set has a few instances of gate sizing, and the sizing is different between datapoints. The data is augmented through two methods: 51 | 52 | 1. **Paraphrasing prompts**: prompts are paraphrased to increase semantic diversity. 53 | 2. **Variable and parameter changes**: pairs are duplicated with changes to the prompt parameters and script variable names. 54 | 55 | ```python 56 | from openroad import Tech, Design 57 | from pathlib import Path 58 | 59 | tech = Tech() 60 | # Make sure you have .lef files read into OpenROAD DB 61 | design = Design(tech) 62 | 63 | designDir = Path("design_path") 64 | design_file_name = "design_filename" 65 | design_top_module_name = "design_top_module_name" 66 | verilogFile = designDir/str(design_file_name + ".v") 67 | design.readVerilog("verilogFile") 68 | design.link(design_top_module_name) 69 | ``` 70 | 71 | # Citing This Work 72 | 73 | If you use this corpus in your work, please use the following citation: 74 | ``` 75 | @inproceedingsV{wu2024eda, 76 | title = {EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD}, 77 | author = {Wu, Bing-Yue and Sharma, Utsav and Kankipati, Sai Rahul Dhanvi and Yadav, Ajay and George, Bintu Kappil and Guntupalli, Sai Ritish and Rovinski, Austin and Chhabria, Vidya A.}, 78 | booktitle = {The First IEEE International Workshop on LLM-Aided Design (LAD'24)}, 79 | month = {June}, 80 | year = {2024}, 81 | organization = {IEEE}, 82 | address = {New York, NY} 83 | } 84 | ``` 85 | 86 | ## Taxonomy 87 | The question-answer and prompt-script data should be individually referred to as "datasets". The two dataset combined should be referred to as a "corpus". 88 | 89 | Citations to this work can be mentioned by `corpusName-datasetName-version`: 90 | 91 | | **Data** | **Name** | 92 | |------------------------------|--------------------| 93 | | All of EDA Corpus | `eda-corpus-v1` | 94 | | Only question-answer dataset | `eda-corpus-qa-v1` | 95 | | Only prompt-script dataset | `eda-corpus-ps-v1` | 96 | 97 | Additionally, you can mention whether you use the **augmented** or **non-augmented** versions. For example, "We train on the augmented eda-corpus-ps-v1 dataset." 98 | 99 | ## License 100 | [![CC BY 4.0][cc-by-shield]][cc-by] 101 | 102 | EDA Corpus is licensed under a [Creative Commons Attribution 4.0 International License][cc-by]. If you use EDA Corpus in a published scholarly work, please use the above citation. If you use EDA Corpus in another publication such as an article or blog post, please include a link to this repository. 103 | 104 | [![CC BY 4.0][cc-by-image]][cc-by] 105 | 106 | [cc-by]: http://creativecommons.org/licenses/by/4.0/ 107 | [cc-by-image]: https://i.creativecommons.org/l/by/4.0/88x31.png 108 | [cc-by-shield]: https://img.shields.io/badge/License-CC%20BY%204.0-lightgrey.svg 109 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Attribution 4.0 International 2 | 3 | ======================================================================= 4 | 5 | Creative Commons Corporation ("Creative Commons") is not a law firm and 6 | does not provide legal services or legal advice. Distribution of 7 | Creative Commons public licenses does not create a lawyer-client or 8 | other relationship. Creative Commons makes its licenses and related 9 | information available on an "as-is" basis. Creative Commons gives no 10 | warranties regarding its licenses, any material licensed under their 11 | terms and conditions, or any related information. Creative Commons 12 | disclaims all liability for damages resulting from their use to the 13 | fullest extent possible. 14 | 15 | Using Creative Commons Public Licenses 16 | 17 | Creative Commons public licenses provide a standard set of terms and 18 | conditions that creators and other rights holders may use to share 19 | original works of authorship and other material subject to copyright 20 | and certain other rights specified in the public license below. The 21 | following considerations are for informational purposes only, are not 22 | exhaustive, and do not form part of our licenses. 23 | 24 | Considerations for licensors: Our public licenses are 25 | intended for use by those authorized to give the public 26 | permission to use material in ways otherwise restricted by 27 | copyright and certain other rights. Our licenses are 28 | irrevocable. Licensors should read and understand the terms 29 | and conditions of the license they choose before applying it. 30 | Licensors should also secure all rights necessary before 31 | applying our licenses so that the public can reuse the 32 | material as expected. Licensors should clearly mark any 33 | material not subject to the license. This includes other CC- 34 | licensed material, or material used under an exception or 35 | limitation to copyright. More considerations for licensors: 36 | wiki.creativecommons.org/Considerations_for_licensors 37 | 38 | Considerations for the public: By using one of our public 39 | licenses, a licensor grants the public permission to use the 40 | licensed material under specified terms and conditions. If 41 | the licensor's permission is not necessary for any reason--for 42 | example, because of any applicable exception or limitation to 43 | copyright--then that use is not regulated by the license. Our 44 | licenses grant only permissions under copyright and certain 45 | other rights that a licensor has authority to grant. Use of 46 | the licensed material may still be restricted for other 47 | reasons, including because others have copyright or other 48 | rights in the material. A licensor may make special requests, 49 | such as asking that all changes be marked or described. 50 | Although not required by our licenses, you are encouraged to 51 | respect those requests where reasonable. More_considerations 52 | for the public: 53 | wiki.creativecommons.org/Considerations_for_licensees 54 | 55 | ======================================================================= 56 | 57 | Creative Commons Attribution 4.0 International Public License 58 | 59 | By exercising the Licensed Rights (defined below), You accept and agree 60 | to be bound by the terms and conditions of this Creative Commons 61 | Attribution 4.0 International Public License ("Public License"). To the 62 | extent this Public License may be interpreted as a contract, You are 63 | granted the Licensed Rights in consideration of Your acceptance of 64 | these terms and conditions, and the Licensor grants You such rights in 65 | consideration of benefits the Licensor receives from making the 66 | Licensed Material available under these terms and conditions. 67 | 68 | 69 | Section 1 -- Definitions. 70 | 71 | a. Adapted Material means material subject to Copyright and Similar 72 | Rights that is derived from or based upon the Licensed Material 73 | and in which the Licensed Material is translated, altered, 74 | arranged, transformed, or otherwise modified in a manner requiring 75 | permission under the Copyright and Similar Rights held by the 76 | Licensor. For purposes of this Public License, where the Licensed 77 | Material is a musical work, performance, or sound recording, 78 | Adapted Material is always produced where the Licensed Material is 79 | synched in timed relation with a moving image. 80 | 81 | b. Adapter's License means the license You apply to Your Copyright 82 | and Similar Rights in Your contributions to Adapted Material in 83 | accordance with the terms and conditions of this Public License. 84 | 85 | c. Copyright and Similar Rights means copyright and/or similar rights 86 | closely related to copyright including, without limitation, 87 | performance, broadcast, sound recording, and Sui Generis Database 88 | Rights, without regard to how the rights are labeled or 89 | categorized. For purposes of this Public License, the rights 90 | specified in Section 2(b)(1)-(2) are not Copyright and Similar 91 | Rights. 92 | 93 | d. Effective Technological Measures means those measures that, in the 94 | absence of proper authority, may not be circumvented under laws 95 | fulfilling obligations under Article 11 of the WIPO Copyright 96 | Treaty adopted on December 20, 1996, and/or similar international 97 | agreements. 98 | 99 | e. Exceptions and Limitations means fair use, fair dealing, and/or 100 | any other exception or limitation to Copyright and Similar Rights 101 | that applies to Your use of the Licensed Material. 102 | 103 | f. Licensed Material means the artistic or literary work, database, 104 | or other material to which the Licensor applied this Public 105 | License. 106 | 107 | g. Licensed Rights means the rights granted to You subject to the 108 | terms and conditions of this Public License, which are limited to 109 | all Copyright and Similar Rights that apply to Your use of the 110 | Licensed Material and that the Licensor has authority to license. 111 | 112 | h. Licensor means the individual(s) or entity(ies) granting rights 113 | under this Public License. 114 | 115 | i. Share means to provide material to the public by any means or 116 | process that requires permission under the Licensed Rights, such 117 | as reproduction, public display, public performance, distribution, 118 | dissemination, communication, or importation, and to make material 119 | available to the public including in ways that members of the 120 | public may access the material from a place and at a time 121 | individually chosen by them. 122 | 123 | j. Sui Generis Database Rights means rights other than copyright 124 | resulting from Directive 96/9/EC of the European Parliament and of 125 | the Council of 11 March 1996 on the legal protection of databases, 126 | as amended and/or succeeded, as well as other essentially 127 | equivalent rights anywhere in the world. 128 | 129 | k. You means the individual or entity exercising the Licensed Rights 130 | under this Public License. Your has a corresponding meaning. 131 | 132 | 133 | Section 2 -- Scope. 134 | 135 | a. License grant. 136 | 137 | 1. Subject to the terms and conditions of this Public License, 138 | the Licensor hereby grants You a worldwide, royalty-free, 139 | non-sublicensable, non-exclusive, irrevocable license to 140 | exercise the Licensed Rights in the Licensed Material to: 141 | 142 | a. reproduce and Share the Licensed Material, in whole or 143 | in part; and 144 | 145 | b. produce, reproduce, and Share Adapted Material. 146 | 147 | 2. Exceptions and Limitations. For the avoidance of doubt, where 148 | Exceptions and Limitations apply to Your use, this Public 149 | License does not apply, and You do not need to comply with 150 | its terms and conditions. 151 | 152 | 3. Term. The term of this Public License is specified in Section 153 | 6(a). 154 | 155 | 4. Media and formats; technical modifications allowed. The 156 | Licensor authorizes You to exercise the Licensed Rights in 157 | all media and formats whether now known or hereafter created, 158 | and to make technical modifications necessary to do so. The 159 | Licensor waives and/or agrees not to assert any right or 160 | authority to forbid You from making technical modifications 161 | necessary to exercise the Licensed Rights, including 162 | technical modifications necessary to circumvent Effective 163 | Technological Measures. For purposes of this Public License, 164 | simply making modifications authorized by this Section 2(a) 165 | (4) never produces Adapted Material. 166 | 167 | 5. Downstream recipients. 168 | 169 | a. Offer from the Licensor -- Licensed Material. Every 170 | recipient of the Licensed Material automatically 171 | receives an offer from the Licensor to exercise the 172 | Licensed Rights under the terms and conditions of this 173 | Public License. 174 | 175 | b. No downstream restrictions. You may not offer or impose 176 | any additional or different terms or conditions on, or 177 | apply any Effective Technological Measures to, the 178 | Licensed Material if doing so restricts exercise of the 179 | Licensed Rights by any recipient of the Licensed 180 | Material. 181 | 182 | 6. No endorsement. Nothing in this Public License constitutes or 183 | may be construed as permission to assert or imply that You 184 | are, or that Your use of the Licensed Material is, connected 185 | with, or sponsored, endorsed, or granted official status by, 186 | the Licensor or others designated to receive attribution as 187 | provided in Section 3(a)(1)(A)(i). 188 | 189 | b. Other rights. 190 | 191 | 1. Moral rights, such as the right of integrity, are not 192 | licensed under this Public License, nor are publicity, 193 | privacy, and/or other similar personality rights; however, to 194 | the extent possible, the Licensor waives and/or agrees not to 195 | assert any such rights held by the Licensor to the limited 196 | extent necessary to allow You to exercise the Licensed 197 | Rights, but not otherwise. 198 | 199 | 2. Patent and trademark rights are not licensed under this 200 | Public License. 201 | 202 | 3. To the extent possible, the Licensor waives any right to 203 | collect royalties from You for the exercise of the Licensed 204 | Rights, whether directly or through a collecting society 205 | under any voluntary or waivable statutory or compulsory 206 | licensing scheme. In all other cases the Licensor expressly 207 | reserves any right to collect such royalties. 208 | 209 | 210 | Section 3 -- License Conditions. 211 | 212 | Your exercise of the Licensed Rights is expressly made subject to the 213 | following conditions. 214 | 215 | a. Attribution. 216 | 217 | 1. If You Share the Licensed Material (including in modified 218 | form), You must: 219 | 220 | a. retain the following if it is supplied by the Licensor 221 | with the Licensed Material: 222 | 223 | i. identification of the creator(s) of the Licensed 224 | Material and any others designated to receive 225 | attribution, in any reasonable manner requested by 226 | the Licensor (including by pseudonym if 227 | designated); 228 | 229 | ii. a copyright notice; 230 | 231 | iii. a notice that refers to this Public License; 232 | 233 | iv. a notice that refers to the disclaimer of 234 | warranties; 235 | 236 | v. a URI or hyperlink to the Licensed Material to the 237 | extent reasonably practicable; 238 | 239 | b. indicate if You modified the Licensed Material and 240 | retain an indication of any previous modifications; and 241 | 242 | c. indicate the Licensed Material is licensed under this 243 | Public License, and include the text of, or the URI or 244 | hyperlink to, this Public License. 245 | 246 | 2. You may satisfy the conditions in Section 3(a)(1) in any 247 | reasonable manner based on the medium, means, and context in 248 | which You Share the Licensed Material. For example, it may be 249 | reasonable to satisfy the conditions by providing a URI or 250 | hyperlink to a resource that includes the required 251 | information. 252 | 253 | 3. If requested by the Licensor, You must remove any of the 254 | information required by Section 3(a)(1)(A) to the extent 255 | reasonably practicable. 256 | 257 | 4. If You Share Adapted Material You produce, the Adapter's 258 | License You apply must not prevent recipients of the Adapted 259 | Material from complying with this Public License. 260 | 261 | 262 | Section 4 -- Sui Generis Database Rights. 263 | 264 | Where the Licensed Rights include Sui Generis Database Rights that 265 | apply to Your use of the Licensed Material: 266 | 267 | a. for the avoidance of doubt, Section 2(a)(1) grants You the right 268 | to extract, reuse, reproduce, and Share all or a substantial 269 | portion of the contents of the database; 270 | 271 | b. if You include all or a substantial portion of the database 272 | contents in a database in which You have Sui Generis Database 273 | Rights, then the database in which You have Sui Generis Database 274 | Rights (but not its individual contents) is Adapted Material; and 275 | 276 | c. You must comply with the conditions in Section 3(a) if You Share 277 | all or a substantial portion of the contents of the database. 278 | 279 | For the avoidance of doubt, this Section 4 supplements and does not 280 | replace Your obligations under this Public License where the Licensed 281 | Rights include other Copyright and Similar Rights. 282 | 283 | 284 | Section 5 -- Disclaimer of Warranties and Limitation of Liability. 285 | 286 | a. UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE 287 | EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS 288 | AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF 289 | ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, 290 | IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, 291 | WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR 292 | PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, 293 | ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT 294 | KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT 295 | ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. 296 | 297 | b. TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE 298 | TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, 299 | NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, 300 | INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, 301 | COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR 302 | USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN 303 | ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR 304 | DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR 305 | IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. 306 | 307 | c. The disclaimer of warranties and limitation of liability provided 308 | above shall be interpreted in a manner that, to the extent 309 | possible, most closely approximates an absolute disclaimer and 310 | waiver of all liability. 311 | 312 | 313 | Section 6 -- Term and Termination. 314 | 315 | a. This Public License applies for the term of the Copyright and 316 | Similar Rights licensed here. However, if You fail to comply with 317 | this Public License, then Your rights under this Public License 318 | terminate automatically. 319 | 320 | b. Where Your right to use the Licensed Material has terminated under 321 | Section 6(a), it reinstates: 322 | 323 | 1. automatically as of the date the violation is cured, provided 324 | it is cured within 30 days of Your discovery of the 325 | violation; or 326 | 327 | 2. upon express reinstatement by the Licensor. 328 | 329 | For the avoidance of doubt, this Section 6(b) does not affect any 330 | right the Licensor may have to seek remedies for Your violations 331 | of this Public License. 332 | 333 | c. For the avoidance of doubt, the Licensor may also offer the 334 | Licensed Material under separate terms or conditions or stop 335 | distributing the Licensed Material at any time; however, doing so 336 | will not terminate this Public License. 337 | 338 | d. Sections 1, 5, 6, 7, and 8 survive termination of this Public 339 | License. 340 | 341 | 342 | Section 7 -- Other Terms and Conditions. 343 | 344 | a. The Licensor shall not be bound by any additional or different 345 | terms or conditions communicated by You unless expressly agreed. 346 | 347 | b. Any arrangements, understandings, or agreements regarding the 348 | Licensed Material not stated herein are separate from and 349 | independent of the terms and conditions of this Public License. 350 | 351 | 352 | Section 8 -- Interpretation. 353 | 354 | a. For the avoidance of doubt, this Public License does not, and 355 | shall not be interpreted to, reduce, limit, restrict, or impose 356 | conditions on any use of the Licensed Material that could lawfully 357 | be made without permission under this Public License. 358 | 359 | b. To the extent possible, if any provision of this Public License is 360 | deemed unenforceable, it shall be automatically reformed to the 361 | minimum extent necessary to make it enforceable. If the provision 362 | cannot be reformed, it shall be severed from this Public License 363 | without affecting the enforceability of the remaining terms and 364 | conditions. 365 | 366 | c. No term or condition of this Public License will be waived and no 367 | failure to comply consented to unless expressly agreed to by the 368 | Licensor. 369 | 370 | d. Nothing in this Public License constitutes or may be interpreted 371 | as a limitation upon, or waiver of, any privileges and immunities 372 | that apply to the Licensor or You, including from the legal 373 | processes of any jurisdiction or authority. 374 | 375 | 376 | ======================================================================= 377 | 378 | Creative Commons is not a party to its public 379 | licenses. Notwithstanding, Creative Commons may elect to apply one of 380 | its public licenses to material it publishes and in those instances 381 | will be considered the “Licensor.” The text of the Creative Commons 382 | public licenses is dedicated to the public domain under the CC0 Public 383 | Domain Dedication. Except for the limited purpose of indicating that 384 | material is shared under a Creative Commons public license or as 385 | otherwise permitted by the Creative Commons policies published at 386 | creativecommons.org/policies, Creative Commons does not authorize the 387 | use of the trademark "Creative Commons" or any other trademark or logo 388 | of Creative Commons without its prior written consent including, 389 | without limitation, in connection with any unauthorized modifications 390 | to any of its public licenses or any other arrangements, 391 | understandings, or agreements concerning use of licensed material. For 392 | the avoidance of doubt, this paragraph does not form part of the 393 | public licenses. 394 | 395 | Creative Commons may be contacted at creativecommons.org. 396 | -------------------------------------------------------------------------------- /Augmented_Data/Question-Answer/Flow/Flow.csv: -------------------------------------------------------------------------------- 1 | Prompts,Answers 2 | Brief me on OpenROAD Flow?,"OpenROAD-flow-scripts (ORFS) is a fully autonomous, RTL-GDSII flow for rapid architecture and design space exploration, early prediction of QoR, and detailed physical design implementation. However, ORFS also enables manual intervention for finer user control of individual flow stages through Tcl commands and Python APIs." 3 | What is OpenROAD Flow and its benefits?,"OpenROAD-flow-scripts (ORFS) is a fully autonomous, RTL-GDSII flow for rapid architecture and design space exploration, early prediction of QoR, and detailed physical design implementation. However, ORFS also enables manual intervention for finer user control of individual flow stages through Tcl commands and Python APIs." 4 | Brief me on OpenROAD Flow?,"OpenROAD-flow-scripts offer a comprehensive, autonomous RTL-GDSII flow for rapid design exploration and physical design, allowing for manual intervention at stages through Tcl commands and Python APIs for greater control." 5 | "I'm trying to port ORFS to a TSMC process. During the detailed route step, I get a lot of DRT-0073 errors. Utilization is set to 20% at the beginning of the P&R flow and it is a pretty simple design. Give me some tips about what to look into? 6 | I have tried to run the pin_access command directly but the -verbose parameter does not seem to work as I don't get any more information","You can try the developer debugs to get a sense of what is going on. Put detailed_route_debug -pa -pa_markers -pin _3504_:A1 before you call detailed_route and run it in the GUI. It will stop at the pin and show you how it is trying to access it and any associated drc markers. You click the continue button to see the various steps. Hopefully, that gives you an idea as to what is going on. The other option is a support contract with precisioninno.com where we can help under NDA. 7 | " 8 | I'm encountering DRT-0073 errors during detailed routing in ORFS; any advice?,"You can try the developer debugs to get a sense of what is going on. Put detailed_route_debug -pa -pa_markers -pin _3504_:A1 before you call detailed_route and run it in the GUI. It will stop at the pin and show you how it is trying to access it and any associated drc markers. You click the continue button to see the various steps. Hopefully, that gives you an idea as to what is going on. The other option is a support contract with precisioninno.com where we can help under NDA. 9 | " 10 | "I'm trying to port ORFS to a TSMC process. During the detailed route step, I get a lot of DRT-0073 errors. Utilization is set to 20% at the beginning of the P&R flow and it is a pretty simple design. Give me some tips about what to look into? 11 | I have tried to run the pin_access command directly but the -verbose parameter does not seem to work as I don't get any more information","Developer debug options in OpenROAD can give insights into detailed routing processes, offering visual debug aids in the GUI and the option for NDA-supported assistance from precisioninno.com." 12 | What does the following argument do in the build command of ORFS: -o or —local?,"The argument, o or —local, builds locally instead of building a Docker image." 13 | How does the -o or —local argument function in the build command of ORFS?,"The argument, o or —local, builds locally instead of building a Docker image." 14 | What does the following argument do in the build command of ORFS: -o or —local?,The -o or --local argument opts for a local build over Docker. 15 | What operation does the -l or --latest argument perform in the build command of ORFS?,The -l or --latest argument specifies to use of the head of branch –or_branch or ‘master’ by default for tools/OpenROAD. 16 | What is accomplished by the -l or --latest argument in the build command of ORFS?,The -l or --latest argument specifies to use of the head of branch –or_branch or ‘master’ by default for tools/OpenROAD. 17 | What operation does the -l or --latest argument perform in the build command of ORFS?,"The -l or --latest argument chooses the latest branch head for tools/OpenROAD, defaulting to master." 18 | How is this argument utilized in the build command of ORFS: --or_branch BRANCH_NAME?,The -or_branch BRANCH_NAME argument stipulates the use of the head of branch BRANCH for tools/OpenROAD. 19 | How is the --or_branch BRANCH_NAME argument used in the build command of ORFS?,The -or_branch BRANCH_NAME argument stipulates the use of the head of branch BRANCH for tools/OpenROAD. 20 | How is this argument utilized in the build command of ORFS: --or_branch BRANCH_NAME?,The -or_branch BRANCH_NAME argument selects the branch head of BRANCH for tools/OpenROAD. 21 | What role does this argument play in the build command of ORFS: --or_repo REPO_URL?, This argument enumerates to use of a fork at REPO-URL (https/ssh) for tools/OpenROAD. 22 | What does the --or_repo REPO_URL argument specify in the build command of ORFS?, This argument enumerates to use of a fork at REPO-URL (https/ssh) for tools/OpenROAD. 23 | What role does this argument play in the build command of ORFS: --or_repo REPO_URL?,Specifies using a tools/OpenROAD fork at a given REPO-URL. 24 | What does the following argument do in the build command of ORFS: --no_init?,The --no_init argument prescribes skipping initializing submodules. 25 | What does the --no_init argument accomplish in the build command of ORFS?,The --no_init argument prescribes skipping initializing submodules. 26 | What does the following argument do in the build command of ORFS: --no_init?,The --no_init option omits submodule initialization. 27 | How does the following argument function in the build command of ORFS: -t N or --threads N?,The -t N or --threads N argument stipulates the use of N cpus when compiling software. 28 | What does the -t N or --threads N argument control in the build command of ORFS?,The -t N or --threads N argument stipulates the use of N cpus when compiling software. 29 | How does the following argument function in the build command of ORFS: -t N or --threads N?,The -t N or --threads N argument utilizes N CPUs for software compilation. 30 | What is the purpose of the following argument in the build command of ORFS: -n or --nice?,"The -n or --nice flag in the build script instructs the build script to set all jobs to the maximim Unix ""niceness"". Niceness determines how much the operating system prefers to schedule process. The purpose of setting this flag is to ensure that a system is not overwhelmed by using all available processing primarily of the build jobs. The build will use all CPUs by default unless --threads is also given, then N threads are used instead." 31 | What is the purpose of the -n or --nice argument in the build command of ORFS?,"The -n or --nice flag in the build script instructs the build script to set all jobs to the maximim Unix ""niceness"". Niceness determines how much the operating system prefers to schedule process. The purpose of setting this flag is to ensure that a system is not overwhelmed by using all available processing primarily of the build jobs. The build will use all CPUs by default unless --threads is also given, then N threads are used instead." 32 | What is the purpose of the following argument in the build command of ORFS: -n or --nice?,"The build script's -n or --nice flag sets all jobs to the maximum Unix ""niceness"" level. This determines the priority with which the operating system schedules processes. The aim is to prevent system overload by allocating all processing power primarily to the build jobs. Without specifying otherwise, the build utilizes all CPUs, but specifying --threads allows for the use of a fixed number of threads." 33 | What does the following argument do in the build command of ORFS: —yosys-args-overwrite?,This argument states to not use default flags set by this scrip during Yosys compilation. 34 | What does the --yosys-args-overwrite argument modify in the build command of ORFS?,This argument states to not use default flags set by this scrip during Yosys compilation. 35 | What does the following argument do in the build command of ORFS: —yosys-args-overwrite?,This parameter instructs the script to ignore the default flags during Yosys compilation. 36 | What is the purpose of the following argument in the build command of ORFS: —yosys-args STRING?,The '—yosys-args STRING' argument adds additional compilation flags for Yosys compilation. 37 | How does the --yosys-args STRING argument customize the build process in ORFS?,The '—yosys-args STRING' argument adds additional compilation flags for Yosys compilation. 38 | What is the purpose of the following argument in the build command of ORFS: —yosys-args STRING?,The '--yosys-args STRING' option allows for the inclusion of extra flags in Yosys compilations. 39 | What function does the following argument serve in the build command of ORFS: —openroad-args-overwrite?,The '—openroad-args-overwrite' argument specifies to not use default flags set by this script during OpenROAD app compilation. 40 | What modification does the --openroad-args-overwrite argument make in the build command of ORFS?,The '—openroad-args-overwrite' argument specifies to not use default flags set by this script during OpenROAD app compilation. 41 | What function does the following argument serve in the build command of ORFS: —openroad-args-overwrite?,The '--openroad-args-overwrite' option commands the script not to apply its default flags during OpenROAD app compilations. 42 | What does the following argument do in the build command of ORFS: —openroad-args STRING?,The '—openroad-args STRING' argument adds aditional compilation flags for OpenROAD app compilation. 43 | How does the --openroad-args STRING argument alter the build process in ORFS?,The '—openroad-args STRING' argument adds aditional compilation flags for OpenROAD app compilation. 44 | What does the following argument do in the build command of ORFS: —openroad-args STRING?,The '--openroad-args STRING' option introduces additional flags for compiling the OpenROAD app. 45 | What is the purpose of the following argument in the build command of ORFS: —lsoracle-enable?,This argument initiates compiling LSOracle since it is disabled by default as it is not currently used on the flow. 46 | What is the function of the --lsoracle-enable argument in the build command of ORFS?,This argument initiates compiling LSOracle since it is disabled by default as it is not currently used on the flow. 47 | What is the purpose of the following argument in the build command of ORFS: —lsoracle-enable?,"Activates the compilation of LSOracle, which is off by default as it's not part of the current workflow." 48 | What does the following argument do in the build command of ORFS: —lsoracle-args-overwrite?,The '—lsoracle-args-overwrite' argument stipulates not to use default flags set by this script during LSOracle compilation. 49 | What does the --lsoracle-args-overwrite argument change in the build command of ORFS?,The '—lsoracle-args-overwrite' argument stipulates not to use default flags set by this script during LSOracle compilation. 50 | What does the following argument do in the build command of ORFS: —lsoracle-args-overwrite?,The '--lsoracle-args-overwrite' command directs the script to bypass default flags for LSOracle compilations. 51 | What does the following argument achieve in the build command of ORFS: —lsoracle-args STRING?,This argument adds aditional compilation flags for LSOracle compilation. 52 | How does the --lsoracle-args STRING argument customize the ORFS build process?,This argument adds aditional compilation flags for LSOracle compilation. 53 | What does the following argument achieve in the build command of ORFS: —lsoracle-args STRING?,This command introduces extra compilation flags for LSOracle. 54 | What function does the following argument serve in the build command of ORFS: —install-path PATH?,The '—install-path PATH' delineates the path to install tools. Default is ${INSTALL_PATH}. 55 | What does the --install-path PATH argument specify in the build command of ORFS?,The '—install-path PATH' delineates the path to install tools. Default is ${INSTALL_PATH}. 56 | What function does the following argument serve in the build command of ORFS: —install-path PATH?,"The '--install-path PATH' option specifies the installation directory for tools, with ${INSTALL_PATH} as the default." 57 | What does the following argument do in the build command of ORFS: —clean?,The '—clean' argument calls the git clean command interactively before compiling. It is useful to remove old build files. 58 | What is achieved by the --clean argument in the build command of ORFS?,The '—clean' argument calls the git clean command interactively before compiling. It is useful to remove old build files. 59 | What does the following argument do in the build command of ORFS: —clean?,"The '--clean' argument triggers an interactive git clean command before compiling, helping remove outdated build files." 60 | What does the following argument do in the build command of ORFS: —clean-force?,This '—clean-force' argument will call git clean before compiling but WARNING: this option will not ask for confirmation. It is useful to remove old build files. 61 | How does the --clean-force argument function in the build command of ORFS?,This '—clean-force' argument will call git clean before compiling but WARNING: this option will not ask for confirmation. It is useful to remove old build files. 62 | What does the following argument do in the build command of ORFS: —clean-force?,"The '--clean-force' command enforces a git clean operation before compilation without seeking user confirmation, aiding in the deletion of old build files." 63 | What function does the following argument serve in the build command of ORFS: -c or --copy-platforms?,This argument is only applicable to docker builds. It is used to copy platforms inside the docker image. 64 | What does the -c or --copy-platforms argument do in the build command of ORFS?,This argument is only applicable to docker builds. It is used to copy platforms inside the docker image. 65 | What function does the following argument serve in the build command of ORFS: -c or --copy-platforms?,"This command is tailored for docker builds, enabling the copying of platforms into the docker image." 66 | What does the following argument do in the build command of ORFS: —docker-args-overwrite?,The ' —docker-args-overwrite' argument is only applicable for docker builds. They specify to not use default flags set by this script for Docker builds. 67 | What modification does the --docker-args-overwrite argument make in the build command of ORFS?,The ' —docker-args-overwrite' argument is only applicable for docker builds. They specify to not use default flags set by this script for Docker builds. 68 | What does the following argument do in the build command of ORFS: —docker-args-overwrite?,"The '--docker-args-overwrite' command is designated for docker builds, instructing not to use the script's default Docker build flags." 69 | What does the following argument do in the build command of ORFS: —docker-args STRING?,This argument is only applicable to docker builds. It is used to add additional compilation flags for the Docker build. 70 | How does the --docker-args STRING argument customize the ORFS build process?,This argument is only applicable to docker builds. It is used to add additional compilation flags for the Docker build. 71 | What does the following argument do in the build command of ORFS: —docker-args STRING?,"This command, specific to docker builds, allows adding extra compilation flags for Docker builds." 72 | "What does the following Synthesis variable, SYNTH_HIERARCHICAL do?","The variable SYNTH_HIERARCHICAL enables synthesis hierarchically, otherwise considered flat synthesis." 73 | What does the SYNTH_HIERARCHICAL variable in Synthesis control?,"The variable SYNTH_HIERARCHICAL enables synthesis hierarchically, otherwise considered flat synthesis." 74 | "What does the following Synthesis variable, SYNTH_HIERARCHICAL do?",SYNTH_HIERARCHICAL toggles between hierarchical and flat synthesis. 75 | "What does the following Synthesis variable, LATCH_MAP_FILE do?",LATCH_MAP_FILE variable specifies the list of latches treated as a black box by Yosys. 76 | What is the purpose of the LATCH_MAP_FILE variable in Synthesis?,LATCH_MAP_FILE variable specifies the list of latches treated as a black box by Yosys. 77 | "What does the following Synthesis variable, LATCH_MAP_FILE do?",LATCH_MAP_FILE lists latches considered as black boxes by Yosys. 78 | "What does the following Synthesis variable, CLKGATE_MAP_FILE do?",This variable specifies a list of cells for the gating clock treated as a black box by Yosys. 79 | How does the CLKGATE_MAP_FILE variable in Synthesis function?,This variable specifies a list of cells for the gating clock treated as a black box by Yosys. 80 | "What does the following Synthesis variable, CLKGATE_MAP_FILE do?",Specifies cells to treat as black boxes for clock gating in Yosys. 81 | "Can you explain the usage of this Synthesis variable, ADDER_MAP_FILE?",List of adders treated as a black box by Yosys. 82 | What does the ADDER_MAP_FILE variable in Synthesis specify?,List of adders treated as a black box by Yosys. 83 | "Can you explain the usage of this Synthesis variable, ADDER_MAP_FILE?",Lists adders treated as black boxes by Yosys. 84 | "What does the following Synthesis variable, TIEHI_CELL_AND_PORT do?","The variable, TIEHI_CELL_AND_PORT is used to tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist." 85 | What does the TIEHI_CELL_AND_PORT variable in Synthesis define?,"The variable, TIEHI_CELL_AND_PORT is used to tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist." 86 | "What does the following Synthesis variable, TIEHI_CELL_AND_PORT do?",TIEHI_CELL_AND_PORT identifies high tie cells used in Yosys synthesis to replace logical 1 in the Netlist. 87 | "What does the following Synthesis variable, TIELO_CELL_AND_PORT do?",This variable is used to tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. 88 | What does the TIELO_CELL_AND_PORT variable in Synthesis indicate?,This variable is used to tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. 89 | "What does the following Synthesis variable, TIELO_CELL_AND_PORT do?",Defines low tie cells used in Yosys synthesis to replace logical 0 in the Netlist. 90 | "What does the following Synthesis variable, MIN_BUF_CELL_AND_PORTS do?",The MIN_BUF_CELL_AND_PORTS variable is used to insert a buffer cell to pass through wires. Used in synthesis. 91 | How does the MIN_BUF_CELL_AND_PORTS variable in Synthesis operate?,The MIN_BUF_CELL_AND_PORTS variable is used to insert a buffer cell to pass through wires. Used in synthesis. 92 | "What does the following Synthesis variable, MIN_BUF_CELL_AND_PORTS do?","MIN_BUF_CELL_AND_PORTS inserts a buffer cell for wire pass-through, used in synthesis." 93 | "What does the following Synthesis variable, ABC_CLOCK_PERIOD_IN_PS do?","The variable, ABC_CLOCK_PERIOD_IN_PS is used to specify the clock period to be used by STA during synthesis. Default value read from constraint.sdc." 94 | What does the ABC_CLOCK_PERIOD_IN_PS variable in Synthesis determine?,"The variable, ABC_CLOCK_PERIOD_IN_PS is used to specify the clock period to be used by STA during synthesis. Default value read from constraint.sdc." 95 | "What does the following Synthesis variable, ABC_CLOCK_PERIOD_IN_PS do?","ABC_CLOCK_PERIOD_IN_PS sets the clock period for STA during synthesis, with a default from constraint.sdc." 96 | "What does the following Synthesis variable, ABC_DRIVER_CELL do?",Default driver cell used during ABC synthesis. 97 | What does the ABC_DRIVER_CELL variable in Synthesis specify?,Default driver cell used during ABC synthesis. 98 | "What does the following Synthesis variable, ABC_DRIVER_CELL do?",Specifies the default driver cell for ABC synthesis. 99 | "What does the following Synthesis variable, ABC_LOAD_IN_FF do?","During synthesis, the set_load value specified by this, ABC_LOAD_IN_FF variable is used." 100 | What does the ABC_LOAD_IN_FF variable in Synthesis imply?,"During synthesis, the set_load value specified by this, ABC_LOAD_IN_FF variable is used." 101 | "What does the following Synthesis variable, ABC_LOAD_IN_FF do?",ABC_LOAD_IN_FF sets the load value during synthesis. 102 | "What does the following Synthesis variable, MAX_UNGROUP_SIZE do?","For hierarchical synthesis, this variable ungroups modules of the size given by this variable." 103 | What does the MAX_UNGROUP_SIZE variable in Synthesis control?,"For hierarchical synthesis, this variable ungroups modules of the size given by this variable." 104 | "What does the following Synthesis variable, MAX_UNGROUP_SIZE do?","For hierarchical synthesis, ungroups modules based on specified size." 105 | "Tell me about the Floorplan variable, FLOORPLAN_DEF?",FLOORPLAN_DEF is used to specify the use of the DEF file to initialize floorplan. 106 | Can you explain the FLOORPLAN_DEF variable in Floorplan?,FLOORPLAN_DEF is used to specify the use of the DEF file to initialize floorplan. 107 | "Tell me about the Floorplan variable, FLOORPLAN_DEF?",FLOORPLAN_DEF uses a DEF file to initialize the floorplan. 108 | "Elaborate on the Floorplan variable, PLACE_SITE?",Placement site for core cells defined in the technology LEF file. 109 | What is the role of the PLACE_SITE variable in Floorplan?,Placement site for core cells defined in the technology LEF file. 110 | "Elaborate on the Floorplan variable, PLACE_SITE?",Defines the placement site for core cells in the technology LEF file. 111 | "Describe the use this Floorplan variable, TAPCELL_TCL?",TAPCELL_TCL specifies the path to the Endcap and Welltie cells file. 112 | How does the TAPCELL_TCL variable in Floorplan function?,TAPCELL_TCL specifies the path to the Endcap and Welltie cells file. 113 | "Describe the use this Floorplan variable, TAPCELL_TCL?",TAPCELL_TCL points to the Endcap and Welltie cells file. 114 | "What is the function of the Floorplan variable, RTLMP_FLOW?","This variable, RTLMP_FLOW enables the Hierarchical RTLMP flow. By default it is disabled." 115 | What does the RTLMP_FLOW variable in Floorplan control?,"This variable, RTLMP_FLOW enables the Hierarchical RTLMP flow. By default it is disabled." 116 | "What is the function of the Floorplan variable, RTLMP_FLOW?","RTLMP_FLOW toggles the Hierarchical RTLMP flow, defaulting to off." 117 | "Tell me about the Floorplan variable, MACRO_HALO?","MACRO_HALO specifies to keep out a distance from macro, in X and Y, to standard cell row." 118 | Can you describe the MACRO_HALO variable in Floorplan?,"MACRO_HALO specifies to keep out a distance from macro, in X and Y, to standard cell row." 119 | "Tell me about the Floorplan variable, MACRO_HALO?",MACRO_HALO sets the keep-out distance around macros in X and Y to standard cell rows. 120 | "Tell me about the Floorplan variable, MACRO_PLACEMENT?",MACRO_PLACEMENT specifies the path of a file on how to place certain macros manually using read_macro_placement. 121 | What does the MACRO_PLACEMENT variable in Floorplan specify?,MACRO_PLACEMENT specifies the path of a file on how to place certain macros manually using read_macro_placement. 122 | "Tell me about the Floorplan variable, MACRO_PLACEMENT?",MACRO_PLACEMENT defines manual macro placement through a specified file. 123 | "Elaborate on the Floorplan variable, MACRO_PLACEMENT_TCL?",This variable specifies the path of a TCL file on how to place certain macros manually. 124 | How does the MACRO_PLACEMENT_TCL variable in Floorplan operate?,This variable specifies the path of a TCL file on how to place certain macros manually. 125 | "Elaborate on the Floorplan variable, MACRO_PLACEMENT_TCL?",Specifies a TCL file for manual macro placement. 126 | "Describe the Floorplan variable, MACRO_PLACE_HALO?",Horizontal /vertical halo around macros (microns). Used by automatic macro placement. 127 | What does the MACRO_PLACE_HALO variable in Floorplan indicate?,Horizontal /vertical halo around macros (microns). Used by automatic macro placement. 128 | "Describe the Floorplan variable, MACRO_PLACE_HALO?","Sets the halo around macros for automatic placement, in microns." 129 | "Tell me about the Floorplan variable, MACRO_PLACE_CHANNEL?",Horizontal/vertical channel width between macros (microns). Used by automatic macro placement when RTLMP_FLOW is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. 130 | What does the MACRO_PLACE_CHANNEL variable in Floorplan define?,Horizontal/vertical channel width between macros (microns). Used by automatic macro placement when RTLMP_FLOW is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. 131 | "Tell me about the Floorplan variable, MACRO_PLACE_CHANNEL?","Determines the channel width between macros for automatic placement, in microns." 132 | "Give me details on the Floorplan variable, MACRO_BLOCKAGE_HALO?",Blockage width overridden from default calculation. 133 | Can you detail the MACRO_BLOCKAGE_HALO variable in Floorplan?,Blockage width overridden from default calculation. 134 | "Give me details on the Floorplan variable, MACRO_BLOCKAGE_HALO?",Overrides the default blockage width calculation. 135 | "Inform me about the Floorplan variable, PDN_TCL?","This variable specifies the file path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps." 136 | What is the purpose of the PDN_TCL variable in Floorplan?,"This variable specifies the file path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps." 137 | "Inform me about the Floorplan variable, PDN_TCL?",Specifies the file path for power grid policies used by pdn. 138 | "Tell me about the Floorplan variable, MAKE_TRACKS.",MAKE_TRACKS variable outlines the Tcl file that defines adding routing tracks to a floorplan. 139 | How does the MAKE_TRACKS variable in Floorplan function?,MAKE_TRACKS variable outlines the Tcl file that defines adding routing tracks to a floorplan. 140 | "Tell me about the Floorplan variable, MAKE_TRACKS.",MAKE_TRACKS outlines a Tcl file for adding routing tracks to a floorplan. 141 | "What is the function of the Floorplan variable, IO_PLACER_H?",The metal layer on which to place the I/O pins horizontally (top and bottom of the die). 142 | What does the IO_PLACER_H variable in Floorplan specify?,The metal layer on which to place the I/O pins horizontally (top and bottom of the die). 143 | "What is the function of the Floorplan variable, IO_PLACER_H?",Specifies the metal layer for horizontal I/O pin placement. 144 | "Inform me about the Floorplan variable, IO_PLACER_V?",The metal layer on which to place the I/O pins vertically (sides of the die). 145 | How does the IO_PLACER_V variable in Floorplan operate?,The metal layer on which to place the I/O pins vertically (sides of the die). 146 | "Inform me about the Floorplan variable, IO_PLACER_V?",Specifies the metal layer for vertical I/O pin placement. 147 | "Tell me about the Floorplan variable, GUI_NO_TIMING?",Skip loading timing for a faster GUI load. 148 | What does the GUI_NO_TIMING variable in Floorplan control?,Skip loading timing for a faster GUI load. 149 | "Tell me about the Floorplan variable, GUI_NO_TIMING?",Skips loading timing for faster GUI loading. 150 | "Give me a description for the following ‘Placement’ tool variable, HAS_IO_CONSTRAINTS?",Skip the initial non-IO based global placement if IO constraints are present. 151 | Can you describe the HAS_IO_CONSTRAINTS variable in the Placement tool?,Skip the initial non-IO based global placement if IO constraints are present. 152 | "Give me a description for the following ‘Placement’ tool variable, HAS_IO_CONSTRAINTS?",Skips initial non-IO based global placement if IO constraints exist. 153 | "Tell me about the ‘Placement’ tool variable, CELL_PAD_IN_SITES_GLOBAL_PLACEMENT?",Cell padding on both sides in site widths to ease routability during global placement. 154 | What does the CELL_PAD_IN_SITES_GLOBAL_PLACEMENT variable in Placement do?,Cell padding on both sides in site widths to ease routability during global placement. 155 | "Tell me about the ‘Placement’ tool variable, CELL_PAD_IN_SITES_GLOBAL_PLACEMENT?",Defines cell padding in site widths for global placement routability. 156 | "What does this ‘Placement’ tool variable, CELL_PAD_IN_SITES_DETAIL_PLACEMENT do?",Cell padding on both sides in site widths to ease routability in detail placement. 157 | How does the CELL_PAD_IN_SITES_DETAIL_PLACEMENT variable in Placement function?,Cell padding on both sides in site widths to ease routability in detail placement. 158 | "What does this ‘Placement’ tool variable, CELL_PAD_IN_SITES_DETAIL_PLACEMENT do?",Defines cell padding in site widths for detail placement routability. 159 | "Give me a description for the following ‘Placement’ tool variable, PLACE_DENSITY?",The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread. 160 | What does the PLACE_DENSITY variable in Placement control?,The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread. 161 | "Give me a description for the following ‘Placement’ tool variable, PLACE_DENSITY?",Sets the desired placement density of cells on the core area. 162 | "What does this ‘Placement’ tool variable, PLACE_DENSITY_LB_ADDON do?",Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. 163 | How does the PLACE_DENSITY_LB_ADDON variable in Placement operate?,Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. 164 | "What does this ‘Placement’ tool variable, PLACE_DENSITY_LB_ADDON do?",Adjusts the lower boundary of PLACE_DENSITY with an addon if present. 165 | "State the function of this OpenROAD ‘Placement’ tool variable, REPAIR_PDN_VIA_LAYER?",Remove power grid vias which generate DRC violations after detailed routing. 166 | What does the REPAIR_PDN_VIA_LAYER variable in Placement specify?,Remove power grid vias which generate DRC violations after detailed routing. 167 | "State the function of this OpenROAD ‘Placement’ tool variable, REPAIR_PDN_VIA_LAYER?",Removes power grid vias causing DRC violations after detailed routing. 168 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, GLOBAL_PLACEMENT_ARGS?",Use additional tuning parameters during global placement other than default args defined in gloabl_place.tcl. 169 | Can you explain the GLOBAL_PLACEMENT_ARGS variable in Placement?,Use additional tuning parameters during global placement other than default args defined in gloabl_place.tcl. 170 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, GLOBAL_PLACEMENT_ARGS?",Uses additional parameters for global placement beyond default args. 171 | "What does this OpenROAD ‘Placement’ tool variable, ENABLE_DPO do?",Enable detail placement with improve_placement feature. 172 | What does the ENABLE_DPO variable in Placement do?,Enable detail placement with improve_placement feature. 173 | "What does this OpenROAD ‘Placement’ tool variable, ENABLE_DPO do?",Enables detailed placement improvement. 174 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, DPO_MAX_DISPLACEMENT?",Specifies how far an instance can be moved when optimizing. 175 | How does the DPO_MAX_DISPLACEMENT variable in Placement function?,Specifies how far an instance can be moved when optimizing. 176 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, DPO_MAX_DISPLACEMENT?",Limits instance movement distance during optimization. 177 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_TIMING_DRIVEN?","In OpenROAD Flow Scripts (ORFS), the GPL_TIMING_DRIVEN variable specifies whether the global placer (gpl) should use timing driven-placement. Timing-driven placement will cause gpl to ocassionally run static timing analysis (sta) during placement in order to determine the timing on each net. gpl will then reweight the nets based on how timing-critical they are. This process improves the timing of the netlist by decreasing the distance between timing-critical cells, but it also causes an increase in gpl runtime due to running timing analysis." 178 | What does the GPL_TIMING_DRIVEN variable in Placement control?,"In OpenROAD Flow Scripts (ORFS), the GPL_TIMING_DRIVEN variable specifies whether the global placer (gpl) should use timing driven-placement. Timing-driven placement will cause gpl to ocassionally run static timing analysis (sta) during placement in order to determine the timing on each net. gpl will then reweight the nets based on how timing-critical they are. This process improves the timing of the netlist by decreasing the distance between timing-critical cells, but it also causes an increase in gpl runtime due to running timing analysis." 179 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_TIMING_DRIVEN?","GPL_TIMING_DRIVEN toggles timing-driven global placement, affecting gpl runtime and netlist timing." 180 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_ROUTABILITY_DRIVEN?","In OpenROAD Flow Scripts (ORFS), the GPL_ROUTABILITY_DRIVEN variable specifies whether the global placer (gpl) should use routability driven-placement. Routability-driven placement will cause gpl to ocassionally run global routing (grt) during placement in order to determine routing congestion hotspots. gpl will then reweight the nets based on how congestion data. This process improves the routability of the netlist by spacing out cells in routing congested areas, but it also causes an increase in gpl runtime due to running global routing." 181 | How does the GPL_ROUTABILITY_DRIVEN variable in Placement operate?,"In OpenROAD Flow Scripts (ORFS), the GPL_ROUTABILITY_DRIVEN variable specifies whether the global placer (gpl) should use routability driven-placement. Routability-driven placement will cause gpl to ocassionally run global routing (grt) during placement in order to determine routing congestion hotspots. gpl will then reweight the nets based on how congestion data. This process improves the routability of the netlist by spacing out cells in routing congested areas, but it also causes an increase in gpl runtime due to running global routing." 182 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_ROUTABILITY_DRIVEN?","GPL_ROUTABILITY_DRIVEN toggles routability-driven global placement, influencing gpl runtime and netlist routability." 183 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, CAP_MARGIN?",Specifies a capacitance margin when fixing max capacitance violations. This option allow you to overfix. 184 | What does the CAP_MARGIN variable in Placement specify?,Specifies a capacitance margin when fixing max capacitance violations. This option allow you to overfix. 185 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, CAP_MARGIN?",Sets a capacitance margin for overfixing max capacitance violations. 186 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, SLEW_MARGIN?",Specifies a slew margin when fixing max slew violations. This option allow you to overfix. 187 | How does the SLEW_MARGIN variable in Placement function?,Specifies a slew margin when fixing max slew violations. This option allow you to overfix. 188 | "Give me a description for the following OpenROAD ‘Placement’ tool variable, SLEW_MARGIN?",Sets a slew margin for overfixing max slew violations. 189 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, CTS_ARGS?",Override clock_tree_synthesis arguments 190 | What does the CTS_ARGS variable in Clock Tree Synthesis control?,Override clock_tree_synthesis arguments 191 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, CTS_ARGS?",Overrides arguments for clock tree synthesis. 192 | What does CTS_BUF_CELL do in ORFS?,The CTS_BUF_CELL variable sets the root buffer cell used in the clock tree during clock tree synthesis (CTS) 193 | What is the purpose of the CTS_BUF_CELL variable in ORFS?,The CTS_BUF_CELL variable sets the root buffer cell used in the clock tree during clock tree synthesis (CTS) 194 | What does CTS_BUF_CELL do in ORFS?,CTS_BUF_CELL selects the root buffer cell for clock tree synthesis. 195 | What is the use of the ORFS variable FILL_CELLS?,The FILL_CELLS variable holds a list of cell names to use as filler cells. Wildcard patterns (*) are supported. Fill cells are used to fill empty cell sites which aids in satisfying design rules and density rules. 196 | How does the FILL_CELLS variable in ORFS function?,The FILL_CELLS variable holds a list of cell names to use as filler cells. Wildcard patterns (*) are supported. Fill cells are used to fill empty cell sites which aids in satisfying design rules and density rules. 197 | What is the use of the ORFS variable FILL_CELLS?,"FILL_CELLS lists cell names for filler cells, supporting wildcards." 198 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, HOLD_SLACK_MARGIN?",Specifies a time margin for the slack when fixing hold violations. This option allow you to overfix. 199 | What does the HOLD_SLACK_MARGIN variable in Clock Tree Synthesis specify?,Specifies a time margin for the slack when fixing hold violations. This option allow you to overfix. 200 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, HOLD_SLACK_MARGIN?",Specifies a time margin for fixing hold violations. 201 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SETUP_SLACK_MARGIN?",Specifies a time margin for the slack when fixing setup violations. 202 | How does the SETUP_SLACK_MARGIN variable in Clock Tree Synthesis operate?,Specifies a time margin for the slack when fixing setup violations. 203 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SETUP_SLACK_MARGIN?",Specifies a time margin for setup violation fixes. 204 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_GATE_CLONING?",Do not use gate cloning transform to fix timing violations (default: use gate cloning) 205 | What does the SKIP_GATE_CLONING variable in Clock Tree Synthesis control?,Do not use gate cloning transform to fix timing violations (default: use gate cloning) 206 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_GATE_CLONING?",Disables gate cloning for timing violation fixes. 207 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_PIN_SWAP?",Do not use pin swapping as a transform to fix timing violations (default: use pin swapping) 208 | What does the SKIP_PIN_SWAP variable in Clock Tree Synthesis indicate?,Do not use pin swapping as a transform to fix timing violations (default: use pin swapping) 209 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_PIN_SWAP?",Disables pin swapping for timing violation fixes. 210 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, TNS_END_PERCENT?","In OpenROAD Flow Scripts, the TNS_END_PERCENT variable specifies what percent of violating timing paths will be fixed during timing optimization. TNS_END_PERCENT must be a floating point value between 0-100. However, even if TNS_END_PERCENT is 0, the worst path will always be fixed. The purpose of this flag is to allow the user some control over how much runtime and logic area is spent on timing optimization, with a higher value leading to more runtime/area and a lower value leading to less runtime/area." 211 | How does the TNS_END_PERCENT variable in Clock Tree Synthesis function?,"In OpenROAD Flow Scripts, the TNS_END_PERCENT variable specifies what percent of violating timing paths will be fixed during timing optimization. TNS_END_PERCENT must be a floating point value between 0-100. However, even if TNS_END_PERCENT is 0, the worst path will always be fixed. The purpose of this flag is to allow the user some control over how much runtime and logic area is spent on timing optimization, with a higher value leading to more runtime/area and a lower value leading to less runtime/area." 212 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, TNS_END_PERCENT?",TNS_END_PERCENT defines the percent of timing path fixes during optimization. 213 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, EQUIVALENCE_CHECK?","In OpenROAD Flow Scripts, the EQUIVALENCE_CHECK variable toggles whether a logical equivalence check is run after timing optimization to ensure logical correctness of the circuit. If EQUIVALENCE_CHECK is 1, the check is performed. If EQUIVALENCE_CHECK is any other value or unset, the check is not run. The default value is unset." 214 | What does the EQUIVALENCE_CHECK variable in Clock Tree Synthesis specify?,"In OpenROAD Flow Scripts, the EQUIVALENCE_CHECK variable toggles whether a logical equivalence check is run after timing optimization to ensure logical correctness of the circuit. If EQUIVALENCE_CHECK is 1, the check is performed. If EQUIVALENCE_CHECK is any other value or unset, the check is not run. The default value is unset." 215 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, EQUIVALENCE_CHECK?",EQUIVALENCE_CHECK toggles logical equivalence checks post-optimization. 216 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, REMOVE_CELLS_FOR_EQY?","In OpenROAD Flow Scripts, the REMOVE_CELLS_FOR_EQY variable sets the list of cells to remove from the verilog netlist file produced specifically for netlist equivalence checking. Netlist equivalence checking is performed with the Yosys EQY tool. Wildcard patterns (*) are supported. This variable is passed directly to write_verilog -remove_cells <>." 217 | How does the REMOVE_CELLS_FOR_EQY variable in Clock Tree Synthesis operate?,"In OpenROAD Flow Scripts, the REMOVE_CELLS_FOR_EQY variable sets the list of cells to remove from the verilog netlist file produced specifically for netlist equivalence checking. Netlist equivalence checking is performed with the Yosys EQY tool. Wildcard patterns (*) are supported. This variable is passed directly to write_verilog -remove_cells <>." 218 | "What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, REMOVE_CELLS_FOR_EQY?",REMOVE_CELLS_FOR_EQY lists cells to exclude from equivalence checking netlist files. 219 | What is the difference between Yosys and OpenROAD?,Yosys is a logic synthesis tool which is responsible for transforming register transfer-level (RTL) code into a gate-level netlist. OpenROAD is a place and route (P&R) tool which is responsible for implementing a gale-level netlist into a chip layout. Yosys is developed by the YosysHQ organization whereas OpenROAD is developed by The OpenROAD Project. OpenROAD Flow Scripts (ORFS) makes use of both of these tools (as well as KLayout) to form a full RTL-to-GDS flow. 220 | Can you contrast Yosys with OpenROAD in terms of functionality?,Yosys is a logic synthesis tool which is responsible for transforming register transfer-level (RTL) code into a gate-level netlist. OpenROAD is a place and route (P&R) tool which is responsible for implementing a gale-level netlist into a chip layout. Yosys is developed by the YosysHQ organization whereas OpenROAD is developed by The OpenROAD Project. OpenROAD Flow Scripts (ORFS) makes use of both of these tools (as well as KLayout) to form a full RTL-to-GDS flow. 221 | What is the difference between Yosys and OpenROAD?,"Yosys transforms RTL code into a gate-level netlist, while OpenROAD handles P&R from netlist to chip layout." 222 | Is there a simple way to open the GUI in ORFS?,"OpenROAD Flow Scripts (ORFS) includes Makefile targets to open the GUI after each step. You can use the command make gui_*, where * is the name of the flow step (e.g. make_floorplan)." 223 | Is there a straightforward method to launch the GUI in ORFS?,"OpenROAD Flow Scripts (ORFS) includes Makefile targets to open the GUI after each step. You can use the command make gui_*, where * is the name of the flow step (e.g. make_floorplan)." 224 | Is there a simple way to open the GUI in ORFS?,OpenROAD Flow Scripts include Makefile targets for GUI access after flow steps. -------------------------------------------------------------------------------- /Augmented_Data/Question-Answer/Tools/Tools.csv: -------------------------------------------------------------------------------- 1 | Prompts,Answers 2 | What does the -switch_cell argument in PDN do while doing power switch insertion?,"During power switch insertion, the -switch_cell argument is used to specify the name of a coarse-grain power switch cell that is to be inserted wherever the standard cell rail connects to the rest of the power grid. The mesh layers are associated with the unswitched power net of the voltage domain, whereas the standard cell rail is associated with the switched power net of the voltage domain. The placement of a power switch cell connects the unswitched power mesh to the switched power rail through a power switch defined by the define_power_switch_cell command." 3 | How does the -switch_cell argument function in PDNGEN during power switch integration?,"During power switch insertion, the -switch_cell argument is used to specify the name of a coarse-grain power switch cell that is to be inserted wherever the standard cell rail connects to the rest of the power grid. The mesh layers are associated with the unswitched power net of the voltage domain, whereas the standard cell rail is associated with the switched power net of the voltage domain. The placement of a power switch cell connects the unswitched power mesh to the switched power rail through a power switch defined by the define_power_switch_cell command." 4 | What does the -switch_cell argument in PDN do while doing power switch insertion?,"For inserting power switches, the -switch_cell parameter is utilized to denote a coarse-grain power switch cell's name for insertion at points where the standard cell rail merges with the broader power grid. The mesh layers correspond with the voltage domain's unswitched power net, and the standard cell rail links to the switched power net. Inserting a power switch cell bridges the unswitched power mesh and the switched power rail, facilitated by the define_power_switch_cell command." 5 | What does the par module do?,"The partitioning module (par) is based on TritonPart, an open-source constraints-driven partitioner. par can be used to partition a hypergraph or a gate-level netlist. TritonPart solves multi-way partitioning by 1) constraints-driven coarsening, 2) initial partitioning, 3) refinement, 4) cut-overlay clustering and partitioning (COCP), and 5) V-cycle refinement. The purpose of partitioning a netlist is to reduce the complexity of a circuit so that algorithms can operate on smaller chunks of the netlist at a time. Partitioning a netlist may slightly reduce the optimization opportunities compared to a non-partitioned approach, but it greatly benefits the runtime. Partitioning a netlist may be the only option to feasibly operate on very large circuits." 6 | What functionality does the par module provide?,"The partitioning module (par) is based on TritonPart, an open-source constraints-driven partitioner. par can be used to partition a hypergraph or a gate-level netlist. TritonPart solves multi-way partitioning by 1) constraints-driven coarsening, 2) initial partitioning, 3) refinement, 4) cut-overlay clustering and partitioning (COCP), and 5) V-cycle refinement. The purpose of partitioning a netlist is to reduce the complexity of a circuit so that algorithms can operate on smaller chunks of the netlist at a time. Partitioning a netlist may slightly reduce the optimization opportunities compared to a non-partitioned approach, but it greatly benefits the runtime. Partitioning a netlist may be the only option to feasibly operate on very large circuits." 7 | What does the par module do?,"The partitioning tool, par, leverages TritonPart, a freely available constraint-based partitioning software. It enables the partitioning of hypergraphs or gate-level netlists through a process involving constraint-led coarsening, initial partitioning, refinement, cut-overlay clustering and partitioning (COCP), and V-cycle refinement. The main goal is to simplify the circuit's complexity, allowing algorithms to manage smaller sections of the netlist efficiently. Though partitioning may slightly limit optimization chances, it significantly enhances runtime and is often the sole strategy for managing vast circuits." 8 | Is TritonRoute the foundation of drt?,"The Detailed Routing (drt) module in OpenROAD is based on the open-source detailed router TritonRoute. TritonRoute consists of several main building blocks, including pin access analysis, track assignment, initial detailed routing, search and repair, and a DRC engine. The initial development of the router is inspired by the ISPD-2018 initial detailed routing contest. However, the current drt framework differs and is built from scratch, aiming for an industrial-oriented, scalable, and flexible flow." 9 | Does TritonRoute serve as the underlying technology for drt?,"The Detailed Routing (drt) module in OpenROAD is based on the open-source detailed router TritonRoute. TritonRoute consists of several main building blocks, including pin access analysis, track assignment, initial detailed routing, search and repair, and a DRC engine. The initial development of the router is inspired by the ISPD-2018 initial detailed routing contest. However, the current drt framework differs and is built from scratch, aiming for an industrial-oriented, scalable, and flexible flow." 10 | Is TritonRoute the foundation of drt?,"The Detailed Routing (drt) module of OpenROAD, founded on the open-source detailed router TritonRoute, incorporates key components like pin access analysis, track assignment, initial routing, search and repair, and a DRC (Design Rule Checking) engine. Initially inspired by the ISPD-2018 detailed routing challenge, the current drt architecture is entirely new, designed for industrial-grade scalability and flexibility." 11 | "What do these Debug output mean? 12 | [INFO MPL-0024] [Multilevel Autoclustering] Creating clustered netlist. 13 | [INFO MPL-0039] [Coarse Shaping] Determining shape functions for clusters. 14 | [INFO MPL-0028] [Hierarchical Macro Placement] Placing clusters and macros. 15 | [INFO MPL-0037] Updated location of 95 macros 16 | Delete buffers for RTLMP flow... 17 | [INFO RSZ-0026] Removed 0 buffers.","Messages with the MPL prefix are from the macro placement (mpl) module. These messages are progress messages, informing the user which step of the HierRTLMP flow is being executed." 18 | What are the units of the -pad_right and -pad_left arguments of the global_placement function,"In global_placement, -pad_right and -pad_left add padding which is measured in cell sites to effectively make the cell appear wider. pad_left adds a pad to the left side, pad_right adds it to the right side. Wider cells during global placement can help reduce placement congestion and make finding a valid placement easier." 19 | What are the measurement units for the -pad_right and -pad_left arguments in the global_placement function?,"In global_placement, -pad_right and -pad_left add padding which is measured in cell sites to effectively make the cell appear wider. pad_left adds a pad to the left side, pad_right adds it to the right side. Wider cells during global placement can help reduce placement congestion and make finding a valid placement easier." 20 | What are the units of the -pad_right and -pad_left arguments of the global_placement function,"In the global placement process, the options -pad_right and -pad_left introduce padding in terms of cell sites, effectively broadening the cell. This padding on either side aids in alleviating placement congestion and facilitates easier placement validation." 21 | Does space padding influence the design utilization? I feel like it shouldn't.,"Cell padding only impacts the way the global placer (gpl) and detailed placer (dpl) sees the cells. Cell padding does not change the logic area of the cell from the user perspective. If you were to use the report_design_area command, you would see the unpadded design utilization reported." 22 | "Does padding affect design utilization, in your opinion?","Cell padding only impacts the way the global placer (gpl) and detailed placer (dpl) sees the cells. Cell padding does not change the logic area of the cell from the user perspective. If you were to use the report_design_area command, you would see the unpadded design utilization reported." 23 | Does space padding influence the design utilization? I feel like it shouldn't.,"Padding adjustments affect only how global and detailed placers view the cells, leaving the cell's logical area as perceived by the user unchanged. Utilizing the report_design_area command will display the design's utilization without the padding." 24 | "Wouldn't manually adding pads in the global_placement function reduce the maximum design utilization possible for a design? Especially since OpenROAD wants to be automatic, GPL will stop everything if it sees a DU >100% even if it could achieve a reasonable DU with equivalent padding","Cell padding can reduce the maximum possible design utilization. If you don't want padding in your design, you can reduce the default padding or turn it off. However, padding is usually necessary to achieve a cleanly routed design, because cells which are too close together may make routing impossible. If you want to optimize for very high-density designs, I believe you can also set padding on a master-by-master basis so that only the most difficult cells are padded. This process may take some trial and error." 25 | Could manually adding pads in the global_placement function affect the maximum design utilization?,"Cell padding can reduce the maximum possible design utilization. If you don't want padding in your design, you can reduce the default padding or turn it off. However, padding is usually necessary to achieve a cleanly routed design, because cells which are too close together may make routing impossible. If you want to optimize for very high-density designs, I believe you can also set padding on a master-by-master basis so that only the most difficult cells are padded. This process may take some trial and error." 26 | "Wouldn't manually adding pads in the global_placement function reduce the maximum design utilization possible for a design? Especially since OpenROAD wants to be automatic, GPL will stop everything if it sees a DU >100% even if it could achieve a reasonable DU with equivalent padding","Implementing cell padding may limit the maximum design utilization achievable. Adjusting or disabling default padding is an option, though padding is often crucial for achieving a neatly routed design by preventing overly congested cell placements. For high-density design optimization, padding can be selectively applied to particularly challenging cells, requiring some experimentation." 27 | Why did I encounter an issue with CORE_UTILIZATION when trying to aim for a DU of 70% on the ASAP7 PDK which should be possible and reasonable for any design?,"If you are using ORFS, the CORE_UTILIZATION variable only determines the core utilization after Yosys (synthesis) runs using the netlist data. The utilization can change dramatically as OpenROAD performs timing optimization, which will insert buffers, remove buffers, and resize cells. For example, if you set CORE_UTILIZATION to 70% utilization during the initialization step, you may end up with 90%+ utilization because of optimization to meet timing constraints. It is currently up to the designer to ensure that the CORE_UTILIZATION is set appropriately, which may require some trial and error." 28 | Why did I face a CORE_UTILIZATION issue when targeting a DU of 70% with the ASAP7 PDK?,"If you are using ORFS, the CORE_UTILIZATION variable only determines the core utilization after Yosys (synthesis) runs using the netlist data. The utilization can change dramatically as OpenROAD performs timing optimization, which will insert buffers, remove buffers, and resize cells. For example, if you set CORE_UTILIZATION to 70% utilization during the initialization step, you may end up with 90%+ utilization because of optimization to meet timing constraints. It is currently up to the designer to ensure that the CORE_UTILIZATION is set appropriately, which may require some trial and error." 29 | Why did I encounter an issue with CORE_UTILIZATION when trying to aim for a DU of 70% on the ASAP7 PDK which should be possible and reasonable for any design?,"With ORFS, the CORE_UTILIZATION variable reflects core utilization post-Yosys synthesis, based on netlist data. Subsequent timing optimization in OpenROAD, which includes buffer insertion, deletion, and cell resizing, can significantly alter utilization levels. Designers must judiciously set CORE_UTILIZATION, anticipating possible adjustments through trial and error." 30 | "If I have a design for which the detailed placement fails for a few instances, if I relax my timing constraints will it result in a successful placement?","Relaxing timing constraints can usually reduce your design utilization because fewer buffers will need to be inserted. However, detailed placement can fail for several reasons, including 1) setting core utilization too high, 2) not having enough cell padding during global placement, 3) having too much cell padding during detailed placement, 4) having a poor macro placement which will block placement of some standard cells" 31 | "If detailed placement fails for certain instances in my design, would loosening timing constraints help achieve placement?","Relaxing timing constraints can usually reduce your design utilization because fewer buffers will need to be inserted. However, detailed placement can fail for several reasons, including 1) setting core utilization too high, 2) not having enough cell padding during global placement, 3) having too much cell padding during detailed placement, 4) having a poor macro placement which will block placement of some standard cells" 32 | "If I have a design for which the detailed placement fails for a few instances, if I relax my timing constraints will it result in a successful placement?","Easing timing constraints can lead to lower design utilization by reducing the need for buffer insertion. However, detailed placement might fail due to reasons like excessive core utilization, insufficient global placement padding, excessive detailed placement padding, or suboptimal macro placement impeding standard cell placement." 33 | "The timing optimizations done by the synthesis tool are ""discarded"" as the buffers are removed?","Empiracally, the OpenROAD team has found that OpenROAD optimizes better when the buffers from Yosys are removed, because Yosys does not do physical synthesis." 34 | Are the timing adjustments made by the synthesis tool lost when buffers are eliminated?,"Empiracally, the OpenROAD team has found that OpenROAD optimizes better when the buffers from Yosys are removed, because Yosys does not do physical synthesis." 35 | "The timing optimizations done by the synthesis tool are ""discarded"" as the buffers are removed?","The OpenROAD team has empirically observed that removing Yosys-inserted buffers leads to better optimization outcomes, as Yosys lacks physical synthesis capabilities." 36 | Is there no need to re-synthesize with different timing constraints with Yosys? Or does it also use different/bigger non-buffer cells that also need to be resized?,"Empirically, applying timing constraints to Yosys for synthesis does not have much impact on the output netlist. However, the results may not be identical if the timing constraints are changed." 37 | "Is re-synthesizing with altered timing constraints unnecessary with Yosys, or does it also resize non-buffer cells?","Empirically, applying timing constraints to Yosys for synthesis does not have much impact on the output netlist. However, the results may not be identical if the timing constraints are changed." 38 | Is there no need to re-synthesize with different timing constraints with Yosys? Or does it also use different/bigger non-buffer cells that also need to be resized?,"Applying timing constraints during Yosys synthesis shows limited influence on the netlist outcome, with possible variations if timing constraints are altered." 39 | "What does this warning mean? 40 | [WARNING ODB-0208] VIA: duplicate VIA (via5_6_120_288_1_2_58_322) ignored...","This warning likely occurs because of multiple block abstracts with the same via. To fix this problem, one should ensure that the block abstracts do not have duplicates via definitions." 41 | "Upon attempting to read an invalid ODB file, OpenROAD doesn't attempt to validate it and instead crashes with a cryptic message of Error: read_db.tcl, 1 ios_base::clear: unspecified iostream_category error. Why is this happening?","I would advise against using low-level OBD APIs to interact with OpenROAD. User-facing APIs in OpenROAD have documentation and error checking to prevent improper usage, however low-level APIs may not have error checking for performance reasons. In this case, it appears the db you are creating does not have a logger and can't issue any messages." 42 | Why does OpenROAD crash without attempting to validate an invalid ODB file?,"I would advise against using low-level OBD APIs to interact with OpenROAD. User-facing APIs in OpenROAD have documentation and error checking to prevent improper usage, however low-level APIs may not have error checking for performance reasons. In this case, it appears the db you are creating does not have a logger and can't issue any messages." 43 | "Upon attempting to read an invalid ODB file, OpenROAD doesn't attempt to validate it and instead crashes with a cryptic message of Error: read_db.tcl, 1 ios_base::clear: unspecified iostream_category error. Why is this happening?","I recommend against using the low-level OBD APIs in OpenROAD since user-friendly APIs offer documentation and error checking to prevent misuse, unlike low-level APIs that might lack error checks for efficiency. In your situation, the database being created lacks a logger, preventing message issuance." 44 | What is IR Drop Analysis?,"The IR Drop Analysis module in OpenROAD (psm) is based on PDNSim, an open-source static IR analyzer. PDNSim will perform a simulation based on the estimated current draw of each instance to estimate what is the voltage drop seen at each cell. That is, it shows the voltage drop between the voltage source(s) of the chip and each instance." 45 | Can you explain IR Drop Analysis and its purposes?,"The IR Drop Analysis module in OpenROAD (psm) is based on PDNSim, an open-source static IR analyzer. PDNSim will perform a simulation based on the estimated current draw of each instance to estimate what is the voltage drop seen at each cell. That is, it shows the voltage drop between the voltage source(s) of the chip and each instance." 46 | What is IR Drop Analysis?,"The IR Drop Analysis module in OpenROAD, based on PDNSim, performs simulations to estimate the voltage drop across each cell by analyzing the current draw of each instance, illustrating the drop from the chip's voltage source(s) to each instance." 47 | What are the features of IR Drop analysis?,"The features of IR Drope analysis are: reporting the worst IR drop, reporting the worst current density over all nodes and wire segments in the power distribution network (given a placed and PDN-synthesized design), checking for floating PDN stripes on the power and ground nets, and spice netlist writer for power distribution network wire segments." 48 | What characteristics define IR Drop analysis?,"The features of IR Drope analysis are: reporting the worst IR drop, reporting the worst current density over all nodes and wire segments in the power distribution network (given a placed and PDN-synthesized design), checking for floating PDN stripes on the power and ground nets, and spice netlist writer for power distribution network wire segments." 49 | What are the features of IR Drop analysis?,"IR Drop analysis features include identifying the most severe IR drop and current density across all nodes and wire segments of the power distribution network, detecting floating PDN stripes on power and ground nets, and generating spice netlists for PDN wire segments." 50 | What is Flute3?,Flute3 is an open-source rectilinear Steiner minimum tree heuristic with improvements made by UFRGS students and James Cherry. This tool is used for the calculation of wirelength in grt and rsz. 51 | What distinguishes Flute3?,Flute3 is an open-source rectilinear Steiner minimum tree heuristic with improvements made by UFRGS students and James Cherry. This tool is used for the calculation of wirelength in grt and rsz. 52 | What is Flute3?,"Flute3, enhanced by UFRGS students and James Cherry, is an open-source heuristic for calculating the rectilinear Steiner minimum tree, crucial for estimating wirelength in tools like grt and rsz." 53 | What does the global_connect command do?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The global_connect command is used to define logical connections between supply pins on design instances and their respective supply nets. Note that the global_connect command only creates a logical connection; it does not perform any routing for a physical connection. 54 | What function does the global_connect command serve?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The global_connect command is used to define logical connections between supply pins on design instances and their respective supply nets. Note that the global_connect command only creates a logical connection; it does not perform any routing for a physical connection. 55 | What does the global_connect command do?,"Global connections are designated for linking supply nets to cell supply pins without establishing physical routes, instead creating logical connections that are made using the global_connect command." 56 | What does the clear_global_connect command do?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The clear_global_connect command is used to clear previously declared connections between supply pins on design instances and their respective supply nets. Note that the clear_global_connect command only clears the logical connections; it does not remove any routing or physical connections. 57 | What is the effect of using the clear_global_connect command?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The clear_global_connect command is used to clear previously declared connections between supply pins on design instances and their respective supply nets. Note that the clear_global_connect command only clears the logical connections; it does not remove any routing or physical connections. 58 | What does the clear_global_connect command do?,The clear_global_connect command removes logical connections between supply pins and their nets without affecting any physical routing or connections. 59 | What does the report_global_connect command do?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The report_global_connect command is used to print out the currently defined global connection rules. 60 | What information does the report_global_connect command provide?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The report_global_connect command is used to print out the currently defined global connection rules. 61 | What does the report_global_connect command do?,"Global connections typically link supply nets to cell supply pins, and the report_global_connect command prints the existing global connection rules." 62 | What does the report_cell_usage command do?,The report_cell_usage command is used to print out the number of instances of each type of cell (master) used in the design. 63 | How does the report_cell_usage command assist users?,The report_cell_usage command is used to print out the number of instances of each type of cell (master) used in the design. 64 | What does the report_cell_usage command do?,The report_cell_usage command displays the count of each cell type used within the design. 65 | Is SystemVerilog support limited to the constructs that Yosys supports?,The OpenROAD Flow is limited to the RTL language support that the Yosys synthesizer provides. Yosys currently provides support for a limited subset of SystemVerilog and full support for Verilog. OpenROAD only supports structural Verilog netlists. 66 | Are there limitations to SystemVerilog support based on Yosys compatibility?,The OpenROAD Flow is limited to the RTL language support that the Yosys synthesizer provides. Yosys currently provides support for a limited subset of SystemVerilog and full support for Verilog. OpenROAD only supports structural Verilog netlists. 67 | Is SystemVerilog support limited to the constructs that Yosys supports?,"OpenROAD's RTL language support is contingent on Yosys synthesizer's capabilities, with full support for Verilog and partial support for SystemVerilog." 68 | What is the job of Pin Placer?,"Place pins on the boundary of the die on the track grid to minimize net wirelengths. Pin placement also creates a metal shape for each pin using min-area rules. For designs with unplaced cells, the net wirelength is computed considering the center of the die area as the unplaced cells' position." 69 | What is the function of the Pin Placer tool?,"Place pins on the boundary of the die on the track grid to minimize net wirelengths. Pin placement also creates a metal shape for each pin using min-area rules. For designs with unplaced cells, the net wirelength is computed considering the center of the die area as the unplaced cells' position." 70 | What is the job of Pin Placer?,"For minimized net wirelengths, place pins on the die's boundary on the track grid, creating metal shapes for each pin according to min-area rules and considering the die center as the position for unplaced cells." 71 | What is RePlAce in OpenROAD?,"RePlAce is a tool for advancing solution quality and routability validation in Global Placement. Its features are analytic and nonlinear placement algorithms. it solves electrostatic force equations using Nesterov's method, verified with various commercial technologies and research enablements using OpenDB, verified deterministic solution generation with various compilers and OS, and supports Mixed-size placement mode." 72 | What is RePlAce and its function in OpenROAD?,"RePlAce is a tool for advancing solution quality and routability validation in Global Placement. Its features are analytic and nonlinear placement algorithms. it solves electrostatic force equations using Nesterov's method, verified with various commercial technologies and research enablements using OpenDB, verified deterministic solution generation with various compilers and OS, and supports Mixed-size placement mode." 73 | What is RePlAce in OpenROAD?,"RePlAce advances global placement solution quality and routability with analytic and nonlinear algorithms, solving electrostatic force equations and ensuring deterministic solutions across various technologies." 74 | What is Hierarchical Macro Placement/ Hier-RTLMP?,"""Hier-RTLMP"" is defined as a hierarchical automatic macro placer for large-scale complex IP blocks. This tool builds on the existing RTLMP (mpl) framework, adopting a multilevel physical planning approach that exploits the hierarchy and data flow inherent in the design RTL." 75 | How is Hierarchical Macro Placement defined within OpenROAD?,"""Hier-RTLMP"" is defined as a hierarchical automatic macro placer for large-scale complex IP blocks. This tool builds on the existing RTLMP (mpl) framework, adopting a multilevel physical planning approach that exploits the hierarchy and data flow inherent in the design RTL." 76 | What is Hierarchical Macro Placement/ Hier-RTLMP?,"Hier-RTLMP, building on the RTLMP framework, is a hierarchical macro placer leveraging design RTL's inherent hierarchy and data flow for complex IP blocks." 77 | What file formats are supported by Parallax Static Timing Analyzer or OpenSTA?,"The Following standard file formats are supported by Parallax Static Timing Analyzer or OpenSTA: Verilog netlist, Liberty library, SDC timing constraints,SDF delay annotation, and SPEF parasitics." 78 | Which file formats does Parallax Static Timing Analyzer accept?,"The Following standard file formats are supported by Parallax Static Timing Analyzer or OpenSTA: Verilog netlist, Liberty library, SDC timing constraints,SDF delay annotation, and SPEF parasitics." 79 | What file formats are supported by Parallax Static Timing Analyzer or OpenSTA?,"OpenSTA supports Verilog netlist, Liberty library, SDC timing constraints, SDF delay annotation, and SPEF parasitics for timing verification." 80 | "`auto_place_pins pin_layer` places pins on a single layer but It should be able to place vertical pins (sides of the die) and horizontal pins (top and bottom of the die) in separate layers, why is it not able to do this?","I currently recommend using `io_placer` instead of `auto_place_pins`. Here's an example:```io_placer -hor_layer 3 -ver_layer 2```Note that `io_placer` uses cell placement information to guide the I/O pin placement. If placement has not yet been run, the `-random` flag is required, which will distribute the pins evenly over the die boundary." 81 | Why can't auto_place_pins pin_layer place pins on separate layers for vertical and horizontal orientations?,"I currently recommend using `io_placer` instead of `auto_place_pins`. Here's an example:```io_placer -hor_layer 3 -ver_layer 2```Note that `io_placer` uses cell placement information to guide the I/O pin placement. If placement has not yet been run, the `-random` flag is required, which will distribute the pins evenly over the die boundary." 82 | "`auto_place_pins pin_layer` places pins on a single layer but It should be able to place vertical pins (sides of the die) and horizontal pins (top and bottom of the die) in separate layers, why is it not able to do this?","For pin placement, io_placer is recommended over auto_place_pins, using layer specifications for guided I/O pin placement or the -random flag for preliminary placement before cell placement." 83 | Tell me about the parts of DFT insertion?,"A simple DFT insertion consists of the following parts: a scan_in pin where the test patterns are shifted in, a scan_out pin where the test patterns are read from, scan cells that replace flops with registers that allow for testing, one or more scan chains (shift registers created from your scan cells), a scan_enable pin to allow your design to enter and leave the test mode." 84 | Could you describe the components involved in DFT insertion?,"A simple DFT insertion consists of the following parts: a scan_in pin where the test patterns are shifted in, a scan_out pin where the test patterns are read from, scan cells that replace flops with registers that allow for testing, one or more scan chains (shift registers created from your scan cells), a scan_enable pin to allow your design to enter and leave the test mode." 85 | Tell me about the parts of DFT insertion?,"DFT insertion typically involves a scan_in pin for inputting test patterns, a scan_out pin for outputting test patterns, scan cells that are substituted for flops, one or more scan chains forming shift registers, and a scan_enable pin for toggling test mode on and off." 86 | What is Metal fill?,"Metal filling is a common process in integrated circuit design to enhance manufacturability and yield by making the density of metal shapes more uniform across the design. In OpenROAD, the Finale module (fin) inserts floating metal fill shapes to meet metal density design rules while obeying DRC constraints. The rules for generating metal fill shapes are driven by a JSON configuration file, and the schema can be found in the OpenROAD documentation." 87 | What is the purpose of Metal fill in OpenROAD?,"Metal filling is a common process in integrated circuit design to enhance manufacturability and yield by making the density of metal shapes more uniform across the design. In OpenROAD, the Finale module (fin) inserts floating metal fill shapes to meet metal density design rules while obeying DRC constraints. The rules for generating metal fill shapes are driven by a JSON configuration file, and the schema can be found in the OpenROAD documentation." 88 | What is Metal fill?,"Metal filling, used to improve manufacturability and yield in IC design by standardizing metal shape density, is implemented in OpenROAD's Finale module. It places non-connecting metal fill shapes in accordance with metal density rules and Design Rule Checking (DRC) constraints, guided by a JSON configuration file detailed in the OpenROAD documentation." 89 | What are the Gate Resizer commands?,The resizer commands stop when the design area is -max_utilization util percent of the core area. util is between 0 and 100. The resizer stops and reports an error if the maximum utilization is exceeded. 90 | What are the functionalities of the Gate Resizer commands?,The resizer commands stop when the design area is -max_utilization util percent of the core area. util is between 0 and 100. The resizer stops and reports an error if the maximum utilization is exceeded. 91 | What are the Gate Resizer commands?,"The resizer tool halts if the design exceeds -max_utilization percent of the core area's utilization, throwing an error if the limit is surpassed." 92 | What is macro placement?,"The macro placement module in OpenROAD (mpl) is based on TritonMacroPlacer, an open-source ParquetFP-based macro cell placer. The macro placer places macros/blocks honoring halos, channels, and cell row ""snapping"". Run global_placement before macro placement." 93 | What is macro placement and its significance in OpenROAD?,"The macro placement module in OpenROAD (mpl) is based on TritonMacroPlacer, an open-source ParquetFP-based macro cell placer. The macro placer places macros/blocks honoring halos, channels, and cell row ""snapping"". Run global_placement before macro placement." 94 | What is macro placement?,"The macro placement module in OpenROAD, built on TritonMacroPlacer, places macros/blocks while respecting design constraints like halos, channels, and cell row alignment. It's recommended to run global_placement prior to macro placement." 95 | Elaborate on FastRoute?,"FastRoute is a global routing tool for VLSI back-end design. It is based on sequential rip-up and re-route (RRR) and a lot of novel techniques. FastRoute 1.0 first uses FLUTE to construct congestion-driven Steiner trees, which will later undergo the edge-shifting process to optimize tree structure to reduce congestion. It then uses pattern routing and maze routing with a logistic function-based cost function to solve the congestion problem. FastRoute 2.0 proposed monotonic routing and multi-source multi-sink maze routing techniques to enhance the capability to reduce congestion. FastRoute 3.0 introduced the virtual capacity technique to adaptively change the capacity associated with each global edge to divert wire usage from highly congested regions to less congested regions. FastRoute 4.0 proposed via-aware Steiner tree, 3-bend routing, and a delicate layer assignment algorithm to effectively reduce via count while maintaining outstanding congestion reduction capability. FastRoute 4.1 simplifies the way the virtual capacities are updated and applies a single set of tuning parameters to all benchmark circuits" 96 | How does FastRoute enhance routing processes?,"FastRoute is a global routing tool for VLSI back-end design. It is based on sequential rip-up and re-route (RRR) and a lot of novel techniques. FastRoute 1.0 first uses FLUTE to construct congestion-driven Steiner trees, which will later undergo the edge-shifting process to optimize tree structure to reduce congestion. It then uses pattern routing and maze routing with a logistic function-based cost function to solve the congestion problem. FastRoute 2.0 proposed monotonic routing and multi-source multi-sink maze routing techniques to enhance the capability to reduce congestion. FastRoute 3.0 introduced the virtual capacity technique to adaptively change the capacity associated with each global edge to divert wire usage from highly congested regions to less congested regions. FastRoute 4.0 proposed via-aware Steiner tree, 3-bend routing, and a delicate layer assignment algorithm to effectively reduce via count while maintaining outstanding congestion reduction capability. FastRoute 4.1 simplifies the way the virtual capacities are updated and applies a single set of tuning parameters to all benchmark circuits" 97 | Elaborate on FastRoute?,"FastRoute utilizes a series of innovative techniques for global routing, including FLUTE for constructing congestion-driven Steiner trees, edge-shifting, pattern routing, and maze routing to address congestion, with further enhancements in subsequent versions to reduce congestion and via count effectively." 98 | "Is there any way I can use just the RTL-MP2 stand-alone on either an RTL design or a gate netlist? The issue is, that we use proprietary tools so do not have an OpenDB database for our designs.","OpenROAD supports interoperability with other EDA tools through the industry standard Verilog, LEF, and DEF formats. In this case, you can import a DEF file into OpenROAD from an external tool, run RTL-MP2, and then export the DEF file. The DEF file format should be supported by nearly all EDA physical design tools." 99 | Is it possible to use RTL-MP2 standalone for RTL designs or gate netlists without an OpenDB database?,"OpenROAD supports interoperability with other EDA tools through the industry standard Verilog, LEF, and DEF formats. In this case, you can import a DEF file into OpenROAD from an external tool, run RTL-MP2, and then export the DEF file. The DEF file format should be supported by nearly all EDA physical design tools." 100 | "Is there any way I can use just the RTL-MP2 stand-alone on either an RTL design or a gate netlist? The issue is, that we use proprietary tools so do not have an OpenDB database for our designs.","OpenROAD facilitates interoperability with other EDA tools through standard formats like Verilog, LEF, and DEF, allowing for seamless DEF file imports and exports to and from external tools." 101 | How do I check DRC?,"In OpenROAD, you can use the check_drc command to run the design rule check (DRC). It should be noted that check_drc is not a general-purpose checker and only verifies signal routing according to routing rules from the technology LEF file. check_drc also requires routing guides in order to run, so global routing must be performed first. DRC is also commonly performed by an external tool which will check all layers, not just the metal routing layers." 102 | How do I perform a DRC check in OpenROAD?,"In OpenROAD, you can use the check_drc command to run the design rule check (DRC). It should be noted that check_drc is not a general-purpose checker and only verifies signal routing according to routing rules from the technology LEF file. check_drc also requires routing guides in order to run, so global routing must be performed first. DRC is also commonly performed by an external tool which will check all layers, not just the metal routing layers." 103 | How do I check DRC?,"The check_drc command in OpenROAD performs design rule checks based on routing rules from the technology LEF file, requiring prior global routing and typically supplemented by external tools for comprehensive DRC across all layers." 104 | What does the argument -floorplan_initialize do in read_def?,"When using the read_def command with the -floorplan_initialize argument, OpenROAD will read only physical placement information such as pin locations and instance locations. It does not read or redefine the netlist." 105 | What does the -floorplan_initialize argument achieve in read_def?,"When using the read_def command with the -floorplan_initialize argument, OpenROAD will read only physical placement information such as pin locations and instance locations. It does not read or redefine the netlist." 106 | What does the argument -floorplan_initialize do in read_def?,"Using the read_def command with -floorplan_initialize in OpenROAD loads only the physical placement data, excluding netlist alterations." 107 | What does the argument -skip_pin_swap & -skip_gate_cloning do in repair_timing?,"These flags disable optimizations in case of trouble or unexpected results. They are mainly included as a failsafe for users, rather than something that is expected to be used." 108 | What are the functions of -skip_pin_swap & -skip_gate_cloning in repair_timing?,"These flags disable optimizations in case of trouble or unexpected results. They are mainly included as a failsafe for users, rather than something that is expected to be used." 109 | What does the argument -skip_pin_swap & -skip_gate_cloning do in repair_timing?,"Certain flags in OpenROAD disable optimizations as a safeguard against unexpected outcomes, intended as a last resort for troubleshooting." 110 | What does the detailed_placement command do in OpenROAD?,"The detailed_placement command moves instances to legal locations after global placement. While the global placer (gpl) may place cells in a roughly optimal position, gpl may not place the cells in legal locations because they may not be aligned to cell rows or sites. The detailed placer (dpl) will legalize the cell by shifting it to a nearby location which is aligned to the cell site grid. The detailed_placement command only performs basic legalization and does not attempt to optimize placement. The optimize_mirroring and improve_placement commands will perform optimization on the legalized cells." 111 | What is the purpose of the detailed_placement command?,"The detailed_placement command moves instances to legal locations after global placement. While the global placer (gpl) may place cells in a roughly optimal position, gpl may not place the cells in legal locations because they may not be aligned to cell rows or sites. The detailed placer (dpl) will legalize the cell by shifting it to a nearby location which is aligned to the cell site grid. The detailed_placement command only performs basic legalization and does not attempt to optimize placement. The optimize_mirroring and improve_placement commands will perform optimization on the legalized cells." 112 | What does the detailed_placement command do in OpenROAD?,"The detailed_placement command in OpenROAD repositions instances to legal sites post-global placement, focusing on basic legalization without attempting placement optimization, which is handled by subsequent commands." 113 | "What does the argument -max_displacement disp|{disp_x disp_y} do in detailed_placement 114 | Command?","Max distance that an instance can be moved (in microns) when finding a site where it can be placed. Either set one value for both directions or set {disp_x disp_y} for individual directions. The default values are {0, 0}, and the allowed values within are integers [0, MAX_INT]. This argument is useful because it limits the amount of searching and therefore amount of runtime that the detailed placer can use." 115 | How does the -max_displacement argument affect the detailed_placement command?,"Max distance that an instance can be moved (in microns) when finding a site where it can be placed. Either set one value for both directions or set {disp_x disp_y} for individual directions. The default values are {0, 0}, and the allowed values within are integers [0, MAX_INT]. This argument is useful because it limits the amount of searching and therefore amount of runtime that the detailed placer can use." 116 | "What does the argument -max_displacement disp|{disp_x disp_y} do in detailed_placement 117 | Command?","Specifies the maximum distance instances can be relocated during detailed placement, with default settings at {0, 0} and customizable values for x and y directions to limit search scope and runtime." 118 | What does the argument -disallow_one_site_gaps do in the detailed_placement command?,"detailed_place -disallow_one_site_gaps will disallow the detailed placer from leaving gaps between cells that are exactly one cell sitewide. This feature is mainly useful for PDKs that do not have filler cells which are one site-wide. In this case, one-site-wide gaps are unfillable and will cause DRC violations." 119 | What does the -disallow_one_site_gaps argument do in detailed_placement?,"detailed_place -disallow_one_site_gaps will disallow the detailed placer from leaving gaps between cells that are exactly one cell sitewide. This feature is mainly useful for PDKs that do not have filler cells which are one site-wide. In this case, one-site-wide gaps are unfillable and will cause DRC violations." 120 | What does the argument -disallow_one_site_gaps do in the detailed_placement command?,"The detailed_place -disallow_one_site_gaps option prevents one-site-wide gaps between cells in detailed placement, addressing DRC issues in PDKs lacking one-site-wide filler cells." 121 | What does the argument -report_file_name do in the detailed_placement command?,"The -report_file_name argument for the detailed_placement command specifies where the report for detailed placement should be saved. The report is saved in the JSON format and contains metrics related to detailed_placement. If this argument is not provided, no report will be saved for the detailed_placement command." 122 | What role does the -report_file_name argument play in the detailed_placement command?,"The -report_file_name argument for the detailed_placement command specifies where the report for detailed placement should be saved. The report is saved in the JSON format and contains metrics related to detailed_placement. If this argument is not provided, no report will be saved for the detailed_placement command." 123 | What does the argument -report_file_name do in the detailed_placement command?,"The detailed_placement command's -report_file_name argument designates the storage location for the placement report in JSON format, detailing metrics of the placement. Without this argument, the command does not save a report." 124 | What does the Set Placement Padding command do?,"The set_placement_padding command sets left and right padding in multiples of the row site width. Use the set_placement_padding command before legalizing placement to leave room for routing. Use the -global flag for padding that applies to all instances. Use -instances for instance-specific padding. The instances insts can be a list of instance names, or an instance object returned by the SDC get_cells command. To specify padding for all instances of a common master, use the -filter ""ref_name == "" option to get_cells." 125 | How does the Set Placement Padding command optimize placement?,"The set_placement_padding command sets left and right padding in multiples of the row site width. Use the set_placement_padding command before legalizing placement to leave room for routing. Use the -global flag for padding that applies to all instances. Use -instances for instance-specific padding. The instances insts can be a list of instance names, or an instance object returned by the SDC get_cells command. To specify padding for all instances of a common master, use the -filter ""ref_name == "" option to get_cells." 126 | What does the Set Placement Padding command do?,"The set_placement_padding command adjusts the left and right padding based on row site width multiples, essential for spacing before placement legalization. It supports global padding via -global or specific instance padding through -instances, with flexibility in selecting instances via a list or the SDC get_cells command." 127 | What is the significance of the filler_placement command?,"The filler_placement command fills gaps between detail-placed instances to connect the power and ground rails in the rows. filler_masters is a list of master/macro names to use for filling the gaps. Wildcard matching is supported, so FILL* will match, e.g., FILLCELL_X1 FILLCELL_X16 FILLCELL_X2 FILLCELL_X32 FILLCELL_X4 FILLCELL_X8. To specify a different naming prefix from FILLER_ use -prefix ." 128 | What is the significance of the filler_placement command?,"The filler_placement command fills gaps between detail-placed instances to connect the power and ground rails in the rows. filler_masters is a list of master/macro names to use for filling the gaps. Wildcard matching is supported, so FILL* will match, e.g., FILLCELL_X1 FILLCELL_X16 FILLCELL_X2 FILLCELL_X32 FILLCELL_X4 FILLCELL_X8. To specify a different naming prefix from FILLER_ use -prefix ." 129 | What is the significance of the filler_placement command?,The filler_placement command utilizes specified master names to fill gaps among placed instances for power and ground rail connectivity. It supports wildcard for master names selection and allows prefix customization with the -prefix option. 130 | What is the purpose of the remove_fillers command?,This command removes all filler cells. 131 | What does the remove_fillers command achieve?,This command removes all filler cells. 132 | What is the purpose of the remove_fillers command?,This command clears all placed filler cells. 133 | What does the check_placement command do?,The check_placement command checks the placement legality. It returns 0 if the placement is legal. 134 | What does the check_placement command verify?,The check_placement command checks the placement legality. It returns 0 if the placement is legal. 135 | What does the check_placement command do?,"The check_placement command verifies if the placement adheres to legality rules, returning 0 for a legal placement." 136 | What does the argument -verbose in the check_placement command do?,The -verbose argument enables verbose logging in the check_placement command. 137 | How does the -verbose argument in the check_placement command enhance its functionality?,The -verbose argument enables verbose logging in the check_placement command. 138 | What does the argument -verbose in the check_placement command do?,Enabling the -verbose argument within the check_placement command activates detailed logging. 139 | What does the argument -disallow_one_site_gaps in the check_placement command do?,The argument -disallow_one_site_gaps disables one site gap during placement check. 140 | What effect does the -disallow_one_site_gaps argument have in the check_placement command?,The argument -disallow_one_site_gaps disables one site gap during placement check. 141 | What does the argument -disallow_one_site_gaps in the check_placement command do?,The -disallow_one_site_gaps argument prevents gaps of one site in the placement legality check. 142 | What role does this argument -report_file_name play in the check_placement command?,The argument -report_file_name in check_placement command files name for saving the report (e.g. report.json). 143 | What information does the -report_file_name argument provide in the check_placement command?,The argument -report_file_name in check_placement command files name for saving the report (e.g. report.json). 144 | What role does this argument -report_file_name play in the check_placement command?,"Within the check_placement command, the -report_file_name argument designates the report's filename, such as report.json." 145 | What does the optimize_mirroring command do?,The optimize_mirroring command mirrors instances about the Y axis in a weak attempt to reduce the total half-perimeter wirelength (HPWL). No arguments are needed for this function. 146 | What optimizations does the optimize_mirroring command perform?,The optimize_mirroring command mirrors instances about the Y axis in a weak attempt to reduce the total half-perimeter wirelength (HPWL). No arguments are needed for this function. 147 | What does the optimize_mirroring command do?,"The optimize_mirroring command adjusts instances around the Y-axis to potentially lessen the total half-perimeter wirelength, requiring no additional arguments." 148 | What are some useful developer commands in the detailed placement module in OpenROAD (dpl)?,"If you are a developer, you might find the following commands useful, 1. detailed_placement_debug: debug detailed placement. 2. get_masters_arg: get masters from a design. 3. get_inst_bbox: get the bounding box of an instance. 4. get_inst_grid_bbox: get the grid bounding box of an instance. 5. format_grid: format grid (takes in length x and site width w as inputs). 6. get_row_site: get row site name." 149 | Can you list some advanced developer commands in the detailed placement module (dpl)?,"If you are a developer, you might find the following commands useful, 1. detailed_placement_debug: debug detailed placement. 2. get_masters_arg: get masters from a design. 3. get_inst_bbox: get the bounding box of an instance. 4. get_inst_grid_bbox: get the grid bounding box of an instance. 5. format_grid: format grid (takes in length x and site width w as inputs). 6. get_row_site: get row site name." 150 | What are some useful developer commands in the detailed placement module in OpenROAD (dpl)?,"Developers might find commands like detailed_placement_debug, get_masters_arg, get_inst_bbox, get_inst_grid_bbox, format_grid, get_row_site beneficial for various debugging and configuration tasks." 151 | What does the argument [-max_length ] do in the set_dft_config command of DFT- Design For Testing?,The argument [-max_length ] takes an integer as input for setting the maximum number of bits that can be in each scan chain. 152 | What does the [-max_length ] argument in the set_dft_config command control?,The argument [-max_length ] takes an integer as input for setting the maximum number of bits that can be in each scan chain. 153 | What does the argument [-max_length ] do in the set_dft_config command of DFT- Design For Testing?,The [-max_length ] argument sets a limit on the scan chain length in bits. 154 | What does the argument [-clock_mixing] do in the set_dft_config command of DFT?,The argument [-clock_mixing] dictates how the architect mixes the scan flops based on the clock driver. The value no_mix creates scan chains with only one type of clock and edge. This may create unbalanced chains. The value clock_mix creates scan chains mixing clocks and edges. Falling edge flops are going to be stitched before the rising edge. 155 | How does the [-clock_mixing] argument in the set_dft_config command affect DFT?,The argument [-clock_mixing] dictates how the architect mixes the scan flops based on the clock driver. The value no_mix creates scan chains with only one type of clock and edge. This may create unbalanced chains. The value clock_mix creates scan chains mixing clocks and edges. Falling edge flops are going to be stitched before the rising edge. 156 | What does the argument [-clock_mixing] do in the set_dft_config command of DFT?,"The [-clock_mixing] argument controls the scan flops' arrangement based on the clock driver, with options for mixing or separating clock types and edges." 157 | What does the report_dft_config command do in DFT- Design For Testing?,The report_dft_config command prints the current DFT configuration to be used by preview_dft and insert_dft. 158 | What insights does the report_dft_config command offer in DFT- Design For Testing?,The report_dft_config command prints the current DFT configuration to be used by preview_dft and insert_dft. 159 | What does the report_dft_config command do in DFT- Design For Testing?,The report_dft_config command outputs the current DFT setup for use in preview_dft and insert_dft. 160 | What does the preview_dft command do in DFT- Design For Testing?,This command prints a preview of the scan chains that will be stitched by insert_dft. Use this command to iterate and try different DFT configurations. This command does not perform any modification to the design. 161 | What preview does the preview_dft command provide in DFT- Design For Testing?,This command prints a preview of the scan chains that will be stitched by insert_dft. Use this command to iterate and try different DFT configurations. This command does not perform any modification to the design. 162 | What does the preview_dft command do in DFT- Design For Testing?,"This command offers a glimpse into the scan chains to be established by insert_dft, allowing for DFT configuration experimentation without altering the design." 163 | What does the argument [-verbose] do in the preview_dft command of DFT- Design For Testing?,The preview_dft command shows more information about each one of the scan chains that will be created. 164 | How does the [-verbose] argument in the preview_dft command enhance its output?,The preview_dft command shows more information about each one of the scan chains that will be created. 165 | What does the argument [-verbose] do in the preview_dft command of DFT- Design For Testing?,The preview_dft command provides detailed insights into the forthcoming scan chains. 166 | What does the insert_dft command do in DFT- Design For Testing?,"The insert_dft command implements the scan chains into the design by performing the following actions: Scan Replace, Scan Architect, Scan Stitch. The result is a design with scan flops connected to form the scan chains." 167 | What is the process of the insert_dft command in DFT- Design For Testing?,"The insert_dft command implements the scan chains into the design by performing the following actions: Scan Replace, Scan Architect, Scan Stitch. The result is a design with scan flops connected to form the scan chains." 168 | What does the insert_dft command do in DFT- Design For Testing?,"By executing actions like Scan Replace, Scan Architect, and Scan Stitch, the insert_dft command integrates scan chains into the design." 169 | Can you give me an example of a basic Design for Testing command?,Here is an example that will create scan chains with a max length of 10 bits mixing all the scan flops in the scan chains: set_dft_config -max_length 10 -clock_mixing clock_mix report_dft_config preview_dft -verbose insert_dft. 170 | Could you provide a basic example of a Design for Testing command?,Here is an example that will create scan chains with a max length of 10 bits mixing all the scan flops in the scan chains: set_dft_config -max_length 10 -clock_mixing clock_mix report_dft_config preview_dft -verbose insert_dft. 171 | Can you give me an example of a basic Design for Testing command?,An example command to create 10-bit long scan chains with mixed flops is: set_dft_config -max_length 10 -clock_mixing clock_mix report_dft_config preview_dft -verbose insert_dft. 172 | What are the limitations of Design for Testing (DFT)?,"The limitations of DFT-Design for Testing are as follows: there are no optimizations for the scan chains, this is a WIP, there is no way to specify existing scan ports to be used by scan insertion, there is currently no way to define a user-defined scan path, and can only work with one-bit cells." 173 | What are the known limitations of Design for Testing (DFT)?,"The limitations of DFT-Design for Testing are as follows: there are no optimizations for the scan chains, this is a WIP, there is no way to specify existing scan ports to be used by scan insertion, there is currently no way to define a user-defined scan path, and can only work with one-bit cells." 174 | What are the limitations of Design for Testing (DFT)?,"DFT limitations include the absence of scan chain optimizations, the inability to specify existing scan ports for insertion, the lack of a method for defining custom scan paths, and compatibility only with one-bit cells." 175 | What is the report_cts command in Clock Tree Synthesis (cst) in OpenROAD used for?,"It is used to extract metrics after a successful clock_tree_synthesis run. These metrics are the number of Clock Roots, number of Buffers Inserted, number of Clock Subnets, and number of Sinks." 176 | What is the purpose of the report_cts command in Clock Tree Synthesis (cts) in OpenROAD?,"It is used to extract metrics after a successful clock_tree_synthesis run. These metrics are the number of Clock Roots, number of Buffers Inserted, number of Clock Subnets, and number of Sinks." 177 | What is the report_cts command in Clock Tree Synthesis (cst) in OpenROAD used for?,"After running clock_tree_synthesis, use this to collect metrics such as the number of Clock Roots, Buffers Inserted, Clock Subnets, and Sinks." 178 | What does the argument -out_file in report_cts command in Clock Tree Synthesis (cst) in OpenROAD do?,"The file to save cts reports. If this parameter is omitted, the report is streamed to stdout and not saved." 179 | What does the -out_file argument in the report_cts command achieve?,"The file to save cts reports. If this parameter is omitted, the report is streamed to stdout and not saved." 180 | What does the argument -out_file in report_cts command in Clock Tree Synthesis (cst) in OpenROAD do?,"Specifies the file for saving cts reports, defaulting to streaming to stdout if not provided." 181 | What does the clock_tree_synthesis_debug command in Clock Tree Synthesis (cst) in OpenROAD do?,This command is an option to plot the CTS to GUI. 182 | How does the clock_tree_synthesis_debug command assist in CST troubleshooting?,This command is an option to plot the CTS to GUI. 183 | What does the clock_tree_synthesis_debug command in Clock Tree Synthesis (cst) in OpenROAD do?,This command allows for CTS visualization in the GUI. 184 | What does the create_power_domain command do in upf?,This command creates power domain for a group of modules. 185 | What does the create_power_domain command achieve in upf?,This command creates power domain for a group of modules. 186 | What does the create_power_domain command do in upf?,Creates power domain for module groups. 187 | What does the create_logic_port command do in upf?,"This command creates logic port. Direction must be specified from: in, out, inout." 188 | What function does the create_logic_port command serve in upf?,"This command creates logic port. Direction must be specified from: in, out, inout." 189 | What does the create_logic_port command do in upf?,Creates logic ports with specified directions. -------------------------------------------------------------------------------- /Augmented_Data/Question-Answer/General/General.csv: -------------------------------------------------------------------------------- 1 | Prompts,Answers 2 | What is PDNGEN?,"The PDNGEN module (pdn) in OpenROAD aims to simplify the process of adding a power grid into a floorplan. A user can specify a small set of power grid policies to be applied to the design, such as the layers to use, stripe width, and spacing, and then pdn will generate the actual metal straps. Power grid policies can be defined over both the standard cell area and areas occupied by macros." 3 | What is the essence of PDNGEN?,"The PDNGEN module (pdn) in OpenROAD aims to simplify the process of adding a power grid into a floorplan. A user can specify a small set of power grid policies to be applied to the design, such as the layers to use, stripe width, and spacing, and then pdn will generate the actual metal straps. Power grid policies can be defined over both the standard cell area and areas occupied by macros." 4 | What is PDNGEN?,"OpenROAD's Power Distribution Network Generator (PDNGEN) module, abbreviated as pdn, streamlines the integration of a power grid into a design's floorplan. Users can establish a few power grid guidelines, such as selecting layers, setting stripe width, and spacing, after which pdn automatically constructs the metal straps. These guidelines can be applied across both the standard cell region and macro-occupied areas." 5 | What is the structure of OpenDB?,The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library-style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures. 6 | Can you describe the architecture of OpenDB?,The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library-style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures. 7 | What is the structure of OpenDB?,"OpenDB's architecture mirrors the LEF (Library Exchange Format) and DEF (Design Exchange Format) text file standards version 5.6, supporting a binary file format for quicker design saving and loading than possible with LEF and DEF. Written in C++ 98, OpenDB employs standard library-style iterators and classes designed for rapid operation, obviating the need for copying into specific application structures." 8 | How is FastRoute better than previous routing frameworks?,"FastRoute innovates over prior routing frameworks because it integrates several novel techniques: fast congestion-driven via-aware Steiner tree construction, 3-bend routing, virtual capacity adjustment, multi-source multi-sink maze routing, and spiral layer assignment. These techniques not only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength and via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that FastRoute is highly effective and efficient in solving ISPD07 and ISPD08 global routing benchmark suites. The results outperform recently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing benchmarks, FastRoute generates 12 congestion-free solutions out of 16 benchmarks with a speed significantly faster than other routers." 9 | In what ways is FastRoute superior to its predecessors in routing frameworks?,"FastRoute innovates over prior routing frameworks because it integrates several novel techniques: fast congestion-driven via-aware Steiner tree construction, 3-bend routing, virtual capacity adjustment, multi-source multi-sink maze routing, and spiral layer assignment. These techniques not only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength and via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that FastRoute is highly effective and efficient in solving ISPD07 and ISPD08 global routing benchmark suites. The results outperform recently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing benchmarks, FastRoute generates 12 congestion-free solutions out of 16 benchmarks with a speed significantly faster than other routers." 10 | How is FastRoute better than previous routing frameworks?,"FastRoute distinguishes itself from previous routing frameworks by integrating innovative approaches such as fast congestion-driven via-aware Steiner tree construction, 3-bend routing, virtual capacity adjustment, multi-source multi-sink maze routing, and spiral layer assignment. These methods tackle routing congestion at global routing grid edges and aim to minimize overall wirelength and via count, vital for detailed routing, yield, and manufacturability. According to tests, FastRoute excels in efficiency and effectiveness across ISPD07 and ISPD08 global routing benchmarks, outperforming contemporary academic routers in routability and speed, delivering congestion-free outcomes for 12 out of 16 benchmarks." 11 | What does RTLMP do?,"A macro placer (MP) is an algorithm which specifically focuses on placing macros in the core area. RTL­MP is a novel macro placer that utilizes RTL information and tries to “mimic” the interaction between the frontend RTL designer and the back­ end physical design engineer to produce human­-quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures, RTL­MP can capture the dataflow inherent in the RTL and use the dataflow information to guide macro placement." 12 | What tasks does RTLMP accomplish?,"A macro placer (MP) is an algorithm which specifically focuses on placing macros in the core area. RTL­MP is a novel macro placer that utilizes RTL information and tries to “mimic” the interaction between the frontend RTL designer and the back­ end physical design engineer to produce human­-quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures, RTL­MP can capture the dataflow inherent in the RTL and use the dataflow information to guide macro placement." 13 | What does RTLMP do?,"A macro placer (MP) specifically targets macro placement within the core area. The novel RTL­MP leverages RTL data to emulate the collaborative process between frontend RTL designers and backend physical design engineers, producing floorplans of comparable quality to human-generated ones. By analyzing logical hierarchies and connections, RTL­MP captures the RTL's inherent data flow to inform its macro placement strategy." 14 | What was the need to develop Hier-RTLMP?,"Recently, with the increasing complexity of IP blocks, and in particular with auto-generated RTL for machine learning (ML) accelerators, the number of macros in a single RTL block can easily run into several hundred. This makes the task of generating an automatic floorplan (.def) with IO pin and macro placements for front-end physical synthesis even more critical and challenging. The so-called peripheral approach of forcing macros to the periphery of the layout is no longer viable when the ratio of the sum of the macro perimeters to the floorplan perimeter is large since this increases the required stacking depth of macros. Thus, a novel multilevel physical planning approach that exploits the hierarchy and dataflow inherent in the design RTL, and describes its realization in a new hierarchical macro placer, Hier-RTLMP was developed. " 15 | What prompted the creation of Hier-RTLMP?,"Recently, with the increasing complexity of IP blocks, and in particular with auto-generated RTL for machine learning (ML) accelerators, the number of macros in a single RTL block can easily run into several hundred. This makes the task of generating an automatic floorplan (.def) with IO pin and macro placements for front-end physical synthesis even more critical and challenging. The so-called peripheral approach of forcing macros to the periphery of the layout is no longer viable when the ratio of the sum of the macro perimeters to the floorplan perimeter is large since this increases the required stacking depth of macros. Thus, a novel multilevel physical planning approach that exploits the hierarchy and dataflow inherent in the design RTL, and describes its realization in a new hierarchical macro placer, Hier-RTLMP was developed. " 16 | What was the need to develop Hier-RTLMP?,"The increasing complexity of IP blocks, especially auto-generated RTL for machine learning (ML) accelerators, has led to designs with hundreds of macros. This escalates the difficulty of automatically generating a floorplan (.def) that includes IO pin and macro placements for front-end physical synthesis. The traditional peripheral placement strategy becomes impractical when the macro perimeter sum greatly exceeds the floorplan's perimeter, necessitating a novel multilevel physical planning approach. This approach, realized in the Hier-RTLMP, leverages design RTL's inherent hierarchy and data flow for effective macro placement." 17 | How is Hier-RTLMP different from RTL-MP?,"Hier-RTLMP consists of an auto-clustering engine that transforms the logical hierarchy into a physical hierarchy. Unlike RTL-MP where the physical hierarchy is a single level, Hier-RTLMP’s autoclustering engine creates a multilevel physical hierarchy of physical clusters. This enables the handling of large RTLs with hundreds of macros and allows for the placement of macros within the core area." 18 | In what aspects does Hier-RTLMP diverge from RTL-MP?,"Hier-RTLMP consists of an auto-clustering engine that transforms the logical hierarchy into a physical hierarchy. Unlike RTL-MP where the physical hierarchy is a single level, Hier-RTLMP’s autoclustering engine creates a multilevel physical hierarchy of physical clusters. This enables the handling of large RTLs with hundreds of macros and allows for the placement of macros within the core area." 19 | How is Hier-RTLMP different from RTL-MP?,"Hier-RTLMP introduces an auto-clustering engine that converts logical hierarchies into a multilevel physical structure. Unlike the single-level physical hierarchy in RTL-MP, Hier-RTLMP's engine facilitates managing extensive RTL designs with numerous macros, allowing for their strategic placement within the core area." 20 | How does FastRoute work?,"The first part of the FastRoute framework is topology generation. Because FastRoute tries to avoid rip-up and reroute to reduce both wirelength and runtime, the initial tree topology has significant impacts. With the congestion-driven and via-aware topology, the next stage of FastRoute is actual routing. We find that there exists significant potential to improve traditional routing techniques in terms of via control and congestion reduction. The most commonly used routing techniques in global routing include L/Z/U pattern routing, monotonic routing, and maze routing. In addition to new topology and routing techniques, Fast Route integrates several performance enhancement techniques to further improve routing quality and reduce run time." 21 | Can you explain the operating principle of FastRoute?,"The first part of the FastRoute framework is topology generation. Because FastRoute tries to avoid rip-up and reroute to reduce both wirelength and runtime, the initial tree topology has significant impacts. With the congestion-driven and via-aware topology, the next stage of FastRoute is actual routing. We find that there exists significant potential to improve traditional routing techniques in terms of via control and congestion reduction. The most commonly used routing techniques in global routing include L/Z/U pattern routing, monotonic routing, and maze routing. In addition to new topology and routing techniques, Fast Route integrates several performance enhancement techniques to further improve routing quality and reduce run time." 22 | How does FastRoute work?,"FastRoute's framework begins with topology generation, aiming to minimize rip-up and reroute actions to reduce wirelength and runtime. The initial tree topology, based on congestion-driven and via-aware principles, sets the stage for the routing phase, which shows significant improvement opportunities over traditional methods in terms of via management and congestion alleviation. Besides innovative topology and routing strategies, FastRoute incorporates various performance-boosting techniques to enhance routing quality and efficiency." 23 | Why is RSMT used more?,"Traditionally, global routing just uses tree structures like RMST or RSMT while RSMT is becoming more popular due to its minimal wirelength to connect a multi-pin net." 24 | Why is RSMT favored over other methods?,"Traditionally, global routing just uses tree structures like RMST or RSMT while RSMT is becoming more popular due to its minimal wirelength to connect a multi-pin net." 25 | Why is RSMT used more?,"Global routing traditionally utilizes tree structures such as RMST or RSMT, with RSMT growing in preference due to its efficiency in connecting multi-pin nets with minimal wirelength." 26 | "Tab completion does work in console mode but not in GUI mode, why?","The OpenROAD GUI is made from custom Qt code and does not apply to the console. OpenROAD relies on the tclreadline package, which doesn't work well with imported namespaces." 27 | Why does tab completion function in console mode but fail in GUI mode?,"The OpenROAD GUI is made from custom Qt code and does not apply to the console. OpenROAD relies on the tclreadline package, which doesn't work well with imported namespaces." 28 | "Tab completion does work in console mode but not in GUI mode, why?","The OpenROAD GUI is built using custom Qt programming and is not applicable to command-line operations. It utilizes the tclreadline package, which faces compatibility issues with imported namespaces." 29 | What is OpenDB?,"OpenDB is a design database to support tools for physical chip design. It was originally developed by Athena Design Systems. Nefelus, Inc. acquired the rights to the code and open-sourced it with BSD-3 license in 2019 to support the DARPA OpenROAD project. The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures." 30 | What is the role of OpenDB?,"OpenDB is a design database to support tools for physical chip design. It was originally developed by Athena Design Systems. Nefelus, Inc. acquired the rights to the code and open-sourced it with BSD-3 license in 2019 to support the DARPA OpenROAD project. The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures." 31 | What is OpenDB?,"OpenDB, originally developed by Athena Design Systems and later open-sourced by Nefelus, Inc. under a BSD-3 license for the DARPA OpenROAD project in 2019, serves as a database for physical chip design, utilizing LEF and DEF formats version 5.6 and supporting a binary format for efficient design loading and saving." 32 | What is Automatic Code Generator used for?,The automatic code generator in OpenROAD is used to generate code for OpenDB objects and Iterators. It uses JSON input and automatically generates corresponding C++ files 33 | What is the purpose behind the Automatic Code Generator?,The automatic code generator in OpenROAD is used to generate code for OpenDB objects and Iterators. It uses JSON input and automatically generates corresponding C++ files 34 | What is Automatic Code Generator used for?,"OpenROAD's automatic code generator produces C++ files for OpenDB objects and iterators from JSON input, streamlining code generation." 35 | What commands are used to read and write design data in OpenROAD?,"OpenROAD is run using Tcl scripts. The following commands are used to read and write design data. 36 | read_lef [-tech] [-library] filename 37 | read_def filename 38 | write_def [-version 5.8|5.7|5.6|5.5|5.4|5.3] filename 39 | read_verilog filename 40 | write_verilog filename 41 | read_db filename 42 | write_db filename 43 | write_abstract_lef filename" 44 | "What support does OpenROAD have for Abstract LEF? 45 | ",OpenROAD contains an abstract LEF writer that can take your current design and emit an abstract LEF representing the external pins of your design and metal obstructions. Use the write_abstract_lef command to generate the abstract LEF. 46 | How does OpenROAD support Abstract LEF?,OpenROAD contains an abstract LEF writer that can take your current design and emit an abstract LEF representing the external pins of your design and metal obstructions. Use the write_abstract_lef command to generate the abstract LEF. 47 | "What support does OpenROAD have for Abstract LEF? 48 | ","The abstract LEF writer in OpenROAD allows for the creation of an abstract LEF from your design, detailing external pins and metal obstructions, using the write_abstract_lef command." 49 | How does OpenROAD compute the die area when using the core_utilization argument in the initialize_floorplan?,"To compute the die area for the initialize_floorplan command, OpenROAD first calculates the core area by dividing the total logic area of the instances coming from synthesis and by the specified core_utilization. OpenROAD then shapes that core area based on the aspect_ratio parameter. Finally, OpenROAD expands the core area by adding a core margin on each edge of the core area. Altogether, this forms the die area." 50 | How does OpenROAD determine die area with the core_utilization argument during floorplan initialization?,"To compute the die area for the initialize_floorplan command, OpenROAD first calculates the core area by dividing the total logic area of the instances coming from synthesis and by the specified core_utilization. OpenROAD then shapes that core area based on the aspect_ratio parameter. Finally, OpenROAD expands the core area by adding a core margin on each edge of the core area. Altogether, this forms the die area." 51 | How does OpenROAD compute the die area when using the core_utilization argument in the initialize_floorplan?,"To calculate die area, OpenROAD first determines the core area by dividing the total logic area by the core utilization, shapes this area using the aspect ratio, and then expands it by adding core margins, resulting in the die area." 52 | I would like to know if there is any way to write the log output from OpenROAD into a file (using a report_ type command)?,"To capture output from OpenROAD, you can use standard Unix file operations and redirections. OpenROAD outputs all messages directly to the stdout I/O stream." 53 | Is there a method to direct OpenROAD's log output to a file?,"To capture output from OpenROAD, you can use standard Unix file operations and redirections. OpenROAD outputs all messages directly to the stdout I/O stream." 54 | I would like to know if there is any way to write the log output from OpenROAD into a file (using a report_ type command)?,"Capturing OpenROAD output can be done using standard Unix redirections, as it sends all messages directly to the stdout stream." 55 | What is the minimum number of metal layers OpenROAD can route in?,"OpenROAD has the theoretical ability to route as few as two layers, but it has rarely been tried by the developers due to the lack of a specialized channel router. It is expected that OpenROAD will hit some issues and have to iterate. If you try this and run into issues, please kindly file an issue on GitHub. However, if the PDK is proprietary, it will be more difficult for the OpenROAD team to diagnose and debug." 56 | What is the minimum metal layer count that OpenROAD can handle for routing?,"OpenROAD has the theoretical ability to route as few as two layers, but it has rarely been tried by the developers due to the lack of a specialized channel router. It is expected that OpenROAD will hit some issues and have to iterate. If you try this and run into issues, please kindly file an issue on GitHub. However, if the PDK is proprietary, it will be more difficult for the OpenROAD team to diagnose and debug." 57 | What is the minimum number of metal layers OpenROAD can route in?,"OpenROAD theoretically can route with as few as two layers, but this is rarely tested and may encounter issues, for which feedback on GitHub is appreciated, especially for proprietary PDKs." 58 | "Can OpenROAD work with multi-VT cells (HVT, LVT, SVT) and swap between them in a single run?","OpenROAD supports using multi-VT cell libraries, and it can swap between VT cells during optimization." 59 | Can OpenROAD manage cells with different threshold voltages within a single run?,"OpenROAD supports using multi-VT cell libraries, and it can swap between VT cells during optimization." 60 | "Can OpenROAD work with multi-VT cells (HVT, LVT, SVT) and swap between them in a single run?","OpenROAD allows the use of multi-VT cell libraries, enabling swapping between VT cells during optimization phases." 61 | Can OpenROAD work with Multi-Mode-Multi-Corner Files (mmmc) ?,"OpenROAD supports multi-corner Static Timing Analysis (STA), but it doesn't currently support multi-mode STA. ""MMMC"" files from proprietary tools are stored in proprietary formats, which OpenROAD cannot support. The OpenSTA manual will contain more information about how to run multi-corner analysis." 62 | Is OpenROAD compatible with Multi-Mode-Multi-Corner Files?,"OpenROAD supports multi-corner Static Timing Analysis (STA), but it doesn't currently support multi-mode STA. ""MMMC"" files from proprietary tools are stored in proprietary formats, which OpenROAD cannot support. The OpenSTA manual will contain more information about how to run multi-corner analysis." 63 | Can OpenROAD work with Multi-Mode-Multi-Corner Files (mmmc) ?,"While OpenROAD supports multi-corner Static Timing Analysis, it does not yet accommodate multi-mode STA due to proprietary format constraints of ""MMMC"" files." 64 | What does Antenna Rule Checker do?,"This tool checks antenna violations and generates a report to indicate violated nets. See LEF/DEF 5.8 Language Reference, Appendix C, ""Calculating and Fixing Process Antenna Violations"" (p.389) for a description of antenna violations." 65 | How does the Antenna Rule Checker contribute to design integrity?,"This tool checks antenna violations and generates a report to indicate violated nets. See LEF/DEF 5.8 Language Reference, Appendix C, ""Calculating and Fixing Process Antenna Violations"" (p.389) for a description of antenna violations." 66 | What does Antenna Rule Checker do?,"The tool checks for antenna violations and reports nets that violate these rules, with guidance found in the LEF/DEF 5.8 Language Reference." 67 | What is Clock Tree Synthesis in OpenROAD?,"Clock tree synthesis (CTS) is the step of distributing a clock to all endpoints (such as flip-flops) while trying to minimize power and skew (the different in clock arrival times between two registers). The clock tree synthesis module in OpenROAD (cts) is based on TritonCTS 2.0, and can be run using the clock_tree_synthesis command. TritonCTS 2.0 features on-the-fly characterization, and therefore does not need to pre-generate characterization data. The on-the-fly characterization feature can be optionally controlled by parameters specified by the configure_cts_characterization command. You can use the set_wire_rc command to set the clock routing layer used when calculating parasitics in this step." 68 | What entails Clock Tree Synthesis in OpenROAD?,"Clock tree synthesis (CTS) is the step of distributing a clock to all endpoints (such as flip-flops) while trying to minimize power and skew (the different in clock arrival times between two registers). The clock tree synthesis module in OpenROAD (cts) is based on TritonCTS 2.0, and can be run using the clock_tree_synthesis command. TritonCTS 2.0 features on-the-fly characterization, and therefore does not need to pre-generate characterization data. The on-the-fly characterization feature can be optionally controlled by parameters specified by the configure_cts_characterization command. You can use the set_wire_rc command to set the clock routing layer used when calculating parasitics in this step." 69 | What is Clock Tree Synthesis in OpenROAD?,"Clock tree synthesis in OpenROAD, facilitated by TritonCTS 2.0, distributes clock signals to endpoints while minimizing power and skew, offering on-the-fly characterization to avoid pre-generated data needs." 70 | Tell me about Detailed Placement in OpenROAD?,"The detailed placement module in OpenROAD (dpl) is based on OpenDP or Open-Source Detailed Placement Engine. Its key features are 71 | fence region and fragmented ROWs." 72 | What does Detailed Placement involve in OpenROAD?,"The detailed placement module in OpenROAD (dpl) is based on OpenDP or Open-Source Detailed Placement Engine. Its key features are 73 | fence region and fragmented ROWs." 74 | Tell me about Detailed Placement in OpenROAD?,"The detailed placement module, based on OpenDP, focuses on fence regions and fragmented rows for placement optimization." 75 | Describe the Restructure module in OpenROAD?,The restructure module in OpenROAD (rmp) is based on an interface to ABC for local resynthesis. The package allows logic restructuring that targets area or timing. It extracts a cloud of logic using the OpenSTA timing engine and passes it to ABC through the blif interface. Multiple recipes for area or timing are run to obtain multiple structures from ABC; the most desirable among these is used to improve the netlist. The ABC output is read back by a blif reader which is integrated into OpenDB. Blif writer and reader also support constants from and to OpenDB. Reading back of constants requires insertion of tie cells which should be provided by the user as per the interface described below. 76 | Can you outline the Restructure module's role in OpenROAD?,The restructure module in OpenROAD (rmp) is based on an interface to ABC for local resynthesis. The package allows logic restructuring that targets area or timing. It extracts a cloud of logic using the OpenSTA timing engine and passes it to ABC through the blif interface. Multiple recipes for area or timing are run to obtain multiple structures from ABC; the most desirable among these is used to improve the netlist. The ABC output is read back by a blif reader which is integrated into OpenDB. Blif writer and reader also support constants from and to OpenDB. Reading back of constants requires insertion of tie cells which should be provided by the user as per the interface described below. 77 | Describe the Restructure module in OpenROAD?,"The restructure module interfaces with ABC for logic resynthesis aimed at area or timing improvement, utilizing OpenSTA for logic extraction and integrating ABC's output through OpenDB's blif reader and writer." 78 | Describe Parallax Static Timing Analyzer or OpenSTA?,"OpenSTA is a gate-level static timing verifier. As a stand-alone executable, it can be used to verify the timing of a design using standard file formats. OpenSTA uses a TCL command interpreter to read the design, specify timing constraints, and print timing reports." 79 | What capabilities does the Parallax Static Timing Analyzer offer?,"OpenSTA is a gate-level static timing verifier. As a stand-alone executable, it can be used to verify the timing of a design using standard file formats. OpenSTA uses a TCL command interpreter to read the design, specify timing constraints, and print timing reports." 80 | Describe Parallax Static Timing Analyzer or OpenSTA?,"OpenSTA performs gate-level static timing analysis, using TCL for design reading, timing constraints specification, and timing report generation." 81 | What is DFT?,This tool is an implementation of Design For Testing. New nets and logic are added to allow IC designs to be tested for errors in manufacturing. Physical imperfections can cause hard failures and variability can cause timing errors. 82 | Can you elaborate on DFT?,This tool is an implementation of Design For Testing. New nets and logic are added to allow IC designs to be tested for errors in manufacturing. Physical imperfections can cause hard failures and variability can cause timing errors. 83 | What is DFT?,"This tool implements Design For Testing (DFT) by introducing new nets and logic, facilitating the testing of IC designs for manufacturing errors. It addresses physical defects and variability, which can lead to hard failures and timing errors, respectively." 84 | What is Read UPF Utility?,"This module contains functionality to read, and modify information from Unified Power Format (UPF) files." 85 | What functionality does the Read UPF Utility offer?,"This module contains functionality to read, and modify information from Unified Power Format (UPF) files." 86 | What is Read UPF Utility?,This module offers tools to access and alter information within Unified Power Format (UPF) files. 87 | Explain Chip-level Connections in OpenROAD?,"The chip-level connections module in OpenROAD (pad) is based on the open-source tool ICeWall. In this utility, either place an IO ring around the boundary of the chip and connect with either wirebond pads or a bump array." 88 | How are chip-level connections managed in OpenROAD?,"The chip-level connections module in OpenROAD (pad) is based on the open-source tool ICeWall. In this utility, either place an IO ring around the boundary of the chip and connect with either wirebond pads or a bump array." 89 | Explain Chip-level Connections in OpenROAD?,"OpenROAD's chip-level connections module (pad) utilizes the open-source ICeWall tool to place an IO ring around the chip's boundary, connecting through wirebond pads or a bump array." 90 | Brief me on the parasitics extraction module?,"The parasitics extraction module in OpenROAD (rcx) is based on the open-source OpenRCX, a Parasitic Extraction (PEX, or RCX) tool that works on OpenDB design APIs. It extracts routed designs based on the LEF/DEF layout model. 91 | OpenRCX extracts both Resistance and Capacitance for wires, based on coupling distance to the nearest wire and the track density context over and/or under the wire of interest, as well as cell abstracts. The capacitance and resistance measurements are based on equations of coupling distance interpolated on exact measurements from a calibration file, called the Extraction Rules file. The Extraction Rules file (RC technology file) is generated once for every process node and corner, using a provided utility for DEF wire pattern generation and regression modeling. 92 | OpenRCX stores resistance, coupling capacitance, and ground (i.e., grounded) capacitance on OpenDB objects with direct pointers to the associated wire and via db objects. Optionally, OpenRCX can generate a .spef file." 93 | Can you brief me on the parasitics extraction module?,"The parasitics extraction module in OpenROAD (rcx) is based on the open-source OpenRCX, a Parasitic Extraction (PEX, or RCX) tool that works on OpenDB design APIs. It extracts routed designs based on the LEF/DEF layout model. 94 | OpenRCX extracts both Resistance and Capacitance for wires, based on coupling distance to the nearest wire and the track density context over and/or under the wire of interest, as well as cell abstracts. The capacitance and resistance measurements are based on equations of coupling distance interpolated on exact measurements from a calibration file, called the Extraction Rules file. The Extraction Rules file (RC technology file) is generated once for every process node and corner, using a provided utility for DEF wire pattern generation and regression modeling. 95 | OpenRCX stores resistance, coupling capacitance, and ground (i.e., grounded) capacitance on OpenDB objects with direct pointers to the associated wire and via db objects. Optionally, OpenRCX can generate a .spef file." 96 | Brief me on the parasitics extraction module?,"The parasitics extraction module in OpenROAD, based on OpenRCX, performs parasitic extraction on routed designs using the LEF/DEF model. It calculates wire resistance and capacitance by considering coupling distance and track density, utilizing a calibration file for accurate measurements. OpenRCX can also produce a .spef file for further analysis." 97 | What is global routing?,"The global routing module in OpenROAD (grt) is based on FastRoute, an open-source global router originally derived from Iowa State University's FastRoute4.1 algorithm. Global routing is responsible for creating routing guides for each net to simplify the job of the detailed router. The purpose of global routing is mainly to avoid overcongestion when creating the guides." 98 | Can you explain global routing and its importance?,"The global routing module in OpenROAD (grt) is based on FastRoute, an open-source global router originally derived from Iowa State University's FastRoute4.1 algorithm. Global routing is responsible for creating routing guides for each net to simplify the job of the detailed router. The purpose of global routing is mainly to avoid overcongestion when creating the guides." 99 | What is global routing?,"OpenROAD's global routing module, built on the FastRoute algorithm, creates routing guides for each net to manage congestion during detailed routing, aiming to prevent overcongestion." 100 | Which environment is required for setting up OpenROAD flow scripts?,You can use the bash shell to run commands and scripts. 101 | What setup is necessary for OpenROAD flow scripts?,You can use the bash shell to run commands and scripts. 102 | Which environment is required for setting up OpenROAD flow scripts?,The bash shell facilitates command and script execution. 103 | What are the ways of installing OpenROAD flow scripts/ ORFS?,"These are the ways of installing OpenROAD flow scripts/ ORFS: Docker, Pre-built Binaries, Windows Subsystem for Linux (WSL), and Local Installation." 104 | What installation methods exist for OpenROAD flow scripts/ORFS?,"These are the ways of installing OpenROAD flow scripts/ ORFS: Docker, Pre-built Binaries, Windows Subsystem for Linux (WSL), and Local Installation." 105 | What are the ways of installing OpenROAD flow scripts/ ORFS?,"OpenROAD flow scripts can be installed via Docker, Pre-built Binaries, WSL, or Local Installation." 106 | What is the basic build command for OpenROAD flow scripts/ ORFS?,The basic basic build command in ORFS is ./build_openroad.sh --help. 107 | What is the fundamental build command for OpenROAD flow scripts/ORFS?,The basic basic build command in ORFS is ./build_openroad.sh --help. 108 | What is the basic build command for OpenROAD flow scripts/ ORFS?,The fundamental ORFS build command is ./build_openroad.sh --help. 109 | What is OpenROAD?,"The OpenROAD (""Foundations and Realization of Open, Accessible Design"") Project was launched in June 2018 within the DARPA IDEA program. OpenROAD aims to bring down the barriers of cost, expertise, and unpredictability that currently block designers' access to hardware implementation in advanced technologies. The project team is developing a fully autonomous, open-source toolchain for digital SoC layout generation, focusing on the RTL-to-GDSII phase of system-on-chip design. Thus, OpenROAD holistically attacks the multiple facets of today's design cost crisis: engineering resources, design tool licenses, project schedule, and risk." 110 | Can you provide an overview of OpenROAD and its functionalities?,"The OpenROAD (""Foundations and Realization of Open, Accessible Design"") Project was launched in June 2018 within the DARPA IDEA program. OpenROAD aims to bring down the barriers of cost, expertise, and unpredictability that currently block designers' access to hardware implementation in advanced technologies. The project team is developing a fully autonomous, open-source toolchain for digital SoC layout generation, focusing on the RTL-to-GDSII phase of system-on-chip design. Thus, OpenROAD holistically attacks the multiple facets of today's design cost crisis: engineering resources, design tool licenses, project schedule, and risk." 111 | What is OpenROAD?,"Launched in June 2018 under DARPA's IDEA program, the OpenROAD (""Foundations and Realization of Open, Accessible Design"") Project aims to democratize access to hardware implementation in cutting-edge technologies by developing a fully autonomous, open-source toolchain for digital SoC layout from RTL-to-GDSII. This initiative addresses the design cost crisis from various angles, including engineering resources, tool licenses, project timelines, and risk." 112 | What is AutoTuner?,"AutoTuner is a ""no-human-in-loop"" parameter tuning framework for commercial and academic RTL-to-GDS flows. AutoTuner provides a generic interface where users can define parameter configuration as JSON objects. This enables AutoTuner to easily support various tools and flows. AutoTuner also utilizes METRICS2.1 to capture PPA of individual search trials. With the abundant features of METRICS2.1, users can explore various reward functions that steer the flow autotuning to different PPA goals." 113 | What is AutoTuner and its purpose in OpenROAD?,"AutoTuner is a ""no-human-in-loop"" parameter tuning framework for commercial and academic RTL-to-GDS flows. AutoTuner provides a generic interface where users can define parameter configuration as JSON objects. This enables AutoTuner to easily support various tools and flows. AutoTuner also utilizes METRICS2.1 to capture PPA of individual search trials. With the abundant features of METRICS2.1, users can explore various reward functions that steer the flow autotuning to different PPA goals." 114 | What is AutoTuner?,"AutoTuner, a ""no-human-in-loop"" framework, facilitates parameter tuning across commercial and academic RTL-to-GDS flows. It employs a generic interface for parameter configurations via JSON objects and leverages METRICS2.1 to evaluate PPA across trials, supporting the exploration of diverse PPA-optimizing reward functions." 115 | WHat are the current supported search algorithms by AutoTuner?,"AutoTuner contains top-level Python script for ORFS, each of which implements a different search algorithm. Current supported search algorithms are as follows: 116 | Random/Grid Search, Population Based Training (PBT), Tree Parzen Estimator (HyperOpt), Bayesian + Multi-Armed Bandit (AxSearch), Tree Parzen Estimator + Covariance Matrix Adaptation Evolution Strategy (Optuna), Evolutionary Algorithm (Nevergrad)" 117 | Which search algorithms are currently supported by AutoTuner?,"AutoTuner contains top-level Python script for ORFS, each of which implements a different search algorithm. Current supported search algorithms are as follows: 118 | Random/Grid Search, Population Based Training (PBT), Tree Parzen Estimator (HyperOpt), Bayesian + Multi-Armed Bandit (AxSearch), Tree Parzen Estimator + Covariance Matrix Adaptation Evolution Strategy (Optuna), Evolutionary Algorithm (Nevergrad)" 119 | WHat are the current supported search algorithms by AutoTuner?,"AutoTuner incorporates a top-level Python script for ORFS, offering various search algorithms like Random/Grid Search, Population Based Training (PBT), Tree Parzen Estimator (HyperOpt), Bayesian + Multi-Armed Bandit (AxSearch), Tree Parzen Estimator + Covariance Matrix Adaptation Evolution Strategy (Optuna), and Evolutionary Algorithm (Nevergrad)." 120 | How to set the direction of tuning in AutoTuner?,"User-defined coefficient values (coeff_perform, coeff_power, coeff_area) of three objectives to set the direction of tuning are written in the script. Each coefficient is expressed as a global variable at the get_ppa function in PPAImprov class in the script (coeff_perform, coeff_power, coeff_area). Efforts to optimize each of the objectives are proportional to the specified coefficients." 121 | How can the tuning direction be set in AutoTuner?,"User-defined coefficient values (coeff_perform, coeff_power, coeff_area) of three objectives to set the direction of tuning are written in the script. Each coefficient is expressed as a global variable at the get_ppa function in PPAImprov class in the script (coeff_perform, coeff_power, coeff_area). Efforts to optimize each of the objectives are proportional to the specified coefficients." 122 | How to set the direction of tuning in AutoTuner?,"In AutoTuner, user-defined coefficient values (coeff_perform, coeff_power, coeff_area) direct the tuning efforts towards optimizing performance, power, and area. These coefficients are globally declared in the PPAImprov class's get_ppa function." 123 | What environment is required for AutoTuner?,"To set up AutoTuner, make sure you have a virtual environment set up with Python 3.9.X. There are plenty of ways to do this, we recommend using Miniconda, which is a free minimal installer for the package manager conda." 124 | What environment is necessary for operating AutoTuner?,"To set up AutoTuner, make sure you have a virtual environment set up with Python 3.9.X. There are plenty of ways to do this, we recommend using Miniconda, which is a free minimal installer for the package manager conda." 125 | What environment is required for AutoTuner?,"To initiate AutoTuner, ensure the setup of a virtual environment using Python 3.9.X, with Miniconda recommended for managing the environment." 126 | Which parameters/variables can be used for tune or sweep?,Any variable that can be set from the command line can be used for tune or sweep. 127 | What parameters or variables can be tuned or swept in AutoTuner?,Any variable that can be set from the command line can be used for tune or sweep. 128 | Which parameters/variables can be used for tune or sweep?,Variables settable via command line can be employed for tuning or sweeping parameters. 129 | How to add verilog designs to ORFS repository for a full RTL-GDS flow execution?,The following design example is based on the design spm that implements a Single-port memory using gf180 platform. This procedure applies to any design for a given platform you choose. Start from the base directory OpenROAD-flow-scripts/flow. Step 1: Create the Verilog source files directory based on the top module name. Step 2: Create config.mk to define design configuration. Step 3: Define key design parameters in config.mk. Step 4: Define SDC constraints. Step 5: Add the design name to Makefile to run the flow with the make command. 130 | How can Verilog designs be added to the ORFS repository for complete RTL-GDSII flow execution?,The following design example is based on the design spm that implements a Single-port memory using gf180 platform. This procedure applies to any design for a given platform you choose. Start from the base directory OpenROAD-flow-scripts/flow. Step 1: Create the Verilog source files directory based on the top module name. Step 2: Create config.mk to define design configuration. Step 3: Define key design parameters in config.mk. Step 4: Define SDC constraints. Step 5: Add the design name to Makefile to run the flow with the make command. 131 | How to add verilog designs to ORFS repository for a full RTL-GDS flow execution?,"Describing a design example for a Single-port memory using the gf180 platform, this process is adaptable to any design. It includes creating a Verilog source directory, configuring design settings in config.mk, defining key parameters, setting SDC constraints, and incorporating the design into the Makefile for execution." 132 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLATFORM?","While designing spm that implements a Single-port memory using gf180 platform, the export PLATFORM value can be gf180." 133 | "For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export PLATFORM?","While designing spm that implements a Single-port memory using gf180 platform, the export PLATFORM value can be gf180." 134 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLATFORM?","For a Single-port memory design on the gf180 platform, the export PLATFORM variable should be set to gf180." 135 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export DESIGN_NAME?","While designing spm that implements a Single-port memory using gf180 platform, the value of the parameter, export DESIGN_NAME can be spm." 136 | "For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export DESIGN_NAME?","While designing spm that implements a Single-port memory using gf180 platform, the value of the parameter, export DESIGN_NAME can be spm." 137 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export DESIGN_NAME?","When designing a Single-port memory on the gf180 platform, the export DESIGN_NAME should be assigned to spm." 138 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export VERILOG_FILES?","For the value of export VERILOG_FILES parameter while designing spm that implements a Single-port memory using gf180 platform, it can be $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))" 139 | "For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export VERILOG_FILES?","For the value of export VERILOG_FILES parameter while designing spm that implements a Single-port memory using gf180 platform, it can be $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))" 140 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export VERILOG_FILES?",The export VERILOG_FILES parameter should be set to include all Verilog files under the design nickname directory for a Single-port memory design on the gf180 platform. 141 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export SDC_FILE?","The parameter, export SDC_FILE can have the value ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc while designing spm that implements a Single-port memory using gf180 platform" 142 | "For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export SDC_FILE?","The parameter, export SDC_FILE can have the value ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc while designing spm that implements a Single-port memory using gf180 platform" 143 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export SDC_FILE?","While designing a Single-port memory on the gf180 platform, the export SDC_FILE parameter should be set to the constraint file path." 144 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export CORE_UTILIZATION?", The value of CORE_UTILIZATION may be subjective but one value for CORE_UTILIZATION while designing spm that implements a Single-port memory using gf180 platform40 145 | "For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export CORE_UTILIZATION?", The value of CORE_UTILIZATION may be subjective but one value for CORE_UTILIZATION while designing spm that implements a Single-port memory using gf180 platform40 146 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export CORE_UTILIZATION?","The CORE_UTILIZATION value, while subjective, could be set to 40 for a Single-port memory design on the gf180 platform." 147 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLACE_DENSITY ","The value of the parameter, export PLACE_DENSITY while designing spm that implements a Single-port memory can be 0.6." 148 | "For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export PLACE_DENSITY?","The value of the parameter, export PLACE_DENSITY while designing spm that implements a Single-port memory can be 0.6." 149 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLACE_DENSITY ","For a Single-port memory design, the export PLACE_DENSITY should be set to 0.6." 150 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export TNS_END_PERCENT?","The value of the parameter, export TNS_END_PERCENT while designing spm that implements a Single-port memory can be 100." 151 | "For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export TNS_END_PERCENT?","The value of the parameter, export TNS_END_PERCENT while designing spm that implements a Single-port memory can be 100." 152 | "While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export TNS_END_PERCENT?","In the case of a Single-port memory design, the export TNS_END_PERCENT should be 100." 153 | What is the function of the Environment Variables for the OpenROAD Flow Scripts?,"Environment variables are used in the OpenROAD flow to define various platform, design, and tool-specific variables to allow finer control and user overrides at various flow stages. These are defined in the config.mk file located in the platform and design-specific directories." 154 | How do Environment Variables influence the OpenROAD Flow Scripts?,"Environment variables are used in the OpenROAD flow to define various platform, design, and tool-specific variables to allow finer control and user overrides at various flow stages. These are defined in the config.mk file located in the platform and design-specific directories." 155 | What is the function of the Environment Variables for the OpenROAD Flow Scripts?,"The OpenROAD flow utilizes environment variables defined in the config.mk file to specify various platform, design, and tool-specific settings, offering detailed control and customization at different stages." 156 | "What does the general variables for all stages, SKIP_REPORT_METRICS do?","The SKIP_REPORT_METRICS general variable if set to 1, then metrics, report_metrics does nothing. This is useful to speed up builds." 157 | What is the role of the SKIP_REPORT_METRICS variable in all stages?,"The SKIP_REPORT_METRICS general variable if set to 1, then metrics, report_metrics does nothing. This is useful to speed up builds." 158 | "What does the general variables for all stages, SKIP_REPORT_METRICS do?","If the SKIP_REPORT_METRICS variable is set to 1, metrics and report_metrics are bypassed, which accelerates the build process." 159 | "Can you explain the usage of the Library Setup variable, PROCESS?","The variable, PROCESS signifies a technology node or process in use." 160 | Can you detail the PROCESS variable in Library Setup?,"The variable, PROCESS signifies a technology node or process in use." 161 | "Can you explain the usage of the Library Setup variable, PROCESS?",The PROCESS variable indicates the technology node or process in use. 162 | "What is the function of the Library Setup variable, CORNER?",This CORNER variable specifies the Library to select based on corner BC/TC/WC. 163 | What is the purpose of the CORNER variable in Library Setup?,This CORNER variable specifies the Library to select based on corner BC/TC/WC. 164 | "What is the function of the Library Setup variable, CORNER?",The CORNER variable determines the Library selection based on corner cases like BC/TC/WC. 165 | "What is the description of Library Setup variable, TECH_LEF","This variable, TECH_LEF, stipulates a technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements." 166 | What does the TECH_LEF variable in Library Setup describe?,"This variable, TECH_LEF, stipulates a technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements." 167 | "What is the description of Library Setup variable, TECH_LEF","TECH_LEF defines a technology LEF file from the PDK containing details on metal layers, vias, and spacing requirements." 168 | "What is the description of Library Setup variable, SC_LEF",SC_LEF is used to specify the path to the technology standard cell LEF file. 169 | What does the SC_LEF variable in Library Setup denote?,SC_LEF is used to specify the path to the technology standard cell LEF file. 170 | "What is the description of Library Setup variable, SC_LEF",SC_LEF specifies the path to the technology standard cell LEF file. 171 | "What is the function of the Library Setup variable, GDS_FILES",GDS_FILES specifies the path to platform GDS files. 172 | What is the role of the GDS_FILES variable in Library Setup?,GDS_FILES specifies the path to platform GDS files. 173 | "What is the function of the Library Setup variable, GDS_FILES",GDS_FILES sets the path to platform GDS files. 174 | "What is the description of Library Setup variable, LIB_FILES","LIB_FILES enumerates a Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing, and power definitions for each cell." 175 | What does the LIB_FILES variable in Library Setup specify?,"LIB_FILES enumerates a Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing, and power definitions for each cell." 176 | "What is the description of Library Setup variable, LIB_FILES","LIB_FILES lists a Liberty file for the standard cell library, including PVT characterization, and definitions of input/output characteristics, timing, and power for each cell." 177 | "Can you explain the usage of the Library Setup variable, DONT_USE_CELLS?","In OpenROAD Flow Scripts, the DONT_USE_CELLS variable stores a list of cells to avoid when performing both synthesis and place & route. Basic wildcard patterns (*) are supported. You may want to mark a cell as dont_use for several reasons, including 1) some cells may have complicated pin access patterns which are more likely to cause design rule violations during detailed routing, 2) some cells may be more prone to manufacturing variation, and will cause difficulty to close timing constraints, 3) A designer may not want to use certain cells during the implementation flow." 178 | How is the DONT_USE_CELLS variable used in Library Setup?,"In OpenROAD Flow Scripts, the DONT_USE_CELLS variable stores a list of cells to avoid when performing both synthesis and place & route. Basic wildcard patterns (*) are supported. You may want to mark a cell as dont_use for several reasons, including 1) some cells may have complicated pin access patterns which are more likely to cause design rule violations during detailed routing, 2) some cells may be more prone to manufacturing variation, and will cause difficulty to close timing constraints, 3) A designer may not want to use certain cells during the implementation flow." 179 | "Can you explain the usage of the Library Setup variable, DONT_USE_CELLS?","In OpenROAD Flow Scripts, DONT_USE_CELLS stores cells to avoid during synthesis and place & route, supporting basic wildcard patterns (*), due to reasons like complex pin access, susceptibility to manufacturing variation, or simply preference." 180 | What does restructuring do?,"Restructuring (the rst module) uses logic resynthesis to optimize combinational logic paths. Restructuring can be performed in either area or delay mode. Area mode will optimize the logic cell area of the paths, whereas delay mode will optimize for delay. An Area Mode Example: restructure -liberty_file ckt.lib -target area -tielo_pin ABC -tiehi_pin DEF. For Timing Mode Example: restructure -liberty_file ckt.lib -target delay -tielo_pin ABC -tiehi_pin DEF -slack_threshold 1 -depth_threshold 2." 181 | How does restructuring contribute to design optimization?,"Restructuring (the rst module) uses logic resynthesis to optimize combinational logic paths. Restructuring can be performed in either area or delay mode. Area mode will optimize the logic cell area of the paths, whereas delay mode will optimize for delay. An Area Mode Example: restructure -liberty_file ckt.lib -target area -tielo_pin ABC -tiehi_pin DEF. For Timing Mode Example: restructure -liberty_file ckt.lib -target delay -tielo_pin ABC -tiehi_pin DEF -slack_threshold 1 -depth_threshold 2." 182 | What does restructuring do?,Restructuring optimizes combinational logic paths in area or delay modes. 183 | Is there a way of knowing which instances were modified by resize command ?,"The Resizer module (rsz) can modify the netlist by inserting or removing buffers, as well as increasing or decreasing the drive strength of cells. rsz does not save a log of which instances were modified, because it would create an excessively long log file. A recommended workaround solution would be to save a layout file (such as DEF or ODB) before performing resizing, and then compare it to a layout file after resizing." 184 | Is it possible to identify instances modified by the resize command?,"The Resizer module (rsz) can modify the netlist by inserting or removing buffers, as well as increasing or decreasing the drive strength of cells. rsz does not save a log of which instances were modified, because it would create an excessively long log file. A recommended workaround solution would be to save a layout file (such as DEF or ODB) before performing resizing, and then compare it to a layout file after resizing." 185 | Is there a way of knowing which instances were modified by resize command ?,Resizer modifies the netlist by adjusting buffer sizes and cell drive strengths without detailed modification logs. 186 | How can I improve runtime?,"In OpenROAD, the runtime of the software is directly related to 1) the modeling accuracy and 2) the circuit optimization effort. Improving runtime is usually a tradeoff of one of these two categories. If you are comfortable with reducing optimization effort, such as when performing design space exploration, you could try the following techniques: 1) Relaxing timing constraints in the SDC file, 2) skipping unnesessary optimization routines, such as setup and hold time fixing, 3) Stopping the design flow early, such as after the placement step or clock tree synthesis (CTS) step." 187 | How might I enhance the runtime efficiency of my design?,"In OpenROAD, the runtime of the software is directly related to 1) the modeling accuracy and 2) the circuit optimization effort. Improving runtime is usually a tradeoff of one of these two categories. If you are comfortable with reducing optimization effort, such as when performing design space exploration, you could try the following techniques: 1) Relaxing timing constraints in the SDC file, 2) skipping unnesessary optimization routines, such as setup and hold time fixing, 3) Stopping the design flow early, such as after the placement step or clock tree synthesis (CTS) step." 188 | How can I improve runtime?,"OpenROAD runtime is influenced by modeling accuracy and optimization efforts, with trade-offs for runtime improvement." 189 | Why does my design take so long?,"In OpenROAD, the runtime of the design can be affected by several factors: 1) the size of the netlist. Designs with a large number of instances (100k or more) can take significantly longer than small designs. 2) the physical area of the design. Designs with large die areas (~1 mm^2 or larger) can take longer because of having to store the die size in memory. 3) improper timing constraints. Designs with excessive timing constaints can cause optimization algorithms, particularly Resizer (rsz) to take excessively long. 4) host machine constraints. Large designs can require a large amount of RAM to run. If the required memory exceeds your machine's available memory, the runtime will be significantly increased. Additionally, OpenROAD scales well with core count, so using a CPU with a greater number of cores can improve runtime." 190 | What factors contribute to prolonged design processing times?,"In OpenROAD, the runtime of the design can be affected by several factors: 1) the size of the netlist. Designs with a large number of instances (100k or more) can take significantly longer than small designs. 2) the physical area of the design. Designs with large die areas (~1 mm^2 or larger) can take longer because of having to store the die size in memory. 3) improper timing constraints. Designs with excessive timing constaints can cause optimization algorithms, particularly Resizer (rsz) to take excessively long. 4) host machine constraints. Large designs can require a large amount of RAM to run. If the required memory exceeds your machine's available memory, the runtime will be significantly increased. Additionally, OpenROAD scales well with core count, so using a CPU with a greater number of cores can improve runtime." 191 | Why does my design take so long?,"Netlist size, design area, timing constraints, and machine capabilities affect OpenROAD's runtime." 192 | What is DBU?,"In OpenROAD, database units (DBU) are an integer representation of distance on a chip. In the LEF/DEF format, each technology specifies a conversion factor in terms of DBU/micron. For example, if a technology used a conversion factor of 2000 DBU/micron, that would mean that each DBU represents 0.0005 micron or 0.5 nm. The purpose for using DBU is that it enables faster calculation and no loss of precision compared to floating point representations." 193 | Can you explain the concept of DBU in OpenROAD?,"In OpenROAD, database units (DBU) are an integer representation of distance on a chip. In the LEF/DEF format, each technology specifies a conversion factor in terms of DBU/micron. For example, if a technology used a conversion factor of 2000 DBU/micron, that would mean that each DBU represents 0.0005 micron or 0.5 nm. The purpose for using DBU is that it enables faster calculation and no loss of precision compared to floating point representations." 194 | What is DBU?,"Database units (DBU) represent distance on a chip, converting to microns for precision without floating point errors." 195 | How do I convert from DBU?,"In OpenROAD, an integer DBU value can be converted to a floating point micron value by using the ord::dbu_to_microns function" 196 | How is conversion from DBU performed?,"In OpenROAD, an integer DBU value can be converted to a floating point micron value by using the ord::dbu_to_microns function" 197 | How do I convert from DBU?,DBU values convert to microns using ord::dbu_to_microns function. 198 | How to access GUI,OpenROAD's GUI can be started in two ways. One is to use the -gui flag when invoking OpenROAD from the command line (e.g. openroad -gui). The other option is to use the gui::show function from inside the openroad command interpreter. 199 | How can the GUI be accessed in OpenROAD?,OpenROAD's GUI can be started in two ways. One is to use the -gui flag when invoking OpenROAD from the command line (e.g. openroad -gui). The other option is to use the gui::show function from inside the openroad command interpreter. 200 | How to access GUI,OpenROAD's GUI is accessible via command line flag or internal show function. 201 | Which commands are essential for manipulating design data in OpenROAD?,"OpenROAD is run using Tcl scripts. The following commands are used to read and write design data. 202 | read_lef [-tech] [-library] filename 203 | read_def filename 204 | write_def [-version 5.8|5.7|5.6|5.5|5.4|5.3] filename 205 | read_verilog filename 206 | write_verilog filename 207 | read_db filename 208 | write_db filename 209 | write_abstract_lef filename" 210 | "What do these Debug output mean? 211 | [INFO MPL-0024] [Multilevel Autoclustering] Creating clustered netlist. 212 | [INFO MPL-0039] [Coarse Shaping] Determining shape functions for clusters. 213 | [INFO MPL-0028] [Hierarchical Macro Placement] Placing clusters and macros. 214 | [INFO MPL-0037] Updated location of 95 macros 215 | Delete buffers for RTLMP flow... 216 | [INFO RSZ-0026] Removed 0 buffers.","Messages with the MPL prefix are from the macro placement (mpl) module. These messages are progress messages, informing the user which step of the HierRTLMP flow is being executed." --------------------------------------------------------------------------------