├── CMakeLists.txt ├── LICENSE ├── README.md ├── benchmark ├── ac97_ctrl.v ├── aes_core.v ├── c1355.v ├── c17.v ├── c17_slack.v ├── c1908.v ├── c2670.v ├── c3540.v ├── c3_path.v ├── c3_slack.v ├── c432.v ├── c499.v ├── c5315.v ├── c6288.v ├── c7552.v ├── c7552_slack.v ├── c880.v ├── des_perf.v ├── s1196.v ├── s1494.v ├── s27.v ├── s27_path.v ├── s27_spef.v ├── s344.v ├── s349.v ├── s386.v ├── s400.v ├── s510.v ├── s526.v ├── simple.v ├── tv80.v ├── usb_phy_ispd.v ├── vga_lcd.v ├── wb_dma.v └── yosys.v ├── example ├── ot_parser.cpp └── sample_parser.cpp ├── image ├── .~lock.circuit.odg# ├── circuit.odg └── circuit.png ├── parser-verilog ├── verilog_data.hpp ├── verilog_driver.hpp ├── verilog_lexer.l ├── verilog_parser.yy └── verilog_scanner.hpp └── unittest └── regression.cpp /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.9) 2 | 3 | project(Parser-Verilog LANGUAGES CXX) 4 | include(CTest) 5 | 6 | # Turn on the verbose 7 | set(CMAKE_VERBOSE_MAKEFILE ON) 8 | 9 | set(CMAKE_CXX_STANDARD 17) 10 | set(CMAKE_CXX_STANDARD_REQUIRED ON) 11 | set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -O2") 12 | 13 | # add the binary tree to the search path for include files 14 | include_directories(${PROJECT_SOURCE_DIR}) 15 | include_directories(${CMAKE_CURRENT_BINARY_DIR}) 16 | include_directories(parser-verilog) 17 | 18 | 19 | # ----------------------------------------------------------------------------- 20 | # Flex & Bison 21 | # ----------------------------------------------------------------------------- 22 | 23 | find_package(BISON REQUIRED) 24 | find_package(FLEX REQUIRED) 25 | 26 | BISON_TARGET(verilog_parser 27 | ${PROJECT_SOURCE_DIR}/parser-verilog/verilog_parser.yy 28 | ${CMAKE_CURRENT_BINARY_DIR}/verilog_parser.tab.cc) 29 | FLEX_TARGET(verilog_lexer 30 | ${PROJECT_SOURCE_DIR}/parser-verilog/verilog_lexer.l 31 | ${CMAKE_CURRENT_BINARY_DIR}/verilog_lexer.yy.cc) 32 | ADD_FLEX_BISON_DEPENDENCY(verilog_lexer verilog_parser) 33 | 34 | 35 | # ----------------------------------------------------------------------------- 36 | # Example program 37 | # ----------------------------------------------------------------------------- 38 | 39 | # Set the output folder to example 40 | set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${PROJECT_SOURCE_DIR}/example) 41 | 42 | # A sample parser 43 | add_executable(sample_parser 44 | ${PROJECT_SOURCE_DIR}/example/sample_parser.cpp 45 | ${FLEX_verilog_lexer_OUTPUTS} 46 | ${BISON_verilog_parser_OUTPUTS} 47 | ) 48 | 49 | # A drop-in replacement OpenTimer Verilog parser 50 | add_executable(ot_parser 51 | ${PROJECT_SOURCE_DIR}/example/ot_parser.cpp 52 | ${FLEX_verilog_lexer_OUTPUTS} 53 | ${BISON_verilog_parser_OUTPUTS} 54 | ) 55 | 56 | 57 | 58 | # ----------------------------------------------------------------------------- 59 | # Unittest 60 | # ----------------------------------------------------------------------------- 61 | 62 | enable_testing() 63 | set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${PROJECT_SOURCE_DIR}/unittest) 64 | 65 | # Regression 66 | set(VP_UTEST_DIR ${PROJECT_SOURCE_DIR}/unittest) 67 | set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${VP_UTEST_DIR}) 68 | 69 | add_executable(regression unittest/regression.cpp ${FLEX_verilog_lexer_OUTPUTS} ${BISON_verilog_parser_OUTPUTS}) 70 | add_test(regression ${VP_UTEST_DIR}/regression) 71 | 72 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 OpenTimer 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Parser-Verilog 2 | 3 | A Standalone Structural Verilog Parser 4 | 5 | # Get Started with Parser-Verilog 6 | 7 | A [Verilog] is a programming language that is used to describe a 8 | digital circuit. Below is a circuit written in Verilog. 9 | 10 | 11 | 12 | ```Verilog 13 | module simple (input1, input2, input3, out); 14 | 15 | // primary inputs 16 | input input1, input2, input3; 17 | 18 | // primary output 19 | output out; 20 | 21 | wire out; 22 | 23 | // wires 24 | wire w1; 25 | wire w2; 26 | wire w3; 27 | 28 | // module instances 29 | AND2_X1 g1 (.a(input1), .b(input2), .o(w1)); 30 | OR2_X1 g2 (.a(input3), .b(w1), .o(w2)); 31 | INV_X2 g3 (.a(w2), .o(w3)); 32 | NOR2_X1 g4 (.a(w1), .b(w3), .o(out)); 33 | 34 | endmodule 35 | ``` 36 | 37 | The following example demonstrates how to use Parser-Verilog to parse a Verilog file. 38 | 39 | 40 | ```cpp 41 | #include 42 | 43 | #include "verilog_driver.hpp" // The only include you need 44 | 45 | // Define your own parser by inheriting the ParserVerilogInterface 46 | struct MyVerilogParser : public verilog::ParserVerilogInterface { 47 | 48 | virtual ~MyVerilogParser(){} 49 | 50 | // Function that will be called when encountering the top module name. 51 | void add_module(std::string&& name){ 52 | std::cout << "Module: " << name << '\n'; 53 | } 54 | 55 | // Function that will be called when encountering a port. 56 | void add_port(verilog::Port&& port) { 57 | std::cout << "Port: " << port << '\n'; 58 | } 59 | 60 | // Function that will be called when encountering a net. 61 | void add_net(verilog::Net&& net) { 62 | std::cout << "Net: " << net << '\n'; 63 | } 64 | 65 | // Function that will be called when encountering a assignment statement. 66 | void add_assignment(verilog::Assignment&& ast) { 67 | std::cout << "Assignment: " << ast << '\n'; 68 | } 69 | 70 | // Function that will be called when encountering a module instance. 71 | void add_instance(verilog::Instance&& inst) { 72 | std::cout << "Instance: " << inst << '\n'; 73 | } 74 | }; 75 | 76 | int main(){ 77 | MyVerilogParser parser; 78 | parser.read("verilog_file.v"); 79 | return EXIT_SUCCESS; 80 | } 81 | ``` 82 | 83 | You need a C++ compiler with C++17 support, [GNU Bison] and [Flex] to compile Parser-Verilog. 84 | ```bash 85 | ~$ flex -o./verilog_lexer.yy.cc parser-verilog/verilog_lexer.l 86 | ~$ bison -d -o verilog_parser.tab.cc parser-verilog/verilog_parser.yy 87 | ~$ g++ -std=c++17 -I parser-verilog/ verilog_parser.tab.cc verilog_lexer.yy.cc example/sample_parser.cpp -o sample_parser -lstdc++fs 88 | ``` 89 | 90 | # Compile Tests 91 | ## System Requirements 92 | To use Parser-Verilog, you need following libraries: 93 | + GNU [C++ Compiler G++ v7.2](https://gcc.gnu.org/gcc-7/) (or higher) with C++17 support 94 | + [GNU Bison] at least 3.0.4 95 | + [Flex] at least 2.6.0 96 | 97 | Currently Parser-Verilog has been tested to run well on Linux distributions. 98 | 99 | ## Build through CMake 100 | We use [CMake](https://cmake.org/) to manage the source and tests. 101 | We recommend using out-of-source build. 102 | 103 | ```bash 104 | ~$ git clone https://github.com/OpenTimer/Parser-Verilog.git 105 | ~$ cd Parser-Verilog 106 | ~$ mkdir build 107 | ~$ cd build 108 | ~$ cmake ../ 109 | ~$ make 110 | ``` 111 | 112 | # Use Parser-Verilog 113 | Parser-Verilog is extremely easy to use and understand. You create your own Verilog parser `struct` or `class` that 114 | inherits the `VerilogParserInterface` and define member functions to be invoked to process the components in a circuit. 115 | 116 | ## Create your own Verilog parser 117 | ```cpp 118 | #include "verilog_driver.hpp" // The only include you need 119 | 120 | // Define your own parser by inheriting the ParserVerilogInterface 121 | struct MyVerilogParser : public verilog::ParserVerilogInterface { 122 | 123 | virtual ~MyVerilogParser(){} 124 | 125 | // Implement below member functions to process different components 126 | 127 | void add_module(std::string&& name){ 128 | // Process the module name 129 | } 130 | void add_port(verilog::Port&& port) { 131 | // Process a port 132 | } 133 | void add_net(verilog::Net&& net) { 134 | // Process a net 135 | } 136 | void add_assignment(verilog::Assignment&& ast) { 137 | // Process an assignment 138 | } 139 | void add_instance(verilog::Instance&& inst) { 140 | // Process a module instance 141 | } 142 | }; 143 | ``` 144 | Below are the required member functions in your custom Verilog parser 145 | 146 | | Name | Argument | Return | Description | 147 | | ----- |:------------------| :-------------- | :-------------- | 148 | | add_module | std::string | n/a | invoked when encountering the name of top module | 149 | | add_port | Port | n/a | invoked when encountering a primary input/output of the module | 150 | | add_net | Net | n/a | invoked when encountering a net declaration | 151 | | add_assignment | Assignment | n/a | invoked when encountering an assignment statement | 152 | | add_instance | Instance | n/a | invoked when encountering a module instance| 153 | 154 | ## Data Structures 155 | We define a set of `structs` storing the information of different components during parsing and 156 | we invoke your parser's member functions on those data structures. 157 | 158 | ### Struct Port 159 | The struct `Port` stores the information of a primary input/output of the module 160 | 161 | | Name | Type | Description | 162 | | ------------- |:-------------| :--------------| 163 | | name | std::vector | the names of ports | 164 | | PortDirection | `enum class` | the direction of the port. The value could be either INPUT, OUTPUT or INOUT. | 165 | | ConnectionType | `enum class` | the connection type of the port. The value could be either NONE, WIRE, REG. | 166 | | beg, end | `int` | the bitwidth (range) of the port | 167 | 168 | 169 | ### Struct Net 170 | The struct `Net` stores the information of a net declaration 171 | 172 | | Name | Type | Description | 173 | | ------------- |:-------------| :--------------| 174 | | name | std::vector | the names of nets | 175 | | NetType | `enum class` | the type of a net. The value could be either NONE, REG, WIRE, WAND, WOR, TRI, TRIOR, TRIAND, SUPPLY0, SUPPLY1 | 176 | | beg, end | `int` | the bitwidth (range) of the net | 177 | 178 | 179 | ### Struct Assignment 180 | The struct `Assignment` stores the information of an assignment statement 181 | 182 | | Name | Type | Description | 183 | | ------------- |:-------------| :--------------| 184 | | lhs | std::vector> | the left hand side of the assignment statement | 185 | | rhs | std::vector> | the right hand side of the assignment statement | 186 | 187 | 188 | ### Struct Instance 189 | The struct `Instance` stores the information of a module instance 190 | 191 | | Name | Type | Description | 192 | | ------------- |:-------------| :--------------| 193 | | module_name | std::string | the name of the module | 194 | | inst_name | std::string | the name of the instance | 195 | | pin_names | std::vector> | the input/output pins of the instance | 196 | | net_names | std::vector>> | the nets connecting to the pins | 197 | 198 | 199 | 200 | ### Struct Constant 201 | The struct `Constant` records the possible number formats in Verilog 202 | 203 | | Name | Type | Description | 204 | | ------------- |:-------------| :--------------| 205 | | value | std::string | the value of the number | 206 | | ConstantType | `enum class` | the format of the number. The value could be NONE, INTEGER, BINARY, OCTAL, DECIMAL, HEX, REAL, EXP | 207 | 208 | 209 | ### Struct NetBit 210 | The struct `NetBit` specifies a bit in a net 211 | 212 | | Name | Type | Description | 213 | | ------------- |:-------------| :--------------| 214 | | name | std::string | the name of a net | 215 | | bit | int | the index of the bit | 216 | 217 | 218 | ### Struct NetRange 219 | The struct `NetRange` specifies a range in a net 220 | 221 | | Name | Type | Description | 222 | | ------------- |:-------------| :--------------| 223 | | name | std::string | the name of a net | 224 | | beg, end | int | the bit range of a net | 225 | 226 | 227 | 228 | 229 | # Examples 230 | The folder [example](./example) contains several tutorial examples to demonstrate the usage of Parser-Verilog. 231 | 232 | | Example | Description | How to Run ? | 233 | | ------------- |:-------------| :--------------| 234 | | [sample_parser.cpp](./example/sample_parser.cpp) | Read a Verilog and print the parsed data to screen | ./sample_parser [file] | 235 | | [ot_parser.cpp](./example/ot_parser.cpp) | A drop-in replacement Verilog parser for OpenTimer | ./ot_parser [file] | 236 | 237 | 238 | # License 239 | 240 | 241 | 242 | Parser-Verilog is licensed under the [MIT License](./LICENSE): 243 | 244 | Copyright © 2019 [Chun-Xun Lin][Chun-Xun Lin], [Tsung-Wei Huang][Tsung-Wei Huang] and [Martin Wong][Martin Wong] 245 | 246 | The University of Illinois at Urbana-Champaign, IL, USA 247 | 248 | Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 249 | 250 | The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. 251 | 252 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 253 | 254 | 255 | *** 256 | [Tsung-Wei Huang]: http://web.engr.illinois.edu/~thuang19/ 257 | [Chun-Xun Lin]: https://github.com/clin99 258 | [Martin Wong]: https://ece.illinois.edu/directory/profile/mdfwong 259 | [Verilog]: https://en.wikipedia.org/wiki/Verilog 260 | [GNU Bison]: https://www.gnu.org/software/bison/ 261 | [Flex]: https://github.com/westes/flex 262 | 263 | -------------------------------------------------------------------------------- /benchmark/c1355.v: -------------------------------------------------------------------------------- 1 | module c1355 ( 2 | n43gat, 3 | n190gat, 4 | n99gat, 5 | n78gat, 6 | n85gat, 7 | n232gat, 8 | n211gat, 9 | n226gat, 10 | n155gat, 11 | n176gat, 12 | n162gat, 13 | n64gat, 14 | n230gat, 15 | n92gat, 16 | n228gat, 17 | n127gat, 18 | n22gat, 19 | n1gat, 20 | n113gat, 21 | n183gat, 22 | n148gat, 23 | n29gat, 24 | n197gat, 25 | n134gat, 26 | n204gat, 27 | n218gat, 28 | n227gat, 29 | n8gat, 30 | n169gat, 31 | n225gat, 32 | n36gat, 33 | n57gat, 34 | n231gat, 35 | n106gat, 36 | n233gat, 37 | n50gat, 38 | n15gat, 39 | n71gat, 40 | n120gat, 41 | n229gat, 42 | n141gat, 43 | n1328gat, 44 | n1348gat, 45 | n1338gat, 46 | n1331gat, 47 | n1339gat, 48 | n1344gat, 49 | n1346gat, 50 | n1353gat, 51 | n1337gat, 52 | n1333gat, 53 | n1347gat, 54 | n1340gat, 55 | n1354gat, 56 | n1351gat, 57 | n1355gat, 58 | n1352gat, 59 | n1343gat, 60 | n1329gat, 61 | n1332gat, 62 | n1336gat, 63 | n1324gat, 64 | n1335gat, 65 | n1334gat, 66 | n1349gat, 67 | n1330gat, 68 | n1327gat, 69 | n1341gat, 70 | n1326gat, 71 | n1345gat, 72 | n1342gat, 73 | n1350gat, 74 | n1325gat); 75 | 76 | // Start PIs 77 | input n43gat; 78 | input n190gat; 79 | input n99gat; 80 | input n78gat; 81 | input n85gat; 82 | input n232gat; 83 | input n211gat; 84 | input n226gat; 85 | input n155gat; 86 | input n176gat; 87 | input n162gat; 88 | input n64gat; 89 | input n230gat; 90 | input n92gat; 91 | input n228gat; 92 | input n127gat; 93 | input n22gat; 94 | input n1gat; 95 | input n113gat; 96 | input n183gat; 97 | input n148gat; 98 | input n29gat; 99 | input n197gat; 100 | input n134gat; 101 | input n204gat; 102 | input n218gat; 103 | input n227gat; 104 | input n8gat; 105 | input n169gat; 106 | input n225gat; 107 | input n36gat; 108 | input n57gat; 109 | input n231gat; 110 | input n106gat; 111 | input n233gat; 112 | input n50gat; 113 | input n15gat; 114 | input n71gat; 115 | input n120gat; 116 | input n229gat; 117 | input n141gat; 118 | 119 | // Start POs 120 | output n1328gat; 121 | output n1348gat; 122 | output n1338gat; 123 | output n1331gat; 124 | output n1339gat; 125 | output n1344gat; 126 | output n1346gat; 127 | output n1353gat; 128 | output n1337gat; 129 | output n1333gat; 130 | output n1347gat; 131 | output n1340gat; 132 | output n1354gat; 133 | output n1351gat; 134 | output n1355gat; 135 | output n1352gat; 136 | output n1343gat; 137 | output n1329gat; 138 | output n1332gat; 139 | output n1336gat; 140 | output n1324gat; 141 | output n1335gat; 142 | output n1334gat; 143 | output n1349gat; 144 | output n1330gat; 145 | output n1327gat; 146 | output n1341gat; 147 | output n1326gat; 148 | output n1345gat; 149 | output n1342gat; 150 | output n1350gat; 151 | output n1325gat; 152 | 153 | // Start wires 154 | wire n43gat; 155 | wire net_107; 156 | wire net_47; 157 | wire n190gat; 158 | wire n1328gat; 159 | wire n99gat; 160 | wire net_61; 161 | wire net_137; 162 | wire n1338gat; 163 | wire net_132; 164 | wire net_54; 165 | wire net_105; 166 | wire net_62; 167 | wire net_6; 168 | wire n176gat; 169 | wire net_129; 170 | wire net_119; 171 | wire net_98; 172 | wire net_23; 173 | wire net_117; 174 | wire net_12; 175 | wire net_74; 176 | wire net_53; 177 | wire net_93; 178 | wire n1353gat; 179 | wire net_135; 180 | wire net_130; 181 | wire n1347gat; 182 | wire net_147; 183 | wire net_127; 184 | wire net_14; 185 | wire n1351gat; 186 | wire net_113; 187 | wire net_26; 188 | wire n204gat; 189 | wire net_76; 190 | wire net_101; 191 | wire net_32; 192 | wire net_111; 193 | wire n1332gat; 194 | wire n1329gat; 195 | wire net_90; 196 | wire net_40; 197 | wire net_100; 198 | wire n8gat; 199 | wire net_85; 200 | wire net_69; 201 | wire n225gat; 202 | wire net_124; 203 | wire n57gat; 204 | wire net_141; 205 | wire n1330gat; 206 | wire net_83; 207 | wire net_115; 208 | wire n1345gat; 209 | wire n120gat; 210 | wire net_4; 211 | wire net_95; 212 | wire net_17; 213 | wire net_78; 214 | wire net_27; 215 | wire net_56; 216 | wire net_87; 217 | wire net_0; 218 | wire n232gat; 219 | wire net_35; 220 | wire n211gat; 221 | wire net_22; 222 | wire net_16; 223 | wire n64gat; 224 | wire net_39; 225 | wire n228gat; 226 | wire n92gat; 227 | wire net_144; 228 | wire net_102; 229 | wire net_2; 230 | wire net_59; 231 | wire net_9; 232 | wire net_42; 233 | wire n22gat; 234 | wire net_120; 235 | wire n1337gat; 236 | wire net_109; 237 | wire net_80; 238 | wire net_65; 239 | wire net_50; 240 | wire n183gat; 241 | wire n1354gat; 242 | wire n1340gat; 243 | wire net_96; 244 | wire net_66; 245 | wire net_38; 246 | wire net_44; 247 | wire n197gat; 248 | wire net_136; 249 | wire net_134; 250 | wire net_19; 251 | wire n1352gat; 252 | wire net_89; 253 | wire net_45; 254 | wire net_126; 255 | wire n1336gat; 256 | wire n1324gat; 257 | wire net_34; 258 | wire net_108; 259 | wire n1334gat; 260 | wire n50gat; 261 | wire n15gat; 262 | wire net_63; 263 | wire n1342gat; 264 | wire n229gat; 265 | wire n141gat; 266 | wire n1348gat; 267 | wire net_116; 268 | wire net_30; 269 | wire n78gat; 270 | wire n1331gat; 271 | wire net_91; 272 | wire net_106; 273 | wire net_99; 274 | wire net_24; 275 | wire net_55; 276 | wire net_46; 277 | wire net_140; 278 | wire net_118; 279 | wire net_104; 280 | wire net_146; 281 | wire net_72; 282 | wire net_122; 283 | wire net_25; 284 | wire net_70; 285 | wire net_7; 286 | wire n1333gat; 287 | wire n113gat; 288 | wire net_5; 289 | wire net_52; 290 | wire n148gat; 291 | wire net_128; 292 | wire n1355gat; 293 | wire net_138; 294 | wire net_13; 295 | wire n218gat; 296 | wire net_94; 297 | wire net_11; 298 | wire n169gat; 299 | wire net_18; 300 | wire net_123; 301 | wire n36gat; 302 | wire n1335gat; 303 | wire net_131; 304 | wire net_114; 305 | wire n1349gat; 306 | wire n1327gat; 307 | wire net_29; 308 | wire n231gat; 309 | wire net_68; 310 | wire n1341gat; 311 | wire net_142; 312 | wire net_77; 313 | wire n71gat; 314 | wire net_20; 315 | wire net_31; 316 | wire n1350gat; 317 | wire net_36; 318 | wire net_49; 319 | wire net_15; 320 | wire net_57; 321 | wire net_41; 322 | wire net_71; 323 | wire n85gat; 324 | wire n226gat; 325 | wire n155gat; 326 | wire net_3; 327 | wire net_84; 328 | wire n162gat; 329 | wire net_112; 330 | wire net_92; 331 | wire net_1; 332 | wire net_103; 333 | wire n1339gat; 334 | wire net_139; 335 | wire n230gat; 336 | wire n127gat; 337 | wire net_43; 338 | wire n1344gat; 339 | wire net_10; 340 | wire n1346gat; 341 | wire net_28; 342 | wire net_21; 343 | wire net_51; 344 | wire net_79; 345 | wire n1gat; 346 | wire net_143; 347 | wire net_97; 348 | wire net_88; 349 | wire n29gat; 350 | wire net_145; 351 | wire net_60; 352 | wire n134gat; 353 | wire net_81; 354 | wire net_58; 355 | wire n227gat; 356 | wire n1343gat; 357 | wire net_82; 358 | wire net_67; 359 | wire net_64; 360 | wire net_37; 361 | wire net_110; 362 | wire net_121; 363 | wire net_73; 364 | wire net_33; 365 | wire net_48; 366 | wire net_86; 367 | wire net_75; 368 | wire net_8; 369 | wire n1326gat; 370 | wire n106gat; 371 | wire n233gat; 372 | wire net_133; 373 | wire net_125; 374 | wire n1325gat; 375 | 376 | // Start cells 377 | NAND2_X1 inst_145 ( .A1(net_112), .ZN(net_104), .A2(net_103) ); 378 | XNOR2_X1 inst_103 ( .B(net_147), .ZN(n1324gat), .A(n1gat) ); 379 | NAND3_X1 inst_125 ( .A2(net_105), .ZN(net_99), .A3(net_91), .A1(net_86) ); 380 | NAND2_X1 inst_138 ( .ZN(net_92), .A2(net_90), .A1(net_77) ); 381 | NAND2_X1 inst_159 ( .A1(net_138), .ZN(net_128), .A2(net_127) ); 382 | XOR2_X1 inst_15 ( .Z(net_28), .A(n120gat), .B(n113gat) ); 383 | NAND2_X1 inst_134 ( .A1(net_116), .ZN(net_100), .A2(net_73) ); 384 | AND2_X4 inst_179 ( .A2(net_94), .A1(net_93), .ZN(net_76) ); 385 | XNOR2_X1 inst_24 ( .ZN(net_13), .A(n92gat), .B(n85gat) ); 386 | NOR2_X1 inst_114 ( .ZN(net_103), .A2(net_95), .A1(net_94) ); 387 | XOR2_X1 inst_6 ( .Z(net_15), .A(n99gat), .B(n71gat) ); 388 | NAND2_X1 inst_131 ( .ZN(net_5), .A2(n233gat), .A1(n228gat) ); 389 | XNOR2_X1 inst_76 ( .B(net_122), .ZN(n1351gat), .A(n190gat) ); 390 | NAND2_X1 inst_160 ( .A1(net_136), .A2(net_134), .ZN(net_129) ); 391 | NAND2_X1 inst_150 ( .A2(net_115), .ZN(net_114), .A1(net_112) ); 392 | XNOR2_X1 inst_33 ( .ZN(net_40), .A(net_32), .B(net_20) ); 393 | INV_X1 inst_172 ( .A(net_145), .ZN(net_75) ); 394 | XNOR2_X1 inst_83 ( .B(net_98), .ZN(n1344gat), .A(n141gat) ); 395 | XNOR2_X1 inst_47 ( .ZN(net_47), .B(net_22), .A(net_12) ); 396 | XOR2_X1 inst_19 ( .Z(net_35), .A(n50gat), .B(n43gat) ); 397 | NAND3_X1 inst_123 ( .A1(net_118), .ZN(net_87), .A2(net_86), .A3(net_82) ); 398 | NAND3_X1 inst_121 ( .A2(net_112), .ZN(net_83), .A3(net_82), .A1(net_73) ); 399 | XOR2_X1 inst_2 ( .Z(net_10), .A(n85gat), .B(n57gat) ); 400 | XOR2_X1 inst_8 ( .Z(net_17), .A(n29gat), .B(n1gat) ); 401 | NOR2_X1 inst_118 ( .ZN(net_134), .A1(net_111), .A2(net_99) ); 402 | XNOR2_X1 inst_86 ( .B(net_104), .ZN(n1341gat), .A(n120gat) ); 403 | NAND2_X1 inst_153 ( .ZN(net_121), .A2(net_120), .A1(net_116) ); 404 | XOR2_X1 inst_20 ( .Z(net_36), .A(n204gat), .B(n176gat) ); 405 | XNOR2_X1 inst_27 ( .ZN(net_22), .A(n162gat), .B(n134gat) ); 406 | XNOR2_X1 inst_38 ( .ZN(net_60), .A(net_34), .B(net_19) ); 407 | XNOR2_X1 inst_100 ( .B(net_132), .ZN(n1327gat), .A(n22gat) ); 408 | XNOR2_X1 inst_52 ( .ZN(net_59), .B(net_58), .A(net_52) ); 409 | XNOR2_X1 inst_90 ( .B(net_128), .ZN(n1337gat), .A(n92gat) ); 410 | NAND2_X1 inst_140 ( .A2(net_115), .A1(net_105), .ZN(net_96) ); 411 | XNOR2_X1 inst_40 ( .ZN(net_44), .A(net_39), .B(net_9) ); 412 | NAND2_X1 inst_162 ( .A2(net_142), .ZN(net_132), .A1(net_131) ); 413 | NAND2_X1 inst_167 ( .ZN(net_141), .A2(net_140), .A1(net_138) ); 414 | XNOR2_X1 inst_93 ( .B(net_137), .ZN(n1334gat), .A(n71gat) ); 415 | XNOR2_X1 inst_81 ( .B(net_108), .ZN(n1346gat), .A(n155gat) ); 416 | XNOR2_X1 inst_95 ( .B(net_146), .ZN(n1332gat), .A(n57gat) ); 417 | XOR2_X1 inst_1 ( .Z(net_9), .A(n92gat), .B(n64gat) ); 418 | XNOR2_X1 inst_72 ( .B(net_119), .ZN(n1355gat), .A(n218gat) ); 419 | NAND2_X1 inst_139 ( .ZN(net_95), .A2(net_90), .A1(net_78) ); 420 | NAND2_X1 inst_155 ( .ZN(net_123), .A2(net_120), .A1(net_105) ); 421 | XNOR2_X1 inst_59 ( .ZN(net_67), .A(net_57), .B(net_3) ); 422 | NAND2_X1 inst_135 ( .A1(net_118), .ZN(net_111), .A2(net_74) ); 423 | XNOR2_X1 inst_44 ( .ZN(net_58), .B(net_21), .A(net_8) ); 424 | XNOR2_X1 inst_55 ( .ZN(net_63), .B(net_56), .A(net_54) ); 425 | INV_X1 inst_174 ( .A(net_131), .ZN(net_72) ); 426 | NOR2_X1 inst_115 ( .ZN(net_142), .A1(net_100), .A2(net_99) ); 427 | XNOR2_X1 inst_37 ( .ZN(net_43), .A(net_37), .B(net_30) ); 428 | NAND2_X1 inst_148 ( .A1(net_112), .ZN(net_109), .A2(net_107) ); 429 | NAND2_X1 inst_164 ( .A1(net_138), .ZN(net_135), .A2(net_134) ); 430 | XOR2_X1 inst_5 ( .Z(net_14), .A(n99gat), .B(n106gat) ); 431 | NAND2_X1 inst_157 ( .A1(net_136), .A2(net_127), .ZN(net_125) ); 432 | XNOR2_X1 inst_84 ( .B(net_101), .ZN(n1343gat), .A(n134gat) ); 433 | XNOR2_X1 inst_51 ( .ZN(net_57), .B(net_56), .A(net_49) ); 434 | NAND2_X1 inst_142 ( .A2(net_107), .A1(net_105), .ZN(net_98) ); 435 | XNOR2_X1 inst_80 ( .B(net_97), .ZN(n1347gat), .A(n162gat) ); 436 | INV_X1 inst_173 ( .ZN(net_112), .A(net_86) ); 437 | OR3_X4 inst_105 ( .A2(net_136), .A1(net_131), .ZN(net_89), .A3(net_79) ); 438 | XNOR2_X1 inst_68 ( .ZN(net_74), .B(net_71), .A(net_41) ); 439 | XNOR2_X1 inst_78 ( .B(net_114), .ZN(n1349gat), .A(n176gat) ); 440 | XNOR2_X1 inst_42 ( .ZN(net_54), .B(net_38), .A(net_28) ); 441 | INV_X1 inst_175 ( .ZN(net_116), .A(net_74) ); 442 | XNOR2_X1 inst_53 ( .ZN(net_61), .A(net_60), .B(net_51) ); 443 | INV_X1 inst_177 ( .ZN(net_105), .A(net_84) ); 444 | NAND2_X1 inst_133 ( .ZN(net_7), .A2(n233gat), .A1(n231gat) ); 445 | XNOR2_X1 inst_26 ( .ZN(net_21), .A(n22gat), .B(n15gat) ); 446 | NAND2_X1 inst_151 ( .ZN(net_117), .A1(net_116), .A2(net_115) ); 447 | NOR2_X1 inst_112 ( .ZN(net_115), .A1(net_94), .A2(net_92) ); 448 | XNOR2_X1 inst_64 ( .ZN(net_145), .B(net_69), .A(net_42) ); 449 | NOR2_X1 inst_107 ( .A1(net_116), .A2(net_105), .ZN(net_82) ); 450 | XNOR2_X1 inst_67 ( .ZN(net_131), .B(net_64), .A(net_40) ); 451 | NAND2_X1 inst_127 ( .ZN(net_1), .A2(n233gat), .A1(n229gat) ); 452 | XNOR2_X1 inst_70 ( .ZN(net_138), .B(net_67), .A(net_44) ); 453 | NAND2_X1 inst_129 ( .ZN(net_3), .A2(n233gat), .A1(n226gat) ); 454 | XNOR2_X1 inst_92 ( .B(net_133), .ZN(n1335gat), .A(n78gat) ); 455 | XNOR2_X1 inst_29 ( .ZN(net_30), .A(n197gat), .B(n169gat) ); 456 | XOR2_X1 inst_17 ( .Z(net_32), .A(n50gat), .B(n22gat) ); 457 | XOR2_X1 inst_11 ( .Z(net_24), .A(n218gat), .B(n211gat) ); 458 | NAND2_X1 inst_146 ( .ZN(net_106), .A1(net_105), .A2(net_103) ); 459 | XOR2_X1 inst_14 ( .Z(net_27), .A(n155gat), .B(n127gat) ); 460 | NAND3_X1 inst_122 ( .A2(net_116), .ZN(net_85), .A1(net_84), .A3(net_80) ); 461 | XNOR2_X1 inst_31 ( .ZN(net_33), .A(n176gat), .B(n169gat) ); 462 | XNOR2_X1 inst_25 ( .ZN(net_18), .A(n211gat), .B(n183gat) ); 463 | NAND2_X1 inst_126 ( .ZN(net_0), .A2(n233gat), .A1(n225gat) ); 464 | NAND2_X1 inst_158 ( .A2(net_134), .A1(net_131), .ZN(net_126) ); 465 | NAND2_X1 inst_141 ( .A1(net_118), .A2(net_107), .ZN(net_97) ); 466 | XNOR2_X1 inst_62 ( .ZN(net_70), .A(net_63), .B(net_6) ); 467 | NOR2_X1 inst_110 ( .ZN(net_79), .A1(net_78), .A2(net_77) ); 468 | XNOR2_X1 inst_74 ( .B(net_113), .ZN(n1353gat), .A(n204gat) ); 469 | XNOR2_X1 inst_57 ( .ZN(net_65), .A(net_53), .B(net_4) ); 470 | XNOR2_X1 inst_35 ( .ZN(net_42), .A(net_17), .B(net_10) ); 471 | XNOR2_X1 inst_99 ( .B(net_144), .ZN(n1328gat), .A(n29gat) ); 472 | XNOR2_X1 inst_48 ( .ZN(net_50), .A(net_49), .B(net_48) ); 473 | XNOR2_X1 inst_69 ( .ZN(net_73), .B(net_65), .A(net_47) ); 474 | XNOR2_X1 inst_46 ( .ZN(net_48), .B(net_31), .A(net_26) ); 475 | XNOR2_X1 inst_82 ( .B(net_109), .ZN(n1345gat), .A(n148gat) ); 476 | NAND2_X1 inst_136 ( .A1(net_136), .ZN(net_94), .A2(net_72) ); 477 | XNOR2_X1 inst_30 ( .ZN(net_31), .A(n148gat), .B(n141gat) ); 478 | XNOR2_X1 inst_102 ( .B(net_139), .ZN(n1325gat), .A(n8gat) ); 479 | NOR2_X1 inst_108 ( .A2(net_118), .A1(net_112), .ZN(net_80) ); 480 | NAND2_X1 inst_165 ( .A2(net_140), .ZN(net_137), .A1(net_136) ); 481 | XNOR2_X1 inst_32 ( .ZN(net_52), .A(net_35), .B(net_29) ); 482 | XOR2_X1 inst_22 ( .Z(net_38), .A(n134gat), .B(n127gat) ); 483 | NAND2_X1 inst_144 ( .A1(net_116), .A2(net_103), .ZN(net_102) ); 484 | XNOR2_X1 inst_34 ( .ZN(net_41), .A(net_27), .B(net_18) ); 485 | XOR2_X1 inst_12 ( .Z(net_25), .A(n204gat), .B(n197gat) ); 486 | XNOR2_X1 inst_56 ( .ZN(net_64), .A(net_50), .B(net_5) ); 487 | XNOR2_X1 inst_71 ( .ZN(net_84), .B(net_68), .A(net_43) ); 488 | XOR2_X1 inst_21 ( .Z(net_37), .A(n141gat), .B(n113gat) ); 489 | OR3_X4 inst_104 ( .A2(net_145), .A1(net_138), .ZN(net_88), .A3(net_76) ); 490 | XNOR2_X1 inst_60 ( .ZN(net_68), .A(net_59), .B(net_1) ); 491 | NAND2_X1 inst_169 ( .A1(net_145), .ZN(net_144), .A2(net_134) ); 492 | NAND2_X1 inst_168 ( .ZN(net_143), .A2(net_142), .A1(net_136) ); 493 | XNOR2_X1 inst_97 ( .B(net_129), .ZN(n1330gat), .A(n43gat) ); 494 | NAND2_X1 inst_161 ( .A1(net_145), .ZN(net_130), .A2(net_127) ); 495 | NAND3_X1 inst_124 ( .A1(net_112), .ZN(net_110), .A3(net_91), .A2(net_84) ); 496 | XOR2_X1 inst_18 ( .Z(net_34), .A(n64gat), .B(n57gat) ); 497 | XOR2_X1 inst_16 ( .Z(net_29), .A(n36gat), .B(n29gat) ); 498 | XNOR2_X1 inst_88 ( .B(net_124), .ZN(n1339gat), .A(n106gat) ); 499 | XOR2_X1 inst_3 ( .Z(net_11), .A(n190gat), .B(n183gat) ); 500 | NAND2_X1 inst_156 ( .A1(net_131), .A2(net_127), .ZN(net_124) ); 501 | XOR2_X1 inst_9 ( .Z(net_19), .A(n78gat), .B(n71gat) ); 502 | NOR2_X1 inst_113 ( .ZN(net_107), .A2(net_95), .A1(net_93) ); 503 | NAND2_X1 inst_170 ( .ZN(net_146), .A1(net_145), .A2(net_140) ); 504 | XNOR2_X1 inst_50 ( .ZN(net_55), .A(net_54), .B(net_48) ); 505 | NAND2_X1 inst_137 ( .ZN(net_91), .A2(net_89), .A1(net_88) ); 506 | XNOR2_X1 inst_41 ( .ZN(net_51), .A(net_14), .B(net_13) ); 507 | NAND2_X1 inst_130 ( .ZN(net_4), .A2(n233gat), .A1(n232gat) ); 508 | XNOR2_X1 inst_91 ( .B(net_130), .ZN(n1336gat), .A(n85gat) ); 509 | NAND2_X1 inst_132 ( .ZN(net_6), .A2(n233gat), .A1(n227gat) ); 510 | NAND2_X1 inst_143 ( .A1(net_118), .A2(net_103), .ZN(net_101) ); 511 | INV_X1 inst_176 ( .ZN(net_118), .A(net_73) ); 512 | NAND2_X1 inst_152 ( .A2(net_120), .ZN(net_119), .A1(net_118) ); 513 | XNOR2_X1 inst_58 ( .ZN(net_66), .A(net_61), .B(net_2) ); 514 | XNOR2_X1 inst_36 ( .ZN(net_49), .A(net_25), .B(net_24) ); 515 | NAND2_X1 inst_147 ( .A1(net_116), .ZN(net_108), .A2(net_107) ); 516 | XNOR2_X1 inst_87 ( .B(net_106), .ZN(n1340gat), .A(n113gat) ); 517 | XNOR2_X1 inst_61 ( .ZN(net_69), .A(net_55), .B(net_0) ); 518 | XNOR2_X1 inst_45 ( .ZN(net_46), .B(net_16), .A(net_15) ); 519 | XNOR2_X1 inst_96 ( .B(net_126), .ZN(n1331gat), .A(n50gat) ); 520 | XNOR2_X1 inst_101 ( .B(net_143), .ZN(n1326gat), .A(n15gat) ); 521 | XOR2_X1 inst_0 ( .Z(net_8), .A(n8gat), .B(n1gat) ); 522 | XOR2_X1 inst_10 ( .Z(net_20), .A(n78gat), .B(n106gat) ); 523 | XOR2_X1 inst_4 ( .Z(net_12), .A(n218gat), .B(n190gat) ); 524 | XNOR2_X1 inst_65 ( .ZN(net_86), .B(net_66), .A(net_45) ); 525 | AND2_X4 inst_178 ( .A1(net_138), .ZN(net_77), .A2(net_75) ); 526 | XNOR2_X1 inst_89 ( .B(net_125), .ZN(n1338gat), .A(n99gat) ); 527 | XNOR2_X1 inst_28 ( .ZN(net_23), .A(n148gat), .B(n120gat) ); 528 | NOR2_X1 inst_111 ( .ZN(net_120), .A1(net_93), .A2(net_92) ); 529 | XNOR2_X1 inst_66 ( .ZN(net_136), .B(net_70), .A(net_46) ); 530 | NOR2_X1 inst_117 ( .ZN(net_140), .A2(net_110), .A1(net_100) ); 531 | XNOR2_X1 inst_98 ( .B(net_135), .ZN(n1329gat), .A(n36gat) ); 532 | XNOR2_X1 inst_63 ( .ZN(net_71), .A(net_62), .B(net_7) ); 533 | XOR2_X1 inst_7 ( .Z(net_16), .A(n43gat), .B(n15gat) ); 534 | XNOR2_X1 inst_49 ( .ZN(net_53), .A(net_52), .B(net_51) ); 535 | NAND3_X1 inst_120 ( .A1(net_105), .ZN(net_81), .A3(net_80), .A2(net_74) ); 536 | NAND2_X1 inst_154 ( .ZN(net_122), .A1(net_118), .A2(net_115) ); 537 | XOR2_X1 inst_13 ( .Z(net_26), .A(n162gat), .B(n155gat) ); 538 | NAND4_X1 inst_119 ( .ZN(net_90), .A2(net_87), .A1(net_85), .A3(net_83), .A4(net_81) ); 539 | XNOR2_X1 inst_75 ( .B(net_123), .ZN(n1352gat), .A(n197gat) ); 540 | NAND2_X1 inst_166 ( .A2(net_142), .ZN(net_139), .A1(net_138) ); 541 | NOR2_X1 inst_116 ( .ZN(net_127), .A1(net_111), .A2(net_110) ); 542 | NAND2_X1 inst_163 ( .A2(net_140), .ZN(net_133), .A1(net_131) ); 543 | XNOR2_X1 inst_85 ( .B(net_102), .ZN(n1342gat), .A(n127gat) ); 544 | XNOR2_X1 inst_54 ( .ZN(net_62), .A(net_60), .B(net_58) ); 545 | XNOR2_X1 inst_79 ( .B(net_96), .ZN(n1348gat), .A(n169gat) ); 546 | NOR2_X1 inst_109 ( .A2(net_138), .ZN(net_78), .A1(net_75) ); 547 | OR2_X4 inst_106 ( .A2(net_136), .ZN(net_93), .A1(net_72) ); 548 | NAND2_X1 inst_149 ( .A2(net_120), .ZN(net_113), .A1(net_112) ); 549 | XNOR2_X1 inst_43 ( .ZN(net_45), .A(net_36), .B(net_23) ); 550 | XNOR2_X1 inst_39 ( .ZN(net_56), .B(net_33), .A(net_11) ); 551 | NAND2_X1 inst_128 ( .ZN(net_2), .A2(n233gat), .A1(n230gat) ); 552 | XNOR2_X1 inst_73 ( .B(net_121), .ZN(n1354gat), .A(n211gat) ); 553 | XOR2_X1 inst_23 ( .Z(net_39), .A(n8gat), .B(n36gat) ); 554 | NAND2_X1 inst_171 ( .ZN(net_147), .A1(net_145), .A2(net_142) ); 555 | XNOR2_X1 inst_77 ( .B(net_117), .ZN(n1350gat), .A(n183gat) ); 556 | XNOR2_X1 inst_94 ( .B(net_141), .ZN(n1333gat), .A(n64gat) ); 557 | 558 | endmodule 559 | -------------------------------------------------------------------------------- /benchmark/c17.v: -------------------------------------------------------------------------------- 1 | module c17 ( 2 | nx1, 3 | nx7, 4 | nx3, 5 | nx2, 6 | nx6, 7 | nx23, 8 | nx22); 9 | 10 | // Start PIs 11 | input nx1; 12 | input nx7; 13 | input nx3; 14 | input nx2; 15 | input nx6; 16 | 17 | // Start POs 18 | output nx23; 19 | output nx22; 20 | 21 | // Start wires 22 | wire net_1; 23 | wire nx23; 24 | wire nx1; 25 | wire nx7; 26 | wire nx3; 27 | wire net_2; 28 | wire nx22; 29 | wire nx6; 30 | wire net_0; 31 | wire net_3; 32 | wire nx2; 33 | 34 | // Start cells 35 | NAND2_X1 inst_5 ( .A2(net_3), .A1(net_0), .ZN(nx22) ); 36 | NAND2_X1 inst_2 ( .ZN(net_2), .A2(net_1), .A1(nx7) ); 37 | NAND2_X1 inst_1 ( .ZN(net_0), .A2(nx3), .A1(nx1) ); 38 | NAND2_X1 inst_4 ( .A1(net_3), .A2(net_2), .ZN(nx23) ); 39 | NAND2_X1 inst_3 ( .ZN(net_3), .A2(net_1), .A1(nx2) ); 40 | NAND2_X1 inst_0 ( .ZN(net_1), .A2(nx6), .A1(nx3) ); 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /benchmark/c17_slack.v: -------------------------------------------------------------------------------- 1 | module c17_slack ( 2 | nx1, 3 | nx7, 4 | nx3, 5 | nx2, 6 | nx6, 7 | nx23, 8 | nx22); 9 | 10 | // Start PIs 11 | input nx1; 12 | input nx7; 13 | input nx3; 14 | input nx2; 15 | input nx6; 16 | 17 | // Start POs 18 | output nx23; 19 | output nx22; 20 | 21 | // Start wires 22 | wire net_1; 23 | wire nx23; 24 | wire nx1; 25 | wire nx7; 26 | wire nx3; 27 | wire net_2; 28 | wire nx22; 29 | wire nx6; 30 | wire net_0; 31 | wire net_3; 32 | wire nx2; 33 | 34 | // Start cells 35 | NAND2_X1 inst_5 ( .A2(net_3), .A1(net_0), .ZN(nx22) ); 36 | NAND2_X1 inst_2 ( .ZN(net_2), .A2(net_1), .A1(nx7) ); 37 | NAND2_X1 inst_1 ( .ZN(net_0), .A2(nx3), .A1(nx1) ); 38 | NAND2_X1 inst_4 ( .A1(net_3), .A2(net_2), .ZN(nx23) ); 39 | NAND2_X1 inst_3 ( .ZN(net_3), .A2(net_1), .A1(nx2) ); 40 | NAND2_X1 inst_0 ( .ZN(net_1), .A2(nx6), .A1(nx3) ); 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /benchmark/c1908.v: -------------------------------------------------------------------------------- 1 | module c1908 ( 2 | n227, 3 | n902, 4 | n217, 5 | n237, 6 | n143, 7 | n131, 8 | n110, 9 | n134, 10 | n952, 11 | n221, 12 | n900, 13 | n140, 14 | n113, 15 | n234, 16 | n146, 17 | n122, 18 | n472, 19 | n104, 20 | n107, 21 | n128, 22 | n953, 23 | n101, 24 | n125, 25 | n224, 26 | n116, 27 | n210, 28 | n475, 29 | n119, 30 | n478, 31 | n898, 32 | n214, 33 | n137, 34 | n469, 35 | n66, 36 | n72, 37 | n69, 38 | n54, 39 | n18, 40 | n24, 41 | n75, 42 | n60, 43 | n39, 44 | n45, 45 | n42, 46 | n30, 47 | n63, 48 | n57, 49 | n9, 50 | n21, 51 | n51, 52 | n33, 53 | n6, 54 | n15, 55 | n12, 56 | n3, 57 | n27, 58 | n48, 59 | n36); 60 | 61 | // Start PIs 62 | input n227; 63 | input n902; 64 | input n217; 65 | input n237; 66 | input n143; 67 | input n131; 68 | input n110; 69 | input n134; 70 | input n952; 71 | input n221; 72 | input n900; 73 | input n140; 74 | input n113; 75 | input n234; 76 | input n146; 77 | input n122; 78 | input n472; 79 | input n104; 80 | input n107; 81 | input n128; 82 | input n953; 83 | input n101; 84 | input n125; 85 | input n224; 86 | input n116; 87 | input n210; 88 | input n475; 89 | input n119; 90 | input n478; 91 | input n898; 92 | input n214; 93 | input n137; 94 | input n469; 95 | 96 | // Start POs 97 | output n66; 98 | output n72; 99 | output n69; 100 | output n54; 101 | output n18; 102 | output n24; 103 | output n75; 104 | output n60; 105 | output n39; 106 | output n45; 107 | output n42; 108 | output n30; 109 | output n63; 110 | output n57; 111 | output n9; 112 | output n21; 113 | output n51; 114 | output n33; 115 | output n6; 116 | output n15; 117 | output n12; 118 | output n3; 119 | output n27; 120 | output n48; 121 | output n36; 122 | 123 | // Start wires 124 | wire net_166; 125 | wire net_107; 126 | wire net_47; 127 | wire net_179; 128 | wire net_176; 129 | wire net_159; 130 | wire net_61; 131 | wire net_137; 132 | wire net_132; 133 | wire net_54; 134 | wire n18; 135 | wire net_105; 136 | wire net_62; 137 | wire net_6; 138 | wire net_129; 139 | wire net_119; 140 | wire net_98; 141 | wire net_23; 142 | wire net_117; 143 | wire net_12; 144 | wire net_151; 145 | wire net_74; 146 | wire net_53; 147 | wire net_93; 148 | wire n63; 149 | wire net_168; 150 | wire net_135; 151 | wire n27; 152 | wire net_130; 153 | wire n113; 154 | wire net_147; 155 | wire net_127; 156 | wire net_14; 157 | wire n146; 158 | wire net_113; 159 | wire net_26; 160 | wire net_76; 161 | wire n128; 162 | wire n101; 163 | wire net_101; 164 | wire net_32; 165 | wire net_187; 166 | wire net_111; 167 | wire net_90; 168 | wire net_40; 169 | wire n116; 170 | wire net_100; 171 | wire n210; 172 | wire n475; 173 | wire net_85; 174 | wire net_69; 175 | wire net_124; 176 | wire net_161; 177 | wire n119; 178 | wire net_141; 179 | wire net_160; 180 | wire net_83; 181 | wire n21; 182 | wire net_115; 183 | wire net_4; 184 | wire n36; 185 | wire net_95; 186 | wire net_17; 187 | wire net_173; 188 | wire net_78; 189 | wire net_27; 190 | wire net_164; 191 | wire n69; 192 | wire net_56; 193 | wire net_87; 194 | wire net_0; 195 | wire net_155; 196 | wire net_35; 197 | wire net_191; 198 | wire n143; 199 | wire net_22; 200 | wire net_16; 201 | wire net_181; 202 | wire n131; 203 | wire net_193; 204 | wire net_39; 205 | wire net_157; 206 | wire net_144; 207 | wire net_102; 208 | wire net_2; 209 | wire net_59; 210 | wire net_9; 211 | wire n952; 212 | wire n57; 213 | wire net_42; 214 | wire n9; 215 | wire net_120; 216 | wire net_109; 217 | wire n12; 218 | wire net_80; 219 | wire net_65; 220 | wire net_50; 221 | wire net_162; 222 | wire n234; 223 | wire net_96; 224 | wire net_66; 225 | wire net_38; 226 | wire net_44; 227 | wire net_167; 228 | wire n122; 229 | wire net_136; 230 | wire net_134; 231 | wire n107; 232 | wire net_19; 233 | wire net_89; 234 | wire net_45; 235 | wire net_126; 236 | wire n45; 237 | wire net_185; 238 | wire net_34; 239 | wire net_108; 240 | wire n478; 241 | wire net_183; 242 | wire net_178; 243 | wire net_150; 244 | wire net_63; 245 | wire n137; 246 | wire n227; 247 | wire n902; 248 | wire n72; 249 | wire net_152; 250 | wire net_116; 251 | wire net_30; 252 | wire net_189; 253 | wire n54; 254 | wire net_175; 255 | wire net_91; 256 | wire n237; 257 | wire n75; 258 | wire net_106; 259 | wire net_99; 260 | wire net_24; 261 | wire net_55; 262 | wire net_186; 263 | wire n39; 264 | wire n60; 265 | wire net_46; 266 | wire net_140; 267 | wire net_118; 268 | wire net_148; 269 | wire net_104; 270 | wire n42; 271 | wire net_146; 272 | wire n134; 273 | wire net_72; 274 | wire net_122; 275 | wire n221; 276 | wire net_25; 277 | wire net_70; 278 | wire n900; 279 | wire n51; 280 | wire net_7; 281 | wire n140; 282 | wire n48; 283 | wire net_194; 284 | wire net_172; 285 | wire net_5; 286 | wire net_52; 287 | wire net_165; 288 | wire net_128; 289 | wire n472; 290 | wire n104; 291 | wire net_138; 292 | wire net_13; 293 | wire net_184; 294 | wire net_94; 295 | wire net_11; 296 | wire net_18; 297 | wire net_123; 298 | wire net_131; 299 | wire net_114; 300 | wire n30; 301 | wire net_196; 302 | wire net_170; 303 | wire net_29; 304 | wire net_68; 305 | wire net_149; 306 | wire net_142; 307 | wire net_77; 308 | wire n898; 309 | wire n214; 310 | wire net_20; 311 | wire net_31; 312 | wire n3; 313 | wire n469; 314 | wire net_36; 315 | wire net_49; 316 | wire net_158; 317 | wire net_15; 318 | wire net_41; 319 | wire net_57; 320 | wire n217; 321 | wire net_71; 322 | wire net_153; 323 | wire net_156; 324 | wire net_3; 325 | wire net_84; 326 | wire net_174; 327 | wire net_154; 328 | wire net_112; 329 | wire net_92; 330 | wire net_1; 331 | wire net_103; 332 | wire net_139; 333 | wire n110; 334 | wire net_43; 335 | wire net_10; 336 | wire net_180; 337 | wire net_28; 338 | wire net_169; 339 | wire net_21; 340 | wire net_51; 341 | wire net_171; 342 | wire net_79; 343 | wire n15; 344 | wire net_143; 345 | wire net_97; 346 | wire net_190; 347 | wire n66; 348 | wire net_88; 349 | wire net_182; 350 | wire net_192; 351 | wire net_145; 352 | wire net_60; 353 | wire n953; 354 | wire net_81; 355 | wire n24; 356 | wire net_163; 357 | wire net_58; 358 | wire n125; 359 | wire net_82; 360 | wire net_67; 361 | wire n224; 362 | wire net_64; 363 | wire net_37; 364 | wire net_188; 365 | wire net_110; 366 | wire net_121; 367 | wire net_73; 368 | wire net_33; 369 | wire net_48; 370 | wire net_177; 371 | wire net_86; 372 | wire net_75; 373 | wire net_8; 374 | wire net_133; 375 | wire n6; 376 | wire n33; 377 | wire net_195; 378 | wire net_125; 379 | 380 | // Start cells 381 | NAND3_X1 inst_145 ( .A3(net_142), .A2(net_121), .ZN(net_120), .A1(net_119) ); 382 | NOR2_X1 inst_103 ( .ZN(net_60), .A1(net_59), .A2(net_58) ); 383 | NOR2_X1 inst_125 ( .ZN(net_162), .A2(net_153), .A1(net_152) ); 384 | AND4_X1 inst_207 ( .A1(net_121), .ZN(net_115), .A3(net_114), .A4(net_113), .A2(net_94) ); 385 | NAND4_X1 inst_138 ( .ZN(net_149), .A2(net_121), .A3(net_114), .A1(net_111), .A4(net_100) ); 386 | NAND2_X1 inst_159 ( .ZN(net_101), .A2(net_21), .A1(n214) ); 387 | AND2_X4 inst_218 ( .A1(net_114), .ZN(net_107), .A2(net_94) ); 388 | XOR2_X1 inst_15 ( .Z(net_82), .A(net_75), .B(n469) ); 389 | INV_X1 inst_197 ( .ZN(net_143), .A(net_88) ); 390 | NOR2_X1 inst_134 ( .A2(net_195), .A1(net_194), .ZN(n57) ); 391 | NAND2_X1 inst_179 ( .ZN(net_157), .A2(net_144), .A1(net_143) ); 392 | XOR2_X1 inst_24 ( .A(net_156), .Z(n12), .B(n110) ); 393 | NOR2_X1 inst_114 ( .A2(net_130), .ZN(net_118), .A1(net_88) ); 394 | XOR2_X1 inst_6 ( .Z(net_13), .A(n137), .B(n134) ); 395 | INV_X1 inst_194 ( .ZN(net_85), .A(net_80) ); 396 | NOR2_X1 inst_131 ( .A1(net_194), .A2(net_187), .ZN(n54) ); 397 | OR2_X4 inst_76 ( .A1(net_121), .ZN(net_110), .A2(net_31) ); 398 | AND2_X4 inst_214 ( .A1(net_59), .A2(net_58), .ZN(net_57) ); 399 | NAND2_X1 inst_180 ( .ZN(net_160), .A2(net_144), .A1(net_142) ); 400 | NAND2_X1 inst_160 ( .ZN(net_22), .A2(net_2), .A1(n953) ); 401 | NAND3_X1 inst_150 ( .ZN(net_181), .A3(net_180), .A1(n902), .A2(n472) ); 402 | XNOR2_X1 inst_33 ( .ZN(net_36), .A(net_7), .B(n110) ); 403 | NAND2_X1 inst_172 ( .ZN(net_126), .A1(net_108), .A2(net_107) ); 404 | NOR4_X1 inst_83 ( .ZN(net_183), .A4(net_175), .A2(net_170), .A1(net_115), .A3(net_112) ); 405 | XNOR2_X1 inst_47 ( .ZN(net_65), .B(net_43), .A(net_10) ); 406 | XOR2_X1 inst_19 ( .A(net_145), .Z(n18), .B(n116) ); 407 | NOR2_X1 inst_123 ( .ZN(net_144), .A2(net_128), .A1(net_89) ); 408 | NOR2_X1 inst_121 ( .ZN(net_146), .A1(net_126), .A2(net_103) ); 409 | XOR2_X1 inst_2 ( .Z(net_7), .A(n128), .B(n119) ); 410 | XOR2_X1 inst_8 ( .Z(net_16), .A(n143), .B(n128) ); 411 | NOR2_X1 inst_118 ( .ZN(net_111), .A1(net_101), .A2(net_99) ); 412 | NOR3_X1 inst_86 ( .ZN(net_56), .A3(net_52), .A1(net_51), .A2(net_11) ); 413 | NAND2_X1 inst_153 ( .ZN(net_3), .A2(n898), .A1(n224) ); 414 | XOR2_X1 inst_20 ( .A(net_146), .Z(n15), .B(n113) ); 415 | XOR2_X1 inst_27 ( .Z(net_176), .A(net_171), .B(net_56) ); 416 | XNOR2_X1 inst_38 ( .ZN(net_59), .A(net_26), .B(n101) ); 417 | NOR2_X1 inst_100 ( .ZN(net_31), .A2(net_30), .A1(n900) ); 418 | XNOR2_X1 inst_52 ( .ZN(net_71), .A(net_69), .B(net_65) ); 419 | NOR3_X1 inst_90 ( .ZN(net_155), .A1(net_134), .A2(net_133), .A3(net_132) ); 420 | NAND4_X1 inst_140 ( .ZN(net_175), .A4(net_174), .A2(net_172), .A3(net_137), .A1(n952) ); 421 | AND4_X1 inst_209 ( .ZN(net_196), .A1(net_191), .A2(net_131), .A3(net_125), .A4(net_122) ); 422 | AND3_X4 inst_211 ( .ZN(net_129), .A2(net_110), .A1(net_106), .A3(net_105) ); 423 | AND2_X4 inst_221 ( .ZN(net_159), .A1(net_143), .A2(net_141) ); 424 | XNOR2_X1 inst_40 ( .ZN(net_47), .A(net_46), .B(net_36) ); 425 | NAND2_X1 inst_162 ( .ZN(net_29), .A2(net_27), .A1(n221) ); 426 | NAND2_X1 inst_167 ( .ZN(net_130), .A1(net_86), .A2(net_85) ); 427 | NOR3_X1 inst_93 ( .ZN(net_156), .A1(net_134), .A3(net_132), .A2(net_130) ); 428 | NOR4_X1 inst_81 ( .ZN(net_136), .A1(net_116), .A4(net_102), .A2(net_87), .A3(net_86) ); 429 | NOR3_X1 inst_95 ( .ZN(net_169), .A1(net_166), .A2(net_165), .A3(net_164) ); 430 | XOR2_X1 inst_1 ( .Z(net_6), .A(n119), .B(n116) ); 431 | XNOR2_X1 inst_72 ( .ZN(net_195), .B(net_190), .A(net_59) ); 432 | NAND4_X1 inst_139 ( .ZN(net_164), .A1(net_160), .A3(net_151), .A4(net_150), .A2(net_138) ); 433 | NAND2_X1 inst_155 ( .A2(net_172), .ZN(net_9), .A1(n227) ); 434 | XNOR2_X1 inst_59 ( .B(net_150), .ZN(n36), .A(n134) ); 435 | NOR2_X1 inst_135 ( .A2(net_196), .A1(net_154), .ZN(n75) ); 436 | INV_X1 inst_196 ( .ZN(net_133), .A(net_90) ); 437 | XNOR2_X1 inst_44 ( .ZN(net_61), .B(net_47), .A(net_39) ); 438 | XNOR2_X1 inst_55 ( .ZN(net_86), .A(net_73), .B(net_62) ); 439 | NAND2_X1 inst_174 ( .ZN(net_128), .A1(net_110), .A2(net_109) ); 440 | NOR2_X1 inst_115 ( .A1(net_134), .ZN(net_95), .A2(net_89) ); 441 | XNOR2_X1 inst_37 ( .ZN(net_38), .A(net_13), .B(n131) ); 442 | AND3_X4 inst_210 ( .A2(net_172), .ZN(net_121), .A3(net_24), .A1(n952) ); 443 | NAND3_X1 inst_148 ( .A3(net_180), .ZN(net_178), .A1(n902), .A2(n478) ); 444 | NAND2_X1 inst_164 ( .ZN(net_89), .A1(net_86), .A2(net_80) ); 445 | INV_X1 inst_191 ( .ZN(net_116), .A(net_29) ); 446 | XOR2_X1 inst_5 ( .Z(net_12), .A(n122), .B(n113) ); 447 | NAND2_X1 inst_157 ( .A2(net_172), .ZN(net_18), .A1(n224) ); 448 | NOR3_X1 inst_84 ( .ZN(net_19), .A2(net_1), .A3(n953), .A1(n237) ); 449 | XNOR2_X1 inst_51 ( .ZN(net_74), .A(net_54), .B(net_37) ); 450 | NAND3_X1 inst_142 ( .ZN(net_30), .A1(net_24), .A3(n953), .A2(n902) ); 451 | OR2_X4 inst_80 ( .A1(net_134), .ZN(net_123), .A2(net_93) ); 452 | NAND2_X1 inst_173 ( .ZN(net_132), .A2(net_109), .A1(net_108) ); 453 | NOR2_X1 inst_105 ( .ZN(net_66), .A2(net_65), .A1(net_8) ); 454 | AND2_X4 inst_213 ( .A2(net_53), .ZN(net_51), .A1(net_50) ); 455 | XNOR2_X1 inst_68 ( .ZN(net_189), .A(net_179), .B(net_77) ); 456 | AND2_X4 inst_216 ( .A1(net_69), .ZN(net_68), .A2(net_67) ); 457 | OR2_X4 inst_78 ( .ZN(net_127), .A1(net_86), .A2(net_80) ); 458 | XNOR2_X1 inst_42 ( .ZN(net_53), .A(net_44), .B(net_38) ); 459 | NAND2_X1 inst_175 ( .ZN(net_147), .A1(net_129), .A2(net_118) ); 460 | XNOR2_X1 inst_53 ( .ZN(net_77), .A(net_55), .B(net_35) ); 461 | INV_X1 inst_205 ( .ZN(net_170), .A(net_169) ); 462 | NAND2_X1 inst_177 ( .ZN(net_151), .A1(net_129), .A2(net_104) ); 463 | NAND2_X1 inst_183 ( .ZN(net_173), .A1(net_172), .A2(net_168) ); 464 | NOR2_X1 inst_133 ( .A1(net_194), .A2(net_193), .ZN(n51) ); 465 | XOR2_X1 inst_26 ( .A(net_159), .Z(n6), .B(n104) ); 466 | NAND3_X1 inst_151 ( .ZN(net_182), .A3(net_180), .A1(n902), .A2(n469) ); 467 | NOR2_X1 inst_112 ( .ZN(net_84), .A1(net_83), .A2(net_82) ); 468 | XNOR2_X1 inst_64 ( .B(net_176), .A(net_22), .ZN(n72) ); 469 | NOR2_X1 inst_107 ( .ZN(net_75), .A2(net_74), .A1(n902) ); 470 | XNOR2_X1 inst_67 ( .ZN(net_188), .A(net_178), .B(net_63) ); 471 | NAND2_X1 inst_181 ( .ZN(net_166), .A1(net_148), .A2(net_147) ); 472 | NOR2_X1 inst_127 ( .ZN(net_185), .A2(net_184), .A1(net_73) ); 473 | XNOR2_X1 inst_70 ( .ZN(net_192), .A(net_185), .B(net_61) ); 474 | INV_X1 inst_186 ( .ZN(net_172), .A(n953) ); 475 | NOR2_X1 inst_129 ( .A1(net_194), .A2(net_189), .ZN(n60) ); 476 | NOR3_X1 inst_92 ( .ZN(net_139), .A1(net_135), .A2(net_133), .A3(net_128) ); 477 | XNOR2_X1 inst_29 ( .ZN(net_42), .A(net_6), .B(n113) ); 478 | INV_X1 inst_189 ( .ZN(net_1), .A(n214) ); 479 | XOR2_X1 inst_17 ( .Z(net_100), .A(net_79), .B(net_76) ); 480 | XOR2_X1 inst_11 ( .Z(net_39), .B(net_25), .A(n137) ); 481 | NAND3_X1 inst_146 ( .A3(net_143), .ZN(net_122), .A2(net_121), .A1(net_119) ); 482 | INV_X1 inst_188 ( .ZN(net_14), .A(n902) ); 483 | XOR2_X1 inst_14 ( .Z(net_80), .B(net_72), .A(n472) ); 484 | INV_X1 inst_202 ( .ZN(net_104), .A(net_103) ); 485 | AND4_X1 inst_206 ( .A1(net_121), .A4(net_113), .ZN(net_112), .A2(net_106), .A3(net_105) ); 486 | INV_X1 inst_187 ( .ZN(net_0), .A(n210) ); 487 | NOR2_X1 inst_122 ( .ZN(net_141), .A2(net_132), .A1(net_127) ); 488 | XNOR2_X1 inst_31 ( .ZN(net_34), .A(net_5), .B(n107) ); 489 | XOR2_X1 inst_25 ( .A(net_158), .Z(n9), .B(n107) ); 490 | NOR2_X1 inst_126 ( .ZN(net_171), .A2(net_167), .A1(n953) ); 491 | NAND2_X1 inst_158 ( .ZN(net_20), .A2(net_3), .A1(n953) ); 492 | NAND3_X1 inst_141 ( .A3(net_172), .ZN(net_23), .A1(n234), .A2(n217) ); 493 | XNOR2_X1 inst_62 ( .B(net_160), .ZN(n30), .A(n128) ); 494 | INV_X1 inst_200 ( .ZN(net_98), .A(net_97) ); 495 | NOR2_X1 inst_110 ( .ZN(net_142), .A2(net_83), .A1(net_81) ); 496 | OR3_X2 inst_74 ( .ZN(net_131), .A3(net_130), .A2(net_124), .A1(net_123) ); 497 | XNOR2_X1 inst_57 ( .B(net_147), .ZN(n42), .A(n140) ); 498 | XNOR2_X1 inst_35 ( .ZN(net_37), .A(net_15), .B(net_9) ); 499 | NOR2_X1 inst_99 ( .ZN(net_194), .A1(net_172), .A2(n952) ); 500 | XNOR2_X1 inst_48 ( .ZN(net_63), .A(net_48), .B(net_23) ); 501 | XNOR2_X1 inst_69 ( .ZN(net_190), .B(net_181), .A(net_58) ); 502 | XNOR2_X1 inst_46 ( .ZN(net_58), .B(net_53), .A(net_42) ); 503 | NOR4_X1 inst_82 ( .ZN(net_161), .A2(net_159), .A4(net_158), .A3(net_156), .A1(net_155) ); 504 | NAND4_X1 inst_136 ( .ZN(net_102), .A1(net_101), .A4(net_100), .A3(net_85), .A2(net_84) ); 505 | XNOR2_X1 inst_30 ( .ZN(net_33), .A(net_16), .B(n134) ); 506 | NOR2_X1 inst_102 ( .A2(net_53), .ZN(net_52), .A1(net_50) ); 507 | NOR2_X1 inst_108 ( .ZN(net_78), .A2(net_77), .A1(n902) ); 508 | NAND2_X1 inst_165 ( .ZN(net_135), .A1(net_87), .A2(net_83) ); 509 | XNOR2_X1 inst_32 ( .ZN(net_35), .A(net_12), .B(n104) ); 510 | XOR2_X1 inst_22 ( .A(net_155), .Z(n3), .B(n101) ); 511 | NAND3_X1 inst_144 ( .ZN(net_138), .A3(net_118), .A1(net_110), .A2(net_107) ); 512 | XNOR2_X1 inst_34 ( .ZN(net_41), .A(net_4), .B(n101) ); 513 | XOR2_X1 inst_12 ( .Z(net_43), .A(net_42), .B(net_41) ); 514 | INV_X1 inst_195 ( .A(net_114), .ZN(net_93) ); 515 | XNOR2_X1 inst_56 ( .B(net_138), .ZN(n27), .A(n125) ); 516 | XNOR2_X1 inst_71 ( .ZN(net_193), .A(net_186), .B(net_71) ); 517 | XOR2_X1 inst_21 ( .A(net_139), .Z(n45), .B(n143) ); 518 | NOR2_X1 inst_104 ( .ZN(net_64), .A2(net_63), .A1(n902) ); 519 | XNOR2_X1 inst_60 ( .B(net_151), .ZN(n33), .A(n131) ); 520 | AND2_X4 inst_215 ( .ZN(net_62), .A2(net_61), .A1(net_14) ); 521 | NAND2_X1 inst_169 ( .A1(net_142), .ZN(net_97), .A2(net_90) ); 522 | NAND2_X1 inst_168 ( .A1(net_101), .A2(net_100), .ZN(net_91) ); 523 | NOR2_X1 inst_97 ( .A1(net_172), .ZN(net_8), .A2(n898) ); 524 | NAND2_X1 inst_161 ( .ZN(net_79), .A2(net_21), .A1(n210) ); 525 | NOR2_X1 inst_124 ( .ZN(net_163), .A1(net_146), .A2(net_145) ); 526 | XOR2_X1 inst_18 ( .A(net_152), .Z(n21), .B(n119) ); 527 | XOR2_X1 inst_16 ( .Z(net_83), .A(net_78), .B(n475) ); 528 | AND4_X1 inst_208 ( .ZN(net_191), .A2(net_183), .A4(net_149), .A1(net_120), .A3(net_117) ); 529 | NOR3_X1 inst_88 ( .ZN(net_76), .A1(net_70), .A3(net_68), .A2(n902) ); 530 | AND2_X4 inst_220 ( .ZN(net_158), .A1(net_142), .A2(net_141) ); 531 | XOR2_X1 inst_3 ( .Z(net_10), .A(n122), .B(n110) ); 532 | NAND2_X1 inst_156 ( .ZN(net_27), .A2(net_14), .A1(n234) ); 533 | XOR2_X1 inst_9 ( .Z(net_17), .A(n146), .B(n143) ); 534 | NOR2_X1 inst_113 ( .A2(net_100), .ZN(net_94), .A1(net_28) ); 535 | NAND2_X1 inst_170 ( .A1(net_143), .ZN(net_103), .A2(net_90) ); 536 | INV_X1 inst_198 ( .ZN(net_105), .A(net_91) ); 537 | XNOR2_X1 inst_50 ( .ZN(net_55), .B(net_49), .A(net_46) ); 538 | NAND4_X1 inst_137 ( .A1(net_121), .ZN(net_117), .A3(net_116), .A4(net_113), .A2(net_92) ); 539 | INV_X1 inst_199 ( .ZN(net_96), .A(net_95) ); 540 | XNOR2_X1 inst_41 ( .ZN(net_48), .B(net_34), .A(net_33) ); 541 | NOR2_X1 inst_130 ( .A1(net_194), .A2(net_188), .ZN(n63) ); 542 | NOR3_X1 inst_91 ( .ZN(net_153), .A1(net_135), .A2(net_127), .A3(net_126) ); 543 | NOR2_X1 inst_132 ( .A1(net_194), .A2(net_192), .ZN(n66) ); 544 | NAND3_X1 inst_143 ( .A3(net_172), .ZN(net_25), .A1(n234), .A2(n221) ); 545 | NAND2_X1 inst_176 ( .ZN(net_148), .A1(net_129), .A2(net_95) ); 546 | NAND2_X1 inst_152 ( .ZN(net_2), .A2(n900), .A1(n227) ); 547 | XNOR2_X1 inst_58 ( .B(net_148), .ZN(n39), .A(n137) ); 548 | XNOR2_X1 inst_36 ( .ZN(net_44), .A(net_17), .B(n128) ); 549 | NAND3_X1 inst_147 ( .ZN(net_168), .A2(net_163), .A1(net_162), .A3(net_161) ); 550 | NOR3_X1 inst_87 ( .ZN(net_72), .A3(net_60), .A1(net_57), .A2(n902) ); 551 | XNOR2_X1 inst_61 ( .B(net_157), .ZN(n48), .A(n146) ); 552 | INV_X1 inst_203 ( .ZN(net_137), .A(net_136) ); 553 | XNOR2_X1 inst_45 ( .ZN(net_54), .B(net_53), .A(net_41) ); 554 | NOR3_X1 inst_96 ( .ZN(net_167), .A2(net_166), .A1(net_165), .A3(net_164) ); 555 | AND3_X4 inst_212 ( .ZN(net_174), .A1(net_163), .A2(net_162), .A3(net_161) ); 556 | NOR2_X1 inst_101 ( .ZN(net_32), .A2(net_30), .A1(n898) ); 557 | XOR2_X1 inst_0 ( .Z(net_5), .A(n122), .B(n116) ); 558 | NAND2_X1 inst_184 ( .ZN(net_180), .A2(net_174), .A1(net_169) ); 559 | XOR2_X1 inst_10 ( .B(net_50), .Z(net_46), .A(n146) ); 560 | XOR2_X1 inst_4 ( .Z(net_50), .A(n140), .B(n125) ); 561 | XNOR2_X1 inst_65 ( .B(net_177), .A(net_20), .ZN(n69) ); 562 | NAND2_X1 inst_178 ( .ZN(net_150), .A1(net_129), .A2(net_98) ); 563 | NOR3_X1 inst_89 ( .A3(net_127), .ZN(net_119), .A2(net_93), .A1(net_91) ); 564 | XNOR2_X1 inst_28 ( .ZN(net_4), .A(n107), .B(n104) ); 565 | NOR2_X1 inst_111 ( .ZN(net_90), .A1(net_86), .A2(net_85) ); 566 | XNOR2_X1 inst_66 ( .ZN(net_187), .A(net_182), .B(net_74) ); 567 | NOR2_X1 inst_117 ( .ZN(net_92), .A2(net_91), .A1(net_82) ); 568 | NOR2_X1 inst_98 ( .A1(net_172), .ZN(net_11), .A2(n900) ); 569 | INV_X1 inst_190 ( .A(net_101), .ZN(net_28) ); 570 | XNOR2_X1 inst_63 ( .ZN(net_177), .B(net_173), .A(net_66) ); 571 | XOR2_X1 inst_7 ( .Z(net_15), .A(n140), .B(n110) ); 572 | INV_X1 inst_204 ( .ZN(net_140), .A(net_139) ); 573 | NAND2_X1 inst_185 ( .ZN(net_184), .A2(net_180), .A1(n902) ); 574 | NAND2_X1 inst_182 ( .ZN(net_165), .A1(net_157), .A2(net_140) ); 575 | XNOR2_X1 inst_49 ( .ZN(net_69), .A(net_45), .B(net_18) ); 576 | NOR2_X1 inst_120 ( .ZN(net_145), .A1(net_126), .A2(net_97) ); 577 | NAND2_X1 inst_154 ( .ZN(net_24), .A2(n237), .A1(n234) ); 578 | XOR2_X1 inst_13 ( .Z(net_45), .B(net_44), .A(n125) ); 579 | NOR2_X1 inst_119 ( .ZN(net_152), .A1(net_126), .A2(net_96) ); 580 | OR2_X4 inst_75 ( .ZN(net_21), .A2(n902), .A1(n237) ); 581 | INV_X1 inst_192 ( .ZN(net_67), .A(net_65) ); 582 | NAND2_X1 inst_166 ( .ZN(net_88), .A2(net_83), .A1(net_81) ); 583 | NOR2_X1 inst_116 ( .A1(net_134), .A2(net_127), .ZN(net_113) ); 584 | NAND2_X1 inst_163 ( .ZN(net_73), .A2(net_27), .A1(n217) ); 585 | NOR3_X1 inst_85 ( .ZN(net_26), .A2(net_0), .A3(n953), .A1(n237) ); 586 | XNOR2_X1 inst_54 ( .ZN(net_81), .A(net_64), .B(n478) ); 587 | OR2_X4 inst_79 ( .ZN(net_134), .A1(net_87), .A2(net_83) ); 588 | NOR2_X1 inst_109 ( .A1(net_116), .ZN(net_114), .A2(net_82) ); 589 | NOR2_X1 inst_106 ( .ZN(net_70), .A1(net_69), .A2(net_67) ); 590 | AND2_X4 inst_219 ( .ZN(net_109), .A1(net_106), .A2(net_94) ); 591 | INV_X1 inst_201 ( .A(net_113), .ZN(net_99) ); 592 | INV_X1 inst_193 ( .ZN(net_87), .A(net_81) ); 593 | NAND3_X1 inst_149 ( .A3(net_180), .ZN(net_179), .A1(n902), .A2(n475) ); 594 | XNOR2_X1 inst_43 ( .ZN(net_49), .A(net_40), .B(n131) ); 595 | XNOR2_X1 inst_39 ( .ZN(net_40), .A(net_19), .B(n143) ); 596 | NOR2_X1 inst_128 ( .ZN(net_186), .A2(net_184), .A1(net_79) ); 597 | OR3_X2 inst_73 ( .A2(net_133), .ZN(net_125), .A1(net_124), .A3(net_123) ); 598 | AND2_X4 inst_217 ( .ZN(net_106), .A2(net_82), .A1(net_29) ); 599 | XOR2_X1 inst_23 ( .A(net_153), .Z(n24), .B(n122) ); 600 | NAND2_X1 inst_171 ( .ZN(net_124), .A1(net_121), .A2(net_105) ); 601 | OR2_X4 inst_77 ( .A1(net_121), .ZN(net_108), .A2(net_32) ); 602 | NOR3_X1 inst_94 ( .ZN(net_154), .A3(net_136), .A2(n953), .A1(n952) ); 603 | 604 | endmodule 605 | -------------------------------------------------------------------------------- /benchmark/c3_path.v: -------------------------------------------------------------------------------- 1 | module c3_path ( 2 | nx1, 3 | nx3, 4 | nx2, 5 | nx4, 6 | nx33, 7 | nx44, 8 | nx12); 9 | 10 | // Start PIs 11 | input nx1; 12 | input nx3; 13 | input nx2; 14 | input nx4; 15 | 16 | // Start POs 17 | output nx33; 18 | output nx44; 19 | output nx12; 20 | 21 | // Start wires 22 | wire nx1; 23 | wire nx3; 24 | wire nx33; 25 | wire nx44; 26 | wire nx12; 27 | wire nx2; 28 | wire nx4; 29 | 30 | // Start cells 31 | BUF_X1 inst_2 ( .Z(nx44), .A(nx4) ); 32 | INV_X1 inst_1 ( .ZN(nx33), .A(nx3) ); 33 | NAND2_X1 inst_0 ( .ZN(nx12), .A2(nx2), .A1(nx1) ); 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /benchmark/c3_slack.v: -------------------------------------------------------------------------------- 1 | module c3_slack ( 2 | nx1, 3 | nx3, 4 | nx2, 5 | nx4, 6 | nx33, 7 | nx44, 8 | nx12); 9 | 10 | // Start PIs 11 | input nx1; 12 | input nx3; 13 | input nx2; 14 | input nx4; 15 | 16 | // Start POs 17 | output nx33; 18 | output nx44; 19 | output nx12; 20 | 21 | // Start wires 22 | wire nx1; 23 | wire nx3; 24 | wire nx33; 25 | wire nx44; 26 | wire nx12; 27 | wire nx2; 28 | wire nx4; 29 | 30 | // Start cells 31 | BUF_X1 inst_2 ( .Z(nx44), .A(nx4) ); 32 | INV_X1 inst_1 ( .ZN(nx33), .A(nx3) ); 33 | NAND2_X1 inst_0 ( .ZN(nx12), .A2(nx2), .A1(nx1) ); 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /benchmark/c432.v: -------------------------------------------------------------------------------- 1 | module c432 ( 2 | n43gat, 3 | n17gat, 4 | n34gat, 5 | n27gat, 6 | n82gat, 7 | n99gat, 8 | n21gat, 9 | n66gat, 10 | n102gat, 11 | n47gat, 12 | n92gat, 13 | n14gat, 14 | n95gat, 15 | n105gat, 16 | n30gat, 17 | n1gat, 18 | n40gat, 19 | n37gat, 20 | n4gat, 21 | n112gat, 22 | n76gat, 23 | n56gat, 24 | n115gat, 25 | n53gat, 26 | n86gat, 27 | n69gat, 28 | n8gat, 29 | n79gat, 30 | n73gat, 31 | n11gat, 32 | n60gat, 33 | n50gat, 34 | n108gat, 35 | n63gat, 36 | n24gat, 37 | n89gat, 38 | n432gat, 39 | n430gat, 40 | n421gat, 41 | n370gat, 42 | n329gat, 43 | n223gat, 44 | n431gat); 45 | 46 | // Start PIs 47 | input n43gat; 48 | input n17gat; 49 | input n34gat; 50 | input n27gat; 51 | input n82gat; 52 | input n99gat; 53 | input n21gat; 54 | input n66gat; 55 | input n102gat; 56 | input n47gat; 57 | input n92gat; 58 | input n14gat; 59 | input n95gat; 60 | input n105gat; 61 | input n30gat; 62 | input n1gat; 63 | input n40gat; 64 | input n37gat; 65 | input n4gat; 66 | input n112gat; 67 | input n76gat; 68 | input n56gat; 69 | input n115gat; 70 | input n53gat; 71 | input n86gat; 72 | input n69gat; 73 | input n8gat; 74 | input n79gat; 75 | input n73gat; 76 | input n11gat; 77 | input n60gat; 78 | input n50gat; 79 | input n108gat; 80 | input n63gat; 81 | input n24gat; 82 | input n89gat; 83 | 84 | // Start POs 85 | output n432gat; 86 | output n430gat; 87 | output n421gat; 88 | output n370gat; 89 | output n329gat; 90 | output n223gat; 91 | output n431gat; 92 | 93 | // Start wires 94 | wire n43gat; 95 | wire net_107; 96 | wire net_47; 97 | wire n34gat; 98 | wire n82gat; 99 | wire n99gat; 100 | wire net_61; 101 | wire net_54; 102 | wire n66gat; 103 | wire net_105; 104 | wire net_62; 105 | wire net_6; 106 | wire net_119; 107 | wire net_98; 108 | wire net_23; 109 | wire net_117; 110 | wire net_12; 111 | wire n102gat; 112 | wire net_74; 113 | wire net_53; 114 | wire net_93; 115 | wire n105gat; 116 | wire n30gat; 117 | wire n40gat; 118 | wire n37gat; 119 | wire n112gat; 120 | wire n432gat; 121 | wire n56gat; 122 | wire net_14; 123 | wire net_113; 124 | wire net_26; 125 | wire net_76; 126 | wire net_101; 127 | wire net_32; 128 | wire net_111; 129 | wire net_90; 130 | wire net_40; 131 | wire net_100; 132 | wire n8gat; 133 | wire net_85; 134 | wire net_69; 135 | wire net_124; 136 | wire net_83; 137 | wire net_115; 138 | wire n63gat; 139 | wire net_4; 140 | wire net_95; 141 | wire net_17; 142 | wire net_78; 143 | wire n17gat; 144 | wire net_27; 145 | wire n370gat; 146 | wire net_56; 147 | wire net_87; 148 | wire net_0; 149 | wire net_35; 150 | wire net_22; 151 | wire net_16; 152 | wire net_39; 153 | wire n92gat; 154 | wire net_102; 155 | wire net_2; 156 | wire net_59; 157 | wire n14gat; 158 | wire net_9; 159 | wire net_42; 160 | wire net_120; 161 | wire n95gat; 162 | wire net_109; 163 | wire net_80; 164 | wire net_65; 165 | wire net_50; 166 | wire net_96; 167 | wire net_66; 168 | wire net_38; 169 | wire net_44; 170 | wire n421gat; 171 | wire net_19; 172 | wire n53gat; 173 | wire net_89; 174 | wire net_45; 175 | wire n69gat; 176 | wire net_126; 177 | wire net_34; 178 | wire n79gat; 179 | wire net_108; 180 | wire n50gat; 181 | wire net_63; 182 | wire n89gat; 183 | wire n430gat; 184 | wire n27gat; 185 | wire net_116; 186 | wire net_30; 187 | wire net_91; 188 | wire net_106; 189 | wire net_99; 190 | wire net_24; 191 | wire net_55; 192 | wire net_46; 193 | wire net_118; 194 | wire net_104; 195 | wire n47gat; 196 | wire net_72; 197 | wire net_122; 198 | wire net_25; 199 | wire net_7; 200 | wire net_70; 201 | wire n4gat; 202 | wire n431gat; 203 | wire n76gat; 204 | wire net_5; 205 | wire net_52; 206 | wire net_13; 207 | wire net_94; 208 | wire net_11; 209 | wire net_18; 210 | wire n73gat; 211 | wire net_123; 212 | wire n11gat; 213 | wire net_114; 214 | wire n60gat; 215 | wire net_29; 216 | wire net_68; 217 | wire net_77; 218 | wire net_20; 219 | wire net_31; 220 | wire net_36; 221 | wire net_49; 222 | wire net_15; 223 | wire net_41; 224 | wire net_57; 225 | wire n21gat; 226 | wire net_71; 227 | wire net_3; 228 | wire net_84; 229 | wire net_112; 230 | wire net_92; 231 | wire net_1; 232 | wire net_103; 233 | wire net_43; 234 | wire net_10; 235 | wire net_28; 236 | wire net_21; 237 | wire net_51; 238 | wire net_79; 239 | wire n1gat; 240 | wire net_97; 241 | wire net_88; 242 | wire net_60; 243 | wire n115gat; 244 | wire net_81; 245 | wire net_58; 246 | wire n86gat; 247 | wire n329gat; 248 | wire net_67; 249 | wire net_82; 250 | wire n223gat; 251 | wire net_64; 252 | wire net_37; 253 | wire net_110; 254 | wire net_121; 255 | wire net_73; 256 | wire net_33; 257 | wire net_48; 258 | wire net_86; 259 | wire net_8; 260 | wire net_75; 261 | wire n108gat; 262 | wire net_125; 263 | wire n24gat; 264 | 265 | // Start cells 266 | INV_X1 inst_103 ( .ZN(net_3), .A(n79gat) ); 267 | INV_X1 inst_125 ( .A(net_113), .ZN(net_108) ); 268 | XNOR2_X1 inst_15 ( .ZN(net_81), .A(net_65), .B(n329gat) ); 269 | OR2_X4 inst_24 ( .A1(net_48), .ZN(net_26), .A2(n1gat) ); 270 | INV_X1 inst_114 ( .ZN(net_14), .A(n73gat) ); 271 | XNOR2_X1 inst_6 ( .ZN(net_45), .A(net_27), .B(n223gat) ); 272 | AND3_X4 inst_131 ( .ZN(net_55), .A3(net_44), .A2(net_6), .A1(n43gat) ); 273 | NAND2_X1 inst_76 ( .ZN(net_61), .A1(net_60), .A2(net_56) ); 274 | NOR3_X1 inst_33 ( .ZN(net_119), .A3(net_118), .A2(net_111), .A1(net_106) ); 275 | NAND2_X1 inst_83 ( .ZN(net_72), .A2(n329gat), .A1(n112gat) ); 276 | NAND4_X1 inst_47 ( .ZN(net_85), .A4(net_82), .A3(net_42), .A2(net_13), .A1(n95gat) ); 277 | OR3_X4 inst_19 ( .A2(net_30), .A3(net_29), .A1(net_28), .ZN(n223gat) ); 278 | INV_X1 inst_123 ( .A(net_116), .ZN(net_106) ); 279 | INV_X1 inst_121 ( .ZN(net_21), .A(net_20) ); 280 | XNOR2_X1 inst_2 ( .ZN(net_44), .A(net_24), .B(n223gat) ); 281 | XNOR2_X1 inst_8 ( .ZN(net_49), .A(net_19), .B(n223gat) ); 282 | INV_X1 inst_118 ( .ZN(net_16), .A(n115gat) ); 283 | NAND2_X1 inst_86 ( .ZN(net_95), .A2(n370gat), .A1(n115gat) ); 284 | OR3_X4 inst_20 ( .ZN(net_60), .A1(net_46), .A3(net_45), .A2(n21gat) ); 285 | NOR4_X1 inst_27 ( .ZN(net_64), .A1(net_63), .A3(net_62), .A2(net_61), .A4(net_52) ); 286 | NOR2_X1 inst_38 ( .ZN(net_29), .A1(net_11), .A2(n102gat) ); 287 | INV_X1 inst_100 ( .ZN(net_0), .A(n69gat) ); 288 | NAND4_X1 inst_52 ( .ZN(net_90), .A4(net_78), .A3(net_49), .A2(net_4), .A1(n30gat) ); 289 | NAND2_X1 inst_90 ( .ZN(net_99), .A2(n370gat), .A1(n14gat) ); 290 | NOR2_X1 inst_40 ( .A1(net_51), .ZN(net_20), .A2(n76gat) ); 291 | NAND2_X1 inst_93 ( .ZN(net_102), .A2(n370gat), .A1(n40gat) ); 292 | NAND2_X1 inst_81 ( .ZN(net_70), .A2(n329gat), .A1(n34gat) ); 293 | NAND2_X1 inst_95 ( .ZN(net_112), .A1(net_111), .A2(net_105) ); 294 | XNOR2_X1 inst_1 ( .ZN(net_42), .A(net_30), .B(n223gat) ); 295 | NAND2_X1 inst_72 ( .ZN(net_36), .A2(n223gat), .A1(n50gat) ); 296 | NAND4_X1 inst_59 ( .ZN(net_114), .A1(net_101), .A4(net_69), .A3(net_32), .A2(n43gat) ); 297 | NOR2_X1 inst_44 ( .ZN(net_123), .A2(net_114), .A1(net_108) ); 298 | NAND4_X1 inst_55 ( .ZN(net_116), .A1(net_98), .A4(net_66), .A3(net_33), .A2(n82gat) ); 299 | INV_X1 inst_115 ( .ZN(net_15), .A(n53gat) ); 300 | NOR2_X1 inst_37 ( .ZN(net_30), .A1(net_1), .A2(n89gat) ); 301 | XNOR2_X1 inst_5 ( .ZN(net_50), .A(net_21), .B(n223gat) ); 302 | NAND2_X1 inst_84 ( .ZN(net_73), .A2(n329gat), .A1(n99gat) ); 303 | NAND4_X1 inst_51 ( .ZN(net_89), .A4(net_77), .A3(net_41), .A2(net_9), .A1(n56gat) ); 304 | NAND2_X1 inst_80 ( .ZN(net_69), .A2(n329gat), .A1(n47gat) ); 305 | INV_X1 inst_105 ( .ZN(net_5), .A(n112gat) ); 306 | NAND2_X1 inst_68 ( .ZN(net_32), .A2(n223gat), .A1(n37gat) ); 307 | NAND2_X1 inst_78 ( .ZN(net_67), .A2(n329gat), .A1(n8gat) ); 308 | NOR2_X1 inst_42 ( .ZN(net_56), .A1(net_55), .A2(net_54) ); 309 | NAND4_X1 inst_53 ( .A4(net_94), .A1(net_87), .A2(net_86), .A3(net_85), .ZN(n370gat) ); 310 | AND2_X2 inst_133 ( .A1(net_125), .A2(net_104), .ZN(n421gat) ); 311 | NOR4_X1 inst_26 ( .ZN(net_25), .A1(net_24), .A2(net_23), .A3(net_22), .A4(net_20) ); 312 | INV_X1 inst_112 ( .ZN(net_12), .A(n60gat) ); 313 | NAND3_X1 inst_64 ( .ZN(net_93), .A1(net_90), .A2(net_89), .A3(net_88) ); 314 | INV_X1 inst_107 ( .ZN(net_7), .A(n43gat) ); 315 | NAND2_X1 inst_67 ( .ZN(net_31), .A2(n223gat), .A1(n1gat) ); 316 | AND3_X4 inst_127 ( .ZN(net_63), .A3(net_40), .A2(net_14), .A1(n69gat) ); 317 | NAND2_X1 inst_70 ( .ZN(net_34), .A2(n223gat), .A1(n11gat) ); 318 | AND3_X4 inst_129 ( .ZN(net_58), .A3(net_42), .A2(net_2), .A1(n95gat) ); 319 | NAND2_X1 inst_92 ( .ZN(net_101), .A2(n370gat), .A1(n53gat) ); 320 | NOR4_X1 inst_29 ( .ZN(net_91), .A4(net_79), .A1(net_48), .A3(net_47), .A2(n14gat) ); 321 | XNOR2_X1 inst_17 ( .ZN(net_83), .A(net_63), .B(n329gat) ); 322 | XNOR2_X1 inst_11 ( .ZN(net_77), .A(net_54), .B(n329gat) ); 323 | XNOR2_X1 inst_14 ( .ZN(net_80), .A(net_60), .B(n329gat) ); 324 | INV_X1 inst_122 ( .ZN(net_53), .A(net_52) ); 325 | NOR4_X1 inst_31 ( .ZN(net_94), .A2(net_93), .A3(net_92), .A4(net_91), .A1(net_84) ); 326 | OR2_X4 inst_25 ( .A1(net_46), .ZN(net_27), .A2(n11gat) ); 327 | INV_X1 inst_126 ( .ZN(net_110), .A(net_109) ); 328 | NAND4_X1 inst_62 ( .ZN(net_105), .A1(net_95), .A4(net_72), .A3(net_35), .A2(n108gat) ); 329 | INV_X1 inst_110 ( .ZN(net_10), .A(n24gat) ); 330 | NAND2_X1 inst_74 ( .ZN(net_38), .A2(n223gat), .A1(n89gat) ); 331 | NAND4_X1 inst_57 ( .ZN(net_107), .A1(net_100), .A4(net_68), .A3(net_36), .A2(n56gat) ); 332 | NOR3_X1 inst_35 ( .A2(net_124), .ZN(net_122), .A3(net_115), .A1(net_112) ); 333 | INV_X1 inst_99 ( .ZN(net_46), .A(n17gat) ); 334 | NAND4_X1 inst_48 ( .ZN(net_86), .A4(net_75), .A3(net_43), .A2(net_16), .A1(n108gat) ); 335 | NAND2_X1 inst_69 ( .ZN(net_33), .A2(n223gat), .A1(n76gat) ); 336 | NAND4_X1 inst_46 ( .ZN(net_28), .A1(net_27), .A3(net_26), .A4(net_25), .A2(net_18) ); 337 | NAND2_X1 inst_82 ( .ZN(net_71), .A2(n329gat), .A1(n21gat) ); 338 | NOR4_X1 inst_30 ( .ZN(net_92), .A4(net_80), .A1(net_46), .A3(net_45), .A2(n27gat) ); 339 | INV_X1 inst_102 ( .ZN(net_2), .A(n99gat) ); 340 | INV_X1 inst_108 ( .ZN(net_8), .A(n56gat) ); 341 | NOR3_X1 inst_32 ( .ZN(net_52), .A1(net_48), .A3(net_47), .A2(n8gat) ); 342 | OR3_X2 inst_22 ( .A2(net_124), .A3(net_123), .A1(net_120), .ZN(n430gat) ); 343 | NOR3_X1 inst_34 ( .ZN(net_126), .A1(net_121), .A2(net_120), .A3(net_118) ); 344 | XNOR2_X1 inst_12 ( .ZN(net_78), .A(net_62), .B(n329gat) ); 345 | NAND4_X1 inst_56 ( .ZN(net_104), .A1(net_99), .A4(net_67), .A3(net_31), .A2(n4gat) ); 346 | NAND2_X1 inst_71 ( .ZN(net_35), .A2(n223gat), .A1(n102gat) ); 347 | OR3_X4 inst_21 ( .ZN(net_65), .A1(net_51), .A3(net_50), .A2(n86gat) ); 348 | INV_X1 inst_104 ( .ZN(net_4), .A(n40gat) ); 349 | NAND4_X1 inst_60 ( .ZN(net_113), .A1(net_102), .A4(net_70), .A3(net_39), .A2(n30gat) ); 350 | NAND2_X1 inst_97 ( .ZN(net_115), .A1(net_114), .A2(net_107) ); 351 | INV_X1 inst_124 ( .ZN(net_120), .A(net_107) ); 352 | OR4_X1 inst_18 ( .A1(net_126), .A4(net_123), .A2(net_119), .A3(net_110), .ZN(n432gat) ); 353 | XNOR2_X1 inst_16 ( .ZN(net_82), .A(net_58), .B(n329gat) ); 354 | NAND2_X1 inst_88 ( .ZN(net_97), .A2(n370gat), .A1(n79gat) ); 355 | XNOR2_X1 inst_3 ( .ZN(net_41), .A(net_23), .B(n223gat) ); 356 | XNOR2_X1 inst_9 ( .ZN(net_75), .A(net_57), .B(n329gat) ); 357 | INV_X1 inst_113 ( .ZN(net_13), .A(n105gat) ); 358 | NAND4_X1 inst_50 ( .ZN(net_88), .A4(net_76), .A3(net_44), .A2(net_15), .A1(n43gat) ); 359 | NOR2_X1 inst_41 ( .ZN(net_24), .A1(net_7), .A2(n37gat) ); 360 | AND3_X4 inst_130 ( .ZN(net_57), .A3(net_43), .A2(net_5), .A1(n108gat) ); 361 | NAND2_X1 inst_91 ( .ZN(net_100), .A2(n370gat), .A1(n66gat) ); 362 | AND3_X4 inst_132 ( .ZN(net_62), .A3(net_49), .A2(net_17), .A1(n30gat) ); 363 | NAND4_X1 inst_58 ( .ZN(net_121), .A1(net_97), .A4(net_74), .A3(net_37), .A2(n69gat) ); 364 | NOR2_X1 inst_36 ( .ZN(net_22), .A1(net_0), .A2(n63gat) ); 365 | NAND2_X1 inst_87 ( .ZN(net_96), .A2(n370gat), .A1(n105gat) ); 366 | NAND4_X1 inst_61 ( .ZN(net_109), .A1(net_103), .A4(net_71), .A3(net_34), .A2(n17gat) ); 367 | NOR2_X1 inst_45 ( .ZN(net_117), .A1(net_116), .A2(net_115) ); 368 | NAND2_X1 inst_96 ( .ZN(net_118), .A2(net_114), .A1(net_113) ); 369 | INV_X1 inst_101 ( .ZN(net_1), .A(n95gat) ); 370 | XNOR2_X1 inst_0 ( .ZN(net_40), .A(net_22), .B(n223gat) ); 371 | XNOR2_X1 inst_10 ( .ZN(net_76), .A(net_55), .B(n329gat) ); 372 | XNOR2_X1 inst_4 ( .ZN(net_43), .A(net_29), .B(n223gat) ); 373 | NAND3_X1 inst_65 ( .ZN(net_125), .A3(net_122), .A2(net_121), .A1(net_116) ); 374 | NAND2_X1 inst_89 ( .ZN(net_98), .A2(n370gat), .A1(n92gat) ); 375 | NOR4_X1 inst_28 ( .ZN(net_84), .A4(net_81), .A1(net_51), .A3(net_50), .A2(n92gat) ); 376 | INV_X1 inst_111 ( .ZN(net_11), .A(n108gat) ); 377 | NAND2_X1 inst_66 ( .ZN(net_18), .A2(net_10), .A1(n30gat) ); 378 | INV_X1 inst_117 ( .ZN(net_48), .A(n4gat) ); 379 | NAND2_X1 inst_98 ( .ZN(net_124), .A2(net_113), .A1(net_109) ); 380 | NAND3_X2 inst_63 ( .A2(net_65), .A1(net_64), .A3(net_59), .ZN(n329gat) ); 381 | XNOR2_X1 inst_7 ( .ZN(net_47), .A(net_26), .B(n223gat) ); 382 | NAND4_X1 inst_49 ( .ZN(net_87), .A4(net_83), .A3(net_40), .A2(net_3), .A1(n69gat) ); 383 | INV_X1 inst_120 ( .ZN(net_19), .A(net_18) ); 384 | XNOR2_X1 inst_13 ( .ZN(net_79), .A(net_53), .B(n329gat) ); 385 | INV_X1 inst_119 ( .ZN(net_17), .A(n34gat) ); 386 | NAND2_X1 inst_75 ( .ZN(net_39), .A2(n223gat), .A1(n24gat) ); 387 | INV_X1 inst_116 ( .ZN(net_51), .A(n82gat) ); 388 | NAND2_X1 inst_85 ( .ZN(net_74), .A2(n329gat), .A1(n73gat) ); 389 | NAND4_X1 inst_54 ( .ZN(net_111), .A1(net_96), .A4(net_73), .A3(net_38), .A2(n95gat) ); 390 | NAND2_X1 inst_79 ( .ZN(net_68), .A2(n329gat), .A1(n60gat) ); 391 | INV_X1 inst_109 ( .ZN(net_9), .A(n66gat) ); 392 | INV_X1 inst_106 ( .ZN(net_6), .A(n47gat) ); 393 | NOR2_X1 inst_43 ( .ZN(net_59), .A1(net_58), .A2(net_57) ); 394 | NOR2_X1 inst_39 ( .ZN(net_23), .A1(net_8), .A2(n50gat) ); 395 | AND3_X4 inst_128 ( .ZN(net_54), .A3(net_41), .A2(net_12), .A1(n56gat) ); 396 | NAND2_X1 inst_73 ( .ZN(net_37), .A2(n223gat), .A1(n63gat) ); 397 | OR3_X2 inst_23 ( .A3(net_126), .A2(net_124), .A1(net_117), .ZN(n431gat) ); 398 | NAND2_X1 inst_77 ( .ZN(net_66), .A2(n329gat), .A1(n86gat) ); 399 | NAND2_X1 inst_94 ( .ZN(net_103), .A2(n370gat), .A1(n27gat) ); 400 | 401 | endmodule 402 | -------------------------------------------------------------------------------- /benchmark/c499.v: -------------------------------------------------------------------------------- 1 | module c499 ( 2 | nid20, 3 | nid6, 4 | nid21, 5 | nic7, 6 | nid0, 7 | nid11, 8 | nid13, 9 | nr, 10 | nic0, 11 | nid1, 12 | nic4, 13 | nid10, 14 | nid31, 15 | nid3, 16 | nic1, 17 | nid22, 18 | nic3, 19 | nid26, 20 | nid23, 21 | nid16, 22 | nid17, 23 | nid27, 24 | nid9, 25 | nic2, 26 | nid7, 27 | nic5, 28 | nid30, 29 | nic6, 30 | nid14, 31 | nid29, 32 | nid8, 33 | nid12, 34 | nid5, 35 | nid15, 36 | nid25, 37 | nid18, 38 | nid28, 39 | nid24, 40 | nid4, 41 | nid19, 42 | nid2, 43 | nod24, 44 | nod6, 45 | nod23, 46 | nod31, 47 | nod14, 48 | nod11, 49 | nod19, 50 | nod28, 51 | nod12, 52 | nod5, 53 | nod13, 54 | nod3, 55 | nod21, 56 | nod29, 57 | nod1, 58 | nod7, 59 | nod17, 60 | nod30, 61 | nod18, 62 | nod4, 63 | nod10, 64 | nod15, 65 | nod0, 66 | nod16, 67 | nod20, 68 | nod27, 69 | nod2, 70 | nod9, 71 | nod25, 72 | nod8, 73 | nod26, 74 | nod22); 75 | 76 | // Start PIs 77 | input nid20; 78 | input nid6; 79 | input nid21; 80 | input nic7; 81 | input nid0; 82 | input nid11; 83 | input nid13; 84 | input nr; 85 | input nic0; 86 | input nid1; 87 | input nic4; 88 | input nid10; 89 | input nid31; 90 | input nid3; 91 | input nic1; 92 | input nid22; 93 | input nic3; 94 | input nid26; 95 | input nid23; 96 | input nid16; 97 | input nid17; 98 | input nid27; 99 | input nid9; 100 | input nic2; 101 | input nid7; 102 | input nic5; 103 | input nid30; 104 | input nic6; 105 | input nid14; 106 | input nid29; 107 | input nid8; 108 | input nid12; 109 | input nid5; 110 | input nid15; 111 | input nid25; 112 | input nid18; 113 | input nid28; 114 | input nid24; 115 | input nid4; 116 | input nid19; 117 | input nid2; 118 | 119 | // Start POs 120 | output nod24; 121 | output nod6; 122 | output nod23; 123 | output nod31; 124 | output nod14; 125 | output nod11; 126 | output nod19; 127 | output nod28; 128 | output nod12; 129 | output nod5; 130 | output nod13; 131 | output nod3; 132 | output nod21; 133 | output nod29; 134 | output nod1; 135 | output nod7; 136 | output nod17; 137 | output nod30; 138 | output nod18; 139 | output nod4; 140 | output nod10; 141 | output nod15; 142 | output nod0; 143 | output nod16; 144 | output nod20; 145 | output nod27; 146 | output nod2; 147 | output nod9; 148 | output nod25; 149 | output nod8; 150 | output nod26; 151 | output nod22; 152 | 153 | // Start wires 154 | wire net_107; 155 | wire net_47; 156 | wire nod23; 157 | wire net_61; 158 | wire net_137; 159 | wire nid21; 160 | wire net_132; 161 | wire net_54; 162 | wire net_105; 163 | wire net_62; 164 | wire net_6; 165 | wire nid13; 166 | wire net_129; 167 | wire net_119; 168 | wire net_98; 169 | wire nod30; 170 | wire net_23; 171 | wire net_117; 172 | wire net_12; 173 | wire net_74; 174 | wire net_53; 175 | wire net_93; 176 | wire net_135; 177 | wire nid3; 178 | wire net_130; 179 | wire nic3; 180 | wire nod26; 181 | wire nid26; 182 | wire nid23; 183 | wire net_127; 184 | wire net_14; 185 | wire nid9; 186 | wire net_113; 187 | wire net_26; 188 | wire net_76; 189 | wire nid7; 190 | wire net_101; 191 | wire net_32; 192 | wire nic6; 193 | wire net_111; 194 | wire net_90; 195 | wire net_40; 196 | wire nod7; 197 | wire net_100; 198 | wire nod4; 199 | wire net_85; 200 | wire net_69; 201 | wire net_124; 202 | wire nid5; 203 | wire nid15; 204 | wire nid25; 205 | wire nid18; 206 | wire net_141; 207 | wire nid28; 208 | wire net_83; 209 | wire net_115; 210 | wire net_4; 211 | wire nid2; 212 | wire net_95; 213 | wire net_17; 214 | wire net_78; 215 | wire net_27; 216 | wire nid20; 217 | wire net_56; 218 | wire net_87; 219 | wire nod19; 220 | wire net_0; 221 | wire nod28; 222 | wire nid0; 223 | wire net_35; 224 | wire net_22; 225 | wire net_16; 226 | wire nic0; 227 | wire nod17; 228 | wire net_39; 229 | wire net_102; 230 | wire net_2; 231 | wire net_59; 232 | wire net_9; 233 | wire net_42; 234 | wire net_120; 235 | wire nic1; 236 | wire net_109; 237 | wire net_80; 238 | wire net_65; 239 | wire nod25; 240 | wire net_50; 241 | wire nod8; 242 | wire net_96; 243 | wire net_66; 244 | wire net_38; 245 | wire net_44; 246 | wire nod11; 247 | wire net_136; 248 | wire net_134; 249 | wire nod13; 250 | wire net_19; 251 | wire nid29; 252 | wire net_89; 253 | wire net_45; 254 | wire net_126; 255 | wire nod1; 256 | wire net_34; 257 | wire net_108; 258 | wire nod15; 259 | wire net_63; 260 | wire nid6; 261 | wire net_116; 262 | wire net_30; 263 | wire net_91; 264 | wire nod21; 265 | wire nod3; 266 | wire net_106; 267 | wire net_99; 268 | wire net_24; 269 | wire net_55; 270 | wire net_46; 271 | wire net_140; 272 | wire net_118; 273 | wire nr; 274 | wire net_104; 275 | wire nic4; 276 | wire nid10; 277 | wire nod16; 278 | wire net_72; 279 | wire net_122; 280 | wire net_25; 281 | wire net_70; 282 | wire net_7; 283 | wire nod9; 284 | wire nod22; 285 | wire nid17; 286 | wire nid27; 287 | wire nod6; 288 | wire net_5; 289 | wire net_52; 290 | wire net_128; 291 | wire net_138; 292 | wire nic5; 293 | wire nod12; 294 | wire net_13; 295 | wire nid30; 296 | wire net_94; 297 | wire nid12; 298 | wire nod18; 299 | wire net_11; 300 | wire net_18; 301 | wire net_123; 302 | wire net_131; 303 | wire net_114; 304 | wire net_29; 305 | wire net_68; 306 | wire nod27; 307 | wire net_142; 308 | wire net_77; 309 | wire net_20; 310 | wire net_31; 311 | wire net_36; 312 | wire net_49; 313 | wire net_15; 314 | wire net_57; 315 | wire nod31; 316 | wire net_41; 317 | wire net_71; 318 | wire nic7; 319 | wire nod5; 320 | wire nid11; 321 | wire net_3; 322 | wire net_84; 323 | wire nod29; 324 | wire net_112; 325 | wire net_92; 326 | wire net_1; 327 | wire net_103; 328 | wire nid1; 329 | wire net_139; 330 | wire nod10; 331 | wire net_43; 332 | wire net_10; 333 | wire nid31; 334 | wire net_28; 335 | wire net_21; 336 | wire net_51; 337 | wire net_79; 338 | wire nid22; 339 | wire net_143; 340 | wire net_97; 341 | wire nod24; 342 | wire nid16; 343 | wire net_88; 344 | wire net_60; 345 | wire nod14; 346 | wire nic2; 347 | wire net_81; 348 | wire net_58; 349 | wire nid14; 350 | wire nid8; 351 | wire net_82; 352 | wire net_67; 353 | wire net_64; 354 | wire net_37; 355 | wire net_110; 356 | wire net_121; 357 | wire net_73; 358 | wire nod0; 359 | wire nod20; 360 | wire net_33; 361 | wire net_48; 362 | wire net_86; 363 | wire net_75; 364 | wire net_8; 365 | wire nid24; 366 | wire nid4; 367 | wire net_133; 368 | wire nod2; 369 | wire nid19; 370 | wire net_125; 371 | 372 | // Start cells 373 | NAND2_X1 inst_145 ( .A1(net_139), .A2(net_135), .ZN(net_104) ); 374 | XNOR2_X1 inst_103 ( .B(net_121), .ZN(nod10), .A(nid10) ); 375 | NAND2_X1 inst_125 ( .ZN(net_2), .A2(nr), .A1(nic7) ); 376 | NAND2_X1 inst_138 ( .A1(net_120), .A2(net_100), .ZN(net_96) ); 377 | NAND2_X1 inst_159 ( .A2(net_133), .ZN(net_127), .A1(net_110) ); 378 | XOR2_X1 inst_15 ( .Z(net_29), .A(nid20), .B(nid16) ); 379 | NAND2_X1 inst_134 ( .A2(net_95), .A1(net_93), .ZN(net_77) ); 380 | XOR2_X1 inst_24 ( .Z(net_38), .A(nid23), .B(nid19) ); 381 | NOR2_X1 inst_114 ( .ZN(net_116), .A2(net_94), .A1(net_93) ); 382 | XOR2_X1 inst_6 ( .Z(net_15), .A(nid6), .B(nid2) ); 383 | NAND2_X1 inst_131 ( .A1(net_117), .ZN(net_90), .A2(net_72) ); 384 | XNOR2_X1 inst_76 ( .B(net_126), .ZN(nod7), .A(nid7) ); 385 | NAND2_X1 inst_160 ( .A2(net_135), .ZN(net_129), .A1(net_128) ); 386 | NAND2_X1 inst_150 ( .A2(net_116), .ZN(net_111), .A1(net_110) ); 387 | XNOR2_X1 inst_33 ( .ZN(net_40), .B(net_27), .A(net_17) ); 388 | INV_X1 inst_172 ( .A(net_110), .ZN(net_89) ); 389 | XNOR2_X1 inst_83 ( .B(net_106), .ZN(nod29), .A(nid29) ); 390 | XNOR2_X1 inst_47 ( .ZN(net_47), .B(net_38), .A(net_37) ); 391 | XOR2_X1 inst_19 ( .Z(net_33), .A(nid30), .B(nid26) ); 392 | NAND2_X1 inst_123 ( .ZN(net_0), .A2(nr), .A1(nic0) ); 393 | NAND3_X1 inst_121 ( .A2(net_120), .ZN(net_94), .A3(net_86), .A1(net_83) ); 394 | XOR2_X1 inst_2 ( .Z(net_11), .A(nid8), .B(nid12) ); 395 | XOR2_X1 inst_8 ( .Z(net_17), .A(nid7), .B(nid3) ); 396 | NAND3_X1 inst_118 ( .A1(net_89), .ZN(net_81), .A2(net_80), .A3(net_76) ); 397 | XNOR2_X1 inst_86 ( .B(net_113), .ZN(nod26), .A(nid26) ); 398 | NAND2_X1 inst_153 ( .ZN(net_118), .A1(net_117), .A2(net_116) ); 399 | XOR2_X1 inst_20 ( .Z(net_34), .A(nid21), .B(nid20) ); 400 | XNOR2_X1 inst_27 ( .ZN(net_18), .A(nid17), .B(nid16) ); 401 | XNOR2_X1 inst_38 ( .ZN(net_58), .B(net_39), .A(net_20) ); 402 | XNOR2_X1 inst_100 ( .B(net_109), .ZN(nod13), .A(nid13) ); 403 | XNOR2_X1 inst_52 ( .ZN(net_59), .A(net_58), .B(net_51) ); 404 | XNOR2_X1 inst_90 ( .B(net_130), .ZN(nod22), .A(nid22) ); 405 | NAND2_X1 inst_140 ( .A2(net_114), .A1(net_110), .ZN(net_98) ); 406 | XNOR2_X1 inst_40 ( .ZN(net_49), .A(net_34), .B(net_9) ); 407 | NAND2_X1 inst_162 ( .A2(net_138), .ZN(net_132), .A1(net_131) ); 408 | NAND2_X1 inst_167 ( .ZN(net_141), .A1(net_139), .A2(net_124) ); 409 | XNOR2_X1 inst_93 ( .B(net_142), .ZN(nod2), .A(nid2) ); 410 | XNOR2_X1 inst_81 ( .B(net_102), .ZN(nod30), .A(nid30) ); 411 | XNOR2_X1 inst_95 ( .B(net_107), .ZN(nod18), .A(nid18) ); 412 | XOR2_X1 inst_1 ( .Z(net_10), .A(nid31), .B(nid30) ); 413 | XNOR2_X1 inst_72 ( .B(net_139), .A(net_120), .ZN(net_74) ); 414 | NAND2_X1 inst_139 ( .A1(net_128), .A2(net_100), .ZN(net_97) ); 415 | NAND2_X1 inst_155 ( .A2(net_138), .ZN(net_121), .A1(net_120) ); 416 | XNOR2_X1 inst_59 ( .ZN(net_67), .A(net_59), .B(net_1) ); 417 | NAND2_X1 inst_135 ( .ZN(net_85), .A2(net_84), .A1(net_78) ); 418 | XNOR2_X1 inst_44 ( .ZN(net_45), .A(net_33), .B(net_23) ); 419 | XNOR2_X1 inst_55 ( .ZN(net_63), .A(net_56), .B(net_54) ); 420 | INV_X1 inst_174 ( .ZN(net_139), .A(net_83) ); 421 | NOR2_X1 inst_115 ( .ZN(net_133), .A1(net_95), .A2(net_92) ); 422 | XNOR2_X1 inst_37 ( .ZN(net_54), .A(net_31), .B(net_18) ); 423 | NAND2_X1 inst_148 ( .A1(net_122), .ZN(net_108), .A2(net_105) ); 424 | NAND2_X1 inst_164 ( .ZN(net_136), .A2(net_135), .A1(net_131) ); 425 | XOR2_X1 inst_5 ( .Z(net_14), .A(nid9), .B(nid8) ); 426 | NAND2_X1 inst_157 ( .A1(net_128), .ZN(net_125), .A2(net_124) ); 427 | XNOR2_X1 inst_84 ( .B(net_108), .ZN(nod28), .A(nid28) ); 428 | XNOR2_X1 inst_51 ( .ZN(net_57), .A(net_56), .B(net_48) ); 429 | NAND2_X1 inst_142 ( .A1(net_131), .ZN(net_101), .A2(net_100) ); 430 | XNOR2_X1 inst_80 ( .B(net_99), .ZN(nod31), .A(nid31) ); 431 | INV_X1 inst_173 ( .A(net_120), .ZN(net_82) ); 432 | XNOR2_X1 inst_105 ( .B(net_129), .ZN(nod0), .A(nid0) ); 433 | XNOR2_X1 inst_68 ( .ZN(net_120), .B(net_70), .A(net_44) ); 434 | XNOR2_X1 inst_78 ( .B(net_101), .ZN(nod5), .A(nid5) ); 435 | XNOR2_X1 inst_42 ( .ZN(net_60), .A(net_35), .B(net_24) ); 436 | INV_X1 inst_175 ( .A(net_122), .ZN(net_72) ); 437 | XNOR2_X1 inst_53 ( .ZN(net_61), .B(net_60), .A(net_52) ); 438 | NAND2_X1 inst_133 ( .A2(net_90), .A1(net_88), .ZN(net_76) ); 439 | XNOR2_X1 inst_26 ( .ZN(net_8), .A(nid11), .B(nid10) ); 440 | NAND2_X1 inst_151 ( .A2(net_116), .ZN(net_113), .A1(net_112) ); 441 | NOR2_X1 inst_112 ( .ZN(net_135), .A2(net_91), .A1(net_88) ); 442 | XNOR2_X1 inst_64 ( .ZN(net_80), .B(net_67), .A(net_45) ); 443 | OR3_X4 inst_107 ( .A2(net_122), .A1(net_117), .ZN(net_79), .A3(net_75) ); 444 | XNOR2_X1 inst_67 ( .ZN(net_117), .B(net_65), .A(net_43) ); 445 | NAND2_X1 inst_127 ( .ZN(net_4), .A2(nr), .A1(nic5) ); 446 | XNOR2_X1 inst_70 ( .ZN(net_122), .B(net_71), .A(net_41) ); 447 | NAND2_X1 inst_129 ( .ZN(net_6), .A2(nr), .A1(nic1) ); 448 | XNOR2_X1 inst_92 ( .B(net_137), .ZN(nod20), .A(nid20) ); 449 | XNOR2_X1 inst_29 ( .ZN(net_24), .A(nid7), .B(nid6) ); 450 | XOR2_X1 inst_17 ( .Z(net_31), .A(nid19), .B(nid18) ); 451 | XOR2_X1 inst_11 ( .Z(net_21), .A(nid9), .B(nid13) ); 452 | NAND2_X1 inst_146 ( .A1(net_117), .ZN(net_106), .A2(net_105) ); 453 | XOR2_X1 inst_14 ( .Z(net_28), .A(nid13), .B(nid12) ); 454 | NAND3_X1 inst_122 ( .A2(net_112), .ZN(net_91), .A1(net_89), .A3(net_85) ); 455 | XNOR2_X1 inst_31 ( .ZN(net_27), .A(nid15), .B(nid11) ); 456 | XOR2_X1 inst_25 ( .Z(net_39), .A(nid3), .B(nid2) ); 457 | NAND2_X1 inst_126 ( .ZN(net_3), .A2(nr), .A1(nic3) ); 458 | NAND2_X1 inst_158 ( .A1(net_139), .ZN(net_126), .A2(net_100) ); 459 | NAND2_X1 inst_141 ( .A1(net_110), .A2(net_105), .ZN(net_99) ); 460 | XNOR2_X1 inst_62 ( .ZN(net_70), .A(net_63), .B(net_7) ); 461 | NOR3_X1 inst_110 ( .ZN(net_100), .A1(net_89), .A2(net_88), .A3(net_87) ); 462 | XNOR2_X1 inst_74 ( .B(net_132), .ZN(nod9), .A(nid9) ); 463 | XNOR2_X1 inst_57 ( .ZN(net_65), .A(net_53), .B(net_4) ); 464 | XNOR2_X1 inst_35 ( .ZN(net_42), .A(net_30), .B(net_11) ); 465 | XNOR2_X1 inst_99 ( .B(net_103), .ZN(nod14), .A(nid14) ); 466 | XNOR2_X1 inst_48 ( .ZN(net_50), .A(net_49), .B(net_48) ); 467 | XNOR2_X1 inst_69 ( .ZN(net_83), .B(net_64), .A(net_40) ); 468 | XNOR2_X1 inst_46 ( .ZN(net_51), .A(net_14), .B(net_8) ); 469 | XNOR2_X1 inst_82 ( .B(net_104), .ZN(nod3), .A(nid3) ); 470 | NAND2_X1 inst_136 ( .ZN(net_86), .A2(net_81), .A1(net_79) ); 471 | XNOR2_X1 inst_30 ( .ZN(net_26), .A(nid29), .B(nid28) ); 472 | XNOR2_X1 inst_102 ( .B(net_140), .ZN(nod11), .A(nid11) ); 473 | OR2_X4 inst_108 ( .A2(net_117), .ZN(net_88), .A1(net_72) ); 474 | NAND2_X1 inst_165 ( .ZN(net_137), .A2(net_133), .A1(net_122) ); 475 | XNOR2_X1 inst_32 ( .ZN(net_52), .B(net_28), .A(net_12) ); 476 | XOR2_X1 inst_22 ( .Z(net_36), .A(nid5), .B(nid1) ); 477 | NAND2_X1 inst_144 ( .A2(net_124), .A1(net_120), .ZN(net_103) ); 478 | XNOR2_X1 inst_34 ( .ZN(net_41), .B(net_29), .A(net_19) ); 479 | XOR2_X1 inst_12 ( .Z(net_22), .A(nid29), .B(nid25) ); 480 | XNOR2_X1 inst_56 ( .ZN(net_64), .A(net_50), .B(net_3) ); 481 | XNOR2_X1 inst_71 ( .ZN(net_131), .B(net_66), .A(net_46) ); 482 | XOR2_X1 inst_21 ( .Z(net_35), .A(nid5), .B(nid4) ); 483 | XNOR2_X1 inst_104 ( .B(net_136), .ZN(nod1), .A(nid1) ); 484 | XNOR2_X1 inst_60 ( .ZN(net_68), .A(net_61), .B(net_2) ); 485 | NAND2_X1 inst_169 ( .ZN(net_143), .A2(net_138), .A1(net_128) ); 486 | NAND2_X1 inst_168 ( .ZN(net_142), .A2(net_135), .A1(net_120) ); 487 | XNOR2_X1 inst_97 ( .B(net_119), .ZN(nod16), .A(nid16) ); 488 | NAND2_X1 inst_161 ( .A2(net_133), .ZN(net_130), .A1(net_112) ); 489 | NAND2_X1 inst_124 ( .ZN(net_1), .A2(nr), .A1(nic6) ); 490 | XOR2_X1 inst_18 ( .Z(net_32), .A(nid25), .B(nid24) ); 491 | XOR2_X1 inst_16 ( .Z(net_30), .A(nid4), .B(nid0) ); 492 | XNOR2_X1 inst_88 ( .B(net_123), .ZN(nod24), .A(nid24) ); 493 | XOR2_X1 inst_3 ( .Z(net_12), .A(nid15), .B(nid14) ); 494 | NAND2_X1 inst_156 ( .ZN(net_123), .A1(net_122), .A2(net_116) ); 495 | XOR2_X1 inst_9 ( .Z(net_19), .A(nid28), .B(nid24) ); 496 | NOR2_X1 inst_113 ( .ZN(net_105), .A1(net_93), .A2(net_92) ); 497 | INV_X1 inst_170 ( .ZN(net_112), .A(net_80) ); 498 | XNOR2_X1 inst_50 ( .ZN(net_55), .B(net_54), .A(net_49) ); 499 | NAND2_X1 inst_137 ( .ZN(net_87), .A2(net_85), .A1(net_80) ); 500 | XNOR2_X1 inst_41 ( .ZN(net_56), .A(net_32), .B(net_25) ); 501 | NAND2_X1 inst_130 ( .ZN(net_7), .A2(nr), .A1(nic2) ); 502 | XNOR2_X1 inst_91 ( .B(net_134), .ZN(nod21), .A(nid21) ); 503 | NAND2_X1 inst_132 ( .A1(net_131), .ZN(net_93), .A2(net_73) ); 504 | NAND2_X1 inst_143 ( .A1(net_112), .A2(net_105), .ZN(net_102) ); 505 | NAND2_X1 inst_152 ( .A1(net_117), .ZN(net_115), .A2(net_114) ); 506 | XNOR2_X1 inst_58 ( .ZN(net_66), .A(net_57), .B(net_6) ); 507 | XNOR2_X1 inst_36 ( .ZN(net_48), .B(net_26), .A(net_10) ); 508 | NAND2_X1 inst_147 ( .A2(net_114), .A1(net_112), .ZN(net_107) ); 509 | XNOR2_X1 inst_87 ( .B(net_118), .ZN(nod25), .A(nid25) ); 510 | XNOR2_X1 inst_61 ( .ZN(net_69), .A(net_55), .B(net_0) ); 511 | XNOR2_X1 inst_45 ( .ZN(net_46), .A(net_36), .B(net_21) ); 512 | XNOR2_X1 inst_96 ( .B(net_115), .ZN(nod17), .A(nid17) ); 513 | XNOR2_X1 inst_101 ( .B(net_125), .ZN(nod12), .A(nid12) ); 514 | XOR2_X1 inst_0 ( .Z(net_9), .A(nid23), .B(nid22) ); 515 | XOR2_X1 inst_10 ( .Z(net_20), .A(nid1), .B(nid0) ); 516 | XOR2_X1 inst_4 ( .Z(net_13), .A(nid21), .B(nid17) ); 517 | XNOR2_X1 inst_65 ( .ZN(net_128), .B(net_69), .A(net_42) ); 518 | XNOR2_X1 inst_89 ( .B(net_127), .ZN(nod23), .A(nid23) ); 519 | XNOR2_X1 inst_28 ( .ZN(net_23), .A(nid22), .B(nid18) ); 520 | NOR3_X1 inst_111 ( .ZN(net_124), .A2(net_90), .A1(net_89), .A3(net_87) ); 521 | XNOR2_X1 inst_66 ( .ZN(net_110), .B(net_68), .A(net_47) ); 522 | NOR2_X1 inst_117 ( .ZN(net_138), .A2(net_91), .A1(net_90) ); 523 | XNOR2_X1 inst_98 ( .B(net_141), .ZN(nod15), .A(nid15) ); 524 | XNOR2_X1 inst_63 ( .ZN(net_71), .A(net_62), .B(net_5) ); 525 | XOR2_X1 inst_7 ( .Z(net_16), .A(nid14), .B(nid10) ); 526 | XNOR2_X1 inst_49 ( .ZN(net_53), .A(net_52), .B(net_51) ); 527 | NAND3_X1 inst_120 ( .A1(net_139), .ZN(net_92), .A3(net_86), .A2(net_82) ); 528 | NAND2_X1 inst_154 ( .A1(net_122), .ZN(net_119), .A2(net_114) ); 529 | XOR2_X1 inst_13 ( .Z(net_25), .A(nid27), .B(nid26) ); 530 | NAND3_X1 inst_119 ( .ZN(net_84), .A1(net_83), .A2(net_82), .A3(net_77) ); 531 | XNOR2_X1 inst_75 ( .B(net_143), .ZN(nod8), .A(nid8) ); 532 | NAND2_X1 inst_166 ( .ZN(net_140), .A1(net_139), .A2(net_138) ); 533 | NOR2_X1 inst_116 ( .ZN(net_114), .A1(net_95), .A2(net_94) ); 534 | NAND2_X1 inst_163 ( .ZN(net_134), .A2(net_133), .A1(net_117) ); 535 | XNOR2_X1 inst_85 ( .B(net_111), .ZN(nod27), .A(nid27) ); 536 | XNOR2_X1 inst_54 ( .ZN(net_62), .B(net_60), .A(net_58) ); 537 | XNOR2_X1 inst_79 ( .B(net_97), .ZN(nod4), .A(nid4) ); 538 | OR2_X4 inst_109 ( .A2(net_131), .ZN(net_95), .A1(net_73) ); 539 | OR3_X4 inst_106 ( .A1(net_131), .A2(net_128), .ZN(net_78), .A3(net_74) ); 540 | NAND2_X1 inst_149 ( .A1(net_131), .A2(net_124), .ZN(net_109) ); 541 | XNOR2_X1 inst_43 ( .ZN(net_44), .B(net_16), .A(net_15) ); 542 | XNOR2_X1 inst_39 ( .ZN(net_43), .A(net_22), .B(net_13) ); 543 | NAND2_X1 inst_128 ( .ZN(net_5), .A2(nr), .A1(nic4) ); 544 | XNOR2_X1 inst_73 ( .B(net_112), .A(net_110), .ZN(net_75) ); 545 | XOR2_X1 inst_23 ( .Z(net_37), .A(nid31), .B(nid27) ); 546 | INV_X1 inst_171 ( .A(net_128), .ZN(net_73) ); 547 | XNOR2_X1 inst_77 ( .B(net_96), .ZN(nod6), .A(nid6) ); 548 | XNOR2_X1 inst_94 ( .B(net_98), .ZN(nod19), .A(nid19) ); 549 | 550 | endmodule 551 | -------------------------------------------------------------------------------- /benchmark/c880.v: -------------------------------------------------------------------------------- 1 | module c880 ( 2 | n201gat, 3 | n189gat, 4 | n17gat, 5 | n72gat, 6 | n152gat, 7 | n255gat, 8 | n159gat, 9 | n85gat, 10 | n267gat, 11 | n87gat, 12 | n116gat, 13 | n74gat, 14 | n55gat, 15 | n90gat, 16 | n210gat, 17 | n96gat, 18 | n228gat, 19 | n260gat, 20 | n143gat, 21 | n80gat, 22 | n207gat, 23 | n153gat, 24 | n268gat, 25 | n171gat, 26 | n1gat, 27 | n135gat, 28 | n111gat, 29 | n237gat, 30 | n183gat, 31 | n130gat, 32 | n29gat, 33 | n261gat, 34 | n101gat, 35 | n59gat, 36 | n138gat, 37 | n149gat, 38 | n195gat, 39 | n86gat, 40 | n177gat, 41 | n219gat, 42 | n42gat, 43 | n121gat, 44 | n146gat, 45 | n91gat, 46 | n26gat, 47 | n156gat, 48 | n68gat, 49 | n13gat, 50 | n246gat, 51 | n8gat, 52 | n75gat, 53 | n73gat, 54 | n36gat, 55 | n88gat, 56 | n126gat, 57 | n106gat, 58 | n165gat, 59 | n259gat, 60 | n89gat, 61 | n51gat, 62 | n420gat, 63 | n389gat, 64 | n879gat, 65 | n865gat, 66 | n850gat, 67 | n446gat, 68 | n767gat, 69 | n390gat, 70 | n874gat, 71 | n864gat, 72 | n768gat, 73 | n421gat, 74 | n863gat, 75 | n419gat, 76 | n388gat, 77 | n449gat, 78 | n450gat, 79 | n880gat, 80 | n423gat, 81 | n866gat, 82 | n447gat, 83 | n391gat, 84 | n448gat, 85 | n878gat, 86 | n418gat, 87 | n422gat); 88 | 89 | // Start PIs 90 | input n201gat; 91 | input n189gat; 92 | input n17gat; 93 | input n72gat; 94 | input n152gat; 95 | input n255gat; 96 | input n159gat; 97 | input n85gat; 98 | input n267gat; 99 | input n87gat; 100 | input n116gat; 101 | input n74gat; 102 | input n55gat; 103 | input n90gat; 104 | input n210gat; 105 | input n96gat; 106 | input n228gat; 107 | input n260gat; 108 | input n143gat; 109 | input n80gat; 110 | input n207gat; 111 | input n153gat; 112 | input n268gat; 113 | input n171gat; 114 | input n1gat; 115 | input n135gat; 116 | input n111gat; 117 | input n237gat; 118 | input n183gat; 119 | input n130gat; 120 | input n29gat; 121 | input n261gat; 122 | input n101gat; 123 | input n59gat; 124 | input n138gat; 125 | input n149gat; 126 | input n195gat; 127 | input n86gat; 128 | input n177gat; 129 | input n219gat; 130 | input n42gat; 131 | input n121gat; 132 | input n146gat; 133 | input n91gat; 134 | input n26gat; 135 | input n156gat; 136 | input n68gat; 137 | input n13gat; 138 | input n246gat; 139 | input n8gat; 140 | input n75gat; 141 | input n73gat; 142 | input n36gat; 143 | input n88gat; 144 | input n126gat; 145 | input n106gat; 146 | input n165gat; 147 | input n259gat; 148 | input n89gat; 149 | input n51gat; 150 | 151 | // Start POs 152 | output n420gat; 153 | output n389gat; 154 | output n879gat; 155 | output n865gat; 156 | output n850gat; 157 | output n446gat; 158 | output n767gat; 159 | output n390gat; 160 | output n874gat; 161 | output n864gat; 162 | output n768gat; 163 | output n421gat; 164 | output n863gat; 165 | output n419gat; 166 | output n388gat; 167 | output n449gat; 168 | output n450gat; 169 | output n880gat; 170 | output n423gat; 171 | output n866gat; 172 | output n447gat; 173 | output n391gat; 174 | output n448gat; 175 | output n878gat; 176 | output n418gat; 177 | output n422gat; 178 | 179 | // Start wires 180 | wire net_47; 181 | wire net_176; 182 | wire net_137; 183 | wire n159gat; 184 | wire net_132; 185 | wire net_54; 186 | wire n768gat; 187 | wire net_105; 188 | wire n419gat; 189 | wire net_129; 190 | wire net_119; 191 | wire net_98; 192 | wire net_12; 193 | wire net_151; 194 | wire net_53; 195 | wire net_93; 196 | wire net_168; 197 | wire net_127; 198 | wire net_76; 199 | wire net_101; 200 | wire net_187; 201 | wire net_111; 202 | wire net_90; 203 | wire n26gat; 204 | wire net_100; 205 | wire net_85; 206 | wire net_124; 207 | wire net_160; 208 | wire net_115; 209 | wire n878gat; 210 | wire net_4; 211 | wire net_17; 212 | wire n51gat; 213 | wire n865gat; 214 | wire n17gat; 215 | wire net_164; 216 | wire net_87; 217 | wire net_0; 218 | wire net_35; 219 | wire n87gat; 220 | wire net_16; 221 | wire n74gat; 222 | wire net_193; 223 | wire net_157; 224 | wire n260gat; 225 | wire net_42; 226 | wire net_120; 227 | wire net_109; 228 | wire net_80; 229 | wire net_65; 230 | wire net_50; 231 | wire n183gat; 232 | wire n130gat; 233 | wire net_96; 234 | wire net_66; 235 | wire net_38; 236 | wire n446gat; 237 | wire net_167; 238 | wire net_136; 239 | wire net_19; 240 | wire n177gat; 241 | wire net_126; 242 | wire n91gat; 243 | wire net_34; 244 | wire net_108; 245 | wire net_183; 246 | wire n88gat; 247 | wire net_150; 248 | wire net_63; 249 | wire n879gat; 250 | wire n255gat; 251 | wire net_30; 252 | wire net_189; 253 | wire net_99; 254 | wire net_24; 255 | wire net_186; 256 | wire net_46; 257 | wire net_118; 258 | wire n55gat; 259 | wire net_146; 260 | wire n96gat; 261 | wire net_122; 262 | wire n143gat; 263 | wire net_7; 264 | wire n111gat; 265 | wire net_172; 266 | wire net_52; 267 | wire net_165; 268 | wire net_13; 269 | wire net_94; 270 | wire net_18; 271 | wire net_131; 272 | wire net_114; 273 | wire n126gat; 274 | wire n866gat; 275 | wire net_29; 276 | wire net_149; 277 | wire net_142; 278 | wire net_31; 279 | wire net_36; 280 | wire net_158; 281 | wire n189gat; 282 | wire net_41; 283 | wire net_3; 284 | wire net_154; 285 | wire n388gat; 286 | wire net_28; 287 | wire n153gat; 288 | wire n391gat; 289 | wire n448gat; 290 | wire net_97; 291 | wire net_182; 292 | wire net_192; 293 | wire net_60; 294 | wire n101gat; 295 | wire n59gat; 296 | wire n149gat; 297 | wire net_58; 298 | wire n863gat; 299 | wire net_82; 300 | wire net_64; 301 | wire net_121; 302 | wire net_73; 303 | wire net_177; 304 | wire net_86; 305 | wire net_75; 306 | wire n447gat; 307 | wire n106gat; 308 | wire net_125; 309 | wire net_107; 310 | wire net_166; 311 | wire net_179; 312 | wire n152gat; 313 | wire net_159; 314 | wire n767gat; 315 | wire net_61; 316 | wire net_62; 317 | wire n116gat; 318 | wire net_6; 319 | wire net_23; 320 | wire n90gat; 321 | wire net_117; 322 | wire net_74; 323 | wire n80gat; 324 | wire net_135; 325 | wire net_130; 326 | wire n420gat; 327 | wire net_147; 328 | wire n261gat; 329 | wire net_14; 330 | wire net_26; 331 | wire net_113; 332 | wire n195gat; 333 | wire net_32; 334 | wire n219gat; 335 | wire net_40; 336 | wire n246gat; 337 | wire n13gat; 338 | wire n8gat; 339 | wire net_69; 340 | wire net_161; 341 | wire net_141; 342 | wire net_83; 343 | wire net_95; 344 | wire net_173; 345 | wire n389gat; 346 | wire n850gat; 347 | wire net_78; 348 | wire net_27; 349 | wire n72gat; 350 | wire net_56; 351 | wire n874gat; 352 | wire net_155; 353 | wire net_191; 354 | wire net_22; 355 | wire net_181; 356 | wire net_39; 357 | wire n228gat; 358 | wire net_2; 359 | wire net_102; 360 | wire net_144; 361 | wire net_9; 362 | wire net_59; 363 | wire n207gat; 364 | wire n268gat; 365 | wire net_162; 366 | wire net_44; 367 | wire net_134; 368 | wire n421gat; 369 | wire net_45; 370 | wire net_89; 371 | wire n146gat; 372 | wire n156gat; 373 | wire net_185; 374 | wire n75gat; 375 | wire n450gat; 376 | wire net_178; 377 | wire n165gat; 378 | wire n418gat; 379 | wire n89gat; 380 | wire net_152; 381 | wire net_116; 382 | wire n390gat; 383 | wire net_175; 384 | wire net_91; 385 | wire net_55; 386 | wire net_106; 387 | wire net_140; 388 | wire n449gat; 389 | wire n210gat; 390 | wire net_104; 391 | wire net_148; 392 | wire n880gat; 393 | wire net_72; 394 | wire net_25; 395 | wire net_70; 396 | wire n171gat; 397 | wire net_194; 398 | wire net_5; 399 | wire net_128; 400 | wire net_138; 401 | wire net_184; 402 | wire net_11; 403 | wire n68gat; 404 | wire n73gat; 405 | wire n36gat; 406 | wire net_123; 407 | wire net_170; 408 | wire net_68; 409 | wire net_77; 410 | wire net_20; 411 | wire net_49; 412 | wire n201gat; 413 | wire net_15; 414 | wire net_57; 415 | wire n85gat; 416 | wire net_71; 417 | wire n267gat; 418 | wire net_153; 419 | wire net_156; 420 | wire net_84; 421 | wire net_174; 422 | wire net_1; 423 | wire net_92; 424 | wire net_112; 425 | wire net_103; 426 | wire net_139; 427 | wire n423gat; 428 | wire net_43; 429 | wire net_10; 430 | wire net_180; 431 | wire net_21; 432 | wire net_169; 433 | wire net_51; 434 | wire net_171; 435 | wire net_79; 436 | wire n135gat; 437 | wire n1gat; 438 | wire n422gat; 439 | wire n237gat; 440 | wire net_143; 441 | wire net_190; 442 | wire n29gat; 443 | wire net_88; 444 | wire net_145; 445 | wire n138gat; 446 | wire n864gat; 447 | wire net_81; 448 | wire net_163; 449 | wire n86gat; 450 | wire net_67; 451 | wire n121gat; 452 | wire n42gat; 453 | wire net_37; 454 | wire net_188; 455 | wire net_110; 456 | wire net_33; 457 | wire net_48; 458 | wire net_8; 459 | wire net_133; 460 | wire n259gat; 461 | 462 | // Start cells 463 | NAND2_X1 inst_145 ( .ZN(net_126), .A2(net_97), .A1(n165gat) ); 464 | NAND2_X1 inst_103 ( .ZN(net_36), .A2(net_31), .A1(n42gat) ); 465 | NAND2_X1 inst_125 ( .ZN(net_73), .A2(net_72), .A1(n153gat) ); 466 | AND2_X4 inst_207 ( .ZN(net_28), .A2(n75gat), .A1(n29gat) ); 467 | NAND2_X1 inst_138 ( .ZN(net_122), .A2(net_89), .A1(n195gat) ); 468 | NAND2_X1 inst_159 ( .ZN(net_147), .A2(net_123), .A1(net_116) ); 469 | AND2_X2 inst_218 ( .A2(net_30), .ZN(n450gat), .A1(n89gat) ); 470 | XNOR2_X1 inst_15 ( .ZN(net_48), .A(net_39), .B(n207gat) ); 471 | AND4_X1 inst_197 ( .ZN(net_178), .A4(net_172), .A1(net_144), .A2(net_118), .A3(net_7) ); 472 | NAND2_X1 inst_134 ( .ZN(net_83), .A2(net_81), .A1(n177gat) ); 473 | NAND2_X1 inst_179 ( .ZN(net_191), .A2(net_188), .A1(n219gat) ); 474 | XNOR2_X1 inst_24 ( .ZN(net_182), .A(net_180), .B(net_156) ); 475 | NAND2_X1 inst_114 ( .ZN(net_85), .A2(net_55), .A1(n55gat) ); 476 | XNOR2_X1 inst_6 ( .ZN(net_25), .B(n126gat), .A(n121gat) ); 477 | AND4_X1 inst_194 ( .ZN(net_167), .A4(net_162), .A1(net_148), .A2(net_142), .A3(net_1) ); 478 | NAND2_X1 inst_131 ( .A2(net_81), .ZN(net_79), .A1(n171gat) ); 479 | NAND3_X1 inst_76 ( .A1(net_177), .A3(net_101), .A2(net_78), .ZN(n863gat) ); 480 | AND2_X4 inst_214 ( .ZN(net_151), .A2(net_123), .A1(n261gat) ); 481 | NAND2_X1 inst_180 ( .ZN(net_192), .A2(net_189), .A1(n219gat) ); 482 | NAND2_X1 inst_160 ( .A1(net_141), .ZN(net_133), .A2(net_132) ); 483 | NAND2_X1 inst_150 ( .ZN(net_103), .A2(net_102), .A1(n246gat) ); 484 | OR2_X4 inst_33 ( .A2(net_122), .A1(net_117), .ZN(net_107) ); 485 | NAND2_X1 inst_172 ( .ZN(net_176), .A2(net_175), .A1(net_138) ); 486 | NAND2_X1 inst_83 ( .ZN(net_2), .A2(n260gat), .A1(n255gat) ); 487 | OR2_X4 inst_47 ( .ZN(net_159), .A2(net_151), .A1(net_141) ); 488 | XNOR2_X1 inst_19 ( .ZN(net_158), .A(net_147), .B(n261gat) ); 489 | NAND2_X1 inst_123 ( .A2(net_72), .ZN(net_70), .A1(n149gat) ); 490 | NAND2_X1 inst_121 ( .ZN(net_68), .A2(net_67), .A1(n106gat) ); 491 | XNOR2_X1 inst_2 ( .ZN(net_20), .B(n106gat), .A(n101gat) ); 492 | XNOR2_X1 inst_8 ( .ZN(net_34), .A(net_33), .B(n42gat) ); 493 | NAND2_X1 inst_118 ( .A2(net_67), .ZN(net_64), .A1(n126gat) ); 494 | NAND2_X1 inst_86 ( .ZN(net_4), .A1(n210gat), .A2(n106gat) ); 495 | NAND2_X1 inst_153 ( .ZN(net_149), .A1(net_122), .A2(net_121) ); 496 | XNOR2_X1 inst_20 ( .ZN(net_161), .A(net_159), .B(net_149) ); 497 | OR3_X4 inst_27 ( .ZN(net_84), .A3(net_54), .A2(net_33), .A1(n268gat) ); 498 | OR2_X4 inst_38 ( .A2(net_128), .ZN(net_118), .A1(net_117) ); 499 | NAND2_X1 inst_100 ( .A2(net_27), .ZN(n421gat), .A1(n80gat) ); 500 | NOR2_X1 inst_52 ( .ZN(net_42), .A2(net_32), .A1(net_17) ); 501 | NAND2_X1 inst_90 ( .ZN(net_7), .A1(n210gat), .A2(n111gat) ); 502 | NAND2_X1 inst_140 ( .A2(net_96), .ZN(net_91), .A1(n246gat) ); 503 | AND2_X4 inst_209 ( .A2(net_18), .ZN(n447gat), .A1(n51gat) ); 504 | AND2_X4 inst_211 ( .ZN(net_52), .A2(net_45), .A1(n59gat) ); 505 | OR2_X4 inst_40 ( .ZN(net_131), .A2(net_130), .A1(net_117) ); 506 | NAND2_X1 inst_162 ( .ZN(net_142), .A2(net_141), .A1(n237gat) ); 507 | NAND2_X1 inst_167 ( .ZN(net_164), .A2(net_161), .A1(n219gat) ); 508 | NAND2_X1 inst_93 ( .ZN(net_10), .A2(n259gat), .A1(n255gat) ); 509 | NAND2_X1 inst_81 ( .ZN(net_0), .A2(n96gat), .A1(n210gat) ); 510 | NAND2_X1 inst_95 ( .ZN(net_12), .A1(n17gat), .A2(n138gat) ); 511 | XOR2_X1 inst_1 ( .Z(net_23), .B(n201gat), .A(n195gat) ); 512 | NAND3_X1 inst_72 ( .ZN(net_89), .A2(net_85), .A1(net_70), .A3(net_61) ); 513 | NAND2_X1 inst_139 ( .ZN(net_128), .A2(net_90), .A1(n189gat) ); 514 | NAND2_X1 inst_155 ( .ZN(net_153), .A1(net_126), .A2(net_105) ); 515 | NOR2_X1 inst_59 ( .ZN(net_132), .A1(net_119), .A2(net_98) ); 516 | NAND2_X1 inst_135 ( .ZN(net_111), .A2(net_86), .A1(n159gat) ); 517 | AND4_X1 inst_196 ( .ZN(net_177), .A4(net_171), .A2(net_146), .A1(net_131), .A3(net_4) ); 518 | OR2_X4 inst_44 ( .A1(net_154), .ZN(net_146), .A2(net_145) ); 519 | NOR2_X1 inst_55 ( .ZN(net_119), .A2(net_90), .A1(n189gat) ); 520 | NAND2_X1 inst_174 ( .ZN(net_181), .A2(net_180), .A1(net_124) ); 521 | NAND2_X1 inst_115 ( .A2(net_67), .ZN(net_61), .A1(n121gat) ); 522 | OR2_X4 inst_37 ( .A1(net_125), .ZN(net_115), .A2(net_114) ); 523 | AND2_X4 inst_210 ( .ZN(net_50), .A1(net_15), .A2(n447gat) ); 524 | NAND2_X1 inst_148 ( .ZN(net_101), .A2(net_100), .A1(n246gat) ); 525 | NAND2_X1 inst_164 ( .ZN(net_160), .A2(net_159), .A1(net_121) ); 526 | INV_X1 inst_191 ( .ZN(net_139), .A(net_106) ); 527 | XNOR2_X1 inst_5 ( .ZN(net_24), .B(n189gat), .A(n183gat) ); 528 | NAND2_X1 inst_157 ( .ZN(net_143), .A1(net_128), .A2(net_99) ); 529 | NAND2_X1 inst_84 ( .ZN(net_16), .A2(n8gat), .A1(n1gat) ); 530 | NOR2_X1 inst_51 ( .A2(net_32), .A1(net_16), .ZN(n418gat) ); 531 | NAND2_X1 inst_142 ( .A2(net_97), .ZN(net_93), .A1(n246gat) ); 532 | NAND3_X1 inst_80 ( .A1(net_194), .A3(net_93), .A2(net_80), .ZN(n879gat) ); 533 | NAND2_X1 inst_173 ( .ZN(net_179), .A2(net_174), .A1(n219gat) ); 534 | NAND2_X1 inst_105 ( .A2(net_42), .A1(net_36), .ZN(n419gat) ); 535 | AND2_X4 inst_213 ( .ZN(net_53), .A2(net_52), .A1(n72gat) ); 536 | NAND4_X1 inst_68 ( .A2(net_170), .A4(net_87), .A1(net_75), .A3(net_2), .ZN(n865gat) ); 537 | AND2_X2 inst_216 ( .ZN(n391gat), .A2(n86gat), .A1(n85gat) ); 538 | NAND3_X1 inst_78 ( .A1(net_190), .A3(net_91), .A2(net_79), .ZN(n880gat) ); 539 | OR2_X4 inst_42 ( .A1(net_154), .ZN(net_137), .A2(net_136) ); 540 | NAND2_X1 inst_175 ( .ZN(net_183), .A2(net_181), .A1(net_125) ); 541 | NOR2_X1 inst_53 ( .ZN(net_55), .A2(net_54), .A1(n268gat) ); 542 | AND2_X4 inst_205 ( .ZN(net_27), .A1(n59gat), .A2(n36gat) ); 543 | NAND2_X1 inst_177 ( .ZN(net_187), .A2(net_186), .A1(net_110) ); 544 | INV_X1 inst_183 ( .ZN(net_117), .A(n237gat) ); 545 | NAND2_X1 inst_133 ( .ZN(net_82), .A2(net_81), .A1(n159gat) ); 546 | XNOR2_X1 inst_26 ( .ZN(net_189), .A(net_183), .B(net_153) ); 547 | NAND2_X1 inst_151 ( .ZN(net_134), .A1(net_111), .A2(net_110) ); 548 | NAND2_X1 inst_112 ( .ZN(net_59), .A2(net_58), .A1(n153gat) ); 549 | NAND4_X1 inst_64 ( .ZN(net_95), .A2(net_84), .A4(net_68), .A1(net_59), .A3(net_6) ); 550 | NAND2_X1 inst_107 ( .ZN(net_51), .A2(net_50), .A1(n17gat) ); 551 | NAND4_X1 inst_67 ( .A2(net_167), .A4(net_103), .A1(net_77), .A3(net_9), .ZN(n850gat) ); 552 | INV_X1 inst_181 ( .ZN(net_154), .A(n228gat) ); 553 | NAND2_X1 inst_127 ( .A2(net_81), .ZN(net_75), .A1(n195gat) ); 554 | NAND4_X1 inst_70 ( .A2(net_178), .A4(net_88), .A1(net_76), .A3(net_10), .ZN(n864gat) ); 555 | INV_X1 inst_186 ( .A(net_36), .ZN(n390gat) ); 556 | NAND2_X1 inst_129 ( .A2(net_81), .ZN(net_77), .A1(n201gat) ); 557 | NAND2_X1 inst_92 ( .ZN(net_9), .A2(n267gat), .A1(n255gat) ); 558 | OR2_X4 inst_29 ( .ZN(net_110), .A2(net_86), .A1(n159gat) ); 559 | INV_X1 inst_189 ( .ZN(net_124), .A(net_104) ); 560 | XNOR2_X1 inst_17 ( .B(net_48), .A(net_47), .ZN(n768gat) ); 561 | XNOR2_X1 inst_11 ( .ZN(net_40), .B(net_26), .A(net_25) ); 562 | NAND2_X1 inst_146 ( .ZN(net_106), .A2(net_95), .A1(n177gat) ); 563 | INV_X1 inst_188 ( .A(net_119), .ZN(net_99) ); 564 | XNOR2_X1 inst_14 ( .ZN(net_47), .A(net_41), .B(n130gat) ); 565 | AND3_X4 inst_202 ( .ZN(net_45), .A3(net_37), .A1(n55gat), .A2(n13gat) ); 566 | AND2_X4 inst_206 ( .ZN(net_29), .A2(n75gat), .A1(n59gat) ); 567 | INV_X1 inst_187 ( .ZN(net_121), .A(net_98) ); 568 | NAND2_X1 inst_122 ( .ZN(net_69), .A2(net_67), .A1(n91gat) ); 569 | OR2_X4 inst_31 ( .ZN(net_129), .A2(net_100), .A1(n183gat) ); 570 | XNOR2_X1 inst_25 ( .ZN(net_188), .A(net_186), .B(net_134) ); 571 | NAND2_X1 inst_126 ( .ZN(net_74), .A2(net_72), .A1(n143gat) ); 572 | NAND2_X1 inst_158 ( .ZN(net_145), .A1(net_130), .A2(net_129) ); 573 | NAND2_X1 inst_141 ( .ZN(net_92), .A2(net_86), .A1(n246gat) ); 574 | NAND4_X1 inst_62 ( .ZN(net_96), .A2(net_84), .A4(net_65), .A1(net_56), .A3(net_12) ); 575 | AND4_X1 inst_200 ( .ZN(net_193), .A4(net_191), .A2(net_135), .A1(net_112), .A3(net_3) ); 576 | NAND2_X1 inst_110 ( .A2(net_58), .ZN(net_56), .A1(n149gat) ); 577 | NAND3_X1 inst_74 ( .ZN(net_102), .A3(net_85), .A2(net_73), .A1(net_64) ); 578 | NOR2_X1 inst_57 ( .ZN(net_114), .A2(net_97), .A1(n165gat) ); 579 | OR2_X4 inst_35 ( .A2(net_126), .A1(net_117), .ZN(net_109) ); 580 | NAND2_X1 inst_99 ( .ZN(net_15), .A1(n59gat), .A2(n156gat) ); 581 | OR2_X4 inst_48 ( .ZN(net_155), .A1(net_154), .A2(net_153) ); 582 | NAND4_X1 inst_69 ( .ZN(net_186), .A4(net_176), .A1(net_140), .A2(net_126), .A3(net_115) ); 583 | OR2_X4 inst_46 ( .A1(net_154), .ZN(net_150), .A2(net_149) ); 584 | NAND2_X1 inst_82 ( .ZN(net_1), .A1(n210gat), .A2(n121gat) ); 585 | NAND2_X1 inst_136 ( .A2(net_89), .ZN(net_87), .A1(n246gat) ); 586 | OR2_X4 inst_30 ( .ZN(net_113), .A2(net_95), .A1(n177gat) ); 587 | NAND2_X1 inst_102 ( .A2(net_27), .ZN(n422gat), .A1(n42gat) ); 588 | NAND2_X1 inst_108 ( .ZN(net_67), .A2(net_44), .A1(net_43) ); 589 | NAND2_X1 inst_165 ( .ZN(net_162), .A2(net_158), .A1(n219gat) ); 590 | OR2_X4 inst_32 ( .ZN(net_123), .A2(net_102), .A1(n201gat) ); 591 | XNOR2_X1 inst_22 ( .ZN(net_169), .A(net_163), .B(net_143) ); 592 | NAND2_X1 inst_144 ( .ZN(net_125), .A2(net_96), .A1(n171gat) ); 593 | OR2_X4 inst_34 ( .A2(net_125), .A1(net_117), .ZN(net_108) ); 594 | XNOR2_X1 inst_12 ( .ZN(net_41), .B(net_22), .A(net_21) ); 595 | AND4_X1 inst_195 ( .ZN(net_170), .A4(net_164), .A1(net_150), .A2(net_107), .A3(net_14) ); 596 | NOR2_X1 inst_56 ( .ZN(net_104), .A2(net_96), .A1(n171gat) ); 597 | NAND3_X1 inst_71 ( .ZN(net_54), .A2(net_28), .A3(n447gat), .A1(n80gat) ); 598 | XNOR2_X1 inst_21 ( .ZN(net_168), .A(net_165), .B(net_145) ); 599 | NAND2_X1 inst_104 ( .ZN(net_35), .A2(net_29), .A1(n42gat) ); 600 | NAND4_X1 inst_60 ( .ZN(net_43), .A3(net_37), .A4(net_35), .A1(n51gat), .A2(n17gat) ); 601 | AND2_X4 inst_215 ( .ZN(net_175), .A2(net_173), .A1(net_113) ); 602 | NAND2_X1 inst_169 ( .ZN(net_173), .A2(net_166), .A1(net_130) ); 603 | NAND2_X1 inst_168 ( .ZN(net_166), .A2(net_165), .A1(net_129) ); 604 | NAND2_X1 inst_97 ( .ZN(net_32), .A2(n17gat), .A1(n13gat) ); 605 | NAND2_X1 inst_161 ( .ZN(net_140), .A1(net_139), .A2(net_138) ); 606 | NAND2_X1 inst_124 ( .A2(net_72), .ZN(net_71), .A1(n146gat) ); 607 | XNOR2_X1 inst_18 ( .A(net_49), .B(net_46), .ZN(n767gat) ); 608 | XNOR2_X1 inst_16 ( .ZN(net_49), .A(net_40), .B(n135gat) ); 609 | AND2_X4 inst_208 ( .ZN(net_31), .A2(n36gat), .A1(n29gat) ); 610 | NAND2_X1 inst_88 ( .ZN(net_5), .A2(n91gat), .A1(n210gat) ); 611 | AND2_X2 inst_220 ( .A2(net_30), .ZN(n423gat), .A1(n90gat) ); 612 | XNOR2_X1 inst_3 ( .ZN(net_21), .B(n165gat), .A(n159gat) ); 613 | NAND2_X1 inst_156 ( .A2(net_139), .ZN(net_127), .A1(n237gat) ); 614 | XNOR2_X1 inst_9 ( .ZN(net_38), .B(net_20), .A(net_19) ); 615 | NAND2_X1 inst_113 ( .ZN(net_60), .A2(net_58), .A1(n143gat) ); 616 | NAND2_X1 inst_170 ( .ZN(net_171), .A2(net_168), .A1(n219gat) ); 617 | AND4_X1 inst_198 ( .ZN(net_184), .A4(net_179), .A2(net_137), .A1(net_127), .A3(net_13) ); 618 | OR2_X4 inst_50 ( .ZN(net_180), .A2(net_175), .A1(net_139) ); 619 | NAND2_X1 inst_137 ( .A2(net_90), .ZN(net_88), .A1(n246gat) ); 620 | AND4_X1 inst_199 ( .ZN(net_190), .A4(net_185), .A2(net_157), .A1(net_108), .A3(net_0) ); 621 | OR2_X4 inst_41 ( .A1(net_154), .ZN(net_135), .A2(net_134) ); 622 | NAND2_X1 inst_130 ( .A2(net_81), .ZN(net_78), .A1(n183gat) ); 623 | NAND2_X1 inst_91 ( .ZN(net_8), .A1(n8gat), .A2(n138gat) ); 624 | NAND2_X1 inst_132 ( .A2(net_81), .ZN(net_80), .A1(n165gat) ); 625 | NAND2_X1 inst_143 ( .A2(net_95), .ZN(net_94), .A1(n246gat) ); 626 | NAND2_X1 inst_176 ( .ZN(net_185), .A2(net_182), .A1(n219gat) ); 627 | NAND2_X1 inst_152 ( .ZN(net_136), .A2(net_113), .A1(net_106) ); 628 | NOR2_X1 inst_58 ( .ZN(net_138), .A1(net_114), .A2(net_104) ); 629 | OR2_X4 inst_36 ( .A1(net_117), .ZN(net_112), .A2(net_111) ); 630 | NAND2_X1 inst_147 ( .ZN(net_130), .A2(net_100), .A1(n183gat) ); 631 | NAND2_X1 inst_87 ( .ZN(net_17), .A2(n26gat), .A1(n1gat) ); 632 | NAND4_X1 inst_61 ( .ZN(net_44), .A4(net_34), .A2(n447gat), .A3(n59gat), .A1(n156gat) ); 633 | AND3_X2 inst_203 ( .A3(net_45), .ZN(n448gat), .A2(n68gat), .A1(n29gat) ); 634 | OR2_X4 inst_45 ( .A1(net_154), .ZN(net_148), .A2(net_147) ); 635 | NAND2_X1 inst_96 ( .ZN(net_13), .A1(n210gat), .A2(n101gat) ); 636 | AND2_X4 inst_212 ( .ZN(net_58), .A2(net_50), .A1(n55gat) ); 637 | NAND2_X1 inst_101 ( .A2(net_29), .ZN(n420gat), .A1(n80gat) ); 638 | XOR2_X1 inst_0 ( .Z(net_19), .B(n96gat), .A(n91gat) ); 639 | INV_X1 inst_184 ( .ZN(net_37), .A(net_16) ); 640 | XNOR2_X1 inst_10 ( .ZN(net_39), .B(net_24), .A(net_23) ); 641 | XNOR2_X1 inst_4 ( .ZN(net_22), .B(n177gat), .A(n171gat) ); 642 | NAND4_X1 inst_65 ( .ZN(net_86), .A2(net_84), .A4(net_69), .A1(net_60), .A3(net_8) ); 643 | NAND2_X1 inst_178 ( .A2(net_187), .A1(net_111), .ZN(n866gat) ); 644 | NAND2_X1 inst_89 ( .ZN(net_6), .A1(n152gat), .A2(n138gat) ); 645 | OR2_X4 inst_28 ( .ZN(net_30), .A2(n88gat), .A1(n87gat) ); 646 | NAND2_X1 inst_111 ( .A2(net_58), .ZN(net_57), .A1(n146gat) ); 647 | NAND4_X1 inst_66 ( .ZN(net_165), .A4(net_152), .A1(net_133), .A2(net_128), .A3(net_120) ); 648 | NAND2_X1 inst_117 ( .A2(net_67), .ZN(net_63), .A1(n111gat) ); 649 | NAND2_X1 inst_98 ( .ZN(net_14), .A1(n210gat), .A2(n116gat) ); 650 | INV_X1 inst_190 ( .A(net_114), .ZN(net_105) ); 651 | NAND4_X1 inst_63 ( .ZN(net_97), .A2(net_84), .A4(net_66), .A1(net_57), .A3(net_11) ); 652 | XNOR2_X1 inst_7 ( .ZN(net_26), .B(n116gat), .A(n111gat) ); 653 | AND3_X2 inst_204 ( .A3(net_52), .ZN(n449gat), .A1(n74gat), .A2(n68gat) ); 654 | INV_X1 inst_185 ( .ZN(net_18), .A(net_17) ); 655 | INV_X1 inst_182 ( .ZN(net_33), .A(n17gat) ); 656 | OR2_X4 inst_49 ( .ZN(net_157), .A2(net_156), .A1(net_154) ); 657 | NAND2_X1 inst_120 ( .A2(net_67), .ZN(net_66), .A1(n96gat) ); 658 | NAND2_X1 inst_154 ( .ZN(net_156), .A1(net_125), .A2(net_124) ); 659 | XNOR2_X1 inst_13 ( .ZN(net_46), .A(net_38), .B(n130gat) ); 660 | NAND2_X1 inst_119 ( .A2(net_67), .ZN(net_65), .A1(n101gat) ); 661 | NAND3_X1 inst_75 ( .ZN(net_100), .A3(net_85), .A2(net_74), .A1(net_63) ); 662 | INV_X1 inst_192 ( .ZN(net_141), .A(net_116) ); 663 | NAND2_X1 inst_166 ( .ZN(net_163), .A2(net_160), .A1(net_122) ); 664 | NAND2_X1 inst_116 ( .A2(net_67), .ZN(net_62), .A1(n116gat) ); 665 | NAND2_X1 inst_163 ( .ZN(net_152), .A1(net_151), .A2(net_132) ); 666 | NAND2_X1 inst_85 ( .ZN(net_3), .A2(n268gat), .A1(n210gat) ); 667 | NOR2_X1 inst_54 ( .ZN(net_98), .A2(net_89), .A1(n195gat) ); 668 | NAND3_X1 inst_79 ( .A1(net_193), .A3(net_92), .A2(net_82), .ZN(n878gat) ); 669 | NAND2_X1 inst_109 ( .ZN(net_72), .A2(net_51), .A1(n1gat) ); 670 | NAND2_X1 inst_106 ( .A2(net_42), .ZN(n446gat), .A1(n390gat) ); 671 | AND2_X2 inst_219 ( .A2(net_31), .ZN(n389gat), .A1(n80gat) ); 672 | AND4_X1 inst_201 ( .ZN(net_194), .A4(net_192), .A2(net_155), .A1(net_109), .A3(net_5) ); 673 | AND4_X1 inst_193 ( .ZN(net_81), .A4(net_53), .A1(n73gat), .A3(n68gat), .A2(n42gat) ); 674 | NAND2_X1 inst_149 ( .ZN(net_116), .A2(net_102), .A1(n201gat) ); 675 | OR2_X4 inst_43 ( .A1(net_154), .ZN(net_144), .A2(net_143) ); 676 | OR2_X4 inst_39 ( .A1(net_122), .ZN(net_120), .A2(net_119) ); 677 | NAND2_X1 inst_128 ( .A2(net_81), .ZN(net_76), .A1(n189gat) ); 678 | NAND3_X1 inst_73 ( .ZN(net_90), .A2(net_85), .A1(net_71), .A3(net_62) ); 679 | AND2_X2 inst_217 ( .A2(net_28), .ZN(n388gat), .A1(n42gat) ); 680 | XNOR2_X1 inst_23 ( .ZN(net_174), .B(net_173), .A(net_136) ); 681 | NAND2_X1 inst_171 ( .ZN(net_172), .A2(net_169), .A1(n219gat) ); 682 | NAND3_X1 inst_77 ( .A1(net_184), .A3(net_94), .A2(net_83), .ZN(n874gat) ); 683 | NAND2_X1 inst_94 ( .ZN(net_11), .A1(n51gat), .A2(n138gat) ); 684 | 685 | endmodule 686 | -------------------------------------------------------------------------------- /benchmark/s27.v: -------------------------------------------------------------------------------- 1 | module s27 ( 2 | G1, 3 | G2, 4 | clk_net, 5 | reset_net, 6 | G3, 7 | G0, 8 | G17); 9 | 10 | // Start PIs 11 | input G1; 12 | input G2; 13 | input clk_net; 14 | input reset_net; 15 | input G3; 16 | input G0; 17 | 18 | // Start POs 19 | output G17; 20 | 21 | // Start wires 22 | wire G1; 23 | wire net_5; 24 | wire net_15; 25 | wire net_27; 26 | wire G17; 27 | wire reset_net; 28 | wire net_14; 29 | wire G3; 30 | wire net_26; 31 | wire clk_net; 32 | wire net_13; 33 | wire G2; 34 | wire net_19; 35 | wire net_3; 36 | wire net_22; 37 | wire net_16; 38 | wire net_6; 39 | wire net_24; 40 | wire net_11; 41 | wire net_1; 42 | wire net_23; 43 | wire net_18; 44 | wire net_12; 45 | wire net_2; 46 | wire net_10; 47 | wire net_8; 48 | wire net_9; 49 | wire net_25; 50 | wire net_21; 51 | wire net_7; 52 | wire net_20; 53 | wire G0; 54 | wire net_4; 55 | wire net_17; 56 | 57 | // Start cells 58 | CLKBUF_X2 inst_19 ( .A(net_17), .Z(net_18) ); 59 | DFFR_X2 inst_14 ( .RN(net_12), .D(net_10), .QN(net_3), .CK(net_27) ); 60 | INV_X1 inst_12 ( .A(net_16), .ZN(G17) ); 61 | INV_X4 inst_8 ( .ZN(net_5), .A(net_1) ); 62 | NOR2_X4 inst_2 ( .ZN(net_11), .A2(net_9), .A1(net_6) ); 63 | NOR2_X4 inst_1 ( .A1(net_14), .ZN(net_8), .A2(G3) ); 64 | CLKBUF_X2 inst_21 ( .A(net_19), .Z(net_20) ); 65 | CLKBUF_X2 inst_25 ( .A(net_23), .Z(net_24) ); 66 | NAND2_X2 inst_7 ( .ZN(net_7), .A1(net_4), .A2(net_3) ); 67 | CLKBUF_X2 inst_20 ( .A(net_18), .Z(net_19) ); 68 | INV_X1 inst_13 ( .ZN(net_12), .A(reset_net) ); 69 | CLKBUF_X2 inst_27 ( .A(net_25), .Z(net_26) ); 70 | CLKBUF_X2 inst_26 ( .A(net_17), .Z(net_25) ); 71 | NOR3_X4 inst_0 ( .ZN(net_16), .A1(net_11), .A3(net_8), .A2(net_5) ); 72 | CLKBUF_X2 inst_18 ( .A(clk_net), .Z(net_17) ); 73 | DFFR_X2 inst_15 ( .D(net_16), .RN(net_12), .QN(net_2), .CK(net_19) ); 74 | DFFR_X2 inst_16 ( .D(net_13), .RN(net_12), .QN(net_1), .CK(net_24) ); 75 | CLKBUF_X2 inst_24 ( .A(net_22), .Z(net_23) ); 76 | NOR2_X2 inst_3 ( .ZN(net_14), .A1(net_2), .A2(G0) ); 77 | NOR2_X2 inst_6 ( .A1(net_16), .A2(net_15), .ZN(net_13) ); 78 | INV_X4 inst_9 ( .ZN(net_9), .A(net_7) ); 79 | NOR2_X2 inst_5 ( .ZN(net_10), .A2(net_9), .A1(G2) ); 80 | INV_X2 inst_10 ( .ZN(net_4), .A(G1) ); 81 | NOR2_X2 inst_4 ( .ZN(net_6), .A1(net_2), .A2(G0) ); 82 | CLKBUF_X2 inst_23 ( .A(net_21), .Z(net_22) ); 83 | INV_X2 inst_11 ( .ZN(net_15), .A(G0) ); 84 | CLKBUF_X2 inst_28 ( .A(net_26), .Z(net_27) ); 85 | CLKBUF_X2 inst_22 ( .A(net_20), .Z(net_21) ); 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /benchmark/s27_path.v: -------------------------------------------------------------------------------- 1 | module s27_path ( 2 | G1, 3 | G2, 4 | clk_net, 5 | reset_net, 6 | G3, 7 | G0, 8 | G17); 9 | 10 | // Start PIs 11 | input G1; 12 | input G2; 13 | input clk_net; 14 | input reset_net; 15 | input G3; 16 | input G0; 17 | 18 | // Start POs 19 | output G17; 20 | 21 | // Start wires 22 | wire G1; 23 | wire net_5; 24 | wire net_15; 25 | wire net_27; 26 | wire G17; 27 | wire reset_net; 28 | wire net_14; 29 | wire G3; 30 | wire net_26; 31 | wire clk_net; 32 | wire net_13; 33 | wire G2; 34 | wire net_19; 35 | wire net_3; 36 | wire net_22; 37 | wire net_16; 38 | wire net_6; 39 | wire net_24; 40 | wire net_11; 41 | wire net_1; 42 | wire net_23; 43 | wire net_18; 44 | wire net_12; 45 | wire net_2; 46 | wire net_10; 47 | wire net_8; 48 | wire net_9; 49 | wire net_25; 50 | wire net_21; 51 | wire net_7; 52 | wire net_20; 53 | wire G0; 54 | wire net_4; 55 | wire net_17; 56 | 57 | // Start cells 58 | CLKBUF_X2 inst_19 ( .A(net_17), .Z(net_18) ); 59 | DFFR_X2 inst_14 ( .RN(net_12), .D(net_10), .QN(net_3), .CK(net_27) ); 60 | INV_X1 inst_12 ( .A(net_16), .ZN(G17) ); 61 | INV_X4 inst_8 ( .ZN(net_5), .A(net_1) ); 62 | NOR2_X4 inst_2 ( .ZN(net_11), .A2(net_9), .A1(net_6) ); 63 | NOR2_X4 inst_1 ( .A1(net_14), .ZN(net_8), .A2(G3) ); 64 | CLKBUF_X2 inst_21 ( .A(net_19), .Z(net_20) ); 65 | CLKBUF_X2 inst_25 ( .A(net_23), .Z(net_24) ); 66 | NAND2_X2 inst_7 ( .ZN(net_7), .A1(net_4), .A2(net_3) ); 67 | CLKBUF_X2 inst_20 ( .A(net_18), .Z(net_19) ); 68 | INV_X1 inst_13 ( .ZN(net_12), .A(reset_net) ); 69 | CLKBUF_X2 inst_27 ( .A(net_25), .Z(net_26) ); 70 | CLKBUF_X2 inst_26 ( .A(net_17), .Z(net_25) ); 71 | NOR3_X4 inst_0 ( .ZN(net_16), .A1(net_11), .A3(net_8), .A2(net_5) ); 72 | CLKBUF_X2 inst_18 ( .A(clk_net), .Z(net_17) ); 73 | DFFR_X2 inst_15 ( .D(net_16), .RN(net_12), .QN(net_2), .CK(net_19) ); 74 | DFFR_X2 inst_16 ( .D(net_13), .RN(net_12), .QN(net_1), .CK(net_24) ); 75 | CLKBUF_X2 inst_24 ( .A(net_22), .Z(net_23) ); 76 | NOR2_X2 inst_3 ( .ZN(net_14), .A1(net_2), .A2(G0) ); 77 | NOR2_X2 inst_6 ( .A1(net_16), .A2(net_15), .ZN(net_13) ); 78 | INV_X4 inst_9 ( .ZN(net_9), .A(net_7) ); 79 | NOR2_X2 inst_5 ( .ZN(net_10), .A2(net_9), .A1(G2) ); 80 | INV_X2 inst_10 ( .ZN(net_4), .A(G1) ); 81 | NOR2_X2 inst_4 ( .ZN(net_6), .A1(net_2), .A2(G0) ); 82 | CLKBUF_X2 inst_23 ( .A(net_21), .Z(net_22) ); 83 | INV_X2 inst_11 ( .ZN(net_15), .A(G0) ); 84 | CLKBUF_X2 inst_28 ( .A(net_26), .Z(net_27) ); 85 | CLKBUF_X2 inst_22 ( .A(net_20), .Z(net_21) ); 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /benchmark/s27_spef.v: -------------------------------------------------------------------------------- 1 | module s27 ( 2 | G1, 3 | G2, 4 | clk_net, 5 | reset_net, 6 | G3, 7 | G0, 8 | G17); 9 | 10 | // Start PIs 11 | input G1; 12 | input G2; 13 | input clk_net; 14 | input reset_net; 15 | input G3; 16 | input G0; 17 | 18 | // Start POs 19 | output G17; 20 | 21 | // Start wires 22 | wire G1; 23 | wire net_5; 24 | wire net_15; 25 | wire net_27; 26 | wire G17; 27 | wire reset_net; 28 | wire net_14; 29 | wire G3; 30 | wire net_26; 31 | wire clk_net; 32 | wire net_13; 33 | wire G2; 34 | wire net_19; 35 | wire net_3; 36 | wire net_22; 37 | wire net_16; 38 | wire net_6; 39 | wire net_24; 40 | wire net_11; 41 | wire net_1; 42 | wire net_23; 43 | wire net_18; 44 | wire net_12; 45 | wire net_2; 46 | wire net_10; 47 | wire net_8; 48 | wire net_9; 49 | wire net_25; 50 | wire net_21; 51 | wire net_7; 52 | wire net_20; 53 | wire G0; 54 | wire net_4; 55 | wire net_17; 56 | 57 | // Start cells 58 | CLKBUF_X2 inst_19 ( .A(net_17), .Z(net_18) ); 59 | DFFR_X2 inst_14 ( .RN(net_12), .D(net_10), .QN(net_3), .CK(net_27) ); 60 | INV_X1 inst_12 ( .A(net_16), .ZN(G17) ); 61 | INV_X4 inst_8 ( .ZN(net_5), .A(net_1) ); 62 | NOR2_X4 inst_2 ( .ZN(net_11), .A2(net_9), .A1(net_6) ); 63 | NOR2_X4 inst_1 ( .A1(net_14), .ZN(net_8), .A2(G3) ); 64 | CLKBUF_X2 inst_21 ( .A(net_19), .Z(net_20) ); 65 | CLKBUF_X2 inst_25 ( .A(net_23), .Z(net_24) ); 66 | NAND2_X2 inst_7 ( .ZN(net_7), .A1(net_4), .A2(net_3) ); 67 | CLKBUF_X2 inst_20 ( .A(net_18), .Z(net_19) ); 68 | INV_X1 inst_13 ( .ZN(net_12), .A(reset_net) ); 69 | CLKBUF_X2 inst_27 ( .A(net_25), .Z(net_26) ); 70 | CLKBUF_X2 inst_26 ( .A(net_17), .Z(net_25) ); 71 | NOR3_X4 inst_0 ( .ZN(net_16), .A1(net_11), .A3(net_8), .A2(net_5) ); 72 | CLKBUF_X2 inst_18 ( .A(clk_net), .Z(net_17) ); 73 | DFFR_X2 inst_15 ( .D(net_16), .RN(net_12), .QN(net_2), .CK(net_19) ); 74 | DFFR_X2 inst_16 ( .D(net_13), .RN(net_12), .QN(net_1), .CK(net_24) ); 75 | CLKBUF_X2 inst_24 ( .A(net_22), .Z(net_23) ); 76 | NOR2_X2 inst_3 ( .ZN(net_14), .A1(net_2), .A2(G0) ); 77 | NOR2_X2 inst_6 ( .A1(net_16), .A2(net_15), .ZN(net_13) ); 78 | INV_X4 inst_9 ( .ZN(net_9), .A(net_7) ); 79 | NOR2_X2 inst_5 ( .ZN(net_10), .A2(net_9), .A1(G2) ); 80 | INV_X2 inst_10 ( .ZN(net_4), .A(G1) ); 81 | NOR2_X2 inst_4 ( .ZN(net_6), .A1(net_2), .A2(G0) ); 82 | CLKBUF_X2 inst_23 ( .A(net_21), .Z(net_22) ); 83 | INV_X2 inst_11 ( .ZN(net_15), .A(G0) ); 84 | CLKBUF_X2 inst_28 ( .A(net_26), .Z(net_27) ); 85 | CLKBUF_X2 inst_22 ( .A(net_20), .Z(net_21) ); 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /benchmark/s344.v: -------------------------------------------------------------------------------- 1 | module s344 ( 2 | B0, 3 | A1, 4 | B1, 5 | A2, 6 | A3, 7 | blif_clk_net, 8 | START, 9 | B3, 10 | A0, 11 | blif_reset_net, 12 | B2, 13 | P7, 14 | P5, 15 | CNTVCON2, 16 | P2, 17 | CNTVCO2, 18 | P1, 19 | P0, 20 | READY, 21 | P6, 22 | P3, 23 | P4); 24 | 25 | // Start PIs 26 | input B0; 27 | input A1; 28 | input B1; 29 | input A2; 30 | input A3; 31 | input blif_clk_net; 32 | input START; 33 | input B3; 34 | input A0; 35 | input blif_reset_net; 36 | input B2; 37 | 38 | // Start POs 39 | output P7; 40 | output P5; 41 | output CNTVCON2; 42 | output P2; 43 | output CNTVCO2; 44 | output P1; 45 | output P0; 46 | output READY; 47 | output P6; 48 | output P3; 49 | output P4; 50 | 51 | // Start wires 52 | wire net_166; 53 | wire net_107; 54 | wire net_47; 55 | wire net_159; 56 | wire net_61; 57 | wire net_137; 58 | wire net_132; 59 | wire net_54; 60 | wire net_105; 61 | wire net_62; 62 | wire P3; 63 | wire net_6; 64 | wire net_129; 65 | wire net_119; 66 | wire net_98; 67 | wire net_23; 68 | wire P5; 69 | wire net_117; 70 | wire net_12; 71 | wire B1; 72 | wire net_151; 73 | wire net_74; 74 | wire net_53; 75 | wire net_93; 76 | wire net_168; 77 | wire net_135; 78 | wire net_130; 79 | wire net_147; 80 | wire net_127; 81 | wire net_14; 82 | wire P1; 83 | wire net_113; 84 | wire net_26; 85 | wire net_76; 86 | wire blif_clk_net; 87 | wire net_101; 88 | wire net_32; 89 | wire net_111; 90 | wire net_90; 91 | wire net_40; 92 | wire net_100; 93 | wire net_85; 94 | wire net_69; 95 | wire net_124; 96 | wire net_161; 97 | wire net_141; 98 | wire net_160; 99 | wire net_83; 100 | wire net_115; 101 | wire B3; 102 | wire net_4; 103 | wire net_95; 104 | wire net_17; 105 | wire net_78; 106 | wire A1; 107 | wire net_27; 108 | wire net_164; 109 | wire net_56; 110 | wire net_87; 111 | wire net_0; 112 | wire net_155; 113 | wire net_35; 114 | wire net_16; 115 | wire net_22; 116 | wire net_39; 117 | wire net_157; 118 | wire net_144; 119 | wire net_102; 120 | wire net_2; 121 | wire net_59; 122 | wire net_9; 123 | wire net_42; 124 | wire net_120; 125 | wire A3; 126 | wire net_109; 127 | wire net_80; 128 | wire net_65; 129 | wire blif_reset_net; 130 | wire net_50; 131 | wire net_162; 132 | wire net_96; 133 | wire net_66; 134 | wire net_38; 135 | wire net_44; 136 | wire net_167; 137 | wire net_136; 138 | wire net_134; 139 | wire net_19; 140 | wire net_89; 141 | wire net_45; 142 | wire net_126; 143 | wire B0; 144 | wire net_34; 145 | wire net_108; 146 | wire net_150; 147 | wire net_63; 148 | wire P2; 149 | wire net_152; 150 | wire net_116; 151 | wire net_30; 152 | wire net_91; 153 | wire net_106; 154 | wire net_24; 155 | wire net_55; 156 | wire net_99; 157 | wire net_46; 158 | wire net_140; 159 | wire net_118; 160 | wire P7; 161 | wire net_148; 162 | wire net_104; 163 | wire net_146; 164 | wire net_72; 165 | wire net_122; 166 | wire net_25; 167 | wire net_7; 168 | wire net_70; 169 | wire P4; 170 | wire net_5; 171 | wire net_52; 172 | wire net_165; 173 | wire net_128; 174 | wire P0; 175 | wire net_138; 176 | wire net_13; 177 | wire P6; 178 | wire net_94; 179 | wire net_11; 180 | wire CNTVCON2; 181 | wire net_18; 182 | wire net_123; 183 | wire net_131; 184 | wire net_114; 185 | wire CNTVCO2; 186 | wire net_170; 187 | wire net_29; 188 | wire net_68; 189 | wire net_149; 190 | wire net_142; 191 | wire net_77; 192 | wire net_20; 193 | wire net_31; 194 | wire net_36; 195 | wire net_49; 196 | wire net_158; 197 | wire net_15; 198 | wire net_41; 199 | wire net_57; 200 | wire A2; 201 | wire net_71; 202 | wire net_153; 203 | wire START; 204 | wire net_156; 205 | wire net_3; 206 | wire net_84; 207 | wire net_154; 208 | wire net_112; 209 | wire net_1; 210 | wire net_92; 211 | wire net_103; 212 | wire net_139; 213 | wire net_43; 214 | wire net_10; 215 | wire net_28; 216 | wire net_169; 217 | wire net_21; 218 | wire net_51; 219 | wire net_79; 220 | wire net_143; 221 | wire net_97; 222 | wire net_88; 223 | wire net_145; 224 | wire net_60; 225 | wire net_81; 226 | wire net_163; 227 | wire net_58; 228 | wire B2; 229 | wire net_67; 230 | wire net_82; 231 | wire net_64; 232 | wire net_37; 233 | wire net_110; 234 | wire net_121; 235 | wire net_73; 236 | wire net_33; 237 | wire net_48; 238 | wire net_8; 239 | wire net_75; 240 | wire net_86; 241 | wire net_133; 242 | wire READY; 243 | wire A0; 244 | wire net_125; 245 | 246 | // Start cells 247 | CLKBUF_X2 inst_145 ( .A(net_133), .Z(net_134) ); 248 | INV_X2 inst_103 ( .A(net_22), .ZN(net_17) ); 249 | DFFR_X1 inst_125 ( .D(net_97), .RN(net_96), .QN(net_2), .CK(net_138) ); 250 | CLKBUF_X2 inst_138 ( .A(net_126), .Z(net_127) ); 251 | CLKBUF_X2 inst_159 ( .A(net_138), .Z(net_148) ); 252 | NAND3_X2 inst_15 ( .ZN(net_84), .A3(net_78), .A1(net_59), .A2(P6) ); 253 | CLKBUF_X2 inst_134 ( .A(net_122), .Z(net_123) ); 254 | CLKBUF_X2 inst_179 ( .A(net_148), .Z(net_168) ); 255 | NAND3_X1 inst_24 ( .ZN(net_83), .A3(net_82), .A1(net_73), .A2(net_72) ); 256 | DFFR_X2 inst_114 ( .RN(net_96), .D(net_69), .QN(net_5), .CK(net_160) ); 257 | OR2_X4 inst_6 ( .ZN(net_41), .A2(READY), .A1(B1) ); 258 | CLKBUF_X2 inst_131 ( .A(net_119), .Z(net_120) ); 259 | INV_X4 inst_76 ( .ZN(net_19), .A(net_10) ); 260 | CLKBUF_X2 inst_180 ( .A(net_168), .Z(net_169) ); 261 | CLKBUF_X2 inst_160 ( .A(net_119), .Z(net_149) ); 262 | CLKBUF_X2 inst_150 ( .A(net_129), .Z(net_139) ); 263 | NAND2_X4 inst_33 ( .A2(net_104), .A1(net_103), .ZN(net_90) ); 264 | CLKBUF_X2 inst_172 ( .A(net_133), .Z(net_161) ); 265 | INV_X4 inst_83 ( .ZN(net_32), .A(net_11) ); 266 | NAND2_X2 inst_47 ( .ZN(net_50), .A1(net_34), .A2(net_31) ); 267 | NAND3_X2 inst_19 ( .ZN(net_117), .A2(net_91), .A3(net_87), .A1(net_84) ); 268 | DFFR_X2 inst_123 ( .RN(net_96), .D(net_93), .QN(net_1), .CK(net_128) ); 269 | DFFR_X2 inst_121 ( .RN(net_96), .D(net_79), .QN(net_13), .CK(net_134) ); 270 | OR3_X2 inst_2 ( .A3(net_113), .A1(net_112), .ZN(net_65), .A2(net_56) ); 271 | NOR2_X2 inst_8 ( .A2(net_29), .A1(net_14), .ZN(CNTVCO2) ); 272 | DFFR_X2 inst_118 ( .RN(net_96), .D(net_76), .QN(net_11), .CK(net_147) ); 273 | INV_X4 inst_86 ( .A(net_73), .ZN(P6) ); 274 | CLKBUF_X2 inst_153 ( .A(net_141), .Z(net_142) ); 275 | NAND3_X2 inst_20 ( .A2(net_117), .A3(net_94), .ZN(net_93), .A1(net_57) ); 276 | NAND2_X4 inst_27 ( .ZN(net_62), .A1(net_30), .A2(net_27) ); 277 | NAND2_X2 inst_38 ( .ZN(net_45), .A2(net_30), .A1(net_17) ); 278 | INV_X2 inst_100 ( .A(net_48), .ZN(P4) ); 279 | NAND2_X2 inst_52 ( .A2(net_62), .ZN(net_58), .A1(net_48) ); 280 | INV_X4 inst_90 ( .ZN(net_44), .A(net_24) ); 281 | CLKBUF_X2 inst_140 ( .A(net_122), .Z(net_129) ); 282 | NAND2_X2 inst_40 ( .ZN(net_33), .A1(net_32), .A2(READY) ); 283 | CLKBUF_X2 inst_162 ( .A(net_150), .Z(net_151) ); 284 | CLKBUF_X2 inst_167 ( .A(net_124), .Z(net_156) ); 285 | INV_X2 inst_93 ( .A(net_114), .ZN(net_113) ); 286 | INV_X4 inst_81 ( .ZN(net_28), .A(net_4) ); 287 | INV_X2 inst_95 ( .ZN(net_26), .A(net_7) ); 288 | XOR2_X2 inst_1 ( .Z(net_63), .B(net_45), .A(net_16) ); 289 | INV_X4 inst_72 ( .ZN(net_115), .A(P0) ); 290 | CLKBUF_X2 inst_139 ( .A(net_127), .Z(net_128) ); 291 | CLKBUF_X2 inst_155 ( .A(net_123), .Z(net_144) ); 292 | NAND2_X2 inst_59 ( .ZN(net_75), .A1(net_62), .A2(net_50) ); 293 | CLKBUF_X2 inst_135 ( .A(net_123), .Z(net_124) ); 294 | NAND2_X2 inst_44 ( .A1(net_113), .ZN(net_99), .A2(net_56) ); 295 | NAND2_X2 inst_55 ( .ZN(net_111), .A1(net_44), .A2(net_2) ); 296 | CLKBUF_X2 inst_174 ( .A(net_162), .Z(net_163) ); 297 | DFFR_X2 inst_115 ( .RN(net_96), .D(net_70), .QN(net_4), .CK(net_155) ); 298 | NAND2_X2 inst_37 ( .A2(net_116), .ZN(net_47), .A1(net_26) ); 299 | CLKBUF_X2 inst_148 ( .A(net_136), .Z(net_137) ); 300 | CLKBUF_X2 inst_164 ( .A(net_152), .Z(net_153) ); 301 | OR2_X4 inst_5 ( .ZN(net_40), .A2(READY), .A1(B2) ); 302 | CLKBUF_X2 inst_157 ( .A(net_145), .Z(net_146) ); 303 | INV_X4 inst_84 ( .ZN(net_37), .A(net_12) ); 304 | NAND2_X2 inst_51 ( .A2(net_62), .ZN(net_57), .A1(net_56) ); 305 | CLKBUF_X2 inst_142 ( .A(net_120), .Z(net_131) ); 306 | INV_X4 inst_80 ( .ZN(net_20), .A(net_5) ); 307 | CLKBUF_X2 inst_173 ( .A(net_161), .Z(net_162) ); 308 | INV_X2 inst_105 ( .A(CNTVCO2), .ZN(CNTVCON2) ); 309 | MUX2_X2 inst_68 ( .Z(net_70), .B(net_28), .S(net_27), .A(A0) ); 310 | INV_X4 inst_78 ( .ZN(net_73), .A(net_2) ); 311 | NAND2_X2 inst_42 ( .ZN(net_38), .A1(net_37), .A2(READY) ); 312 | CLKBUF_X2 inst_175 ( .A(net_163), .Z(net_164) ); 313 | NAND2_X2 inst_53 ( .A2(net_62), .ZN(net_61), .A1(net_60) ); 314 | CLKBUF_X2 inst_177 ( .A(net_164), .Z(net_166) ); 315 | CLKBUF_X2 inst_133 ( .A(net_121), .Z(net_122) ); 316 | NAND2_X4 inst_26 ( .ZN(net_112), .A1(net_100), .A2(net_28) ); 317 | CLKBUF_X2 inst_151 ( .A(net_139), .Z(net_140) ); 318 | DFFR_X2 inst_112 ( .RN(net_96), .D(net_55), .QN(net_10), .CK(net_167) ); 319 | NAND2_X1 inst_64 ( .A2(net_88), .ZN(net_87), .A1(net_83) ); 320 | INV_X2 inst_107 ( .ZN(net_110), .A(net_64) ); 321 | MUX2_X2 inst_67 ( .Z(net_69), .S(net_27), .B(net_20), .A(A1) ); 322 | CLKBUF_X2 inst_181 ( .A(net_169), .Z(net_170) ); 323 | AND2_X4 inst_127 ( .A1(net_116), .ZN(net_100), .A2(net_0) ); 324 | MUX2_X2 inst_70 ( .S(net_91), .Z(net_77), .A(net_52), .B(net_35) ); 325 | CLKBUF_X2 inst_129 ( .A(blif_clk_net), .Z(net_118) ); 326 | INV_X4 inst_92 ( .ZN(net_91), .A(net_62) ); 327 | NAND2_X4 inst_29 ( .A2(net_99), .A1(net_98), .ZN(net_82) ); 328 | NAND3_X2 inst_17 ( .ZN(net_109), .A1(net_88), .A3(net_60), .A2(net_47) ); 329 | NOR2_X2 inst_11 ( .ZN(net_74), .A2(net_63), .A1(START) ); 330 | CLKBUF_X2 inst_146 ( .A(net_126), .Z(net_135) ); 331 | NAND3_X2 inst_14 ( .A1(net_113), .A3(net_112), .A2(net_56), .ZN(net_54) ); 332 | DFFR_X2 inst_122 ( .RN(net_96), .D(net_89), .QN(net_0), .CK(net_130) ); 333 | NAND2_X4 inst_31 ( .A2(net_102), .A1(net_101), .ZN(net_88) ); 334 | NAND2_X4 inst_25 ( .A2(net_116), .ZN(net_21), .A1(net_20) ); 335 | CLKBUF_X3 inst_126 ( .A(net_116), .Z(P0) ); 336 | CLKBUF_X2 inst_158 ( .A(net_146), .Z(net_147) ); 337 | CLKBUF_X2 inst_141 ( .A(net_129), .Z(net_130) ); 338 | NAND2_X2 inst_62 ( .ZN(net_92), .A1(net_91), .A2(net_90) ); 339 | INV_X1 inst_110 ( .A(net_82), .ZN(net_78) ); 340 | INV_X4 inst_74 ( .ZN(net_56), .A(net_1) ); 341 | NAND2_X2 inst_57 ( .A2(net_91), .ZN(net_71), .A1(net_32) ); 342 | NAND2_X2 inst_35 ( .A2(net_116), .ZN(net_24), .A1(net_23) ); 343 | INV_X2 inst_99 ( .A(net_60), .ZN(P7) ); 344 | NAND2_X2 inst_48 ( .ZN(net_51), .A1(net_39), .A2(net_36) ); 345 | MUX2_X2 inst_69 ( .S(net_91), .Z(net_76), .A(net_53), .B(net_37) ); 346 | NAND2_X2 inst_46 ( .ZN(net_49), .A1(net_48), .A2(net_25) ); 347 | INV_X4 inst_82 ( .ZN(net_60), .A(net_3) ); 348 | CLKBUF_X2 inst_136 ( .A(net_124), .Z(net_125) ); 349 | NAND2_X4 inst_30 ( .A2(net_111), .ZN(net_101), .A1(net_82) ); 350 | INV_X2 inst_102 ( .ZN(net_16), .A(net_9) ); 351 | INV_X2 inst_108 ( .A(net_88), .ZN(net_85) ); 352 | CLKBUF_X2 inst_165 ( .A(net_153), .Z(net_154) ); 353 | NAND2_X4 inst_32 ( .A2(net_110), .ZN(net_103), .A1(net_88) ); 354 | NAND3_X2 inst_22 ( .ZN(net_95), .A2(net_94), .A3(net_92), .A1(net_61) ); 355 | CLKBUF_X2 inst_144 ( .A(net_132), .Z(net_133) ); 356 | NAND2_X4 inst_34 ( .A2(net_109), .ZN(net_105), .A1(net_90) ); 357 | NAND3_X4 inst_12 ( .ZN(net_30), .A2(net_19), .A3(net_15), .A1(net_9) ); 358 | NAND2_X2 inst_56 ( .A2(net_112), .ZN(net_66), .A1(net_49) ); 359 | MUX2_X2 inst_71 ( .S(net_91), .Z(net_79), .B(net_66), .A(net_51) ); 360 | NAND3_X2 inst_21 ( .ZN(net_107), .A3(net_106), .A1(net_105), .A2(net_91) ); 361 | INV_X2 inst_104 ( .ZN(net_18), .A(P6) ); 362 | NAND2_X2 inst_60 ( .ZN(net_80), .A2(net_75), .A1(net_71) ); 363 | CLKBUF_X2 inst_169 ( .A(net_157), .Z(net_158) ); 364 | CLKBUF_X2 inst_168 ( .A(net_156), .Z(net_157) ); 365 | INV_X2 inst_97 ( .A(net_37), .ZN(P2) ); 366 | CLKBUF_X2 inst_161 ( .A(net_149), .Z(net_150) ); 367 | DFFR_X2 inst_124 ( .RN(net_96), .D(net_95), .QN(net_3), .CK(net_125) ); 368 | NAND3_X2 inst_18 ( .A2(net_94), .ZN(net_89), .A3(net_86), .A1(net_58) ); 369 | NAND3_X2 inst_16 ( .A2(net_91), .ZN(net_86), .A3(net_81), .A1(net_65) ); 370 | INV_X4 inst_88 ( .ZN(net_22), .A(net_15) ); 371 | OR2_X4 inst_3 ( .ZN(net_29), .A1(net_22), .A2(net_9) ); 372 | CLKBUF_X2 inst_156 ( .A(net_144), .Z(net_145) ); 373 | NOR2_X2 inst_9 ( .ZN(net_64), .A1(net_60), .A2(net_47) ); 374 | DFFR_X2 inst_113 ( .RN(net_96), .D(net_67), .QN(net_7), .CK(net_165) ); 375 | CLKBUF_X2 inst_170 ( .A(net_158), .Z(net_159) ); 376 | NAND2_X2 inst_50 ( .ZN(net_53), .A1(net_41), .A2(net_33) ); 377 | CLKBUF_X2 inst_137 ( .A(net_118), .Z(net_126) ); 378 | NAND2_X2 inst_41 ( .ZN(net_36), .A1(net_35), .A2(READY) ); 379 | CLKBUF_X2 inst_130 ( .A(net_118), .Z(net_119) ); 380 | INV_X4 inst_91 ( .ZN(net_72), .A(net_44) ); 381 | CLKBUF_X2 inst_132 ( .A(blif_clk_net), .Z(net_121) ); 382 | CLKBUF_X2 inst_143 ( .A(net_131), .Z(net_132) ); 383 | CLKBUF_X2 inst_176 ( .A(net_164), .Z(net_165) ); 384 | CLKBUF_X2 inst_152 ( .A(net_140), .Z(net_141) ); 385 | NAND2_X2 inst_58 ( .ZN(net_102), .A1(net_73), .A2(net_72) ); 386 | NAND2_X2 inst_36 ( .A2(net_116), .A1(net_28), .ZN(net_25) ); 387 | CLKBUF_X2 inst_147 ( .A(net_135), .Z(net_136) ); 388 | INV_X4 inst_87 ( .A(net_19), .ZN(net_14) ); 389 | NAND2_X2 inst_61 ( .ZN(net_106), .A2(net_85), .A1(net_64) ); 390 | NAND2_X2 inst_45 ( .ZN(net_104), .A1(net_60), .A2(net_47) ); 391 | INV_X2 inst_96 ( .A(net_32), .ZN(P1) ); 392 | INV_X2 inst_101 ( .A(net_56), .ZN(P5) ); 393 | XOR2_X2 inst_0 ( .Z(net_43), .A(net_29), .B(net_19) ); 394 | NOR2_X2 inst_10 ( .ZN(net_55), .A2(net_43), .A1(START) ); 395 | OR2_X4 inst_4 ( .ZN(net_39), .A2(READY), .A1(B3) ); 396 | MUX2_X2 inst_65 ( .Z(net_67), .S(net_27), .B(net_26), .A(A3) ); 397 | CLKBUF_X2 inst_178 ( .A(net_166), .Z(net_167) ); 398 | INV_X4 inst_89 ( .A(net_30), .ZN(READY) ); 399 | NAND2_X4 inst_28 ( .A2(net_112), .ZN(net_98), .A1(net_42) ); 400 | DFFR_X2 inst_111 ( .RN(net_96), .D(net_46), .QN(net_8), .CK(net_170) ); 401 | MUX2_X2 inst_66 ( .Z(net_68), .S(net_27), .B(net_23), .A(A2) ); 402 | DFFR_X2 inst_117 ( .RN(net_96), .D(net_74), .QN(net_9), .CK(net_148) ); 403 | INV_X2 inst_98 ( .A(net_35), .ZN(P3) ); 404 | NAND2_X1 inst_63 ( .A2(net_82), .ZN(net_81), .A1(net_54) ); 405 | OR2_X2 inst_7 ( .ZN(net_34), .A2(READY), .A1(B0) ); 406 | NAND2_X2 inst_49 ( .ZN(net_52), .A1(net_40), .A2(net_38) ); 407 | DFFR_X2 inst_120 ( .QN(net_116), .RN(net_96), .D(net_80), .CK(net_120) ); 408 | CLKBUF_X2 inst_154 ( .A(net_142), .Z(net_143) ); 409 | NAND3_X2 inst_13 ( .ZN(net_27), .A2(net_22), .A3(net_10), .A1(net_9) ); 410 | DFFR_X2 inst_119 ( .RN(net_96), .D(net_77), .QN(net_12), .CK(net_143) ); 411 | INV_X4 inst_75 ( .ZN(net_15), .A(net_8) ); 412 | CLKBUF_X2 inst_166 ( .A(net_154), .Z(net_155) ); 413 | DFFR_X2 inst_116 ( .RN(net_96), .D(net_68), .QN(net_6), .CK(net_151) ); 414 | CLKBUF_X2 inst_163 ( .A(net_122), .Z(net_152) ); 415 | INV_X4 inst_85 ( .ZN(net_94), .A(START) ); 416 | NAND2_X2 inst_54 ( .ZN(net_108), .A2(net_62), .A1(net_18) ); 417 | INV_X4 inst_79 ( .ZN(net_35), .A(net_13) ); 418 | INV_X1 inst_109 ( .ZN(net_96), .A(blif_reset_net) ); 419 | INV_X2 inst_106 ( .A(net_72), .ZN(net_59) ); 420 | CLKBUF_X2 inst_149 ( .A(net_137), .Z(net_138) ); 421 | NAND2_X2 inst_43 ( .A2(net_114), .ZN(net_42), .A1(net_1) ); 422 | NAND2_X2 inst_39 ( .A1(net_115), .ZN(net_31), .A2(READY) ); 423 | AND2_X2 inst_128 ( .A1(net_94), .ZN(net_46), .A2(net_45) ); 424 | INV_X4 inst_73 ( .ZN(net_114), .A(net_21) ); 425 | NAND3_X2 inst_23 ( .A3(net_108), .A1(net_107), .ZN(net_97), .A2(net_94) ); 426 | CLKBUF_X2 inst_171 ( .A(net_159), .Z(net_160) ); 427 | INV_X4 inst_77 ( .ZN(net_48), .A(net_0) ); 428 | INV_X2 inst_94 ( .ZN(net_23), .A(net_6) ); 429 | 430 | endmodule 431 | -------------------------------------------------------------------------------- /benchmark/s349.v: -------------------------------------------------------------------------------- 1 | module s349 ( 2 | B0, 3 | A1, 4 | B1, 5 | A2, 6 | A3, 7 | blif_clk_net, 8 | START, 9 | B3, 10 | A0, 11 | blif_reset_net, 12 | B2, 13 | P7, 14 | P5, 15 | CNTVCON2, 16 | P2, 17 | P1, 18 | CNTVCO2, 19 | P0, 20 | P6, 21 | READY, 22 | P3, 23 | P4); 24 | 25 | // Start PIs 26 | input B0; 27 | input A1; 28 | input B1; 29 | input A2; 30 | input A3; 31 | input blif_clk_net; 32 | input START; 33 | input B3; 34 | input A0; 35 | input blif_reset_net; 36 | input B2; 37 | 38 | // Start POs 39 | output P7; 40 | output P5; 41 | output CNTVCON2; 42 | output P2; 43 | output P1; 44 | output CNTVCO2; 45 | output P0; 46 | output P6; 47 | output READY; 48 | output P3; 49 | output P4; 50 | 51 | // Start wires 52 | wire net_166; 53 | wire net_107; 54 | wire net_47; 55 | wire net_179; 56 | wire net_176; 57 | wire net_159; 58 | wire net_61; 59 | wire net_137; 60 | wire net_132; 61 | wire net_54; 62 | wire net_105; 63 | wire net_62; 64 | wire P3; 65 | wire net_6; 66 | wire net_129; 67 | wire net_119; 68 | wire net_98; 69 | wire net_23; 70 | wire P5; 71 | wire net_117; 72 | wire net_12; 73 | wire B1; 74 | wire net_151; 75 | wire net_74; 76 | wire net_53; 77 | wire net_93; 78 | wire net_168; 79 | wire net_135; 80 | wire net_130; 81 | wire net_147; 82 | wire net_127; 83 | wire net_14; 84 | wire P1; 85 | wire net_113; 86 | wire net_26; 87 | wire net_76; 88 | wire blif_clk_net; 89 | wire net_101; 90 | wire net_32; 91 | wire net_111; 92 | wire net_90; 93 | wire net_40; 94 | wire net_100; 95 | wire net_85; 96 | wire net_69; 97 | wire net_124; 98 | wire net_161; 99 | wire net_141; 100 | wire net_160; 101 | wire net_83; 102 | wire net_115; 103 | wire B3; 104 | wire net_4; 105 | wire net_95; 106 | wire net_17; 107 | wire net_173; 108 | wire net_78; 109 | wire A1; 110 | wire net_27; 111 | wire net_164; 112 | wire net_56; 113 | wire net_87; 114 | wire net_0; 115 | wire net_155; 116 | wire net_35; 117 | wire net_16; 118 | wire net_22; 119 | wire net_181; 120 | wire net_39; 121 | wire net_157; 122 | wire net_144; 123 | wire net_102; 124 | wire net_2; 125 | wire net_59; 126 | wire net_9; 127 | wire net_42; 128 | wire net_120; 129 | wire A3; 130 | wire net_109; 131 | wire net_80; 132 | wire net_65; 133 | wire blif_reset_net; 134 | wire net_50; 135 | wire net_162; 136 | wire net_96; 137 | wire net_66; 138 | wire net_38; 139 | wire net_44; 140 | wire net_167; 141 | wire net_136; 142 | wire net_134; 143 | wire net_19; 144 | wire net_89; 145 | wire net_45; 146 | wire net_126; 147 | wire B0; 148 | wire net_34; 149 | wire net_108; 150 | wire net_178; 151 | wire net_150; 152 | wire net_63; 153 | wire P2; 154 | wire net_152; 155 | wire net_116; 156 | wire net_30; 157 | wire net_175; 158 | wire net_91; 159 | wire net_106; 160 | wire net_24; 161 | wire net_55; 162 | wire net_99; 163 | wire net_46; 164 | wire net_140; 165 | wire net_118; 166 | wire P7; 167 | wire net_148; 168 | wire net_104; 169 | wire net_146; 170 | wire net_72; 171 | wire net_122; 172 | wire net_25; 173 | wire net_7; 174 | wire net_70; 175 | wire P4; 176 | wire net_172; 177 | wire net_5; 178 | wire net_52; 179 | wire net_165; 180 | wire net_128; 181 | wire P0; 182 | wire net_138; 183 | wire net_13; 184 | wire P6; 185 | wire net_94; 186 | wire net_11; 187 | wire CNTVCON2; 188 | wire net_18; 189 | wire net_123; 190 | wire net_131; 191 | wire net_114; 192 | wire CNTVCO2; 193 | wire net_170; 194 | wire net_29; 195 | wire net_68; 196 | wire net_149; 197 | wire net_142; 198 | wire net_77; 199 | wire net_20; 200 | wire net_31; 201 | wire net_36; 202 | wire net_49; 203 | wire net_158; 204 | wire net_15; 205 | wire net_41; 206 | wire net_57; 207 | wire A2; 208 | wire net_71; 209 | wire net_153; 210 | wire START; 211 | wire net_156; 212 | wire net_3; 213 | wire net_84; 214 | wire net_174; 215 | wire net_154; 216 | wire net_112; 217 | wire net_1; 218 | wire net_92; 219 | wire net_103; 220 | wire net_139; 221 | wire net_43; 222 | wire net_10; 223 | wire net_180; 224 | wire net_28; 225 | wire net_169; 226 | wire net_21; 227 | wire net_51; 228 | wire net_171; 229 | wire net_79; 230 | wire net_143; 231 | wire net_97; 232 | wire net_88; 233 | wire net_182; 234 | wire net_145; 235 | wire net_60; 236 | wire net_81; 237 | wire net_163; 238 | wire net_58; 239 | wire B2; 240 | wire net_67; 241 | wire net_82; 242 | wire net_64; 243 | wire net_37; 244 | wire net_110; 245 | wire net_121; 246 | wire net_73; 247 | wire net_33; 248 | wire net_48; 249 | wire net_177; 250 | wire net_8; 251 | wire net_75; 252 | wire net_86; 253 | wire net_133; 254 | wire READY; 255 | wire A0; 256 | wire net_125; 257 | 258 | // Start cells 259 | CLKBUF_X2 inst_145 ( .A(net_133), .Z(net_134) ); 260 | INV_X4 inst_103 ( .ZN(net_64), .A(net_52) ); 261 | DFFR_X2 inst_125 ( .RN(net_102), .D(net_73), .QN(net_6), .CK(net_179) ); 262 | DFFR_X1 inst_138 ( .D(net_103), .RN(net_102), .QN(net_2), .CK(net_150) ); 263 | CLKBUF_X2 inst_159 ( .A(net_147), .Z(net_148) ); 264 | NOR2_X2 inst_15 ( .ZN(net_85), .A2(net_77), .A1(START) ); 265 | DFFR_X2 inst_134 ( .RN(net_102), .D(net_87), .QN(net_13), .CK(net_146) ); 266 | CLKBUF_X2 inst_179 ( .A(blif_clk_net), .Z(net_168) ); 267 | NAND3_X2 inst_24 ( .A2(net_100), .ZN(net_99), .A3(net_95), .A1(net_61) ); 268 | INV_X2 inst_114 ( .A(net_42), .ZN(P1) ); 269 | OR2_X2 inst_6 ( .A2(net_113), .ZN(net_90), .A1(net_89) ); 270 | DFFR_X2 inst_131 ( .RN(net_102), .D(net_86), .QN(net_9), .CK(net_159) ); 271 | INV_X4 inst_76 ( .A(net_128), .ZN(net_126) ); 272 | CLKBUF_X2 inst_180 ( .A(net_168), .Z(net_169) ); 273 | CLKBUF_X2 inst_160 ( .A(net_148), .Z(net_149) ); 274 | CLKBUF_X2 inst_150 ( .A(net_138), .Z(net_139) ); 275 | NAND2_X4 inst_33 ( .ZN(net_112), .A1(net_52), .A2(net_2) ); 276 | CLKBUF_X2 inst_172 ( .A(net_137), .Z(net_161) ); 277 | INV_X4 inst_83 ( .ZN(net_56), .A(net_3) ); 278 | NAND2_X2 inst_47 ( .ZN(net_39), .A1(net_38), .A2(READY) ); 279 | NAND3_X2 inst_19 ( .ZN(net_71), .A3(net_70), .A2(net_46), .A1(P5) ); 280 | INV_X1 inst_123 ( .ZN(net_102), .A(blif_reset_net) ); 281 | INV_X2 inst_121 ( .ZN(net_111), .A(net_65) ); 282 | OR2_X4 inst_2 ( .ZN(net_40), .A2(READY), .A1(B3) ); 283 | NOR3_X2 inst_8 ( .ZN(net_80), .A1(net_78), .A3(net_51), .A2(START) ); 284 | INV_X2 inst_118 ( .ZN(net_70), .A(net_68) ); 285 | INV_X4 inst_86 ( .ZN(net_100), .A(START) ); 286 | CLKBUF_X2 inst_153 ( .A(net_141), .Z(net_142) ); 287 | NAND3_X2 inst_20 ( .A3(net_117), .ZN(net_116), .A1(net_113), .A2(P6) ); 288 | NAND3_X2 inst_27 ( .A3(net_109), .A1(net_108), .ZN(net_103), .A2(net_100) ); 289 | NAND2_X4 inst_38 ( .A1(net_105), .ZN(net_94), .A2(net_89) ); 290 | INV_X4 inst_100 ( .ZN(net_45), .A(net_32) ); 291 | NAND2_X2 inst_52 ( .ZN(net_57), .A1(net_35), .A2(net_34) ); 292 | INV_X4 inst_90 ( .ZN(net_17), .A(net_2) ); 293 | AND2_X4 inst_140 ( .A1(net_121), .ZN(net_118), .A2(net_0) ); 294 | NAND2_X4 inst_40 ( .A1(net_104), .ZN(net_97), .A2(net_66) ); 295 | CLKBUF_X2 inst_162 ( .A(net_148), .Z(net_151) ); 296 | CLKBUF_X2 inst_167 ( .A(net_146), .Z(net_156) ); 297 | INV_X4 inst_93 ( .ZN(net_18), .A(net_16) ); 298 | INV_X4 inst_81 ( .ZN(net_24), .A(net_10) ); 299 | INV_X4 inst_95 ( .ZN(net_23), .A(net_18) ); 300 | XNOR2_X2 inst_1 ( .ZN(net_79), .A(net_78), .B(net_27) ); 301 | MUX2_X2 inst_72 ( .S(net_123), .Z(net_83), .A(net_60), .B(net_38) ); 302 | CLKBUF_X3 inst_139 ( .A(net_121), .Z(P0) ); 303 | CLKBUF_X2 inst_155 ( .A(net_143), .Z(net_144) ); 304 | NAND2_X2 inst_59 ( .A2(net_128), .ZN(net_109), .A1(net_20) ); 305 | DFFR_X2 inst_135 ( .RN(net_102), .D(net_96), .QN(net_0), .CK(net_142) ); 306 | NAND2_X2 inst_44 ( .A2(net_121), .ZN(net_53), .A1(net_33) ); 307 | NAND2_X2 inst_55 ( .ZN(net_60), .A1(net_44), .A2(net_43) ); 308 | CLKBUF_X2 inst_174 ( .A(net_162), .Z(net_163) ); 309 | INV_X2 inst_115 ( .ZN(net_19), .A(P5) ); 310 | NAND2_X4 inst_37 ( .A1(net_114), .A2(net_112), .ZN(net_105) ); 311 | CLKBUF_X2 inst_148 ( .A(net_136), .Z(net_137) ); 312 | CLKBUF_X2 inst_164 ( .A(net_152), .Z(net_153) ); 313 | CLKBUF_X2 inst_191 ( .A(net_154), .Z(net_180) ); 314 | OR2_X2 inst_5 ( .ZN(net_35), .A2(READY), .A1(B0) ); 315 | CLKBUF_X2 inst_157 ( .A(net_145), .Z(net_146) ); 316 | INV_X4 inst_84 ( .ZN(net_38), .A(net_12) ); 317 | NAND2_X2 inst_51 ( .ZN(net_66), .A1(net_56), .A2(net_53) ); 318 | CLKBUF_X2 inst_142 ( .A(net_130), .Z(net_131) ); 319 | INV_X4 inst_80 ( .ZN(net_16), .A(net_8) ); 320 | CLKBUF_X2 inst_173 ( .A(net_161), .Z(net_162) ); 321 | INV_X2 inst_105 ( .A(net_128), .ZN(net_127) ); 322 | MUX2_X2 inst_68 ( .S(net_122), .Z(net_72), .B(net_33), .A(A3) ); 323 | INV_X4 inst_78 ( .ZN(net_120), .A(P0) ); 324 | NAND2_X2 inst_42 ( .ZN(net_48), .A1(net_27), .A2(net_23) ); 325 | CLKBUF_X2 inst_175 ( .A(net_139), .Z(net_164) ); 326 | NAND2_X2 inst_53 ( .ZN(net_58), .A1(net_41), .A2(net_39) ); 327 | CLKBUF_X2 inst_177 ( .A(net_165), .Z(net_166) ); 328 | CLKBUF_X2 inst_183 ( .A(net_171), .Z(net_172) ); 329 | DFFR_X2 inst_133 ( .QN(net_121), .RN(net_102), .D(net_88), .CK(net_132) ); 330 | NAND3_X2 inst_26 ( .A2(net_125), .ZN(net_108), .A3(net_107), .A1(net_106) ); 331 | CLKBUF_X2 inst_151 ( .A(net_139), .Z(net_140) ); 332 | INV_X2 inst_112 ( .A(net_38), .ZN(P2) ); 333 | NAND2_X2 inst_64 ( .ZN(net_115), .A2(net_94), .A1(net_90) ); 334 | INV_X2 inst_107 ( .A(net_114), .ZN(net_113) ); 335 | NAND2_X2 inst_67 ( .A1(net_126), .ZN(net_98), .A2(net_97) ); 336 | CLKBUF_X2 inst_181 ( .A(net_169), .Z(net_170) ); 337 | DFFR_X2 inst_127 ( .RN(net_102), .D(net_80), .QN(net_8), .CK(net_172) ); 338 | MUX2_X2 inst_70 ( .S(net_122), .Z(net_74), .B(net_21), .A(A1) ); 339 | CLKBUF_X2 inst_186 ( .A(net_174), .Z(net_175) ); 340 | DFFR_X2 inst_129 ( .RN(net_102), .D(net_85), .QN(net_10), .CK(net_163) ); 341 | INV_X4 inst_92 ( .A(net_15), .ZN(P5) ); 342 | NAND2_X4 inst_29 ( .A1(net_118), .ZN(net_68), .A2(net_30) ); 343 | CLKBUF_X2 inst_189 ( .A(net_158), .Z(net_178) ); 344 | NAND3_X4 inst_17 ( .ZN(net_49), .A2(net_24), .A3(net_16), .A1(net_9) ); 345 | NOR2_X2 inst_11 ( .ZN(net_51), .A2(net_49), .A1(net_26) ); 346 | CLKBUF_X2 inst_146 ( .A(net_134), .Z(net_135) ); 347 | CLKBUF_X2 inst_188 ( .A(net_176), .Z(net_177) ); 348 | NOR2_X2 inst_14 ( .A1(net_129), .ZN(net_81), .A2(net_70) ); 349 | CLKBUF_X2 inst_187 ( .A(net_175), .Z(net_176) ); 350 | INV_X2 inst_122 ( .A(net_94), .ZN(net_92) ); 351 | NAND2_X4 inst_31 ( .ZN(net_128), .A2(net_122), .A1(net_49) ); 352 | NAND3_X2 inst_25 ( .ZN(net_101), .A2(net_100), .A3(net_98), .A1(net_63) ); 353 | DFFR_X2 inst_126 ( .RN(net_102), .D(net_75), .QN(net_4), .CK(net_177) ); 354 | CLKBUF_X2 inst_158 ( .A(net_138), .Z(net_147) ); 355 | CLKBUF_X2 inst_141 ( .A(blif_clk_net), .Z(net_130) ); 356 | NAND2_X2 inst_62 ( .A1(net_128), .ZN(net_82), .A2(net_57) ); 357 | INV_X2 inst_110 ( .A(net_56), .ZN(P7) ); 358 | MUX2_X2 inst_74 ( .S(net_124), .Z(net_87), .B(net_69), .A(net_59) ); 359 | NAND2_X2 inst_57 ( .A2(net_128), .ZN(net_62), .A1(net_54) ); 360 | NAND2_X4 inst_35 ( .ZN(net_89), .A1(net_64), .A2(net_17) ); 361 | INV_X4 inst_99 ( .A(net_49), .ZN(READY) ); 362 | NAND2_X2 inst_48 ( .ZN(net_43), .A1(net_42), .A2(READY) ); 363 | MUX2_X2 inst_69 ( .S(net_122), .Z(net_73), .B(net_28), .A(A2) ); 364 | NAND2_X2 inst_46 ( .ZN(net_37), .A1(net_36), .A2(READY) ); 365 | INV_X4 inst_82 ( .ZN(net_21), .A(net_5) ); 366 | DFFR_X2 inst_136 ( .RN(net_102), .D(net_99), .QN(net_1), .CK(net_140) ); 367 | NAND2_X4 inst_30 ( .A1(net_121), .ZN(net_29), .A2(net_28) ); 368 | INV_X4 inst_102 ( .ZN(net_46), .A(net_45) ); 369 | INV_X2 inst_108 ( .ZN(net_33), .A(net_7) ); 370 | CLKBUF_X2 inst_165 ( .A(net_153), .Z(net_154) ); 371 | NAND2_X4 inst_32 ( .ZN(net_129), .A1(net_45), .A2(net_15) ); 372 | NAND3_X2 inst_22 ( .A2(net_127), .A3(net_116), .A1(net_115), .ZN(net_95) ); 373 | CLKBUF_X2 inst_144 ( .A(net_131), .Z(net_133) ); 374 | NAND2_X4 inst_34 ( .ZN(net_119), .A2(net_68), .A1(net_47) ); 375 | NOR2_X2 inst_12 ( .ZN(net_78), .A1(net_25), .A2(READY) ); 376 | NAND2_X2 inst_56 ( .A2(net_128), .ZN(net_61), .A1(net_19) ); 377 | MUX2_X2 inst_71 ( .S(net_122), .Z(net_75), .B(net_30), .A(A0) ); 378 | NAND3_X2 inst_21 ( .A2(net_126), .ZN(net_93), .A3(net_91), .A1(net_71) ); 379 | INV_X4 inst_104 ( .ZN(net_67), .A(net_66) ); 380 | NAND2_X2 inst_60 ( .ZN(net_69), .A2(net_68), .A1(net_55) ); 381 | CLKBUF_X2 inst_169 ( .A(net_157), .Z(net_158) ); 382 | CLKBUF_X2 inst_168 ( .A(net_156), .Z(net_157) ); 383 | INV_X4 inst_97 ( .ZN(net_25), .A(net_23) ); 384 | CLKBUF_X2 inst_161 ( .A(net_149), .Z(net_150) ); 385 | DFFR_X2 inst_124 ( .RN(net_102), .D(net_72), .QN(net_7), .CK(net_182) ); 386 | NAND3_X2 inst_18 ( .ZN(net_122), .A2(net_18), .A3(net_10), .A1(net_9) ); 387 | NOR2_X2 inst_16 ( .ZN(net_86), .A2(net_79), .A1(START) ); 388 | INV_X4 inst_88 ( .ZN(net_15), .A(net_1) ); 389 | OR2_X4 inst_3 ( .ZN(net_41), .A2(READY), .A1(B2) ); 390 | CLKBUF_X2 inst_156 ( .A(net_144), .Z(net_145) ); 391 | NOR2_X2 inst_9 ( .A2(net_48), .A1(net_14), .ZN(CNTVCO2) ); 392 | INV_X2 inst_113 ( .A(net_36), .ZN(P3) ); 393 | CLKBUF_X2 inst_170 ( .A(net_158), .Z(net_159) ); 394 | NAND2_X2 inst_50 ( .ZN(net_55), .A1(net_54), .A2(net_31) ); 395 | DFFR_X2 inst_137 ( .RN(net_102), .D(net_101), .QN(net_3), .CK(net_137) ); 396 | NAND2_X4 inst_41 ( .A2(net_110), .ZN(net_106), .A1(net_97) ); 397 | DFFR_X2 inst_130 ( .RN(net_102), .D(net_83), .QN(net_11), .CK(net_160) ); 398 | INV_X4 inst_91 ( .A(net_24), .ZN(net_14) ); 399 | DFFR_X2 inst_132 ( .RN(net_102), .D(net_84), .QN(net_12), .CK(net_155) ); 400 | CLKBUF_X2 inst_143 ( .A(net_131), .Z(net_132) ); 401 | CLKBUF_X2 inst_176 ( .A(net_164), .Z(net_165) ); 402 | CLKBUF_X2 inst_152 ( .A(net_138), .Z(net_141) ); 403 | NAND2_X2 inst_58 ( .A2(net_128), .ZN(net_63), .A1(net_56) ); 404 | NAND2_X4 inst_36 ( .A2(net_129), .A1(net_119), .ZN(net_114) ); 405 | CLKBUF_X2 inst_147 ( .A(net_135), .Z(net_136) ); 406 | INV_X4 inst_87 ( .ZN(net_42), .A(net_11) ); 407 | NAND2_X2 inst_61 ( .A2(net_125), .ZN(net_76), .A1(net_42) ); 408 | NAND2_X2 inst_45 ( .A1(net_120), .ZN(net_34), .A2(READY) ); 409 | INV_X4 inst_96 ( .ZN(net_27), .A(net_9) ); 410 | INV_X4 inst_101 ( .ZN(net_52), .A(net_29) ); 411 | XNOR2_X2 inst_0 ( .ZN(net_77), .A(net_50), .B(net_24) ); 412 | CLKBUF_X2 inst_184 ( .A(net_142), .Z(net_173) ); 413 | NOR2_X2 inst_10 ( .ZN(net_50), .A1(net_48), .A2(READY) ); 414 | OR2_X4 inst_4 ( .ZN(net_44), .A2(READY), .A1(B1) ); 415 | NAND2_X2 inst_65 ( .ZN(net_110), .A2(net_94), .A1(net_67) ); 416 | CLKBUF_X2 inst_178 ( .A(net_166), .Z(net_167) ); 417 | INV_X4 inst_89 ( .ZN(net_54), .A(net_0) ); 418 | NAND2_X4 inst_28 ( .A2(net_121), .ZN(net_22), .A1(net_21) ); 419 | INV_X2 inst_111 ( .A(net_54), .ZN(P4) ); 420 | NAND2_X2 inst_66 ( .ZN(net_107), .A2(net_92), .A1(net_65) ); 421 | INV_X2 inst_117 ( .ZN(net_26), .A(net_25) ); 422 | INV_X4 inst_98 ( .ZN(net_32), .A(net_22) ); 423 | CLKBUF_X2 inst_190 ( .A(net_178), .Z(net_179) ); 424 | NAND2_X2 inst_63 ( .ZN(net_88), .A2(net_82), .A1(net_76) ); 425 | OR2_X2 inst_7 ( .A2(net_113), .ZN(net_91), .A1(net_81) ); 426 | CLKBUF_X2 inst_185 ( .A(net_173), .Z(net_174) ); 427 | CLKBUF_X2 inst_182 ( .A(net_170), .Z(net_171) ); 428 | NAND2_X2 inst_49 ( .ZN(net_47), .A1(net_32), .A2(net_1) ); 429 | INV_X2 inst_120 ( .ZN(net_117), .A(net_64) ); 430 | CLKBUF_X2 inst_154 ( .A(net_138), .Z(net_143) ); 431 | NOR2_X2 inst_13 ( .ZN(net_65), .A1(net_56), .A2(net_53) ); 432 | INV_X2 inst_119 ( .ZN(CNTVCON2), .A(CNTVCO2) ); 433 | INV_X8 inst_75 ( .A(net_128), .ZN(net_123) ); 434 | CLKBUF_X2 inst_192 ( .A(net_180), .Z(net_181) ); 435 | CLKBUF_X2 inst_166 ( .A(net_154), .Z(net_155) ); 436 | INV_X2 inst_116 ( .ZN(net_20), .A(P6) ); 437 | CLKBUF_X2 inst_163 ( .A(net_151), .Z(net_152) ); 438 | INV_X4 inst_85 ( .ZN(net_30), .A(net_4) ); 439 | NAND2_X2 inst_54 ( .ZN(net_59), .A1(net_40), .A2(net_37) ); 440 | INV_X4 inst_79 ( .ZN(net_36), .A(net_13) ); 441 | INV_X2 inst_109 ( .ZN(net_28), .A(net_6) ); 442 | INV_X2 inst_106 ( .A(net_128), .ZN(net_125) ); 443 | CLKBUF_X2 inst_193 ( .A(net_181), .Z(net_182) ); 444 | CLKBUF_X2 inst_149 ( .A(net_130), .Z(net_138) ); 445 | NAND2_X2 inst_43 ( .A2(net_121), .ZN(net_31), .A1(net_30) ); 446 | NAND2_X4 inst_39 ( .A2(net_111), .ZN(net_104), .A1(net_94) ); 447 | DFFR_X2 inst_128 ( .RN(net_102), .D(net_74), .QN(net_5), .CK(net_167) ); 448 | MUX2_X2 inst_73 ( .S(net_123), .Z(net_84), .A(net_58), .B(net_36) ); 449 | NAND3_X2 inst_23 ( .A2(net_100), .ZN(net_96), .A3(net_93), .A1(net_62) ); 450 | CLKBUF_X2 inst_171 ( .A(net_132), .Z(net_160) ); 451 | INV_X4 inst_77 ( .A(net_128), .ZN(net_124) ); 452 | INV_X4 inst_94 ( .A(net_17), .ZN(P6) ); 453 | 454 | endmodule 455 | -------------------------------------------------------------------------------- /benchmark/s386.v: -------------------------------------------------------------------------------- 1 | module s386 ( 2 | v4, 3 | v3, 4 | v5, 5 | v1, 6 | v0, 7 | blif_clk_net, 8 | v2, 9 | v6, 10 | blif_reset_net, 11 | v13_D_11, 12 | v13_D_6, 13 | v13_D_10, 14 | v13_D_12, 15 | v13_D_7, 16 | v13_D_8, 17 | v13_D_9); 18 | 19 | // Start PIs 20 | input v4; 21 | input v3; 22 | input v5; 23 | input v1; 24 | input v0; 25 | input blif_clk_net; 26 | input v2; 27 | input v6; 28 | input blif_reset_net; 29 | 30 | // Start POs 31 | output v13_D_11; 32 | output v13_D_6; 33 | output v13_D_10; 34 | output v13_D_12; 35 | output v13_D_7; 36 | output v13_D_8; 37 | output v13_D_9; 38 | 39 | // Start wires 40 | wire net_166; 41 | wire net_107; 42 | wire net_47; 43 | wire net_159; 44 | wire v13_D_7; 45 | wire net_61; 46 | wire net_137; 47 | wire net_132; 48 | wire net_54; 49 | wire net_105; 50 | wire net_62; 51 | wire net_6; 52 | wire net_129; 53 | wire net_119; 54 | wire net_98; 55 | wire net_23; 56 | wire net_117; 57 | wire net_12; 58 | wire net_151; 59 | wire net_74; 60 | wire v13_D_12; 61 | wire net_53; 62 | wire net_93; 63 | wire net_168; 64 | wire net_135; 65 | wire net_130; 66 | wire net_147; 67 | wire net_127; 68 | wire net_14; 69 | wire net_113; 70 | wire net_26; 71 | wire net_76; 72 | wire blif_clk_net; 73 | wire net_101; 74 | wire net_32; 75 | wire net_111; 76 | wire net_90; 77 | wire net_40; 78 | wire net_100; 79 | wire net_85; 80 | wire net_69; 81 | wire net_124; 82 | wire net_161; 83 | wire net_141; 84 | wire net_160; 85 | wire v1; 86 | wire net_83; 87 | wire net_115; 88 | wire v2; 89 | wire net_4; 90 | wire net_95; 91 | wire net_17; 92 | wire net_78; 93 | wire net_27; 94 | wire net_164; 95 | wire net_56; 96 | wire net_87; 97 | wire v13_D_11; 98 | wire net_0; 99 | wire net_155; 100 | wire net_35; 101 | wire v6; 102 | wire net_16; 103 | wire net_22; 104 | wire net_39; 105 | wire net_157; 106 | wire net_144; 107 | wire net_102; 108 | wire v3; 109 | wire net_2; 110 | wire net_59; 111 | wire net_9; 112 | wire net_42; 113 | wire net_120; 114 | wire net_109; 115 | wire net_80; 116 | wire net_65; 117 | wire blif_reset_net; 118 | wire net_50; 119 | wire net_162; 120 | wire net_96; 121 | wire net_66; 122 | wire net_38; 123 | wire net_44; 124 | wire net_167; 125 | wire net_136; 126 | wire net_134; 127 | wire net_19; 128 | wire net_89; 129 | wire net_45; 130 | wire net_126; 131 | wire net_34; 132 | wire net_108; 133 | wire v13_D_6; 134 | wire net_150; 135 | wire net_63; 136 | wire net_152; 137 | wire net_116; 138 | wire net_30; 139 | wire net_91; 140 | wire net_24; 141 | wire net_55; 142 | wire net_99; 143 | wire net_106; 144 | wire net_46; 145 | wire net_140; 146 | wire net_118; 147 | wire net_148; 148 | wire net_104; 149 | wire net_146; 150 | wire v13_D_8; 151 | wire net_72; 152 | wire net_122; 153 | wire net_25; 154 | wire v0; 155 | wire net_7; 156 | wire net_70; 157 | wire net_5; 158 | wire net_52; 159 | wire net_165; 160 | wire net_128; 161 | wire v5; 162 | wire net_138; 163 | wire net_13; 164 | wire net_94; 165 | wire net_11; 166 | wire net_18; 167 | wire net_123; 168 | wire net_131; 169 | wire net_114; 170 | wire net_29; 171 | wire net_68; 172 | wire net_149; 173 | wire net_142; 174 | wire v13_D_10; 175 | wire net_77; 176 | wire net_20; 177 | wire net_31; 178 | wire net_36; 179 | wire net_49; 180 | wire net_158; 181 | wire v4; 182 | wire net_15; 183 | wire net_41; 184 | wire net_57; 185 | wire net_71; 186 | wire net_153; 187 | wire net_156; 188 | wire net_3; 189 | wire net_84; 190 | wire net_154; 191 | wire net_1; 192 | wire net_92; 193 | wire net_112; 194 | wire net_103; 195 | wire net_139; 196 | wire net_43; 197 | wire net_10; 198 | wire net_28; 199 | wire net_169; 200 | wire net_21; 201 | wire net_51; 202 | wire net_79; 203 | wire net_143; 204 | wire net_97; 205 | wire net_88; 206 | wire net_145; 207 | wire net_60; 208 | wire net_81; 209 | wire net_163; 210 | wire net_58; 211 | wire v13_D_9; 212 | wire net_67; 213 | wire net_82; 214 | wire net_64; 215 | wire net_37; 216 | wire net_110; 217 | wire net_121; 218 | wire net_73; 219 | wire net_33; 220 | wire net_48; 221 | wire net_8; 222 | wire net_75; 223 | wire net_86; 224 | wire net_133; 225 | wire net_125; 226 | 227 | // Start cells 228 | DFFR_X2 inst_145 ( .QN(net_146), .RN(net_97), .D(net_90), .CK(net_165) ); 229 | INV_X4 inst_103 ( .ZN(net_43), .A(v1) ); 230 | INV_X4 inst_125 ( .ZN(net_24), .A(net_19) ); 231 | INV_X2 inst_138 ( .A(net_133), .ZN(net_132) ); 232 | CLKBUF_X2 inst_159 ( .A(net_151), .Z(net_152) ); 233 | NOR2_X2 inst_15 ( .A2(net_139), .ZN(net_13), .A1(net_12) ); 234 | INV_X4 inst_134 ( .ZN(net_94), .A(net_87) ); 235 | NAND4_X2 inst_24 ( .A3(net_74), .ZN(net_64), .A2(net_63), .A4(net_62), .A1(net_2) ); 236 | INV_X4 inst_114 ( .A(net_143), .ZN(net_14) ); 237 | NOR4_X2 inst_6 ( .A3(net_75), .A4(net_73), .A2(net_40), .A1(net_17), .ZN(v13_D_9) ); 238 | INV_X4 inst_131 ( .A(net_46), .ZN(net_32) ); 239 | NAND2_X2 inst_76 ( .A2(net_142), .ZN(net_122), .A1(net_51) ); 240 | CLKBUF_X2 inst_160 ( .A(net_152), .Z(net_153) ); 241 | AND4_X2 inst_150 ( .A3(net_146), .A4(net_129), .ZN(net_44), .A2(net_43), .A1(v4) ); 242 | NAND3_X2 inst_33 ( .ZN(net_102), .A2(net_74), .A1(net_68), .A3(net_65) ); 243 | CLKBUF_X2 inst_172 ( .A(net_164), .Z(net_165) ); 244 | NAND2_X2 inst_83 ( .A1(net_111), .ZN(net_78), .A2(net_31) ); 245 | NAND2_X4 inst_47 ( .ZN(net_85), .A2(net_31), .A1(net_24) ); 246 | NOR2_X2 inst_19 ( .ZN(net_49), .A1(net_23), .A2(net_14) ); 247 | INV_X4 inst_123 ( .ZN(net_25), .A(net_18) ); 248 | INV_X4 inst_121 ( .ZN(net_15), .A(net_14) ); 249 | OR2_X2 inst_2 ( .A2(net_147), .A1(net_143), .ZN(net_9) ); 250 | NOR3_X2 inst_8 ( .ZN(net_119), .A3(net_116), .A2(net_114), .A1(net_49) ); 251 | INV_X4 inst_118 ( .ZN(net_77), .A(net_75) ); 252 | NAND2_X2 inst_86 ( .ZN(net_110), .A2(net_72), .A1(net_52) ); 253 | AND2_X4 inst_153 ( .A2(net_148), .A1(net_147), .ZN(net_6) ); 254 | NOR2_X2 inst_20 ( .A1(net_132), .ZN(net_59), .A2(net_41) ); 255 | NAND3_X4 inst_27 ( .ZN(net_90), .A2(net_88), .A1(net_82), .A3(net_66) ); 256 | NAND3_X2 inst_38 ( .ZN(net_130), .A1(net_67), .A3(net_37), .A2(net_33) ); 257 | INV_X4 inst_100 ( .A(net_134), .ZN(net_133) ); 258 | NAND2_X4 inst_52 ( .A1(net_112), .ZN(net_106), .A2(net_68) ); 259 | NAND2_X2 inst_90 ( .A2(net_121), .A1(net_120), .ZN(net_112) ); 260 | INV_X2 inst_140 ( .ZN(net_0), .A(v2) ); 261 | NAND3_X2 inst_40 ( .ZN(net_81), .A3(net_48), .A2(net_39), .A1(net_30) ); 262 | CLKBUF_X2 inst_162 ( .A(net_154), .Z(net_155) ); 263 | CLKBUF_X2 inst_167 ( .A(blif_clk_net), .Z(net_160) ); 264 | NAND2_X2 inst_93 ( .A2(net_100), .A1(net_80), .ZN(v13_D_11) ); 265 | NAND2_X2 inst_81 ( .ZN(net_72), .A1(net_71), .A2(net_57) ); 266 | INV_X4 inst_95 ( .A(net_144), .ZN(net_138) ); 267 | OR2_X4 inst_1 ( .ZN(net_28), .A1(net_27), .A2(net_26) ); 268 | NAND2_X2 inst_72 ( .ZN(net_55), .A1(net_54), .A2(net_53) ); 269 | INV_X2 inst_139 ( .A(net_117), .ZN(net_116) ); 270 | AND2_X2 inst_155 ( .ZN(net_124), .A2(net_31), .A1(v1) ); 271 | NAND2_X2 inst_59 ( .ZN(net_141), .A1(net_19), .A2(net_7) ); 272 | INV_X4 inst_135 ( .ZN(net_95), .A(net_93) ); 273 | NAND3_X2 inst_44 ( .A1(net_103), .ZN(net_96), .A3(net_92), .A2(net_91) ); 274 | NAND2_X2 inst_55 ( .ZN(net_140), .A1(net_131), .A2(v2) ); 275 | CLKBUF_X2 inst_174 ( .A(net_166), .Z(net_167) ); 276 | INV_X4 inst_115 ( .A(net_146), .ZN(net_16) ); 277 | NAND3_X2 inst_37 ( .A2(net_147), .A1(net_105), .ZN(net_67), .A3(v4) ); 278 | DFFR_X2 inst_148 ( .QN(net_147), .RN(net_97), .D(net_95), .CK(net_156) ); 279 | CLKBUF_X2 inst_164 ( .A(net_154), .Z(net_157) ); 280 | NOR4_X2 inst_5 ( .A2(net_77), .A1(net_76), .A3(net_63), .ZN(v13_D_12), .A4(v0) ); 281 | CLKBUF_X2 inst_157 ( .A(net_149), .Z(net_150) ); 282 | NAND2_X2 inst_84 ( .A1(net_122), .ZN(net_109), .A2(net_71) ); 283 | NAND2_X4 inst_51 ( .A1(net_126), .ZN(net_120), .A2(net_31) ); 284 | INV_X2 inst_142 ( .ZN(net_40), .A(net_39) ); 285 | NAND2_X2 inst_80 ( .ZN(net_88), .A1(net_74), .A2(net_56) ); 286 | CLKBUF_X2 inst_173 ( .A(net_155), .Z(net_166) ); 287 | INV_X4 inst_105 ( .A(net_148), .ZN(net_34) ); 288 | NAND2_X2 inst_68 ( .ZN(net_121), .A2(net_65), .A1(v1) ); 289 | NAND2_X2 inst_78 ( .A1(net_134), .ZN(net_70), .A2(net_42) ); 290 | NAND3_X2 inst_42 ( .A1(net_110), .A3(net_92), .A2(net_91), .ZN(net_87) ); 291 | CLKBUF_X2 inst_175 ( .A(net_167), .Z(net_168) ); 292 | NAND2_X2 inst_53 ( .A2(net_145), .ZN(net_3), .A1(v1) ); 293 | INV_X4 inst_133 ( .A(net_85), .ZN(net_56) ); 294 | NAND4_X2 inst_26 ( .A4(net_102), .A1(net_101), .ZN(net_89), .A3(net_88), .A2(net_64) ); 295 | AND4_X2 inst_151 ( .A1(net_75), .A4(net_62), .A3(net_47), .ZN(v13_D_10), .A2(v1) ); 296 | INV_X4 inst_112 ( .ZN(net_75), .A(net_5) ); 297 | NAND2_X2 inst_64 ( .A2(net_143), .A1(net_140), .ZN(net_105) ); 298 | INV_X4 inst_107 ( .ZN(net_12), .A(v3) ); 299 | NAND2_X2 inst_67 ( .ZN(net_45), .A2(net_25), .A1(net_16) ); 300 | INV_X4 inst_127 ( .ZN(net_65), .A(net_36) ); 301 | NAND2_X2 inst_70 ( .A2(net_129), .ZN(net_48), .A1(net_28) ); 302 | INV_X4 inst_129 ( .ZN(net_38), .A(net_24) ); 303 | NAND2_X2 inst_92 ( .ZN(net_100), .A2(net_99), .A1(net_77) ); 304 | NAND3_X2 inst_29 ( .A2(net_136), .ZN(net_21), .A3(net_6), .A1(net_1) ); 305 | NOR2_X2 inst_17 ( .A1(net_147), .ZN(net_54), .A2(net_31) ); 306 | NOR2_X4 inst_11 ( .A1(net_131), .ZN(net_129), .A2(v3) ); 307 | DFFR_X2 inst_146 ( .QN(net_145), .RN(net_97), .D(net_89), .CK(net_161) ); 308 | NOR2_X2 inst_14 ( .A2(net_143), .ZN(net_125), .A1(net_63) ); 309 | INV_X4 inst_122 ( .ZN(net_68), .A(net_16) ); 310 | NAND3_X2 inst_31 ( .ZN(net_37), .A1(net_13), .A3(net_10), .A2(net_9) ); 311 | NAND4_X2 inst_25 ( .A2(net_115), .ZN(net_107), .A1(net_65), .A4(net_31), .A3(v0) ); 312 | INV_X4 inst_126 ( .A(net_147), .ZN(net_22) ); 313 | CLKBUF_X2 inst_158 ( .A(net_150), .Z(net_151) ); 314 | INV_X2 inst_141 ( .A(net_71), .ZN(net_17) ); 315 | NAND2_X2 inst_62 ( .A2(net_125), .A1(net_114), .ZN(net_33) ); 316 | INV_X4 inst_110 ( .ZN(net_5), .A(net_2) ); 317 | NAND2_X2 inst_74 ( .ZN(net_57), .A1(net_35), .A2(net_21) ); 318 | NAND2_X2 inst_57 ( .ZN(net_11), .A2(net_3), .A1(v0) ); 319 | NAND3_X2 inst_35 ( .A3(net_65), .ZN(net_60), .A2(net_54), .A1(v5) ); 320 | INV_X4 inst_99 ( .A(net_135), .ZN(net_134) ); 321 | NAND2_X4 inst_48 ( .A1(net_118), .ZN(net_113), .A2(net_85) ); 322 | NAND2_X2 inst_69 ( .ZN(net_47), .A1(net_46), .A2(net_4) ); 323 | NAND2_X4 inst_46 ( .A2(net_143), .A1(net_139), .ZN(net_36) ); 324 | NAND2_X2 inst_82 ( .ZN(net_126), .A2(net_70), .A1(net_43) ); 325 | INV_X4 inst_136 ( .ZN(net_98), .A(net_96) ); 326 | NAND3_X2 inst_30 ( .A1(net_147), .A2(net_129), .ZN(net_117), .A3(net_26) ); 327 | INV_X4 inst_102 ( .ZN(net_63), .A(v5) ); 328 | INV_X4 inst_108 ( .A(net_145), .ZN(net_2) ); 329 | CLKBUF_X2 inst_165 ( .A(net_157), .Z(net_158) ); 330 | NAND3_X2 inst_32 ( .A1(net_147), .ZN(net_142), .A2(net_135), .A3(net_34) ); 331 | NOR2_X2 inst_22 ( .A2(net_116), .ZN(net_79), .A1(net_59) ); 332 | DFFR_X2 inst_144 ( .QN(net_143), .RN(net_97), .D(net_86), .CK(net_169) ); 333 | NAND3_X2 inst_34 ( .A1(net_133), .ZN(net_50), .A3(net_18), .A2(v2) ); 334 | NOR2_X4 inst_12 ( .A2(net_146), .ZN(net_115), .A1(net_22) ); 335 | NAND2_X2 inst_56 ( .A2(net_143), .ZN(net_10), .A1(v2) ); 336 | NAND2_X2 inst_71 ( .ZN(net_76), .A2(net_62), .A1(net_46) ); 337 | NOR2_X2 inst_21 ( .ZN(net_73), .A1(net_69), .A2(net_44) ); 338 | INV_X4 inst_104 ( .ZN(net_74), .A(v0) ); 339 | NAND2_X2 inst_60 ( .A1(net_31), .ZN(net_29), .A2(net_5) ); 340 | CLKBUF_X2 inst_169 ( .A(net_155), .Z(net_162) ); 341 | CLKBUF_X2 inst_168 ( .A(net_160), .Z(net_161) ); 342 | INV_X4 inst_97 ( .A(net_138), .ZN(net_137) ); 343 | CLKBUF_X2 inst_161 ( .A(net_153), .Z(net_154) ); 344 | INV_X4 inst_124 ( .A(net_68), .ZN(net_46) ); 345 | NOR2_X2 inst_18 ( .ZN(net_62), .A2(net_36), .A1(net_8) ); 346 | NOR2_X2 inst_16 ( .ZN(net_53), .A1(net_36), .A2(v5) ); 347 | NAND2_X2 inst_88 ( .A1(net_130), .ZN(net_108), .A2(net_31) ); 348 | OR2_X2 inst_3 ( .ZN(net_52), .A2(net_51), .A1(net_15) ); 349 | CLKBUF_X2 inst_156 ( .A(blif_clk_net), .Z(net_149) ); 350 | NOR3_X2 inst_9 ( .A1(net_119), .ZN(net_86), .A3(net_85), .A2(net_84) ); 351 | INV_X4 inst_113 ( .ZN(net_8), .A(net_6) ); 352 | CLKBUF_X2 inst_170 ( .A(net_162), .Z(net_163) ); 353 | NAND2_X4 inst_50 ( .A2(net_124), .A1(net_123), .ZN(net_82) ); 354 | INV_X2 inst_137 ( .A(net_137), .ZN(net_136) ); 355 | NAND3_X2 inst_41 ( .ZN(net_104), .A1(net_78), .A3(net_55), .A2(net_50) ); 356 | INV_X4 inst_130 ( .ZN(net_39), .A(net_25) ); 357 | NAND2_X2 inst_91 ( .A2(net_107), .A1(net_106), .ZN(net_99) ); 358 | INV_X4 inst_132 ( .ZN(net_92), .A(net_38) ); 359 | INV_X1 inst_143 ( .ZN(net_97), .A(blif_reset_net) ); 360 | CLKBUF_X2 inst_176 ( .A(net_168), .Z(net_169) ); 361 | AND3_X1 inst_152 ( .A1(net_92), .A2(net_91), .A3(net_83), .ZN(v13_D_6) ); 362 | NAND2_X2 inst_58 ( .A2(net_146), .A1(net_145), .ZN(net_19) ); 363 | NAND3_X2 inst_36 ( .ZN(net_66), .A2(net_65), .A1(net_45), .A3(net_11) ); 364 | DFFR_X2 inst_147 ( .QN(net_148), .RN(net_97), .D(net_94), .CK(net_151) ); 365 | NAND2_X2 inst_87 ( .ZN(net_83), .A2(net_81), .A1(net_60) ); 366 | NAND2_X2 inst_61 ( .A1(net_71), .ZN(net_30), .A2(net_0) ); 367 | NAND2_X4 inst_45 ( .ZN(net_7), .A1(net_6), .A2(v0) ); 368 | INV_X4 inst_96 ( .ZN(net_139), .A(net_138) ); 369 | INV_X4 inst_101 ( .A(net_138), .ZN(net_131) ); 370 | OR2_X4 inst_0 ( .A1(net_147), .A2(net_143), .ZN(net_41) ); 371 | NOR3_X2 inst_10 ( .A1(net_85), .A2(net_84), .A3(net_79), .ZN(v13_D_7) ); 372 | NOR4_X2 inst_4 ( .A1(net_76), .A2(net_75), .A3(net_74), .ZN(v13_D_8), .A4(v6) ); 373 | NAND2_X2 inst_65 ( .A2(net_114), .ZN(net_35), .A1(net_34) ); 374 | NAND2_X2 inst_89 ( .A2(net_109), .A1(net_108), .ZN(net_103) ); 375 | NAND3_X2 inst_28 ( .A3(net_147), .A1(net_26), .ZN(net_20), .A2(net_12) ); 376 | INV_X4 inst_111 ( .A(net_34), .ZN(net_31) ); 377 | NAND2_X2 inst_66 ( .ZN(net_42), .A1(net_41), .A2(net_20) ); 378 | INV_X4 inst_117 ( .ZN(net_27), .A(net_14) ); 379 | INV_X4 inst_98 ( .A(net_136), .ZN(net_135) ); 380 | NAND2_X2 inst_63 ( .A2(net_128), .A1(net_127), .ZN(net_51) ); 381 | NOR3_X2 inst_7 ( .A1(net_132), .A2(net_74), .ZN(net_69), .A3(net_68) ); 382 | NAND2_X4 inst_49 ( .A1(net_113), .ZN(net_101), .A2(v1) ); 383 | INV_X4 inst_120 ( .ZN(net_91), .A(net_84) ); 384 | AND2_X2 inst_154 ( .ZN(net_1), .A2(v2), .A1(v3) ); 385 | NOR2_X2 inst_13 ( .A1(net_147), .A2(net_138), .ZN(net_114) ); 386 | INV_X4 inst_119 ( .ZN(net_71), .A(net_14) ); 387 | NAND2_X2 inst_75 ( .ZN(net_58), .A1(net_36), .A2(net_29) ); 388 | CLKBUF_X2 inst_166 ( .A(net_158), .Z(net_159) ); 389 | INV_X4 inst_116 ( .ZN(net_18), .A(net_8) ); 390 | CLKBUF_X2 inst_163 ( .A(net_155), .Z(net_156) ); 391 | NAND2_X2 inst_85 ( .ZN(net_123), .A2(net_61), .A1(net_38) ); 392 | NAND2_X2 inst_54 ( .ZN(net_84), .A2(net_43), .A1(v0) ); 393 | NAND2_X2 inst_79 ( .A1(net_117), .ZN(net_111), .A2(net_27) ); 394 | INV_X4 inst_109 ( .ZN(net_128), .A(net_34) ); 395 | INV_X4 inst_106 ( .ZN(net_26), .A(v4) ); 396 | DFFR_X2 inst_149 ( .QN(net_144), .D(net_98), .RN(net_97), .CK(net_159) ); 397 | NAND3_X2 inst_43 ( .A1(net_104), .ZN(net_93), .A3(net_92), .A2(net_91) ); 398 | NAND3_X2 inst_39 ( .ZN(net_80), .A2(net_74), .A3(net_58), .A1(net_32) ); 399 | INV_X4 inst_128 ( .ZN(net_23), .A(net_22) ); 400 | NAND2_X2 inst_73 ( .A1(net_141), .ZN(net_118), .A2(net_65) ); 401 | NOR2_X1 inst_23 ( .A2(net_147), .A1(net_137), .ZN(net_127) ); 402 | CLKBUF_X2 inst_171 ( .A(net_163), .Z(net_164) ); 403 | NAND2_X2 inst_77 ( .A1(net_115), .ZN(net_61), .A2(net_53) ); 404 | NAND2_X1 inst_94 ( .ZN(net_4), .A2(v0), .A1(v5) ); 405 | 406 | endmodule 407 | -------------------------------------------------------------------------------- /benchmark/s400.v: -------------------------------------------------------------------------------- 1 | module s400 ( 2 | TEST, 3 | FM, 4 | blif_clk_net, 5 | CLR, 6 | blif_reset_net, 7 | YLW1, 8 | RED2, 9 | GRN1, 10 | RED1, 11 | YLW2, 12 | GRN2); 13 | 14 | // Start PIs 15 | input TEST; 16 | input FM; 17 | input blif_clk_net; 18 | input CLR; 19 | input blif_reset_net; 20 | 21 | // Start POs 22 | output YLW1; 23 | output RED2; 24 | output GRN1; 25 | output RED1; 26 | output YLW2; 27 | output GRN2; 28 | 29 | // Start wires 30 | wire net_166; 31 | wire net_107; 32 | wire net_47; 33 | wire net_179; 34 | wire GRN1; 35 | wire net_176; 36 | wire net_159; 37 | wire net_61; 38 | wire net_137; 39 | wire net_132; 40 | wire net_54; 41 | wire net_105; 42 | wire net_62; 43 | wire net_6; 44 | wire net_129; 45 | wire net_119; 46 | wire net_98; 47 | wire net_23; 48 | wire net_117; 49 | wire net_12; 50 | wire net_151; 51 | wire net_74; 52 | wire net_53; 53 | wire net_93; 54 | wire net_210; 55 | wire net_205; 56 | wire net_168; 57 | wire net_135; 58 | wire net_130; 59 | wire net_147; 60 | wire net_127; 61 | wire net_14; 62 | wire net_113; 63 | wire net_26; 64 | wire net_76; 65 | wire blif_clk_net; 66 | wire net_101; 67 | wire net_32; 68 | wire net_187; 69 | wire net_111; 70 | wire net_90; 71 | wire net_40; 72 | wire net_100; 73 | wire net_85; 74 | wire net_69; 75 | wire net_124; 76 | wire net_161; 77 | wire CLR; 78 | wire net_141; 79 | wire net_160; 80 | wire net_83; 81 | wire net_115; 82 | wire RED1; 83 | wire net_4; 84 | wire net_95; 85 | wire net_17; 86 | wire net_173; 87 | wire net_78; 88 | wire net_27; 89 | wire net_164; 90 | wire net_56; 91 | wire net_87; 92 | wire net_0; 93 | wire net_155; 94 | wire net_35; 95 | wire net_191; 96 | wire net_16; 97 | wire net_22; 98 | wire net_181; 99 | wire net_193; 100 | wire net_39; 101 | wire net_157; 102 | wire net_144; 103 | wire net_102; 104 | wire net_2; 105 | wire net_59; 106 | wire net_9; 107 | wire net_42; 108 | wire net_120; 109 | wire net_201; 110 | wire net_109; 111 | wire net_80; 112 | wire net_65; 113 | wire blif_reset_net; 114 | wire net_50; 115 | wire net_162; 116 | wire YLW1; 117 | wire FM; 118 | wire net_96; 119 | wire net_66; 120 | wire net_38; 121 | wire net_44; 122 | wire net_167; 123 | wire net_207; 124 | wire net_199; 125 | wire net_136; 126 | wire net_134; 127 | wire net_19; 128 | wire net_89; 129 | wire net_45; 130 | wire net_126; 131 | wire net_185; 132 | wire net_34; 133 | wire net_108; 134 | wire net_183; 135 | wire TEST; 136 | wire net_178; 137 | wire net_208; 138 | wire net_150; 139 | wire net_63; 140 | wire net_212; 141 | wire net_152; 142 | wire net_30; 143 | wire net_116; 144 | wire net_189; 145 | wire net_175; 146 | wire net_91; 147 | wire net_24; 148 | wire net_55; 149 | wire net_99; 150 | wire net_106; 151 | wire net_186; 152 | wire net_46; 153 | wire net_140; 154 | wire net_118; 155 | wire net_148; 156 | wire net_104; 157 | wire net_146; 158 | wire net_72; 159 | wire net_122; 160 | wire net_25; 161 | wire net_7; 162 | wire net_70; 163 | wire net_194; 164 | wire net_172; 165 | wire net_5; 166 | wire net_52; 167 | wire net_165; 168 | wire net_128; 169 | wire net_138; 170 | wire net_13; 171 | wire net_184; 172 | wire net_94; 173 | wire net_11; 174 | wire net_18; 175 | wire net_123; 176 | wire net_131; 177 | wire net_114; 178 | wire net_196; 179 | wire net_170; 180 | wire net_29; 181 | wire net_68; 182 | wire net_214; 183 | wire net_149; 184 | wire net_142; 185 | wire net_77; 186 | wire net_20; 187 | wire net_31; 188 | wire net_36; 189 | wire net_49; 190 | wire net_158; 191 | wire net_15; 192 | wire net_41; 193 | wire net_57; 194 | wire net_198; 195 | wire net_71; 196 | wire net_209; 197 | wire net_153; 198 | wire net_156; 199 | wire net_3; 200 | wire net_84; 201 | wire net_174; 202 | wire net_154; 203 | wire net_1; 204 | wire net_92; 205 | wire net_112; 206 | wire net_103; 207 | wire net_213; 208 | wire net_139; 209 | wire net_43; 210 | wire YLW2; 211 | wire net_10; 212 | wire net_180; 213 | wire net_28; 214 | wire net_169; 215 | wire net_21; 216 | wire net_51; 217 | wire net_171; 218 | wire net_79; 219 | wire net_143; 220 | wire net_97; 221 | wire net_190; 222 | wire net_88; 223 | wire net_182; 224 | wire net_192; 225 | wire net_145; 226 | wire net_60; 227 | wire net_197; 228 | wire net_204; 229 | wire net_81; 230 | wire RED2; 231 | wire net_163; 232 | wire net_58; 233 | wire GRN2; 234 | wire net_67; 235 | wire net_82; 236 | wire net_64; 237 | wire net_202; 238 | wire net_37; 239 | wire net_188; 240 | wire net_110; 241 | wire net_121; 242 | wire net_73; 243 | wire net_200; 244 | wire net_48; 245 | wire net_33; 246 | wire net_177; 247 | wire net_8; 248 | wire net_75; 249 | wire net_86; 250 | wire net_211; 251 | wire net_133; 252 | wire net_206; 253 | wire net_203; 254 | wire net_195; 255 | wire net_125; 256 | 257 | // Start cells 258 | AND4_X4 inst_145 ( .ZN(net_86), .A1(net_80), .A4(net_73), .A2(net_47), .A3(net_37) ); 259 | INV_X2 inst_103 ( .A(net_136), .ZN(net_135) ); 260 | DFFR_X2 inst_125 ( .RN(net_118), .D(net_43), .QN(net_6), .CK(net_209) ); 261 | CLKBUF_X2 inst_207 ( .A(net_172), .Z(net_201) ); 262 | DFFR_X1 inst_138 ( .RN(net_118), .D(net_97), .QN(RED2), .CK(net_177) ); 263 | CLKBUF_X2 inst_159 ( .A(net_152), .Z(net_153) ); 264 | CLKBUF_X2 inst_218 ( .A(net_211), .Z(net_212) ); 265 | NOR3_X2 inst_15 ( .A1(net_132), .A2(net_112), .ZN(net_75), .A3(net_54) ); 266 | CLKBUF_X2 inst_197 ( .A(net_190), .Z(net_191) ); 267 | DFFR_X1 inst_134 ( .RN(net_118), .D(net_72), .Q(YLW2), .CK(net_200) ); 268 | CLKBUF_X2 inst_179 ( .A(net_172), .Z(net_173) ); 269 | NOR2_X4 inst_24 ( .A1(net_130), .ZN(net_100), .A2(net_29) ); 270 | INV_X2 inst_114 ( .ZN(net_15), .A(net_10) ); 271 | XNOR2_X1 inst_6 ( .ZN(net_101), .A(net_100), .B(net_99) ); 272 | CLKBUF_X2 inst_194 ( .A(net_187), .Z(net_188) ); 273 | DFFR_X2 inst_131 ( .RN(net_118), .D(net_103), .QN(net_12), .CK(net_173) ); 274 | NAND2_X2 inst_76 ( .A1(net_141), .ZN(net_110), .A2(net_109) ); 275 | CLKBUF_X2 inst_214 ( .A(net_207), .Z(net_208) ); 276 | CLKBUF_X2 inst_180 ( .A(net_145), .Z(net_174) ); 277 | CLKBUF_X2 inst_160 ( .A(net_153), .Z(net_154) ); 278 | CLKBUF_X2 inst_150 ( .A(blif_clk_net), .Z(net_144) ); 279 | NOR2_X2 inst_33 ( .A1(net_126), .A2(net_76), .ZN(net_69) ); 280 | CLKBUF_X2 inst_172 ( .A(net_165), .Z(net_166) ); 281 | INV_X4 inst_83 ( .ZN(net_16), .A(net_0) ); 282 | NAND3_X2 inst_47 ( .ZN(net_102), .A1(net_100), .A2(net_99), .A3(net_66) ); 283 | NOR3_X2 inst_19 ( .ZN(net_105), .A3(net_104), .A1(net_90), .A2(net_83) ); 284 | INV_X1 inst_123 ( .ZN(net_118), .A(blif_reset_net) ); 285 | INV_X2 inst_121 ( .A(net_100), .ZN(net_93) ); 286 | XNOR2_X2 inst_2 ( .ZN(net_54), .A(net_53), .B(net_40) ); 287 | OR3_X2 inst_8 ( .A2(net_66), .ZN(net_50), .A1(net_49), .A3(net_48) ); 288 | INV_X2 inst_118 ( .ZN(net_33), .A(net_32) ); 289 | INV_X4 inst_86 ( .ZN(net_29), .A(net_16) ); 290 | CLKBUF_X2 inst_153 ( .A(net_145), .Z(net_147) ); 291 | NOR3_X2 inst_20 ( .ZN(net_106), .A3(net_104), .A1(net_94), .A2(net_89) ); 292 | NOR2_X2 inst_27 ( .ZN(net_80), .A1(net_2), .A2(CLR) ); 293 | NOR2_X2 inst_38 ( .A2(net_129), .ZN(net_92), .A1(net_56) ); 294 | INV_X4 inst_100 ( .ZN(net_112), .A(net_109) ); 295 | NAND2_X4 inst_52 ( .ZN(net_136), .A1(net_131), .A2(net_70) ); 296 | INV_X4 inst_90 ( .ZN(net_58), .A(net_19) ); 297 | DFFR_X1 inst_140 ( .RN(net_118), .D(net_107), .QN(net_9), .CK(net_160) ); 298 | CLKBUF_X2 inst_209 ( .A(net_202), .Z(net_203) ); 299 | CLKBUF_X2 inst_211 ( .A(net_189), .Z(net_205) ); 300 | NOR2_X1 inst_40 ( .A2(net_90), .ZN(net_89), .A1(net_88) ); 301 | CLKBUF_X2 inst_162 ( .A(net_155), .Z(net_156) ); 302 | CLKBUF_X2 inst_167 ( .A(net_155), .Z(net_161) ); 303 | INV_X4 inst_93 ( .ZN(net_99), .A(net_1) ); 304 | INV_X4 inst_81 ( .ZN(net_70), .A(net_12) ); 305 | INV_X4 inst_95 ( .A(net_57), .ZN(net_45) ); 306 | XNOR2_X2 inst_1 ( .A(net_51), .ZN(net_30), .B(FM) ); 307 | NAND2_X2 inst_72 ( .A2(net_128), .ZN(net_104), .A1(net_45) ); 308 | DFFR_X1 inst_139 ( .RN(net_118), .D(net_96), .QN(YLW1), .CK(net_146) ); 309 | CLKBUF_X2 inst_155 ( .A(net_148), .Z(net_149) ); 310 | NAND2_X2 inst_59 ( .ZN(net_48), .A1(net_16), .A2(net_1) ); 311 | DFFR_X1 inst_135 ( .RN(net_118), .D(net_79), .Q(RED1), .CK(net_193) ); 312 | CLKBUF_X2 inst_196 ( .A(net_189), .Z(net_190) ); 313 | NAND3_X2 inst_44 ( .A3(net_80), .A2(net_58), .A1(net_51), .ZN(net_41) ); 314 | NAND2_X4 inst_55 ( .A1(net_125), .ZN(net_98), .A2(net_28) ); 315 | CLKBUF_X2 inst_174 ( .A(net_167), .Z(net_168) ); 316 | INV_X2 inst_115 ( .ZN(net_88), .A(net_10) ); 317 | NOR2_X2 inst_37 ( .A1(net_130), .ZN(net_125), .A2(net_1) ); 318 | CLKBUF_X2 inst_210 ( .A(net_203), .Z(net_204) ); 319 | AND2_X2 inst_148 ( .ZN(net_53), .A2(net_34), .A1(net_26) ); 320 | CLKBUF_X2 inst_164 ( .A(net_157), .Z(net_158) ); 321 | CLKBUF_X2 inst_191 ( .A(net_184), .Z(net_185) ); 322 | XNOR2_X2 inst_5 ( .ZN(net_108), .A(net_102), .B(net_58) ); 323 | CLKBUF_X2 inst_157 ( .A(net_150), .Z(net_151) ); 324 | INV_X4 inst_84 ( .ZN(net_66), .A(net_2) ); 325 | NAND2_X4 inst_51 ( .A2(net_140), .ZN(net_137), .A1(net_131) ); 326 | DFFR_X1 inst_142 ( .RN(net_118), .D(net_114), .QN(net_0), .CK(net_154) ); 327 | INV_X4 inst_80 ( .ZN(net_49), .A(net_5) ); 328 | CLKBUF_X2 inst_173 ( .A(net_166), .Z(net_167) ); 329 | INV_X2 inst_105 ( .A(net_133), .ZN(net_132) ); 330 | CLKBUF_X2 inst_213 ( .A(net_206), .Z(net_207) ); 331 | NAND2_X2 inst_68 ( .ZN(net_84), .A1(net_81), .A2(net_67) ); 332 | CLKBUF_X2 inst_216 ( .A(net_195), .Z(net_210) ); 333 | INV_X4 inst_78 ( .ZN(net_87), .A(net_9) ); 334 | NAND4_X2 inst_42 ( .A1(net_66), .ZN(net_63), .A4(net_62), .A2(net_51), .A3(net_17) ); 335 | CLKBUF_X2 inst_175 ( .A(net_168), .Z(net_169) ); 336 | NAND2_X4 inst_53 ( .A2(net_137), .A1(net_136), .ZN(net_119) ); 337 | CLKBUF_X2 inst_205 ( .A(net_156), .Z(net_199) ); 338 | CLKBUF_X2 inst_177 ( .A(net_170), .Z(net_171) ); 339 | CLKBUF_X2 inst_183 ( .A(net_176), .Z(net_177) ); 340 | DFFR_X2 inst_133 ( .RN(net_118), .D(net_106), .QN(net_10), .CK(net_164) ); 341 | NOR2_X2 inst_26 ( .ZN(net_81), .A1(net_5), .A2(CLR) ); 342 | CLKBUF_X2 inst_151 ( .A(net_144), .Z(net_145) ); 343 | INV_X2 inst_112 ( .ZN(net_13), .A(net_11) ); 344 | NAND2_X2 inst_64 ( .ZN(net_55), .A2(net_41), .A1(net_39) ); 345 | INV_X2 inst_107 ( .A(net_129), .ZN(net_128) ); 346 | NAND2_X2 inst_67 ( .ZN(net_73), .A2(net_65), .A1(net_49) ); 347 | CLKBUF_X2 inst_181 ( .A(net_165), .Z(net_175) ); 348 | DFFR_X2 inst_127 ( .RN(net_118), .D(net_78), .QN(net_8), .CK(net_198) ); 349 | NAND2_X2 inst_70 ( .ZN(net_91), .A2(net_84), .A1(net_63) ); 350 | CLKBUF_X2 inst_186 ( .A(net_179), .Z(net_180) ); 351 | DFFR_X2 inst_129 ( .QN(net_124), .RN(net_118), .D(net_77), .CK(net_196) ); 352 | INV_X4 inst_92 ( .A(net_29), .ZN(net_28) ); 353 | NOR2_X2 inst_29 ( .A2(net_34), .ZN(net_27), .A1(net_26) ); 354 | CLKBUF_X2 inst_189 ( .A(net_182), .Z(net_183) ); 355 | NOR3_X2 inst_17 ( .ZN(net_78), .A3(net_76), .A1(net_53), .A2(net_27) ); 356 | NOR3_X2 inst_11 ( .ZN(net_64), .A1(net_51), .A3(net_48), .A2(net_19) ); 357 | AND3_X2 inst_146 ( .A3(net_122), .ZN(net_114), .A1(net_111), .A2(net_109) ); 358 | CLKBUF_X2 inst_188 ( .A(net_167), .Z(net_182) ); 359 | NOR3_X2 inst_14 ( .ZN(net_72), .A3(net_60), .A1(net_33), .A2(net_21) ); 360 | CLKBUF_X2 inst_202 ( .A(net_195), .Z(net_196) ); 361 | CLKBUF_X2 inst_206 ( .A(net_199), .Z(net_200) ); 362 | CLKBUF_X2 inst_187 ( .A(net_180), .Z(net_181) ); 363 | INV_X1 inst_122 ( .ZN(net_26), .A(net_8) ); 364 | NOR2_X2 inst_31 ( .ZN(net_44), .A1(net_42), .A2(net_30) ); 365 | NOR2_X2 inst_25 ( .A2(net_127), .A1(net_124), .ZN(net_34) ); 366 | DFFR_X2 inst_126 ( .QN(net_127), .RN(net_118), .D(net_69), .CK(net_204) ); 367 | CLKBUF_X2 inst_158 ( .A(net_150), .Z(net_152) ); 368 | DFFR_X1 inst_141 ( .RN(net_118), .D(net_117), .QN(net_1), .CK(net_156) ); 369 | NAND2_X2 inst_62 ( .A2(net_133), .ZN(net_76), .A1(net_45) ); 370 | CLKBUF_X2 inst_200 ( .A(net_174), .Z(net_194) ); 371 | INV_X2 inst_110 ( .ZN(net_139), .A(net_125) ); 372 | NAND2_X2 inst_74 ( .ZN(net_96), .A1(net_95), .A2(net_85) ); 373 | NAND2_X2 inst_57 ( .ZN(net_140), .A2(net_11), .A1(net_10) ); 374 | NOR2_X2 inst_35 ( .A1(net_136), .ZN(net_90), .A2(net_11) ); 375 | INV_X4 inst_99 ( .A(net_66), .ZN(net_31) ); 376 | NAND3_X2 inst_48 ( .A2(net_139), .A1(net_138), .ZN(net_121), .A3(net_93) ); 377 | NAND2_X2 inst_69 ( .ZN(net_85), .A1(net_84), .A2(net_68) ); 378 | NAND3_X2 inst_46 ( .A2(net_109), .ZN(net_79), .A1(net_50), .A3(net_46) ); 379 | INV_X4 inst_82 ( .ZN(net_17), .A(CLR) ); 380 | DFFR_X1 inst_136 ( .RN(net_118), .D(net_82), .Q(GRN2), .CK(net_191) ); 381 | NOR2_X2 inst_30 ( .ZN(net_43), .A1(net_42), .A2(net_22) ); 382 | INV_X4 inst_102 ( .ZN(net_115), .A(net_111) ); 383 | INV_X2 inst_108 ( .ZN(net_143), .A(net_128) ); 384 | CLKBUF_X2 inst_165 ( .A(net_158), .Z(net_159) ); 385 | NOR2_X2 inst_32 ( .ZN(net_61), .A2(net_60), .A1(net_57) ); 386 | NOR3_X2 inst_22 ( .A1(net_115), .ZN(net_113), .A2(net_112), .A3(net_108) ); 387 | DFFR_X1 inst_144 ( .RN(net_118), .D(net_113), .QN(net_3), .CK(net_174) ); 388 | NOR2_X2 inst_34 ( .A2(net_131), .ZN(net_71), .A1(net_70) ); 389 | NOR3_X2 inst_12 ( .A2(net_58), .ZN(net_52), .A3(net_38), .A1(net_18) ); 390 | CLKBUF_X2 inst_195 ( .A(net_188), .Z(net_189) ); 391 | NAND2_X4 inst_56 ( .A1(net_121), .ZN(net_111), .A2(net_36) ); 392 | NAND2_X2 inst_71 ( .ZN(net_95), .A2(net_91), .A1(net_88) ); 393 | NOR3_X2 inst_21 ( .A3(net_143), .A1(net_142), .A2(net_112), .ZN(net_107) ); 394 | INV_X2 inst_104 ( .A(net_136), .ZN(net_134) ); 395 | NAND2_X2 inst_60 ( .A1(net_51), .ZN(net_37), .A2(net_36) ); 396 | CLKBUF_X2 inst_215 ( .A(net_208), .Z(net_209) ); 397 | CLKBUF_X2 inst_169 ( .A(net_162), .Z(net_163) ); 398 | CLKBUF_X2 inst_168 ( .A(net_161), .Z(net_162) ); 399 | INV_X4 inst_97 ( .ZN(net_35), .A(net_28) ); 400 | CLKBUF_X2 inst_161 ( .A(net_144), .Z(net_155) ); 401 | DFFR_X2 inst_124 ( .RN(net_118), .D(net_44), .QN(net_4), .CK(net_214) ); 402 | NOR3_X2 inst_18 ( .A1(net_134), .A3(net_104), .ZN(net_103), .A2(net_71) ); 403 | NOR3_X2 inst_16 ( .ZN(net_77), .A3(net_76), .A1(net_34), .A2(net_24) ); 404 | CLKBUF_X2 inst_208 ( .A(net_201), .Z(net_202) ); 405 | INV_X4 inst_88 ( .ZN(net_18), .A(net_17) ); 406 | CLKBUF_X2 inst_220 ( .A(net_213), .Z(net_214) ); 407 | XNOR2_X2 inst_3 ( .ZN(net_142), .A(net_94), .B(net_87) ); 408 | CLKBUF_X2 inst_156 ( .A(net_149), .Z(net_150) ); 409 | OR2_X4 inst_9 ( .ZN(net_60), .A1(net_35), .A2(net_1) ); 410 | INV_X2 inst_113 ( .ZN(net_14), .A(CLR) ); 411 | CLKBUF_X2 inst_170 ( .A(net_163), .Z(net_164) ); 412 | CLKBUF_X2 inst_198 ( .A(net_158), .Z(net_192) ); 413 | NAND2_X4 inst_50 ( .A1(net_133), .ZN(net_131), .A2(net_6) ); 414 | DFFR_X1 inst_137 ( .RN(net_118), .D(net_86), .Q(GRN1), .CK(net_181) ); 415 | CLKBUF_X2 inst_199 ( .A(net_192), .Z(net_193) ); 416 | NOR2_X1 inst_41 ( .ZN(net_122), .A2(net_100), .A1(net_92) ); 417 | DFFR_X2 inst_130 ( .RN(net_118), .D(net_91), .QN(net_5), .CK(net_186) ); 418 | INV_X4 inst_91 ( .A(net_58), .ZN(net_36) ); 419 | DFFR_X2 inst_132 ( .RN(net_118), .D(net_105), .QN(net_11), .CK(net_169) ); 420 | DFFR_X1 inst_143 ( .RN(net_118), .D(net_116), .QN(net_2), .CK(net_151) ); 421 | CLKBUF_X2 inst_176 ( .A(net_146), .Z(net_170) ); 422 | CLKBUF_X2 inst_152 ( .A(net_145), .Z(net_146) ); 423 | NAND2_X2 inst_58 ( .ZN(net_38), .A1(net_29), .A2(net_1) ); 424 | NOR2_X2 inst_36 ( .A2(net_135), .ZN(net_83), .A1(net_13) ); 425 | AND2_X4 inst_147 ( .ZN(net_32), .A2(net_14), .A1(net_2) ); 426 | INV_X4 inst_87 ( .ZN(net_57), .A(net_17) ); 427 | NAND2_X2 inst_61 ( .ZN(net_39), .A2(net_32), .A1(net_23) ); 428 | CLKBUF_X2 inst_203 ( .A(net_179), .Z(net_197) ); 429 | NAND3_X2 inst_45 ( .ZN(net_46), .A3(net_31), .A1(net_25), .A2(net_20) ); 430 | INV_X4 inst_96 ( .A(net_36), .ZN(net_25) ); 431 | CLKBUF_X2 inst_212 ( .A(net_205), .Z(net_206) ); 432 | INV_X4 inst_101 ( .ZN(net_62), .A(net_38) ); 433 | XOR2_X2 inst_0 ( .Z(net_22), .B(net_6), .A(TEST) ); 434 | CLKBUF_X2 inst_184 ( .A(net_174), .Z(net_178) ); 435 | NOR4_X2 inst_10 ( .ZN(net_82), .A1(net_81), .A3(net_80), .A2(net_61), .A4(net_59) ); 436 | XNOR2_X2 inst_4 ( .ZN(net_141), .A(net_98), .B(net_66) ); 437 | NAND2_X2 inst_65 ( .ZN(net_67), .A1(net_66), .A2(net_64) ); 438 | CLKBUF_X2 inst_178 ( .A(net_171), .Z(net_172) ); 439 | INV_X4 inst_89 ( .A(net_49), .ZN(net_20) ); 440 | NOR2_X2 inst_28 ( .A2(net_126), .A1(net_123), .ZN(net_24) ); 441 | INV_X2 inst_111 ( .A(net_124), .ZN(net_123) ); 442 | NAND2_X2 inst_66 ( .ZN(net_68), .A1(net_62), .A2(net_55) ); 443 | INV_X2 inst_117 ( .A(net_58), .ZN(net_23) ); 444 | INV_X4 inst_98 ( .A(net_109), .ZN(net_42) ); 445 | CLKBUF_X2 inst_190 ( .A(net_183), .Z(net_184) ); 446 | NAND2_X2 inst_63 ( .A2(net_62), .A1(net_51), .ZN(net_47) ); 447 | OR3_X4 inst_7 ( .A2(net_81), .A1(net_80), .ZN(net_74), .A3(net_52) ); 448 | CLKBUF_X2 inst_204 ( .A(net_162), .Z(net_198) ); 449 | CLKBUF_X2 inst_185 ( .A(net_178), .Z(net_179) ); 450 | CLKBUF_X2 inst_182 ( .A(net_175), .Z(net_176) ); 451 | NAND2_X4 inst_49 ( .ZN(net_133), .A1(net_120), .A2(net_40) ); 452 | INV_X2 inst_120 ( .ZN(net_65), .A(net_64) ); 453 | CLKBUF_X2 inst_154 ( .A(net_147), .Z(net_148) ); 454 | NOR3_X2 inst_13 ( .ZN(net_59), .A1(net_58), .A2(net_57), .A3(net_56) ); 455 | INV_X2 inst_119 ( .ZN(net_56), .A(net_35) ); 456 | NAND2_X2 inst_75 ( .ZN(net_97), .A2(net_95), .A1(net_74) ); 457 | CLKBUF_X2 inst_192 ( .A(net_185), .Z(net_186) ); 458 | CLKBUF_X2 inst_166 ( .A(net_159), .Z(net_160) ); 459 | INV_X2 inst_116 ( .ZN(net_21), .A(net_20) ); 460 | CLKBUF_X2 inst_163 ( .A(net_155), .Z(net_157) ); 461 | INV_X4 inst_85 ( .ZN(net_40), .A(net_7) ); 462 | NAND2_X4 inst_54 ( .ZN(net_130), .A1(net_119), .A2(net_87) ); 463 | INV_X4 inst_79 ( .ZN(net_19), .A(net_3) ); 464 | INV_X2 inst_109 ( .A(net_127), .ZN(net_126) ); 465 | INV_X2 inst_106 ( .A(net_130), .ZN(net_129) ); 466 | CLKBUF_X2 inst_219 ( .A(net_212), .Z(net_213) ); 467 | CLKBUF_X2 inst_201 ( .A(net_194), .Z(net_195) ); 468 | CLKBUF_X2 inst_193 ( .A(net_170), .Z(net_187) ); 469 | AND2_X2 inst_149 ( .ZN(net_94), .A2(net_90), .A1(net_15) ); 470 | NAND3_X2 inst_43 ( .A2(net_127), .A3(net_124), .ZN(net_120), .A1(net_8) ); 471 | NOR2_X2 inst_39 ( .ZN(net_116), .A2(net_115), .A1(net_110) ); 472 | DFFR_X2 inst_128 ( .RN(net_118), .D(net_75), .QN(net_7), .CK(net_197) ); 473 | NAND2_X2 inst_73 ( .ZN(net_138), .A1(net_129), .A2(net_66) ); 474 | CLKBUF_X2 inst_217 ( .A(net_210), .Z(net_211) ); 475 | NOR3_X2 inst_23 ( .ZN(net_117), .A1(net_115), .A2(net_112), .A3(net_101) ); 476 | CLKBUF_X2 inst_171 ( .A(net_163), .Z(net_165) ); 477 | INV_X4 inst_77 ( .ZN(net_51), .A(net_4) ); 478 | INV_X4 inst_94 ( .ZN(net_109), .A(net_57) ); 479 | 480 | endmodule 481 | -------------------------------------------------------------------------------- /benchmark/simple.v: -------------------------------------------------------------------------------- 1 | module simple ( 2 | inp1, 3 | inp2, 4 | tau2015_clk, 5 | out 6 | ); 7 | 8 | // Start PIs 9 | input inp1; 10 | input inp2; 11 | input tau2015_clk; 12 | 13 | // Start POs 14 | output out; 15 | 16 | // Start wires 17 | wire n1; 18 | wire n2; 19 | wire n3; 20 | wire n4; 21 | wire inp1; 22 | wire inp2; 23 | wire tau2015_clk; 24 | wire out; 25 | 26 | // Start cells 27 | NAND2_X1 u1 ( .a(inp1), .b(inp2), .o(n1) ); 28 | DFF_X80 f1 ( .d(n2), .ck(tau2015_clk), .q(n3) ); 29 | INV_X1 u2 ( .a(n3), .o(n4) ); 30 | INV_X2 u3 ( .a(n4), .o(out) ); 31 | NOR2_X1 u4 ( .a(n1), .b(n3), .o(n2) ); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /example/ot_parser.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "verilog_driver.hpp" 4 | 5 | // Struct: Gate 6 | struct Gate { 7 | std::string name; 8 | std::string cell; 9 | std::unordered_map cellpin2net; 10 | std::unordered_map net2cellpin; 11 | }; 12 | 13 | // Struct: Module 14 | struct Module { 15 | std::string name; 16 | std::vector ports; 17 | std::vector wires; 18 | std::vector inputs; 19 | std::vector outputs; 20 | std::vector gates; 21 | }; 22 | 23 | 24 | // A verilog parser compatible with OpenTimer 25 | struct OpenTimerParser : public verilog::ParserVerilogInterface { 26 | OpenTimerParser() = default; 27 | virtual ~OpenTimerParser(){} 28 | 29 | void add_module(std::string&& name){ module.name = std::move(name); } 30 | 31 | void add_port(verilog::Port&& port) { 32 | if(port.dir == verilog::PortDirection::INPUT) { 33 | module.inputs.insert(module.inputs.end(), port.names.begin(), port.names.end()); 34 | } 35 | else if(port.dir == verilog::PortDirection::OUTPUT) { 36 | module.outputs.insert(module.outputs.end(), port.names.begin(), port.names.end()); 37 | } 38 | else{ 39 | module.inputs.insert(module.inputs.end(), port.names.begin(), port.names.end()); 40 | module.outputs.insert(module.outputs.end(), port.names.begin(), port.names.end()); 41 | } 42 | std::move(port.names.begin(), port.names.end(), std::back_inserter(module.ports)); 43 | } 44 | 45 | void add_net(verilog::Net&& net) { 46 | if(net.type == verilog::NetType::WIRE){ 47 | std::move(net.names.begin(), net.names.end(), std::back_inserter(module.wires)); 48 | } 49 | } 50 | 51 | void add_assignment(verilog::Assignment&& ast) { 52 | // Skip assignment 53 | } 54 | 55 | void add_instance(verilog::Instance&& inst) { 56 | auto &g = module.gates.emplace_back(); 57 | g.name = inst.module_name; 58 | g.cell = inst.inst_name; 59 | 60 | std::string pin; 61 | std::string net; 62 | for(size_t i=0; i(pin_name); break; 69 | case 1: pin = std::get<1>(pin_name).name; break; 70 | case 2: pin = std::get<2>(pin_name).name; break; 71 | } 72 | 73 | switch(net_name.index()) { 74 | case 0: net = std::get<0>(net_name); break; 75 | case 1: net = std::get<1>(net_name).name; break; 76 | case 2: net = std::get<2>(net_name).name; break; 77 | case 3: net = std::get<3>(net_name).value; break; 78 | } 79 | 80 | g.cellpin2net.insert({pin, net}); 81 | g.net2cellpin.insert({std::move(net), std::move(pin)}); 82 | } 83 | } 84 | } 85 | 86 | Module module; 87 | }; 88 | 89 | 90 | 91 | int main(const int argc, const char **argv){ 92 | if(argc < 2) { 93 | std::cerr << "Usage: ./sample_parser verilog_file\n"; 94 | return EXIT_FAILURE; 95 | } 96 | 97 | if(std::filesystem::exists(argv[1])) { 98 | OpenTimerParser parser; 99 | parser.read(argv[1]); 100 | } 101 | return EXIT_SUCCESS; 102 | } 103 | -------------------------------------------------------------------------------- /example/sample_parser.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "verilog_driver.hpp" 4 | 5 | // A custom parser struct 6 | struct SampleParser : public verilog::ParserVerilogInterface { 7 | virtual ~SampleParser(){} 8 | 9 | void add_module(std::string&& name){ 10 | std::cout << "Module name = " << name << '\n'; 11 | } 12 | 13 | void add_port(verilog::Port&& port) { 14 | std::cout << "Port: " << port << '\n'; 15 | ports.push_back(std::move(port)); 16 | } 17 | 18 | void add_net(verilog::Net&& net) { 19 | std::cout << "Net: " << net << '\n'; 20 | nets.push_back(std::move(net)); 21 | } 22 | 23 | void add_assignment(verilog::Assignment&& ast) { 24 | std::cout << "Assignment: " << ast << '\n'; 25 | assignments.push_back(std::move(ast)); 26 | } 27 | 28 | void add_instance(verilog::Instance&& inst) { 29 | std::cout << "Instance: " << inst << '\n'; 30 | insts.push_back(std::move(inst)); 31 | } 32 | 33 | std::vector ports; 34 | std::vector nets; 35 | std::vector assignments; 36 | std::vector insts; 37 | }; 38 | 39 | 40 | int main(const int argc, const char **argv){ 41 | if(argc < 2) { 42 | std::cerr << "Usage: ./sample_parser verilog_file\n"; 43 | return EXIT_FAILURE; 44 | } 45 | 46 | if(std::filesystem::exists(argv[1])) { 47 | SampleParser parser; 48 | parser.read(argv[1]); 49 | } 50 | return EXIT_SUCCESS; 51 | } 52 | -------------------------------------------------------------------------------- /image/.~lock.circuit.odg#: -------------------------------------------------------------------------------- 1 | ,clin99,csl-408-12.csl.illinois.edu,04.01.2019 17:25,file:///home/clin99/.config/libreoffice/4; -------------------------------------------------------------------------------- /image/circuit.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenTimer/Parser-Verilog/9776a25a63d9793e244cf7808c016022c440883a/image/circuit.odg -------------------------------------------------------------------------------- /image/circuit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/OpenTimer/Parser-Verilog/9776a25a63d9793e244cf7808c016022c440883a/image/circuit.png -------------------------------------------------------------------------------- /parser-verilog/verilog_data.hpp: -------------------------------------------------------------------------------- 1 | #ifndef DATA_VERILOG_HPP_ 2 | #define DATA_VERILOG_HPP_ 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | 12 | namespace verilog { 13 | 14 | enum class ConstantType { 15 | NONE, 16 | INTEGER, 17 | BINARY, 18 | OCTAL, 19 | DECIMAL, 20 | HEX, 21 | REAL, 22 | EXP 23 | }; 24 | 25 | inline std::ostream& operator<<(std::ostream& os, const ConstantType& t) { 26 | switch(t) { 27 | case ConstantType::NONE: os << "NONE"; break; 28 | case ConstantType::INTEGER: os << "INTEGER"; break; 29 | case ConstantType::BINARY: os << "BINARY"; break; 30 | case ConstantType::OCTAL: os << "OCTAL"; break; 31 | case ConstantType::DECIMAL: os << "DECIMAL"; break; 32 | case ConstantType::HEX: os << "HEX"; break; 33 | case ConstantType::REAL: os << "REAL"; break; 34 | case ConstantType::EXP: os << "EXP"; break; 35 | } 36 | return os; 37 | } 38 | 39 | struct Constant { 40 | Constant() = default; // Need this default constructor for return token 41 | Constant(std::string&& v, ConstantType t) : value(std::move(v)), type(t) {} 42 | std::string value; 43 | ConstantType type {ConstantType::NONE}; 44 | }; 45 | 46 | inline std::ostream& operator<<(std::ostream& os, const Constant& c) { 47 | std::cout << " constant value: " << c.value << " type: " << c.type; 48 | return os; 49 | } 50 | 51 | enum class PortDirection { 52 | INPUT, 53 | OUTPUT, 54 | INOUT 55 | }; 56 | 57 | inline std::ostream& operator<<(std::ostream& os, const PortDirection& dir) { 58 | switch(dir){ 59 | case PortDirection::INPUT: os << "INPUT"; break; 60 | case PortDirection::OUTPUT: os << "OUTPUT"; break; 61 | case PortDirection::INOUT: os << "INOUT"; break; 62 | } 63 | return os; 64 | } 65 | 66 | enum class ConnectionType { 67 | NONE, 68 | WIRE, 69 | REG 70 | }; 71 | 72 | inline std::ostream& operator<<(std::ostream& os, const ConnectionType& ct) { 73 | switch(ct){ 74 | case ConnectionType::NONE: os << "NONE"; break; 75 | case ConnectionType::WIRE: os << "WIRE"; break; 76 | case ConnectionType::REG: os << "REG"; break; 77 | } 78 | return os; 79 | } 80 | 81 | struct Port { 82 | std::vector names; 83 | int beg {-1}; 84 | int end {-1}; 85 | PortDirection dir; 86 | ConnectionType type {ConnectionType::NONE}; 87 | }; 88 | 89 | inline std::ostream& operator<<(std::ostream& os, const Port& port) { 90 | os << "beg: " << port.beg << " end: " << port.end << '\n'; 91 | os << "Dir: " << port.dir << " type: " << port.type << '\n'; 92 | for(const auto& n: port.names){ 93 | os << n << '\n'; 94 | } 95 | return os; 96 | } 97 | 98 | enum class NetType { 99 | NONE, 100 | REG, 101 | WIRE, 102 | WAND, 103 | WOR, 104 | TRI, 105 | TRIOR, 106 | TRIAND, 107 | SUPPLY0, 108 | SUPPLY1 109 | }; 110 | 111 | inline std::ostream& operator<<(std::ostream& os, const NetType& t) { 112 | switch(t){ 113 | case NetType::NONE: os << "NONE"; break; 114 | case NetType::REG: os << "REG"; break; 115 | case NetType::WIRE: os << "WIRE"; break; 116 | case NetType::WAND: os << "WAND"; break; 117 | case NetType::WOR: os << "WOR"; break; 118 | case NetType::TRI: os << "TRI"; break; 119 | case NetType::TRIAND: os << "TRIAND"; break; 120 | case NetType::TRIOR: os << "TRIOR"; break; 121 | case NetType::SUPPLY0: os << "SUPPLY0"; break; 122 | case NetType::SUPPLY1: os << "SUPPLY1"; break; 123 | } 124 | return os; 125 | } 126 | 127 | struct Net { 128 | std::vector names; 129 | int beg {-1}; 130 | int end {-1}; 131 | NetType type {NetType::NONE}; 132 | }; 133 | 134 | inline std::ostream& operator<<(std::ostream& os, const Net& net) { 135 | os << "beg: " << net.beg << " end: " << net.end << '\n'; 136 | os << "type: " << net.type << '\n'; 137 | for(const auto& n: net.names){ 138 | os << n << '\n'; 139 | } 140 | return os; 141 | } 142 | 143 | struct NetBit { 144 | NetBit(std::string&& n, int b): name(std::move(n)), bit(b) {} 145 | std::string name; 146 | int bit {-1}; 147 | }; 148 | 149 | inline std::ostream& operator<<(std::ostream& os, const NetBit& n) { 150 | os << n.name << '[' << n.bit << "] "; 151 | return os; 152 | } 153 | 154 | struct NetRange { 155 | NetRange(std::string&& n, int b, int e): name(std::move(n)), beg(b), end(e) {} 156 | std::string name; 157 | int beg {-1}; 158 | int end {-1}; 159 | }; 160 | 161 | inline std::ostream& operator<<(std::ostream& os, const NetRange& n) { 162 | os << n.name << '[' << n.beg << ':' << n.end << "] "; 163 | return os; 164 | } 165 | 166 | struct Assignment { 167 | // Left hand side can be: a wire, a bit in a wire, a part of a wire 168 | std::vector> lhs; 169 | 170 | // Right hand side can be: a wire, a bit in a wire, a part of a wire, a constant 171 | std::vector> rhs; 172 | }; 173 | 174 | inline std::ostream& operator<<(std::ostream& os, const Assignment& ast) { 175 | os << "LHS: "; 176 | for(const auto& l: ast.lhs){ 177 | switch(l.index()){ 178 | case 0: os << std::get<0>(l) << ' '; break; 179 | case 1: os << std::get<1>(l).name << '/' << std::get<1>(l).bit << ' '; 180 | break; 181 | case 2: os << std::get<2>(l).name << '/' << std::get<2>(l).beg << '/' << std::get<2>(l).end << ' '; 182 | break; 183 | } 184 | } 185 | os << '\n'; 186 | os << "RHS: "; 187 | for(const auto& r: ast.rhs){ 188 | switch(r.index()){ 189 | case 0: os << std::get<0>(r) << ' '; break; 190 | case 1: os << std::get<1>(r).name << '/' << std::get<1>(r).bit << ' '; 191 | break; 192 | case 2: os << std::get<2>(r).name << '/' << std::get<2>(r).beg << '/' << std::get<2>(r).end << ' '; 193 | break; 194 | case 3: os << std::get<3>(r) << ' '; break; 195 | } 196 | } 197 | 198 | return os; 199 | } 200 | 201 | using NetConcat = std::variant; 202 | 203 | struct Instance { 204 | std::string module_name; 205 | std::string inst_name; 206 | 207 | // pin_names might be empty. e.g. my_module m1(net1, net2); 208 | std::vector> pin_names; 209 | std::vector> net_names; 210 | }; 211 | 212 | inline std::ostream& operator<<(std::ostream& os, const Instance& inst) { 213 | os << inst.module_name << ' ' << inst.inst_name << '('; 214 | 215 | if(!inst.pin_names.empty()){ 216 | for(size_t i=0; i 1){ 220 | std::cout << '{'; 221 | } 222 | for(const auto& v: inst.net_names[i]){ 223 | std::visit([](const auto& v){ std::cout << v << ' '; }, v); 224 | } 225 | if(inst.net_names[i].size() > 1){ 226 | std::cout << '}'; 227 | } 228 | std::cout << ") " ; 229 | } 230 | } 231 | else{ 232 | for(size_t i=0; i 1){ 234 | std::cout << '{'; 235 | } 236 | for(const auto& v: inst.net_names[i]){ 237 | std::visit([](const auto& v){ std::cout << v << ' '; }, v); 238 | } 239 | if(inst.net_names[i].size() > 1){ 240 | std::cout << '}'; 241 | } 242 | std::cout << ','; 243 | } 244 | } 245 | os << ')'; 246 | return os; 247 | } 248 | 249 | 250 | 251 | } 252 | #endif 253 | 254 | 255 | -------------------------------------------------------------------------------- /parser-verilog/verilog_driver.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PARSER_VERILOG_HPP_ 2 | #define PARSER_VERILOG_HPP_ 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | #include "verilog_scanner.hpp" 12 | #include "verilog_parser.tab.hh" 13 | 14 | namespace verilog { 15 | 16 | class ParserVerilogInterface { 17 | public: 18 | virtual ~ParserVerilogInterface(){ 19 | if(_scanner) delete _scanner; 20 | if(_parser) delete _parser; 21 | } 22 | virtual void add_module(std::string&&) = 0; 23 | // port names, begin index, end index, port type (IOB), connection type (wire, reg) 24 | virtual void add_port(Port&&) = 0; 25 | virtual void add_net(Net&&) = 0; 26 | virtual void add_assignment(Assignment&&) = 0; 27 | virtual void add_instance(Instance&&) = 0; 28 | 29 | void read(const std::filesystem::path&); 30 | 31 | private: 32 | VerilogScanner* _scanner {nullptr}; 33 | VerilogParser* _parser {nullptr}; 34 | }; 35 | 36 | inline void ParserVerilogInterface::read(const std::filesystem::path& p){ 37 | if(! std::filesystem::exists(p)){ 38 | return ; 39 | } 40 | 41 | std::ifstream ifs(p); 42 | 43 | if(!_scanner){ 44 | _scanner = new VerilogScanner(&ifs); 45 | } 46 | if(!_parser){ 47 | _parser = new VerilogParser(*_scanner, this); 48 | } 49 | _parser->parse(); 50 | } 51 | 52 | 53 | } 54 | #endif 55 | -------------------------------------------------------------------------------- /parser-verilog/verilog_lexer.l: -------------------------------------------------------------------------------- 1 | %{ 2 | /* C++ string header, for string ops below */ 3 | #include 4 | #include 5 | 6 | /* Implementation of yyFlexScanner */ 7 | #include "verilog_scanner.hpp" 8 | #undef YY_DECL 9 | #define YY_DECL int verilog::VerilogScanner::yylex(verilog::VerilogParser::semantic_type * const lval, verilog::VerilogParser::location_type *loc ) 10 | 11 | /* typedef to make the returns for the tokens shorter */ 12 | using token = verilog::VerilogParser::token; 13 | 14 | /* define yyterminate as this instead of NULL */ 15 | #define yyterminate() return( token::END ) 16 | 17 | /* msvc2010 requires that we exclude this header file. */ 18 | #define YY_NO_UNISTD_H 19 | 20 | /* update location on matching */ 21 | #define YY_USER_ACTION loc->step(); loc->columns(yyleng); 22 | %} 23 | 24 | /* Make the generated scanner run in debug mode. */ 25 | %option debug 26 | 27 | /* Cause the default rule (that unmatched scanner input is echoed to stdout) to be suppressed. */ 28 | %option nodefault 29 | 30 | /* Inform flex that a derived NAME is implemented as a subclass of yyFlexLexer, so flex will place your actions in the member function foo::yylex() instead of yyFlexLexer::yylex(). */ 31 | %option yyclass="verilog::VerilogScanner" 32 | 33 | /* Set yywrap always returns 1. yywrap is called when reaching EOF */ 34 | %option noyywrap 35 | 36 | /* Suppress the warning message yyunput is defined but not used */ 37 | %option nounput 38 | %option never-interactive 39 | %option c++ 40 | 41 | /* Define inclusive/exclusive states */ 42 | %x in_comment 43 | %x in_attribute 44 | 45 | /* Predefined rules */ 46 | NEWLINE "\n"|"\r\n" 47 | SPACE " "|"\t"|"\f" 48 | COMMENT_BEGIN "/*" 49 | COMMENT_END "*/" 50 | COMMENT_LINE "//".*\n 51 | 52 | ATTRIBUTE_BEGIN "(*" 53 | ATTRIBUTE_END "*)" 54 | 55 | /* Name rule http://www.asic-world.com/verilog/syntax1.html */ 56 | NAME [_a-zA-Z][$_a-zA-Z0-9]*{0,1023} 57 | /* 58 | Check the escape rule inside character class 59 | https://www.regular-expressions.info/charclass.html 60 | */ 61 | ESCAPED_NAME \\[\\^!"#$%&',()*+\-.a-zA-Z0-9/{|}~[\]_:;<=>?@]+[\t\f ] 62 | INTEGER [1-9][0-9]*|0 63 | BINARY [+-]?[0-9]*"'"[Bb][01_xXzZ]+ 64 | OCTAL [+-]?[0-9]*"'"[Oo][0-7_xXzZ]+ 65 | DECIMAL [+-]?[0-9]*"'"[Dd][0-9_xXzZ]+ 66 | HEX [+-]?[0-9]*"'"[Hh][0-9a-fA-F_xXzZ]+ 67 | REAL [-+]?([0-9]*\.[0-9]+|[0-9]+) 68 | EXP [-+]?[0-9]+"."?[0-9]*"E"[-+]?[0-9]+ 69 | 70 | 71 | /* Token rule section begins */ 72 | %% 73 | %{ /** Code executed at the beginning of yylex **/ 74 | yylval = lval; 75 | %} 76 | 77 | <*>{SPACE} { /* ignore any space */ } 78 | {NEWLINE} { // Update line numbers 79 | loc->lines(); 80 | // return( token::NEWLINE ); 81 | } 82 | 83 | 84 | {COMMENT_LINE} { loc->lines(); } 85 | 86 | {COMMENT_BEGIN} { BEGIN(in_comment); } 87 | <> { 88 | BEGIN(INITIAL); 89 | std::cerr << "Unclosed comment at line " << loc->end.line << " col " << loc->end.column << '\n'; 90 | yyterminate(); 91 | } 92 | {NEWLINE} { loc->lines(); } 93 | . { /* ignore characters in comment */ } 94 | {COMMENT_END} { BEGIN(INITIAL); } 95 | 96 | 97 | {ATTRIBUTE_BEGIN} { BEGIN(in_attribute); } 98 | <> { 99 | BEGIN(INITIAL); 100 | std::cerr << "Unclosed attribute at line " << loc->end.line << " col " << loc->end.column << '\n'; 101 | yyterminate(); 102 | } 103 | {NEWLINE} { loc->lines(); } 104 | . { /* ignore characters in comment */ } 105 | {ATTRIBUTE_END} { BEGIN(INITIAL); } 106 | 107 | 108 | ":"|"."|"{"|"}"|"["|"]"|","|"*"|";"|"="|"-"|"+"|"|"|"("|")" { 109 | return yytext[0]; 110 | } 111 | 112 | module { return token::MODULE; } 113 | endmodule { return token::ENDMODULE; } 114 | input { return token::INPUT; } 115 | output { return token::OUTPUT; } 116 | inout { return token::INOUT; } 117 | reg { return token::REG; } 118 | wire { return token::WIRE; } 119 | wor { return token::WOR; } 120 | wand { return token::WAND; } 121 | tri { return token::TRI; } 122 | trior { return token::TRIOR; } 123 | triand { return token::TRIAND; } 124 | SUPPLY0 { return token::SUPPLY0; } 125 | SUPPLY1 { return token::SUPPLY1; } 126 | assign { return token::ASSIGN; } 127 | 128 | 129 | {ESCAPED_NAME} { 130 | yylval->build(yytext); 131 | return token::ESCAPED_NAME; 132 | } 133 | 134 | {NAME} { 135 | yylval->build( yytext ); 136 | return token::NAME; 137 | } 138 | 139 | {INTEGER} { 140 | yylval->build(verilog::Constant(yytext, verilog::ConstantType::INTEGER)); 141 | return token::INTEGER; 142 | } 143 | 144 | {BINARY} { 145 | yylval->build(verilog::Constant(yytext, verilog::ConstantType::BINARY)); 146 | return token::BINARY; 147 | } 148 | 149 | {OCTAL} { 150 | yylval->build(verilog::Constant(yytext, verilog::ConstantType::OCTAL)); 151 | return token::OCTAL; 152 | } 153 | 154 | {DECIMAL} { 155 | yylval->build(verilog::Constant(yytext, verilog::ConstantType::DECIMAL)); 156 | return token::DECIMAL; 157 | } 158 | 159 | {HEX} { 160 | yylval->build(verilog::Constant(yytext, verilog::ConstantType::HEX)); 161 | return token::HEX; 162 | } 163 | 164 | {REAL} { 165 | verilog::Constant c(yytext, verilog::ConstantType::REAL); 166 | return token::REAL; 167 | } 168 | 169 | {EXP} { 170 | verilog::Constant c(yytext, verilog::ConstantType::EXP); 171 | return token::EXP; 172 | } 173 | 174 | 175 | 176 | 177 | . { 178 | /* Last rule catches any unmatched character */ 179 | std::cerr << "Failed to match : " << yytext << '\n'; 180 | yyterminate(); 181 | } 182 | %% 183 | 184 | 185 | -------------------------------------------------------------------------------- /parser-verilog/verilog_parser.yy: -------------------------------------------------------------------------------- 1 | %skeleton "lalr1.cc" 2 | %require "3.0" 3 | %debug 4 | %defines 5 | %define api.namespace {verilog} 6 | %define api.parser.class {VerilogParser} 7 | 8 | %define parse.error verbose 9 | 10 | %code requires{ 11 | #include "verilog_data.hpp" 12 | 13 | namespace verilog { 14 | class ParserVerilogInterface; 15 | class VerilogScanner; 16 | } 17 | 18 | // The following definitions is missing when %locations isn't used 19 | # ifndef YY_NULLPTR 20 | # if defined __cplusplus && 201103L <= __cplusplus 21 | # define YY_NULLPTR nullptr 22 | # else 23 | # define YY_NULLPTR 0 24 | # endif 25 | # endif 26 | 27 | } 28 | 29 | %parse-param { VerilogScanner &scanner } 30 | %parse-param { ParserVerilogInterface *driver } 31 | 32 | %code { 33 | #include 34 | #include 35 | #include 36 | #include 37 | #include 38 | 39 | /* include for all driver functions */ 40 | #include "verilog_driver.hpp" 41 | 42 | #undef yylex 43 | #define yylex scanner.yylex 44 | } 45 | 46 | %define api.value.type variant 47 | %define parse.assert 48 | 49 | 50 | %left '-' '+' 51 | %left '*' '/' 52 | %left UMINUS 53 | 54 | %token END 0 "end of file" 55 | %token NEWLINE 56 | %token UNDEFINED 57 | 58 | /* Valid name (Identifiers) */ 59 | %token NAME 60 | %token ESCAPED_NAME 61 | 62 | %token INTEGER BINARY OCTAL DECIMAL HEX REAL EXP 63 | 64 | /* Keyword tokens */ 65 | %token MODULE ENDMODULE INPUT OUTPUT INOUT REG WIRE WAND WOR TRI TRIOR TRIAND SUPPLY0 SUPPLY1 ASSIGN 66 | 67 | 68 | /* Nonterminal Symbols */ 69 | %type valid_name 70 | 71 | %type> port_type 72 | %type port_declarations port_decl port_decl_statements 73 | 74 | %type net_type 75 | %type net_decl_statements net_decl 76 | 77 | %type constant 78 | %type assignment 79 | %type>> lhs lhs_concat lhs_exprs lhs_expr 80 | %type> rhs rhs_concat rhs_exprs rhs_expr 81 | 82 | %type instance 83 | %type>, std::vector>>> inst_pins nets_by_name 84 | 85 | %type>> nets_by_position 86 | 87 | %type, std::vector>> net_by_name 88 | 89 | %locations 90 | %start design 91 | 92 | %% 93 | 94 | valid_name 95 | : NAME { $$ = $1; } 96 | | ESCAPED_NAME { $$ = $1; } 97 | ; 98 | 99 | design 100 | : modules; 101 | 102 | modules 103 | : 104 | | modules module 105 | ; 106 | 107 | module 108 | : MODULE valid_name ';' 109 | { 110 | driver->add_module(std::move($2)); 111 | } 112 | statements ENDMODULE 113 | | MODULE valid_name '(' ')' ';' 114 | { 115 | driver->add_module(std::move($2)); 116 | } 117 | statements ENDMODULE 118 | | MODULE valid_name '(' port_names ')' ';' 119 | { 120 | driver->add_module(std::move($2)); 121 | } 122 | statements ENDMODULE 123 | | MODULE valid_name '(' 124 | { 125 | driver->add_module(std::move($2)); 126 | } 127 | port_declarations ')' 128 | { 129 | driver->add_port(std::move($5)); 130 | } 131 | ';' statements ENDMODULE 132 | ; 133 | 134 | // port names are ignored as they will be parsed later in declaration 135 | port_names 136 | : valid_name { } 137 | | port_names ',' valid_name { } 138 | ; 139 | 140 | 141 | port_type 142 | : INPUT { $$ = std::make_pair(verilog::PortDirection::INPUT, verilog::ConnectionType::NONE); } 143 | | INPUT WIRE { $$ = std::make_pair(verilog::PortDirection::INPUT, verilog::ConnectionType::WIRE); } 144 | | OUTPUT { $$ = std::make_pair(verilog::PortDirection::OUTPUT,verilog::ConnectionType::NONE); } 145 | | OUTPUT REG { $$ = std::make_pair(verilog::PortDirection::OUTPUT,verilog::ConnectionType::REG); } 146 | | INOUT { $$ = std::make_pair(verilog::PortDirection::INOUT, verilog::ConnectionType::NONE); } 147 | | INOUT WIRE { $$ = std::make_pair(verilog::PortDirection::INOUT, verilog::ConnectionType::WIRE); } 148 | | INOUT REG { $$ = std::make_pair(verilog::PortDirection::INOUT, verilog::ConnectionType::REG); } 149 | ; 150 | 151 | // e.g. "input a, b, output c, d" is allowed in port declarations 152 | port_declarations 153 | : port_decl 154 | { 155 | $$ = $1; 156 | } 157 | | port_declarations ',' port_decl 158 | { 159 | driver->add_port(std::move($1)); 160 | $$ = $3; 161 | } 162 | | port_declarations ',' valid_name 163 | { 164 | $1.names.emplace_back(std::move($3)); 165 | $$ = $1; 166 | } 167 | ; 168 | 169 | port_decl 170 | : port_type valid_name 171 | { 172 | $$.dir = std::get<0>($1); 173 | $$.type = std::get<1>($1); 174 | $$.names.emplace_back(std::move($2)); 175 | } 176 | | port_type '[' INTEGER ':' INTEGER ']' valid_name 177 | { 178 | $$.dir = std::get<0>($1); 179 | $$.type = std::get<1>($1); 180 | $$.beg = std::stoi($3.value); 181 | $$.end = std::stoi($5.value); 182 | $$.names.push_back(std::move($7)); 183 | } 184 | ; 185 | 186 | statements 187 | : // empty 188 | | statements statement 189 | | statements statement_assign 190 | ; 191 | 192 | statement 193 | : declaration 194 | | instance 195 | ; 196 | 197 | 198 | declaration 199 | : port_decl_statements ';' { driver->add_port(std::move($1)); } 200 | | net_decl_statements ';' { driver->add_net(std::move($1)); } 201 | ; 202 | 203 | // e.g. "input a, b, output c, d" is not allowed in port declaration statements 204 | port_decl_statements 205 | : port_decl 206 | { 207 | $$ = $1; 208 | } 209 | | port_decl_statements ',' valid_name 210 | { 211 | $1.names.emplace_back(std::move($3)); 212 | $$ = $1; 213 | } 214 | ; 215 | 216 | 217 | net_type 218 | : WIRE { $$ = verilog::NetType::WIRE; } 219 | | WAND { $$ = verilog::NetType::WAND; } 220 | | WOR { $$ = verilog::NetType::WOR; } 221 | | TRI { $$ = verilog::NetType::TRI; } 222 | | TRIOR { $$ = verilog::NetType::TRIOR; } 223 | | TRIAND { $$ = verilog::NetType::TRIAND; } 224 | | SUPPLY0 { $$ = verilog::NetType::SUPPLY0; } 225 | | SUPPLY1 { $$ = verilog::NetType::SUPPLY1; } 226 | ; 227 | 228 | net_decl_statements 229 | : net_decl 230 | { 231 | $$ = $1; 232 | } 233 | | net_decl_statements ',' valid_name 234 | { 235 | $1.names.push_back(std::move($3)); 236 | $$ = $1; 237 | } 238 | ; 239 | 240 | net_decl 241 | : net_type valid_name 242 | { 243 | $$.type = $1; 244 | $$.names.push_back(std::move($2)); 245 | } 246 | | net_type '[' INTEGER ':' INTEGER ']' valid_name 247 | { 248 | $$.type = $1; 249 | $$.beg = std::stoi($3.value); 250 | $$.end = std::stoi($5.value); 251 | $$.names.push_back(std::move($7)); 252 | } 253 | ; 254 | 255 | 256 | statement_assign 257 | : ASSIGN assignments ';' 258 | 259 | assignments 260 | : assignment 261 | | assignments ',' assignment 262 | ; 263 | 264 | assignment 265 | : lhs '=' rhs { $$.lhs = $1; $$.rhs = $3; driver->add_assignment(std::move($$)); } 266 | ; 267 | 268 | 269 | // Should try to merge lhs & rhs definition 270 | lhs 271 | : valid_name { $$.push_back(std::move($1)); } 272 | | valid_name '[' INTEGER ']' 273 | { $$.emplace_back(verilog::NetBit(std::move($1), std::stoi($3.value))); } 274 | | valid_name '[' INTEGER ':' INTEGER ']' 275 | { $$.emplace_back(verilog::NetRange(std::move($1), std::stoi($3.value), std::stoi($5.value))); } 276 | | lhs_concat { $$ = $1; } 277 | ; 278 | 279 | lhs_concat 280 | : '{' lhs_exprs '}' { std::move($2.begin(), $2.end(), std::back_inserter($$)); } 281 | ; 282 | 283 | lhs_exprs 284 | : lhs_expr { std::move($1.begin(), $1.end(), std::back_inserter($$)); } 285 | | lhs_exprs ',' lhs_expr 286 | { 287 | std::move($1.begin(), $1.end(), std::back_inserter($$)); 288 | std::move($3.begin(), $3.end(), std::back_inserter($$)); 289 | } 290 | ; 291 | 292 | lhs_expr 293 | : valid_name { $$.push_back(std::move($1)); } 294 | | valid_name '[' INTEGER ']' 295 | { $$.emplace_back(verilog::NetBit(std::move($1), std::stoi($3.value))); } 296 | | valid_name '[' INTEGER ':' INTEGER ']' 297 | { $$.emplace_back(verilog::NetRange(std::move($1), std::stoi($3.value), std::stoi($5.value))); } 298 | | lhs_concat 299 | { std::move($1.begin(), $1.end(), std::back_inserter($$)); } 300 | ; 301 | 302 | 303 | 304 | constant 305 | : INTEGER { $$=$1; } 306 | | BINARY { $$=$1; } 307 | | OCTAL { $$=$1; } 308 | | DECIMAL { $$=$1; } 309 | | HEX { $$=$1; } 310 | | REAL { $$=$1; } 311 | | EXP { $$=$1; } 312 | ; 313 | 314 | rhs 315 | : valid_name { $$.emplace_back($1); } 316 | | valid_name '[' INTEGER ']' 317 | { $$.emplace_back(verilog::NetBit(std::move($1), std::stoi($3.value))); } 318 | | valid_name '[' INTEGER ':' INTEGER ']' 319 | { $$.emplace_back(verilog::NetRange(std::move($1), std::stoi($3.value), std::stoi($5.value))); } 320 | | constant { $$.push_back(std::move($1)); } 321 | | rhs_concat { $$ = $1; } 322 | ; 323 | 324 | rhs_concat 325 | : '{' rhs_exprs '}' { std::move($2.begin(), $2.end(), std::back_inserter($$)); } 326 | ; 327 | 328 | rhs_exprs 329 | : rhs_expr { std::move($1.begin(), $1.end(), std::back_inserter($$)); } 330 | | rhs_exprs ',' rhs_expr 331 | { 332 | std::move($1.begin(), $1.end(), std::back_inserter($$)); 333 | std::move($3.begin(), $3.end(), std::back_inserter($$)); 334 | } 335 | ; 336 | 337 | rhs_expr 338 | : valid_name { $$.push_back(std::move($1)); } 339 | | valid_name '[' INTEGER ']' 340 | { $$.emplace_back(verilog::NetBit(std::move($1), std::stoi($3.value))); } 341 | | valid_name '[' INTEGER ':' INTEGER ']' 342 | { $$.emplace_back(verilog::NetRange(std::move($1), std::stoi($3.value), std::stoi($5.value))); } 343 | | constant { $$.push_back(std::move($1)); } 344 | | rhs_concat 345 | { std::move($1.begin(), $1.end(), std::back_inserter($$)); } 346 | ; 347 | 348 | 349 | 350 | 351 | 352 | instance 353 | : valid_name valid_name '(' inst_pins ')' ';' 354 | { 355 | std::swap($$.module_name, $1); 356 | std::swap($$.inst_name, $2); 357 | std::swap($$.pin_names, std::get<0>($4)); 358 | std::swap($$.net_names, std::get<1>($4)); 359 | driver->add_instance(std::move($$)); 360 | } 361 | | valid_name parameters valid_name '(' inst_pins ')' ';' 362 | { 363 | std::swap($$.module_name, $1); 364 | std::swap($$.inst_name, $3); 365 | std::swap($$.pin_names, std::get<0>($5)); 366 | std::swap($$.net_names, std::get<1>($5)); 367 | driver->add_instance(std::move($$)); 368 | } 369 | ; 370 | 371 | inst_pins 372 | : { } // empty 373 | | nets_by_position { std::swap(std::get<1>($$), $1); } 374 | | nets_by_name 375 | { 376 | std::swap(std::get<0>($$), std::get<0>($1)); 377 | std::swap(std::get<1>($$), std::get<1>($1)); 378 | } 379 | ; 380 | 381 | nets_by_position 382 | : rhs { $$.emplace_back(std::move($1)); } 383 | | nets_by_position ',' rhs 384 | { 385 | std::move($1.begin(), $1.end(), std::back_inserter($$)); 386 | $$.push_back(std::move($3)); 387 | } 388 | ; 389 | 390 | 391 | nets_by_name 392 | : net_by_name 393 | { 394 | std::get<0>($$).push_back(std::move(std::get<0>($1))); 395 | std::get<1>($$).push_back(std::move(std::get<1>($1))); 396 | } 397 | | nets_by_name ',' net_by_name 398 | { 399 | auto &pin_names = std::get<0>($1); 400 | auto &net_names = std::get<1>($1); 401 | std::move(pin_names.begin(), pin_names.end(), std::back_inserter(std::get<0>($$))); 402 | std::move(net_names.begin(), net_names.end(), std::back_inserter(std::get<1>($$))); 403 | 404 | std::get<0>($$).push_back(std::move(std::get<0>($3))); 405 | std::get<1>($$).push_back(std::move(std::get<1>($3))); 406 | } 407 | ; 408 | 409 | 410 | net_by_name 411 | : '.' valid_name '(' ')' 412 | { std::get<0>($$) = $2; } 413 | | '.' valid_name '(' valid_name ')' 414 | { 415 | std::get<0>($$) = $2; 416 | std::get<1>($$).push_back(std::move($4)); 417 | } 418 | | '.' valid_name '(' valid_name '[' INTEGER ']' ')' 419 | { 420 | std::get<0>($$) = $2; 421 | std::get<1>($$).emplace_back(verilog::NetBit(std::move($4), std::stoi($6.value))); 422 | } 423 | // The previous two rules are also in rhs. But I don't want to create special rule just for this case 424 | | '.' valid_name '(' rhs ')' 425 | { 426 | std::get<0>($$) = $2; 427 | std::get<1>($$) = $4; 428 | } 429 | // Bus port bit 430 | | '.' valid_name '[' INTEGER ']' '(' ')' 431 | { 432 | std::get<0>($$) = verilog::NetBit(std::move($2), std::stoi($4.value)); 433 | } 434 | | '.' valid_name '[' INTEGER ']' '(' rhs ')' 435 | { 436 | std::get<0>($$) = verilog::NetBit(std::move($2), std::stoi($4.value)); 437 | std::get<1>($$) = $7; 438 | } 439 | // Bus port part 440 | | '.' valid_name '[' INTEGER ':' INTEGER ']' '(' ')' 441 | { 442 | std::get<0>($$) = verilog::NetRange(std::move($2), std::stoi($4.value), std::stoi($6.value)); 443 | } 444 | | '.' valid_name '[' INTEGER ':' INTEGER ']' '(' rhs ')' 445 | { 446 | std::get<0>($$) = verilog::NetRange(std::move($2), std::stoi($4.value), std::stoi($6.value)); 447 | std::get<1>($$) = $9; 448 | } 449 | ; 450 | 451 | 452 | // parameters are ignored for now 453 | parameters 454 | : '#' '(' param_exprs ')' 455 | ; 456 | 457 | param_exprs 458 | : param_expr 459 | | param_exprs ',' param_expr 460 | ; 461 | 462 | param_expr 463 | : valid_name 464 | | '`' valid_name 465 | | constant 466 | | '-' param_expr %prec UMINUS 467 | | param_expr '+' param_expr 468 | | param_expr '-' param_expr 469 | | param_expr '*' param_expr 470 | | param_expr '/' param_expr 471 | | '(' param_expr ')' 472 | ; 473 | 474 | 475 | %% 476 | 477 | void verilog::VerilogParser::error(const location_type &l, const std::string &err_message) { 478 | std::cerr << "Parser error: " << err_message << '\n' 479 | << " begin at line " << l.begin.line << " col " << l.begin.column << '\n' 480 | << " end at line " << l.end.line << " col " << l.end.column << "\n"; 481 | std::abort(); 482 | } 483 | 484 | 485 | -------------------------------------------------------------------------------- /parser-verilog/verilog_scanner.hpp: -------------------------------------------------------------------------------- 1 | #ifndef SCANNER_VERILOG_HPP_ 2 | #define SCANNER_VERILOG_HPP_ 3 | 4 | #if ! defined(yyFlexLexerOnce) 5 | #include 6 | #endif 7 | 8 | #include "verilog_parser.tab.hh" 9 | #include "location.hh" 10 | 11 | namespace verilog { 12 | 13 | class VerilogScanner : public yyFlexLexer{ 14 | public: 15 | 16 | VerilogScanner(std::istream *in) : yyFlexLexer(in) { 17 | }; 18 | virtual ~VerilogScanner() {}; 19 | 20 | //get rid of override virtual function warning 21 | using FlexLexer::yylex; 22 | 23 | virtual 24 | int yylex( verilog::VerilogParser::semantic_type * const lval, 25 | verilog::VerilogParser::location_type *location ); 26 | // YY_DECL defined in mc_lexer.l 27 | // Method body created by flex in mc_lexer.yy.cc 28 | 29 | private: 30 | /* yyval ptr */ 31 | verilog::VerilogParser::semantic_type *yylval = nullptr; 32 | }; 33 | 34 | } /* end namespace MC */ 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /unittest/regression.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #include "verilog_driver.hpp" 6 | 7 | 8 | // A custom parser struct 9 | struct VerilogParser : public verilog::ParserVerilogInterface { 10 | virtual ~VerilogParser(){} 11 | 12 | void add_module(std::string&& name){} 13 | void add_port(verilog::Port&& port) {} 14 | void add_net(verilog::Net&& net) {} 15 | void add_assignment(verilog::Assignment&& ast) {} 16 | void add_instance(verilog::Instance&& inst) { } 17 | }; 18 | 19 | 20 | int main(const int argc, const char **argv){ 21 | std::cout << std::setw(10) << ' ' 22 | << std::setw(20) << "[Benchmark]" 23 | << std::setw(13) << "[Runtime]" << '\n'; 24 | std::cout << std::string(45, '-') << '\n'; 25 | 26 | for(const auto&p : std::filesystem::directory_iterator("../benchmark/")){ 27 | 28 | std::cout << std::setw(10) << "Parsing " 29 | << std::setw(20) << p.path().filename().string() ; 30 | 31 | VerilogParser parser; 32 | auto t1 = std::chrono::high_resolution_clock::now(); 33 | parser.read(p); 34 | auto t2 = std::chrono::high_resolution_clock::now(); 35 | 36 | std::cout << std::setw(13) 37 | << std::chrono::duration_cast(t2 - t1).count()/1000.0f << "ms\n"; 38 | } 39 | 40 | return( EXIT_SUCCESS ); 41 | } 42 | --------------------------------------------------------------------------------