├── LICENSE ├── Logs └── ryzen7-1800x │ ├── README.md │ ├── off-chip-bl.log │ ├── proxy-mode.iolog.bz2 │ ├── psp-emu.tracelog.bz2 │ └── reg-map.txt ├── Presentations ├── 36c3 │ └── 36c3-10942-uncover_understand_own_-_regaining_control_over_your_amd_cpu.pdf └── BlackHat2020 │ └── us-20-BuhrenEichner-All-you-ever-wanted-to-know-about-the-AMD-Platform-Security-Processor-and-were-Afraid-to-Emulate.pdf ├── README.md ├── SmnRegions.md ├── masterthesis-eichner-psp-2020.pdf ├── mmio_regions.txt └── svc_syscall_table.txt /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /Logs/ryzen7-1800x/README.md: -------------------------------------------------------------------------------- 1 | # Logs and output from a Ryzen7 1800X running on an Asus Prime X370-Pro 2 | 3 | This directory contains logs for an off chip BL run in the emulator with proxy mode configured. 4 | The hardware used was a Ryzen7 1800X on an Asus Prime X370-Pro mainboard. 5 | The following command line was used to record the log using proxy mode: 6 | ``` 7 | ./PSPEmu \ 8 | --emulation-mode sys \ 9 | --flash-rom ../../binaries/Ryzen/Asus/PRIME-X370-PRO/PRIME-X370-PRO-ASUS-3803.ROM \ 10 | --cpu-profile ryzen7-1800x \ 11 | --trace-log /tmp/log \ 12 | --timer-real-time \ 13 | --intercept-svc-6 \ 14 | --emulate-single-socket-id 0 \ 15 | --emulate-single-die-id 0 \ 16 | --psp-proxy-addr tcp://localhost:1236 \ 17 | --emulate-devices ccp-v5:flash:timer2 \ 18 | --iom-log-all-accesses \ 19 | --trace-svcs \ 20 | --io-log-write ../../ryzen_1800X.iolog 21 | ``` 22 | 23 | The resulting files are contained in this directory, namely: 24 | * `off-chip-bl.log`: The output of the off chip BL when intercepting the debug log syscall 25 | * `reg-map.txt`: Register map parsed from the recorded I/O log using `psp-iolog-tool --mode reg-map --iolog-input ` 26 | * `psp-emu.tracelog.bz2`: Compressed tracelog recorded by PSPEmu 27 | * `proxy-mode.iolog.bz2`: Compressed I/O log for replaying 28 | 29 | ## Replaying the I/O log 30 | 31 | For replaying the I/O log you need the exact same firmware image version which was used when 32 | recording the log. You can download the image from ASUS website [here](https://dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/PRIME_X370-PRO/PRIME-X370-PRO-ASUS-3803.zip). 33 | 34 | After decompressing the I/O log from this directory PSPEmu can be invoked with the following command line 35 | for replay: 36 | ``` 37 | ./PSPEmu \ 38 | --emulation-mode sys \ # Start with the off chip BL 39 | --cpu-profile ryzen7-1800x \ # Select CPU profile 40 | --flash-rom PRIME-X370-PRO-ASUS-3803.ROM \ # The flash image from ASUS website 41 | --trace-log run.tracelog \ # The log to generate 42 | --timer-real-time \ # Emulated timers tick in realtime 43 | --emulate-devices ccp-v5:flash:timer2 \ # Emulate those devices instead of reading from the I/O log 44 | --iom-log-all-accesses \ # Log all I/O accesses to the trace log 45 | --trace-svcs \ # Trace all syscalls being made 46 | --intercept-svc-6 \ # Intercept debug log syscall 47 | --dbg 4000 \ # Enable GDB stub on port 4000 48 | --io-log-replay proxy-mode.iolog # The I/O log to replay 49 | ``` 50 | -------------------------------------------------------------------------------- /Logs/ryzen7-1800x/off-chip-bl.log: -------------------------------------------------------------------------------- 1 | 2 | *SEC_DBG_MODULE* Entering DebugUnlock module 3 | 4 | 5 | *SEC_DBG_MODULE* Exiting DebugUnlock module 6 | 7 | 8 | *SEC_DBG_MODULE* Entering DebugUnlock module 9 | 10 | 11 | *SEC_DBG_MODULE* Exiting DebugUnlock module 12 | 13 | 14 | Entering security gasket programming application 15 | 16 | 17 | ABL0 - Main ABL Execution 18 | 19 | AGESA MEM - Initial APCB Support 20 | 21 | AGESA MEM - Initial APCB Support 22 | 23 | 24 | Calling ABL 1 BL 25 | 26 | 27 | ABL1 Loaded 28 | 29 | 30 | Slave: ABL, Init Slave states 31 | 32 | Cannot find the APCB BoardID Data: APCB_PSP_TYPE_BOARD_ID_GETTING_METHOD 33 | 34 | AGESA MEM - Initial APCB Support 35 | 36 | 37 | SPD Data Sync 38 | 39 | 40 | Debug Sync 41 | 42 | 43 | Debug Sync Disabled - Die count < = 1 44 | 45 | 46 | Returned from ABL 1 BL 47 | 48 | 49 | Calling ABL 6 BL 50 | 51 | 52 | Starting AGESA 6 BL 53 | 54 | 55 | Slave: ABL, Init Slave states 56 | 57 | 58 | Restore 59 | 60 | 61 | Locate 62 | 63 | 64 | Init 65 | 66 | 67 | Mem Phase 1 Start 68 | 69 | 70 | Mem Phase 1 DqMap, AutoConfig, DctConfig 71 | 72 | 73 | Mem Phase 1 DqMap, AutoConfig, DctConfig 74 | 75 | 76 | Mem Phase 1 PlatSpec 77 | 78 | 79 | Mem Phase 1 PlatSpec 80 | 81 | 82 | Sync All Dies Disabled - Die count < = 1 83 | 84 | 85 | Sync All Dies Disabled - Die count < = 1 86 | 87 | 88 | Mem Phase 1 End 89 | 90 | 91 | Debug Sync 92 | 93 | 94 | Debug Sync Disabled - Die count < = 1 95 | 96 | 97 | Returned from ABL 6 BL 98 | 99 | 100 | Calling ABL 2 BL 101 | 102 | 103 | ABL2 Loaded 104 | 105 | 106 | Mem Phase 2 Start 107 | 108 | 109 | Sync All Dies Disabled - Die count < = 1 110 | 111 | 112 | Sync All Dies Disabled - Die count < = 1 113 | 114 | 115 | Mem Phase 2 Mission Mode and Turnaround 116 | 117 | 118 | Mem Phase 2 Mission Mode and Turnaround 119 | 120 | 121 | Mem Phase 2 End 122 | 123 | 124 | Debug Sync 125 | 126 | 127 | Debug Sync Disabled - Die count < = 1 128 | 129 | 130 | Returned from ABL 2 BL 131 | 132 | 133 | Calling ABL 3 BL 134 | 135 | 136 | ABL3 Loaded 137 | 138 | 139 | Sync All Dies Disabled - Die count < = 1 140 | 141 | 142 | Sync All Dies Disabled - Die count < = 1 143 | 144 | 145 | Sync All Dies Disabled - Die count < = 1 146 | 147 | 148 | Sync All Dies Disabled - Die count < = 1 149 | 150 | 151 | Sync All Dies Disabled - Die count < = 1 152 | 153 | 154 | Sync All Dies Disabled - Die count < = 1 155 | 156 | 157 | Sync All Dies Disabled - Die count < = 1 158 | 159 | 160 | Sync All Dies Disabled - Die count < = 1 161 | 162 | 163 | Sync All Dies Disabled - Die count < = 1 164 | 165 | 166 | A DF table entry 167 | 168 | 169 | A DF table entry 170 | 171 | 172 | A DF table entry 173 | 174 | 175 | A DF table entry 176 | 177 | 178 | A DF table entry 179 | 180 | 181 | A DF table entry 182 | 183 | 184 | A DF table entry 185 | 186 | 187 | A DF table entry 188 | 189 | 190 | A DF table entry 191 | 192 | 193 | A DF table entry 194 | 195 | 196 | A DF table entry 197 | 198 | 199 | A DF table entry 200 | 201 | 202 | A DF table entry 203 | 204 | 205 | Sync All Dies Disabled - Die count < = 1 206 | 207 | 208 | A DF table entry 209 | 210 | 211 | A DF table entry 212 | 213 | 214 | A DF table entry 215 | 216 | 217 | A DF table entry 218 | 219 | 220 | A DF table entry 221 | 222 | 223 | A DF table entry 224 | 225 | 226 | A DF table entry 227 | 228 | 229 | A DF table entry 230 | 231 | 232 | A DF table entry 233 | 234 | 235 | A DF table entry 236 | 237 | 238 | A DF table entry 239 | 240 | 241 | A DF table entry 242 | 243 | 244 | A DF table entry 245 | 246 | 247 | A DF table entry 248 | 249 | 250 | A DF table entry 251 | 252 | 253 | A DF table entry 254 | 255 | 256 | A DF table entry 257 | 258 | 259 | A DF table entry 260 | 261 | 262 | A DF table entry 263 | 264 | 265 | A DF table entry 266 | 267 | 268 | A DF table entry 269 | 270 | 271 | A DF table entry 272 | 273 | 274 | A DF table entry 275 | 276 | 277 | A DF table entry 278 | 279 | 280 | A DF table entry 281 | 282 | 283 | A DF table entry 284 | 285 | 286 | A DF table entry 287 | 288 | 289 | A DF table entry 290 | 291 | 292 | A DF table entry 293 | 294 | 295 | A DF table entry 296 | 297 | 298 | A DF table entry 299 | 300 | 301 | A DF table entry 302 | 303 | 304 | A DF table entry 305 | 306 | 307 | A DF table entry 308 | 309 | 310 | A DF table entry 311 | 312 | 313 | A DF table entry 314 | 315 | 316 | A DF table entry 317 | 318 | 319 | A DF table entry 320 | 321 | 322 | A DF table entry 323 | 324 | 325 | A DF table entry 326 | 327 | 328 | A DF table entry 329 | 330 | 331 | A DF table entry 332 | 333 | 334 | A DF table entry 335 | 336 | 337 | A DF table entry 338 | 339 | 340 | A DF table entry 341 | 342 | 343 | A DF table entry 344 | 345 | 346 | A DF table entry 347 | 348 | 349 | A DF table entry 350 | 351 | 352 | A DF table entry 353 | 354 | 355 | A DF table entry 356 | 357 | 358 | A DF table entry 359 | 360 | 361 | A DF table entry 362 | 363 | 364 | A DF table entry 365 | 366 | 367 | A DF table entry 368 | 369 | 370 | A DF table entry 371 | 372 | 373 | A DF table entry 374 | 375 | 376 | A DF table entry 377 | 378 | 379 | A DF table entry 380 | 381 | 382 | A DF table entry 383 | 384 | 385 | A DF table entry 386 | 387 | 388 | A DF table entry 389 | 390 | 391 | A DF table entry 392 | 393 | 394 | A DF table entry 395 | 396 | 397 | A DF table entry 398 | 399 | 400 | A DF table entry 401 | 402 | 403 | A DF table entry 404 | 405 | 406 | A DF table entry 407 | 408 | 409 | A DF table entry 410 | 411 | 412 | A DF table entry 413 | 414 | 415 | A DF table entry 416 | 417 | 418 | A DF table entry 419 | 420 | 421 | A DF table entry 422 | 423 | 424 | A DF table entry 425 | 426 | 427 | A DF table entry 428 | 429 | 430 | A DF table entry 431 | 432 | 433 | A DF table entry 434 | 435 | 436 | A DF table entry 437 | 438 | 439 | A DF table entry 440 | 441 | 442 | A DF table entry 443 | 444 | 445 | A DF table entry 446 | 447 | 448 | A DF table entry 449 | 450 | 451 | A DF table entry 452 | 453 | 454 | A DF table entry 455 | 456 | 457 | A DF table entry 458 | 459 | 460 | A DF table entry 461 | 462 | 463 | A DF table entry 464 | 465 | 466 | A DF table entry 467 | 468 | 469 | A DF table entry 470 | 471 | 472 | A DF table entry 473 | 474 | 475 | A DF table entry 476 | 477 | 478 | A DF table entry 479 | 480 | 481 | A DF table entry 482 | 483 | 484 | A DF table entry 485 | 486 | 487 | A DF table entry 488 | 489 | 490 | A DF table entry 491 | 492 | 493 | A DF table entry 494 | 495 | 496 | A DF table entry 497 | 498 | 499 | A DF table entry 500 | 501 | 502 | A DF table entry 503 | 504 | 505 | A DF table entry 506 | 507 | 508 | A DF table entry 509 | 510 | 511 | A DF table entry 512 | 513 | 514 | A DF table entry 515 | 516 | 517 | A DF table entry 518 | 519 | 520 | A DF table entry 521 | 522 | 523 | A DF table entry 524 | 525 | 526 | A DF table entry 527 | 528 | 529 | A DF table entry 530 | 531 | 532 | A DF table entry 533 | 534 | 535 | A DF table entry 536 | 537 | 538 | A DF table entry 539 | 540 | 541 | A DF table entry 542 | 543 | 544 | A DF table entry 545 | 546 | 547 | A DF table entry 548 | 549 | 550 | A DF table entry 551 | 552 | 553 | A DF table entry 554 | 555 | 556 | A DF table entry 557 | 558 | 559 | A DF table entry 560 | 561 | 562 | A DF table entry 563 | 564 | 565 | A DF table entry 566 | 567 | 568 | A DF table entry 569 | 570 | 571 | A DF table entry 572 | 573 | 574 | A DF table entry 575 | 576 | 577 | A DF table entry 578 | 579 | 580 | A DF table entry 581 | 582 | 583 | A DF table entry 584 | 585 | 586 | A DF table entry 587 | 588 | 589 | A DF table entry 590 | 591 | 592 | A DF table entry 593 | 594 | 595 | A DF table entry 596 | 597 | 598 | A DF table entry 599 | 600 | 601 | A DF table entry 602 | 603 | 604 | A DF table entry 605 | 606 | 607 | A DF table entry 608 | 609 | 610 | A DF table entry 611 | 612 | 613 | A DF table entry 614 | 615 | 616 | A DF table entry 617 | 618 | 619 | A DF table entry 620 | 621 | 622 | A DF table entry 623 | 624 | 625 | A DF table entry 626 | 627 | 628 | A DF table entry 629 | 630 | 631 | A DF table entry 632 | 633 | 634 | A DF table entry 635 | 636 | 637 | A DF table entry 638 | 639 | 640 | A DF table entry 641 | 642 | 643 | A DF table entry 644 | 645 | 646 | A DF table entry 647 | 648 | 649 | A DF table entry 650 | 651 | 652 | A DF table entry 653 | 654 | 655 | A DF table entry 656 | 657 | 658 | A DF table entry 659 | 660 | 661 | A DF table entry 662 | 663 | 664 | A DF table entry 665 | 666 | 667 | A DF table entry 668 | 669 | 670 | A DF table entry 671 | 672 | 673 | A DF table entry 674 | 675 | 676 | A DF table entry 677 | 678 | 679 | A DF table entry 680 | 681 | 682 | A DF table entry 683 | 684 | 685 | A DF table entry 686 | 687 | 688 | A DF table entry 689 | 690 | 691 | A DF table entry 692 | 693 | 694 | A DF table entry 695 | 696 | 697 | A DF table entry 698 | 699 | 700 | A DF table entry 701 | 702 | 703 | A DF table entry 704 | 705 | 706 | A DF table entry 707 | 708 | 709 | Mem Phase 3 Start 710 | 711 | 712 | Mem Phase 3 Complete 713 | 714 | 715 | Mem Phase 3 End 716 | 717 | 718 | Debug Sync 719 | 720 | 721 | Debug Sync Disabled - Die count < = 1 722 | 723 | 724 | Returned from ABL 3 BL 725 | 726 | 727 | Calling ABL 4 BL 728 | 729 | 730 | Starting AGESA 4 BL 731 | 732 | 733 | Slave: ABL, Init Slave states 734 | 735 | 736 | Restore 737 | 738 | 739 | Locate 740 | 741 | 742 | Init 743 | 744 | 745 | A DF table entry 746 | 747 | 748 | A DF table entry 749 | 750 | 751 | A DF table entry 752 | 753 | 754 | A DF table entry 755 | 756 | 757 | A DF table entry 758 | 759 | 760 | A DF table entry 761 | 762 | 763 | A DF table entry 764 | 765 | 766 | A DF table entry 767 | 768 | 769 | A DF table entry 770 | 771 | 772 | A DF table entry 773 | 774 | 775 | A DF table entry 776 | 777 | 778 | A DF table entry 779 | 780 | 781 | A DF table entry 782 | 783 | 784 | A DF table entry 785 | 786 | 787 | A DF table entry 788 | 789 | 790 | A DF table entry 791 | 792 | 793 | A DF table entry 794 | 795 | 796 | A DF table entry 797 | 798 | 799 | A DF table entry 800 | 801 | 802 | A DF table entry 803 | 804 | 805 | A DF table entry 806 | 807 | 808 | A DF table entry 809 | 810 | 811 | A DF table entry 812 | 813 | 814 | A DF table entry 815 | 816 | 817 | A DF table entry 818 | 819 | 820 | A DF table entry 821 | 822 | 823 | A DF table entry 824 | 825 | 826 | A DF table entry 827 | 828 | 829 | A DF table entry 830 | 831 | 832 | A DF table entry 833 | 834 | 835 | A DF table entry 836 | 837 | 838 | A DF table entry 839 | 840 | 841 | A DF table entry 842 | 843 | 844 | A DF table entry 845 | 846 | 847 | A DF table entry 848 | 849 | 850 | A DF table entry 851 | 852 | 853 | A DF table entry 854 | 855 | 856 | A DF table entry 857 | 858 | 859 | A DF table entry 860 | 861 | 862 | A DF table entry 863 | 864 | 865 | A DF table entry 866 | 867 | 868 | Sync All Dies Disabled - Die count < = 1 869 | 870 | 871 | AGESA MEM - Memory test ready 872 | 873 | 874 | ABL Mem Test - Enabled 875 | 876 | 877 | Write Pattern 878 | 879 | 880 | Read Pattern 881 | 882 | 883 | Agesa Mem Test Complete 884 | 885 | 886 | Memory Test Results sync Start 887 | 888 | 889 | Mem Test Sync Disabled - Die count < = 1 890 | 891 | 892 | Create APOB 893 | 894 | 895 | AGESA MEM - Multi-Die - APOB Support 896 | 897 | 898 | APOB Sync Disabled - Die count < = 1 899 | 900 | 901 | Debug Sync 902 | 903 | 904 | Debug Sync Disabled - Die count < = 1 905 | 906 | 907 | Returned from ABL 4 BL 908 | 909 | 910 | All ABLs Complete (pass control back to PSP BL 911 | 912 | 913 | -------------------------------------------------------------------------------- /Logs/ryzen7-1800x/proxy-mode.iolog.bz2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PSPReverse/psp-docs/c70d3520b02b3be73937c9068327de2cdb5dd430/Logs/ryzen7-1800x/proxy-mode.iolog.bz2 -------------------------------------------------------------------------------- /Logs/ryzen7-1800x/psp-emu.tracelog.bz2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PSPReverse/psp-docs/c70d3520b02b3be73937c9068327de2cdb5dd430/Logs/ryzen7-1800x/psp-emu.tracelog.bz2 -------------------------------------------------------------------------------- /Presentations/36c3/36c3-10942-uncover_understand_own_-_regaining_control_over_your_amd_cpu.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PSPReverse/psp-docs/c70d3520b02b3be73937c9068327de2cdb5dd430/Presentations/36c3/36c3-10942-uncover_understand_own_-_regaining_control_over_your_amd_cpu.pdf -------------------------------------------------------------------------------- /Presentations/BlackHat2020/us-20-BuhrenEichner-All-you-ever-wanted-to-know-about-the-AMD-Platform-Security-Processor-and-were-Afraid-to-Emulate.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PSPReverse/psp-docs/c70d3520b02b3be73937c9068327de2cdb5dd430/Presentations/BlackHat2020/us-20-BuhrenEichner-All-you-ever-wanted-to-know-about-the-AMD-Platform-Security-Processor-and-were-Afraid-to-Emulate.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # psp-docs 2 | Documentation about the reversed engineered PSP interfaces/hardware components. 3 | -------------------------------------------------------------------------------- /SmnRegions.md: -------------------------------------------------------------------------------- 1 | # SMN (System management network) Address map 2 | 3 | ## Description 4 | 5 | The system management network enables the PSP to talk to other system components on the package. 6 | It uses a distinctive address space and the PSP implements an interface to map those addresses 7 | into the PSP memory space so the registers of various devices can be accessed. 8 | 9 | This map documents accessed addresses and their purpose if possible. 10 | 11 | ## CCX source to target mapping 12 | 13 | Each CCX has its own set of registers but one CCX can access the range of another CCX by adding the offset from the following table 14 | (the block offsets are stored in global PSP memory): 15 | 16 | +-----------+------------+------------+------------+------------+------------+------------+------------+------------+ 17 | | tgt CCX ->| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 18 | +-----------| | | | | | | | | 19 | | src CCX | | | | | | | | | 20 | | v | | | | | | | | | 21 | +-----------+------------+------------+------------+------------+------------+------------+------------+------------+ 22 | | 0 | 0x0 | 0xf0000000 | 0xe0000000 | 0xd0000000 | 0xc0000000 | 0x30000000 | 0x20000000 | 0x10000000 | 23 | | 1 | 0x10000000 | 0x0 | 0xf0000000 | 0xe0000000 | 0xd0000000 | 0xc0000000 | 0x30000000 | 0x20000000 | 24 | | 2 | 0x20000000 | 0x10000000 | 0x0 | 0xf0000000 | 0xe0000000 | 0xd0000000 | 0xc0000000 | 0x30000000 | 25 | | 3 | 0x30000000 | 0x20000000 | 0x10000000 | 0x0 | 0xf0000000 | 0xe0000000 | 0xd0000000 | 0xc0000000 | 26 | | 4 | 0xc0000000 | 0x30000000 | 0x20000000 | 0x10000000 | 0x0 | 0xf0000000 | 0xe0000000 | 0xd0000000 | 27 | | 5 | 0xd0000000 | 0xc0000000 | 0x30000000 | 0x20000000 | 0x10000000 | 0x0 | 0xf0000000 | 0xe0000000 | 28 | | 6 | 0xe0000000 | 0xd0000000 | 0xc0000000 | 0x30000000 | 0x20000000 | 0x10000000 | 0x0 | 0xf0000000 | 29 | | 7 | 0xf0000000 | 0xe0000000 | 0xd0000000 | 0xc0000000 | 0x30000000 | 0x20000000 | 0x10000000 | 0x0 | 30 | +-----------+------------+------------+------------+------------+------------+------------+------------+------------+ 31 | 32 | Example: 33 | Suppose you're executing on CCX ID 0 and want to access the register at SMN offset 0x1c880 on CCX 7. From the table 34 | the block for CCX 7 starts at offset 0xf0000000 on CCX 0 which added to the offset 0x1c880 yields 0xf001c880 resulting 35 | in the final SMN address for that register. 36 | 37 | Current state: 38 | It is not possible to access all SMN regions on a different CCX from the master PSP, most accesses seem to cause a system reset. 39 | Only the region for the VEK seems to be exempt from this rule as the SEV firmware programs all AES engines only from the master PSP. 40 | Slave CCXs seem to have no way to access regions in the SMN network except its own region. 41 | 42 | ## Address Map 43 | 44 | This address map collects information gathered about various SMM addresses and their purpose where it could be infered. 45 | 46 | Legend for Table: 47 | - Region = The base address of the region in the SMN (per PSP) 48 | - Size = Size of the whole region in bytes 49 | - WP = Flag whether the region is write protected by default and requires SMU message {0x14, 0x1} to disable the write protection 50 | Write protection should be enabled afterwards using SMU message {0x14, 0x0} to prevent accidental writes. 51 | Writes to this region will cause a system reset when write protection is enabled. 52 | - + = Write protected by default 53 | - - = No write protection 54 | - ? = Write protection status unknown 55 | - MPsp = Flag whether the master PSP can access this region on another CCX without poking the owning slave PSP. 56 | - + = Master PSP has access 57 | - - = Master PSP has no access 58 | - ? = Status unknown 59 | 60 | Legend for Register Description: 61 | - ? = Unknown purpose 62 | - x = Not used/Reserved 63 | - e = Enable/Disable bit 64 | - a = Some part of an address (see description) 65 | - d = Some arbitrary data (see description) 66 | - s = See functional description of the register for the purpose of this bit. 67 | 68 | | Region | Size | WP | MPsp | Offset | RegSz | Description | Register description | 69 | |------------|------|----|------|--------|--------|----------------------------------------------------------------------------------------|----------------------------------| 70 | | 0x0001c760 | 32 | ? | ? | | | Seems to be related to memory protection slots, see psp_dev_smn_addr_0x0001c760_init | | 71 | | | | | | 0x00 | 32bit | Register 0 | ???????????????????????????????? | 72 | | | | | | ... | ... | Register 1 - 7 | ... | 73 | |------------+------+----+------+--------+--------+----------------------------------------------------------------------------------------+----------------------------------| 74 | | 0x0001c880 | 128 | + | - | | | Memory protection slots | | 75 | | | | | | 0x00 | 32bit | Slot 0: Start address of protected region X86PADDR[47:20] + 4 flags | aaaaaaaaaaaaaaaaaaaaaaaaaaaa???? | 76 | | | | | | 0x04 | 32bit | Slot 0: End address (inclusive) of protected region X86PADDR[47:20] + 4 flags | aaaaaaaaaaaaaaaaaaaaaaaaaaaa???? | 77 | | | | | | 0x08 | 32bit | Slot 0: Control register (seen 0x600000a | 0x6000006) | ???????????????????????????????e | 78 | | | | | | 0x0c | 32bit | Slot 0: Unused/Reserved (no access observed anywhere) | xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx | 79 | | | | | | ... | ... | Slot 1 - 6 | ... | 80 | | | | | | 0x70 | 32bit | Slot 7: Start address... | | 81 | | | | | | 0x74 | 32bit | Slot 7: End address... | | 82 | | | | | | 0x78 | 32bit | Slot 7: Control register... | | 83 | | | | | | 0x7c | 32bit | Slot 7: Unused/Reserved... | | 84 | |------------+------+----+------+--------+--------+----------------------------------------------------------------------------------------+----------------------------------| 85 | | 0x00050a00 | 256 | + | + | | | Programs the AES engine with the EKs for the individual ASIDs, first memory channel | | 86 | | | | | | 0x00 | 128bit | ASID 0 EK | dddddddddddddddddddddddddddddddd | 87 | | | | | | 0x10 | 128bit | ASID 1 EK | dddddddddddddddddddddddddddddddd | 88 | | | | | | 0x20 | 128bit | ASID 2 EK | dddddddddddddddddddddddddddddddd | 89 | | | | | | ... | ... | ASID 3 - 15 EK | ... | 90 | |------------+------+----+------+--------+--------+----------------------------------------------------------------------------------------+----------------------------------| 91 | | 0x00054a00 | 256 | + | + | | | Programs the AES engine with the EKs for the individual ASIDs, second memory channel | | 92 | | | | | | 0x00 | 128bit | ASID 0 EK | dddddddddddddddddddddddddddddddd | 93 | | | | | | 0x10 | 128bit | ASID 1 EK | dddddddddddddddddddddddddddddddd | 94 | | | | | | 0x20 | 128bit | ASID 2 EK | dddddddddddddddddddddddddddddddd | 95 | | | | | | ... | ... | ASID 3 - 15 EK | ... | 96 | |------------+------+----+------+--------+--------+----------------------------------------------------------------------------------------+----------------------------------| 97 | | 0x00059834 | 32 | - | ? | | | Contains maximum SOC temperature values (the biggest one out of the values is picked?) | | 98 | | | | | | 0x00 | 32bit | SOC Max Temp 0 (extracted value - 0x188) ?= max T in F (0x282 - 0x188 = 250F > ~121°C) | ssssssssssssssssssss???????????? | 99 | | | | | | ... | ... | SOC Max Temp 1 - 7 | ... | 100 | |------------+------+----+------+--------+--------+----------------------------------------------------------------------------------------+----------------------------------| 101 | | 0x03b10700 | 24 | - | ? | | | SMU mailbox interface | | 102 | | | | | | 0x00 | 32bit | Argument 0 | dddddddddddddddddddddddddddddddd | 103 | | | | | | 0x04 | 32bit | Status/Response | ssssssssssssssssssssssssssssssss | 104 | | | | | | 0x08 | 32bit | Unknown (Argument 1?) | ???????????????????????????????? | 105 | | | | | | 0x0c | 32bit | Unknown (Argument 2?) | ???????????????????????????????? | 106 | | | | | | 0x10 | 32bit | Unknown (Argument 3?) | ???????????????????????????????? | 107 | | | | | | 0x14 | 32bit | Message identifier | dddddddddddddddddddddddddddddddd | 108 | 109 | 110 | Deprecated (convert to new format): 111 | 112 | SMN address Region size Description 113 | 0x0004971c 4 114 | 0x0102e814 4 115 | 0x02d01380 4 Used in handle_dev_irq_0xf_maybe_watchdog() 116 | 0x02dc4000 32 Plays a role in the flash config (maybe SPI speed slection as well?) 117 | 0x038105a0 Plays a role in MCM communication, psp_mcm_master_to_slave_something() 118 | 0x03b10034 4 Plays a role in taking MP1 out of reset 119 | 120 | ## Functional description 121 | 122 | ### 0x0001c880: Memory protection slots 123 | 124 | The DRAM controller offers 8 "memory protection" slots which can be used to revoke access from the x86 core (and possibly other entities). 125 | They are programmed by the PSP. So far only slot 0 and 1 seem to be used. Slot 0 covers the SMM region while slot 1 is holding the TMR region 126 | for SEV-ES when enabled by the host. 127 | One slot is configured by three registers, the first one holds the 1MB aligned physical address of the start of the region to protect. For current 128 | hardware which implements 48bits bits [47:20] of the physical address are used to program the register. The remaining 4 LSBs contain some flags which purpose is 129 | unknown so far, they could configure some caching or maybe some additional properties of the region (like whether to return 0xff or 0x00 on a read and what to do with a write). 130 | The second register holds the last remaining physical address still belonging to the protected region (inclusive) and like the first register holds only bits [47:20] + some 131 | unknown flags in the 4 LSBs. If a single 1MB region should be protected The address bits of the start and end register are equal. 132 | Register three seems to be some sort of control register where only the purpose of bit 0 is known. Bit 0 toggles the protection on (1) or off (0), the remaining function of the bits remain 133 | unknown. 134 | 135 | ### 0x03b10700: SMU - System management unit 136 | 137 | @todo Find out whether there is only one SMU or one per CCX too. 138 | 139 | The SMU is mainly used for power management related tasks but it also controls write access to the System Management Network (SMN), at least 140 | writes for certain SMN ranges cause a system reset without sending the proper SMU message beforehand. 141 | 142 | Bit 0 of the Status/Response register indicates whether a request is currently pending. 1 means that a new request can be issued. The following is the usual 143 | sequence in pseudo code to send a message to the SMU: 144 | 145 | while (0x03b10700[1] & 0x1 == 0); 146 | 0x03b10700[1] = 0; 147 | 0x03b10700[0] = Argument 0; 148 | 0x03b10700[5] = idMsg; 149 | while (0x03b10700[1] & 0x1 == 0); 150 | if (0x03b10700[1] != 1) 151 | error; 152 | else 153 | success; 154 | status/response = 0x03b10700[0]; 155 | 156 | Messages found: 157 | - 0x1 Unknown, issued by the PSP during initialization 158 | - uArg0: 3 159 | - 0x4 Unknown, issued by the PSP during initialization 160 | - uArg0: Deduced by a called function 161 | - 0x6 Unknown 162 | - uArg0: SMU firmware region [End]|Start[31:16] 163 | - 0x9 Unknown 164 | - uArg0: 1 165 | - 0x14 Controls SMN write protection for certain regions 166 | - uArg0: 1 - Disable write protection 0 - Enable write protection 167 | 168 | Sources: https://fahrplan.events.ccc.de/congress/2014/Fahrplan/system/attachments/2503/original/ccc-final.pdf 169 | 170 | ### 0x00050a00, 0x00054a00: DRAM Controller AES engine 171 | 172 | The DRAM controller has a builtin AES encryption/decryption engine for the SME and SEV features. Each CCD controls two memory channels and should therefore have two controllers. 173 | The encryption key, of a VM for example, is tied to a specific ASID (0 is usually the host itself). The PSP programs the VEK into the corresponding slot of both DRAM controllers to activate 174 | AES encryption for the given ASID. The key is fixed to a 128bit length. This range can be accessed from the master PSP without poking the slaves. 175 | 176 | ### 0x00059834: Maximum SOC temperatures 177 | 178 | Acess was observed in the AR3B module in function dxioIfGetMaxSOCTemperature(). Looks like it contains 8 values which are in Fahrenheit and offset by 0x188, reading the values and 179 | calculating the values gives around 120-121°C which looks reasonable. The function reads all 8 values and takes the biggest temperature returning it minus the offset. 180 | -------------------------------------------------------------------------------- /masterthesis-eichner-psp-2020.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PSPReverse/psp-docs/c70d3520b02b3be73937c9068327de2cdb5dd430/masterthesis-eichner-psp-2020.pdf -------------------------------------------------------------------------------- /mmio_regions.txt: -------------------------------------------------------------------------------- 1 | MMIO address 2 | 3 | -- CCP device v5? 4 | 0x03000004 CMD5_QUEUE_PRIO_OFFSET 5 | * writes: 6 | start_ccp_cmd: *0x03000004 = *0x03000004 & ~(7 << uQueueNr * 3) | dwParmUnk3 << uQueueNr * 3; 7 | FUN_00007dc4: *0x03000004 = *(undefined4 *)(iParm2 + 0xfc0); 8 | * reads: 9 | FUN_0000848c: *(undefined4 *)(iParm2 + 0xfc0) = *0x03000004; 10 | 0x03000008 CMD5_REQID_CONFIG_OFFSET 11 | * writes: 12 | FUN_00007dc4: *0x03000008 = *(undefined4 *)(iParm2 + 0xfd0); 13 | * reads: 14 | FUN_0000848c: *(undefined4 *)(iParm2 + 0xfc8) = *DAT_000085a0; 15 | 0x0300000c TRNG_OUT_REG 16 | * reads: 17 | init_some_device_maybe: local_18 = *0x0300000c; 18 | 0x03000010 CMD5_CMD_TIMEOUT_OFFSET 19 | * reads: 20 | FUN_00007dc4 21 | FUN_0000848c 22 | 0x03000014 23 | * reads: 24 | FUN_0000848c 25 | 0x03000018 LSB_PUBLIC_MASK_LO_OFFSET 26 | * writes: 27 | FUN_00007dc4 28 | * reads: 29 | FUN_0000848c 30 | 0x0300001c LSB_PUBLIC_MASK_HI_OFFSET 31 | * reads: 32 | FUN_0000848c 33 | 0x03000020 LSB_PRIVATE_MASK_LO_OFFSET 34 | * reads: 35 | FUN_0000848c 36 | 0x03000024 LSB_PRIVATE_MASK_HI_OFFSET 37 | * reads: 38 | FUN_0000848c 39 | 40 | -- CCP dev first queue registers 41 | 0x03001000 CMD5_Q_CONTROL_BASE 42 | 0x03001004 CMD5_Q_TAIL_LO_BASE 43 | 0x03001008 CMD5_Q_HEAD_LO_BASE 44 | 0x03001100 CMD5_Q_STATUS_BASE 45 | 46 | -- Dev3? 47 | 0x03006000 48 | 0x03006008 49 | 0x03006020 50 | 0x03006024 51 | 0x0300603c 52 | 0x03006040 53 | 0x0300604c 54 | 0x03006054 55 | 56 | -- Dev4? 57 | 0x03010004 58 | 59 | 0x0301003c 60 | 0x03010040 61 | 62 | -- Dev5? 63 | 0x03010104 64 | * reads: 65 | only_referenced_from_main: iVar4 = *0x03010104; 66 | FUN_00004690: bVar6 = (DAT_00004718 & ~*0x03010104) == 0; 67 | is_any_of_two_bits_in_mmio_reg_clear: if ((0x00080002 & ~*0x03010104) != 0) 68 | is_any_of_two_bits_in_mmio_reg_clear_v2: if ((0x00080002 & ~*0x03010104) != 0) 69 | init_some_dev_in_mmio: if ((*DAT_000059d0 >> 0x1f & ~(uint)((0x00080002 & ~*0x03010104) == 0)) == 0) { 70 | FUN_0000710c: if ((0x00080002 & ~*0x03010104) == 0) { 71 | FUN_0000a8c0: if ((((0x00080002 & ~*0x03010104) == 0) || (*(int *)(iParm1 + 0x30) != 0)) && 72 | FUN_000093b0: if (((0x00080002 & ~*0x03010104) == 0) && (*DAT_000093dc << 0x1d < 0)) { 73 | FUN_0000b338: (bVar4 = (0x00080002 & ~*0x03010104) == 0, dwParamUnk1 = (uint32_t)bVar4, bVar4)) { 74 | 75 | 0x03010300 76 | 0x030103b0 77 | 0x030103c0 <- INTR pending? bit 0 => 1 not pending 78 | 0x030103c4 <- INTR source pending next? 79 | 80 | 0x03010400 81 | 82 | -- Some timer/count device (taken from psp_sleep_maybe()) 83 | 0x03010424 <- Control register 84 | 0x03010428 85 | 0x0301042c 86 | 0x03010430 87 | 0x03010434 88 | 0x03010438 89 | 0x0301043c 90 | 0x03010440 91 | 0x03010444 <- Counted ticks register maybe 92 | 93 | -- Dev6? 94 | 0x03010544 95 | 0x03010560 96 | 0x03010570 <- Mailbox registers start? 97 | 0x03010580 98 | 0x03010594 99 | 0x03010598 100 | 0x030105a0 101 | 0x030105a4 102 | 0x030105c4 103 | 0x030105f0 104 | 0x030105fc 105 | 106 | 0x03010618 107 | 0x0301061c 108 | 109 | 0x0301071c 110 | 111 | -------------------------------------------------------------------------------- /svc_syscall_table.txt: -------------------------------------------------------------------------------- 1 | === SVC syscall table provided by PSP === 2 | 3 | 0x00: 4 | Description: Exits the userspace and cleans it up, does not return to userspace. 5 | Arguments: N/A 6 | Returns: N/A 7 | Used by: 8 | * SEV 9 | * DebugUnlock 10 | * DramTraining 11 | 12 | 0x01: 13 | Description: Initializes userspace memory and maps stack 14 | Arguments: 15 | r0: 16 | r1: 17 | r2: 18 | Returns: 19 | r0: 20 | Used by: 21 | * SEV 22 | * DebugUnlock 23 | * DramTraining 24 | 25 | 0x02: 26 | Description: Allows the app to load another directory entry from the flash 27 | Arguments: 28 | r0: Directory entry type/App ID 29 | r1: Userspace pointer to load the entry to. 30 | r2: Size of the userspace buffer. 31 | Returns: 32 | r0: PSP status code. 33 | Used by: 34 | 35 | 0x03: 36 | Description: Maps an SMN (System management network) address into the PSP address space, extended version. 37 | Arguments: 38 | r0: The SMN address to map. 39 | r1: Some CCD id (not used by fw) 40 | Returns: 41 | r0: PSP virtual address to access the SMN address. 42 | Used by: 43 | * SEV 44 | 45 | 0x04: 46 | Description: Maps an SMN (System management network) address into the PSP address space. 47 | Arguments: 48 | r0: The SMN address to map. 49 | Returns: 50 | r0: PSP virtual address to access the SMN address. 51 | Used by: 52 | * DebugUnlock 53 | * DramTraining 54 | 55 | 0x05: 56 | Description: Unmaps a previously mapped SMN (System management network) address. 57 | Arguments: 58 | r0: PSP virtual address of the mapped SMN region to unmap. 59 | Returns: 60 | r0: PSP status code. 61 | Used by: 62 | * SEV 63 | * DebugUnlock 64 | * DramTraining 65 | 66 | 0x06: 67 | Description: A logging syscall taking a zero terminated ASCII string, not provided by the stock firmware 68 | Arguments: 69 | r0: Address of the string in userspace. 70 | Returns: 71 | r0: 72 | Used by: 73 | * DebugUnlock 74 | * DramTraining 75 | 76 | 0x07: 77 | Description: Seems to map an x86 host physical memory address into the PSP memory space and makes it accessible to userspace. 78 | Arguments: 79 | r0: Low 32bit of the x86 physical address 80 | r1: High 32bit of the x86 physical address 81 | Returns: 82 | r0: PSP virtual address accessible by userspace 83 | Used by: 84 | 85 | 0x08: 86 | Description: Unmap a x86 host physical memory address by the given PSP virtual address 87 | Arguments: 88 | r0: PSP virtual address returned by syscal 0x07 89 | Returns: 90 | r0: Status code 91 | Used by: 92 | * SEV 93 | 94 | 0x09: 95 | Description: Seems to copy data from the given x86 host physical memory address to PSP local memory. 96 | Arguments: 97 | r0: Low 32bit of the x86 physical address to copy from 98 | r1: High 32bit of the x86 physical address to copy from 99 | r2: PSP virtual address to copy to 100 | r3: Number of bytes to copy 101 | Returns: 102 | r0: Status code. 103 | Used by: 104 | * AR3B (PCI device access?) 105 | 106 | 0x0a: 107 | Description: Writes a status code or copies a value to a given x86 host physical memory address. 108 | Arguments: 109 | r0: Low 32bit of the x86 physical address to copy to 110 | r1: High 32bit of the x86 physical address to copy to 111 | r2: Data item to copy (1, 2 or 4 bytes) 112 | r3: Number of bytes to write 113 | Returns: 114 | r0: Status code. 115 | Used by: 116 | * DramTraining 117 | * 0BAR / ABL0 118 | * AR3B (PCI device access?) 119 | 120 | 0x0b: 121 | Description: Seems to provide an interface for invalidating/cleaning memory. 122 | Arguments: 123 | r0: 124 | r1: 125 | r2: 126 | Returns: 127 | r0: Status code. 128 | Used by: 129 | 130 | 0x0c: 131 | Description: Provides an interface to the CCP for offloading cryptographic work. 132 | Arguments: 133 | r0: Userspace pointer to a request buffer maybe (@todo Figure out format of request buffer) 134 | Returns: 135 | r0: Status code. 136 | Used by: 137 | * DebugUnlock 138 | 139 | 0x0d: 140 | Description: 141 | Arguments: 142 | r0: 143 | Returns: 144 | r0: Status code. 145 | Used by: 146 | * SEV 147 | * DebugUnlock 148 | 149 | 0x0e: 150 | Description: 151 | Arguments: 152 | r0: 153 | Returns: 154 | r0: Status code. 155 | Used by: 156 | * DebugUnlock 157 | 158 | 0x0f: 159 | Description: 160 | Arguments: 161 | r0: 162 | Returns: 163 | r0: Status code. 164 | Used by: 165 | * DebugUnlock 166 | 167 | 0x10: 168 | Description: 169 | Arguments: 170 | r0: 171 | Returns: 172 | r0: Status code. 173 | Used by: 174 | 175 | 0x11: 176 | Description: Related to inter die communication 177 | Arguments: 178 | r0: Always 0 179 | r1: Some function to execute on other dies maybe 180 | r2: 181 | r3: 182 | Returns: 183 | r0: Status code. 184 | Used by: 185 | 186 | 0x12: 187 | Description: Related to inter die communication 188 | Arguments: 189 | r0: Always 0 190 | r1: Some function to execute on other dies maybe 191 | r2: 192 | r3: 193 | Returns: 194 | r0: Status code. 195 | Used by: 196 | 197 | 0x13: 198 | Description: Related to inter die communication 199 | Arguments: 200 | r0: Always 0 201 | r1: Some function to execute on other dies maybe 202 | r2: 203 | r3: 204 | Returns: 205 | r0: Status code. 206 | Used by: 207 | * DramTraining 208 | 209 | 0x14: 210 | Description: Related to inter die communication 211 | Arguments: 212 | r0: Always 0 213 | r1: Some function to execute on other dies maybe 214 | r2: 215 | r3: 216 | Returns: 217 | r0: Status code. 218 | Used by: 219 | * DramTraining 220 | 221 | 0x15: 222 | Description: 223 | Arguments: 224 | r0: 225 | r1: 226 | Returns: 227 | r0: Status code. 228 | Used by: 229 | 230 | 0x16: 231 | Description: 232 | Arguments: 233 | r0: 234 | Returns: 235 | r0: Status code. 236 | Used by: 237 | 238 | 0x17: 239 | Description: Related to inter die communication 240 | Arguments: 241 | r0: Always 0 242 | r1: Some function to execute on other dies maybe 243 | r2: 244 | r3: 245 | Returns: 246 | r0: Status code. 247 | Used by: 248 | * DramTraining 249 | 250 | 0x18: 251 | Description: Related to inter die communication 252 | Arguments: 253 | r0: Always 0 254 | r1: Some function to execute on other dies maybe 255 | r2: 256 | r3: 257 | Returns: 258 | r0: Status code. 259 | Used by: 260 | * DramTraining 261 | 262 | 0x19: 263 | Description: 264 | Arguments: 265 | r0: 266 | Returns: 267 | r0: Status code. 268 | Used by: 269 | * DramTraining 270 | 271 | 0x1a: 272 | Description: Not provided by the PSP firmware 273 | Arguments: 274 | Returns: 275 | Used by: 276 | * DebugUnlock 277 | 278 | 0x1b: 279 | Description: Busy wait until the given amount of ticks has passed. 280 | Arguments: 281 | r0: The amount of ticks to wait (in 10 nano second increments). 282 | Returns: 283 | r0: Status code. 284 | Used by: 285 | * DramTraining 286 | Remarks: 287 | 1 tick seems to correspond to a timespan of 10ns which indicates that the clock 288 | the counter is running on is operated with 100MHz (or a it is scaled down at some point). 289 | 290 | 0x1c: 291 | Description: Determines the boot mode of the system (cold boot vs warm resume) 292 | Arguments: 293 | r0: Pointer to a a 32bit memory location holding the boot mode enum on return. 294 | Returns: 295 | r0: Status code. 296 | Used by: 297 | * 0BAR / ABL0 298 | 299 | 0x1d: 300 | Description: 301 | Arguments: 302 | r0: 303 | r1: 304 | r2: 305 | Returns: 306 | r0: Status code. 307 | Used by: 308 | 309 | 0x1e: 310 | Description: 311 | Arguments: 312 | r0: 313 | r1: 314 | r2: 315 | r3: 316 | Returns: 317 | r0: Status code. 318 | Used by: 319 | 320 | 0x1f: 321 | Description: 322 | Arguments: 323 | r0: 324 | r1: 325 | r2: 326 | Returns: 327 | r0: Status code. 328 | Used by: 329 | * DebugUnlock 330 | 331 | 0x20: 332 | Description: Copies a user supplied buffer to PSP supervisor memory at address 0x0000d810. 333 | Arguments: 334 | r0: Some pointer to a 32byte buffer. 335 | Returns: 336 | r0: Status code. 337 | Used by: 338 | * DebugUnlock 339 | 340 | 0x21: 341 | Description: 342 | Arguments: 343 | r0: 344 | r1: 345 | Returns: 346 | r0: Status code. 347 | Used by: 348 | 349 | 0x22: 350 | Description: 351 | Arguments: 352 | r0[8]: 353 | r1[8]: 354 | r2: 355 | Returns: 356 | r0: Status code. 357 | Used by: 358 | 359 | 0x23: 360 | Description: 361 | Arguments: 362 | r0: 363 | Returns: 364 | r0: Status code. 365 | Used by: 366 | 367 | 0x24: 368 | Description: 369 | Arguments: 370 | r0: 371 | Returns: 372 | r0: Status code. 373 | Used by: 374 | 375 | 0x25: 376 | Description: Maps a x86 host physical memory address into the PSP address space. 377 | Arguments: 378 | r0: Low 32bit of the x86 physical address to copy from 379 | r1: High 32bit of the x86 physical address to copy from 380 | r2: Maybe some channel number to identify the controller to use 381 | Returns: 382 | r0: PSP virtual address on success, NULL on error. 383 | Used by: 384 | * SEV 385 | 386 | 0x26: 387 | Description: Copies data from x86 host memory to PSP local memory. 388 | Arguments: 389 | r0: Userspace pointer to the request structure (see, PSPSVC0x26REQ in Ghidra) 390 | Returns: 391 | r0: Status code. 392 | Used by: 393 | * DramTraining 394 | 395 | 0x27: 396 | Description: Writes a status code or data value from PSP local memory to x86 host memory. 397 | Arguments: 398 | r0: Userspace pointer to the request structure (see remarks) 399 | Returns: 400 | r0: Status code. 401 | Used by: 402 | * DramTraining 403 | * AR3B 404 | Remarks: 405 | Request structure: 406 | { 407 | X86PADDR PhysX86AddrDst; /**< Physical x86 address of the destination to write */ 408 | PSPADDR PspAddrSrc; /**< PSP memory address where the value is store */ 409 | uint32_t cbWrite; /**< How much to write */ 410 | uint32_t enmMemTarget /**< Memory target type (4 = normal DRAM, 6 = special memory region where some peripherals seem to be mapped) */ 411 | } 412 | 413 | Observed address value pairs written: 414 | 0xfffdfc000cf9: 0xe (1 byte) /**< System reset issued by AR3B on memory overclock error. */ 415 | 416 | 0x28: 417 | Description: Send message to SMU and get result 418 | Arguments: 419 | r0: 420 | r1: 421 | r2: 422 | Returns: 423 | r0: Status code. 424 | Used by: 425 | * SEV 426 | 427 | 0x29: 428 | Description: 429 | Arguments: 430 | r0[8]: 431 | r1[8]: 432 | r2[8]: 433 | Returns: 434 | r0: Status code. 435 | Used by: 436 | 437 | 0x2a: 438 | Description: Seems to set the location and size of the secure DRAM region for the SMU firmware 439 | Arguments: 440 | r0: Low 32bit of the x86 physical address to copy from 441 | r1: High 32bit of the x86 physical address to copy from 442 | r2: Some other address, 0xfb800000 443 | r3: Size of the region in bytes maybe, 0xfffd (almost 64KB) 444 | Returns: 445 | r0: Status code. 446 | Used by: 447 | * AR3B 448 | 449 | 0x2b: 450 | Description: 451 | Arguments: 452 | r0: 453 | Returns: 454 | r0: Status code. 455 | Used by: 456 | 457 | 0x2c: 458 | Description: Writes a 0 to the global PSP firmware state 459 | Arguments: N/A 460 | Returns: 461 | r0: Status code. 462 | Used by: 463 | 464 | 0x2d: 465 | Description: Seems to do something flash memory related 466 | Arguments: 467 | r0: 468 | r1: 469 | r2: 470 | r3: 471 | Returns: 472 | r0: Status code. 473 | Used by: 474 | 475 | 0x2e: 476 | Description: 477 | Arguments: 478 | r0: 479 | r1: 480 | r2: 481 | r3: 482 | Returns: 483 | r0: Status code. 484 | Used by: 485 | 486 | 0x2f: 487 | Description: 488 | Arguments: 489 | r0: 490 | r1: 491 | Returns: 492 | r0: Status code. 493 | Used by: 494 | 495 | 0x30: 496 | Description: 497 | Arguments: 498 | r0: 499 | r1: 500 | Returns: 501 | r0: Status code. 502 | Used by: 503 | 504 | 0x31: 505 | Description: Calls a PSP on a different CCX (can be called only on master) 506 | Arguments: 507 | r0: CCX ID of the PSP to call, 0 to do the request on all available PSPs 508 | r1: Pointer to the request structure, first 32bit contain the request to execute 509 | r2: Size of the request structure in bytes 510 | Returns: 511 | r0: Status code. 512 | Used by: 513 | * SEV 514 | 515 | 0x32: 516 | Description: Updates the non-volatile data from user space. 517 | Arguments: 518 | r0: The user space buffer where the encrypted and hmac'd data is stored. 519 | r1: The length of the data (including the hmac). 520 | Returns: 521 | r0: Status code. 522 | Used by: 523 | * SEV 524 | Remarks: 525 | The length of the data seems always to be 0x24b2. 526 | 527 | 0x33: 528 | Description: Loads the non-volatile data to user space. 529 | Arguments: 530 | r0: The user space buffer where to store the (encrypted and hmac'd) data. 531 | r1: The length of the data (including the hmac). 532 | Returns: 533 | r0: Status code. 534 | Used by: 535 | * SEV 536 | Remarks: 537 | The length of the data seems always to be 0x24b2. 538 | 539 | 0x34: 540 | Description: Executes a platform reset. 541 | Arguments: 542 | r0: 543 | Returns: 544 | r0: Status code. 545 | Used by: 546 | * SEV 547 | 548 | 0x35: 549 | Description: Copies crypto material into user space 550 | Arguments: 551 | r0: Pointer to request structure in user space. 552 | Request Structure: 553 | struct SEV_SVC_0x33_PARAMS { 554 | // The output buffer has a size of 16 bytes 555 | // (The encryption key is 32 bytes long but has a 16 byte prefix of zeros) 556 | uint8_t * output; 557 | uint32_t output_length; 558 | 559 | uint8_t * unknown; // Is always NULL 560 | uint32_t unknown_length; // Is always 0 561 | 562 | // The parameter name is either 563 | // "sev-persistent-encryption" for the encryption key 564 | // or 565 | // "sev-persistent-integrity" for the hmac key 566 | char * param_name; 567 | uint32_t param_name_length; 568 | 569 | uint32_t unknown_a[2]; // First element uninitialized, second element is set to 0 570 | uint32_t unknwon_w; // Is always 4 571 | }; 572 | 573 | Returns: 574 | r0: Status code. 575 | Used by: 576 | * SEV 577 | 578 | 0x36: 579 | Description: Accesses the CCP 580 | Arguments: 581 | r0: Some request structure encapsulating the arguments @todo Examine the structure 582 | Returns: 583 | r0: Status code. 584 | Used by: 585 | * SEV 586 | 587 | 0x37: 588 | Description: Invalidate/clean memory ranges. 589 | Arguments: 590 | r0: Operation to perform (see INV_MEM_OP in Ghidra) 591 | r1: Flag whether to operate on data or instruction memory. 592 | r2: PSP virtual address of the start of the memory region to operate on 593 | r3: Size of the memory region to operate on. 594 | Returns: 595 | r0: Status code. 596 | Used by: 597 | * SEV 598 | 599 | 0x38: 600 | Description: Performs hashing operations. 601 | Arguments: 602 | r0: Userspace virtual address to the command buffer (see PSPSVC0X38REQ in Ghidra) 603 | Request Structure: 604 | struct PSPSVC0X38REQ { 605 | uint8_t * data_input; 606 | uint32_t data_input_length; 607 | 608 | uint32_t unknown_two; // Is always 2 609 | 610 | uint8_t * hash_output; 611 | uint32_t hash_size; // Is always 0x20 612 | uint8_t * initial_hash; 613 | 614 | uint32_t unknown; 615 | 616 | uint32_t unknown_one; // Is always 1 617 | 618 | bool last_hash_round; 619 | }; 620 | 621 | Returns: 622 | r0: Status code. 623 | Used by: 624 | * SEV 625 | 626 | 0x39: 627 | Description: Fills a given buffer with random numbers using the CCP TRNG. 628 | Arguments: 629 | r0: Userspace virtual address to the start of the buffer to fill. 630 | r1: Number of bytes to fill. 631 | Returns: 632 | r0: Status code. 633 | Used by: 634 | * SEV 635 | 636 | 0x3a: 637 | Description: Sets the minimum ASID required for non SEV-ES guests. 638 | Arguments: 639 | r0: The ASID to set. 640 | Returns: 641 | r0: Status code. 642 | Used by: 643 | 644 | 0x3b: 645 | Description: Returns the minium ASID required for non SEV-ES guests. 646 | Arguments: N/A 647 | Returns: 648 | r0: The minimum ASID. 649 | Used by: 650 | * SEV 651 | 652 | 0x3c: 653 | Description: Returns a Userspace virtual address from the global PSP firmware state. 654 | Arguments: 655 | r0: Size of the region to map. 656 | Returns: 657 | r0: Userspace virtual address. 658 | Used by: 659 | * SEV 660 | 661 | 0x3d: 662 | Description: Reads from some global memory. 663 | Arguments: N/A 664 | Returns: 665 | r0: Data read. 666 | Used by: 667 | 668 | 0x3e: 669 | Description: Copies a fixed 32 byte region from the PSP supervisor memory to a userspace provided memory buffer 670 | Arguments: 671 | r0: Userspace virtual address of the buffer 672 | r1: Size of the buffer 673 | Returns: 674 | r0: Status code. 675 | Used by: 676 | * SEV 677 | 678 | 0x3f: 679 | Description: Not provided by the PSP firmware 680 | Arguments: 681 | Returns: 682 | Used by: 683 | * SEV 684 | 685 | 0x40: 686 | Description: 687 | Arguments: 688 | r0: 689 | Returns: 690 | r0: Status code. 691 | Used by: 692 | * DebugUnlock 693 | 694 | 0x41: 695 | Description: 696 | Arguments: 697 | r0: 698 | Returns: 699 | r0: Status code. 700 | Used by: 701 | * SEV 702 | 703 | 0x42: 704 | Description: Performs a CCP operation 705 | Arguments: 706 | r0: 707 | r1: Userspace virtual address to return the number of bytes processed maybe. 708 | Returns: 709 | r0: Status code. 710 | Used by: 711 | * SEV 712 | 713 | 0x43: 714 | Description: 715 | Arguments: 716 | r0: 717 | Returns: 718 | r0: Status code. 719 | Used by: 720 | * AR3B 721 | 722 | 0x44: 723 | Description: 724 | Arguments: 725 | r0: 726 | Returns: 727 | r0: Status code. 728 | Used by: 729 | 730 | 0x47: 731 | Description: 732 | Arguments: 733 | r0: 734 | r1: 735 | r2: 736 | r3: 737 | Returns: 738 | r0: Status code. 739 | Used by: 740 | 741 | 0x48: 742 | Description: Queries the start and size of the configured SMM region (TSeg) on the host. 743 | Arguments: 744 | r0: Pointer where to store the 64bit physical address of the start of the region. 745 | r1: Pointer where to store the 64bit region size in bytes. 746 | Returns: 747 | r0: Status code. 748 | Used by: 749 | * SEV 750 | Remarks: 751 | Used by the SEV app to prevent a compromised operating system from reading/writing from/to the 752 | SMM region. 753 | See https://www.amd.com/system/files/TechDocs/24593.pdf#G16.974288 for documentation on Tseg. 754 | 755 | 0x49: 756 | Description: Copies a 64bit word given the argument registers to PSP global memory. 757 | Arguments: 758 | r0: Low 32bit of the 64bit data. 759 | r1: High 32bit of the 64bit data. 760 | Returns: 761 | r0: Status code. 762 | Used by: 763 | Remarks: 764 | The global memory referenced is read in a function called during cold boot and warm resume. 765 | 766 | 0x4a: 767 | Description: 768 | Arguments: 769 | r0: 770 | Returns: 771 | r0: Status code. 772 | Used by: 773 | * DramTraining 774 | 775 | 0x4b: 776 | Description: Some NOP. 777 | Arguments: N/A 778 | Returns: N/A 779 | Used by: 780 | 781 | 0x4c: 782 | Description: 783 | Arguments: 784 | r0: 785 | r1: 786 | Returns: 787 | r0: Status code. 788 | Used by: 789 | 790 | 0x4d: 791 | Description: Downloads a new firmware from the provided x86 host memory, not provided by the PSP firmware 792 | Arguments: 793 | Returns: 794 | Used by: 795 | * SEV 796 | --------------------------------------------------------------------------------