├── .gitignore ├── .library_mapping.xml ├── .project ├── .settings ├── com.sigasi.hdt.vhdl.Vhdl.prefs ├── com.sigasi.hdt.vhdl.version.prefs └── org.eclipse.core.resources.prefs ├── APA └── SystemVerilog │ ├── nonproject │ ├── build │ │ ├── build.tcl │ │ ├── config_parameters.tcl │ │ └── overrides.inc │ └── scripts │ │ ├── design_post_place.xdc │ │ └── vivado_procedures.tcl │ └── project │ └── final_project │ └── final_project.xpr ├── CH10 ├── IP │ ├── ddr2_vga │ │ ├── ddr2_vga.xci │ │ └── mig_a.prj │ ├── pix_clk │ │ └── pix_clk.xci │ └── sys_pll │ │ └── sys_pll.xci ├── SystemVerilog │ ├── build │ │ └── vga.xpr │ ├── hdl │ │ ├── text_rom.sv │ │ ├── vga.sv │ │ └── vga_core.sv │ └── tb │ │ └── tb_vga.sv ├── VHDL │ ├── build │ │ └── vga.xpr │ ├── hdl │ │ ├── components_pkg.vhd │ │ ├── text_rom.vhd │ │ ├── vga.vhd │ │ ├── vga_core.vhd │ │ └── vga_pkg.vhd │ └── tb │ │ ├── bmp_pkg.vhdl │ │ └── tb_vga.vhdl └── xdc │ ├── ddr2.xdc │ ├── vga.xdc │ └── vga_gold.xdc ├── CH11 ├── SystemVerilog │ ├── build │ │ ├── debounce.xpr │ │ ├── final_project.xpr │ │ └── ps2.xpr │ ├── hdl │ │ ├── debounce.sv │ │ ├── final_project.sv │ │ ├── final_project_pkg.sv │ │ ├── i2c_temp_flt.sv │ │ ├── i2c_wrapper.sv │ │ ├── pdm_inputs.sv │ │ ├── ps2_host.sv │ │ ├── text_rom.sv │ │ └── vga_core.sv │ └── tb │ │ ├── ddr2_model_parameters.vh │ │ ├── tb_debounce.sv │ │ ├── tb_final_project.sv │ │ └── tb_ps2.sv ├── VHDL │ ├── build │ │ ├── debounce.xpr │ │ ├── final_project.xpr │ │ └── ps2.xpr │ ├── hdl │ │ ├── debounce.vhd │ │ ├── final_project.vhd │ │ ├── i2c_temp_flt.vhd │ │ ├── i2c_temp_flt_components_pkg.vhd │ │ ├── i2c_wrapper.vhd │ │ ├── i2c_wrapper_pkg.vhd │ │ ├── pdm_inputs.vhd │ │ ├── pdm_top.vhd │ │ ├── ps2_host.vhd │ │ ├── ps2_pkg.vhd │ │ ├── temp_pkg.vhd │ │ ├── text_rom.vhd │ │ ├── vga_core.vhd │ │ └── vga_pkg.vhd │ └── tb │ │ ├── tb_debounce.vhd │ │ ├── tb_ps2.sv │ │ └── tb_ps2.vhd └── xdc │ └── vga.xdc ├── CH12 ├── IP │ └── sys_pll │ │ └── sys_pll.xci ├── SystemVerilog │ ├── build │ │ ├── acl_top.xpr │ │ └── uart_top.xpr │ ├── hdl │ │ ├── acl_top.sv │ │ ├── async_fifo.sv │ │ ├── cathode_top.sv │ │ ├── seven_segment.sv │ │ ├── spi.sv │ │ ├── sync_fifo.sv │ │ ├── uart.sv │ │ ├── uart_cpu.sv │ │ └── uart_top.sv │ └── sim │ │ ├── runsim │ │ ├── tests │ │ ├── cts_test.h │ │ ├── ext_loopback.h │ │ ├── int_loopback.h │ │ ├── overrun.h │ │ ├── reg_test.h │ │ ├── speed_mismatch.h │ │ ├── speedtest.h │ │ ├── uart_uart_int.h │ │ ├── uart_uart_int2.h │ │ ├── uart_uart_int_frame.h │ │ ├── uart_uart_int_par.h │ │ └── uart_uart_poll.h │ │ └── uart_build ├── VHDL │ ├── build │ │ ├── acl_top.xpr │ │ └── uart_top.xpr │ ├── hdl │ │ ├── acl_top.vhd │ │ ├── cathode_top.vhd │ │ ├── counting_buttons_pkg.vhd │ │ ├── seven_segment.vhd │ │ ├── spi.vhd │ │ ├── temp_pkg.vhd │ │ ├── uart.vhd │ │ ├── uart_cpu.vhd │ │ └── uart_top.vhd │ └── sim │ │ ├── runsim │ │ ├── tests │ │ ├── cts_test.h │ │ ├── ext_loopback.h │ │ ├── int_loopback.h │ │ ├── overrun.h │ │ ├── reg_test.h │ │ ├── speed_mismatch.h │ │ ├── speedtest.h │ │ ├── uart_uart_int.h │ │ ├── uart_uart_int2.h │ │ ├── uart_uart_int_frame.h │ │ ├── uart_uart_int_par.h │ │ └── uart_uart_poll.h │ │ └── uart_build ├── tb │ └── tb_uart.sv └── xdc │ ├── spi_a7100t.xdc │ └── uart_a7100t.xdc ├── CH13 ├── C │ └── helloworld.c ├── SystemVerilog │ └── build │ │ └── hello_world.xpr ├── VHDL │ ├── build │ │ └── hello_world.xpr │ └── hello_world.xpr └── xdc │ ├── ddr2.xdc │ └── uart_a7100t.xdc ├── CH14 ├── SystemVerilog │ ├── build │ │ ├── inferred_wire.xpr │ │ ├── labels.xpr │ │ ├── latch_error.xpr │ │ ├── pipeline.xpr │ │ ├── pre_synth.tcl │ │ ├── ps2_host.xpr │ │ └── streaming.xpr │ ├── hdl │ │ ├── inferred_wire.sv │ │ ├── labels.sv │ │ ├── latch_error.sv │ │ ├── pipeline.sv │ │ ├── ps2_host.sv │ │ ├── ps2_intf.sv │ │ └── streaming.sv │ └── tb │ │ └── tb_ps2.sv └── xdc │ ├── latch.xdc │ ├── pipeline.xdc │ └── vga.xdc ├── CH2 ├── SystemVerilog │ ├── build │ │ ├── challenge.xpr │ │ └── logic_ex.xpr │ ├── hdl │ │ ├── challenge.sv │ │ └── logic_ex.sv │ └── tb │ │ ├── tb.sv │ │ └── tb_challenge.sv ├── VHDL │ ├── build │ │ ├── challenge.xpr │ │ ├── challenge │ │ │ └── challenge.xpr │ │ ├── logic_ex.xpr │ │ └── logic_ex │ │ │ └── logic_ex.xpr │ ├── hdl │ │ ├── challenge.vhd │ │ └── logic_ex.vhd │ └── tb │ │ ├── tb.vhd │ │ └── tb_challenge.vhd └── xdc │ └── Nexys-A7-100T-Master.xdc ├── CH3 ├── SystemVerilog │ ├── build │ │ └── project_2.xpr │ ├── hdl │ │ ├── add_sub.sv │ │ ├── leading_ones.sv │ │ ├── mult.sv │ │ ├── num_ones.sv │ │ └── project_2.sv │ └── tb │ │ └── tb.sv ├── VHDL │ ├── build │ │ └── project_2.xpr │ ├── hdl │ │ ├── add_sub.vhd │ │ ├── leading_ones.vhd │ │ ├── mult.vhd │ │ ├── num_ones.vhd │ │ └── project_2.vhd │ └── tb │ │ └── tb.vhd └── xdc │ └── Nexys-A7-100T-Master.xdc ├── CH4 ├── SystemVerilog │ ├── blocking │ │ ├── build │ │ │ └── blocking.xpr │ │ ├── hdl │ │ │ └── blocking.sv │ │ └── tb │ │ │ └── tb_blocking.sv │ ├── counting_buttons │ │ ├── build │ │ │ └── counting_buttons.xpr │ │ └── hdl │ │ │ ├── cathode_top.sv │ │ │ ├── counting_buttons.sv │ │ │ └── seven_segment.sv │ ├── simple_ff │ │ ├── build │ │ │ └── simple_ff.xpr │ │ ├── hdl │ │ │ └── simple_ff.sv │ │ └── tb │ │ │ └── tb_simple_ff.sv │ ├── simple_ff_async │ │ ├── build │ │ │ └── simple_ff.xpr │ │ ├── hdl │ │ │ └── simple_ff_async_.sv │ │ └── tb │ │ │ └── tb_simple_ff_async.sv │ └── simple_init_ff │ │ ├── build │ │ └── simple_init_ff.xpr │ │ ├── hdl │ │ └── simple_init_ff.sv │ │ └── tb │ │ └── tb_simple_init_ff.sv ├── VHDL │ ├── blocking │ │ ├── build │ │ │ └── blocking.xpr │ │ ├── hdl │ │ │ └── blocking.vhd │ │ └── tb │ │ │ └── tb_blocking.vhd │ ├── counting_buttons │ │ ├── build │ │ │ └── counting_buttons.xpr │ │ └── hdl │ │ │ ├── cathode_top.vhd │ │ │ ├── counting_buttons.vhd │ │ │ ├── counting_buttons_pkg.vhd │ │ │ └── seven_segment.vhd │ ├── simple_ff │ │ ├── build │ │ │ └── simple_ff.xpr │ │ ├── hdl │ │ │ └── simple_ff.vhd │ │ └── tb │ │ │ └── tb_simple_ff.vhd │ └── simple_ff_async │ │ ├── build │ │ └── simple_ff_async.xpr │ │ ├── hdl │ │ └── simple_ff_async.vhd │ │ └── tb │ │ └── tb_simple_ff_async.vhd └── xdc │ ├── Nexys-A7-100T-Master.xdc │ └── simple_fifo_arty_a7100t.xdc ├── CH5 ├── IP │ └── sys_pll │ │ └── sys_pll.xci ├── SystemVerilog │ ├── build │ │ ├── calculator.xpr │ │ ├── divider_nr.xpr │ │ └── traffic_light.xpr │ ├── hdl │ │ ├── calculator_mealy.sv │ │ ├── calculator_moore.sv │ │ ├── calculator_pkg.sv │ │ ├── calculator_top.sv │ │ ├── divider_nr.sv │ │ └── traffic_light.sv │ └── tb │ │ └── tb_divider_nr.sv ├── VHDL │ ├── build │ │ ├── calculator.xpr │ │ ├── divider_nr.xpr │ │ └── traffic_light.xpr │ ├── hdl │ │ ├── calculator_mealy.vhd │ │ ├── calculator_moore.vhd │ │ ├── calculator_pkg.vhd │ │ ├── calculator_top.vhd │ │ ├── divider_nr.vhd │ │ └── traffic_light.vhd │ └── tb │ │ └── tb_divider_nr.vhd └── xdc │ ├── calculator_a7100t.xdc │ └── traffic_light_a7100t.xdc ├── CH6 ├── SystemVerilog │ ├── build │ │ ├── i2c_temp.xpr │ │ └── pdm_audio.xpr │ ├── hdl │ │ ├── i2c_temp.sv │ │ ├── pdm_inputs.sv │ │ ├── pdm_output.sv │ │ ├── pdm_top.sv │ │ ├── pwm_outputs.sv │ │ └── temp_pkg.sv │ └── tb │ │ ├── adt7420_mdl.sv │ │ ├── tb_pdm_top.sv │ │ └── tb_temp.sv ├── VHDL │ ├── build │ │ ├── i2c_temp.xpr │ │ └── pdm_audio.xpr │ ├── hdl │ │ ├── i2c_temp.vhd │ │ ├── pdm_inputs.vhd │ │ ├── pdm_output.vhd │ │ ├── pdm_top.vhd │ │ ├── pwm_outputs.vhd │ │ ├── temp_pkg.vhd │ │ └── util_pkg.vhd │ └── tb │ │ ├── adt7420_mdl.vhd │ │ ├── tb_pdm_top.vhd │ │ └── tb_temp.vhd └── xdc │ ├── i2c_temp.xdc │ └── pdm_audio.xdc ├── CH7 ├── IP │ ├── fix_to_float │ │ └── fix_to_float.xci │ ├── flt_to_fix │ │ └── flt_to_fix.xci │ ├── fp_addsub │ │ └── fp_addsub.xci │ ├── fp_fused_mult_add │ │ └── fp_fused_mult_add.xci │ └── fp_mult │ │ └── fp_mult.xci ├── SystemVerilog │ ├── build │ │ ├── i2c_temp.xpr │ │ ├── i2c_temp_flt.xpr │ │ └── parallel.xpr │ ├── hdl │ │ ├── i2c_temp.sv │ │ ├── i2c_temp_flt.sv │ │ ├── parallel.sv │ │ └── temp_pkg.sv │ └── tb │ │ ├── adt7420_mdl.sv │ │ ├── tb_parallel.sv │ │ ├── tb_temp.sv │ │ └── tb_temp_flt.sv ├── VHDL │ ├── build │ │ ├── i2c_temp.xpr │ │ ├── i2c_temp_flt.xpr │ │ ├── parallel.xpr │ │ └── parallel │ │ │ └── parallel.xpr │ ├── hdl │ │ ├── i2c_temp.vhd │ │ ├── i2c_temp_flt.vhd │ │ ├── i2c_temp_flt_components_pkg.vhd │ │ ├── parallel.vhd │ │ ├── temp_pkg.vhd │ │ └── util_pkg.vhd │ └── tb │ │ ├── adt7420_mdl.vhd │ │ ├── tb_parallel.vhd │ │ └── tb_temp.vhd └── xdc │ └── i2c_temp.xdc ├── CH8 ├── SystemVerilog │ ├── build │ │ ├── completed │ │ │ └── i2c_temp_flt_bd │ │ │ │ └── i2c_temp_flt_bd.xpr │ │ ├── i2c_temp_flt_bd.tcl │ │ ├── i2c_temp_flt_unpkg.xpr │ │ └── scaffold │ │ │ └── i2c_temp_flt_bd.tcl │ ├── hdl │ │ ├── adt7420_i2c_bd.v │ │ └── adt7420_i2c_mod.sv │ └── ip_source │ │ ├── adt7420_i2c │ │ └── hdl │ │ │ ├── adt7420_i2c.sv │ │ │ └── temp_pkg.sv │ │ ├── flt_temp │ │ └── hdl │ │ │ ├── flt_temp.sv │ │ │ └── temp_pkg.sv │ │ └── seven_segment │ │ └── hdl │ │ ├── cathode_top.sv │ │ └── seven_segment.sv ├── VHDL │ ├── build │ │ ├── completed │ │ │ ├── i2c_temp_flt_bd.gen │ │ │ │ └── sources_1 │ │ │ │ │ └── bd │ │ │ │ │ └── design_1 │ │ │ │ │ └── hdl │ │ │ │ │ └── design_1_wrapper.vhd │ │ │ ├── i2c_temp_flt_bd.srcs │ │ │ │ └── sources_1 │ │ │ │ │ └── bd │ │ │ │ │ └── design_1 │ │ │ │ │ └── design_1.bd │ │ │ └── i2c_temp_flt_bd.xpr │ │ └── scaffold │ │ │ └── i2c_temp_flt_bd.xpr │ ├── ip_source │ │ ├── adt7420_i2c │ │ │ ├── component.xml │ │ │ ├── hdl │ │ │ │ └── adt7420_i2c.vhd │ │ │ └── xgui │ │ │ │ └── adt7420_i2c_v1_0.tcl │ │ ├── flt_temp │ │ │ ├── component.xml │ │ │ ├── hdl │ │ │ │ ├── flt_temp.vhd │ │ │ │ ├── temp_pkg.vhd │ │ │ │ └── util_pkg.vhd │ │ │ └── xgui │ │ │ │ └── flt_temp_v1_0.tcl │ │ └── seven_segment │ │ │ ├── component.xml │ │ │ ├── hdl │ │ │ ├── cathode_top.vhd │ │ │ └── seven_segment.vhd │ │ │ └── xgui │ │ │ └── seven_segment_v1_0.tcl │ └── tb │ │ ├── adt7420_mdl.vhd │ │ └── tb_design_1_wrapper.vhd └── xdc │ ├── i2c_temp.xdc │ └── i2c_temp_flt_bd.tcl ├── CH9 ├── SystemVerilog │ ├── build │ │ └── ddr2.xpr │ ├── hdl │ │ └── example_top.v │ └── tb │ │ └── sim_tb_top.v ├── VHDL │ └── build │ │ └── ddr2.xpr └── xdc │ ├── Nexys4DDRmemorypinout.ucf │ └── ddr2.xdc ├── LICENSE ├── README.md └── regression.py /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/.gitignore -------------------------------------------------------------------------------- /.library_mapping.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/.library_mapping.xml -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/.project -------------------------------------------------------------------------------- /.settings/com.sigasi.hdt.vhdl.Vhdl.prefs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/.settings/com.sigasi.hdt.vhdl.Vhdl.prefs -------------------------------------------------------------------------------- /.settings/com.sigasi.hdt.vhdl.version.prefs: -------------------------------------------------------------------------------- 1 | =2008 2 | -------------------------------------------------------------------------------- /.settings/org.eclipse.core.resources.prefs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/.settings/org.eclipse.core.resources.prefs -------------------------------------------------------------------------------- /APA/SystemVerilog/nonproject/build/build.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/APA/SystemVerilog/nonproject/build/build.tcl -------------------------------------------------------------------------------- /APA/SystemVerilog/nonproject/build/config_parameters.tcl: -------------------------------------------------------------------------------- 1 | set top_module final_project 2 | set fpga_part xc7a100tcsg324-1 3 | -------------------------------------------------------------------------------- /APA/SystemVerilog/nonproject/build/overrides.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/APA/SystemVerilog/nonproject/build/overrides.inc -------------------------------------------------------------------------------- /APA/SystemVerilog/nonproject/scripts/design_post_place.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/APA/SystemVerilog/nonproject/scripts/design_post_place.xdc -------------------------------------------------------------------------------- /APA/SystemVerilog/nonproject/scripts/vivado_procedures.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/APA/SystemVerilog/nonproject/scripts/vivado_procedures.tcl -------------------------------------------------------------------------------- /APA/SystemVerilog/project/final_project/final_project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/APA/SystemVerilog/project/final_project/final_project.xpr -------------------------------------------------------------------------------- /CH10/IP/ddr2_vga/ddr2_vga.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/IP/ddr2_vga/ddr2_vga.xci -------------------------------------------------------------------------------- /CH10/IP/ddr2_vga/mig_a.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/IP/ddr2_vga/mig_a.prj -------------------------------------------------------------------------------- /CH10/IP/pix_clk/pix_clk.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/IP/pix_clk/pix_clk.xci -------------------------------------------------------------------------------- /CH10/IP/sys_pll/sys_pll.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/IP/sys_pll/sys_pll.xci -------------------------------------------------------------------------------- /CH10/SystemVerilog/build/vga.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/SystemVerilog/build/vga.xpr -------------------------------------------------------------------------------- /CH10/SystemVerilog/hdl/text_rom.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/SystemVerilog/hdl/text_rom.sv -------------------------------------------------------------------------------- /CH10/SystemVerilog/hdl/vga.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/SystemVerilog/hdl/vga.sv -------------------------------------------------------------------------------- /CH10/SystemVerilog/hdl/vga_core.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/SystemVerilog/hdl/vga_core.sv -------------------------------------------------------------------------------- /CH10/SystemVerilog/tb/tb_vga.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/SystemVerilog/tb/tb_vga.sv -------------------------------------------------------------------------------- /CH10/VHDL/build/vga.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/VHDL/build/vga.xpr -------------------------------------------------------------------------------- /CH10/VHDL/hdl/components_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/VHDL/hdl/components_pkg.vhd -------------------------------------------------------------------------------- /CH10/VHDL/hdl/text_rom.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/VHDL/hdl/text_rom.vhd -------------------------------------------------------------------------------- /CH10/VHDL/hdl/vga.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/VHDL/hdl/vga.vhd -------------------------------------------------------------------------------- /CH10/VHDL/hdl/vga_core.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/VHDL/hdl/vga_core.vhd -------------------------------------------------------------------------------- /CH10/VHDL/hdl/vga_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/VHDL/hdl/vga_pkg.vhd -------------------------------------------------------------------------------- /CH10/VHDL/tb/bmp_pkg.vhdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/VHDL/tb/bmp_pkg.vhdl -------------------------------------------------------------------------------- /CH10/VHDL/tb/tb_vga.vhdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/VHDL/tb/tb_vga.vhdl -------------------------------------------------------------------------------- /CH10/xdc/ddr2.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/xdc/ddr2.xdc -------------------------------------------------------------------------------- /CH10/xdc/vga.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/xdc/vga.xdc -------------------------------------------------------------------------------- /CH10/xdc/vga_gold.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH10/xdc/vga_gold.xdc -------------------------------------------------------------------------------- /CH11/SystemVerilog/build/debounce.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/build/debounce.xpr -------------------------------------------------------------------------------- /CH11/SystemVerilog/build/final_project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/build/final_project.xpr -------------------------------------------------------------------------------- /CH11/SystemVerilog/build/ps2.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/build/ps2.xpr -------------------------------------------------------------------------------- /CH11/SystemVerilog/hdl/debounce.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/hdl/debounce.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/hdl/final_project.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/hdl/final_project.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/hdl/final_project_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/hdl/final_project_pkg.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/hdl/i2c_temp_flt.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/hdl/i2c_temp_flt.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/hdl/i2c_wrapper.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/hdl/i2c_wrapper.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/hdl/pdm_inputs.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/hdl/pdm_inputs.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/hdl/ps2_host.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/hdl/ps2_host.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/hdl/text_rom.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/hdl/text_rom.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/hdl/vga_core.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/hdl/vga_core.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/tb/ddr2_model_parameters.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/tb/ddr2_model_parameters.vh -------------------------------------------------------------------------------- /CH11/SystemVerilog/tb/tb_debounce.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/tb/tb_debounce.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/tb/tb_final_project.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/tb/tb_final_project.sv -------------------------------------------------------------------------------- /CH11/SystemVerilog/tb/tb_ps2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/SystemVerilog/tb/tb_ps2.sv -------------------------------------------------------------------------------- /CH11/VHDL/build/debounce.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/build/debounce.xpr -------------------------------------------------------------------------------- /CH11/VHDL/build/final_project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/build/final_project.xpr -------------------------------------------------------------------------------- /CH11/VHDL/build/ps2.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/build/ps2.xpr -------------------------------------------------------------------------------- /CH11/VHDL/hdl/debounce.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/debounce.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/final_project.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/final_project.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/i2c_temp_flt.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/i2c_temp_flt.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/i2c_temp_flt_components_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/i2c_temp_flt_components_pkg.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/i2c_wrapper.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/i2c_wrapper.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/i2c_wrapper_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/i2c_wrapper_pkg.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/pdm_inputs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/pdm_inputs.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/pdm_top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/pdm_top.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/ps2_host.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/ps2_host.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/ps2_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/ps2_pkg.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/temp_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/temp_pkg.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/text_rom.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/text_rom.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/vga_core.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/vga_core.vhd -------------------------------------------------------------------------------- /CH11/VHDL/hdl/vga_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/hdl/vga_pkg.vhd -------------------------------------------------------------------------------- /CH11/VHDL/tb/tb_debounce.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/tb/tb_debounce.vhd -------------------------------------------------------------------------------- /CH11/VHDL/tb/tb_ps2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/tb/tb_ps2.sv -------------------------------------------------------------------------------- /CH11/VHDL/tb/tb_ps2.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/VHDL/tb/tb_ps2.vhd -------------------------------------------------------------------------------- /CH11/xdc/vga.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH11/xdc/vga.xdc -------------------------------------------------------------------------------- /CH12/IP/sys_pll/sys_pll.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/IP/sys_pll/sys_pll.xci -------------------------------------------------------------------------------- /CH12/SystemVerilog/build/acl_top.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/build/acl_top.xpr -------------------------------------------------------------------------------- /CH12/SystemVerilog/build/uart_top.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/build/uart_top.xpr -------------------------------------------------------------------------------- /CH12/SystemVerilog/hdl/acl_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/hdl/acl_top.sv -------------------------------------------------------------------------------- /CH12/SystemVerilog/hdl/async_fifo.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/hdl/async_fifo.sv -------------------------------------------------------------------------------- /CH12/SystemVerilog/hdl/cathode_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/hdl/cathode_top.sv -------------------------------------------------------------------------------- /CH12/SystemVerilog/hdl/seven_segment.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/hdl/seven_segment.sv -------------------------------------------------------------------------------- /CH12/SystemVerilog/hdl/spi.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/hdl/spi.sv -------------------------------------------------------------------------------- /CH12/SystemVerilog/hdl/sync_fifo.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/hdl/sync_fifo.sv -------------------------------------------------------------------------------- /CH12/SystemVerilog/hdl/uart.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/hdl/uart.sv -------------------------------------------------------------------------------- /CH12/SystemVerilog/hdl/uart_cpu.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/hdl/uart_cpu.sv -------------------------------------------------------------------------------- /CH12/SystemVerilog/hdl/uart_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/hdl/uart_top.sv -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/runsim: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/runsim -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/cts_test.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/cts_test.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/ext_loopback.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/ext_loopback.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/int_loopback.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/int_loopback.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/overrun.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/overrun.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/reg_test.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/reg_test.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/speed_mismatch.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/speed_mismatch.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/speedtest.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/speedtest.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/uart_uart_int.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/uart_uart_int.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/uart_uart_int2.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/uart_uart_int2.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/uart_uart_int_frame.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/uart_uart_int_frame.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/uart_uart_int_par.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/uart_uart_int_par.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/tests/uart_uart_poll.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/tests/uart_uart_poll.h -------------------------------------------------------------------------------- /CH12/SystemVerilog/sim/uart_build: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/SystemVerilog/sim/uart_build -------------------------------------------------------------------------------- /CH12/VHDL/build/acl_top.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/build/acl_top.xpr -------------------------------------------------------------------------------- /CH12/VHDL/build/uart_top.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/build/uart_top.xpr -------------------------------------------------------------------------------- /CH12/VHDL/hdl/acl_top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/hdl/acl_top.vhd -------------------------------------------------------------------------------- /CH12/VHDL/hdl/cathode_top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/hdl/cathode_top.vhd -------------------------------------------------------------------------------- /CH12/VHDL/hdl/counting_buttons_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/hdl/counting_buttons_pkg.vhd -------------------------------------------------------------------------------- /CH12/VHDL/hdl/seven_segment.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/hdl/seven_segment.vhd -------------------------------------------------------------------------------- /CH12/VHDL/hdl/spi.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/hdl/spi.vhd -------------------------------------------------------------------------------- /CH12/VHDL/hdl/temp_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/hdl/temp_pkg.vhd -------------------------------------------------------------------------------- /CH12/VHDL/hdl/uart.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/hdl/uart.vhd -------------------------------------------------------------------------------- /CH12/VHDL/hdl/uart_cpu.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/hdl/uart_cpu.vhd -------------------------------------------------------------------------------- /CH12/VHDL/hdl/uart_top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/hdl/uart_top.vhd -------------------------------------------------------------------------------- /CH12/VHDL/sim/runsim: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/runsim -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/cts_test.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/cts_test.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/ext_loopback.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/ext_loopback.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/int_loopback.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/int_loopback.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/overrun.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/overrun.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/reg_test.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/reg_test.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/speed_mismatch.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/speed_mismatch.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/speedtest.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/speedtest.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/uart_uart_int.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/uart_uart_int.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/uart_uart_int2.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/uart_uart_int2.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/uart_uart_int_frame.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/uart_uart_int_frame.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/uart_uart_int_par.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/uart_uart_int_par.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/tests/uart_uart_poll.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/tests/uart_uart_poll.h -------------------------------------------------------------------------------- /CH12/VHDL/sim/uart_build: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/VHDL/sim/uart_build -------------------------------------------------------------------------------- /CH12/tb/tb_uart.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/tb/tb_uart.sv -------------------------------------------------------------------------------- /CH12/xdc/spi_a7100t.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/xdc/spi_a7100t.xdc -------------------------------------------------------------------------------- /CH12/xdc/uart_a7100t.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH12/xdc/uart_a7100t.xdc -------------------------------------------------------------------------------- /CH13/C/helloworld.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH13/C/helloworld.c -------------------------------------------------------------------------------- /CH13/SystemVerilog/build/hello_world.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH13/SystemVerilog/build/hello_world.xpr -------------------------------------------------------------------------------- /CH13/VHDL/build/hello_world.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH13/VHDL/build/hello_world.xpr -------------------------------------------------------------------------------- /CH13/VHDL/hello_world.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH13/VHDL/hello_world.xpr -------------------------------------------------------------------------------- /CH13/xdc/ddr2.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH13/xdc/ddr2.xdc -------------------------------------------------------------------------------- /CH13/xdc/uart_a7100t.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH13/xdc/uart_a7100t.xdc -------------------------------------------------------------------------------- /CH14/SystemVerilog/build/inferred_wire.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/build/inferred_wire.xpr -------------------------------------------------------------------------------- /CH14/SystemVerilog/build/labels.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/build/labels.xpr -------------------------------------------------------------------------------- /CH14/SystemVerilog/build/latch_error.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/build/latch_error.xpr -------------------------------------------------------------------------------- /CH14/SystemVerilog/build/pipeline.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/build/pipeline.xpr -------------------------------------------------------------------------------- /CH14/SystemVerilog/build/pre_synth.tcl: -------------------------------------------------------------------------------- 1 | set_msg_config -id {[Synth 8-327]} -new_severity ERROR 2 | -------------------------------------------------------------------------------- /CH14/SystemVerilog/build/ps2_host.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/build/ps2_host.xpr -------------------------------------------------------------------------------- /CH14/SystemVerilog/build/streaming.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/build/streaming.xpr -------------------------------------------------------------------------------- /CH14/SystemVerilog/hdl/inferred_wire.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/hdl/inferred_wire.sv -------------------------------------------------------------------------------- /CH14/SystemVerilog/hdl/labels.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/hdl/labels.sv -------------------------------------------------------------------------------- /CH14/SystemVerilog/hdl/latch_error.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/hdl/latch_error.sv -------------------------------------------------------------------------------- /CH14/SystemVerilog/hdl/pipeline.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/hdl/pipeline.sv -------------------------------------------------------------------------------- /CH14/SystemVerilog/hdl/ps2_host.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/hdl/ps2_host.sv -------------------------------------------------------------------------------- /CH14/SystemVerilog/hdl/ps2_intf.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/hdl/ps2_intf.sv -------------------------------------------------------------------------------- /CH14/SystemVerilog/hdl/streaming.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/hdl/streaming.sv -------------------------------------------------------------------------------- /CH14/SystemVerilog/tb/tb_ps2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/SystemVerilog/tb/tb_ps2.sv -------------------------------------------------------------------------------- /CH14/xdc/latch.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/xdc/latch.xdc -------------------------------------------------------------------------------- /CH14/xdc/pipeline.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/xdc/pipeline.xdc -------------------------------------------------------------------------------- /CH14/xdc/vga.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH14/xdc/vga.xdc -------------------------------------------------------------------------------- /CH2/SystemVerilog/build/challenge.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/SystemVerilog/build/challenge.xpr -------------------------------------------------------------------------------- /CH2/SystemVerilog/build/logic_ex.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/SystemVerilog/build/logic_ex.xpr -------------------------------------------------------------------------------- /CH2/SystemVerilog/hdl/challenge.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/SystemVerilog/hdl/challenge.sv -------------------------------------------------------------------------------- /CH2/SystemVerilog/hdl/logic_ex.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/SystemVerilog/hdl/logic_ex.sv -------------------------------------------------------------------------------- /CH2/SystemVerilog/tb/tb.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/SystemVerilog/tb/tb.sv -------------------------------------------------------------------------------- /CH2/SystemVerilog/tb/tb_challenge.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/SystemVerilog/tb/tb_challenge.sv -------------------------------------------------------------------------------- /CH2/VHDL/build/challenge.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/VHDL/build/challenge.xpr -------------------------------------------------------------------------------- /CH2/VHDL/build/challenge/challenge.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/VHDL/build/challenge/challenge.xpr -------------------------------------------------------------------------------- /CH2/VHDL/build/logic_ex.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/VHDL/build/logic_ex.xpr -------------------------------------------------------------------------------- /CH2/VHDL/build/logic_ex/logic_ex.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/VHDL/build/logic_ex/logic_ex.xpr -------------------------------------------------------------------------------- /CH2/VHDL/hdl/challenge.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/VHDL/hdl/challenge.vhd -------------------------------------------------------------------------------- /CH2/VHDL/hdl/logic_ex.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/VHDL/hdl/logic_ex.vhd -------------------------------------------------------------------------------- /CH2/VHDL/tb/tb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/VHDL/tb/tb.vhd -------------------------------------------------------------------------------- /CH2/VHDL/tb/tb_challenge.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/VHDL/tb/tb_challenge.vhd -------------------------------------------------------------------------------- /CH2/xdc/Nexys-A7-100T-Master.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH2/xdc/Nexys-A7-100T-Master.xdc -------------------------------------------------------------------------------- /CH3/SystemVerilog/build/project_2.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/SystemVerilog/build/project_2.xpr -------------------------------------------------------------------------------- /CH3/SystemVerilog/hdl/add_sub.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/SystemVerilog/hdl/add_sub.sv -------------------------------------------------------------------------------- /CH3/SystemVerilog/hdl/leading_ones.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/SystemVerilog/hdl/leading_ones.sv -------------------------------------------------------------------------------- /CH3/SystemVerilog/hdl/mult.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/SystemVerilog/hdl/mult.sv -------------------------------------------------------------------------------- /CH3/SystemVerilog/hdl/num_ones.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/SystemVerilog/hdl/num_ones.sv -------------------------------------------------------------------------------- /CH3/SystemVerilog/hdl/project_2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/SystemVerilog/hdl/project_2.sv -------------------------------------------------------------------------------- /CH3/SystemVerilog/tb/tb.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/SystemVerilog/tb/tb.sv -------------------------------------------------------------------------------- /CH3/VHDL/build/project_2.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/VHDL/build/project_2.xpr -------------------------------------------------------------------------------- /CH3/VHDL/hdl/add_sub.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/VHDL/hdl/add_sub.vhd -------------------------------------------------------------------------------- /CH3/VHDL/hdl/leading_ones.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/VHDL/hdl/leading_ones.vhd -------------------------------------------------------------------------------- /CH3/VHDL/hdl/mult.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/VHDL/hdl/mult.vhd -------------------------------------------------------------------------------- /CH3/VHDL/hdl/num_ones.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/VHDL/hdl/num_ones.vhd -------------------------------------------------------------------------------- /CH3/VHDL/hdl/project_2.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/VHDL/hdl/project_2.vhd -------------------------------------------------------------------------------- /CH3/VHDL/tb/tb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/VHDL/tb/tb.vhd -------------------------------------------------------------------------------- /CH3/xdc/Nexys-A7-100T-Master.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH3/xdc/Nexys-A7-100T-Master.xdc -------------------------------------------------------------------------------- /CH4/SystemVerilog/blocking/build/blocking.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/blocking/build/blocking.xpr -------------------------------------------------------------------------------- /CH4/SystemVerilog/blocking/hdl/blocking.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/blocking/hdl/blocking.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/blocking/tb/tb_blocking.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/blocking/tb/tb_blocking.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/counting_buttons/build/counting_buttons.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/counting_buttons/build/counting_buttons.xpr -------------------------------------------------------------------------------- /CH4/SystemVerilog/counting_buttons/hdl/cathode_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/counting_buttons/hdl/cathode_top.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/counting_buttons/hdl/counting_buttons.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/counting_buttons/hdl/counting_buttons.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/counting_buttons/hdl/seven_segment.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/counting_buttons/hdl/seven_segment.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/simple_ff/build/simple_ff.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/simple_ff/build/simple_ff.xpr -------------------------------------------------------------------------------- /CH4/SystemVerilog/simple_ff/hdl/simple_ff.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/simple_ff/hdl/simple_ff.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/simple_ff/tb/tb_simple_ff.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/simple_ff/tb/tb_simple_ff.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/simple_ff_async/build/simple_ff.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/simple_ff_async/build/simple_ff.xpr -------------------------------------------------------------------------------- /CH4/SystemVerilog/simple_ff_async/hdl/simple_ff_async_.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/simple_ff_async/hdl/simple_ff_async_.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/simple_ff_async/tb/tb_simple_ff_async.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/simple_ff_async/tb/tb_simple_ff_async.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/simple_init_ff/build/simple_init_ff.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/simple_init_ff/build/simple_init_ff.xpr -------------------------------------------------------------------------------- /CH4/SystemVerilog/simple_init_ff/hdl/simple_init_ff.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/simple_init_ff/hdl/simple_init_ff.sv -------------------------------------------------------------------------------- /CH4/SystemVerilog/simple_init_ff/tb/tb_simple_init_ff.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/SystemVerilog/simple_init_ff/tb/tb_simple_init_ff.sv -------------------------------------------------------------------------------- /CH4/VHDL/blocking/build/blocking.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/blocking/build/blocking.xpr -------------------------------------------------------------------------------- /CH4/VHDL/blocking/hdl/blocking.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/blocking/hdl/blocking.vhd -------------------------------------------------------------------------------- /CH4/VHDL/blocking/tb/tb_blocking.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/blocking/tb/tb_blocking.vhd -------------------------------------------------------------------------------- /CH4/VHDL/counting_buttons/build/counting_buttons.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/counting_buttons/build/counting_buttons.xpr -------------------------------------------------------------------------------- /CH4/VHDL/counting_buttons/hdl/cathode_top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/counting_buttons/hdl/cathode_top.vhd -------------------------------------------------------------------------------- /CH4/VHDL/counting_buttons/hdl/counting_buttons.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/counting_buttons/hdl/counting_buttons.vhd -------------------------------------------------------------------------------- /CH4/VHDL/counting_buttons/hdl/counting_buttons_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/counting_buttons/hdl/counting_buttons_pkg.vhd -------------------------------------------------------------------------------- /CH4/VHDL/counting_buttons/hdl/seven_segment.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/counting_buttons/hdl/seven_segment.vhd -------------------------------------------------------------------------------- /CH4/VHDL/simple_ff/build/simple_ff.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/simple_ff/build/simple_ff.xpr -------------------------------------------------------------------------------- /CH4/VHDL/simple_ff/hdl/simple_ff.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/simple_ff/hdl/simple_ff.vhd -------------------------------------------------------------------------------- /CH4/VHDL/simple_ff/tb/tb_simple_ff.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/simple_ff/tb/tb_simple_ff.vhd -------------------------------------------------------------------------------- /CH4/VHDL/simple_ff_async/build/simple_ff_async.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/simple_ff_async/build/simple_ff_async.xpr -------------------------------------------------------------------------------- /CH4/VHDL/simple_ff_async/hdl/simple_ff_async.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/simple_ff_async/hdl/simple_ff_async.vhd -------------------------------------------------------------------------------- /CH4/VHDL/simple_ff_async/tb/tb_simple_ff_async.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/VHDL/simple_ff_async/tb/tb_simple_ff_async.vhd -------------------------------------------------------------------------------- /CH4/xdc/Nexys-A7-100T-Master.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/xdc/Nexys-A7-100T-Master.xdc -------------------------------------------------------------------------------- /CH4/xdc/simple_fifo_arty_a7100t.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH4/xdc/simple_fifo_arty_a7100t.xdc -------------------------------------------------------------------------------- /CH5/IP/sys_pll/sys_pll.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/IP/sys_pll/sys_pll.xci -------------------------------------------------------------------------------- /CH5/SystemVerilog/build/calculator.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/build/calculator.xpr -------------------------------------------------------------------------------- /CH5/SystemVerilog/build/divider_nr.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/build/divider_nr.xpr -------------------------------------------------------------------------------- /CH5/SystemVerilog/build/traffic_light.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/build/traffic_light.xpr -------------------------------------------------------------------------------- /CH5/SystemVerilog/hdl/calculator_mealy.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/hdl/calculator_mealy.sv -------------------------------------------------------------------------------- /CH5/SystemVerilog/hdl/calculator_moore.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/hdl/calculator_moore.sv -------------------------------------------------------------------------------- /CH5/SystemVerilog/hdl/calculator_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/hdl/calculator_pkg.sv -------------------------------------------------------------------------------- /CH5/SystemVerilog/hdl/calculator_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/hdl/calculator_top.sv -------------------------------------------------------------------------------- /CH5/SystemVerilog/hdl/divider_nr.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/hdl/divider_nr.sv -------------------------------------------------------------------------------- /CH5/SystemVerilog/hdl/traffic_light.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/hdl/traffic_light.sv -------------------------------------------------------------------------------- /CH5/SystemVerilog/tb/tb_divider_nr.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/SystemVerilog/tb/tb_divider_nr.sv -------------------------------------------------------------------------------- /CH5/VHDL/build/calculator.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/build/calculator.xpr -------------------------------------------------------------------------------- /CH5/VHDL/build/divider_nr.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/build/divider_nr.xpr -------------------------------------------------------------------------------- /CH5/VHDL/build/traffic_light.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/build/traffic_light.xpr -------------------------------------------------------------------------------- /CH5/VHDL/hdl/calculator_mealy.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/hdl/calculator_mealy.vhd -------------------------------------------------------------------------------- /CH5/VHDL/hdl/calculator_moore.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/hdl/calculator_moore.vhd -------------------------------------------------------------------------------- /CH5/VHDL/hdl/calculator_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/hdl/calculator_pkg.vhd -------------------------------------------------------------------------------- /CH5/VHDL/hdl/calculator_top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/hdl/calculator_top.vhd -------------------------------------------------------------------------------- /CH5/VHDL/hdl/divider_nr.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/hdl/divider_nr.vhd -------------------------------------------------------------------------------- /CH5/VHDL/hdl/traffic_light.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/hdl/traffic_light.vhd -------------------------------------------------------------------------------- /CH5/VHDL/tb/tb_divider_nr.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/VHDL/tb/tb_divider_nr.vhd -------------------------------------------------------------------------------- /CH5/xdc/calculator_a7100t.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/xdc/calculator_a7100t.xdc -------------------------------------------------------------------------------- /CH5/xdc/traffic_light_a7100t.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH5/xdc/traffic_light_a7100t.xdc -------------------------------------------------------------------------------- /CH6/SystemVerilog/build/i2c_temp.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/build/i2c_temp.xpr -------------------------------------------------------------------------------- /CH6/SystemVerilog/build/pdm_audio.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/build/pdm_audio.xpr -------------------------------------------------------------------------------- /CH6/SystemVerilog/hdl/i2c_temp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/hdl/i2c_temp.sv -------------------------------------------------------------------------------- /CH6/SystemVerilog/hdl/pdm_inputs.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/hdl/pdm_inputs.sv -------------------------------------------------------------------------------- /CH6/SystemVerilog/hdl/pdm_output.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/hdl/pdm_output.sv -------------------------------------------------------------------------------- /CH6/SystemVerilog/hdl/pdm_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/hdl/pdm_top.sv -------------------------------------------------------------------------------- /CH6/SystemVerilog/hdl/pwm_outputs.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/hdl/pwm_outputs.sv -------------------------------------------------------------------------------- /CH6/SystemVerilog/hdl/temp_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/hdl/temp_pkg.sv -------------------------------------------------------------------------------- /CH6/SystemVerilog/tb/adt7420_mdl.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/tb/adt7420_mdl.sv -------------------------------------------------------------------------------- /CH6/SystemVerilog/tb/tb_pdm_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/tb/tb_pdm_top.sv -------------------------------------------------------------------------------- /CH6/SystemVerilog/tb/tb_temp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/SystemVerilog/tb/tb_temp.sv -------------------------------------------------------------------------------- /CH6/VHDL/build/i2c_temp.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/build/i2c_temp.xpr -------------------------------------------------------------------------------- /CH6/VHDL/build/pdm_audio.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/build/pdm_audio.xpr -------------------------------------------------------------------------------- /CH6/VHDL/hdl/i2c_temp.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/hdl/i2c_temp.vhd -------------------------------------------------------------------------------- /CH6/VHDL/hdl/pdm_inputs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/hdl/pdm_inputs.vhd -------------------------------------------------------------------------------- /CH6/VHDL/hdl/pdm_output.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/hdl/pdm_output.vhd -------------------------------------------------------------------------------- /CH6/VHDL/hdl/pdm_top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/hdl/pdm_top.vhd -------------------------------------------------------------------------------- /CH6/VHDL/hdl/pwm_outputs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/hdl/pwm_outputs.vhd -------------------------------------------------------------------------------- /CH6/VHDL/hdl/temp_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/hdl/temp_pkg.vhd -------------------------------------------------------------------------------- /CH6/VHDL/hdl/util_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/hdl/util_pkg.vhd -------------------------------------------------------------------------------- /CH6/VHDL/tb/adt7420_mdl.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/tb/adt7420_mdl.vhd -------------------------------------------------------------------------------- /CH6/VHDL/tb/tb_pdm_top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/tb/tb_pdm_top.vhd -------------------------------------------------------------------------------- /CH6/VHDL/tb/tb_temp.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/VHDL/tb/tb_temp.vhd -------------------------------------------------------------------------------- /CH6/xdc/i2c_temp.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/xdc/i2c_temp.xdc -------------------------------------------------------------------------------- /CH6/xdc/pdm_audio.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH6/xdc/pdm_audio.xdc -------------------------------------------------------------------------------- /CH7/IP/fix_to_float/fix_to_float.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/IP/fix_to_float/fix_to_float.xci -------------------------------------------------------------------------------- /CH7/IP/flt_to_fix/flt_to_fix.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/IP/flt_to_fix/flt_to_fix.xci -------------------------------------------------------------------------------- /CH7/IP/fp_addsub/fp_addsub.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/IP/fp_addsub/fp_addsub.xci -------------------------------------------------------------------------------- /CH7/IP/fp_fused_mult_add/fp_fused_mult_add.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/IP/fp_fused_mult_add/fp_fused_mult_add.xci -------------------------------------------------------------------------------- /CH7/IP/fp_mult/fp_mult.xci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/IP/fp_mult/fp_mult.xci -------------------------------------------------------------------------------- /CH7/SystemVerilog/build/i2c_temp.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/build/i2c_temp.xpr -------------------------------------------------------------------------------- /CH7/SystemVerilog/build/i2c_temp_flt.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/build/i2c_temp_flt.xpr -------------------------------------------------------------------------------- /CH7/SystemVerilog/build/parallel.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/build/parallel.xpr -------------------------------------------------------------------------------- /CH7/SystemVerilog/hdl/i2c_temp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/hdl/i2c_temp.sv -------------------------------------------------------------------------------- /CH7/SystemVerilog/hdl/i2c_temp_flt.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/hdl/i2c_temp_flt.sv -------------------------------------------------------------------------------- /CH7/SystemVerilog/hdl/parallel.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/hdl/parallel.sv -------------------------------------------------------------------------------- /CH7/SystemVerilog/hdl/temp_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/hdl/temp_pkg.sv -------------------------------------------------------------------------------- /CH7/SystemVerilog/tb/adt7420_mdl.sv: -------------------------------------------------------------------------------- 1 | ../../../CH6/SystemVerilog/tb/adt7420_mdl.sv -------------------------------------------------------------------------------- /CH7/SystemVerilog/tb/tb_parallel.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/tb/tb_parallel.sv -------------------------------------------------------------------------------- /CH7/SystemVerilog/tb/tb_temp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/tb/tb_temp.sv -------------------------------------------------------------------------------- /CH7/SystemVerilog/tb/tb_temp_flt.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/SystemVerilog/tb/tb_temp_flt.sv -------------------------------------------------------------------------------- /CH7/VHDL/build/i2c_temp.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/build/i2c_temp.xpr -------------------------------------------------------------------------------- /CH7/VHDL/build/i2c_temp_flt.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/build/i2c_temp_flt.xpr -------------------------------------------------------------------------------- /CH7/VHDL/build/parallel.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/build/parallel.xpr -------------------------------------------------------------------------------- /CH7/VHDL/build/parallel/parallel.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/build/parallel/parallel.xpr -------------------------------------------------------------------------------- /CH7/VHDL/hdl/i2c_temp.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/hdl/i2c_temp.vhd -------------------------------------------------------------------------------- /CH7/VHDL/hdl/i2c_temp_flt.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/hdl/i2c_temp_flt.vhd -------------------------------------------------------------------------------- /CH7/VHDL/hdl/i2c_temp_flt_components_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/hdl/i2c_temp_flt_components_pkg.vhd -------------------------------------------------------------------------------- /CH7/VHDL/hdl/parallel.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/hdl/parallel.vhd -------------------------------------------------------------------------------- /CH7/VHDL/hdl/temp_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/hdl/temp_pkg.vhd -------------------------------------------------------------------------------- /CH7/VHDL/hdl/util_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/hdl/util_pkg.vhd -------------------------------------------------------------------------------- /CH7/VHDL/tb/adt7420_mdl.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/tb/adt7420_mdl.vhd -------------------------------------------------------------------------------- /CH7/VHDL/tb/tb_parallel.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/tb/tb_parallel.vhd -------------------------------------------------------------------------------- /CH7/VHDL/tb/tb_temp.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/VHDL/tb/tb_temp.vhd -------------------------------------------------------------------------------- /CH7/xdc/i2c_temp.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH7/xdc/i2c_temp.xdc -------------------------------------------------------------------------------- /CH8/SystemVerilog/build/completed/i2c_temp_flt_bd/i2c_temp_flt_bd.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/build/completed/i2c_temp_flt_bd/i2c_temp_flt_bd.xpr -------------------------------------------------------------------------------- /CH8/SystemVerilog/build/i2c_temp_flt_bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/build/i2c_temp_flt_bd.tcl -------------------------------------------------------------------------------- /CH8/SystemVerilog/build/i2c_temp_flt_unpkg.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/build/i2c_temp_flt_unpkg.xpr -------------------------------------------------------------------------------- /CH8/SystemVerilog/build/scaffold/i2c_temp_flt_bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/build/scaffold/i2c_temp_flt_bd.tcl -------------------------------------------------------------------------------- /CH8/SystemVerilog/hdl/adt7420_i2c_bd.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/hdl/adt7420_i2c_bd.v -------------------------------------------------------------------------------- /CH8/SystemVerilog/hdl/adt7420_i2c_mod.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/hdl/adt7420_i2c_mod.sv -------------------------------------------------------------------------------- /CH8/SystemVerilog/ip_source/adt7420_i2c/hdl/adt7420_i2c.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/ip_source/adt7420_i2c/hdl/adt7420_i2c.sv -------------------------------------------------------------------------------- /CH8/SystemVerilog/ip_source/adt7420_i2c/hdl/temp_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/ip_source/adt7420_i2c/hdl/temp_pkg.sv -------------------------------------------------------------------------------- /CH8/SystemVerilog/ip_source/flt_temp/hdl/flt_temp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/ip_source/flt_temp/hdl/flt_temp.sv -------------------------------------------------------------------------------- /CH8/SystemVerilog/ip_source/flt_temp/hdl/temp_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/ip_source/flt_temp/hdl/temp_pkg.sv -------------------------------------------------------------------------------- /CH8/SystemVerilog/ip_source/seven_segment/hdl/cathode_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/ip_source/seven_segment/hdl/cathode_top.sv -------------------------------------------------------------------------------- /CH8/SystemVerilog/ip_source/seven_segment/hdl/seven_segment.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/SystemVerilog/ip_source/seven_segment/hdl/seven_segment.sv -------------------------------------------------------------------------------- /CH8/VHDL/build/completed/i2c_temp_flt_bd.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/build/completed/i2c_temp_flt_bd.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd -------------------------------------------------------------------------------- /CH8/VHDL/build/completed/i2c_temp_flt_bd.srcs/sources_1/bd/design_1/design_1.bd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/build/completed/i2c_temp_flt_bd.srcs/sources_1/bd/design_1/design_1.bd -------------------------------------------------------------------------------- /CH8/VHDL/build/completed/i2c_temp_flt_bd.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/build/completed/i2c_temp_flt_bd.xpr -------------------------------------------------------------------------------- /CH8/VHDL/build/scaffold/i2c_temp_flt_bd.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/build/scaffold/i2c_temp_flt_bd.xpr -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/adt7420_i2c/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/adt7420_i2c/component.xml -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/adt7420_i2c/hdl/adt7420_i2c.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/adt7420_i2c/hdl/adt7420_i2c.vhd -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/adt7420_i2c/xgui/adt7420_i2c_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/adt7420_i2c/xgui/adt7420_i2c_v1_0.tcl -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/flt_temp/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/flt_temp/component.xml -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/flt_temp/hdl/flt_temp.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/flt_temp/hdl/flt_temp.vhd -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/flt_temp/hdl/temp_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/flt_temp/hdl/temp_pkg.vhd -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/flt_temp/hdl/util_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/flt_temp/hdl/util_pkg.vhd -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/flt_temp/xgui/flt_temp_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/flt_temp/xgui/flt_temp_v1_0.tcl -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/seven_segment/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/seven_segment/component.xml -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/seven_segment/hdl/cathode_top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/seven_segment/hdl/cathode_top.vhd -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/seven_segment/hdl/seven_segment.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/seven_segment/hdl/seven_segment.vhd -------------------------------------------------------------------------------- /CH8/VHDL/ip_source/seven_segment/xgui/seven_segment_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/ip_source/seven_segment/xgui/seven_segment_v1_0.tcl -------------------------------------------------------------------------------- /CH8/VHDL/tb/adt7420_mdl.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/tb/adt7420_mdl.vhd -------------------------------------------------------------------------------- /CH8/VHDL/tb/tb_design_1_wrapper.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/VHDL/tb/tb_design_1_wrapper.vhd -------------------------------------------------------------------------------- /CH8/xdc/i2c_temp.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/xdc/i2c_temp.xdc -------------------------------------------------------------------------------- /CH8/xdc/i2c_temp_flt_bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH8/xdc/i2c_temp_flt_bd.tcl -------------------------------------------------------------------------------- /CH9/SystemVerilog/build/ddr2.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH9/SystemVerilog/build/ddr2.xpr -------------------------------------------------------------------------------- /CH9/SystemVerilog/hdl/example_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH9/SystemVerilog/hdl/example_top.v -------------------------------------------------------------------------------- /CH9/SystemVerilog/tb/sim_tb_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH9/SystemVerilog/tb/sim_tb_top.v -------------------------------------------------------------------------------- /CH9/VHDL/build/ddr2.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH9/VHDL/build/ddr2.xpr -------------------------------------------------------------------------------- /CH9/xdc/Nexys4DDRmemorypinout.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH9/xdc/Nexys4DDRmemorypinout.ucf -------------------------------------------------------------------------------- /CH9/xdc/ddr2.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/CH9/xdc/ddr2.xdc -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/README.md -------------------------------------------------------------------------------- /regression.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/HEAD/regression.py --------------------------------------------------------------------------------