├── quality ├── tex │ ├── c1-scope │ │ ├── book.md │ │ └── metadata.md │ ├── c2-normative-references │ │ ├── book.md │ │ └── metadata.md │ ├── c3-terms-and-definitions │ │ ├── book.md │ │ └── metadata.md │ ├── c5-leadership │ │ ├── book.md │ │ └── metadata.md │ ├── c6-planning │ │ ├── book.md │ │ └── metadata.md │ ├── c10-improvement │ │ ├── book.md │ │ └── metadata.md │ ├── c9-performance-evaluation │ │ ├── book.md │ │ └── metadata.md │ ├── c4-context-of-the-organization │ │ ├── book.md │ │ └── metadata.md │ ├── c7-support │ │ ├── book.md │ │ ├── metadata.md │ │ └── chapters │ │ │ ├── chapter4.md │ │ │ ├── chapter3.md │ │ │ └── chapter2.md │ └── c8-operation │ │ ├── book.md │ │ ├── metadata.md │ │ └── chapters │ │ └── chapter6.md ├── ISO 9001-2015-Quinta-Edición.pdf ├── ISO-9001-2015-Fifth-Edition.pdf ├── book │ ├── metadata.md │ └── book.md └── ada │ └── book │ └── book.md ├── configuration ├── go │ ├── go.mod │ └── book │ │ └── book.md ├── rust │ ├── demo │ │ ├── Cargo.toml │ │ ├── library │ │ │ └── Cargo.toml │ │ └── application │ │ │ └── Cargo.toml │ ├── library │ │ ├── pu │ │ │ ├── bb │ │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ │ └── Cargo.toml │ │ │ ├── wb │ │ │ │ └── Cargo.toml │ │ │ ├── ahb4 │ │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ │ └── Cargo.toml │ │ │ └── axi4 │ │ │ │ └── Cargo.toml │ │ ├── bfm │ │ │ ├── bb │ │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ │ └── Cargo.toml │ │ │ ├── wb │ │ │ │ └── Cargo.toml │ │ │ ├── ahb4 │ │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ │ └── Cargo.toml │ │ │ └── axi4 │ │ │ │ └── Cargo.toml │ │ ├── core │ │ │ ├── bb │ │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ │ └── Cargo.toml │ │ │ ├── wb │ │ │ │ └── Cargo.toml │ │ │ ├── ahb4 │ │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ │ └── Cargo.toml │ │ │ └── axi4 │ │ │ │ └── Cargo.toml │ │ ├── soc │ │ │ ├── bb │ │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ │ └── Cargo.toml │ │ │ ├── wb │ │ │ │ └── Cargo.toml │ │ │ ├── ahb4 │ │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ │ └── Cargo.toml │ │ │ └── axi4 │ │ │ │ └── Cargo.toml │ │ └── mpsoc │ │ │ ├── ahb4 │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ └── Cargo.toml │ │ │ ├── axi4 │ │ │ └── Cargo.toml │ │ │ ├── bb │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ └── Cargo.toml │ │ │ └── wb │ │ │ └── Cargo.toml │ ├── application │ │ ├── bfm │ │ │ ├── bb │ │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ │ └── Cargo.toml │ │ │ ├── wb │ │ │ │ └── Cargo.toml │ │ │ ├── ahb4 │ │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ │ └── Cargo.toml │ │ │ └── axi4 │ │ │ │ └── Cargo.toml │ │ ├── pu │ │ │ ├── bb │ │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ │ └── Cargo.toml │ │ │ ├── wb │ │ │ │ └── Cargo.toml │ │ │ ├── ahb4 │ │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ │ └── Cargo.toml │ │ │ └── axi4 │ │ │ │ └── Cargo.toml │ │ ├── soc │ │ │ ├── bb │ │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ │ └── Cargo.toml │ │ │ ├── wb │ │ │ │ └── Cargo.toml │ │ │ ├── ahb4 │ │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ │ └── Cargo.toml │ │ │ └── axi4 │ │ │ │ └── Cargo.toml │ │ ├── core │ │ │ ├── bb │ │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ │ └── Cargo.toml │ │ │ ├── wb │ │ │ │ └── Cargo.toml │ │ │ ├── ahb4 │ │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ │ └── Cargo.toml │ │ │ └── axi4 │ │ │ │ └── Cargo.toml │ │ └── mpsoc │ │ │ ├── bb │ │ │ └── Cargo.toml │ │ │ ├── tl │ │ │ └── Cargo.toml │ │ │ ├── wb │ │ │ └── Cargo.toml │ │ │ ├── ahb4 │ │ │ └── Cargo.toml │ │ │ ├── apb4 │ │ │ └── Cargo.toml │ │ │ └── axi4 │ │ │ └── Cargo.toml │ ├── examples │ │ └── book.md │ └── book │ │ └── book.md ├── c │ └── book │ │ └── book.md └── cpp │ └── book │ └── book.md ├── sim ├── vhdl │ ├── validation │ │ ├── uvm │ │ │ ├── pu │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── wb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── axi4 │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bfm │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── axi4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── wb │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── core │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── axi4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── wb │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── mpsoc │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── axi4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── wb │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── soc │ │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ └── wb │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── classes │ │ │ ├── bfm │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── wb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── axi4 │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── pu │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── wb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── axi4 │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── soc │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── wb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── axi4 │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── core │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── axi4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── wb │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── mpsoc │ │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ └── wb │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── osvvm │ │ │ ├── bfm │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── axi4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── bb │ │ │ │ │ ├── msim │ │ │ │ │ │ └── run.do │ │ │ │ │ └── ghdl │ │ │ │ │ │ └── system.g │ │ │ │ ├── tl │ │ │ │ │ ├── msim │ │ │ │ │ │ └── run.do │ │ │ │ │ └── ghdl │ │ │ │ │ │ └── system.g │ │ │ │ └── wb │ │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── core │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── wb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── axi4 │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── mpsoc │ │ │ │ ├── bb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── tl │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── wb │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ └── axi4 │ │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── pu │ │ │ │ ├── ahb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── axi4 │ │ │ │ │ └── msim │ │ │ │ │ │ └── run.do │ │ │ │ ├── bb │ │ │ │ │ ├── msim │ │ │ │ │ │ └── run.do │ │ │ │ │ └── ghdl │ │ │ │ │ │ └── system.g │ │ │ │ ├── tl │ │ │ │ │ ├── msim │ │ │ │ │ │ └── run.do │ │ │ │ │ └── ghdl │ │ │ │ │ │ └── system.g │ │ │ │ └── wb │ │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ └── soc │ │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ │ ├── bb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ │ ├── tl │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ │ └── wb │ │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ └── system.g │ │ └── types │ │ │ ├── bfm │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ └── wb │ │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ └── system.g │ │ │ ├── core │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── mpsoc │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── pu │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ └── wb │ │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ └── system.g │ │ │ └── soc │ │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ └── ghdl │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ └── ghdl │ │ │ │ └── system.g │ │ │ └── wb │ │ │ ├── msim │ │ │ └── run.do │ │ │ └── ghdl │ │ │ └── system.g │ └── verification │ │ ├── osvvm │ │ ├── bfm │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── pu │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── soc │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── core │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── wb │ │ │ │ └── msim │ │ │ │ └── run.do │ │ └── mpsoc │ │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ │ ├── types │ │ ├── bfm │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── pu │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── soc │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── core │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── wb │ │ │ │ └── msim │ │ │ │ └── run.do │ │ └── mpsoc │ │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ │ ├── uvm │ │ ├── bfm │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── wb │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── core │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── mpsoc │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── pu │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── wb │ │ │ │ └── msim │ │ │ │ └── run.do │ │ └── soc │ │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ │ └── classes │ │ ├── bfm │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ │ ├── core │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ │ ├── mpsoc │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── wb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ └── axi4 │ │ │ └── msim │ │ │ └── run.do │ │ ├── pu │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ │ └── soc │ │ ├── ahb4 │ │ └── msim │ │ │ └── run.do │ │ ├── apb4 │ │ └── msim │ │ │ └── run.do │ │ ├── axi4 │ │ └── msim │ │ │ └── run.do │ │ ├── bb │ │ └── msim │ │ │ └── run.do │ │ ├── tl │ │ └── msim │ │ │ └── run.do │ │ └── wb │ │ └── msim │ │ └── run.do └── verilog │ ├── validation │ ├── osvvm │ │ ├── pu │ │ │ ├── bb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── wb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── ahb4 │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── apb4 │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ └── axi4 │ │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ └── system.g │ │ ├── bfm │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ └── wb │ │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ └── system.g │ │ ├── core │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ └── wb │ │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ └── system.g │ │ ├── mpsoc │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── wb │ │ │ │ └── msim │ │ │ │ └── run.do │ │ └── soc │ │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ └── ghdl │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ └── ghdl │ │ │ │ └── system.g │ │ │ └── wb │ │ │ ├── msim │ │ │ └── run.do │ │ │ └── ghdl │ │ │ └── system.g │ ├── types │ │ ├── pu │ │ │ ├── bb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── wb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── ahb4 │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── apb4 │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ └── axi4 │ │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ └── system.g │ │ ├── bfm │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ └── wb │ │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ └── system.g │ │ ├── core │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ │ ├── msim │ │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ │ └── system.g │ │ │ └── wb │ │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ │ └── ghdl │ │ │ │ └── system.g │ │ ├── mpsoc │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── wb │ │ │ │ └── msim │ │ │ │ └── run.do │ │ └── soc │ │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ └── ghdl │ │ │ │ └── system.g │ │ │ ├── tl │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ └── ghdl │ │ │ │ └── system.g │ │ │ └── wb │ │ │ ├── msim │ │ │ └── run.do │ │ │ └── ghdl │ │ │ └── system.g │ ├── uvm │ │ ├── bfm │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── core │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── pu │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── wb │ │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── soc │ │ │ ├── bb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── wb │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── ahb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ │ └── msim │ │ │ │ │ └── run.do │ │ │ └── axi4 │ │ │ │ └── msim │ │ │ │ └── run.do │ │ └── mpsoc │ │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ └── classes │ │ ├── bfm │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ │ ├── core │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── wb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ └── axi4 │ │ │ └── msim │ │ │ └── run.do │ │ ├── mpsoc │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── wb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ └── axi4 │ │ │ └── msim │ │ │ └── run.do │ │ ├── pu │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ │ └── soc │ │ ├── ahb4 │ │ └── msim │ │ │ └── run.do │ │ ├── apb4 │ │ └── msim │ │ │ └── run.do │ │ ├── axi4 │ │ └── msim │ │ │ └── run.do │ │ ├── bb │ │ └── msim │ │ │ └── run.do │ │ ├── tl │ │ └── msim │ │ │ └── run.do │ │ └── wb │ │ └── msim │ │ └── run.do │ └── verification │ ├── uvm │ ├── pu │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── wb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ └── axi4 │ │ │ └── msim │ │ │ └── run.do │ ├── bfm │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ ├── core │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ ├── mpsoc │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ └── soc │ │ ├── ahb4 │ │ └── msim │ │ │ └── run.do │ │ ├── apb4 │ │ └── msim │ │ │ └── run.do │ │ ├── axi4 │ │ └── msim │ │ │ └── run.do │ │ ├── bb │ │ └── msim │ │ │ └── run.do │ │ ├── tl │ │ └── msim │ │ │ └── run.do │ │ └── wb │ │ └── msim │ │ └── run.do │ ├── classes │ ├── bfm │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── wb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ └── axi4 │ │ │ └── msim │ │ │ └── run.do │ ├── pu │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── wb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ └── axi4 │ │ │ └── msim │ │ │ └── run.do │ ├── soc │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── wb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ └── axi4 │ │ │ └── msim │ │ │ └── run.do │ ├── core │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ └── mpsoc │ │ ├── ahb4 │ │ └── msim │ │ │ └── run.do │ │ ├── apb4 │ │ └── msim │ │ │ └── run.do │ │ ├── axi4 │ │ └── msim │ │ │ └── run.do │ │ ├── bb │ │ └── msim │ │ │ └── run.do │ │ ├── tl │ │ └── msim │ │ │ └── run.do │ │ └── wb │ │ └── msim │ │ └── run.do │ ├── osvvm │ ├── bfm │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ └── wb │ │ │ └── msim │ │ │ └── run.do │ ├── core │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── wb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ └── axi4 │ │ │ └── msim │ │ │ └── run.do │ ├── mpsoc │ │ ├── bb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── tl │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── wb │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ └── axi4 │ │ │ └── msim │ │ │ └── run.do │ ├── pu │ │ ├── ahb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── apb4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── axi4 │ │ │ └── msim │ │ │ │ └── run.do │ │ ├── bb │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ └── ghdl │ │ │ │ └── system.g │ │ ├── tl │ │ │ ├── msim │ │ │ │ └── run.do │ │ │ └── ghdl │ │ │ │ └── system.g │ │ └── wb │ │ │ ├── msim │ │ │ └── run.do │ │ │ └── ghdl │ │ │ └── system.g │ └── soc │ │ ├── ahb4 │ │ └── msim │ │ │ └── run.do │ │ ├── apb4 │ │ └── msim │ │ │ └── run.do │ │ ├── axi4 │ │ └── msim │ │ │ └── run.do │ │ ├── bb │ │ └── msim │ │ │ └── run.do │ │ ├── tl │ │ └── msim │ │ │ └── run.do │ │ └── wb │ │ └── msim │ │ └── run.do │ └── types │ ├── bfm │ ├── ahb4 │ │ └── msim │ │ │ └── run.do │ ├── apb4 │ │ └── msim │ │ │ └── run.do │ ├── axi4 │ │ └── msim │ │ │ └── run.do │ ├── bb │ │ └── msim │ │ │ └── run.do │ ├── tl │ │ └── msim │ │ │ └── run.do │ └── wb │ │ └── msim │ │ └── run.do │ ├── core │ ├── bb │ │ └── msim │ │ │ └── run.do │ ├── tl │ │ └── msim │ │ │ └── run.do │ ├── wb │ │ └── msim │ │ │ └── run.do │ ├── ahb4 │ │ └── msim │ │ │ └── run.do │ ├── apb4 │ │ └── msim │ │ │ └── run.do │ └── axi4 │ │ └── msim │ │ └── run.do │ ├── mpsoc │ ├── bb │ │ └── msim │ │ │ └── run.do │ ├── tl │ │ └── msim │ │ │ └── run.do │ ├── wb │ │ └── msim │ │ │ └── run.do │ ├── ahb4 │ │ └── msim │ │ │ └── run.do │ ├── apb4 │ │ └── msim │ │ │ └── run.do │ └── axi4 │ │ └── msim │ │ └── run.do │ ├── pu │ ├── ahb4 │ │ └── msim │ │ │ └── run.do │ ├── apb4 │ │ └── msim │ │ │ └── run.do │ ├── axi4 │ │ └── msim │ │ │ └── run.do │ ├── bb │ │ ├── msim │ │ │ └── run.do │ │ └── ghdl │ │ │ └── system.g │ ├── tl │ │ └── msim │ │ │ └── run.do │ └── wb │ │ └── msim │ │ └── run.do │ └── soc │ ├── ahb4 │ └── msim │ │ └── run.do │ ├── apb4 │ └── msim │ │ └── run.do │ ├── axi4 │ └── msim │ │ └── run.do │ ├── bb │ └── msim │ │ └── run.do │ ├── tl │ └── msim │ │ └── run.do │ └── wb │ └── msim │ └── run.do ├── tag.sh ├── icon.jpg ├── upload.sh ├── verilog2vhdl.png ├── certification ├── RTCA-DO-178B.pdf ├── RTCA-DO-254.pdf ├── template │ ├── book.md │ └── metadata.md ├── rtca │ ├── hardware │ │ ├── metadata.md │ │ └── book.md │ └── software │ │ ├── metadata.md │ │ └── book.md └── book │ ├── metadata.md │ └── book.md ├── doc ├── book │ ├── assets │ │ ├── chapter3 │ │ │ ├── dnc.png │ │ │ ├── ntm_top.jpg │ │ │ ├── ntm_decoder.png │ │ │ ├── ntm_encoder.png │ │ │ ├── ntm_heads.jpg │ │ │ ├── ntm_addressing.jpg │ │ │ ├── ntm_controller.png │ │ │ ├── ntm_inputs_vector.png │ │ │ ├── ntm_multi_head_attention.png │ │ │ ├── ntm_scaled_dot_product_attention.png │ │ │ └── automata-theory.dot │ │ ├── chapter5 │ │ │ ├── dnc.png │ │ │ ├── ntm_top.jpg │ │ │ ├── ntm_decoder.png │ │ │ ├── ntm_encoder.png │ │ │ ├── ntm_heads.jpg │ │ │ ├── ntm_addressing.jpg │ │ │ ├── ntm_controller.png │ │ │ ├── ntm_inputs_vector.png │ │ │ ├── ntm_multi_head_attention.png │ │ │ ├── ntm_scaled_dot_product_attention.png │ │ │ └── automata-theory.dot │ │ └── chapter13 │ │ │ └── hardware-verification.dot │ ├── metadata.md │ └── book.md └── acceleration │ ├── traditional.md │ ├── metadata.md │ └── assets │ └── chapter2 │ └── automata-theory.dot ├── install.sh ├── lifecycle ├── edition │ ├── assets │ │ └── chapter4 │ │ │ ├── back-end.png │ │ │ ├── front-end.png │ │ │ ├── codesign-project.png │ │ │ ├── hardware-project.png │ │ │ └── software-project.png │ ├── edition.md │ └── metadata.md ├── devops │ ├── assets │ │ ├── chapter1 │ │ │ ├── codesign-project.png │ │ │ ├── hardware-project.png │ │ │ └── software-project.png │ │ ├── chapter3 │ │ │ ├── user-developer.dot │ │ │ └── management.dot │ │ └── chapter4 │ │ │ ├── hardware-4004-verification.dot │ │ │ ├── hardware-msp430-verification.dot │ │ │ └── hardware-riscv-verification.dot │ ├── book.md │ └── metadata.md ├── book │ ├── metadata.md │ └── book.md └── chisel │ ├── application │ ├── bfm │ │ ├── bb │ │ │ └── peripheral_test.scala │ │ ├── tl │ │ │ └── peripheral_test.scala │ │ ├── wb │ │ │ └── peripheral_test.scala │ │ ├── ahb4 │ │ │ └── peripheral_test.scala │ │ ├── apb4 │ │ │ └── peripheral_test.scala │ │ └── axi4 │ │ │ └── peripheral_test.scala │ ├── core │ │ ├── bb │ │ │ └── peripheral_test.scala │ │ ├── tl │ │ │ └── peripheral_test.scala │ │ ├── wb │ │ │ └── peripheral_test.scala │ │ ├── ahb4 │ │ │ └── peripheral_test.scala │ │ ├── apb4 │ │ │ └── peripheral_test.scala │ │ └── axi4 │ │ │ └── peripheral_test.scala │ ├── pu │ │ ├── ahb4 │ │ │ └── peripheral_test.scala │ │ ├── apb4 │ │ │ └── peripheral_test.scala │ │ ├── axi4 │ │ │ └── peripheral_test.scala │ │ ├── bb │ │ │ └── peripheral_test.scala │ │ ├── tl │ │ │ └── peripheral_test.scala │ │ └── wb │ │ │ └── peripheral_test.scala │ ├── soc │ │ ├── bb │ │ │ └── peripheral_test.scala │ │ ├── tl │ │ │ └── peripheral_test.scala │ │ ├── wb │ │ │ └── peripheral_test.scala │ │ ├── ahb4 │ │ │ └── peripheral_test.scala │ │ ├── apb4 │ │ │ └── peripheral_test.scala │ │ └── axi4 │ │ │ └── peripheral_test.scala │ └── mpsoc │ │ ├── ahb4 │ │ └── peripheral_test.scala │ │ ├── apb4 │ │ └── peripheral_test.scala │ │ ├── axi4 │ │ └── peripheral_test.scala │ │ ├── bb │ │ └── peripheral_test.scala │ │ ├── tl │ │ └── peripheral_test.scala │ │ └── wb │ │ └── peripheral_test.scala │ └── book │ └── book.md ├── validation ├── tasks │ └── book │ │ └── metadata.md ├── uvm │ └── book │ │ ├── metadata.md │ │ └── uvm.md ├── classes │ └── book │ │ └── metadata.md ├── osvvm │ └── book │ │ ├── metadata.md │ │ └── osvvm.md ├── types │ └── book │ │ ├── metadata.md │ │ └── types.md └── procedures │ └── book │ ├── metadata.md │ └── types.md ├── verification ├── uvm │ ├── book │ │ ├── metadata.md │ │ └── uvm.md │ └── library │ │ ├── bfm │ │ ├── axi4 │ │ │ └── peripheral_uvm_sequencer.sv │ │ └── bb │ │ │ └── peripheral_uvm_sequencer.sv │ │ └── core │ │ └── bb │ │ └── peripheral_uvm_sequencer.sv ├── classes │ └── book │ │ └── metadata.md ├── tasks │ └── book │ │ └── metadata.md ├── osvvm │ └── book │ │ ├── metadata.md │ │ └── osvvm.md ├── types │ └── book │ │ ├── metadata.md │ │ └── types.md └── procedures │ └── book │ ├── metadata.md │ └── types.md └── requirements ├── psl └── book │ └── book.md ├── python └── book │ └── book.md └── matlab └── book └── book.md /quality/tex/c1-scope/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacoReinaCampo/verilog2vhdl/HEAD/icon.jpg -------------------------------------------------------------------------------- /configuration/rust/demo/Cargo.toml: -------------------------------------------------------------------------------- 1 | [workspace] 2 | members = ["library", "application"] 3 | -------------------------------------------------------------------------------- /upload.sh: -------------------------------------------------------------------------------- 1 | git add * 2 | git commit -m "Working in HDL Translator ✏️" 3 | git push origin main 4 | -------------------------------------------------------------------------------- /verilog2vhdl.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PacoReinaCampo/verilog2vhdl/HEAD/verilog2vhdl.png -------------------------------------------------------------------------------- /quality/tex/c5-leadership/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | -------------------------------------------------------------------------------- /quality/tex/c6-planning/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | -------------------------------------------------------------------------------- /quality/tex/c10-improvement/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | -------------------------------------------------------------------------------- /certification/RTCA-DO-178B.pdf: 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6 | 7 | [dependencies] -------------------------------------------------------------------------------- /configuration/rust/library/pu/ahb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "pu_library_ahb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] -------------------------------------------------------------------------------- /configuration/rust/library/pu/apb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "pu_library_apb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] -------------------------------------------------------------------------------- /configuration/rust/library/pu/axi4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "pu_library_axi4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = 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"0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] -------------------------------------------------------------------------------- /configuration/rust/library/mpsoc/ahb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mpsoc_library_ahb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] -------------------------------------------------------------------------------- /configuration/rust/library/mpsoc/apb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mpsoc_library_apb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] -------------------------------------------------------------------------------- /configuration/rust/library/mpsoc/axi4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = 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DO-254. 8 | --- 9 | -------------------------------------------------------------------------------- /certification/template/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Certification' 3 | subtitle: 'QueenField ![](../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Certification. DO-254. 8 | --- 9 | -------------------------------------------------------------------------------- /configuration/rust/demo/application/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "application" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | library = { path = "../library" } 9 | -------------------------------------------------------------------------------- /quality/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Quality Assurance' 3 | subtitle: 'QueenField ![](../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /quality/tex/c1-scope/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Scope' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /quality/tex/c8-operation/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | -------------------------------------------------------------------------------- /quality/tex/c6-planning/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Planning' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /quality/tex/c7-support/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Support' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /validation/tasks/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Universal Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Universal Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /validation/uvm/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Universal Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Universal Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /verification/uvm/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Universal Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Universal Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /doc/acceleration/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: '**Traditional Computing Theory**' 3 | subtitle: 'QueenField ![](../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Traditional Computing Theory. 8 | --- -------------------------------------------------------------------------------- /quality/tex/c5-leadership/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Leadership' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /quality/tex/c8-operation/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Operation' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /validation/classes/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Universal Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Universal Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /verification/classes/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Universal Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Universal Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /verification/tasks/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Universal Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Universal Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /quality/tex/c10-improvement/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Improvement' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /lifecycle/devops/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | -------------------------------------------------------------------------------- /validation/osvvm/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Open Source VHDL Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Open Source VHDL Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /validation/types/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Open Source VHDL Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Open Source VHDL Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /validation/uvm/book/uvm.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | -------------------------------------------------------------------------------- /verification/uvm/book/uvm.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | -------------------------------------------------------------------------------- /validation/procedures/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Open Source VHDL Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Open Source VHDL Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /verification/osvvm/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Open Source VHDL Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Open Source VHDL Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /verification/types/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Open Source VHDL Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Open Source VHDL Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /configuration/rust/application/bfm/bb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "bfm_bb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | bfm_library_bb = { path = "../../../library/bfm/bb" } -------------------------------------------------------------------------------- /configuration/rust/application/bfm/tl/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "bfm_tl" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | bfm_library_tl = { path = "../../../library/bfm/tl" } -------------------------------------------------------------------------------- /configuration/rust/application/bfm/wb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "bfm_wb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | bfm_library_wb = { path = "../../../library/bfm/wb" } -------------------------------------------------------------------------------- /configuration/rust/application/pu/bb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "pu_bb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | pu_library_bb = { path = "../../../library/pu/bb" } -------------------------------------------------------------------------------- /configuration/rust/application/pu/tl/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "pu_tl" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | pu_library_tl = { path = "../../../library/pu/tl" } -------------------------------------------------------------------------------- /configuration/rust/application/pu/wb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "pu_wb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | pu_library_wb = { path = "../../../library/pu/wb" } -------------------------------------------------------------------------------- /configuration/rust/application/soc/bb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "soc_bb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | soc_library_bb = { path = "../../../library/soc/bb" } -------------------------------------------------------------------------------- /configuration/rust/application/soc/tl/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "soc_tl" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | soc_library_tl = { path = "../../../library/soc/tl" } -------------------------------------------------------------------------------- /configuration/rust/application/soc/wb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "soc_wb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | soc_library_wb = { path = "../../../library/soc/wb" } -------------------------------------------------------------------------------- /quality/tex/c2-normative-references/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Normative references' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /quality/tex/c3-terms-and-definitions/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Term and Definitions' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /verification/procedures/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Open Source VHDL Verification Methodology' 3 | subtitle: 'QueenField' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Open Source VHDL Verification Methodology. 8 | --- 9 | -------------------------------------------------------------------------------- /configuration/rust/application/core/bb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "core_bb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | core_library_bb = { path = "../../../library/core/bb" } -------------------------------------------------------------------------------- /configuration/rust/application/core/tl/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "core_tl" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | core_library_tl = { path = "../../../library/core/tl" } -------------------------------------------------------------------------------- /configuration/rust/application/core/wb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "core_wb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | core_library_wb = { path = "../../../library/core/wb" } -------------------------------------------------------------------------------- /configuration/rust/application/pu/ahb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "pu_ahb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | pu_library_ahb4 = { path = "../../../library/pu/ahb4" } -------------------------------------------------------------------------------- /configuration/rust/application/pu/apb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "pu_apb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | pu_library_apb4 = { path = "../../../library/pu/apb4" } -------------------------------------------------------------------------------- /configuration/rust/application/pu/axi4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "pu_axi4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | pu_library_axi4 = { path = "../../../library/pu/axi4" } -------------------------------------------------------------------------------- /lifecycle/devops/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'DevOps' 3 | subtitle: 'QueenField ![](assets/chapter1/devops-toolchain.svg){width=17cm}' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: DevOps for Hardware and Software Systems. 8 | --- 9 | -------------------------------------------------------------------------------- /quality/tex/c9-performance-evaluation/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Performance Evaluation' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /configuration/rust/application/bfm/ahb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "bfm_ahb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | bfm_library_ahb4 = { path = "../../../library/bfm/ahb4" } -------------------------------------------------------------------------------- /configuration/rust/application/bfm/apb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "bfm_apb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | bfm_library_apb4 = { path = "../../../library/bfm/apb4" } -------------------------------------------------------------------------------- /configuration/rust/application/bfm/axi4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "bfm_axi4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | bfm_library_axi4 = { path = "../../../library/bfm/axi4" } -------------------------------------------------------------------------------- /configuration/rust/application/mpsoc/bb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mpsoc_bb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | mpsoc_library_bb = { path = "../../../library/mpsoc/bb" } -------------------------------------------------------------------------------- /configuration/rust/application/mpsoc/tl/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mpsoc_tl" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | mpsoc_library_tl = { path = "../../../library/mpsoc/tl" } -------------------------------------------------------------------------------- /configuration/rust/application/mpsoc/wb/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mpsoc_wb" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | mpsoc_library_wb = { path = "../../../library/mpsoc/wb" } -------------------------------------------------------------------------------- /configuration/rust/application/soc/ahb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "soc_ahb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | soc_library_ahb4 = { path = "../../../library/soc/ahb4" } -------------------------------------------------------------------------------- /configuration/rust/application/soc/apb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "soc_apb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | soc_library_apb4 = { path = "../../../library/soc/apb4" } -------------------------------------------------------------------------------- /configuration/rust/application/soc/axi4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "soc_axi4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | soc_library_axi4 = { path = "../../../library/soc/axi4" } -------------------------------------------------------------------------------- /lifecycle/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Design Lifecycle Data' 3 | subtitle: 'QueenField ![](assets/front/open-source-hardware.svg){width=17cm}' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Hardware Certification. DO-254. 8 | --- 9 | -------------------------------------------------------------------------------- /configuration/rust/application/core/ahb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "core_ahb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | core_library_ahb4 = { path = "../../../library/core/ahb4" } -------------------------------------------------------------------------------- /configuration/rust/application/core/apb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "core_apb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | core_library_apb4 = { path = "../../../library/core/apb4" } -------------------------------------------------------------------------------- /configuration/rust/application/core/axi4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "core_axi4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | core_library_axi4 = { path = "../../../library/core/axi4" } -------------------------------------------------------------------------------- /quality/tex/c4-context-of-the-organization/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Context of the Organization' 3 | subtitle: 'QueenField ![](../../../../icon.jpg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Quality Assurance. ISO 9001:2015. 8 | --- 9 | -------------------------------------------------------------------------------- /configuration/rust/application/mpsoc/ahb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mpsoc_ahb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | mpsoc_library_ahb4 = { path = "../../../library/mpsoc/ahb4" } -------------------------------------------------------------------------------- /configuration/rust/application/mpsoc/apb4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mpsoc_apb4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | mpsoc_library_apb4 = { path = "../../../library/mpsoc/apb4" } -------------------------------------------------------------------------------- /configuration/rust/application/mpsoc/axi4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mpsoc_axi4" 3 | version = "0.0.0" 4 | authors = [] 5 | edition = "2021" 6 | 7 | [dependencies] 8 | rand = "0.9.0" 9 | mpsoc_library_axi4 = { path = "../../../library/mpsoc/axi4" } -------------------------------------------------------------------------------- /lifecycle/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | -------------------------------------------------------------------------------- /requirements/psl/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | -------------------------------------------------------------------------------- /quality/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | -------------------------------------------------------------------------------- /lifecycle/edition/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'Edition' 3 | subtitle: 'QueenField ![](assets/front/open-source-hardware.svg)' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: Edición de la documentación de los proyectos Application, Advanced, Architecture, DV, EDA y Peripheral. 8 | --- 9 | -------------------------------------------------------------------------------- /requirements/python/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | -------------------------------------------------------------------------------- /certification/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | -------------------------------------------------------------------------------- /quality/tex/c7-support/chapters/chapter4.md: -------------------------------------------------------------------------------- 1 | # COMMUNICATION 2 | 3 | The organization must determine the internal and external communications relevant to the QMS, including: 4 | 5 | * What needs to be communicated. 6 | * When to communicate. 7 | * With whom to communicate. 8 | * How to communicate. 9 | -------------------------------------------------------------------------------- /configuration/rust/examples/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter21.md 2 | chapters/chapter22.md 3 | chapters/chapter23.md 4 | chapters/chapter24.md 5 | chapters/chapter25.md 6 | chapters/chapter26.md 7 | chapters/chapter27.md 8 | chapters/chapter28.md 9 | chapters/chapter29.md 10 | chapters/chapter30.md 11 | chapters/chapter31.md 12 | -------------------------------------------------------------------------------- /lifecycle/devops/assets/chapter3/user-developer.dot: -------------------------------------------------------------------------------- 1 | digraph Project { 2 | // Introduction 3 | graph [rankdir = LR, splines=ortho]; 4 | node[shape=record]; 5 | 6 | // Blocks 7 | user[label="user"]; 8 | developer[label="developer"]; 9 | 10 | // Sequence 11 | user -> developer; 12 | developer -> user; 13 | } 14 | -------------------------------------------------------------------------------- /quality/tex/c7-support/chapters/chapter3.md: -------------------------------------------------------------------------------- 1 | # AWARENESS 2 | 3 | Employees must be aware of: 4 | 5 | * The quality policy. 6 | * Relevant quality objectives. 7 | * Their contribution to the effectiveness of the QMS, including the benefits of improved performance. 8 | * The implications of not conforming to QMS requirements. 9 | -------------------------------------------------------------------------------- /validation/osvvm/book/osvvm.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | -------------------------------------------------------------------------------- /validation/types/book/types.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | -------------------------------------------------------------------------------- /verification/osvvm/book/osvvm.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | -------------------------------------------------------------------------------- /verification/types/book/types.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | -------------------------------------------------------------------------------- /validation/procedures/book/types.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | -------------------------------------------------------------------------------- /verification/procedures/book/types.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/bfm/bb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/bfm/tl/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/bfm/wb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/core/bb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/core/tl/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/core/wb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/pu/ahb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/pu/apb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/pu/axi4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/pu/bb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/pu/tl/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/pu/wb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/soc/bb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/soc/tl/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/soc/wb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/bfm/ahb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/bfm/apb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/bfm/axi4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/core/ahb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/core/apb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/core/axi4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/mpsoc/ahb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/mpsoc/apb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/mpsoc/axi4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/mpsoc/bb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/mpsoc/tl/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/mpsoc/wb/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/soc/ahb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/soc/apb4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /lifecycle/chisel/application/soc/axi4/peripheral_test.scala: -------------------------------------------------------------------------------- 1 | import chisel3._ 2 | 3 | class HelloWorld extends Module { 4 | val io = IO(new Bundle { 5 | val out = Output(UInt(8.W)) 6 | }) 7 | 8 | io.out := "helloworld".U 9 | } 10 | 11 | object HelloWorld extends App { 12 | chisel3.Driver.execute(args, () => new HelloWorld) 13 | } 14 | -------------------------------------------------------------------------------- /quality/ada/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | chapters/chapter13.md 14 | -------------------------------------------------------------------------------- /verification/uvm/library/bfm/axi4/peripheral_uvm_sequencer.sv: -------------------------------------------------------------------------------- 1 | class peripheral_uvm_sequencer extends uvm_sequencer #(peripheral_uvm_transaction); 2 | // Declaration of component utils to register with factory 3 | `uvm_component_utils(peripheral_uvm_sequencer) 4 | 5 | // Constructor 6 | function new(string name, uvm_component parent); 7 | super.new(name, parent); 8 | endfunction 9 | endclass 10 | -------------------------------------------------------------------------------- /verification/uvm/library/bfm/bb/peripheral_uvm_sequencer.sv: -------------------------------------------------------------------------------- 1 | class peripheral_uvm_sequencer extends uvm_sequencer #(peripheral_uvm_transaction); 2 | // Declaration of component utils to register with factory 3 | `uvm_component_utils(peripheral_uvm_sequencer) 4 | 5 | // Constructor 6 | function new(string name, uvm_component parent); 7 | super.new(name, parent); 8 | endfunction 9 | endclass 10 | -------------------------------------------------------------------------------- /verification/uvm/library/core/bb/peripheral_uvm_sequencer.sv: -------------------------------------------------------------------------------- 1 | class peripheral_uvm_sequencer extends uvm_sequencer #(peripheral_uvm_transaction); 2 | // Declaration of component utils to register with factory 3 | `uvm_component_utils(peripheral_uvm_sequencer) 4 | 5 | // Constructor 6 | function new(string name, uvm_component parent); 7 | super.new(name, parent); 8 | endfunction 9 | endclass 10 | -------------------------------------------------------------------------------- /lifecycle/chisel/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | chapters/chapter13.md 14 | chapters/chapter14.md 15 | chapters/chapter15.md 16 | -------------------------------------------------------------------------------- /certification/rtca/software/book.md: -------------------------------------------------------------------------------- 1 | chapters/init.md 2 | chapters/chapter1.md 3 | chapters/chapter2.md 4 | chapters/chapter3.md 5 | chapters/chapter4.md 6 | chapters/chapter5.md 7 | chapters/chapter6.md 8 | chapters/chapter7.md 9 | chapters/chapter8.md 10 | chapters/chapter9.md 11 | chapters/chapter10.md 12 | chapters/chapter11.md 13 | chapters/chapter12.md 14 | appendix/appendix-a.md 15 | annex/annex-a.md 16 | annex/annex-b.md 17 | -------------------------------------------------------------------------------- /quality/tex/c8-operation/chapters/chapter6.md: -------------------------------------------------------------------------------- 1 | # RELEASE OF PRODUCTS AND SERVICES 2 | 3 | The organization must establish procedures for the release of products and services to ensure that they meet specified requirements before delivery to customers. This includes: 4 | 5 | * Conducting final inspections and tests to verify product and service conformity. 6 | * Obtaining customer approval or acceptance before delivering products and services. 7 | -------------------------------------------------------------------------------- /certification/rtca/hardware/book.md: -------------------------------------------------------------------------------- 1 | chapters/init.md 2 | chapters/chapter-1.md 3 | chapters/chapter-2.md 4 | chapters/chapter-3.md 5 | chapters/chapter-4.md 6 | chapters/chapter-5.md 7 | chapters/chapter-6.md 8 | chapters/chapter-7.md 9 | chapters/chapter-8.md 10 | chapters/chapter-9.md 11 | chapters/chapter-10.md 12 | chapters/chapter-11.md 13 | appendix/appendix-a.md 14 | appendix/appendix-b.md 15 | appendix/appendix-c.md 16 | appendix/appendix-d.md 17 | -------------------------------------------------------------------------------- /configuration/go/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | chapters/chapter13.md 14 | chapters/chapter14.md 15 | chapters/chapter15.md 16 | chapters/chapter16.md 17 | chapters/chapter17.md 18 | -------------------------------------------------------------------------------- /doc/book/metadata.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: 'verilog2vhdl' 3 | subtitle: 'QueenField ![](../../verilog2vhdl.svg){width=17cm}' 4 | 5 | author: Paco Reina Campo 6 | 7 | abstract: A Hardware Description Language (HDL) is a specialized computer language used to describe the structure and behavior of digital logic circuits. It allows for the synthesis of a HDL into a netlist, which can then be synthesized, placed and routed to produce the set of masks used to create an integrated circuit. 8 | --- 9 | -------------------------------------------------------------------------------- /lifecycle/devops/assets/chapter3/management.dot: -------------------------------------------------------------------------------- 1 | digraph Project { 2 | // Introduction 3 | graph [rankdir = LR, splines=ortho]; 4 | node[shape=record]; 5 | 6 | // Blocks 7 | BFM[label="BFM"]; 8 | Peripheral[label="Peripheral"]; 9 | Core[label="Core"]; 10 | PU[label="PU"]; 11 | SoC[label="SoC"]; 12 | MPSoC[label="MPSoC"]; 13 | 14 | // Sequence 15 | BFM -> Peripheral; 16 | BFM -> Core; 17 | Core -> PU; 18 | Peripheral -> SoC; 19 | PU -> SoC; 20 | SoC -> MPSoC; 21 | } 22 | -------------------------------------------------------------------------------- /doc/book/assets/chapter3/automata-theory.dot: -------------------------------------------------------------------------------- 1 | digraph Project { 2 | // Introduction 3 | graph [rankdir = LR, splines=ortho]; 4 | node[shape=record]; 5 | 6 | // Blocks 7 | subgraph "cluster TuringMachine" { label = "Turing Machine"; 8 | subgraph "cluster PushdownAutomaton" { label = "Pushdown Automaton"; 9 | subgraph "cluster FiniteStateMachine" { label = "Finite State Machine"; 10 | CombinationalLogic[shape=box, label="Combinational Logic"]; 11 | } 12 | } 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /doc/book/assets/chapter5/automata-theory.dot: -------------------------------------------------------------------------------- 1 | digraph Project { 2 | // Introduction 3 | graph [rankdir = LR, splines=ortho]; 4 | node[shape=record]; 5 | 6 | // Blocks 7 | subgraph "cluster TuringMachine" { label = "Turing Machine"; 8 | subgraph "cluster PushdownAutomaton" { label = "Pushdown Automaton"; 9 | subgraph "cluster FiniteStateMachine" { label = "Finite State Machine"; 10 | CombinationalLogic[shape=box, label="Combinational Logic"]; 11 | } 12 | } 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /doc/acceleration/assets/chapter2/automata-theory.dot: -------------------------------------------------------------------------------- 1 | digraph Project { 2 | // Introduction 3 | graph [rankdir = LR, splines=ortho]; 4 | node[shape=record]; 5 | 6 | // Blocks 7 | subgraph "cluster TuringMachine" { label = "Turing Machine"; 8 | subgraph "cluster PushdownAutomaton" { label = "Pushdown Automaton"; 9 | subgraph "cluster FiniteStateMachine" { label = "Finite State Machine"; 10 | CombinationalLogic[shape=box, label="Combinational Logic"]; 11 | } 12 | } 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /configuration/cpp/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | chapters/chapter13.md 14 | chapters/chapter14.md 15 | chapters/chapter15.md 16 | chapters/chapter16.md 17 | chapters/chapter17.md 18 | chapters/chapter18.md 19 | chapters/chapter19.md 20 | chapters/chapter20.md 21 | -------------------------------------------------------------------------------- /configuration/rust/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | chapters/chapter13.md 14 | chapters/chapter14.md 15 | chapters/chapter15.md 16 | chapters/chapter16.md 17 | chapters/chapter17.md 18 | chapters/chapter18.md 19 | chapters/chapter19.md 20 | chapters/chapter20.md 21 | -------------------------------------------------------------------------------- /quality/tex/c7-support/chapters/chapter2.md: -------------------------------------------------------------------------------- 1 | # COMPETENCE 2 | 3 | The organization must ensure that employees performing work affecting the quality of products and services are competent based on appropriate education, training, skills, and experience. This involves: 4 | 5 | * Determining the necessary competence for personnel performing work. 6 | * Providing training or taking other actions to achieve the necessary competence. 7 | * Evaluating the effectiveness of these actions. 8 | * Retaining documented information as evidence of competence. 9 | -------------------------------------------------------------------------------- /requirements/matlab/book/book.md: -------------------------------------------------------------------------------- 1 | chapters/chapter1.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | chapters/chapter13.md 14 | chapters/chapter14.md 15 | chapters/chapter15.md 16 | chapters/chapter16.md 17 | chapters/chapter17.md 18 | chapters/chapter18.md 19 | chapters/chapter19.md 20 | chapters/chapter20.md 21 | -------------------------------------------------------------------------------- /doc/book/book.md: -------------------------------------------------------------------------------- 1 | preface/preface.md 2 | chapters/chapter2.md 3 | chapters/chapter3.md 4 | chapters/chapter4.md 5 | chapters/chapter5.md 6 | chapters/chapter6.md 7 | chapters/chapter7.md 8 | chapters/chapter8.md 9 | chapters/chapter9.md 10 | chapters/chapter10.md 11 | chapters/chapter11.md 12 | chapters/chapter12.md 13 | chapters/chapter13.md 14 | chapters/chapter14.md 15 | chapters/chapter15.md 16 | appendix/appendix1.md 17 | appendix/appendix2.md 18 | appendix/appendix3.md 19 | appendix/appendix4.md 20 | appendix/appendix5.md 21 | appendix/appendix6.md 22 | -------------------------------------------------------------------------------- /doc/book/assets/chapter13/hardware-verification.dot: -------------------------------------------------------------------------------- 1 | digraph Project { 2 | // Introduction 3 | graph [rankdir = LR, splines=ortho]; 4 | node[shape=record]; 5 | 6 | // Blocks 7 | subgraph "cluster TestBench" { label = "TestBench"; 8 | Stimulus[shape=box, label="Stimulus"]; 9 | Model[shape=box, label="Model (Target)"]; 10 | DUT[shape=box, label="DUT (Device)"]; 11 | Asserts[shape=box, label="Asserts"]; 12 | } 13 | 14 | // Sequence 15 | Stimulus -> Model; 16 | Stimulus -> DUT; 17 | Model -> Asserts; 18 | DUT -> Asserts; 19 | } 20 | -------------------------------------------------------------------------------- /sim/vhdl/validation/osvvm/pu/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/bb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/bb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/bb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/bb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/bb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/osvvm/pu/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/tl/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/tl/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/tl/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/tl/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/tl/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/osvvm/pu/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/wb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/wb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/wb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/wb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/wb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/types/pu/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/bb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/bb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/bb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/bb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/bb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/types/pu/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/tl/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/tl/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/tl/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/tl/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/tl/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/types/pu/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/wb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/wb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/wb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/wb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/wb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/pu/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/bb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/bb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/bb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/bb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/bb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/pu/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/tl/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/tl/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/tl/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/tl/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/tl/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/pu/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/wb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/wb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/wb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/wb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/wb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/pu/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/bb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/bb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/bb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/bb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/bb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/pu/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/tl/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/tl/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/tl/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/tl/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/tl/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/pu/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/wb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/wb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/wb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/wb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/wb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/osvvm/bfm/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/bb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/bb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/bb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/bb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/bb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/osvvm/bfm/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/tl/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/tl/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/tl/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/tl/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/tl/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/osvvm/bfm/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/wb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/wb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/wb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/wb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/wb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/osvvm/soc/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/bb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/bb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/bb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/bb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/bb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/osvvm/soc/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/tl/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/tl/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/tl/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/tl/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/tl/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/osvvm/soc/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/wb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/wb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/wb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/wb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/wb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/types/bfm/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/bb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/bb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/bb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/bb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/bb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/types/bfm/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/tl/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/tl/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/tl/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/tl/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/tl/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/types/bfm/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/wb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/wb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/wb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/wb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/wb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/types/soc/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/bb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/bb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/bb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/bb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/bb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/types/soc/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/tl/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/tl/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/tl/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/tl/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/tl/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/vhdl/validation/types/soc/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/wb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/wb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/wb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/wb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/wb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /lifecycle/devops/assets/chapter4/hardware-4004-verification.dot: -------------------------------------------------------------------------------- 1 | digraph Project { 2 | // Introduction 3 | graph [rankdir = LR, splines=ortho]; 4 | node[shape=record]; 5 | 6 | // Blocks 7 | subgraph "cluster TestBench" { label = "TestBench"; 8 | Stimulus[shape=box, label="Stimulus"]; 9 | Model[shape=box, label="Model (4004)"]; 10 | DUT[shape=box, label="DUT (4004)"]; 11 | Asserts[shape=box, label="Asserts"]; 12 | } 13 | 14 | // Sequence 15 | Stimulus -> Model; 16 | Stimulus -> DUT; 17 | Model -> Asserts; 18 | DUT -> Asserts; 19 | } 20 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/bfm/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/bb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/bb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/bb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/bb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/bb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/bfm/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/tl/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/tl/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/tl/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/tl/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/tl/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/bfm/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/wb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/bfm/wb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/wb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/wb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/bfm/wb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/soc/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/bb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/bb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/bb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/bb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/bb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/soc/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/tl/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/tl/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/tl/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/tl/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/tl/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/soc/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/wb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/soc/wb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/wb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/wb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/soc/wb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/bfm/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/bb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/bb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/bb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/bb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/bb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/bfm/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/tl/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/tl/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/tl/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/tl/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/tl/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/bfm/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/wb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/bfm/wb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/wb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/wb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/bfm/wb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/soc/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/bb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/bb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/bb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/bb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/bb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/soc/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/tl/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/tl/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/tl/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/tl/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/tl/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/soc/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/wb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/soc/wb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/wb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/wb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/soc/wb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /lifecycle/devops/assets/chapter4/hardware-msp430-verification.dot: -------------------------------------------------------------------------------- 1 | digraph Project { 2 | // Introduction 3 | graph [rankdir = LR, splines=ortho]; 4 | node[shape=record]; 5 | 6 | // Blocks 7 | subgraph "cluster TestBench" { label = "TestBench"; 8 | Stimulus[shape=box, label="Stimulus"]; 9 | Model[shape=box, label="Model (MSP430)"]; 10 | DUT[shape=box, label="DUT (MSP430)"]; 11 | Asserts[shape=box, label="Asserts"]; 12 | } 13 | 14 | // Sequence 15 | Stimulus -> Model; 16 | Stimulus -> DUT; 17 | Model -> Asserts; 18 | DUT -> Asserts; 19 | } 20 | -------------------------------------------------------------------------------- /lifecycle/devops/assets/chapter4/hardware-riscv-verification.dot: -------------------------------------------------------------------------------- 1 | digraph Project { 2 | // Introduction 3 | graph [rankdir = LR, splines=ortho]; 4 | node[shape=record]; 5 | 6 | // Blocks 7 | subgraph "cluster TestBench" { label = "TestBench"; 8 | Stimulus[shape=box, label="Stimulus"]; 9 | Model[shape=box, label="Model (RISC-V)"]; 10 | DUT[shape=box, label="DUT (RISC-V)"]; 11 | Asserts[shape=box, label="Asserts"]; 12 | } 13 | 14 | // Sequence 15 | Stimulus -> Model; 16 | Stimulus -> DUT; 17 | Model -> Asserts; 18 | DUT -> Asserts; 19 | } 20 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/core/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/core/bb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/core/bb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/core/bb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/core/bb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/core/bb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/core/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/core/tl/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/core/tl/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/core/tl/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/core/tl/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/core/tl/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/core/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/core/wb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/core/wb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/core/wb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/core/wb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/core/wb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/pu/ahb4/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/ahb4/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/ahb4/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/ahb4/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/ahb4/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/ahb4/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/pu/apb4/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/apb4/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/apb4/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/apb4/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/apb4/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/apb4/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/osvvm/pu/axi4/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/axi4/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/application/pu/axi4/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/axi4/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/axi4/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/osvvm/library/pu/axi4/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/core/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/core/bb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/core/bb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/core/bb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/core/bb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/core/bb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/core/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/core/tl/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/core/tl/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/core/tl/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/core/tl/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/core/tl/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/core/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/core/wb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/core/wb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/core/wb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/core/wb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/core/wb/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/pu/ahb4/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/ahb4/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/ahb4/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/ahb4/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/ahb4/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/ahb4/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/pu/apb4/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/apb4/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/apb4/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/apb4/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/apb4/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/apb4/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/validation/types/pu/axi4/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/axi4/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../validation/types/application/pu/axi4/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/axi4/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/axi4/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../validation/types/library/pu/axi4/peripheral_types_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/verification/osvvm/pu/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/application/pu/bb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/application/pu/bb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/library/pu/bb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/library/pu/bb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/library/pu/bb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/verification/osvvm/pu/tl/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/application/pu/tl/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/application/pu/tl/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/library/pu/tl/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/library/pu/tl/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/library/pu/tl/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/verification/osvvm/pu/wb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/application/pu/wb/peripheral_osvvm_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/application/pu/wb/peripheral_osvvm_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/library/pu/wb/peripheral_osvvm_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/library/pu/wb/peripheral_osvvm_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../verification/osvvm/library/pu/wb/peripheral_osvvm_testbench.vhd 6 | -------------------------------------------------------------------------------- /sim/verilog/verification/types/pu/bb/ghdl/system.g: -------------------------------------------------------------------------------- 1 | ghdl -a --std=08 ../../../../../../../../verification/types/application/pu/bb/peripheral_types_design.vhd 2 | ghdl -a --std=08 ../../../../../../../../verification/types/application/pu/bb/peripheral_types_design_pkg.vhd 3 | ghdl -a --std=08 ../../../../../../../../verification/types/library/pu/bb/peripheral_types_model.vhd 4 | ghdl -a --std=08 ../../../../../../../../verification/types/library/pu/bb/peripheral_types_model_pkg.vhd 5 | ghdl -a --std=08 ../../../../../../../../verification/types/library/pu/bb/peripheral_types_testbench.vhd 6 | --------------------------------------------------------------------------------