├── .github ├── actions │ └── setupenv │ │ └── action.yml ├── pages │ └── index.html ├── scripts │ ├── Find_Tests.sh │ └── Group_Tests.py └── workflows │ ├── _make_boot.yml │ ├── _make_zpkg.yml │ ├── _release.yml │ ├── _test_hdl.yml │ ├── _test_matrix.yml │ ├── _test_python_autogen.yml │ ├── code.yml │ └── docs.yml ├── .gitignore ├── CHANGELOG.rst ├── CONFIG.example ├── CONTRIBUTING.rst ├── LICENSE ├── Makefile ├── README.rst ├── apps ├── PandABox-fmc_24vio.app.ini ├── PandABox-fmc_acq427.app.ini ├── PandABox-fmc_acq430.app.ini ├── PandABox-fmc_lback-sfp_lback.app.ini ├── PandABox-no-fmc-sfp2_udpontrig.app.ini ├── PandABox-no-fmc-sfp3_dls_eventr.app.ini ├── PandABox-no-fmc.app.ini ├── PandABrick.app.ini ├── ZedBoard-no-fmc.app.ini ├── xu5_st1-fmc_acq430.app.ini ├── xu5_st1-fmc_x4sfp.app.ini └── xu5_st1-no-fmc.app.ini ├── check-whitespace ├── common ├── __init__.py ├── fpga.make ├── hdl │ ├── axi_lite_slave.vhd │ ├── axi_read_master.vhd │ ├── bitmux.vhd │ ├── clock2_phase.vhd │ ├── defines │ │ ├── interface_types.vhd │ │ ├── operator.vhd │ │ ├── picxo_pkg.vhd │ │ ├── support.vhd │ │ └── top_defines.vhd │ ├── delay_filter.vhd │ ├── delay_line.vhd │ ├── encoders │ │ ├── absenc.vhd │ │ ├── biss_clock_gen.vhd │ │ ├── biss_crc.vhd │ │ ├── biss_master.vhd │ │ ├── biss_slave.vhd │ │ ├── biss_sniffer.vhd │ │ ├── encoders.vhd │ │ ├── encoders_block.vhd │ │ ├── encoders_top.vhd │ │ ├── incenc.vhd │ │ ├── pmacenc.vhd │ │ ├── ssi_error_detect.vhd │ │ ├── ssi_master.vhd │ │ ├── ssi_slave.vhd │ │ └── ssi_sniffer.vhd │ ├── finedelay.vhd │ ├── freq_counter.vhd │ ├── iobuf_registered.vhd │ ├── latched_sync.vhd │ ├── mmcm_clkmux.vhd │ ├── pll_autoreset.vhd │ ├── posmux.vhd │ ├── prescaler.vhd │ ├── prescaler_pos.vhd │ ├── pulse2pulse.vhd │ ├── qdec.vhd │ ├── qdecoder.vhd │ ├── qenc.vhd │ ├── qencoder.vhd │ ├── reg.vhd │ ├── reg_top.vhd │ ├── serial_engine.vhd │ ├── serial_engine_rx.vhd │ ├── serial_engine_tx.vhd │ ├── serial_link_detect.vhd │ ├── shifter_in.vhd │ ├── spbram.vhd │ ├── ssi_clock_gen.vhd │ ├── sync_bit.vhd │ ├── table_read_engine.vhd │ └── ts_mux.vhd ├── hdl_zynq │ └── IDDR_sync_bit.vhd ├── hdl_zynqmp │ └── IDDR_sync_bit.vhd ├── python │ ├── __init__.py │ ├── compat.py │ ├── configs.py │ ├── copy_file_in_modules.py │ ├── generate_app.py │ ├── generate_constants.py │ ├── generate_hdl_timing.py │ ├── ini_util.py │ ├── make_extensions.py │ ├── parse_git_version.py │ ├── simulations.py │ ├── sphinx_block_fields_directive.py │ ├── sphinx_timing_directive.py │ └── timing_plot.py ├── scripts │ ├── build_boot.tcl │ ├── build_ip.tcl │ ├── build_ip_proj.tcl │ ├── build_ps.tcl │ ├── build_top.tcl │ ├── make_bif_zynq.sh │ └── make_bif_zynqmp.sh └── templates │ ├── addr_defines.vhd.jinja2 │ ├── block_ctrl.vhd.jinja2 │ ├── block_wrapper.vhd.jinja2 │ ├── config.jinja2 │ ├── constraints.tcl.jinja2 │ ├── default_ipmi.ini │ ├── descriptions.jinja2 │ ├── dma_hdl_timing_extra │ ├── hdl_timing.sv.jinja2 │ ├── ip.make.jinja2 │ ├── module.tcl.jinja2 │ ├── pcap_hdl_timing.sv.jinja2 │ ├── reg_defines.vhd.jinja2 │ ├── registers.jinja2 │ ├── registers_server │ ├── sim_server.jinja2 │ ├── soft_blocks.vhd.jinja2 │ └── top_defines_gen.vhd.jinja2 ├── docs ├── PandA-logo-for-black-background.svg ├── PandA-logo.ico ├── __init__.py ├── _static │ └── theme_overrides.css ├── _templates │ └── layout.html ├── blocks.rst ├── conf.py ├── fpga_arch.png ├── index.html ├── index.rst ├── reference │ ├── app.rst │ ├── block.rst │ ├── build_arch.png │ ├── changelog.rst │ ├── contributing.rst │ ├── framework.rst │ ├── glossary.rst │ └── testing.rst ├── requirements.txt └── tutorials │ ├── template_tutorial1_leds.json │ ├── template_tutorial2_pcap.json │ ├── tutorial1_bits.png │ ├── tutorial1_blinking_leds.rst │ ├── tutorial1_layout.png │ ├── tutorial1_pulse.png │ ├── tutorial2.timing.ini │ ├── tutorial2_layout.png │ ├── tutorial2_pcap.png │ ├── tutorial2_position_capture.rst │ ├── tutorial2_positions.png │ ├── tutorial3_position_compare.rst │ └── tutorial4_snake_scan.rst ├── etc ├── check_ipmi ├── i2c │ ├── __init__.py │ ├── create_ipmi.py │ ├── eeprom.py │ ├── ini_file.py │ ├── parse_ipmi.py │ └── smbus2.py ├── panda-fpga.docs.html ├── show_ipmi └── write_eeprom ├── includes ├── common_soft_blocks.include.ini └── pandabrick_soft_blocks.include.ini ├── ip_defs ├── PICXO_FRACXO.tcl ├── eth_mac.tcl ├── eth_phy.tcl ├── event_receiver_mgt.tcl ├── fifo_1K32.tcl ├── fifo_1K32_ft.tcl ├── fmc_acq427_dac_fifo.tcl ├── fmc_acq430_ch_fifo.tcl ├── fmc_acq430_sample_ram.tcl ├── ila_0.tcl ├── ila_32x8K.tcl ├── picxo_ila.tcl ├── picxo_vio.tcl ├── pulse_queue.tcl ├── sfp_panda_sync.tcl ├── sfp_panda_sync_us.tcl ├── sfp_transmit_mem.tcl ├── sfpgtx.tcl └── system_cmd_fifo.tcl ├── modules ├── absenc │ ├── absenc.block.ini │ ├── absenc_doc.rst │ └── hdl ├── bits │ ├── bits.block.ini │ ├── bits.timing.ini │ ├── bits_doc.rst │ ├── bits_sim.py │ └── hdl │ │ └── bits.vhd ├── calc │ ├── calc.block.ini │ ├── calc.timing.ini │ ├── calc_doc.rst │ ├── calc_sim.py │ └── hdl │ │ └── calc.vhd ├── clock │ ├── clock.block.ini │ ├── clock.timing.ini │ ├── clock_doc.rst │ ├── clock_sim.py │ └── hdl │ │ └── clock.vhd ├── counter │ ├── counter.block.ini │ ├── counter_doc.rst │ ├── counter_documentation.timing.ini │ ├── counter_functionality.timing.ini │ ├── counter_sim.py │ └── hdl │ │ └── counter.vhd ├── div │ ├── div.block.ini │ ├── div.timing.ini │ ├── div_doc.rst │ ├── div_sim.py │ └── hdl │ │ └── div.vhd ├── filter │ ├── filter.block.ini │ ├── filter_doc.rst │ ├── filter_documentation.timing.ini │ ├── filter_functionality.timing.ini │ ├── filter_sim.py │ └── hdl │ │ ├── divider.vhd │ │ └── filter.vhd ├── fmc_24vio │ ├── const │ │ └── fmc_24vio_impl.xdc │ ├── fmc_24v_doc.rst │ ├── fmc_24vio.block.ini │ ├── hdl │ │ ├── fmc_24vio.vhd │ │ ├── fmc_24vio_wrapper.vhd │ │ ├── max14900_ctrl.vhd │ │ └── max14900_sclk_gen.vhd │ ├── ipmi.ini │ └── ipmi_definition.ini ├── fmc_acq427 │ ├── const │ │ ├── fmc_adc427.xdc │ │ ├── fmc_dac427.xdc │ │ └── fmc_dac427_impl.xdc │ ├── extensions │ │ └── fmc_acq427.py │ ├── fmc_acq427.block.ini │ ├── fmc_acq427_doc.rst │ ├── hdl │ │ ├── fmc_acq427_wrapper.vhd │ │ ├── fmc_adc_interface.vhd │ │ ├── fmc_adc_spi.vhd │ │ ├── fmc_adc_start.vhd │ │ ├── fmc_dac_interface.vhd │ │ ├── fmc_dac_spi.vhd │ │ ├── fmc_dac_start.vhd │ │ └── fmc_types.vhd │ └── ipmi.ini ├── fmc_acq430 │ ├── const │ │ ├── fmc_acq430.xdc │ │ └── fmc_acq430_impl.xdc │ ├── fmc_acq430.block.ini │ ├── fmc_acq430_doc.rst │ ├── hdl │ │ ├── fmc_acq430_wrapper.vhd │ │ ├── fmc_adc430_start.vhd │ │ ├── fmc_func.vhd │ │ ├── fmc_interface.vhd │ │ ├── fmc_spi.vhd │ │ └── fmc_types.vhd │ ├── hdl_zynq │ │ └── enablable_clock_oddr.vhd │ ├── hdl_zynqmp │ │ └── enablable_clock_oddr.vhd │ └── ipmi.ini ├── fmc_loopback │ ├── const │ │ ├── fmc_loopback.xdc │ │ └── fmc_loopback_impl.xdc │ ├── fmc_loopback.block.ini │ ├── fmc_loopback_doc.rst │ ├── hdl │ │ └── fmc_loopback_wrapper.vhd │ └── ipmi.ini ├── fmc_x4sfp │ ├── const │ │ ├── fmc_x4sfp.xdc │ │ └── fmc_x4sfp_impl.xdc │ ├── fmc_x4sfp.block.ini │ └── hdl │ │ └── fmc_x4sfp_wrapper.vhd ├── incenc │ ├── hdl │ ├── incenc.block.ini │ └── incenc_doc.rst ├── inenc │ ├── hdl │ ├── inenc.block.ini │ └── inenc_doc.rst ├── lut │ ├── hdl │ │ └── lut.vhd │ ├── lut.block.ini │ ├── lut.timing.ini │ ├── lut_doc.rst │ └── lut_sim.py ├── lvdsin │ ├── hdl │ │ └── lvdsin_top.vhd │ ├── lvdsin.block.ini │ └── lvdsin_doc.rst ├── lvdsout │ ├── hdl │ │ ├── lvdsout_block.vhd │ │ └── lvdsout_top.vhd │ ├── lvdsout.block.ini │ └── lvdsout_doc.rst ├── outenc │ ├── hdl │ ├── outenc.block.ini │ └── outenc_doc.rst ├── pandabrick_test │ ├── hdl │ │ └── test_regs.vhd │ └── pandabrick_test.block.ini ├── pcap │ ├── hdl │ │ ├── axi_write_master.vhd │ │ ├── pcap_arming.vhd │ │ ├── pcap_buffer.vhd │ │ ├── pcap_bus_delay.vhd │ │ ├── pcap_core.vhd │ │ ├── pcap_core_ctrl.vhd │ │ ├── pcap_core_wrapper.vhd │ │ ├── pcap_dma.vhd │ │ ├── pcap_frame.vhd │ │ ├── pcap_frame_mode.vhd │ │ └── pcap_top.vhd │ ├── pcap.block.ini │ ├── pcap_doc.rst │ ├── pcap_documentation.timing.ini │ ├── pcap_functionality.timing.ini │ └── pcap_sim.py ├── pcomp │ ├── hdl │ │ └── pcomp.vhd │ ├── pcomp.block.ini │ ├── pcomp.timing.ini │ ├── pcomp_doc.rst │ └── pcomp_sim.py ├── pgen │ ├── PGEN_1000.txt │ ├── hdl │ │ └── pgen.vhd │ ├── pgen.block.ini │ ├── pgen.timing.ini │ ├── pgen_doc.rst │ └── pgen_sim.py ├── pmacenc │ ├── hdl │ ├── pmacenc.block.ini │ └── pmacenc_doc.rst ├── posenc │ ├── hdl │ │ └── posenc.vhd │ ├── posenc.block.ini │ ├── posenc_doc.rst │ ├── posenc_documentation.timing.ini │ ├── posenc_functionality.timing.ini │ └── posenc_sim.py ├── pulse │ ├── hdl │ │ └── pulse.vhd │ ├── pulse.block.ini │ ├── pulse.timing.ini │ ├── pulse_doc.rst │ └── pulse_sim.py ├── qdec │ ├── hdl │ │ └── README.txt │ ├── qdec.block.ini │ ├── qdec_doc.rst │ ├── qdec_documentation.timing.ini │ ├── qdec_functionality.timing.ini │ └── qdec_sim.py ├── seq │ ├── hdl │ │ ├── seq.vhd │ │ ├── sequencer_defines.vhd │ │ ├── sequencer_double_table.vhd │ │ ├── sequencer_prescaler.vhd │ │ └── sequencer_table.vhd │ ├── seq.block.ini │ ├── seq_doc.rst │ ├── seq_documentation.timing.ini │ ├── seq_double_table_documentation.timing.ini │ ├── seq_double_table_functionality.timing.ini │ ├── seq_functionality.timing.ini │ └── seq_sim.py ├── sfp_eventr │ ├── const │ │ └── sfp_event_receiver_impl.xdc │ ├── hdl │ │ ├── sfp_dls_eventr_wrapper.vhd │ │ ├── sfp_event_receiver.vhd │ │ ├── sfp_receiver.vhd │ │ └── sfp_transmitter.vhd │ ├── sfp_dls_eventr.block.ini │ └── sfp_dls_eventr_doc.rst ├── sfp_loopback │ ├── const │ │ └── sfp_loopback_impl.xdc │ ├── hdl │ │ ├── gt_rom_init_rx.dat │ │ ├── gt_rom_init_tx.dat │ │ ├── sfp_loopback_wrapper.vhd │ │ ├── sfpgtx_common.vhd │ │ ├── sfpgtx_common_reset.vhd │ │ ├── sfpgtx_exdes.vhd │ │ ├── sfpgtx_gt_frame_check.vhd │ │ ├── sfpgtx_gt_frame_gen.vhd │ │ ├── sfpgtx_gt_usrclk_source.vhd │ │ └── sfpgtx_support.vhd │ ├── sfp_loopback.block.ini │ └── sfp_loopback_doc.rst ├── sfp_panda_sync │ ├── const │ │ ├── zynq │ │ │ └── sfp_panda_sync_impl.xdc │ │ └── zynqmp │ │ │ └── sfp_panda_sync_impl.xdc │ ├── hdl │ │ ├── sfp_panda_sync_receiver.vhd │ │ ├── sfp_panda_sync_transmit.vhd │ │ ├── sfp_panda_sync_wrapper.vhd │ │ └── sim │ │ │ ├── pandaSync_rx_TB.vhd │ │ │ ├── pandaSync_tx_TB.vhd │ │ │ ├── run_xsim_rx.sh │ │ │ ├── run_xsim_tx.sh │ │ │ └── xsim.tcl │ ├── hdl_zynq │ │ └── sfp_panda_sync_mgt_interface.vhd │ ├── hdl_zynqmp │ │ └── sfp_panda_sync_mgt_interface.vhd │ ├── sfp_panda_sync.block.ini │ ├── sfp_panda_sync_doc.rst │ └── sfp_panda_sync_us.block.ini ├── sfp_udpontrig │ ├── const │ │ └── sfp_udpontrig_impl.xdc │ ├── hdl │ │ ├── common │ │ │ ├── arp_types.vhd │ │ │ ├── axi_types.vhd │ │ │ ├── icmp_types.vhd │ │ │ ├── ipv4_channels_types.vhd │ │ │ └── ipv4_types.vhd │ │ ├── ip_layer │ │ │ ├── arp │ │ │ │ ├── arp.vhd │ │ │ │ ├── arp_layer_component_pkg.vhd │ │ │ │ ├── arp_req.vhd │ │ │ │ ├── arp_rx.vhd │ │ │ │ ├── arp_store_br.vhd │ │ │ │ ├── arp_sync.vhd │ │ │ │ ├── arp_tx.vhd │ │ │ │ └── arp_v2.vhd │ │ │ ├── ip_complete_nomac.vhd │ │ │ ├── ip_layer_component_pkg.vhd │ │ │ ├── ip_tx_arbitrator.vhd │ │ │ ├── ipv4 │ │ │ │ ├── ipv4.vhd │ │ │ │ ├── ipv4_rx.vhd │ │ │ │ └── ipv4_tx.vhd │ │ │ └── mac_tx_arbitrator.vhd │ │ ├── phy_layer │ │ │ ├── example_design_eth_phy │ │ │ │ ├── gig_ethernet_pcs_pma_0_example_design.vhd │ │ │ │ ├── gig_ethernet_pcs_pma_0_reset_sync_ex.vhd │ │ │ │ ├── gig_ethernet_pcs_pma_0_sync_block_ex.vhd │ │ │ │ ├── gig_ethernet_pcs_pma_0_tx_elastic_buffer.vhd │ │ │ │ └── support │ │ │ │ │ ├── gig_ethernet_pcs_pma_0_clocking.vhd │ │ │ │ │ ├── gig_ethernet_pcs_pma_0_gt_common.vhd │ │ │ │ │ ├── gig_ethernet_pcs_pma_0_resets.vhd │ │ │ │ │ └── gig_ethernet_pcs_pma_0_support.vhd │ │ │ └── trimac_fifo_bloc │ │ │ │ ├── common │ │ │ │ ├── tri_mode_ethernet_mac_0_reset_sync.vhd │ │ │ │ └── tri_mode_ethernet_mac_0_sync_block.vhd │ │ │ │ ├── fifo │ │ │ │ ├── tri_mode_ethernet_mac_0_bram_tdp.vhd │ │ │ │ ├── tri_mode_ethernet_mac_0_rx_client_fifo.vhd │ │ │ │ ├── tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.vhd │ │ │ │ └── tri_mode_ethernet_mac_0_tx_client_fifo.vhd │ │ │ │ └── tri_mode_ethernet_mac_0_fifo_block.vhd │ │ ├── sfp_udp_complete.vhd │ │ ├── sfp_udp_component_pkg.vhd │ │ ├── sfp_udpontrig_wrapper.vhd │ │ └── udp_layer │ │ │ ├── udp_complete_ping_nomac.vhd │ │ │ ├── udp_layer_component_pkg.vhd │ │ │ ├── udp_ping.vhd │ │ │ ├── udp_rx.vhd │ │ │ └── udp_tx.vhd │ ├── sfp_udpontrig.block.ini │ └── sfp_udpontrig_doc.rst ├── srgate │ ├── hdl │ │ └── srgate.vhd │ ├── srgate.block.ini │ ├── srgate.timing.ini │ ├── srgate_doc.rst │ └── srgate_sim.py ├── system │ ├── extensions │ │ └── system.py │ ├── hdl │ │ ├── led_management.vhd │ │ ├── system_interface.vhd │ │ ├── system_registers.vhd │ │ └── system_top.vhd │ ├── system.block.ini │ └── system_doc.rst ├── ttlin │ ├── hdl │ │ ├── ttlin_block.vhd │ │ └── ttlin_top.vhd │ ├── ttlin.block.ini │ └── ttlin_doc.rst ├── ttlout │ ├── hdl │ │ ├── ttlout_block.vhd │ │ └── ttlout_top.vhd │ ├── ttlout.block.ini │ └── ttlout_doc.rst ├── us_system │ ├── extensions │ │ └── us_system.py │ ├── hdl │ │ └── us_system_top.vhd │ └── us_system.block.ini └── zedboard_demo │ ├── hdl │ └── zedboard_demo_top.vhd │ └── zedboard_demo.block.ini ├── old ├── Makefile ├── __init__.py ├── common │ ├── __init__.py │ ├── python │ │ ├── __init__.py │ │ ├── capture │ │ │ ├── __init__.py │ │ │ └── capture.py │ │ ├── fpga_vector_generator.py │ │ ├── pandablocks │ │ │ ├── __init__.py │ │ │ ├── block.py │ │ │ └── configparser │ │ │ │ └── configblock.py │ │ ├── sphinxext │ │ │ └── __init__.py │ │ ├── vhdl_generator.py │ │ └── vhdl_templates │ │ │ ├── addr_defines_template │ │ │ ├── panda_bitbus_template │ │ │ ├── panda_block_ctrl_template │ │ │ └── panda_buses_template │ └── vhdl │ │ ├── soft_blocks.vhd │ │ ├── syncdata.vhd │ │ ├── syncff.vhd │ │ ├── templates │ │ ├── FB_block.vhd │ │ ├── FB_top.vhd │ │ ├── fmc_top.vhd │ │ └── sfp_top.vhd │ │ └── top.vhd ├── docs │ ├── Manuals │ │ ├── FPGA-Development-Kit.docx │ │ └── FPGA-Development-Kit.pdf │ ├── conf.py │ ├── configparser.rst │ ├── fixed_exposure_gate_trigger.png │ ├── fpga_testing.rst │ ├── index.rst │ ├── toc.rst │ └── triggering.rst └── tests │ ├── fpga_tests │ ├── I18.test │ ├── adc.test │ ├── biss-daisy │ ├── biss-pcomp │ ├── biss-snake │ ├── counter │ ├── div │ ├── i08-setup │ ├── parser.m │ ├── pcap.m │ ├── pcomp │ ├── pos-capture │ ├── pulse │ ├── quad-snake │ ├── readme │ ├── seq │ ├── table │ └── test_table.py │ ├── sim │ ├── panda_biss │ │ ├── bench │ │ │ ├── biss_master_slave_tb.tcl │ │ │ ├── biss_master_slave_tb.vhd │ │ │ ├── biss_result.v │ │ │ ├── biss_sniffer_tb.v │ │ │ └── glbl.v │ │ └── do │ │ │ ├── biss0.prn │ │ │ ├── biss2.prn │ │ │ └── ila.csv │ ├── panda_inenc │ │ └── bench │ │ │ ├── inenc_tb_compile.tcl │ │ │ └── inenc_top_tb.vhd │ ├── panda_outenc │ │ └── bench │ │ │ └── outenc_tb.v │ ├── panda_slowctrl │ │ └── bench │ │ │ ├── glbl.v │ │ │ └── panda_slowctrl_tb.v │ ├── panda_ssi │ │ └── bench │ │ │ └── panda_ssi_tb.vhd │ ├── panda_status │ │ └── bench │ │ │ └── panda_status_tb.vhd │ └── regression_tests.tcl │ ├── system_tests │ ├── system_tests.py │ └── testseq │ └── test_zebra2 │ └── test_simulation │ ├── test_block.py │ └── test_controller.py ├── targets ├── PandABox │ ├── PandABox.target.ini │ ├── bd │ │ └── panda_ps.tcl │ ├── const │ │ ├── FMC_MGT1_pins.xdc │ │ ├── PandABox-clks_impl.xdc │ │ ├── PandABox-freq.xdc │ │ ├── PandABox-pins_impl.xdc │ │ ├── SFP1_pins.xdc │ │ ├── SFP2_pins.xdc │ │ └── SFP3_pins.xdc │ ├── etc │ │ ├── load-panda-firmware │ │ ├── panda-fpga.list │ │ └── target-defs │ ├── hdl │ │ ├── PandABox_top.vhd │ │ └── slow_defines.vhd │ ├── platform_incl.make │ ├── target-top.dts │ └── target_incl.tcl ├── PandABrick │ ├── PandABrick.target.ini │ ├── bd │ │ └── panda_ps.tcl │ ├── const │ │ ├── PandABrick-clks.xdc │ │ ├── PandABrick-pins_impl.xdc │ │ └── SFP1_pins.xdc │ ├── etc │ │ ├── atsha240a-gen.py │ │ ├── load-panda-firmware │ │ ├── panda-fpga.list │ │ └── target-defs │ ├── hdl │ │ ├── Adaptor_PIC_SPI.v │ │ ├── PandABrick_encoders.vhd │ │ ├── PandABrick_encoders_block.vhd │ │ ├── PandABrick_encoders_top.vhd │ │ ├── PandABrick_top.vhd │ │ └── sim │ │ │ ├── Adaptor_PIC_SPI_tb.vhd │ │ │ ├── run_xsim.sh │ │ │ └── xsim.tcl │ ├── platform_incl.make │ ├── target-top.dts │ └── target_incl.tcl ├── ZedBoard │ ├── ZedBoard.target.ini │ ├── bd │ │ └── panda_ps.tcl │ ├── const │ │ └── ZedBoard-pins_impl.xdc │ ├── etc │ │ ├── load-panda-firmware │ │ ├── panda-fpga.list │ │ └── target-defs │ ├── hdl │ │ └── ZedBoard_top.vhd │ ├── platform_incl.make │ ├── target-top.dts │ └── target_incl.tcl └── xu5_st1 │ ├── bd │ └── panda_ps.tcl │ ├── const │ ├── FMC_MGT1_pins.xdc │ ├── FMC_MGT2_pins.xdc │ ├── FMC_MGT3_pins.xdc │ ├── FMC_MGT4_pins.xdc │ ├── xu5_st1-clks.xdc │ └── xu5_st1-pins_impl.xdc │ ├── etc │ ├── load-panda-firmware │ ├── panda-fpga.list │ └── target-defs │ ├── hdl │ └── xu5_st1_top.vhd │ ├── platform_incl.make │ ├── target-top.dts │ ├── target_incl.tcl │ └── xu5_st1.target.ini └── tests ├── __init__.py ├── hdl ├── regression_tests.tcl └── single_test.tcl ├── python ├── __init__.py ├── build │ └── etc │ │ └── panda-fpga.list ├── test_block_simulation.py ├── test_calc_extensions.py ├── test_configs.py ├── test_data │ ├── app-expected │ │ ├── config_d │ │ │ ├── config │ │ │ ├── description │ │ │ └── registers │ │ ├── hdl │ │ │ ├── addr_defines.vhd │ │ │ ├── lut_ctrl.vhd │ │ │ ├── lut_wrapper.vhd │ │ │ └── soft_blocks.vhd │ │ └── usage.txt │ ├── test.app.ini │ ├── test.block.ini │ ├── test.timing.ini │ └── timing-expected │ │ ├── testblock.tcl │ │ ├── timing001 │ │ ├── 1testblockexpected.csv │ │ └── hdl_timing.sv │ │ └── timing002 │ │ ├── 2testblockexpected.csv │ │ └── hdl_timing.sv ├── test_data_calc_extensions │ ├── app-expected │ │ ├── config_d │ │ │ ├── config │ │ │ ├── description │ │ │ └── registers │ │ └── hdl │ │ │ ├── addr_defines.vhd │ │ │ ├── dummy_ctrl.vhd │ │ │ ├── fmc_acq427_ctrl.vhd │ │ │ └── interval_ctrl.vhd │ ├── calc_extension.app.ini │ ├── dummy │ │ └── dummy.block.ini │ ├── fmc_acq427 │ │ └── fmc_acq427.block.ini │ └── interval │ │ └── interval.block.ini ├── test_generate_app.py ├── test_generate_timing.py └── test_parse_git_version.py ├── requirements.txt ├── sim ├── finedelay │ └── bench │ │ ├── finedelay_tb.vhd │ │ └── finedelay_tb_compile.tcl ├── sequencer_double_table │ └── bench │ │ ├── sequencer_double_table_tb.vhd │ │ ├── sequencer_double_table_tb_compile.tcl │ │ └── top_defines_gen.vhd └── sfp_receiver │ ├── bench │ ├── sfp_tb_compile.tcl │ └── sfp_top_tb.vhd │ └── mem │ ├── dbus_event_tb.v │ └── event_receiver_mem.coe └── test_python_sim_timing.py /.github/actions/setupenv/action.yml: -------------------------------------------------------------------------------- 1 | name: "Perform Repetitive Tasks" 2 | description: "Composite action that checks out repos, and adjusts directory permissions for runner" 3 | 4 | runs: 5 | using: "composite" 6 | steps: 7 | - name: Checkout PandABlocks-rootfs 8 | uses: actions/checkout@v4 9 | with: 10 | repository: PandABlocks/PandABlocks-rootfs 11 | path: repos/PandABlocks-rootfs 12 | fetch-depth: 0 13 | 14 | - name: Give runner build perms, and adjust repos config path 15 | shell: bash 16 | run: | 17 | sudo mkdir /build 18 | sudo chmod -R 777 /build -------------------------------------------------------------------------------- /.github/pages/index.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | Redirecting to master branch 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /.github/scripts/Find_Tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Modules path 4 | search_dir=$1 5 | work_dir=$2 6 | 7 | # Find files matching timing name pattern 8 | found_files=$(find "$search_dir" -type f -name "*.timing.ini") 9 | echo $found_files 10 | # Array of modules and their test count 11 | module_grps=() 12 | 13 | # Check if any files were found 14 | if [ -z "$found_files" ]; then 15 | echo "No timing tests found" 16 | else 17 | # Loop through each found file 18 | for file in $found_files; do 19 | # Count occurrences of [*] in the file 20 | # Min 5 char to filter descriptions and index 21 | count=$(grep -o '\[[^][]\{5,\}\]' "$file" | wc -l) 22 | # Duplicate names allowed for multiple test files in same module subdirectory 23 | module_name=$(basename "$(dirname "$file")") 24 | module_grps+=("$module_name" "$count") 25 | done 26 | # Run python script to define job matrix based on found tests 27 | python3 $work_dir/Group_Tests.py "${module_grps[@]}" 28 | fi -------------------------------------------------------------------------------- /.github/scripts/Group_Tests.py: -------------------------------------------------------------------------------- 1 | import sys 2 | import json 3 | 4 | modules_grps = (sys.argv)[1:] 5 | print(modules_grps) 6 | modules = [] 7 | num_jobs = 5 8 | 9 | 10 | # Allocate modules to jobs with lowest load 11 | def split_modules(modules, num_jobs): 12 | modules.sort(key=lambda x: x[1], reverse=True) 13 | jobs = [[] for _ in range(num_jobs)] 14 | for module, count in modules: 15 | min_sum_job_idx = min( 16 | range(num_jobs), key=lambda i: sum(subset[1] for subset in jobs[i]) 17 | ) 18 | jobs[min_sum_job_idx].append([module, count]) 19 | return jobs 20 | 21 | 22 | # Produce matrix in format expected by 'make hdl_test' job step 23 | def generate_matrix(jobs): 24 | matrix = {"modules": []} 25 | for job in jobs: 26 | job_include = " ".join(module[0] for module in job) 27 | matrix["modules"].append(job_include) 28 | return matrix 29 | 30 | 31 | # Convert bash array to sensible py array 32 | for i in range(0, len(modules_grps) - 1, 2): 33 | # If duplicate module names are found, add their counts 34 | if modules and modules_grps[i] == modules_grps[i - 2]: 35 | modules[-1][1] += int(modules_grps[i + 1]) 36 | # If no duplicate present, append new element 37 | else: 38 | modules.append([modules_grps[i], int(modules_grps[i + 1])]) 39 | print(modules) 40 | 41 | # Produce JSON file to pass to GH job 42 | with open("github_tests.json", "w") as matrix_file: 43 | json.dump(generate_matrix(split_modules(modules, num_jobs)), matrix_file) 44 | -------------------------------------------------------------------------------- /.github/workflows/_make_boot.yml: -------------------------------------------------------------------------------- 1 | on: 2 | workflow_call: 3 | 4 | jobs: 5 | make_boot: 6 | strategy: 7 | fail-fast: false 8 | matrix: 9 | include: 10 | - platform: zynq 11 | app: PandABox-no-fmc 12 | - platform: zynqmp 13 | app: xu5_st1-no-fmc 14 | - platform: zynqmp 15 | app: PandABrick 16 | runs-on: 17 | group: iris_runners 18 | container: 19 | image: ghcr.io/pandablocks/pandablocks-ci-container:latest 20 | options: --privileged 21 | 22 | steps: 23 | # Necessary to find action.yml 24 | - name: Checkout Source 25 | uses: actions/checkout@v4 26 | with: 27 | path: repos/PandABlocks-fpga 28 | fetch-depth: 0 29 | 30 | - name: Checkout rootfs and Give Directory Perms 31 | uses: ./repos/PandABlocks-fpga/.github/actions/setupenv 32 | 33 | # Generate bootable image 34 | # The Xvfb process causes the job to hang, so is killed after the image is generated 35 | - name: Make boot 36 | id: make_boot 37 | run: | 38 | echo "boot_files=false" >> $GITHUB_OUTPUT 39 | cd repos/PandABlocks-fpga 40 | ln -s CONFIG.example CONFIG 41 | make boot APP_NAME=${{ matrix.app }} 42 | ps -Ao pid= -o comm= | awk '$2 ~ /Xvfb/ { print $1}' | xargs kill 43 | 44 | # Upload artifacts if boot files present 45 | - name: Upload boot 46 | if: ${{ steps.make_boot.outputs.boot_files == 'true'}} 47 | uses: actions/upload-artifact@v4 48 | with: 49 | name: boot-${{ matrix.app }} 50 | path: /build/boot*.zip 51 | -------------------------------------------------------------------------------- /.github/workflows/_make_zpkg.yml: -------------------------------------------------------------------------------- 1 | on: 2 | workflow_call: 3 | 4 | env: 5 | WORK_DIR: /__w/PandABlocks-FPGA/PandABlocks-FPGA 6 | 7 | jobs: 8 | make_zpkg: 9 | strategy: 10 | fail-fast: false 11 | matrix: 12 | app: [ 13 | "PandABox-no-fmc", 14 | "PandABox-fmc_24vio", 15 | "PandABox-fmc_acq427", 16 | "PandABox-fmc_acq430", 17 | "PandABox-fmc_lback-sfp_lback", 18 | "PandABrick", 19 | "xu5_st1-no-fmc", 20 | "xu5_st1-fmc_acq430" 21 | ] 22 | runs-on: 23 | group: iris_runners 24 | container: 25 | image: ghcr.io/pandablocks/pandablocks-ci-container:latest 26 | options: --privileged 27 | 28 | steps: 29 | # Necessary to find action.yml 30 | - name: Checkout Source 31 | uses: actions/checkout@v4 32 | with: 33 | path: repos/PandABlocks-fpga 34 | fetch-depth: 0 35 | 36 | - name: Checkout rootfs and Give Directory Perms 37 | uses: ./repos/PandABlocks-fpga/.github/actions/setupenv 38 | 39 | # Make zpkgs 40 | - name: build carrier_ip and zpkg 41 | id: make_zpkg 42 | run: | 43 | cd repos/PandABlocks-fpga 44 | ln -s CONFIG.example CONFIG 45 | make WORK_DIR=$WORK_DIR carrier_ip APP_NAME=${{ matrix.app }} 46 | tini -s -- make WORK_DIR=$WORK_DIR zpkg APP_NAME=${{ matrix.app }} 47 | 48 | # Artifacts 49 | - name: Upload zpkg 50 | uses: actions/upload-artifact@v4 51 | with: 52 | name: zpkgs-${{ matrix.app }} 53 | path: /build/panda-fpga@*.zpg -------------------------------------------------------------------------------- /.github/workflows/_release.yml: -------------------------------------------------------------------------------- 1 | on: 2 | workflow_call: 3 | 4 | jobs: 5 | release: 6 | runs-on: ubuntu-latest 7 | # make a release on every tag 8 | if: github.event_name == 'push' && startsWith(github.event.ref, 'refs/tags') 9 | steps: 10 | - uses: actions/download-artifact@v4 11 | with: 12 | path: zpkgs 13 | merge-multiple: true 14 | 15 | 16 | - name: Github Release 17 | # We pin to the SHA, not the tag, for security reasons. 18 | # https://docs.github.com/en/actions/learn-github-actions/security-hardening-for-github-actions#using-third-party-actions 19 | uses: softprops/action-gh-release@2d72d869af3bf23602f9593a1e3fd739b80ac1eb # v0.1.12 20 | with: 21 | prerelease: ${{ contains(github.ref_name, 'a') || contains(github.ref_name, 'b') || contains(github.ref_name, 'rc') }} 22 | files: zpkgs/* 23 | body: See [Changelog](CHANGELOG.rst) for more details 24 | env: 25 | GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} 26 | -------------------------------------------------------------------------------- /.github/workflows/_test_hdl.yml: -------------------------------------------------------------------------------- 1 | on: 2 | workflow_call: 3 | inputs: 4 | matrix: 5 | required: true 6 | type: string 7 | 8 | jobs: 9 | test: 10 | strategy: 11 | fail-fast: false 12 | # Using generated matrix from previous job 13 | matrix: ${{fromJSON(inputs.matrix)}} 14 | runs-on: 15 | group: iris_runners 16 | container: 17 | image: ghcr.io/pandablocks/pandablocks-ci-container:latest 18 | options: --privileged 19 | 20 | steps: 21 | # Necessary to find action.yml 22 | - name: Checkout Source 23 | uses: actions/checkout@v4 24 | with: 25 | path: repos/PandABlocks-fpga 26 | fetch-depth: 0 27 | 28 | - name: Checkout rootfs and Give Directory Perms 29 | uses: ./repos/PandABlocks-fpga/.github/actions/setupenv 30 | 31 | # Run tests 32 | - name: Make hdl Tests 33 | run: | 34 | cd repos/PandABlocks-fpga 35 | ln -s CONFIG.example CONFIG 36 | make hdl_test MODULES="${{matrix.modules}}" -------------------------------------------------------------------------------- /.github/workflows/_test_matrix.yml: -------------------------------------------------------------------------------- 1 | on: 2 | workflow_call: 3 | outputs: 4 | matrix: 5 | value: ${{ jobs.test_matrix.outputs.matrix }} 6 | 7 | env: 8 | WORK_DIR: /__w/PandABlocks-FPGA/PandABlocks-FPGA 9 | 10 | jobs: 11 | test_matrix: 12 | runs-on: 13 | group: iris_runners 14 | container: 15 | image: docker.io/shihabdls/pandablocks-container-extension:v2.5 16 | options: --privileged 17 | outputs: 18 | matrix: ${{steps.make_matrix.outputs.matrix}} 19 | steps: 20 | - name: Checkout Source 21 | uses: actions/checkout@v4 22 | with: 23 | path: repos/PandABlocks-fpga 24 | fetch-depth: 0 25 | 26 | - name: Evaluate number of modules/tests & generate job matrix 27 | id: make_matrix 28 | run: | 29 | bash $WORK_DIR/repos/PandABlocks-fpga/.github/scripts/Find_Tests.sh "$WORK_DIR/repos/PandABlocks-fpga/modules" "$WORK_DIR/repos/PandABlocks-fpga/.github/scripts" 30 | json_content=$(cat github_tests.json) 31 | echo "::set-output name=matrix::$json_content" 32 | echo "$json_content" -------------------------------------------------------------------------------- /.github/workflows/_test_python_autogen.yml: -------------------------------------------------------------------------------- 1 | on: 2 | workflow_call: 3 | 4 | jobs: 5 | test_python_autogen: 6 | runs-on: 7 | group: iris_runners 8 | container: 9 | image: ghcr.io/pandablocks/pandablocks-ci-container:latest 10 | options: --privileged 11 | 12 | steps: 13 | # Necessary to find action.yml 14 | - name: Checkout Source 15 | uses: actions/checkout@v4 16 | with: 17 | path: repos/PandABlocks-fpga 18 | fetch-depth: 0 19 | 20 | - name: Checkout rootfs and Give Directory Perms 21 | uses: ./repos/PandABlocks-fpga/.github/actions/setupenv 22 | 23 | # Run tests 24 | - name: Make Python Tests 25 | run: | 26 | cd repos/PandABlocks-fpga 27 | ln -s CONFIG.example CONFIG 28 | make python_tests 29 | make python_timing 30 | make autogen -------------------------------------------------------------------------------- /.github/workflows/code.yml: -------------------------------------------------------------------------------- 1 | name: Code CI 2 | 3 | on: 4 | # Only run on changes to branches with open PRs 5 | pull_request: 6 | types: [opened, edited, synchronize] 7 | # Run after PR merged, on implicit push, and on tag pushes 8 | push: 9 | tags: 10 | - '*' 11 | branches: [master] 12 | 13 | jobs: 14 | 15 | # Make Boot files 16 | make_boot: 17 | uses: ./.github/workflows/_make_boot.yml 18 | 19 | # Make zpkg for FPGA apps 20 | make_zpkg: 21 | uses: ./.github/workflows/_make_zpkg.yml 22 | 23 | # Release on push to tag 24 | release: 25 | needs: [ make_boot, make_zpkg, test_hdl, test_matrix, test_python_autogen ] 26 | uses: ./.github/workflows/_release.yml 27 | 28 | # Generate job matrix to evenly split tests 29 | test_matrix: 30 | uses: ./.github/workflows/_test_matrix.yml 31 | 32 | # python and autogen tests 33 | test_python_autogen: 34 | uses: ./.github/workflows/_test_python_autogen.yml 35 | 36 | # hdl tests 37 | test_hdl: 38 | needs: [test_matrix, test_python_autogen] 39 | uses: ./.github/workflows/_test_hdl.yml 40 | with: 41 | matrix: ${{needs.test_matrix.outputs.matrix}} -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /CONFIG 2 | /build 3 | /docs/build 4 | *.pyc 5 | *~ 6 | /build_* 7 | *.jou 8 | *.log 9 | .Xil 10 | 11 | # virtual environment folder 12 | /venv 13 | .idea 14 | 15 | # For mac 16 | *.DS_Store 17 | -------------------------------------------------------------------------------- /CHANGELOG.rst: -------------------------------------------------------------------------------- 1 | Changelog 2 | ========= 3 | 4 | The changelog for the PandABlocks-FPGA repo is the list of `closed pull requests 5 | `_ 6 | 7 | All developments for the ``master`` branch take place via pull requests. 8 | -------------------------------------------------------------------------------- /CONFIG.example: -------------------------------------------------------------------------------- 1 | # Example configuration file for building PandA firmware, and for simulation 2 | # 3 | # Copy this file to a file named CONFIG and edit as appropriate. Lines that are 4 | # commented out can be left as they are, the default value is shown. Uncommented 5 | # lines must be assigned values. 6 | 7 | # Default build location. Default is to build in build subdirectory. 8 | BUILD_DIR = /build 9 | 10 | # Development Tool Version 11 | # VIVADO_VER = 2023.2 12 | 13 | # Definitions needed for FPGA build 14 | export VIVADO = /scratch/Xilinx/Vivado/$(VIVADO_VER)/settings64.sh 15 | # Path to external IP repository (if required) 16 | export EXT_IP_REPO = /scratch/Xilinx/XAPP589/PICXO_FRACXO_v40_rev6 17 | 18 | 19 | # Specifiy licence server, if required 20 | # export LM_LICENSE_FILE = 21 | 22 | # Location of rootfs builder. This needs to be at least version 1.13 and can be 23 | # downloaded from https://github.com/araneidae/rootfs 24 | export ROOTFS_TOP = /rootfs 25 | 26 | # Where to find source files 27 | export TAR_FILES = /tar-files 28 | 29 | # Path to root filesystem 30 | # WORK_DIR can be ignored for local builds, explicitly set in CI 31 | PANDA_ROOTFS = $(WORK_DIR)/repos/PandABlocks-rootfs 32 | # MAKE_ZPKG = $(PANDA_ROOTFS)/make-zpkg 33 | 34 | # Python interpreter for running scripts 35 | # 36 | # PYTHON = python3 37 | 38 | # Sphinx build for documentation. 39 | # SPHINX_BUILD = sphinx-build 40 | 41 | # List of default targets to build when running make 42 | # DEFAULT_TARGETS = zpkg 43 | 44 | # FPGA Application Name 45 | APP_NAME = PandABox-fmc_lback-sfp_lback 46 | 47 | # vim: set filetype=make: -------------------------------------------------------------------------------- /apps/PandABox-fmc_24vio.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: 3 | Standard set of PandABox blocks with: 4 | - DLS 24V I/O FMC module 5 | - PandA synchroniser on SFP3 6 | target: PandABox 7 | options: !pcap_std_dev 8 | includes: common_soft_blocks.include.ini 9 | 10 | [FMC_24V] 11 | module: fmc_24vio 12 | 13 | [SFP3_SYNC] 14 | module: sfp_panda_sync 15 | site: sfp 3 16 | -------------------------------------------------------------------------------- /apps/PandABox-fmc_acq427.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: 3 | Standard set of PandABox blocks with: 4 | - D-TACQ ACQ427 FMC module 5 | - PandA synchroniser on SFP3 6 | target: PandABox 7 | options: !pcap_std_dev 8 | includes: common_soft_blocks.include.ini 9 | 10 | [FMC] 11 | module: fmc_acq427 12 | 13 | [SFP3_SYNC] 14 | module: sfp_panda_sync 15 | site: sfp 3 16 | -------------------------------------------------------------------------------- /apps/PandABox-fmc_acq430.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: 3 | Standard set of PandABox blocks with: 4 | - D-TACQ ACQ430 FMC module 5 | - PandA synchroniser on SFP3 6 | target: PandABox 7 | options: !pcap_std_dev 8 | includes: common_soft_blocks.include.ini 9 | 10 | [FMC_ACQ430_IN] 11 | module: fmc_acq430 12 | 13 | [SFP3_SYNC] 14 | module: sfp_panda_sync 15 | site : sfp 3 16 | 17 | -------------------------------------------------------------------------------- /apps/PandABox-fmc_lback-sfp_lback.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: 3 | Standard set of PandABox blocks with: 4 | - loopback FMC module 5 | - loopback SPF modules in all 3 sites 6 | Used for hardware testing only 7 | target: PandABox 8 | options: fine_delay 9 | includes: common_soft_blocks.include.ini 10 | 11 | [FMC_LBACK] 12 | module: fmc_loopback 13 | 14 | [SFP1_LBACK] 15 | module: sfp_loopback 16 | site: sfp 1 17 | 18 | [SFP2_LBACK] 19 | module: sfp_loopback 20 | site: sfp 2 21 | 22 | [SFP3_LBACK] 23 | module: sfp_loopback 24 | site: sfp 3 25 | 26 | [SFP4_LBACK] 27 | module: sfp_loopback 28 | site: fmc_mgt 1 29 | 30 | -------------------------------------------------------------------------------- /apps/PandABox-no-fmc-sfp2_udpontrig.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: 3 | Standard set of PandABox blocks with: 4 | - no FMC modules 5 | - udpontrig on SFP2 6 | target: PandABox 7 | options: !pcap_std_dev 8 | includes: common_soft_blocks.include.ini 9 | 10 | [SFP2_UDPONTRIG] 11 | module: sfp_udpontrig 12 | site: sfp 2 13 | 14 | 15 | -------------------------------------------------------------------------------- /apps/PandABox-no-fmc-sfp3_dls_eventr.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: 3 | Standard set of PandABox blocks with: 4 | - no FMC modules 5 | - DLS event reciever on SFP3 6 | - PandA synchroniser on SFP2 7 | target: PandABox 8 | options: !pcap_std_dev 9 | includes: common_soft_blocks.include.ini 10 | 11 | [SFP3_EVR] 12 | module: sfp_eventr 13 | ini: sfp_dls_eventr.block.ini 14 | site: sfp 3 15 | 16 | [SFP2_SYNC] 17 | module: sfp_panda_sync 18 | site: sfp 2 19 | 20 | -------------------------------------------------------------------------------- /apps/PandABox-no-fmc.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: 3 | Standard set of PandABox blocks with: 4 | - no FMC modules 5 | - PandA synchroniser on SFP3 6 | target: PandABox 7 | options: !pcap_std_dev 8 | includes: common_soft_blocks.include.ini 9 | 10 | [SFP2_SYNC] 11 | module: sfp_panda_sync 12 | site: sfp 2 13 | 14 | [SFP3_SYNC] 15 | module: sfp_panda_sync 16 | site: sfp 3 17 | 18 | -------------------------------------------------------------------------------- /apps/PandABrick.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: 3 | Standard set of PandABlocks with: 4 | - built-in FMC encoder card 5 | - PandA synchroniser on SFP on-board FMC 6 | target: PandABrick 7 | includes: pandabrick_soft_blocks.include.ini 8 | 9 | [SFP_SYNC] 10 | module: sfp_panda_sync 11 | ini: sfp_panda_sync_us.block.ini 12 | site: sfp 1 13 | 14 | -------------------------------------------------------------------------------- /apps/ZedBoard-no-fmc.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Standard set of PandABox blocks with no SFP or FMC modules 3 | target: ZedBoard 4 | 5 | [BITS] 6 | number:1 7 | 8 | [CLOCK] 9 | number:1 10 | 11 | -------------------------------------------------------------------------------- /apps/xu5_st1-fmc_acq430.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Standard set of PandABox blocks with a D-TACQ ACQ430 FMC module 3 | target: xu5_st1 4 | includes: common_soft_blocks.include.ini 5 | 6 | [FMC_ACQ430_IN] 7 | module: fmc_acq430 8 | 9 | -------------------------------------------------------------------------------- /apps/xu5_st1-fmc_x4sfp.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: 3 | Standard set of PandABox blocks with: 4 | - FMC x4SFP 5 | - PandA synchroniser on all MGTs 6 | target: xu5_st1 7 | options: !pcap_std_dev 8 | includes: common_soft_blocks.include.ini 9 | 10 | [FMC_X4SFP] 11 | module: fmc_x4sfp 12 | 13 | [SFP1_SYNC] 14 | module: sfp_panda_sync 15 | ini: sfp_panda_sync_us.block.ini 16 | site: fmc_mgt 1 17 | 18 | [SFP2_SYNC] 19 | module: sfp_panda_sync 20 | ini: sfp_panda_sync_us.block.ini 21 | site: fmc_mgt 2 22 | 23 | [SFP3_SYNC] 24 | module: sfp_panda_sync 25 | ini: sfp_panda_sync_us.block.ini 26 | site: fmc_mgt 3 27 | 28 | [SFP4_SYNC] 29 | module: sfp_panda_sync 30 | ini: sfp_panda_sync_us.block.ini 31 | site: fmc_mgt 4 32 | 33 | 34 | -------------------------------------------------------------------------------- /apps/xu5_st1-no-fmc.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Standard set of PandaBox blocks with no FMC modules 3 | target: xu5_st1 4 | includes: common_soft_blocks.include.ini 5 | 6 | -------------------------------------------------------------------------------- /check-whitespace: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Simple script to check for files with bad whitespace. Checks for trailing 4 | # whitespace and unexpected hard tab characters. 5 | 6 | cd "$(dirname "$0")" 7 | 8 | # Search for files with trailing whitespace 9 | grep --exclude-dir=build --exclude-dir=.git -rIl ' $' . 10 | 11 | # Search for files with tab characters 12 | # We exclude Makefiles because they need tab characters 13 | # We also exclude the .dts files because that seems to be the convention 14 | grep --exclude-dir=build --exclude-dir=.git \ 15 | --exclude=Makefile --exclude=\*.dts -rIl $'\t' . 16 | -------------------------------------------------------------------------------- /common/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/common/__init__.py -------------------------------------------------------------------------------- /common/hdl/iobuf_registered.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- PandA Motion Project - 2016 3 | -- Diamond Light Source, Oxford, UK 4 | -- SOLEIL Synchrotron, GIF-sur-YVETTE, France 5 | -- 6 | -- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) 7 | -------------------------------------------------------------------------------- 8 | -- 9 | -- Description : An IOBUF macro with registered I and O with IOB packing 10 | -- 11 | -------------------------------------------------------------------------------- 12 | 13 | library ieee; 14 | use ieee.std_logic_1164.all; 15 | use ieee.numeric_std.all; 16 | 17 | library unisim; 18 | use unisim.vcomponents.all; 19 | 20 | entity iobuf_registered is 21 | port ( 22 | clock : in std_logic; 23 | I : in std_logic; 24 | O : out std_logic; 25 | T : in std_logic; 26 | IO : inout std_logic 27 | ); 28 | end iobuf_registered; 29 | 30 | architecture rtl of iobuf_registered is 31 | 32 | signal ipad : std_logic; 33 | signal opad : std_logic; 34 | 35 | begin 36 | 37 | -------------------------------------------------------------------------- 38 | -- Register and pack into IOBs 39 | -------------------------------------------------------------------------- 40 | process(clock) begin 41 | if rising_edge(clock) then 42 | O <= opad; 43 | ipad <= I; 44 | end if; 45 | end process; 46 | 47 | -- Physical IOBUF instantiations controlled with PROTOCOL 48 | IOBUF_inst : IOBUF 49 | port map ( 50 | I => ipad, 51 | O => opad, 52 | T => T, 53 | IO => IO 54 | ); 55 | 56 | end rtl; 57 | 58 | -------------------------------------------------------------------------------- /common/hdl/pll_autoreset.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.numeric_std.all; 3 | use ieee.std_logic_1164.all; 4 | 5 | entity pll_autoreset is 6 | port ( 7 | clk_i : in std_logic; 8 | pll_locked_i : in std_logic; 9 | pll_reset_o : out std_logic 10 | ); 11 | end pll_autoreset; 12 | 13 | 14 | architecture rtl of pll_autoreset is 15 | constant c_wait_reset : natural := 1000; 16 | 17 | signal pll_reset_cnt : unsigned(9 downto 0) := (others => '0'); 18 | begin 19 | 20 | process(clk_i) 21 | begin 22 | if rising_edge(clk_i) then 23 | -- Enable the PLL reset 24 | if pll_reset_cnt /= c_wait_reset and pll_locked_i = '0' then 25 | pll_reset_cnt <= pll_reset_cnt + 1; 26 | -- Reset the PLL reset when it goes out of lock 27 | elsif pll_locked_i = '1' then 28 | pll_reset_cnt <= (others => '0'); 29 | end if; 30 | if pll_locked_i = '0' then 31 | if pll_reset_cnt = c_wait_reset then 32 | pll_reset_o <= '0'; 33 | else 34 | pll_reset_o <= '1'; 35 | end if; 36 | end if; 37 | end if; 38 | end process; 39 | 40 | end architecture rtl; 41 | -------------------------------------------------------------------------------- /common/hdl/prescaler.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- File: prescaler.vhd 3 | -- Desc: A simple 32-bit prescaler. 4 | -- 5 | -------------------------------------------------------------------------------- 6 | library ieee; 7 | use ieee.std_logic_1164.all; 8 | use ieee.numeric_std.all; 9 | 10 | entity prescaler is 11 | port ( 12 | clk_i : in std_logic; 13 | reset_i : in std_logic; 14 | PERIOD : in std_logic_vector(31 downto 0); 15 | pulse_o : out std_logic 16 | ); 17 | end prescaler; 18 | 19 | architecture rtl of prescaler is 20 | 21 | signal clk_cnt : unsigned(31 downto 0) := (others => '0'); 22 | 23 | begin 24 | 25 | -- 26 | -- 32-bit up counter rolling over PERIOD 27 | -- 28 | process(clk_i) 29 | begin 30 | if rising_edge(clk_i) then 31 | if (reset_i = '1') then 32 | pulse_o <= '0'; 33 | clk_cnt <= (others => '0'); 34 | else 35 | if (clk_cnt = unsigned(PERIOD)-1) then 36 | pulse_o <= '1'; 37 | clk_cnt <= (others => '0'); 38 | else 39 | pulse_o <= '0'; 40 | clk_cnt <= clk_cnt + 1; 41 | end if; 42 | end if; 43 | end if; 44 | end process; 45 | 46 | end rtl; 47 | -------------------------------------------------------------------------------- /common/hdl/prescaler_pos.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- File: prescaler.vhd 3 | -- Desc: A simple 32-bit prescaler. 4 | -- 5 | -------------------------------------------------------------------------------- 6 | library ieee; 7 | use ieee.std_logic_1164.all; 8 | use ieee.numeric_std.all; 9 | 10 | entity prescaler_pos is 11 | port ( 12 | clk_i : in std_logic; 13 | reset_i : in std_logic; 14 | PERIOD : in std_logic_vector(31 downto 0); 15 | pulse_o : out std_logic 16 | ); 17 | end prescaler_pos; 18 | 19 | architecture rtl of prescaler_pos is 20 | 21 | constant c_zeros : unsigned(31 downto 0) := X"00000000"; 22 | 23 | signal clk_cnt : unsigned(31 downto 0) := (others => '0'); 24 | signal period_rollover : unsigned(31 downto 0); 25 | 26 | begin 27 | 28 | period_rollover <= c_zeros when (unsigned(PERIOD) < 1) else unsigned(PERIOD) - 1; 29 | 30 | pulse_o <= '1' when (clk_cnt = period_rollover) else '0'; 31 | 32 | -- 33 | -- Generate QENC clk defined by the prescaler 34 | -- 35 | qenc_clk_gen : process(clk_i) 36 | begin 37 | if rising_edge(clk_i) then 38 | if (reset_i = '1') then 39 | clk_cnt <= (others => '0'); 40 | else 41 | if (clk_cnt = period_rollover) then 42 | clk_cnt <= (others => '0'); 43 | else 44 | clk_cnt <= clk_cnt + 1; 45 | end if; 46 | end if; 47 | end if; 48 | end process; 49 | 50 | end rtl; 51 | -------------------------------------------------------------------------------- /common/hdl/sync_bit.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity sync_bit is 5 | port ( 6 | clk_i : in std_logic; 7 | bit_i : in std_logic; 8 | bit_o : out std_logic 9 | ); 10 | end entity; 11 | 12 | architecture rtl of sync_bit is 13 | 14 | signal bit_meta : std_logic; 15 | 16 | attribute async_reg : string; 17 | attribute async_reg of bit_meta : signal is "TRUE"; 18 | attribute async_reg of bit_o : signal is "TRUE"; 19 | 20 | begin 21 | 22 | sync_io : process (clk_i) begin 23 | if rising_edge(clk_i) then 24 | bit_meta <= bit_i; 25 | bit_o <= bit_meta; 26 | end if; 27 | end process; 28 | 29 | end; 30 | -------------------------------------------------------------------------------- /common/hdl/ts_mux.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | use work.top_defines.all; 6 | use work.support.all; 7 | 8 | entity ts_mux is 9 | generic ( 10 | NUM_SFP : natural := 1 11 | ); 12 | port ( 13 | clk_i : in std_logic; 14 | ts_src_i : in std_logic_vector(LOG2(NUM_SFP) downto 0); 15 | latch_en_i : in std_logic; 16 | ts_sec_i : in std32_array(NUM_SFP-1 downto 0); 17 | ts_ticks_i : in std32_array(NUM_SFP-1 downto 0); 18 | ts_sec_o : out std_logic_vector(31 downto 0); 19 | ts_ticks_o : out std_logic_vector(31 downto 0) 20 | ); 21 | end ts_mux; 22 | 23 | architecture rtl of ts_mux is 24 | 25 | begin 26 | 27 | process(clk_i) 28 | begin 29 | if rising_edge(clk_i) then 30 | if latch_en_i then 31 | if unsigned(ts_src_i) = 0 then 32 | ts_sec_o <= (others => '0'); 33 | ts_ticks_o <= (others => '0'); 34 | elsif unsigned(ts_src_i) <= NUM_SFP then 35 | ts_sec_o <= ts_sec_i(to_integer(unsigned(ts_src_i))-1); 36 | ts_ticks_o <= ts_ticks_i(to_integer(unsigned(ts_src_i))-1); 37 | else 38 | ts_sec_o <= (others => '0'); 39 | ts_ticks_o <= (others => '0'); 40 | end if; 41 | end if; 42 | end if; 43 | end process; 44 | 45 | end rtl; 46 | 47 | -------------------------------------------------------------------------------- /common/hdl_zynq/IDDR_sync_bit.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | Library UNISIM; 5 | use UNISIM.vcomponents.all; 6 | 7 | entity IDDR_sync_bit is 8 | port ( 9 | clk_i : in std_logic; 10 | bit_i : in std_logic; 11 | bit_o : out std_logic 12 | ); 13 | end entity; 14 | 15 | architecture rtl of IDDR_sync_bit is 16 | 17 | signal tied_to_ground : std_logic := '0'; 18 | signal tied_to_vcc : std_logic := '1'; 19 | 20 | begin 21 | 22 | IDDR_inst : IDDR 23 | generic map ( 24 | DDR_CLK_EDGE => "SAME_EDGE_PIPELINED") 25 | port map ( 26 | Q1 => bit_o, 27 | Q2 => open, 28 | C => clk_i, 29 | CE => tied_to_vcc, 30 | D => bit_i, 31 | R => tied_to_ground, 32 | S => tied_to_ground 33 | ); 34 | 35 | end; 36 | -------------------------------------------------------------------------------- /common/hdl_zynqmp/IDDR_sync_bit.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | Library UNISIM; 5 | use UNISIM.vcomponents.all; 6 | 7 | entity IDDR_sync_bit is 8 | port ( 9 | clk_i : in std_logic; 10 | bit_i : in std_logic; 11 | bit_o : out std_logic 12 | ); 13 | end entity; 14 | 15 | architecture rtl of IDDR_sync_bit is 16 | 17 | signal tied_to_ground : std_logic := '0'; 18 | signal tied_to_vcc : std_logic := '1'; 19 | 20 | begin 21 | 22 | IDDRE1_inst : IDDRE1 23 | generic map ( 24 | DDR_CLK_EDGE => "SAME_EDGE_PIPELINED" 25 | ) 26 | port map ( 27 | D => bit_i, 28 | Q1 => bit_o, 29 | Q2 => open, 30 | C => clk_i, 31 | CB => not clk_i, 32 | R => tied_to_ground 33 | ); 34 | end; 35 | -------------------------------------------------------------------------------- /common/python/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/common/python/__init__.py -------------------------------------------------------------------------------- /common/python/compat.py: -------------------------------------------------------------------------------- 1 | try: 2 | # Python2 3 | import ConfigParser as configparser 4 | except ImportError: 5 | # Python3 6 | import configparser 7 | 8 | try: 9 | # For type checking only 10 | from typing import TYPE_CHECKING 11 | except ImportError: 12 | TYPE_CHECKING = False 13 | 14 | try: 15 | # Python2 16 | str_ = basestring 17 | except NameError: 18 | # Python3 19 | str_ = str 20 | 21 | # Taken from six 22 | def add_metaclass(metaclass): 23 | """Class decorator for creating a class with a metaclass.""" 24 | def wrapper(cls): 25 | orig_vars = cls.__dict__.copy() 26 | orig_vars.pop('__dict__', None) 27 | orig_vars.pop('__weakref__', None) 28 | return metaclass(cls.__name__, cls.__bases__, orig_vars) 29 | return wrapper 30 | -------------------------------------------------------------------------------- /common/python/generate_constants.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import argparse 3 | 4 | 5 | def parse_args(): 6 | parser = argparse.ArgumentParser() 7 | parser.add_argument('file_path') 8 | return parser.parse_args() 9 | 10 | 11 | def main(): 12 | args = parse_args() 13 | print('library ieee;') 14 | print('use ieee.std_logic_1164.all;') 15 | print('package panda_constants is') 16 | 17 | for line in open(args.file_path, 'r'): 18 | if '=' not in line: 19 | continue 20 | 21 | first, second = line.split('=') 22 | key, val = first.strip().upper(), int(second) 23 | print(f' constant {key} : std_logic_vector(31 downto 0)', end='') 24 | print(f' := X"{val:08x}";') 25 | 26 | print('end panda_constants;') 27 | 28 | 29 | if __name__ == "__main__": 30 | main() 31 | -------------------------------------------------------------------------------- /common/python/parse_git_version.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | """ 3 | Generate FPGA version like 0.1.0c9 from git describe like 0.1-9-g5539563-dirty 4 | """ 5 | from __future__ import print_function 6 | import logging 7 | import re 8 | from argparse import ArgumentParser 9 | 10 | 11 | def parse_git_version(git_version): 12 | # type: (str) -> str 13 | # Get the git tag numbers, they should be of the format x.y[.z][-something] 14 | match = re.match("(\d+)\.(\d+)(?:\.(\d+))?(?:-(\d+))?", git_version) 15 | assert match, "Git version %r can't be parsed" % git_version 16 | hex_numbers = [] 17 | for g in match.groups(): 18 | if g: 19 | hex_numbers.append("%02x" % min(int(g), 255)) 20 | else: 21 | hex_numbers.append("00") 22 | return "".join(hex_numbers[-1:] + hex_numbers[:-1]) 23 | 24 | 25 | def main(): 26 | parser = ArgumentParser(description=__doc__) 27 | parser.add_argument("git_describe", help="Output of git describe") 28 | git_version = parser.parse_args().git_describe 29 | try: 30 | hex_str = parse_git_version(git_version) 31 | except Exception as e: 32 | logging.exception(e) 33 | # Something went wrong, just print 0.0.0c0 34 | hex_str = "00000000" 35 | print(hex_str) 36 | 37 | 38 | if __name__ == "__main__": 39 | main() 40 | -------------------------------------------------------------------------------- /common/scripts/build_boot.tcl: -------------------------------------------------------------------------------- 1 | set PLATFORM [lindex $argv 0] 2 | set HWSPEC [lindex $argv 1] 3 | set DEVTREE_SRC [lindex $argv 2] 4 | set OUTPUT_DIR [lindex $argv 3] 5 | 6 | if {$PLATFORM=="zynq"} { 7 | set PROC ps7_cortexa9_0 8 | set FSBL_APP zynq_fsbl 9 | } elseif {$PLATFORM=="zynqmp"} { 10 | set PROC psu_cortexa53_0 11 | set FSBL_APP zynqmp_fsbl 12 | } else { 13 | error "Unknown target platform!" 14 | } 15 | 16 | hsi open_hw_design $HWSPEC 17 | hsi generate_app -proc $PROC -app $FSBL_APP -dir $OUTPUT_DIR/fsbl -compile 18 | hsi set_repo_path $DEVTREE_SRC 19 | hsi create_sw_design device_tree -os device_tree -proc $PROC 20 | hsi generate_target -dir $OUTPUT_DIR/dts 21 | if {$PLATFORM=="zynqmp"} { 22 | hsi generate_app -os standalone -proc psu_pmu_0 -app zynqmp_pmufw \ 23 | -dir $OUTPUT_DIR/pmufw -compile 24 | } 25 | hsi close_hw_design [hsi current_hw_design] 26 | 27 | -------------------------------------------------------------------------------- /common/scripts/build_ip.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Generate IP Cores 3 | # 4 | 5 | set TOP [lindex $argv 0] 6 | 7 | set IP_PROJ [lindex $argv 1] 8 | 9 | set BUILD_DIR [lindex $argv 2] 10 | 11 | set IP [lindex $argv 3] 12 | 13 | set IP_TCL [lindex $argv 4] 14 | 15 | # Open Managed IP Project 16 | open_project $IP_PROJ 17 | 18 | #Remove IP from project if already existing 19 | if {[file exists $BUILD_DIR/$IP/$IP.xci]} { 20 | remove_files [get_files $BUILD_DIR/$IP/$IP.xci] 21 | file delete -force $BUILD_DIR/$IP 22 | } 23 | 24 | #Create and configure XCI file 25 | source $IP_TCL 26 | 27 | # Generate output products for global synthesis 28 | set_property generate_synth_checkpoint false [get_files $BUILD_DIR/$IP/$IP.xci] 29 | generate_target all [get_files $BUILD_DIR/$IP/$IP.xci] 30 | 31 | # Procedure for modifying generated sources 32 | proc replaceInFile {file searchPat oldVal newVal} { 33 | set fd [open $file r] 34 | set newfd [open ${file}.tmp w] 35 | while {[gets $fd line] >= 0} { 36 | if {[string match $searchPat $line] == 1} { 37 | regsub $oldVal $line $newVal newline 38 | puts $newfd $newline 39 | } else { 40 | puts $newfd $line 41 | } 42 | } 43 | close $fd 44 | close $newfd 45 | file rename -force ${file}.tmp $file 46 | } 47 | 48 | # Check if patch function defined for IP and run 49 | if {[llength [info proc patch]] > 0} { 50 | patch $BUILD_DIR 51 | } 52 | 53 | close_project 54 | 55 | -------------------------------------------------------------------------------- /common/scripts/build_ip_proj.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Generate IP Project 3 | # 4 | 5 | set TGT_INCL_TCL [lindex $argv 0] 6 | 7 | # Source directory 8 | set PROJ_FILE [lindex $argv 1] 9 | 10 | # Set external IP REPO path 11 | set EXT_IP_REPO [lindex $argv 2] 12 | 13 | source $TGT_INCL_TCL 14 | 15 | # Create Managed IP Project 16 | create_project -part $FPGA_PART -force -ip $PROJ_FILE 17 | 18 | set_property target_language VHDL [current_project] 19 | set_property target_simulator ModelSim [current_project] 20 | 21 | set_property ip_repo_paths $EXT_IP_REPO [current_project] 22 | 23 | close_project 24 | 25 | -------------------------------------------------------------------------------- /common/scripts/build_ps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Generate PS part of the firmware based as Zynq Block design 3 | # 4 | 5 | set TOP [lindex $argv 0] 6 | 7 | # Source directory 8 | set TARGET_DIR [lindex $argv 1] 9 | 10 | # Build directory 11 | set BUILD_DIR [lindex $argv 2] 12 | 13 | # Output file 14 | set OUTPUT_FILE [lindex $argv 3] 15 | 16 | source $TARGET_DIR/target_incl.tcl 17 | 18 | # Create project 19 | create_project -part $FPGA_PART -force panda_ps $BUILD_DIR 20 | 21 | # Set the directory path for the new project 22 | set proj_dir [get_property directory [current_project]] 23 | 24 | # Set project properties 25 | set obj [get_projects panda_ps] 26 | set_property "default_lib" "xil_defaultlib" $obj 27 | set_property "simulator_language" "Mixed" $obj 28 | set_property "target_language" "VHDL" $obj 29 | 30 | # Create block design 31 | # (THIS is exported from Vivado design tool) 32 | source $TARGET_DIR/bd/panda_ps.tcl 33 | 34 | # Generate the wrapper 35 | set design_name [get_bd_designs] 36 | make_wrapper -files [get_files $design_name.bd] -top -import 37 | 38 | # Create 'sources_1' fileset (if not found) 39 | if {[string equal [get_filesets -quiet sources_1] ""]} { 40 | create_fileset -srcset sources_1 41 | } 42 | 43 | # Set 'sources_1' fileset properties 44 | set obj [get_filesets sources_1] 45 | set_property "top" "panda_ps_wrapper" $obj 46 | 47 | # Generate Output Files 48 | set_property GENERATE_SYNTH_CHECKPOINT FALSE [get_files $OUTPUT_FILE] 49 | generate_target all [get_files $OUTPUT_FILE] 50 | 51 | # Export to SDK 52 | write_hw_platform -fixed -force $BUILD_DIR/panda_ps.xsa 53 | 54 | -------------------------------------------------------------------------------- /common/scripts/make_bif_zynq.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Creates bootgen interface file from arguments 4 | 5 | cat <"$1" 6 | the_ROM_image: { 7 | [bootloader]$2 8 | $3 9 | } 10 | EOF 11 | -------------------------------------------------------------------------------- /common/scripts/make_bif_zynqmp.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Creates bootgen interface file from arguments 4 | 5 | cat <"$1" 6 | the_ROM_image: { 7 | [bootloader,destination_cpu=a53-0] $2 8 | [pmufw_image] $3 9 | [destination_cpu=a53-0,exception_level=el-3,trustzone] $4 10 | [destination_cpu=a53-0,exception_level=el-2] $5 11 | } 12 | EOF 13 | -------------------------------------------------------------------------------- /common/templates/config.jinja2: -------------------------------------------------------------------------------- 1 | *METADATA 2 | APPNAME constant ={{ app }} 3 | DESIGN string 4 | LAYOUT multiline 5 | EXPORTS multiline 6 | {% for block in server_blocks %} 7 | {# Make a label for holding the block description #} 8 | {% for i in range(block.number) %} 9 | {{ pad("LABEL_%s%d" % (block.name, i + 1)) }} string 10 | {% endfor %} 11 | {% endfor %} 12 | 13 | {% for block in server_blocks %} 14 | {# block is a BlockConfig object #} 15 | {# insert its name and the number of block instances in this app #} 16 | {{ block.name }}[{{ block.number }}] 17 | {% for field in block.fields %} 18 | {# field is a FieldConfig object #} 19 | {# insert its name and type (including subtype and options) #} 20 | {% if not field.no_config %} 21 | {{ pad(field.name) }} {{ field.config_line() }} 22 | {% for line in field.extra_config_lines %} 23 | {# some fields line enum and table have extra lines, insert them here #} 24 | {{ line }} 25 | {% endfor %} 26 | {% endif %} 27 | {% endfor %} 28 | {# insert a blank line between blocks for readability #} 29 | 30 | {% endfor %} 31 | -------------------------------------------------------------------------------- /common/templates/constraints.tcl.jinja2: -------------------------------------------------------------------------------- 1 | # AUTOGENERATED 2 | 3 | # All IP code required 4 | {% for ip in ips %} 5 | read_ip $IP_DIR/{{ ip }}/{{ ip }}.xci 6 | {% endfor %} 7 | 8 | # Module code and constraints 9 | {% for block in fpga_blocks %} 10 | {# block module code #} 11 | add_files $TOP_DIR/{{ block.module_path }}/hdl/ 12 | set_property -quiet FILE_TYPE "VHDL 2019" [get_files $TOP_DIR/{{ block.module_path }}/hdl/*.vhd] 13 | add_files -quiet $TOP_DIR/{{ block.module_path }}/hdl_$PLATFORM/ 14 | set_property -quiet FILE_TYPE "VHDL 2019" [get_files -quiet $TOP_DIR/{{ block.module_path }}/hdl_$PLATFORM/*.vhd] 15 | {# MGT pin constraints #} 16 | {% for const in block.interfaceConstraints %} 17 | add_files $TARGET_DIR/const/{{const}} 18 | {% endfor %} 19 | {# Module constraints #} 20 | {% for const in block.constraints %} 21 | add_files $AUTOGEN/const/{{ block.name }}_{{ os.path.basename(const) }} 22 | {% endfor %} 23 | {% endfor %} 24 | -------------------------------------------------------------------------------- /common/templates/default_ipmi.ini: -------------------------------------------------------------------------------- 1 | # No IPMI EEPROM expected 2 | [.] 3 | eeprom = ignore 4 | -------------------------------------------------------------------------------- /common/templates/descriptions.jinja2: -------------------------------------------------------------------------------- 1 | {% for block in server_blocks %} 2 | {# block is a BlockConfig object #} 3 | {# insert its name and description #} 4 | {{ pad(block.name) }} {{ block.description }} 5 | {% for field in block.fields %} 6 | {# field is a FieldConfig object #} 7 | {# insert its name and description #} 8 | {% if not field.no_config %} 9 | {{ pad(field.name) }} {{ field.description }} 10 | {% endif %} 11 | {% endfor %} 12 | {# insert a blank line between blocks for readability #} 13 | 14 | {% endfor %} 15 | -------------------------------------------------------------------------------- /common/templates/ip.make.jinja2: -------------------------------------------------------------------------------- 1 | {% for ip in ips %} 2 | APP_IP_DEPS += $(IP_DIR)/{{ ip }}/IP_DONE 3 | {% endfor %} 4 | -------------------------------------------------------------------------------- /common/templates/module.tcl.jinja2: -------------------------------------------------------------------------------- 1 | # AUTOGENERATED 2 | # This is a script to add all of the tests and required hdl code for the 3 | # {{block.entity}} module to the vivado project 4 | 5 | set_property SOURCE_SET sources_1 [get_filesets sim_1] 6 | 7 | array set tests { 8 | {% for i in range(number) %} 9 | {{block.entity}}_{{loop.index}}_tb 1 10 | {% endfor %} 11 | } 12 | 13 | # add the module vhd code 14 | add_files -norecurse $TOP_DIR/modules/{{block.entity}}/hdl 15 | 16 | # read xci files for any IP required by module 17 | {% if block.ip %} 18 | {% for ip in block.ip %} 19 | read_ip $TGT_BUILD_DIR/ip_repo/{{ ip }}/{{ ip }}.xci 20 | {% endfor %} 21 | {% endif %} 22 | 23 | add_files -fileset sim_1 -norecurse \ 24 | {% for i in range(number) %} 25 | $BUILD_DIR/hdl_timing/{{block.entity}}/timing{{'%03d'% loop.index|int}}/hdl_timing.sv \ 26 | $BUILD_DIR/hdl_timing/{{block.entity}}/timing{{'%03d'% loop.index|int}}/{{ 27 | loop.index}}{{block.entity}}expected.csv \ 28 | {% endfor %} 29 | $TOP_DIR/modules/{{block.entity}}/ 30 | 31 | -------------------------------------------------------------------------------- /common/templates/reg_defines.vhd.jinja2: -------------------------------------------------------------------------------- 1 | --AUTOGENERATED 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | package reg_defines is 7 | 8 | {% for reg in regs %} 9 | {% if "*" in reg.name %} 10 | 11 | --{{ reg.name }} block: 12 | 13 | {% else %} 14 | constant {{reg.block}}_{{reg.name}} : natural := {{reg.number}}; 15 | {% endif %} 16 | {% endfor %} 17 | 18 | end reg_defines; 19 | 20 | package body reg_defines is 21 | 22 | 23 | end reg_defines; 24 | -------------------------------------------------------------------------------- /common/templates/registers.jinja2: -------------------------------------------------------------------------------- 1 | {% include 'registers_server' %} 2 | 3 | {% for block in server_blocks %} 4 | {# block is a BlockConfig object #} 5 | {# insert its name and block base address #} 6 | {{ pad(block.name) }} {{ block.block_address }}{% 7 | if block.extension %} {{ block.extension }}{% endif %} 8 | 9 | {% for field in block.fields %} 10 | {# field is a FieldConfig object #} 11 | {# ask it for its register addresses within the block base address #} 12 | {% if not field.no_config %} 13 | {{ pad(field.name) }} {{ field.address_line() }} 14 | {% endif %} 15 | {% endfor %} 16 | {# insert a blank line between blocks for readability #} 17 | 18 | {% endfor %} 19 | -------------------------------------------------------------------------------- /common/templates/sim_server.jinja2: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python2 2 | # Autogenerated hardware simulation server. 3 | # 4 | # Lists on a socket port and performs the appropriate exchange to implement 5 | # hardware reading and writing. 6 | 7 | try: 8 | from pkg_resources import require 9 | require('numpy') 10 | except ImportError: 11 | pass 12 | 13 | import argparse 14 | import os 15 | import sys 16 | 17 | parser = argparse.ArgumentParser(description='PandA Hardware simulation') 18 | parser.add_argument( 19 | '-d', '--daemon', action='store_true', help='Run as daemon process') 20 | parser.add_argument( 21 | '-v', '--verbose', action='store_true', help='Log register access') 22 | args = parser.parse_args() 23 | 24 | # Import from the simulation module to do the work 25 | sys.path.append(os.path.join(os.path.dirname(__file__), "..", "..", "..", "..")) 26 | from common.python.simulations import \ 27 | SimulationController, SimulationServer, daemonise 28 | 29 | # Create as much of the controller before we daemonise so that errors can be 30 | # caught if possible at this stage. 31 | controller = SimulationController(args.verbose) 32 | {% for block in fpga_blocks %} 33 | controller.create_block("{{ block.ini_path }}", {{ block.number }}, {{ block.block_address }}) 34 | {% endfor %} 35 | server = SimulationServer(controller) 36 | 37 | print 'Simulating server ready' 38 | if args.daemon: 39 | daemonise() 40 | 41 | # now we can start the simulation ticking 42 | server.run() 43 | -------------------------------------------------------------------------------- /common/templates/top_defines_gen.vhd.jinja2: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package top_defines_gen is 5 | 6 | -------------------------------------------------------------------------- 7 | -- !!! Remember to add aliases for any new entities here to top_defines 8 | -------------------------------------------------------------------------- 9 | 10 | -- Bit Bus Width, Multiplexer Select Width ------------------------------- 11 | constant BBUSW : natural := 128; 12 | constant BBUSBW : natural := 7; 13 | 14 | -- Position Bus Width, Multiplexer Select Width. 15 | constant PBUSW : natural := {{ total_pos_bus_length }}; 16 | constant PBUSBW : natural := 5; 17 | 18 | -- Extended Position Bus Width. 19 | constant EBUSW : natural := 12; 20 | -------------------------------------------------------------------------- 21 | 22 | -- FPGA options 23 | {% for option, val in fpga_options.items() %} 24 | constant {{ option | upper }}_OPTION : std_logic := '{{ val | int }}'; 25 | {% endfor %} 26 | 27 | end top_defines_gen; 28 | -------------------------------------------------------------------------------- /docs/PandA-logo.ico: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/PandA-logo.ico -------------------------------------------------------------------------------- /docs/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/__init__.py -------------------------------------------------------------------------------- /docs/_static/theme_overrides.css: -------------------------------------------------------------------------------- 1 | /* make line indents zero so we can break table rows */ 2 | .rst-content .line-block { 3 | margin-left: 0px; 4 | } 5 | 6 | /* override table width restrictions */ 7 | @media screen and (min-width: 639px) { 8 | 9 | .wy-table-responsive table td { 10 | /* !important prevents the common CSS stylesheets from 11 | overriding this as on RTD they are loaded after this stylesheet */ 12 | white-space: normal !important; 13 | } 14 | 15 | .wy-table-responsive { 16 | overflow: visible !important; 17 | } 18 | 19 | } 20 | 21 | /* override table padding */ 22 | .rst-content table.docutils th, .rst-content table.docutils td { 23 | padding: 4px 6px; 24 | } 25 | 26 | /* Add two-column option */ 27 | @media only screen and (min-width: 1000px) { 28 | .columns { 29 | padding-left: 10px; 30 | padding-right: 10px; 31 | float: left; 32 | width: 50%; 33 | min-height: 145px; 34 | } 35 | } 36 | 37 | .endcolumns { 38 | clear: both 39 | } 40 | -------------------------------------------------------------------------------- /docs/blocks.rst: -------------------------------------------------------------------------------- 1 | .. _blocks_doc: 2 | 3 | Available Blocks 4 | ================ 5 | 6 | These are the `block_` types that may be built into an `app_`. Some are 7 | soft blocks, and some are tied to particular hardware, so not all Blocks 8 | will be included in every `pandablocks_device_`. 9 | 10 | .. include:: build/blocks.txt -------------------------------------------------------------------------------- /docs/fpga_arch.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/fpga_arch.png -------------------------------------------------------------------------------- /docs/index.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | Documentation 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /docs/reference/build_arch.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/reference/build_arch.png -------------------------------------------------------------------------------- /docs/reference/changelog.rst: -------------------------------------------------------------------------------- 1 | .. include:: ../../CHANGELOG.rst 2 | -------------------------------------------------------------------------------- /docs/reference/contributing.rst: -------------------------------------------------------------------------------- 1 | .. include:: ../../CONTRIBUTING.rst 2 | -------------------------------------------------------------------------------- /docs/reference/testing.rst: -------------------------------------------------------------------------------- 1 | Running the tests 2 | ================= 3 | 4 | There are a number of different test systems in place within the 5 | PandABlocks-FPGA directory. There are python tests to check the output of some 6 | of the Jinja2 templates, python tests to check the logic of the timing diagram 7 | and then there are hdl testbenches which test the functionality of the blocks. 8 | The python tests are ran as part of the Travis tests when a commit is made to 9 | the git repository, however the hdl testbenches have to be manually ran. 10 | 11 | Python tests 12 | ~~~~~~~~~~~~ 13 | 14 | The first of the python tests, checking the output of the Jinja2 templates, can 15 | be run from the Makefile:: 16 | 17 | make python_tests 18 | 19 | The python simulation tests, can be run with the following Makefile command:: 20 | 21 | make python_timing 22 | 23 | HDL tests 24 | ~~~~~~~~~ 25 | 26 | There are two Makefile functions which can be used to run the hdl testbenches:: 27 | 28 | make hdl_test MODULES="module name" 29 | 30 | make single_hdl_test TEST="MODULE_NAME TEST_NUMBER" 31 | 32 | The first, by default, will run every testbench. However if the optional 33 | argument of MODULES is given it will instead run every test for the specified 34 | module. Please note that the module name is the entity name for the top level 35 | hdl filein that module. 36 | 37 | The second command will run a single testbench as specified by the module name, 38 | and the test number separated by a space. 39 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | matplotlib 2 | sphinx 3 | sphinx_rtd_theme 4 | -------------------------------------------------------------------------------- /docs/tutorials/tutorial1_bits.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/tutorials/tutorial1_bits.png -------------------------------------------------------------------------------- /docs/tutorials/tutorial1_layout.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/tutorials/tutorial1_layout.png -------------------------------------------------------------------------------- /docs/tutorials/tutorial1_pulse.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/tutorials/tutorial1_pulse.png -------------------------------------------------------------------------------- /docs/tutorials/tutorial2_layout.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/tutorials/tutorial2_layout.png -------------------------------------------------------------------------------- /docs/tutorials/tutorial2_pcap.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/tutorials/tutorial2_pcap.png -------------------------------------------------------------------------------- /docs/tutorials/tutorial2_positions.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/docs/tutorials/tutorial2_positions.png -------------------------------------------------------------------------------- /docs/tutorials/tutorial3_position_compare.rst: -------------------------------------------------------------------------------- 1 | .. _position_compare_tutorial: 2 | 3 | Position Compare Tutorial 4 | ========================= 5 | 6 | This tutorial will introduce you to the concept of Position Compare. It will 7 | show a one dimensional scan of an encoder, how to create trigger pulses 8 | at regularly spaced positional intervals, and capture time information. 9 | -------------------------------------------------------------------------------- /docs/tutorials/tutorial4_snake_scan.rst: -------------------------------------------------------------------------------- 1 | .. _snake_scan_tutorial: 2 | 3 | Snake Scan Tutorial 4 | =================== 5 | 6 | This tutorial will introduce the concept of table based position compare 7 | using the SEQ block to do a two dimensional 'snake' scan. This is where the 8 | X dimension scans forward over the range, Y steps forward, then X scans 9 | backwards, repeated until the scan is complete. 10 | -------------------------------------------------------------------------------- /etc/check_ipmi: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | # Validates FMC IPMI EEPROM against the expected configuration 4 | from __future__ import print_function 5 | 6 | import sys 7 | import errno 8 | from i2c import ini_file, eeprom, parse_ipmi 9 | 10 | IPMI_INI = '/opt/share/panda-fpga/ipmi.ini' 11 | 12 | 13 | ini = ini_file.load_ini_file(IPMI_INI) 14 | 15 | # Read the eeprom key from the [.] section, default to "required" if missing 16 | try: 17 | eeprom_key = ini['.']['eeprom'] 18 | except KeyError: 19 | eeprom_key = 'required' 20 | 21 | 22 | if eeprom_key == 'ignore': 23 | # No FMC card fitted, or FMC has no EEPROM. Just ignore the EEPROM 24 | print('Ignoring IPMI EEPROM') 25 | sys.exit(0) 26 | 27 | # We expect the EEPROM to be present. First try to read it. 28 | try: 29 | image = eeprom.read_eeprom() 30 | except OSError as e: 31 | if e.errno == errno.ENXIO: # No such device or address (i.e. no FMC EEPROM detected) 32 | print('FMC was expected but none detected') 33 | sys.exit(1) 34 | else: 35 | print('Unable to read FMC EEPROM:', e) 36 | sys.exit(1) 37 | except Exception as e: 38 | print('Unable to read FMC EEPROM:', e) 39 | sys.exit(1) 40 | 41 | # Now try to parse the image we've just read 42 | try: 43 | ipmi = parse_ipmi.parse(image) 44 | except Exception as e: 45 | print('Error parsing FMC EEPROM:', e) 46 | sys.exit(1) 47 | 48 | # Finally check the parse against the ini file 49 | try: 50 | ini_file.compare_ini(ini, ipmi, ignore = ['.']) 51 | except ini_file.CompareFail as e: 52 | print('FMC EEPROM mismatch:', e) 53 | sys.exit(1) 54 | 55 | # If we get this far then all is well! 56 | print('FMC EEPROM matches') 57 | sys.exit(0) 58 | -------------------------------------------------------------------------------- /etc/i2c/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/etc/i2c/__init__.py -------------------------------------------------------------------------------- /etc/panda-fpga.docs.html: -------------------------------------------------------------------------------- 1 |

FPGA

2 | 3 |

4 | The FPGA provides the implementation of the logical Blocks that are wired 5 | together for a given application. It exposes a register interface to the 6 | TCP server so that the parameters and wiring of these Blocks can be changed 7 | at runtime. 8 |

9 | 10 | 12 | FPGA Documentation 13 | 14 | 15 | -------------------------------------------------------------------------------- /etc/show_ipmi: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | # Dumps IPMI EEPROM in readable format 4 | 5 | import sys 6 | import argparse 7 | 8 | from i2c import eeprom, parse_ipmi 9 | 10 | parser = argparse.ArgumentParser(description = 'Dump FMC IPMI EEPROM') 11 | parser.add_argument( 12 | '-b', '--binary', action = 'store_true', default = False, 13 | help = 'Dump raw EEPROM image') 14 | args = parser.parse_args() 15 | 16 | 17 | image = eeprom.read_eeprom() 18 | if args.binary: 19 | image.tofile(sys.stdout) 20 | else: 21 | parse_ipmi.parse(image).emit() 22 | -------------------------------------------------------------------------------- /etc/write_eeprom: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import argparse 3 | import errno 4 | import sys 5 | 6 | from i2c import smbus2, eeprom, ini_file, create_ipmi 7 | 8 | 9 | def parse_args(): 10 | parser = argparse.ArgumentParser(description='flash data to FMC EEPROM') 11 | parser.add_argument( 12 | 'ini_path', type=str, help='Path to IPMI definition file') 13 | return parser.parse_args() 14 | 15 | 16 | 17 | def main(): 18 | args = parse_args() 19 | ini = ini_file.load_ini_file(args.ini_path) 20 | print('Please ensure the FMC is', ini['Board']['product name']) 21 | serial_number = input('Serial number: ').strip() 22 | if not serial_number: 23 | serial_number = None 24 | 25 | ipmi = create_ipmi.generate_ipmi(ini, serial_number) 26 | bus = smbus2.SMBus(0) 27 | try: 28 | address16bit = ini['.']['eeprom'] == '16-bit' 29 | except KeyError: 30 | address16bit = False 31 | 32 | print('Writing EEPROM...') 33 | eeprom.write_address(data=ipmi, address16bit=address16bit) 34 | readback = eeprom.read_eeprom(length=len(ipmi)) 35 | if bytes(readback) != bytes(ipmi): 36 | print('Verification failed') 37 | sys.exit(1) 38 | else: 39 | print('Verification OK') 40 | 41 | 42 | if __name__ == "__main__": 43 | main() 44 | -------------------------------------------------------------------------------- /includes/common_soft_blocks.include.ini: -------------------------------------------------------------------------------- 1 | [BITS] 2 | number: 1 3 | 4 | [CALC] 5 | number: 2 6 | 7 | [CLOCK] 8 | number: 2 9 | 10 | [COUNTER] 11 | number: 8 12 | 13 | [DIV] 14 | number: 2 15 | 16 | [FILTER] 17 | number: 2 18 | 19 | [LUT] 20 | number: 8 21 | 22 | [PCOMP] 23 | number: 2 24 | 25 | [PGEN] 26 | number: 2 27 | 28 | [PULSE] 29 | number: 4 30 | 31 | [SEQ] 32 | number: 2 33 | 34 | [SRGATE] 35 | number: 4 36 | -------------------------------------------------------------------------------- /includes/pandabrick_soft_blocks.include.ini: -------------------------------------------------------------------------------- 1 | [BITS] 2 | number: 1 3 | 4 | [CALC] 5 | number: 2 6 | 7 | [CLOCK] 8 | number: 2 9 | 10 | [COUNTER] 11 | number: 4 12 | 13 | [DIV] 14 | number: 2 15 | 16 | [FILTER] 17 | number: 2 18 | 19 | [LUT] 20 | number: 8 21 | 22 | [PCOMP] 23 | number: 2 24 | 25 | [PGEN] 26 | number: 2 27 | 28 | [PULSE] 29 | number: 4 30 | 31 | [SEQ] 32 | number: 2 33 | 34 | [SRGATE] 35 | number: 4 36 | -------------------------------------------------------------------------------- /ip_defs/PICXO_FRACXO.tcl: -------------------------------------------------------------------------------- 1 | ## Create PICXO IP 2 | 3 | create_ip -vlnv [get_ipdefs -filter {NAME == PICXO_FRACXO}] -module_name PICXO_FRACXO -dir $BUILD_DIR/ 4 | 5 | set_property CONFIG.GT_TYPE {GTX} [get_ips PICXO_FRACXO] 6 | 7 | -------------------------------------------------------------------------------- /ip_defs/eth_mac.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create Eth Mac for sfp 3 | # 4 | 5 | create_ip -vlnv [get_ipdefs -filter {NAME == tri_mode_ethernet_mac}] \ 6 | -module_name eth_mac -dir $BUILD_DIR/ 7 | 8 | 9 | #shared logic inside of core 10 | # CONFIG.Physical_Interface {GMII} \ phy_eth is internal (no IOB or idelay in pad) CONFIG.Physical_Interface {Internal} 11 | 12 | set_property -dict [list \ 13 | CONFIG.Physical_Interface {Internal} \ 14 | CONFIG.MAC_Speed {1000_Mbps} \ 15 | CONFIG.Management_Interface {false} \ 16 | CONFIG.Management_Frequency {125.00} \ 17 | CONFIG.Enable_Priority_Flow_Control {false} \ 18 | CONFIG.Frame_Filter {false} \ 19 | CONFIG.Number_of_Table_Entries {0} \ 20 | CONFIG.Enable_MDIO {false} \ 21 | CONFIG.SupportLevel {1} \ 22 | CONFIG.Make_MDIO_External {false} \ 23 | CONFIG.Statistics_Counters {false} \ 24 | ] [get_ips eth_mac] 25 | 26 | -------------------------------------------------------------------------------- /ip_defs/eth_phy.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create Eth Phy for sfp 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == gig_ethernet_pcs_pma}] \ 5 | -module_name eth_phy -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design} \ 9 | CONFIG.Management_Interface {false} \ 10 | CONFIG.Auto_Negotiation {false} \ 11 | CONFIG.EMAC_IF_TEMAC {TEMAC} \ 12 | ] [get_ips eth_phy] 13 | 14 | -------------------------------------------------------------------------------- /ip_defs/fifo_1K32.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create Standard 1Kx32-bit FIFO IP 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == fifo_generator}] \ 5 | -module_name fifo_1K32 -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.Fifo_Implementation {Common_Clock_Distributed_RAM} \ 9 | CONFIG.Input_Data_Width {32} \ 10 | CONFIG.Data_Count {true} \ 11 | CONFIG.Output_Data_Width {32} \ 12 | CONFIG.Reset_Type {Synchronous_Reset} \ 13 | ] [get_ips fifo_1K32] 14 | 15 | 16 | -------------------------------------------------------------------------------- /ip_defs/fifo_1K32_ft.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create Standard 1Kx32-bit first word fall through FIFO IP 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == fifo_generator}] \ 5 | -module_name fifo_1K32_ft -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.Fifo_Implementation {Common_Clock_Distributed_RAM} \ 9 | CONFIG.Performance_Options {First_Word_Fall_Through} \ 10 | CONFIG.Input_Data_Width {32} \ 11 | CONFIG.Data_Count {true} \ 12 | CONFIG.Output_Data_Width {32} \ 13 | CONFIG.Reset_Type {Synchronous_Reset} \ 14 | ] [get_ips fifo_1K32_ft] 15 | 16 | -------------------------------------------------------------------------------- /ip_defs/fmc_acq427_dac_fifo.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create Standard Asymmetric 1K, 128-bit(WR), 32-bit(RD) FIFO IP for ACQ427 DAC FMC 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == fifo_generator}] \ 5 | -module_name fmc_acq427_dac_fifo -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} \ 9 | CONFIG.Input_Data_Width {128} \ 10 | CONFIG.Input_Depth {16} \ 11 | CONFIG.Output_Data_Width {32} \ 12 | CONFIG.Write_Data_Count {true} \ 13 | CONFIG.Read_Data_Count {true} \ 14 | CONFIG.Output_Depth {64} \ 15 | CONFIG.Reset_Type {Asynchronous_Reset} \ 16 | CONFIG.Full_Flags_Reset_Value {1} \ 17 | CONFIG.Data_Count_Width {4} \ 18 | CONFIG.Write_Data_Count_Width {4} \ 19 | CONFIG.Read_Data_Count_Width {6} \ 20 | CONFIG.Full_Threshold_Assert_Value {13} \ 21 | CONFIG.Full_Threshold_Negate_Value {12} 22 | ] [get_ips fmc_acq427_dac_fifo] 23 | 24 | -------------------------------------------------------------------------------- /ip_defs/fmc_acq430_ch_fifo.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create Standard Asymmetric 1K, 32-bit(WR), 256-bit(RD) FIFO IP for ACQ430 FMC 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == fifo_generator}] \ 5 | -module_name fmc_acq430_ch_fifo -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} \ 9 | CONFIG.asymmetric_port_width {true} \ 10 | CONFIG.Input_Data_Width {32} \ 11 | CONFIG.Input_Depth {256} \ 12 | CONFIG.Output_Data_Width {256} \ 13 | CONFIG.Read_Data_Count {true} \ 14 | CONFIG.Output_Depth {32} \ 15 | CONFIG.Reset_Type {Asynchronous_Reset} \ 16 | CONFIG.Full_Flags_Reset_Value {1} \ 17 | CONFIG.Data_Count_Width {8} \ 18 | CONFIG.Write_Data_Count_Width {8} \ 19 | CONFIG.Read_Data_Count_Width {5} \ 20 | CONFIG.Full_Threshold_Assert_Value {253} \ 21 | CONFIG.Full_Threshold_Negate_Value {252} 22 | ] [get_ips fmc_acq430_ch_fifo] 23 | 24 | -------------------------------------------------------------------------------- /ip_defs/fmc_acq430_sample_ram.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create low level ACQ430 FMC Sample RAM 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == dist_mem_gen}] \ 5 | -module_name fmc_acq430_sample_ram -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.depth {32} \ 9 | CONFIG.data_width {24} \ 10 | CONFIG.memory_type {dual_port_ram} \ 11 | CONFIG.output_options {registered} \ 12 | CONFIG.common_output_clk {true} 13 | ] [get_ips fmc_acq430_sample_ram] 14 | 15 | -------------------------------------------------------------------------------- /ip_defs/ila_0.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create ILA chipscope 3 | create_ip -vlnv [get_ipdefs -filter {NAME == ila}] \ 4 | -module_name ila_0 -dir $BUILD_DIR/ 5 | 6 | set_property -dict [list \ 7 | CONFIG.C_DATA_DEPTH {2048} \ 8 | CONFIG.C_PROBE7_WIDTH {32} \ 9 | CONFIG.C_PROBE6_WIDTH {6} \ 10 | CONFIG.C_PROBE5_WIDTH {32} \ 11 | CONFIG.C_PROBE4_WIDTH {32} \ 12 | CONFIG.C_PROBE3_WIDTH {32} \ 13 | CONFIG.C_PROBE2_WIDTH {32} \ 14 | CONFIG.C_PROBE1_WIDTH {32} \ 15 | CONFIG.C_PROBE0_WIDTH {32} \ 16 | CONFIG.C_NUM_OF_PROBES {8} \ 17 | CONFIG.C_TRIGOUT_EN {false} \ 18 | CONFIG.C_TRIGIN_EN {false} \ 19 | ] [get_ips ila_0] 20 | 21 | -------------------------------------------------------------------------------- /ip_defs/ila_32x8K.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create ILA IP (32-bit wide with 8K Depth) 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == ila}] \ 5 | -module_name ila_32x8K -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.C_PROBE0_WIDTH {32} \ 9 | CONFIG.C_DATA_DEPTH {8192} \ 10 | ] [get_ips ila_32x8K] 11 | 12 | -------------------------------------------------------------------------------- /ip_defs/picxo_ila.tcl: -------------------------------------------------------------------------------- 1 | create_ip -vlnv [get_ipdefs -filter {NAME == ila}] -module_name picxo_ila -dir $BUILD_DIR/ 2 | 3 | set_property -dict [list \ 4 | CONFIG.ALL_PROBE_SAME_MU_CNT {2} \ 5 | CONFIG.C_EN_STRG_QUAL {1} \ 6 | CONFIG.C_INPUT_PIPE_STAGES {2} \ 7 | CONFIG.C_NUM_OF_PROBES {10} \ 8 | CONFIG.C_PROBE0_WIDTH {21} \ 9 | CONFIG.C_PROBE1_WIDTH {22} \ 10 | CONFIG.C_PROBE2_WIDTH {8} \ 11 | ] [get_ips picxo_ila] 12 | 13 | -------------------------------------------------------------------------------- /ip_defs/picxo_vio.tcl: -------------------------------------------------------------------------------- 1 | create_ip -vlnv [get_ipdefs -filter {NAME == vio}] -module_name picxo_vio -dir $BUILD_DIR/ 2 | 3 | set_property -dict [list \ 4 | CONFIG.C_NUM_PROBE_IN {0} \ 5 | CONFIG.C_NUM_PROBE_OUT {15} \ 6 | CONFIG.C_PROBE_OUT0_INIT_VAL {0x08} \ 7 | CONFIG.C_PROBE_OUT0_WIDTH {5} \ 8 | CONFIG.C_PROBE_OUT12_WIDTH {7} \ 9 | CONFIG.C_PROBE_OUT13_WIDTH {10} \ 10 | CONFIG.C_PROBE_OUT14_WIDTH {10} \ 11 | CONFIG.C_PROBE_OUT1_INIT_VAL {0x10} \ 12 | CONFIG.C_PROBE_OUT1_WIDTH {5} \ 13 | CONFIG.C_PROBE_OUT2_INIT_VAL {0x0200} \ 14 | CONFIG.C_PROBE_OUT2_WIDTH {16} \ 15 | CONFIG.C_PROBE_OUT3_INIT_VAL {0x0200} \ 16 | CONFIG.C_PROBE_OUT3_WIDTH {16} \ 17 | CONFIG.C_PROBE_OUT4_INIT_VAL {0x4} \ 18 | CONFIG.C_PROBE_OUT4_WIDTH {4} \ 19 | CONFIG.C_PROBE_OUT5_INIT_VAL {0x0003ff} \ 20 | CONFIG.C_PROBE_OUT5_WIDTH {24} \ 21 | CONFIG.C_PROBE_OUT6_WIDTH {22} \ 22 | ] [get_ips picxo_vio] 23 | 24 | -------------------------------------------------------------------------------- /ip_defs/pulse_queue.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create PULSE_QUEUE IP 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == fifo_generator}]\ 5 | -module_name pulse_queue -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.Fifo_Implementation {Common_Clock_Distributed_RAM} \ 9 | CONFIG.Performance_Options {First_Word_Fall_Through} \ 10 | CONFIG.Input_Data_Width {49} \ 11 | CONFIG.Input_Depth {256} \ 12 | CONFIG.Data_Count {true} \ 13 | CONFIG.Output_Data_Width {49} \ 14 | CONFIG.Output_Depth {256} \ 15 | CONFIG.Reset_Type {Synchronous_Reset} \ 16 | ] [get_ips pulse_queue] 17 | 18 | -------------------------------------------------------------------------------- /ip_defs/sfp_panda_sync_us.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create SFP sync mgt core for Ultrascale+ 3 | create_ip -vlnv [get_ipdefs -filter {NAME == gtwizard_ultrascale}] \ 4 | -module_name sfp_panda_sync_us -dir $BUILD_DIR/ 5 | 6 | set_property -dict [list \ 7 | CONFIG.DISABLE_LOC_XDC {true} \ 8 | CONFIG.CHANNEL_ENABLE {X0Y5} \ 9 | CONFIG.LOCATE_RX_USER_CLOCKING {CORE} \ 10 | CONFIG.LOCATE_TX_USER_CLOCKING {CORE} \ 11 | CONFIG.RX_COMMA_ALIGN_WORD {4} \ 12 | CONFIG.RX_COMMA_M_ENABLE {true} \ 13 | CONFIG.RX_COMMA_PRESET {K28.5} \ 14 | CONFIG.RX_COMMA_P_ENABLE {true} \ 15 | CONFIG.RX_COMMA_SHOW_REALIGN_ENABLE {false} \ 16 | CONFIG.RX_COMMA_VALID_ONLY {0} \ 17 | CONFIG.RX_DATA_DECODING {8B10B} \ 18 | CONFIG.RX_LINE_RATE {5} \ 19 | CONFIG.RX_MASTER_CHANNEL {X0Y5} \ 20 | CONFIG.RX_PLL_TYPE {CPLL} \ 21 | CONFIG.RX_REFCLK_FREQUENCY {125} \ 22 | CONFIG.RX_REFCLK_SOURCE {X0Y5 clk1} \ 23 | CONFIG.TX_DATA_ENCODING {8B10B} \ 24 | CONFIG.TX_LINE_RATE {5} \ 25 | CONFIG.TX_MASTER_CHANNEL {X0Y5} \ 26 | CONFIG.TX_PLL_TYPE {CPLL} \ 27 | CONFIG.TX_REFCLK_FREQUENCY {125} \ 28 | CONFIG.TX_REFCLK_SOURCE {X0Y5 clk1} \ 29 | ] [get_ips sfp_panda_sync_us] 30 | 31 | 32 | -------------------------------------------------------------------------------- /ip_defs/sfp_transmit_mem.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create Memory 3 | create_ip -vlnv [get_ipdefs -filter {NAME == blk_mem_gen}] \ 4 | -module_name sfp_transmit_mem -dir $BUILD_DIR/ 5 | 6 | set_property -dict [list \ 7 | CONFIG.Write_Depth_A {4096} \ 8 | CONFIG.Operating_Mode_A {READ_FIRST} \ 9 | CONFIG.Load_Init_File {true} \ 10 | CONFIG.Coe_File $TOP/tests/sim/sfp_receiver/mem/event_receiver_mem.coe \ 11 | CONFIG.Use_RSTA_Pin {false} \ 12 | ] [get_ips sfp_transmit_mem] 13 | 14 | -------------------------------------------------------------------------------- /ip_defs/sfpgtx.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create SFP GTX Aurora IP 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == gtwizard}] \ 5 | -module_name sfpgtx -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.identical_protocol_file {aurora_8b10b_single_lane_2byte} \ 9 | CONFIG.gt0_val_tx_refclk {REFCLK0_Q0} \ 10 | CONFIG.gt0_val {true} \ 11 | CONFIG.identical_val_tx_line_rate {1} \ 12 | CONFIG.identical_val_tx_reference_clock {125.000} \ 13 | CONFIG.identical_val_rx_line_rate {1} \ 14 | CONFIG.identical_val_rx_reference_clock {125.000} \ 15 | ] [get_ips sfpgtx] 16 | 17 | -------------------------------------------------------------------------------- /ip_defs/system_cmd_fifo.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Create System FPGA Command FIFO 3 | # 4 | create_ip -vlnv [get_ipdefs -filter {NAME == fifo_generator}] \ 5 | -module_name system_cmd_fifo -dir $BUILD_DIR/ 6 | 7 | set_property -dict [list \ 8 | CONFIG.Performance_Options {First_Word_Fall_Through} \ 9 | CONFIG.Input_Data_Width {42} \ 10 | CONFIG.Output_Data_Width {42} \ 11 | ] [get_ips system_cmd_fifo] 12 | 13 | -------------------------------------------------------------------------------- /modules/absenc/absenc.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Absolute encoder 3 | entity: absenc 4 | 5 | [CLK] 6 | type: bit_mux 7 | description: Clock output to slave encoder 8 | 9 | [PROTOCOL] 10 | type: param enum 11 | description: Type of absolute/incremental protocol 12 | 0: SSI 13 | 1: BISS 14 | 2: enDat 15 | 16 | [ENABLED] 17 | type: read bit 18 | description: Is ABSENC enabled? 19 | 20 | [ENCODING] 21 | type: param enum 22 | description: Position encoding (for absolute encoders) 23 | 0: Unsigned Binary 24 | 1: Unsigned Gray 25 | 2: Signed Binary 26 | 3: Signed Gray 27 | 28 | [CLK_SRC] 29 | type: param enum 30 | description: Bypass/Pass Through encoder signals 31 | 0: Internally Generated 32 | 1: From CLK 33 | 34 | [CLK_PERIOD] 35 | type: param time 36 | description: Clock rate 37 | 38 | [FRAME_PERIOD] 39 | type: param time 40 | description: Frame rate 41 | 42 | [BITS] 43 | type: param uint 63 44 | description: Number of bits 45 | 46 | [LSB_DISCARD] 47 | type: param uint 31 48 | description: Number of LSB bits to discard 49 | 50 | [MSB_DISCARD] 51 | type: param uint 31 52 | description: Number of MSB bits to discard 53 | 54 | [DATA] 55 | type: bit_out 56 | description: Data input from slave encoder 57 | 58 | [CONN] 59 | type: bit_out 60 | description: Signal detected 61 | 62 | [HOMED] 63 | type: read bit 64 | description: Quadrature homed status 65 | 66 | [HEALTH] 67 | type: read enum 68 | description: Table status 69 | 0: OK 70 | 1: Linkup error (=not CONN) 71 | 2: Timeout error (for BISS, monitor SSI) 72 | 3: CRC error (for BISS) 73 | 4: Error bit active (for BISS) 74 | 5: ENDAT not implemented 75 | 6: Protocol readback error 76 | 77 | [VAL] 78 | type: pos_out 79 | description: Current position 80 | -------------------------------------------------------------------------------- /modules/absenc/absenc_doc.rst: -------------------------------------------------------------------------------- 1 | ABSENC - Absolute encoder 2 | ========================= 3 | The ABSENC block handles the Absolute encoder signals 4 | 5 | Fields 6 | ------ 7 | 8 | .. block_fields:: modules/absenc/absenc.block.ini 9 | -------------------------------------------------------------------------------- /modules/absenc/hdl: -------------------------------------------------------------------------------- 1 | ../../common/hdl/encoders -------------------------------------------------------------------------------- /modules/bits/bits.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Soft inputs and constant bits 3 | entity: bits 4 | 5 | [A] 6 | type: param bit 7 | description: The value that output A should take 8 | 9 | [B] 10 | type: param bit 11 | description: The value that output B should take 12 | 13 | [C] 14 | type: param bit 15 | description: The value that output C should take 16 | 17 | [D] 18 | type: param bit 19 | description: The value that output D should take 20 | 21 | [OUTA] 22 | type: bit_out 23 | description: The value of A on the bit bus 24 | 25 | [OUTB] 26 | type: bit_out 27 | description: The value of B on the bit bus 28 | 29 | [OUTC] 30 | type: bit_out 31 | description: The value of C on the bit bus 32 | 33 | [OUTD] 34 | type: bit_out 35 | description: The value of D on the bit bus -------------------------------------------------------------------------------- /modules/bits/bits.timing.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Timing diagrams for BITS block 3 | scope: bits.block.ini 4 | 5 | [Outputs follow inputs] 6 | 3 : A=1 -> OUTA=1 7 | 5 : A=0, B=1 -> OUTA=0, OUTB=1 8 | 8 : A=1 -> OUTA=1 9 | 9 : B=0 -> OUTB=0 10 | 13 : A=0 -> OUTA=0 11 | -------------------------------------------------------------------------------- /modules/bits/bits_doc.rst: -------------------------------------------------------------------------------- 1 | BITS - Soft inputs and constant bits 2 | ==================================== 3 | 4 | The BITS block contains 4 soft values A..D. Each of these soft values can be set 5 | to 0 or 1 by using the SET_A..SET_D parameters. 6 | 7 | Fields 8 | ------ 9 | 10 | .. block_fields:: modules/bits/bits.block.ini 11 | 12 | Outputs follow parameters 13 | ------------------------- 14 | 15 | This example shows how the values on the bit bus follow the parameter values 16 | after a 1 clock tick propagation delay 17 | 18 | .. timing_plot:: 19 | :path: modules/bits/bits.timing.ini 20 | :section: Outputs follow inputs -------------------------------------------------------------------------------- /modules/bits/bits_sim.py: -------------------------------------------------------------------------------- 1 | from common.python.simulations import BlockSimulation, properties_from_ini, \ 2 | TYPE_CHECKING 3 | 4 | if TYPE_CHECKING: 5 | from typing import Dict 6 | 7 | 8 | NAMES, PROPERTIES = properties_from_ini(__file__, "bits.block.ini") 9 | 10 | 11 | class BitsSimulation(BlockSimulation): 12 | A, B, C, D, OUTA, OUTB, OUTC, OUTD = PROPERTIES 13 | 14 | def on_changes(self, ts, changes): 15 | """Handle field changes at a particular timestamp 16 | 17 | Args: 18 | ts (int): The timestamp the changes occurred at 19 | changes (Dict[str, int]): Fields that changed with their value 20 | 21 | Returns: 22 | If the Block needs to be called back at a particular ts then return 23 | that int, otherwise return None and it will be called when a field 24 | next changes 25 | """ 26 | # Set attributes 27 | super(BitsSimulation, self).on_changes(ts, changes) 28 | 29 | for name, value in changes.items(): 30 | if name in 'ABCD': 31 | setattr(self, 'OUT'+name, value) 32 | -------------------------------------------------------------------------------- /modules/bits/hdl/bits.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- PandA Motion Project - 2016 3 | -- Diamond Light Source, Oxford, UK 4 | -- SOLEIL Synchrotron, GIF-sur-YVETTE, France 5 | -- 6 | -- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) 7 | -------------------------------------------------------------------------------- 8 | -- 9 | -- Description : BITS block provides 4 user configurable soft inputs. 10 | -- Soft inputs are controlled through register interface. 11 | -- 12 | -------------------------------------------------------------------------------- 13 | 14 | library ieee; 15 | use ieee.std_logic_1164.all; 16 | use ieee.numeric_std.all; 17 | 18 | entity bits is 19 | port ( 20 | -- Clock and Reset 21 | clk_i : in std_logic; 22 | -- Block Input and Outputs 23 | OUTA_o : out std_logic; 24 | OUTB_o : out std_logic; 25 | OUTC_o : out std_logic; 26 | OUTD_o : out std_logic; 27 | -- Block Parameters 28 | A : in std_logic_vector(31 downto 0); 29 | B : in std_logic_vector(31 downto 0); 30 | C : in std_logic_vector(31 downto 0); 31 | D : in std_logic_vector(31 downto 0) 32 | ); 33 | end bits; 34 | 35 | architecture rtl of bits is 36 | 37 | begin 38 | 39 | 40 | process(clk_i) 41 | begin 42 | if rising_edge(clk_i) then 43 | OUTA_o <= A(0); 44 | OUTb_o <= B(0); 45 | OUTc_o <= C(0); 46 | OUTd_o <= D(0); 47 | end if; 48 | end process; 49 | 50 | end rtl; 51 | 52 | 53 | -------------------------------------------------------------------------------- /modules/calc/calc.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | entity: calc 3 | description: Position calc 4 | 5 | [INPA] 6 | type: pos_mux 7 | description: Position input A 8 | 9 | [INPB] 10 | type: pos_mux 11 | description: Position input B 12 | 13 | [INPC] 14 | type: pos_mux 15 | description: Position input C 16 | 17 | [INPD] 18 | type: pos_mux 19 | description: Position input D 20 | 21 | [TYPEA] 22 | type: param enum 23 | description: Source of the value of A for calculation 24 | 0: Value 25 | 1: -Value 26 | 27 | [TYPEB] 28 | type: param enum 29 | description: Source of the value of B for calculation 30 | 0: Value 31 | 1: -Value 32 | 33 | [TYPEC] 34 | type: param enum 35 | description: Source of the value of B for calculation 36 | 0: Value 37 | 1: -Value 38 | 39 | [TYPED] 40 | type: param enum 41 | description: Source of the value of B for calculation 42 | 0: Value 43 | 1: -Value 44 | 45 | [SHIFT] 46 | type: param uint 47 | description: Number of places to right shift calculation result before output 48 | max_value: 2 49 | 50 | [OUT] 51 | type: pos_out 52 | description: Position output 53 | 54 | -------------------------------------------------------------------------------- /modules/calc/calc.timing.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Timing diagrams for CALC block 3 | scope: calc.block.ini 4 | 5 | [Adding inputs] 6 | 3 : INPA = 1 -> OUT = 1 7 | 5 : INPB = 1 -> OUT = 2 8 | 7 : INPC = 4 -> OUT = 6 9 | 8 : INPD = 8 -> OUT = 14 10 | 11 | [Scaling] 12 | 3 : SHIFT = 0 13 | 5 : INPA = 1 -> OUT = 1 14 | 6 : INPB = 1 -> OUT = 2 15 | 8 : SHIFT = 1 -> OUT = 1 16 | 10 : INPC = 10 -> OUT = 6 17 | 12 : SHIFT = 2 -> OUT = 3 18 | 15 : INPD = 10 -> OUT = 5 19 | 16 : INPC = 0 -> OUT = 3 20 | 21 | [Inverting] 22 | 1 : INPA = 1 -> OUT = 1 23 | 4 : INPB = 1 -> OUT = 2 24 | 7 : INPB = 2 -> OUT = 3 25 | 10 : TYPEB = 1 -> OUT = -1 26 | 12 : INPC = 10 -> OUT = 9 27 | 14 : INPD = 8 -> OUT = 17 28 | 19 : TYPED = 1 -> OUT = 1 29 | -------------------------------------------------------------------------------- /modules/calc/calc_doc.rst: -------------------------------------------------------------------------------- 1 | CALC - Position Calc 2 | ==================== 3 | The position calc block has an output which is the sum of the position inputs 4 | 5 | Fields 6 | ------ 7 | 8 | .. block_fields:: modules/calc/calc.block.ini 9 | 10 | Adding inputs 11 | ------------- 12 | The output is the sum of the inputs 13 | 14 | .. timing_plot:: 15 | :path: modules/calc/calc.timing.ini 16 | :section: Adding inputs 17 | 18 | Scaling 19 | ------- 20 | The scale factor is a bit shift and is applied after the sum. 21 | 22 | .. timing_plot:: 23 | :path: modules/calc/calc.timing.ini 24 | :section: Scaling 25 | 26 | Inverting 27 | --------- 28 | Each input can be individually inverted before they are added together 29 | 30 | .. timing_plot:: 31 | :path: modules/calc/calc.timing.ini 32 | :section: Inverting 33 | -------------------------------------------------------------------------------- /modules/calc/calc_sim.py: -------------------------------------------------------------------------------- 1 | from common.python.simulations import BlockSimulation, properties_from_ini 2 | 3 | 4 | NAMES, PROPERTIES = properties_from_ini(__file__, "calc.block.ini") 5 | 6 | 7 | class CalcSimulation(BlockSimulation): 8 | INPA, INPB, INPC, INPD, TYPEA, TYPEB, TYPEC, TYPED, SHIFT, OUT = PROPERTIES 9 | 10 | def on_changes(self, ts, changes): 11 | """Handle changes at a particular timestamp, then return the timestamp 12 | when we next need to be called""" 13 | super(CalcSimulation, self).on_changes(ts, changes) 14 | 15 | inpa = self.INPA * (-1 if self.TYPEA else 1) 16 | inpb = self.INPB * (-1 if self.TYPEB else 1) 17 | inpc = self.INPC * (-1 if self.TYPEC else 1) 18 | inpd = self.INPD * (-1 if self.TYPED else 1) 19 | 20 | self.OUT = (inpa + inpb + inpc + inpd) >> self.SHIFT 21 | -------------------------------------------------------------------------------- /modules/clock/clock.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Configurable clocks 3 | entity: clock 4 | 5 | [ENABLE] 6 | type: bit_mux 7 | description: Halt and reset on falling edge, enable on rising 8 | 9 | [PERIOD] 10 | type: param time 11 | description: Period of clock output 12 | wstb: True 13 | 14 | [WIDTH] 15 | type: param time 16 | description: Width of clock output 17 | wstb: True 18 | 19 | [OUT] 20 | type: bit_out 21 | description: Clock output 22 | -------------------------------------------------------------------------------- /modules/clock/clock_doc.rst: -------------------------------------------------------------------------------- 1 | CLOCK - Configurable clock 2 | ========================== 3 | 4 | The CLOCK block contains a user-settable clock with parametable width and period. 5 | 6 | Fields 7 | ------ 8 | 9 | .. block_fields:: modules/clock/clock.block.ini 10 | 11 | Setting clock period parameters 12 | ------------------------------- 13 | 14 | Each time a clock width or period parameter is set, the clock restarts from that point with 15 | the new width and period value. 16 | 17 | .. timing_plot:: 18 | :path: modules/clock/clock.timing.ini 19 | :section: Setting a parameter starts clock 20 | 21 | The clock is disabled when both width and period parameters are set to 0. 22 | If period is smaller or egale to width then it'll be adjusted to (width + 1) and at least to 2. 23 | If width=0, then the clock duty-cycle will be 50%: 24 | 25 | .. timing_plot:: 26 | :path: modules/clock/clock.timing.ini 27 | :section: Run clock with WIDTH and PERIOD parameters 28 | 29 | Clock settings while disabled 30 | ----------------------------- 31 | 32 | To start the clock synchronously you can set them while the Block is disabled. 33 | It will start on rising edge of ENABLE and be zeroed on the falling edge. 34 | 35 | .. timing_plot:: 36 | :path: modules/clock/clock.timing.ini 37 | :section: Enable low does not run clocks -------------------------------------------------------------------------------- /modules/counter/counter.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Up/Down pulse counter 3 | entity: counter 4 | 5 | [ENABLE] 6 | type: bit_mux 7 | description: Halt on falling edge, reset and enable on rising 8 | 9 | [TRIG] 10 | type: bit_mux 11 | description: Rising edge ticks the counter up/down by STEP 12 | 13 | [DIR] 14 | type: bit_mux 15 | description: Up/Down direction (0 = Up, 1 = Down) 16 | 17 | [TRIG_EDGE] 18 | type: param enum 19 | description: INP trigger edge 20 | wstb: True 21 | 0: Rising 22 | 1: Falling 23 | 2: Either 24 | 25 | [OUT_MODE] 26 | type: param enum 27 | description: Counter OUT update mode (on internal counter value change or on ENABLE falling edge) 28 | 0: On-Change 29 | 1: On-Disable 30 | 31 | [SET] 32 | type: param int 33 | description: set current value of a counter 34 | wstb: true 35 | 36 | [START] 37 | type: param int 38 | description: Counter start value 39 | wstb: True 40 | 41 | [STEP] 42 | type: param 43 | description: Up/Down step value 44 | wstb: True 45 | 46 | [MAX] 47 | type: param int 48 | description: Rollover value 49 | wstb: true 50 | 51 | [MIN] 52 | type: param int 53 | description: Value to which counter should rollover to 54 | wstb: true 55 | 56 | [CARRY] 57 | type: bit_out 58 | description: Internal counter overflow status 59 | 60 | [OUT] 61 | type: pos_out 62 | description: Current counter value 63 | -------------------------------------------------------------------------------- /modules/div/div.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Pulse divider 3 | entity: div 4 | 5 | [ENABLE] 6 | type: bit_mux 7 | description: Reset on falling edge, enable on rising 8 | 9 | [INP] 10 | type: bit_mux 11 | description: Input pulse train 12 | 13 | [DIVISOR] 14 | type: param 15 | description: Divisor value 16 | wstb: True 17 | 18 | [FIRST_PULSE] 19 | type: param enum 20 | description: Where to send first pulse 21 | wstb: True 22 | 0: OutN 23 | 1: OutD 24 | 25 | [OUTD] 26 | type: bit_out 27 | description: Divided pulse output 28 | 29 | [OUTN] 30 | type: bit_out 31 | description: Non-divided pulse output 32 | 33 | [COUNT] 34 | type: read 35 | description: Internal counter value 36 | -------------------------------------------------------------------------------- /modules/div/div_doc.rst: -------------------------------------------------------------------------------- 1 | DIV - Pulse divider 2 | =================== 3 | 4 | A DIV block is a 32-bit pulse divider that can divide a pulse train between two 5 | outputs. It has an internal counter that counts from 0 to DIVISOR-1. On each 6 | rising edge of INP, if counter = DIVISOR-1, then it is set to 0 and the pulse is 7 | sent to OUTD, otherwise it is sent to OUTN. Change in any parameter causes the 8 | block to be reset. 9 | 10 | Fields 11 | ------ 12 | 13 | .. block_fields:: modules/div/div.block.ini 14 | 15 | Which output do pulses go to 16 | ---------------------------- 17 | 18 | With a DIVISOR of 3, the block will send 1 of 3 INP pulses to OUTD and 2 of 3 19 | INP pulses to OUTN. The following two examples illustrate how the FIRST_PULSE 20 | parameter controls the initial value of OUT, which controls whether OUTD or 21 | OUTN gets the next pulse. 22 | 23 | .. timing_plot:: 24 | :path: modules/div/div.timing.ini 25 | :section: Start on OUTN 26 | 27 | .. timing_plot:: 28 | :path: modules/div/div.timing.ini 29 | :section: Start on OUTD 30 | 31 | Reset conditions 32 | ---------------- 33 | 34 | If an ENABLE falling edge is received at the same time as an INP rising edge, 35 | the input signal is ignored and the block reset. 36 | 37 | 38 | .. timing_plot:: 39 | :path: modules/div/div.timing.ini 40 | :section: Reset conditions -------------------------------------------------------------------------------- /modules/filter/filter.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Filter block modes are Difference and Divider 3 | entity: filter 4 | 5 | [ENABLE] 6 | type: bit_mux 7 | description: Enable event 8 | 9 | [TRIG] 10 | type: bit_mux 11 | description: Trigger event 12 | 13 | [INP] 14 | type: pos_mux 15 | description: Input data 16 | 17 | [MODE] 18 | type: param enum 19 | description: Select operation mode 20 | 0: difference 21 | 1: average 22 | 23 | [READY] 24 | type: bit_out 25 | description: Output Ready 26 | 27 | [OUT] 28 | type: pos_out 29 | description: Output data 30 | 31 | [HEALTH] 32 | type: read enum 33 | description: Error 34 | 0: OK 35 | 1: Accumulator overflow 36 | 2: Divider retrigger 37 | -------------------------------------------------------------------------------- /modules/filter/filter_functionality.timing.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Functionality timing diagrams for FILTER block 3 | scope: filter.block.ini 4 | 5 | [Difference mode 0 output - fun] 6 | 3 : MODE = 0 7 | 4 : INP = -10 8 | 5 : ENABLE = 1 9 | 6 : INP = 0 10 | 7 : INP = 10 11 | 8 : INP = 0 12 | 9 : INP = -10 13 | 11 : TRIG = 1 -> OUT=0, READY=1 14 | 12 : TRIG = 0 -> READY=0 15 | 15 : ENABLE = 0 16 | -------------------------------------------------------------------------------- /modules/fmc_24vio/const/fmc_24vio_impl.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # Enable on-chip pulldown for floating FMC_IN[0-7] inputs 3 | # ------------------------------------------------------------------- 4 | set_property PULLTYPE PULLDOWN [get_ports FMC_LA_P[*]] 5 | set_property PULLTYPE PULLDOWN [get_ports FMC_LA_N[*]] 6 | 7 | -------------------------------------------------------------------------------- /modules/fmc_24vio/fmc_24v_doc.rst: -------------------------------------------------------------------------------- 1 | FMC_24V - FMC 24V IO Module 2 | =========================== 3 | 4 | Fields 5 | ------ 6 | 7 | The module has bee splits into two blocks: The inputs and the outputs. 8 | 9 | .. block_fields:: modules/fmc_24vio/fmc_24vio.block.ini 10 | 11 | -------------------------------------------------------------------------------- /modules/fmc_24vio/ipmi.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | eeprom = 16-bit 3 | 4 | [Board] 5 | manufacturer: DLS 6 | product name: FMC-24V 7 | -------------------------------------------------------------------------------- /modules/fmc_24vio/ipmi_definition.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | eeprom = 16-bit 3 | 4 | [Board] 5 | manufacture date: 2011-12-08 00:00 6 | manufacturer: DLS 7 | product name: FMC-24V 8 | serial number: DCS00000000 9 | part number: FMC-24V 10 | fru file id: 11 | extra 1: Rev 1 12 | 13 | [FMC IO] 14 | module size: 0 15 | p1 size: 0 16 | p2 size: 3 17 | clkx bidir: False 18 | p1 a: 31 19 | p1 b: 0 20 | p2 a: 0 21 | p2 b: 0 22 | p1 gbt: 0 23 | p2 gbt: 0 24 | max tck: 0 25 | 26 | [VADJ] 27 | nominal v: 1.8 28 | min v: 1.1 29 | max v: 3.5 30 | pp noise: 0.05 31 | min i: 0.0 32 | max i: 2.0 33 | 34 | [3P3V] 35 | nominal v: 3.3 36 | min v: 3.15 37 | max v: 3.5 38 | pp noise: 0.05 39 | min i: 0.0 40 | max i: 3.0 41 | 42 | [12P0V] 43 | nominal v: 12.0 44 | min v: 11.4 45 | max v: 12.6 46 | pp noise: 0.05 47 | min i: 0.0 48 | max i: 1.0 49 | 50 | [VIO_B_M2C] 51 | nominal v: 0.0 52 | min v: 0.0 53 | max v: 0.0 54 | pp noise: 0.0 55 | min i: 0.0 56 | max i: 0.0 57 | standby: False 58 | 59 | [VREF_A_M2C] 60 | nominal v: 0.0 61 | min v: 0.0 62 | max v: 0.0 63 | pp noise: 0.0 64 | min i: 0.0 65 | max i: 0.0 66 | standby: False 67 | 68 | [VREF_B_M2C] 69 | nominal v: 0.0 70 | min v: 0.0 71 | max v: 0.0 72 | pp noise: 0.0 73 | min i: 0.0 74 | max i: 0.0 75 | standby: False 76 | -------------------------------------------------------------------------------- /modules/fmc_acq427/const/fmc_adc427.xdc: -------------------------------------------------------------------------------- 1 | #set_false_path -from [get_clocks clk_fpga_0] -through [get_pins -hierarchical -filter {NAME=~ "*ACQ427*SEL_CLK_SEL/O"}] -to [get_clocks clk_fpga_0] 2 | -------------------------------------------------------------------------------- /modules/fmc_acq427/const/fmc_dac427.xdc: -------------------------------------------------------------------------------- 1 | create_generated_clock -name softblocks_inst/{{ block.name }}_inst/THE_ACQ427FMC_DAC_INTERFACE/I -source [get_pins ps/FCLK_CLK0] -divide_by 2 [get_pins softblocks_inst/{{ block.name }}_inst/THE_ACQ427FMC_DAC_INTERFACE/clk_62_5M_raw_reg/Q] 2 | 3 | -------------------------------------------------------------------------------- /modules/fmc_acq427/const/fmc_dac427_impl.xdc: -------------------------------------------------------------------------------- 1 | set_clock_groups -asynchronous -group [get_clocks \ 2 | {softblocks_inst/{{ block.name }}_inst/THE_ACQ427FMC_DAC_INTERFACE/I}] 3 | 4 | -------------------------------------------------------------------------------- /modules/fmc_acq427/fmc_acq427_doc.rst: -------------------------------------------------------------------------------- 1 | FMC_ACQ427 - FMC ACQ427 Module 2 | ============================== 3 | 4 | Fields 5 | ------ 6 | 7 | The module has been split into two blocks: the inputs, which controls the ADC; 8 | and the outputs, which control the DAC. 9 | 10 | .. block_fields:: modules/fmc_acq427/fmc_acq427.block.ini 11 | 12 | Clock note 13 | ---------- 14 | 15 | The ADC runs at 1MHz 16 | -------------------------------------------------------------------------------- /modules/fmc_acq427/hdl/fmc_types.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------------------- 2 | --! @file 3 | --! @brief Local Types for the ACQ427FMC 4 | --! @author John McLean 5 | --! @date 14th June 2017 6 | --! @details 7 | --! D-TACQ Solutions Ltd Copyright 2013-2018 8 | --! 9 | 10 | --! Standard Libraries - numeric.std for all designs 11 | library ieee; 12 | use ieee.std_logic_1164.all; -- Standard Logic Functions 13 | use ieee.numeric_std.all; -- Numeric Functions for Signed / Unsigned Arithmetic 14 | 15 | --! Xilinx Primitive Library 16 | library UNISIM; 17 | use UNISIM.VComponents.all; -- Xilinx Primitives 18 | 19 | package ACQ427TYPES is 20 | 21 | constant c_MODULE_TYPE : std_logic_vector( 7 downto 0) := x"07"; -- ! This is the definition of the module 22 | constant c_MODULE_TYPE_FAST : std_logic_vector( 7 downto 0) := x"A7"; -- ! This is the definition of the module 23 | constant c_MODULE_VERSION : std_logic_vector( 7 downto 0) := x"00"; 24 | constant c_FPGA_REVISION : std_logic_vector(15 downto 0) := x"0001"; 25 | 26 | --! This is the array of Registers used as a structure for ease of VHDL entity and instantiation definition 27 | type REG_ARRAY is array(15 downto 0) of std_logic_vector(31 downto 0); 28 | 29 | end package ACQ427TYPES; 30 | -------------------------------------------------------------------------------- /modules/fmc_acq427/ipmi.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | eeprom = 16-bit 3 | 4 | [Board] 5 | manufacturer: D-TACQ Solutions 6 | product name: ACQ427ELF 7 | 8 | [VADJ] 9 | nominal v: 1.8 10 | -------------------------------------------------------------------------------- /modules/fmc_acq430/const/fmc_acq430.xdc: -------------------------------------------------------------------------------- 1 | create_generated_clock -name softblocks_inst/{{ block.name }}_inst/THE_ACQ430FMC_INTERFACE/s_CLK_GEN_CLK_reg/Q -source [get_pins ps/FCLK_CLK0] -divide_by 4 [get_pins softblocks_inst/{{ block.name }}_inst/THE_ACQ430FMC_INTERFACE/s_CLK_GEN_CLK_reg/Q] 2 | 3 | -------------------------------------------------------------------------------- /modules/fmc_acq430/const/fmc_acq430_impl.xdc: -------------------------------------------------------------------------------- 1 | set_clock_groups -asynchronous -group [get_clocks \ 2 | {softblocks_inst/{{ block.name }}_inst/THE_ACQ430FMC_INTERFACE/s_CLK_GEN_CLK_reg/Q}] 3 | -------------------------------------------------------------------------------- /modules/fmc_acq430/fmc_acq430.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: FMC ACQ430 ADC Module 3 | entity: fmc_acq430 4 | type: io 5 | interfaces: FMC 6 | constraints: const/fmc_acq430.xdc const/fmc_acq430_impl.xdc 7 | ip: fmc_acq430_ch_fifo fmc_acq430_sample_ram 8 | 9 | [VAL1] 10 | type: pos_out 11 | description: ADC Channel 1 Data 12 | scale: 4.65661287e-9 13 | units: V 14 | 15 | [VAL2] 16 | type: pos_out 17 | description: ADC Channel 2 Data 18 | scale: 4.65661287e-9 19 | units: V 20 | 21 | [VAL3] 22 | type: pos_out 23 | description: ADC Channel 3 Data 24 | scale: 4.65661287e-9 25 | units: V 26 | 27 | [VAL4] 28 | type: pos_out 29 | description: ADC Channel 4 Data 30 | scale: 4.65661287e-9 31 | units: V 32 | 33 | [VAL5] 34 | type: pos_out 35 | description: ADC Channel 5 Data 36 | scale: 4.65661287e-9 37 | units: V 38 | 39 | [VAL6] 40 | type: pos_out 41 | description: ADC Channel 6 Data 42 | scale: 4.65661287e-9 43 | units: V 44 | 45 | [VAL7] 46 | type: pos_out 47 | description: ADC Channel 7 Data 48 | scale: 4.65661287e-9 49 | units: V 50 | 51 | [VAL8] 52 | type: pos_out 53 | description: ADC Channel 8 Data 54 | scale: 4.65661287e-9 55 | units: V 56 | 57 | [TTL] 58 | type: bit_out 59 | description: C/T 5V TTL input 60 | 61 | -------------------------------------------------------------------------------- /modules/fmc_acq430/fmc_acq430_doc.rst: -------------------------------------------------------------------------------- 1 | FMC_ACQ430 - FMC ACQ430 Module 2 | ============================== 3 | 4 | Fields 5 | ------ 6 | .. block_fields:: modules/fmc_acq430/fmc_acq430.block.ini 7 | 8 | 9 | Clock note 10 | ---------- 11 | 12 | The ADC runs in High Res mode using a divisor of 5 from the main clock 13 | frequency. 14 | 15 | 125 Mhz/5/512 gives and ADC sample rate of 48.828125 kHz 16 | -------------------------------------------------------------------------------- /modules/fmc_acq430/hdl_zynq/enablable_clock_oddr.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | library unisim; 6 | use unisim.vcomponents.all; 7 | 8 | entity enablable_clock_oddr is 9 | port ( 10 | clock_i : in std_logic; 11 | clock_o : out std_logic; 12 | enable_i : in std_logic 13 | ); 14 | end enablable_clock_oddr; 15 | 16 | architecture rtl of enablable_clock_oddr is 17 | begin 18 | 19 | -- Signals to the physical ADCs 20 | cmp_ADC_SPI_CLK_ODDR : ODDR 21 | generic map( 22 | DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 23 | INIT => '0', -- Initial value for Q port ('1' or '0') 24 | SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") 25 | port map ( 26 | Q => clock_o, -- 1-bit DDR output 27 | C => clock_i, -- 1-bit clock input 28 | CE => enable_i, -- 1-bit clock enable_i input 29 | D1 => '1', -- 1-bit data input (positive edge) 30 | D2 => '0', -- 1-bit data input (negative edge) 31 | R => '0', -- 1-bit reset input 32 | S => '0' -- 1-bit set input 33 | ); 34 | 35 | end rtl; 36 | -------------------------------------------------------------------------------- /modules/fmc_acq430/hdl_zynqmp/enablable_clock_oddr.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | library unisim; 6 | use unisim.vcomponents.all; 7 | 8 | entity enablable_clock_oddr is 9 | port ( 10 | clock_i : in std_logic; 11 | clock_o : out std_logic; 12 | enable_i : in std_logic 13 | ); 14 | end enablable_clock_oddr; 15 | 16 | architecture rtl of enablable_clock_oddr is 17 | begin 18 | 19 | -- Signals to the physical ADCs 20 | cmp_ADC_SPI_CLK_ODDR : ODDRE1 21 | port map ( 22 | SR => '0', -- Active High Asynchronous Reset 23 | C => clock_i, -- 1-bit clock input 24 | Q => clock_o, -- 1-bit DDR output 25 | D1 => enable_i, -- 1-bit data input (positive edge) 26 | D2 => '0' -- 1-bit data input (negative edge) 27 | ); 28 | 29 | end rtl; 30 | -------------------------------------------------------------------------------- /modules/fmc_acq430/ipmi.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | eeprom = 16-bit 3 | 4 | [Board] 5 | Manufacturer: D-TACQ Solutions 6 | Product Name: ACQ430FMC 7 | 8 | [VADJ] 9 | Nominal V: 1.8 10 | -------------------------------------------------------------------------------- /modules/fmc_loopback/const/fmc_loopback.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # FMC Clock Timing Constraints 3 | # ------------------------------------------------------------------- 4 | create_clock -period 6.400 [get_ports FMC_CLK0_M2C_P[0]] 5 | create_clock -period 6.400 [get_ports FMC_CLK1_M2C_P[0]] 6 | 7 | -------------------------------------------------------------------------------- /modules/fmc_loopback/const/fmc_loopback_impl.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # Define asynchronous clocks 3 | # ------------------------------------------------------------------- 4 | set_clock_groups -asynchronous -group FMC_CLK0_M2C_P[0] 5 | set_clock_groups -asynchronous -group FMC_CLK1_M2C_P[0] 6 | 7 | # ------------------------------------------------------------------- 8 | # Override Differential Pairs' IOSTANDARD 9 | # ------------------------------------------------------------------- 10 | set_property IOSTANDARD LVDS [get_ports FMC_CLK0_M2C_P[0]] 11 | set_property IOSTANDARD LVDS [get_ports FMC_CLK1_M2C_P[0]] 12 | 13 | # ------------------------------------------------------------------- 14 | # Async false reset paths 15 | # ------------------------------------------------------------------- 16 | # If running into timing problems, try uncommenting the lines below ... 17 | #set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}] 18 | #set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}] 19 | #set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}] 20 | 21 | # FMC [33:17] are inputs 22 | #set_false_path -from [lrange [get_ports -regexp FMC_LA_P.*] 1 16] 23 | #set_false_path -from [lrange [get_ports -regexp FMC_LA_N.*] 1 16] 24 | 25 | -------------------------------------------------------------------------------- /modules/fmc_loopback/fmc_loopback.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: FMC Loopback Module 3 | entity: fmc_loopback 4 | type: io 5 | interfaces: FMC 6 | constraints: const/fmc_loopback.xdc const/fmc_loopback_impl.xdc 7 | extra_interface: fmc_mgt: mgt 1 8 | 9 | [LOOP_PERIOD] 10 | type: param 11 | description: Loopback toggle period for IO 12 | 13 | [FMC_PRSNT] 14 | type: read enum 15 | description: FMC present 16 | 0: FMC Disconnected 17 | 1: FMC Connected 18 | 2: FMC_PRSNT not supported 19 | 20 | [LA_P_ERROR] 21 | type: read 22 | description: LA_P loopback status 23 | 24 | [LA_N_ERROR] 25 | type: read 26 | description: LA_N loopback status 27 | 28 | [FMC_CLK0] 29 | type: read 30 | description: FMC CLK0 clock freq 31 | 32 | [FMC_CLK1] 33 | type: read 34 | description: FMC CLK1 clock freq 35 | 36 | -------------------------------------------------------------------------------- /modules/fmc_loopback/fmc_loopback_doc.rst: -------------------------------------------------------------------------------- 1 | FMC_LOOPBACK - FMC Loopback Module 2 | ================================== 3 | 4 | Fields 5 | ------ 6 | .. block_fields:: modules/fmc_loopback/fmc_loopback.block.ini 7 | -------------------------------------------------------------------------------- /modules/fmc_loopback/ipmi.ini: -------------------------------------------------------------------------------- 1 | [VADJ] 2 | max v: 3.5 3 | min v: 1.1 4 | 5 | [Board] 6 | product name: XM107 7 | manufacturer: Whizz Inc 8 | -------------------------------------------------------------------------------- /modules/fmc_x4sfp/const/fmc_x4sfp.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # FMC Clock Timing Constraints 3 | # ------------------------------------------------------------------- 4 | create_clock -period 6.400 [get_ports FMC_CLK0_M2C_P[0]] 5 | create_clock -period 6.400 [get_ports FMC_CLK1_M2C_P[0]] 6 | 7 | -------------------------------------------------------------------------------- /modules/fmc_x4sfp/const/fmc_x4sfp_impl.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # Define asynchronous clocks 3 | # ------------------------------------------------------------------- 4 | set_clock_groups -asynchronous -group FMC_CLK0_M2C_P[0] 5 | set_clock_groups -asynchronous -group FMC_CLK1_M2C_P[0] 6 | 7 | # ------------------------------------------------------------------- 8 | # Override Differential Pairs' IOSTANDARD 9 | # ------------------------------------------------------------------- 10 | set_property IOSTANDARD LVDS [get_ports FMC_CLK0_M2C_P[0]] 11 | set_property IOSTANDARD LVDS [get_ports FMC_CLK1_M2C_P[0]] 12 | 13 | -------------------------------------------------------------------------------- /modules/fmc_x4sfp/fmc_x4sfp.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: HPC-FMC card with 4 SFP+ ports 3 | entity: fmc_x4sfp 4 | type: io 5 | interfaces: FMC 6 | constraints: const/fmc_x4sfp.xdc const/fmc_x4sfp_impl.xdc 7 | extra_interface: fmc_mgt: mgt 4 8 | 9 | [FMC_PRSNT] 10 | type: read enum 11 | description: FMC present 12 | 0: FMC Disconnected 13 | 1: FMC Connected 14 | 2: FMC_PRSNT not supported 15 | 16 | [FMC_I2C_MUX] 17 | description: MUX selector for FMC I2C 18 | type: param enum 19 | 0: SFP1 20 | 1: SFP2 21 | 2: SFP3 22 | 3: SFP4 23 | 4: Si570 24 | 25 | [FMC_CLK0] 26 | type: read 27 | description: FMC CLK0 clock freq (if supported) 28 | 29 | [FMC_CLK1] 30 | type: read 31 | description: FMC CLK1 clock freq (if supported) 32 | 33 | -------------------------------------------------------------------------------- /modules/incenc/hdl: -------------------------------------------------------------------------------- 1 | ../../common/hdl/encoders -------------------------------------------------------------------------------- /modules/incenc/incenc.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Incremental encoder 3 | entity: incenc 4 | 5 | [PROTOCOL] 6 | type: param enum 7 | description: Type of absolute/incremental protocol 8 | 0: Quadrature 9 | 1: Step/Direction 10 | 11 | [BITS] 12 | type: param uint 63 13 | description: Number of bits 14 | 15 | [LSB_DISCARD] 16 | type: param uint 31 17 | description: Number of LSB bits to discard 18 | 19 | [MSB_DISCARD] 20 | type: param uint 31 21 | description: Number of MSB bits to discard 22 | 23 | [SETP] 24 | type: write int 25 | description: Set point 26 | 27 | [RST_ON_Z] 28 | type: param bit 29 | description: Zero position on Z rising edge 30 | 31 | ; [A] 32 | ; type: bit_out 33 | ; description: Quadrature A if in incremental mode 34 | 35 | ; [B] 36 | ; type: bit_out 37 | ; description: Quadrature B if in incremental mode 38 | 39 | ; [Z] 40 | ; type: bit_out 41 | ; description: Z index channel if in incremental mode 42 | 43 | [CONN] 44 | type: bit_out 45 | description: Signal detected 46 | 47 | [HOMED] 48 | type: read bit 49 | description: Quadrature homed status 50 | 51 | [QPERIOD] 52 | type: param time 53 | description: Quadrature prescaler 54 | 55 | [QSTATE] 56 | type: read enum 57 | description: Quadrature state 58 | 0: Disabled 59 | 1: At position 60 | 2: Slewing 61 | 62 | [HEALTH] 63 | type: read enum 64 | description: Table status 65 | 0: OK 66 | 1: Linkup error (=not CONN) 67 | 2: Timeout error (for BISS, monitor SSI) 68 | 3: CRC error (for BISS) 69 | 4: Error bit active (for BISS) 70 | 5: ENDAT not implemented 71 | 6: Protocol readback error 72 | 73 | [VAL] 74 | type: pos_out 75 | description: Current position 76 | 77 | -------------------------------------------------------------------------------- /modules/incenc/incenc_doc.rst: -------------------------------------------------------------------------------- 1 | INENC - Input encoder 2 | ===================== 3 | The INENC block handles the encoder input signals 4 | 5 | Fields 6 | ------ 7 | 8 | .. block_fields:: modules/inenc/inenc.block.ini 9 | -------------------------------------------------------------------------------- /modules/inenc/hdl: -------------------------------------------------------------------------------- 1 | ../../common/hdl/encoders/ -------------------------------------------------------------------------------- /modules/inenc/inenc_doc.rst: -------------------------------------------------------------------------------- 1 | INENC - Input encoder 2 | ===================== 3 | The INENC block handles the encoder input signals 4 | 5 | Fields 6 | ------ 7 | 8 | .. block_fields:: modules/inenc/inenc.block.ini 9 | -------------------------------------------------------------------------------- /modules/lut/lut.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Lookup table 3 | entity: lut 4 | 5 | [INPA] 6 | type: bit_mux 7 | description: Input A 8 | 9 | [INPB] 10 | type: bit_mux 11 | description: Input B 12 | 13 | [INPC] 14 | type: bit_mux 15 | description: Input C 16 | 17 | [INPD] 18 | type: bit_mux 19 | description: Input D 20 | 21 | [INPE] 22 | type: bit_mux 23 | description: Input E 24 | 25 | [TYPEA] 26 | type: param enum 27 | description: Source of the value of A for calculation 28 | 0: Input-Level 29 | 1: Pulse-On-Rising-Edge 30 | 2: Pulse-On-Falling-Edge 31 | 3: Pulse-On-Either-Edge 32 | 33 | [TYPEB] 34 | type: param enum 35 | description: Source of the value of B for calculation 36 | 0: Input-Level 37 | 1: Pulse-On-Rising-Edge 38 | 2: Pulse-On-Falling-Edge 39 | 3: Pulse-On-Either-Edge 40 | 41 | [TYPEC] 42 | type: param enum 43 | description: Source of the value of C for calculation 44 | 0: Input-Level 45 | 1: Pulse-On-Rising-Edge 46 | 2: Pulse-On-Falling-Edge 47 | 3: Pulse-On-Either-Edge 48 | 49 | [TYPED] 50 | type: param enum 51 | description: Source of the value of D for calculation 52 | 0: Input-Level 53 | 1: Pulse-On-Rising-Edge 54 | 2: Pulse-On-Falling-Edge 55 | 3: Pulse-On-Either-Edge 56 | 57 | [TYPEE] 58 | type: param enum 59 | description: Source of the value of E for calculation 60 | 0: Input-Level 61 | 1: Pulse-On-Rising-Edge 62 | 2: Pulse-On-Falling-Edge 63 | 3: Pulse-On-Either-Edge 64 | 65 | [FUNC] 66 | type: param lut 67 | description: Input func 68 | 69 | [OUT] 70 | type: bit_out 71 | description: Lookup table output 72 | -------------------------------------------------------------------------------- /modules/lvdsin/hdl/lvdsin_top.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- PandA Motion Project - 2016 3 | -- Diamond Light Source, Oxford, UK 4 | -- SOLEIL Synchrotron, GIF-sur-YVETTE, France 5 | -- 6 | -- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) 7 | -------------------------------------------------------------------------------- 8 | -- 9 | -- Description : Interface to external LVDS inputs. 10 | -- LVDS inputs are registered before assigned to System Bus. 11 | -- 12 | -------------------------------------------------------------------------------- 13 | 14 | library ieee; 15 | use ieee.std_logic_1164.all; 16 | use ieee.numeric_std.all; 17 | 18 | library work; 19 | use work.top_defines.all; 20 | use work.addr_defines.all; 21 | 22 | entity lvdsin_top is 23 | port ( 24 | -- Clocks and Resets 25 | clk_i : in std_logic; 26 | -- LVDS I/O 27 | pad_i : in std_logic_vector(LVDSIN_NUM-1 downto 0); 28 | val_o : out std_logic_vector(LVDSIN_NUM-1 downto 0) 29 | ); 30 | end lvdsin_top; 31 | 32 | architecture rtl of lvdsin_top is 33 | 34 | begin 35 | 36 | -- Syncroniser for each input 37 | LVDSIN_GEN : FOR I IN 0 TO LVDSIN_NUM-1 GENERATE 38 | 39 | syncer : entity work.IDDR_sync_bit 40 | port map ( 41 | clk_i => clk_i, 42 | bit_i => pad_i(I), 43 | bit_o => val_o(I) 44 | ); 45 | 46 | END GENERATE; 47 | 48 | end rtl; 49 | 50 | 51 | -------------------------------------------------------------------------------- /modules/lvdsin/lvdsin.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: LVDS input 3 | entity: lvdsin 4 | 5 | [VAL] 6 | type: bit_out 7 | description: LVDS input value -------------------------------------------------------------------------------- /modules/lvdsin/lvdsin_doc.rst: -------------------------------------------------------------------------------- 1 | LVDSIN - LVDS Input 2 | =================== 3 | 4 | The LVDSIN block handles the signals from the LVDS Input connectors 5 | 6 | Fields 7 | ------ 8 | 9 | .. block_fields:: modules/lvdsin/lvdsin.block.ini 10 | -------------------------------------------------------------------------------- /modules/lvdsout/lvdsout.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: LVDS output 3 | entity: lvdsout 4 | 5 | [QUARTER_DELAY] 6 | type: param uint 3 7 | description: Number of 1/4 ticks to delay (range 0-3) 8 | if-option: fine_delay 9 | 10 | [FINE_DELAY] 11 | type: param uint 31 12 | description: Fine delay (range 0-31) 13 | if-option: fine_delay 14 | 15 | [VAL] 16 | type: bit_mux 17 | description: LVDS output value 18 | -------------------------------------------------------------------------------- /modules/lvdsout/lvdsout_doc.rst: -------------------------------------------------------------------------------- 1 | LVDSOUT - LVDS Output 2 | ===================== 3 | 4 | The LVDSOUT block handles the signals to the LVDS Output connectors 5 | 6 | Fields 7 | ------ 8 | 9 | .. block_fields:: modules/lvdsout/lvdsout.block.ini 10 | -------------------------------------------------------------------------------- /modules/outenc/hdl: -------------------------------------------------------------------------------- 1 | ../../common/hdl/encoders/ -------------------------------------------------------------------------------- /modules/outenc/outenc_doc.rst: -------------------------------------------------------------------------------- 1 | OUTENC - Output encoder 2 | ======================= 3 | The OUTENC block handles the encoder output signals 4 | 5 | Fields 6 | ------ 7 | 8 | .. block_fields:: modules/outenc/outenc.block.ini 9 | -------------------------------------------------------------------------------- /modules/pandabrick_test/pandabrick_test.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Test block for PandABrick 3 | entity: test_regs 4 | 5 | [TEST_VAL] 6 | type: read int 7 | description: Test Value 8 | 9 | -------------------------------------------------------------------------------- /modules/pcomp/pcomp.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Position compare 3 | entity: pcomp 4 | 5 | [ENABLE] 6 | type: bit_mux 7 | description: Stop on falling edge, reset and enable on rising edge 8 | 9 | [INP] 10 | type: pos_mux 11 | description: Position data from position-data bus 12 | 13 | [PRE_START] 14 | type: param int 15 | description: INP must be this far from START before waiting for START 16 | 17 | [START] 18 | type: param int 19 | description: Pulse absolute/relative start position value 20 | 21 | [WIDTH] 22 | type: param int 23 | description: The relative distance between a rising and falling edge 24 | 25 | [STEP] 26 | type: param int 27 | description: The relative distance between successive rising edges 28 | 29 | [PULSES] 30 | type: param 31 | description: The number of pulses to produce, 0 means infinite 32 | 33 | [RELATIVE] 34 | type: param enum 35 | description: If 1 then START is relative to the position of INP at enable 36 | 0: Absolute 37 | 1: Relative 38 | 39 | [DIR] 40 | type: param enum 41 | description: Direction to apply all relative offsets to 42 | 0: Positive 43 | 1: Negative 44 | 2: Either 45 | 46 | [ACTIVE] 47 | type: bit_out 48 | description: Active output is high while block is in operation 49 | 50 | [OUT] 51 | type: bit_out 52 | description: Output pulse train 53 | 54 | [HEALTH] 55 | type: read enum 56 | description: Error details if anything goes wrong 57 | 0: OK 58 | 1: Position jumped by more than STEP 59 | 2: Can't guess DIR when RELATIVE and PRE_START=0 and START=0 60 | 61 | [PRODUCED] 62 | type: read 63 | description: The number of pulses produced 64 | 65 | [STATE] 66 | type: read enum 67 | description: The internal statemachine state 68 | 0: WAIT_ENABLE 69 | 1: WAIT_DIR 70 | 2: WAIT_PRE_START 71 | 3: WAIT_RISING 72 | 4: WAIT_FALLING 73 | -------------------------------------------------------------------------------- /modules/pgen/PGEN_1000.txt: -------------------------------------------------------------------------------- 1 | POS 2 | 10 3 | 11 4 | 12 5 | 13 6 | 14 7 | 15 8 | 16 9 | 21 10 | 52 11 | 32 12 | -------------------------------------------------------------------------------- /modules/pgen/pgen.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Position generator 3 | entity: pgen 4 | type: dma 5 | ip: fifo_1K32 6 | 7 | [ENABLE] 8 | type: bit_mux 9 | description: Halt on falling edge, reset and enable on rising 10 | 11 | [TRIG] 12 | type: bit_mux 13 | description: Trigger a sample to be produced 14 | 15 | [TABLE] 16 | type: table 17 | description: Table of positions to be output 18 | wstb: True 19 | 31:0 POSITION int 20 | The position to set OUT to on trigger 21 | 22 | [REPEATS] 23 | type: param 24 | description: Number of times the table will repeat 25 | 26 | [ACTIVE] 27 | type: bit_out 28 | description: High when output is being produced from the table 29 | 30 | [OUT] 31 | type: pos_out 32 | description: Current sample 33 | 34 | [HEALTH] 35 | type: read enum 36 | description: Table status 37 | 0: OK 38 | 1: Table not ready 39 | 3: DMA overrun 40 | 41 | 42 | -------------------------------------------------------------------------------- /modules/pgen/pgen.timing.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Timing diagrams for the pgen block 3 | scope: pgen.block.ini 4 | 5 | [Normal operation] 6 | 3 : REPEATS=2 7 | 4 : TABLE_ADDRESS=PGEN_1000.txt 8 | 5 : TABLE_LENGTH=40 9 | 6 : ENABLE=1 -> ACTIVE=1 10 | 10 : TRIG=1 -> OUT=10 11 | 11 : TRIG=0 12 | 12 : TRIG=1 -> OUT=11 13 | 13 : TRIG=0 14 | 14 : TRIG=1 -> OUT=12 15 | 15 : TRIG=0 16 | 16 : TRIG=1 -> OUT=13 17 | 17 : TRIG=0 18 | 18 : TRIG=1 -> OUT=14 19 | 19 : TRIG=0 20 | 20 : TRIG=1 -> OUT=15 21 | 21 : TRIG=0 22 | 22 : TRIG=1 -> OUT=16 23 | 23 : TRIG=0 24 | 24 : TRIG=1 -> OUT=21 25 | 25 : TRIG=0 26 | 26 : TRIG=1 -> OUT=52 27 | 27 : TRIG=0 28 | 28 : TRIG=1 -> OUT=32 29 | 29 : TRIG=0 30 | 30 : TRIG=1 -> OUT=10 31 | 31 : TRIG=0 32 | 32 : TRIG=1 -> OUT=11 33 | 33 : TRIG=0 34 | 34 : TRIG=1 -> OUT=12 35 | 35 : TRIG=0 36 | 36 : TRIG=1 -> OUT=13 37 | 37 : TRIG=0 38 | 38 : TRIG=1 -> OUT=14 39 | 39 : TRIG=0 40 | 40 : TRIG=1 -> OUT=15 41 | 41 : TRIG=0 42 | 42 : TRIG=1 -> OUT=16 43 | 43 : TRIG=0 44 | 44 : TRIG=1 -> OUT=21 45 | 45 : TRIG=0 46 | 46 : TRIG=1 -> OUT=52 47 | 47 : TRIG=0 48 | 48 : TRIG=1 -> OUT=32, ACTIVE=0 49 | 49 : TRIG=0 50 | 50 : TRIG=1 51 | 51 : TRIG=0 52 | 53 | -------------------------------------------------------------------------------- /modules/pgen/pgen_doc.rst: -------------------------------------------------------------------------------- 1 | PGEN - Position Generator 2 | ========================= 3 | The position generator block produces an output position which is pre-defined in 4 | a table 5 | 6 | Fields 7 | ------ 8 | 9 | .. block_fields:: modules/pgen/pgen.block.ini 10 | 11 | 12 | Normal operation 13 | ----------------- 14 | The output pulse will be generated regardless of the direction of the INP data 15 | 16 | .. timing_plot:: 17 | :path: modules/pgen/pgen.timing.ini 18 | :section: Normal operation 19 | -------------------------------------------------------------------------------- /modules/pmacenc/hdl: -------------------------------------------------------------------------------- 1 | ../../common/hdl/encoders -------------------------------------------------------------------------------- /modules/pmacenc/pmacenc.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | entity: pmacenc 3 | description: Pmac encoder 4 | 5 | [ENABLE] 6 | type: bit_mux 7 | description: Halt of falling edge, reset and enable on rising 8 | 9 | [GENERATOR_ERROR] 10 | type: param enum 11 | description: generate error on output 12 | 0: No 13 | 1: BISS frame error bit 14 | 15 | [DATA] 16 | type: bit_mux 17 | description: Data output to master encoder 18 | 19 | [PROTOCOL] 20 | type: param enum 21 | description: Type of absolute/incremental protocol 22 | 0: Passthrough - UVWT 23 | 1: Passthrough - Absolute 24 | 2: Read - Step/Direction 25 | 3: Generate - SSI 26 | 4: Generate - enDat 27 | 5: Generate - Biss 28 | 29 | [ENCODING] 30 | type: param enum 31 | description: Position encoding (for absolute encoders) 32 | 0: Unsigned Binary 33 | 1: Unsigned Gray 34 | 2: Signed Binary 35 | 3: Signed Gray 36 | 37 | [BITS] 38 | type: param uint 32 39 | description: Number of bits 40 | 41 | [CLK] 42 | type: bit_out 43 | description: Clock input from encoder 44 | 45 | ; [STEP] 46 | ; type: bit_out 47 | ; description: STEP input from encoder 48 | 49 | ; [DIR] 50 | ; type: bit_out 51 | ; description: Direction input from encoder 52 | 53 | [VAL] 54 | type: pos_mux 55 | description: Input for position (all other protocols) 56 | 57 | [HEALTH] 58 | type: read enum 59 | description: Table status 60 | 0: OK 61 | 1: Biss timeout error (did not received right number of sck for biss frame) 62 | 2: ENDAT not implemented 63 | 3: OUTENC unused (MONITOR mode) 64 | 4: Protocol readback error 65 | -------------------------------------------------------------------------------- /modules/pmacenc/pmacenc_doc.rst: -------------------------------------------------------------------------------- 1 | PMACENC - Pmac encoder 2 | ====================== 3 | The PMACENC block handles the pmac encoder signals 4 | 5 | Fields 6 | ------ 7 | 8 | .. block_fields:: modules/pmacenc/pmacenc.block.ini 9 | -------------------------------------------------------------------------------- /modules/posenc/posenc.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Quadrature and step/direction encoder 3 | entity: posenc 4 | 5 | [ENABLE] 6 | type: bit_mux 7 | description: Halt on falling edge, reset and enable on rising 8 | 9 | [INP] 10 | type: pos_mux 11 | description: Output position 12 | 13 | [PERIOD] 14 | type: param time 15 | description: Minimum time between Quadrature transitions of step pulses 16 | wstb: True 17 | 18 | [PROTOCOL] 19 | type:param enum 20 | description: Quadrature or step/direction 21 | 0: Quadrature 22 | 1: Step/Direction 23 | 24 | [A] 25 | type: bit_out 26 | description: Quadrature A/Step output 27 | 28 | [B] 29 | type: bit_out 30 | description: Quadrature B/Direction output 31 | 32 | [STATE] 33 | type: read enum 34 | description: State of quadrature output 35 | 0: Disabled 36 | 1: At position 37 | 2: Slewing 38 | 39 | -------------------------------------------------------------------------------- /modules/pulse/pulse.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: One-shot pulse delay and stretch 3 | entity: pulse 4 | ip: pulse_queue 5 | 6 | [ENABLE] 7 | type: bit_mux 8 | description: Reset on falling edge, enable on rising 9 | 10 | [TRIG] 11 | type: bit_mux 12 | description: Input pulse train 13 | 14 | [DELAY] 15 | type: time 16 | description: Output pulse delay (0 for no delay) 17 | wstb: True 18 | 19 | [WIDTH] 20 | type: time 21 | description: Output pulse width (0 for input pulse width) 22 | wstb: True 23 | 24 | [PULSES] 25 | type: param 26 | description: The number of pulses to produce on each trigger, 0 means 1 27 | wstb: True 28 | 29 | [STEP] 30 | type: time 31 | description: If pulses > 1, the time between successive pulse rising edges 32 | wstb: True 33 | 34 | [TRIG_EDGE] 35 | type: param enum 36 | description: INP trigger edge 37 | wstb: True 38 | 0: Rising 39 | 1: Falling 40 | 2: Either 41 | 42 | [OUT] 43 | type: bit_out 44 | description: Output pulse train 45 | 46 | [QUEUED] 47 | type: read uint 1023 48 | description: Length of the delay queue 49 | 50 | [DROPPED] 51 | type: read 52 | description: Number of pulses not produced because of an ERR condition 53 | -------------------------------------------------------------------------------- /modules/qdec/hdl/README.txt: -------------------------------------------------------------------------------- 1 | All hdl code for qdec has now been moved to common 2 | -------------------------------------------------------------------------------- /modules/qdec/qdec.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Quadrature decoder 3 | entity: qdec 4 | 5 | [LINKUP_INCR] 6 | type: param bit 7 | description: link up incremental coder signal 8 | 9 | [A] 10 | type: bit_mux 11 | description: Quadrature A 12 | 13 | [B] 14 | type: bit_mux 15 | description: Quadrature B 16 | 17 | [Z] 18 | type: bit_mux 19 | description: Z index channel 20 | 21 | [RST_ON_Z] 22 | type: param bit 23 | description: Zero position on Z rising edge 24 | 25 | [SETP] 26 | type: write int 27 | description: Set point 28 | wstb: True 29 | 30 | [HOMED] 31 | type: read bit 32 | description: Quadrature homed status 33 | 34 | [OUT] 35 | type: pos_out 36 | description: Output position 37 | -------------------------------------------------------------------------------- /modules/qdec/qdec_doc.rst: -------------------------------------------------------------------------------- 1 | QDEC - Quadrature Decoder 2 | ========================= 3 | The QDEC block handles the encoder Decoding 4 | 5 | Fields 6 | ------ 7 | 8 | .. block_fields:: modules/qdec/qdec.block.ini 9 | 10 | 11 | Counting 12 | -------- 13 | 14 | The quadrature decoder counts, incrementing at each rising or falling edge of 15 | the sequence. If the sequence is reversed the count will decrease at each edge. 16 | The initial value is set to the value of the SETP input. 17 | 18 | .. timing_plot:: 19 | :path: modules/qdec/qdec_documentation.timing.ini 20 | :section: No Set Point 21 | 22 | .. timing_plot:: 23 | :path: modules/qdec/qdec_documentation.timing.ini 24 | :section: Up then Down 25 | 26 | Resetting 27 | --------- 28 | 29 | Whilst counting, it can be reset to '0' on while the Z input is high, provided 30 | that this functionality is enabled by setting the RST_ON_Z input to '1'. If the 31 | SETP input is changed the count value changes to the new value. 32 | 33 | .. timing_plot:: 34 | :path: modules/qdec/qdec_documentation.timing.ini 35 | :section: Up then down with reset and change of Set Point 36 | 37 | Limitations 38 | ----------- 39 | 40 | The block can continue to count when there is not a constant period between the 41 | pulses. 42 | 43 | .. timing_plot:: 44 | :path: modules/qdec/qdec_documentation.timing.ini 45 | :section: Variable quadrature period 46 | 47 | The output takes three clock pulses to update. If the inputs are changing faster 48 | than this, inputs can be lost. 49 | 50 | .. timing_plot:: 51 | :path: modules/qdec/qdec_documentation.timing.ini 52 | :section: Faster input than output 53 | -------------------------------------------------------------------------------- /modules/qdec/qdec_functionality.timing.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Functionality timing diagrams for the qdec block 3 | scope: qdec.block.ini 4 | 5 | [count below zero] 6 | 7 | 3 : B=1, LINKUP_INCR=1 8 | 5 : A=1 -> OUT=-1, HOMED=0 9 | 7 : B=0 -> OUT=-2 10 | 9 : A=0 -> OUT=-3 11 | 11 : B=1 -> OUT=-4 12 | 13 : A=1 -> OUT=-5 13 | 15 : B=0 -> OUT=-6 14 | 17 : A=0 -> OUT=-7 15 | 19 : -> OUT=-8 16 | -------------------------------------------------------------------------------- /modules/seq/hdl/sequencer_prescaler.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- File: prescaler.vhd 3 | -- Desc: A simple 32-bit prescaler. 4 | -- 5 | -------------------------------------------------------------------------------- 6 | library ieee; 7 | use ieee.std_logic_1164.all; 8 | use ieee.numeric_std.all; 9 | 10 | entity sequencer_prescaler is 11 | port ( 12 | clk_i : in std_logic; 13 | reset_i : in std_logic; 14 | PERIOD : in std_logic_vector(31 downto 0); 15 | pulse_o : out std_logic 16 | ); 17 | end sequencer_prescaler; 18 | 19 | architecture rtl of sequencer_prescaler is 20 | 21 | constant c_zeros : unsigned(31 downto 0) := X"00000000"; 22 | 23 | signal clk_cnt : unsigned(31 downto 0) := (others => '0'); 24 | signal period_rollover : unsigned(31 downto 0); 25 | 26 | begin 27 | 28 | period_rollover <= c_zeros when (unsigned(PERIOD) < 1) else unsigned(PERIOD) - 1; 29 | 30 | pulse_o <= '1' when (clk_cnt = period_rollover) else '0'; 31 | 32 | -- 33 | -- Generate QENC clk defined by the prescaler 34 | -- 35 | qenc_clk_gen : process(clk_i) 36 | begin 37 | if rising_edge(clk_i) then 38 | if (reset_i = '1') then 39 | clk_cnt <= (others => '0'); 40 | else 41 | if (clk_cnt = period_rollover) then 42 | clk_cnt <= (others => '0'); 43 | else 44 | clk_cnt <= clk_cnt + 1; 45 | end if; 46 | end if; 47 | end if; 48 | end process; 49 | 50 | end rtl; 51 | -------------------------------------------------------------------------------- /modules/sfp_eventr/const/sfp_event_receiver_impl.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # SFP MGT constraint 3 | # ------------------------------------------------------------------- 4 | 5 | set_property LOC ${{ block.site_LOC }}_LOC \ 6 | [get_cells softblocks_inst/{{ block.name }}_inst/sfpgtx_event_receiver_inst/event_receiver_mgt_inst/U0/event_receiver_mgt_i/gt0_event_receiver_mgt_i/gtxe2_i] 7 | 8 | # ------------------------------------------------------------------- 9 | # Define asynchronous clocks 10 | # ------------------------------------------------------------------- 11 | set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks \ 12 | {softblocks_inst/{{ block.name }}_inst/sfpgtx_event_receiver_inst/event_receiver_mgt_inst/U0/event_receiver_mgt_i/gt0_event_receiver_mgt_i/gtxe2_i/RXOUTCLK}] 13 | 14 | -------------------------------------------------------------------------------- /modules/sfp_eventr/sfp_dls_eventr_doc.rst: -------------------------------------------------------------------------------- 1 | SFP_DLS_EVENTR - SFP Event Receiver Module 2 | ========================================== 3 | 4 | Fields 5 | ------ 6 | .. block_fields:: modules/sfp_eventr/sfp_dls_eventr.block.ini -------------------------------------------------------------------------------- /modules/sfp_loopback/const/sfp_loopback_impl.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # SFP Loopback MGT constraints 3 | # ------------------------------------------------------------------- 4 | 5 | set_property LOC ${{ block.site_LOC }}_LOC \ 6 | [get_cells softblocks_inst/{{ block.name }}_inst/sfpgtx_exdes_i/sfpgtx_support_i/sfpgtx_init_i/U0/sfpgtx_i/gt0_sfpgtx_i/gtxe2_i] 7 | 8 | 9 | # ------------------------------------------------------------------- 10 | # Define asynchronous clocks 11 | # ------------------------------------------------------------------- 12 | set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks \ 13 | {softblocks_inst/{{ block.name }}_inst/sfpgtx_exdes_i/sfpgtx_support_i/sfpgtx_init_i/U0/sfpgtx_i/gt0_sfpgtx_i/gtxe2_i/TXOUTCLK}] 14 | 15 | -------------------------------------------------------------------------------- /modules/sfp_loopback/sfp_loopback.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: SFP Block Status 3 | entity: sfp_loopback 4 | type: io 5 | interfaces: MGT 6 | constraints: const/sfp_loopback_impl.xdc 7 | otherconst: mgt_pins 8 | ip: sfpgtx 9 | 10 | [SOFT_RESET] 11 | type: write action 12 | description: GTX Soft Reset 13 | 14 | [SFP_LOS] 15 | type: read 16 | description: SFP Loss Of Signal (from SFP module) 17 | 18 | [LINK_UP] 19 | type: read 20 | description: GTX link status 21 | 22 | [ERROR_COUNT] 23 | type: read 24 | description: GTX error count 25 | 26 | [SFP_CLK] 27 | type: read 28 | description: SFP clock freq 29 | 30 | [SFP_MAC_LO] 31 | type: read 32 | description: MAC low in integer value bit 23:0 33 | 34 | [SFP_MAC_HI] 35 | type: read 36 | description: MAC high in integer value bit 47:24 37 | -------------------------------------------------------------------------------- /modules/sfp_loopback/sfp_loopback_doc.rst: -------------------------------------------------------------------------------- 1 | SFP_LOOPBACK- SFP Loopback Module 2 | ================================= 3 | 4 | Fields 5 | ------ 6 | .. block_fields:: modules/sfp_loopback/sfp_loopback.block.ini -------------------------------------------------------------------------------- /modules/sfp_panda_sync/const/zynq/sfp_panda_sync_impl.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # SFP MGT constraint 3 | # ------------------------------------------------------------------- 4 | 5 | set_property LOC ${{ block.site_LOC }}_LOC \ 6 | [get_cells softblocks_inst/{{ block.name }}_inst/sfp_panda_sync_mgt_interface_inst/sfp_panda_sync_i/U0/sfp_panda_sync_i/gt0_sfp_panda_sync_i/gtxe2_i] 7 | 8 | # ------------------------------------------------------------------- 9 | # Define asynchronous clocks 10 | # ------------------------------------------------------------------- 11 | set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks \ 12 | {softblocks_inst/{{ block.name }}_inst/sfp_panda_sync_mgt_interface_inst/sfp_panda_sync_i/U0/sfp_panda_sync_i/gt0_sfp_panda_sync_i/gtxe2_i/TXOUTCLK}] 13 | 14 | set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks \ 15 | {softblocks_inst/{{ block.name }}_inst/sfp_panda_sync_mgt_interface_inst/sfp_panda_sync_i/U0/sfp_panda_sync_i/gt0_sfp_panda_sync_i/gtxe2_i/RXOUTCLK}] 16 | 17 | -------------------------------------------------------------------------------- /modules/sfp_panda_sync/hdl/sim/run_xsim_rx.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/sh 2 | 3 | VIVADO=/dls_sw/FPGA/Xilinx/Vivado/2022.2 4 | 5 | . $VIVADO/settings64.sh 6 | 7 | mkdir -p build && cd build 8 | 9 | xvhdl ../../../../../common/hdl/sync_bit.vhd && 10 | xvhdl -2008 ../../sfp_panda_sync_receiver.vhd ../pandaSync_rx_TB.vhd && 11 | xelab -debug typical pandaSync_rx_TB && 12 | xsim pandaSync_rx_TB -gui --autoloadwcfg -t ../xsim.tcl 13 | 14 | -------------------------------------------------------------------------------- /modules/sfp_panda_sync/hdl/sim/run_xsim_tx.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/sh 2 | 3 | VIVADO=/dls_sw/FPGA/Xilinx/Vivado/2022.2 4 | 5 | . $VIVADO/settings64.sh 6 | 7 | mkdir -p build && cd build 8 | 9 | xvhdl ../../../../../common/hdl/sync_bit.vhd && 10 | xvhdl -2008 ../../sfp_panda_sync_transmit.vhd ../pandaSync_tx_TB.vhd && 11 | xelab -debug typical pandaSync_tx_TB && 12 | xsim pandaSync_tx_TB -gui --autoloadwcfg -t ../xsim.tcl 13 | 14 | -------------------------------------------------------------------------------- /modules/sfp_panda_sync/hdl/sim/xsim.tcl: -------------------------------------------------------------------------------- 1 | #open_wave_config {/scratch/clm61942/PandA_tmp/fmc_panda_sync/sync-fix/PandABlocks-FPGA/modules/sfp_panda_sync/hdl/sim/build/work.pandaSync_tx_TB_work.glbl.wcfg} 2 | #add_force /pandaSync_tx_TB/uut/wren_low 1 496 -cancel_after 696 3 | #add_force /pandaSync_tx_TB/uut/rden_low 1 896 -cancel_after 1096 4 | add_force /pandaSync_rx_TB/uut/rx_link_ok 1 100 5 | run all 6 | 7 | -------------------------------------------------------------------------------- /modules/sfp_panda_sync/sfp_panda_sync_doc.rst: -------------------------------------------------------------------------------- 1 | SFP_PANDA_SYNC - Synchronize data between 2 PandAs 2 | ================================================== 3 | 4 | Fields 5 | ------ 6 | .. block_fields:: modules/sfp_panda_sync/sfp_panda_sync.block.ini -------------------------------------------------------------------------------- /modules/sfp_udpontrig/const/sfp_udpontrig_impl.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # SFP MGTs - Bank 112 3 | # ------------------------------------------------------------------- 4 | 5 | set_property LOC ${{ block.site_LOC }}_LOC \ 6 | [get_cells softblocks_inst/{{ block.name }}_inst/SFP_UDP_Complete_i/eth_phy_i/core_support_i/pcs_pma_i/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i] 7 | 8 | #----------------------------------------------------------- 9 | # GMII Tx Elastic Buffer Constraints - 10 | #----------------------------------------------------------- 11 | 12 | # Control Gray Code delay and skew across clock boundary 13 | set_false_path -to [get_pins -hier -filter {name =~ softblocks_inst/{{ block.name }}_inst/SFP_UDP_Complete_i/eth_phy_i/tx_elastic_buffer_inst/reclock_rd_addrgray*/data_sync*/D}] 14 | set_false_path -to [get_pins -hier -filter {name =~ softblocks_inst/{{ block.name }}_inst/SFP_UDP_Complete_i/eth_phy_i/tx_elastic_buffer_inst/reclock_wr_addrgray*/data_sync*/D}] 15 | 16 | set_false_path -to [get_pins -hier -filter {name =~ softblocks_inst/{{ block.name }}_inst/SFP_UDP_Complete_i/eth_phy_i/*/*reset_sync*/PRE }] 17 | set_false_path -to [get_pins -hier -filter {name =~ softblocks_inst/{{ block.name }}_inst/SFP_UDP_Complete_i/core_resets_i/pma_reset_pipe_reg*/PRE}] 18 | set_false_path -to [get_pins -hier -filter {name =~ softblocks_inst/{{ block.name }}_inst/SFP_UDP_Complete_i/core_resets_i/pma_reset_pipe*[0]/D}] 19 | 20 | -------------------------------------------------------------------------------- /modules/sfp_udpontrig/sfp_udpontrig_doc.rst: -------------------------------------------------------------------------------- 1 | SFP_UDPONTRIG - SFP UDP on trig Module 2 | ====================================== 3 | This module, when started, can generate UDP broadcast frames on the rising edge on input trigger. The IPv4 ICMP ping protocol is also implemented in this module which can accept 0 to 256 Bytes ICMP payload size. 4 | 5 | Fields 6 | ------ 7 | .. block_fields:: modules/sfp_udpontrig/sfp_udpontrig.block.ini -------------------------------------------------------------------------------- /modules/srgate/srgate.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Set reset gate 3 | entity: srgate 4 | 5 | [ENABLE] 6 | type: bit_mux 7 | description: Whether to listen to SET/RST events 8 | 9 | [SET] 10 | type: bit_mux 11 | description: A falling/rising edge sets the output to 1 12 | 13 | [RST] 14 | type: bit_mux 15 | description: a falling/rising edge resets the output to 0 16 | 17 | [WHEN_DISABLED] 18 | type: param enum 19 | description: What to do with the output when Enable is low 20 | 0: Set output low 21 | 1: Set output high 22 | 2: Keep current output 23 | 24 | [SET_EDGE] 25 | type: param enum 26 | description: Output set edge 27 | 0: Rising 28 | 1: Falling 29 | 2: Either 30 | 31 | [RST_EDGE] 32 | type: param enum 33 | description: Output reset edge 34 | 0: Rising 35 | 1: Falling 36 | 2: Either 37 | 38 | [FORCE_SET] 39 | type: write action 40 | description: Set output to 1 41 | wstb: True 42 | 43 | [FORCE_RST] 44 | type: write action 45 | description: Reset output to 0 46 | wstb: True 47 | 48 | [OUT] 49 | type: bit_out 50 | description: output value 51 | -------------------------------------------------------------------------------- /modules/system/extensions/system.py: -------------------------------------------------------------------------------- 1 | # Support for xadc readout 2 | 3 | # This file is loaded by the extension server 4 | 5 | import os.path 6 | 7 | XADC_PATH = '/sys/bus/iio/devices/iio:device0' 8 | 9 | class XADC: 10 | def __init__(self, node): 11 | self.node = node 12 | try: 13 | self.offset = self.read_node('offset') 14 | except: 15 | self.offset = 0 16 | self.scale = self.read_node('scale') 17 | 18 | def read_node(self, part): 19 | filename = os.path.join(XADC_PATH, '%s_%s' % (self.node, part)) 20 | return float(open(filename).read()) 21 | 22 | def read(self, number): 23 | return self.scale * (self.offset + self.read_node('raw')) 24 | 25 | 26 | class Extension: 27 | def __init__(self, count): 28 | assert count == 1, 'Only one system block expected' 29 | 30 | def parse_read(self, node): 31 | return XADC(node).read 32 | -------------------------------------------------------------------------------- /modules/system/system_doc.rst: -------------------------------------------------------------------------------- 1 | SYSTEM - System control FPGA 2 | ============================ 3 | 4 | Fields 5 | ------ 6 | 7 | .. block_fields:: modules/system/system.block.ini 8 | -------------------------------------------------------------------------------- /modules/ttlin/ttlin.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | entity: ttlin 3 | description: TTL input 4 | 5 | [TERM] 6 | type: param enum 7 | description: Select TTL input termination 8 | 0: High-Z 9 | 1: 50-Ohm 10 | 11 | [VAL] 12 | type: bit_out 13 | description: TTL input value -------------------------------------------------------------------------------- /modules/ttlin/ttlin_doc.rst: -------------------------------------------------------------------------------- 1 | TTLIN - TTL Input 2 | ================= 3 | 4 | The TTLIN block handles the signals from the TTL Input connectors 5 | 6 | Fields 7 | ------ 8 | 9 | .. block_fields:: modules/ttlin/ttlin.block.ini 10 | 11 | -------------------------------------------------------------------------------- /modules/ttlout/ttlout.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: TTL output 3 | entity: ttlout 4 | 5 | [QUARTER_DELAY] 6 | type: param uint 3 7 | description: Number of 1/4 ticks to delay (range 0-3) 8 | if-option: fine_delay 9 | 10 | [FINE_DELAY] 11 | type: param uint 31 12 | description: Fine delay (range 0-31) 13 | if-option: fine_delay 14 | 15 | [VAL] 16 | type: bit_mux 17 | description: TTL output value 18 | -------------------------------------------------------------------------------- /modules/ttlout/ttlout_doc.rst: -------------------------------------------------------------------------------- 1 | TTLOUT - TTL Output 2 | =================== 3 | The TTLOUT block handles the signals to the TTL Output connectors 4 | 5 | Fields 6 | ------ 7 | 8 | .. block_fields:: modules/ttlout/ttlout.block.ini 9 | 10 | -------------------------------------------------------------------------------- /modules/us_system/extensions/us_system.py: -------------------------------------------------------------------------------- 1 | # Support for sysmon readout 2 | 3 | # This file is loaded by the extension server 4 | 5 | import os.path 6 | 7 | SYSMON_PATH = '/sys/bus/iio/devices/iio:device0' 8 | 9 | 10 | class SYSMON: 11 | def __init__(self, node): 12 | self.node = node 13 | try: 14 | self.offset = self.read_node('offset') 15 | except: 16 | self.offset = 0 17 | self.scale = self.read_node('scale') 18 | 19 | def read_node(self, part): 20 | filename = os.path.join(SYSMON_PATH, '%s_%s' % (self.node, part)) 21 | return float(open(filename).read()) 22 | 23 | def read(self, number): 24 | return self.scale * (self.offset + self.read_node('raw')) 25 | 26 | 27 | class Extension: 28 | def __init__(self, count): 29 | assert count == 1, 'Only one system block expected' 30 | 31 | def parse_read(self, node): 32 | return SYSMON(node).read 33 | -------------------------------------------------------------------------------- /modules/us_system/hdl/us_system_top.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | use work.support.all; 5 | use work.top_defines.all; 6 | use work.version.all; 7 | 8 | entity us_system_top is 9 | generic (NUM : natural := 1); 10 | port ( 11 | -- Clock and Reset 12 | clk_i : in std_logic; 13 | sys_i2c_mux_o : out std_logic; 14 | -- Memory Bus Interface 15 | read_strobe_i : in std_logic; 16 | read_address_i : in std_logic_vector(PAGE_AW-1 downto 0); 17 | read_data_o : out std_logic_vector(31 downto 0); 18 | read_ack_o : out std_logic; 19 | 20 | write_strobe_i : in std_logic; 21 | write_address_i : in std_logic_vector(PAGE_AW-1 downto 0); 22 | write_data_i : in std_logic_vector(31 downto 0); 23 | write_ack_o : out std_logic 24 | ); 25 | end us_system_top; 26 | 27 | architecture rtl of us_system_top is 28 | 29 | signal sys_i2c_mux : std_logic_vector(31 downto 0); 30 | 31 | begin 32 | 33 | sys_i2c_mux_o <= sys_i2c_mux(0); 34 | 35 | us_system_ctrl_inst : entity work.us_system_ctrl 36 | port map( 37 | clk_i => clk_i, 38 | reset_i => '0', 39 | bit_bus_i => (others => '0'), 40 | pos_bus_i => (others => (others => '0')), 41 | SYS_I2C_MUX => sys_i2c_mux, 42 | -- Memory Bus Interface 43 | read_strobe_i => read_strobe_i, 44 | read_address_i => read_address_i(BLK_AW-1 downto 0), 45 | read_data_o => read_data_o, 46 | read_ack_o => read_ack_o, 47 | 48 | write_strobe_i => write_strobe_i, 49 | write_address_i => write_address_i(BLK_AW-1 downto 0), 50 | write_data_i => write_data_i, 51 | write_ack_o => write_ack_o 52 | ); 53 | end rtl; 54 | -------------------------------------------------------------------------------- /modules/us_system/us_system.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: System Block for Zynq UltraScale+ series 3 | entity: us_system 4 | extension: 5 | 6 | [SYS_I2C_MUX] 7 | description: MUX selector for FPGA I2C (if applicable) 8 | type: param enum 9 | 0: Top-level FPGA pins 10 | 1: FMC 11 | 12 | [TEMP_PS] 13 | description: On-board CPU temperature 14 | type: read scalar 15 | extension: in_temp7 16 | scale: 0.001 17 | offset: 0 18 | units: deg 19 | 20 | [TEMP_PL] 21 | description: On-board FPGA temperature 22 | type: read scalar 23 | extension: in_temp20 24 | scale: 0.001 25 | offset: 0 26 | units: deg 27 | 28 | [VCCINT1] 29 | type: read scalar 30 | description: On-board voltage sensor 1 31 | extension: in_voltage2 32 | scale: 0.001 33 | offset: 0 34 | units: V 35 | 36 | [VCCINT2] 37 | type: read scalar 38 | description: On-board voltage sensor 2 39 | extension: in_voltage18 40 | scale: 0.001 41 | offset: 0 42 | units: V 43 | 44 | -------------------------------------------------------------------------------- /modules/zedboard_demo/zedboard_demo.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: ZedBoard Demo Block 3 | entity: zedboard_demo 4 | 5 | [LED_SELECT] 6 | type: param enum 7 | description: Select source driving LEDs 8 | 0: led_set 9 | 1: switches 10 | 11 | [LED_SET] 12 | type: param int 13 | description: LED setting 14 | 15 | [SWITCH_STAT] 16 | type: read int 17 | description: Switch readback 18 | 19 | -------------------------------------------------------------------------------- /old/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/old/__init__.py -------------------------------------------------------------------------------- /old/common/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/old/common/__init__.py -------------------------------------------------------------------------------- /old/common/python/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/old/common/python/__init__.py -------------------------------------------------------------------------------- /old/common/python/capture/__init__.py: -------------------------------------------------------------------------------- 1 | # zebra2 python package 2 | from .capture import Capture, DataHandler 3 | -------------------------------------------------------------------------------- /old/common/python/pandablocks/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /old/common/python/sphinxext/__init__.py: -------------------------------------------------------------------------------- 1 | # zebra2 python package 2 | -------------------------------------------------------------------------------- /old/common/python/vhdl_templates/addr_defines_template: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | package addr_defines is 6 | 7 | -- Functional Address Space Chip Selects 8 | {% for name, block in blocks.iteritems() %} 9 | constant {{name}}_CS : natural := {{block.base}}; 10 | {% endfor %} 11 | 12 | -- Block instantiation 13 | {% for name, block in blocks.iteritems() %} 14 | constant {{name}}_NUM : natural := {{block.num}}; 15 | {% endfor %} 16 | 17 | -- Block Register Address Space 18 | 19 | {% for blockname, block in blocks.iteritems() %} 20 | -- {{blockname}} Block: 21 | {% for regname, reg in block.registers.iteritems() %} 22 | constant {{blockname}}_{{regname}} : natural := {{reg[0]}}; 23 | {% endfor %} 24 | 25 | {% endfor %} 26 | 27 | 28 | end addr_defines; 29 | 30 | package body addr_defines is 31 | 32 | 33 | end addr_defines; 34 | -------------------------------------------------------------------------------- /old/common/python/vhdl_templates/panda_bitbus_template: -------------------------------------------------------------------------------- 1 | 2 | {% for name, block in blocks.iteritems() %} 3 | {% for fieldname, field in block.fields.iteritems() %} 4 | {% if field.cls == 'bit_out'%} 5 | {% set bit_bus_counter = 0 -%} 6 | {% for register in field.reg %} 7 | localparam {{name}}_{{field.name}}{{bit_bus_counter}} = {{register}}; 8 | {% set bit_bus_counter = bit_bus_counter + 1 %} 9 | {% endfor %} 10 | {% elif field.cls == 'pos_out'%} 11 | {% set pos_bus_counter = 0 -%} 12 | {% for register in field.reg %} 13 | localparam {{name}}_{{field.name}}{{pos_bus_counter}} = {{register}}; 14 | {% set pos_bus_counter = pos_bus_counter + 1 %} 15 | {% endfor %} 16 | {% endif %} 17 | {% endfor %} 18 | {% endfor %} 19 | 20 | 21 | -------------------------------------------------------------------------------- /old/common/vhdl/syncff.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------- 2 | -- Project : Diamond Diamond FOFB Communication Controller 3 | -- Filename : syncff.vhd 4 | -- Purpose : 2 DFF single-bit synchroniser 5 | -- Author : Isa S. Uzun 6 | ---------------------------------------------------------------------------- 7 | -- Copyright (c) 2007 Diamond Light Source Ltd. 8 | -- All rights reserved. 9 | ---------------------------------------------------------------------------- 10 | -- Description: 2 DFF single-bit synchroniser. A VHDL attribute is used to preserve 11 | -- signals so that they will be implemented using hard DFFs in the Virtex Slices, 12 | -- not LUTs. 13 | ---------------------------------------------------------------------------- 14 | -- Limitations & Assumptions: 15 | ---------------------------------------------------------------------------- 16 | 17 | library ieee; 18 | use ieee.std_logic_1164.all; 19 | 20 | entity syncff is 21 | port ( 22 | clk_i : in std_logic; 23 | dat_i : in std_logic; 24 | dat_o : out std_logic 25 | ); 26 | end syncff; 27 | 28 | architecture rtl of syncff is 29 | 30 | signal stage1 : std_logic; 31 | signal stage2 : std_logic; 32 | 33 | attribute keep : string; 34 | attribute keep of stage1, stage2: signal is "true"; 35 | 36 | begin 37 | 38 | process(clk_i) 39 | begin 40 | if rising_edge(clk_i) then 41 | stage1 <= dat_i; 42 | stage2 <= stage1; 43 | end if; 44 | end process; 45 | 46 | dat_o <= stage2; 47 | 48 | end rtl; 49 | 50 | -------------------------------------------------------------------------------- /old/common/vhdl/templates/sfp_top.vhd: -------------------------------------------------------------------------------- 1 | entity sfp_top is 2 | port ( 3 | -- DO NOT EDIT BELOW THIS LINE --------------------- 4 | -- Standard SFP Block ports, do not add to or delete 5 | clk_i : in std_logic; 6 | clk_aux_i : in std_logic; 7 | reset_i : in std_logic; 8 | -- System Bus Inputs 9 | bit_bus_i : in std_logic_vector(127 downto 0); 10 | pos_bus_i : in std32_array(31 downto 0); 11 | -- Generic Inputs to BitBus and PosBus from FMC and SFP 12 | sfp_inputs_o : out std_logic_vector(15 downto 0); 13 | sfp_data_o : out std32_array(15 downto 0); 14 | -- PandABlocks Memory Bus Interface 15 | read_strobe_i : in std_logic; 16 | read_address_i : in std_logic_vector(PAGE_AW-1 downto 0); 17 | read_data_o : out std_logic_vector(31 downto 0); 18 | read_ack_o : out std_logic; 19 | 20 | write_strobe_i : in std_logic; 21 | write_address_i : in std_logic_vector(PAGE_AW-1 downto 0); 22 | write_data_i : in std_logic_vector(31 downto 0); 23 | write_ack_o : out std_logic; 24 | -- SFP GTX I/O 25 | GTREFCLK_N : in std_logic; 26 | GTREFCLK_P : in std_logic; 27 | RXN_IN : in std_logic_vector(2 downto 0); 28 | RXP_IN : in std_logic_vector(2 downto 0); 29 | TXN_OUT : out std_logic_vector(2 downto 0); 30 | TXP_OUT : out std_logic_vector(2 downto 0) 31 | ); 32 | end sfp_top; 33 | 34 | -------------------------------------------------------------------------------- /old/docs/Manuals/FPGA-Development-Kit.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/old/docs/Manuals/FPGA-Development-Kit.docx -------------------------------------------------------------------------------- /old/docs/Manuals/FPGA-Development-Kit.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/old/docs/Manuals/FPGA-Development-Kit.pdf -------------------------------------------------------------------------------- /old/docs/configparser.rst: -------------------------------------------------------------------------------- 1 | API doc for configparser 2 | ======================== 3 | 4 | .. module: common.python.pandablocks.configparser.ConfigParser 5 | 6 | .. autoclass:: common.python.pandablocks.configparser.ConfigParser 7 | :members: 8 | 9 | .. autoclass:: common.python.pandablocks.configparser.ConfigBlock 10 | :members: 11 | 12 | .. autoclass:: common.python.pandablocks.configparser.ConfigField 13 | :members: 14 | -------------------------------------------------------------------------------- /old/docs/fixed_exposure_gate_trigger.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/old/docs/fixed_exposure_gate_trigger.png -------------------------------------------------------------------------------- /old/docs/index.rst: -------------------------------------------------------------------------------- 1 | Zebra2 2 | ====== 3 | 4 | This is what Zebra2 is 5 | -------------------------------------------------------------------------------- /old/docs/toc.rst: -------------------------------------------------------------------------------- 1 | Table of Contents 2 | ================= 3 | 4 | Contents: 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | index 10 | blocks/index.rst 11 | triggering.rst 12 | fpga_testing.rst 13 | configparser.rst 14 | -------------------------------------------------------------------------------- /old/docs/triggering.rst: -------------------------------------------------------------------------------- 1 | Triggering schemes 2 | ================== 3 | 4 | There are a number of ways that the PandA can be used with a live/dead frame 5 | signal to trigger a detector and PCAP. 6 | 7 | Fixed exposure gate and trigger 8 | ------------------------------- 9 | 10 | .. image:: fixed_exposure_gate_trigger.png 11 | 12 | (Edit the diagram with `draw.io `_, 13 | opening the png file from the docs directory). 14 | 15 | In this scheme triggers are expected to be a fixed distance apart. The live and 16 | dead signals are used in an SRGate to give a gapless gate signal while the 17 | detector is active. The LUT relies on the extra clock ticks it takes for the 18 | signal to get through the SRGate so that capture signals are generated at 19 | the end of every live frame. A number of detectors can be triggered from Pulse 20 | blocks with delay of readout/2 and width of exposure. 21 | 22 | .. sequence_plot:: 23 | :block: system 24 | :title: Fixed exposure gate and trigger 25 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/I18.test: -------------------------------------------------------------------------------- 1 | *VERBOSE=1 2 | *CAPTURE= 3 | 4 | CLOCKS.A_PERIOD.UNITS=us 5 | CLOCKS.A_PERIOD=1 6 | CLOCKS.B_PERIOD.UNITS=us 7 | CLOCKS.B_PERIOD=2 8 | CLOCKS.C_PERIOD.UNITS=us 9 | CLOCKS.C_PERIOD=4 10 | 11 | PCAP.ENABLE=BITS.ONE 12 | PCAP.FRAME=TTLIN2.VAL 13 | PCAP.CAPTURE=TTLIN3.VAL 14 | PCAP.FRAME_NUM=2562 15 | PCAP.FRAME_LENGTH.CAPTURE=Capture 16 | PCAP.CAPTURE_OFFSET.CAPTURE=Capture 17 | INENC1.VAL.CAPTURE=Triggered 18 | INENC2.VAL.CAPTURE=Triggered 19 | 20 | COUNTER1.STEP=1 21 | COUNTER1.START=0 22 | COUNTER1.ENABLE=PCAP.ACTIVE 23 | COUNTER1.TRIG=TTLIN2.VAL 24 | COUNTER1.OUT.CAPTURE=Difference 25 | 26 | COUNTER2.STEP=1 27 | COUNTER2.START=0 28 | COUNTER2.ENABLE=PCAP.ACTIVE 29 | COUNTER2.TRIG=CLOCKS.OUTB 30 | COUNTER2.OUT.CAPTURE=Difference 31 | 32 | COUNTER3.STEP=1 33 | COUNTER3.START=0 34 | COUNTER3.ENABLE=PCAP.ACTIVE 35 | COUNTER3.TRIG=CLOCKS.OUTC 36 | COUNTER3.OUT.CAPTURE=Difference 37 | 38 | PULSE1.WIDTH.UNITS=ms 39 | PULSE1.DELAY.UNITS=ms 40 | PULSE1.DELAY=0.1 41 | PULSE1.WIDTH=2 42 | PULSE1.INP=TTLIN1.VAL 43 | PULSE1.ENABLE=BITS.ONE 44 | TTLOUT1.VAL=PULSE1.OUT 45 | 46 | TTLOUT5.VAL=CLOCKS.OUTA 47 | TTLOUT9.VAL=TTLIN3.VAL 48 | TTLOUT10.VAL=TTLIN2.VAL 49 | 50 | *PCAP.ARM= 51 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/adc.test: -------------------------------------------------------------------------------- 1 | *VERBOSE=1 2 | *PCAP.DISARM= 3 | *CAPTURE= 4 | SEQ1.PRESCALE.RAW=125 5 | SEQ1.TABLE_CYCLE=1 6 | SEQ1.TABLE< 7 | 1 8 | 520109824 9 | 5000 10 | 1 11 | 12 | FMC.ADC1_GAIN=1 13 | FMC.ADC2_GAIN=2 14 | FMC.ADC3_GAIN=4 15 | FMC.ADC4_GAIN=8 16 | FMC.ADC1.CAPTURE=Triggered 17 | FMC.ADC2.CAPTURE=Triggered 18 | FMC.ADC3.CAPTURE=Triggered 19 | FMC.ADC4.CAPTURE=Triggered 20 | FMC.ENABLE=BITS.ONE 21 | PCAP.ENABLE=SEQ1.ACTIVE 22 | PCAP.FRAME=BITS.ZERO 23 | PCAP.CAPTURE=FMC.ADC_VALID 24 | TTLOUT1.VAL=SEQ1.OUTA 25 | TTLOUT2.VAL=FMC.ADC_VALID 26 | *PCAP.ARM= 27 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/biss-daisy: -------------------------------------------------------------------------------- 1 | # 2 PComps in daisy chain with BiSS 2 | *VERBOSE=1 3 | *PCAP.DISARM= 4 | *CAPTURE= 5 | INENC1.PROTOCOL=BISS 6 | OUTENC1.PROTOCOL=BISS 7 | INENC1.BITS_CRC=8 8 | INENC1.BITS=19 9 | PCOMP1.ENABLE=PCAP.ACTIVE 10 | PCOMP1.INP=INENC1.VAL 11 | PCOMP1.DELTAP=100 12 | PCOMP1.START=1000 13 | PCOMP1.STEP=0 14 | PCOMP1.WIDTH=9000 15 | PCOMP1.DIR=Positive 16 | PCOMP1.PNUM=1 17 | PCOMP1.RELATIVE=Absolute 18 | PCOMP1.USE_TABLE=No 19 | PCOMP2.ENABLE=PCOMP1.OUT 20 | PCOMP2.INP=INENC1.VAL 21 | PCOMP2.DELTAP=0 22 | PCOMP2.START=0 23 | PCOMP2.STEP=1000 24 | PCOMP2.WIDTH=100 25 | PCOMP2.DIR=Positive 26 | PCOMP2.PNUM=0 27 | PCOMP2.RELATIVE=Relative 28 | PCOMP2.USE_TABLE=No 29 | PCAP.ENABLE=PCOMP1.ACTIVE 30 | PCAP.ENABLE.DELAY=0 31 | PCAP.FRAME=BITS.ZERO 32 | PCAP.CAPTURE=PCOMP2.OUT 33 | INENC1.VAL.CAPTURE=Triggered 34 | PCAP.CAPTURE_TS.CAPTURE=Trigger 35 | *PCAP.ARM= 36 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/biss-pcomp: -------------------------------------------------------------------------------- 1 | # Single PComp using BISS encoder 2 | *VERBOSE=1 3 | *PCAP.DISARM= 4 | *CAPTURE= 5 | INENC1.PROTOCOL=BISS 6 | OUTENC1.PROTOCOL=BISS 7 | INENC1.BITS_CRC=6 8 | INENC1.BITS=19 9 | PCOMP1.ENABLE=PCAP.ACTIVE 10 | PCOMP1.INP=INENC1.VAL 11 | PCOMP1.DELTAP=10 12 | PCOMP1.START=100 13 | PCOMP1.STEP=100 14 | PCOMP1.WIDTH=10 15 | PCOMP1.DIR=Positive 16 | PCOMP1.PNUM=5 17 | PCOMP1.RELATIVE=Absolute 18 | PCOMP1.USE_TABLE=No 19 | PCAP.ENABLE=PCOMP1.ACTIVE 20 | PCAP.ENABLE.DELAY=0 21 | PCAP.FRAME=BITS.ZERO 22 | PCAP.CAPTURE=PCOMP1.OUT 23 | INENC1.VAL.CAPTURE=Triggered 24 | PCAP.CAPTURE_TS.CAPTURE=Trigger 25 | *PCAP.ARM= 26 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/counter: -------------------------------------------------------------------------------- 1 | *VERBOSE=1 2 | *PCAP.DISARM= 3 | *CAPTURE= 4 | SEQ1.PRESCALE.RAW=125 5 | SEQ1.TABLE_CYCLE=1 6 | SEQ1.TABLE< 7 | 100000000 8 | 520109824 9 | 1 10 | 1 11 | 12 | TTLOUT1.VAL=SEQ1.OUTA 13 | COUNTER1.STEP=1 14 | COUNTER1.START=0 15 | COUNTER1.ENABLE=SEQ1.ACTIVE 16 | COUNTER1.TRIG=TTLIN1.VAL 17 | COUNTER1.TRIG=SEQ1.OUTA 18 | COUNTER1.OUT.CAPTURE=Triggered 19 | SEQ1.ENABLE=PCAP.ACTIVE 20 | SEQ1.INPA=BITS.ONE 21 | PCAP.ENABLE=SEQ1.ACTIVE 22 | PCAP.FRAME=BITS.ZERO 23 | PCAP.CAPTURE=SEQ1.OUTA 24 | PCAP.CAPTURE_TS.CAPTURE=Trigger 25 | *PCAP.ARM= 26 | 27 | 28 | #*VERBOSE=1 29 | #*PCAP.DISARM= 30 | #*CAPTURE= 31 | #COUNTER1.STEP=50 32 | #COUNTER1.START=100 33 | #COUNTER1.ENABLE=SEQ1.ACTIVE 34 | #COUNTER1.TRIG=SEQ1.OUTA 35 | #COUNTER1.OUT.CAPTURE=Triggered 36 | #SEQ1.PRESCALE=0.05 37 | #SEQ1.TABLE_CYCLE=1 38 | #SEQ1.TABLE< 39 | #500 40 | #520109824 41 | #1 42 | #1 43 | # 44 | #SEQ1.ENABLE=PCAP.ACTIVE 45 | #SEQ1.INPA=BITS.ONE 46 | #PCAP.ENABLE=SEQ1.ACTIVE 47 | #PCAP.FRAME=BITS.ZERO 48 | #PCAP.CAPTURE=SEQ1.OUTA 49 | #PCAP.CAPTURE_TS.CAPTURE=Trigger 50 | 51 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/div: -------------------------------------------------------------------------------- 1 | *VERBOSE=1 2 | CLOCKS.A_PERIOD=1000 3 | TTLOUT1.VAL=CLOCKS.OUTA 4 | TTLOUT2.VAL=DIV4.OUTN 5 | TTLOUT3.VAL=DIV4.OUTD 6 | DIV4.FIRST_PULSE=OutD 7 | DIV4.INP=TTLIN1.VAL 8 | DIV4.DIVISOR=3 9 | DIV4.ENABLE=BITS.ONE 10 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/i08-setup: -------------------------------------------------------------------------------- 1 | *PCAP.DISARM= 2 | *CAPTURE= 3 | INENC1.PROTOCOL=BISS 4 | OUTENC1.PROTOCOL=BISS 5 | INENC1.BITS=32 6 | INENC2.PROTOCOL=BISS 7 | OUTENC2.PROTOCOL=BISS 8 | INENC2.BITS=32 9 | INENC3.PROTOCOL=BISS 10 | OUTENC3.PROTOCOL=BISS 11 | INENC3.BITS=32 12 | INENC4.PROTOCOL=BISS 13 | OUTENC4.PROTOCOL=BISS 14 | INENC4.BITS=32 15 | INENC1.DCARD_MODE? 16 | INENC2.DCARD_MODE? 17 | INENC3.DCARD_MODE? 18 | INENC4.DCARD_MODE? 19 | INENC1.VAL.CAPTURE=Triggered 20 | INENC2.VAL.CAPTURE=Triggered 21 | INENC3.VAL.CAPTURE=Triggered 22 | INENC4.VAL.CAPTURE=Triggered 23 | PCAP.CAPTURE_TS.CAPTURE=Trigger 24 | PCAP.ENABLE=BITS.ONE 25 | PCAP.FRAME=BITS.ZERO 26 | PCAP.CAPTURE=INENC1.TRANS 27 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/parser.m: -------------------------------------------------------------------------------- 1 | function [x]= parser(Fields) 2 | 3 | f=fopen('log.file'); 4 | x = fread(f,[Fields,inf],'int32'); 5 | fclose(f); -------------------------------------------------------------------------------- /old/tests/fpga_tests/pcap.m: -------------------------------------------------------------------------------- 1 | function [ts x xref y yref]=pcap(filename) 2 | 3 | fields=6; 4 | f = fopen(filename); x = fread(f,'6*uint32=>uint32'); fclose(f); 5 | raw = reshape(x, fields, []); 6 | x1 = raw(1,:); 7 | x2 = raw(2,:); 8 | ts = double(x1) + double(x2)*2^32; 9 | 10 | x = raw(3,:); 11 | xref = raw(4,:); 12 | 13 | y = raw(5,:); 14 | yref = raw(6,:); 15 | 16 | x = 1024*typecast(x, 'int32'); 17 | xref = 1024*typecast(xref, 'int32'); 18 | y = 1024*typecast(y, 'int32'); 19 | yref = 1024*typecast(yref, 'int32'); 20 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/pcomp: -------------------------------------------------------------------------------- 1 | #Up/Down Pulse Gen 2 | *VERBOSE=1 3 | *PCAP.DISARM= 4 | *CAPTURE= 5 | PCOMP1.ENABLE=PCAP.ACTIVE 6 | PCOMP1.INP=INENC1.VAL 7 | PCOMP1.DELTAP=100 8 | PCOMP1.START=1000 9 | PCOMP1.STEP=1000 10 | PCOMP1.WIDTH=500 11 | PCOMP1.DIR=Positive 12 | PCOMP1.PNUM=5 13 | PCOMP1.RELATIVE=Absolute 14 | PCOMP1.USE_TABLE=No 15 | PCOMP2.ENABLE=PCAP.ACTIVE 16 | PCOMP2.INP=INENC1.VAL 17 | PCOMP2.DELTAP=100 18 | PCOMP2.START=5000 19 | PCOMP2.STEP=1000 20 | PCOMP2.WIDTH=500 21 | PCOMP2.DIR=Negative 22 | PCOMP2.PNUM=5 23 | PCOMP2.RELATIVE=Absolute 24 | PCOMP2.USE_TABLE=No 25 | LUT1.INPA=PCOMP1.OUT 26 | LUT1.INPB=PCOMP2.OUT 27 | LUT1.FUNC=A|B 28 | INENC1.VAL.CAPTURE=Triggered 29 | PCAP.CAPTURE_TS.CAPTURE=Trigger 30 | PCAP.ENABLE=PCOMP2.ACTIVE 31 | PCAP.FRAME=BITS.ZERO 32 | PCAP.CAPTURE=LUT1.OUT 33 | *PCAP.ARM= 34 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/pos-capture: -------------------------------------------------------------------------------- 1 | # Capture encoder position as it changes 2 | *VERBOSE=1 3 | *PCAP.DISARM= 4 | *CAPTURE= 5 | INENC1.PROTOCOL=BISS 6 | OUTENC1.PROTOCOL=BISS 7 | INENC1.BITS_CRC=8 8 | INENC1.BITS=19 9 | PCOMP1.ENABLE=PCAP.ACTIVE 10 | PCOMP1.INP=INENC1.VAL 11 | PCOMP1.DELTAP=100 12 | PCOMP1.START=1000 13 | PCOMP1.STEP=0 14 | PCOMP1.WIDTH=9000 15 | PCOMP1.DIR=Positive 16 | PCOMP1.PNUM=1 17 | PCOMP1.RELATIVE=Absolute 18 | PCOMP1.USE_TABLE=No 19 | PCAP.ENABLE=PCOMP1.ACTIVE 20 | PCAP.ENABLE.DELAY=0 21 | PCAP.FRAME=BITS.ZERO 22 | PCAP.CAPTURE=INENC1.TRANS 23 | INENC1.VAL.CAPTURE=Triggered 24 | *PCAP.ARM= 25 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/pulse: -------------------------------------------------------------------------------- 1 | *VERBOSE=1 2 | CLOCKS.A_PERIOD=1000 3 | TTLOUT1.VAL=CLOCKS.OUTA 4 | TTLOUT2.VAL=PULSE1.OUT 5 | TTLOUT3.VAL=PULSE4.OUT 6 | PULSE1.WIDTH.UNITS=us 7 | PULSE1.DELAY.UNITS=us 8 | PULSE1.DELAY=100 9 | PULSE1.WIDTH=250 10 | PULSE1.INP=TTLIN1.VAL 11 | PULSE1.ENABLE=BITS.ONE 12 | PULSE4.WIDTH.UNITS=us 13 | PULSE4.DELAY.UNITS=us 14 | PULSE4.DELAY=100 15 | PULSE4.WIDTH=500 16 | PULSE4.INP=TTLIN1.VAL 17 | PULSE4.ENABLE=BITS.ONE 18 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/readme: -------------------------------------------------------------------------------- 1 | nc 172.23.252.201 8889 (hit enter twice) 2 | 3 | cat seq | nc 172.23.252.201 8888 4 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/seq: -------------------------------------------------------------------------------- 1 | # repeats, mask, cond, p1out, p2out, p1time, p2time 2 | # 10, 1, 15, 0, 63, 1, 1 3 | # 10, 2, 15, 0, 63, 1, 1 4 | # 10, 4, 15, 0, 63, 1, 1 5 | # 10, 8, 15, 0, 63, 1, 1 6 | # 10, 9, 8, 0, 63, 1, 1 7 | # 10, 15, 0, 0, 63, 1, 1 8 | 9 | *VERBOSE=1 10 | *PCAP.DISARM= 11 | *CAPTURE= 12 | COUNTER1.STEP=1 13 | COUNTER1.START=0 14 | COUNTER1.ENABLE=SEQ1.ACTIVE 15 | COUNTER1.TRIG=SEQ1.OUTA 16 | COUNTER1.OUT.CAPTURE=Triggered 17 | COUNTER2.STEP=1 18 | COUNTER2.START=0 19 | COUNTER2.ENABLE=SEQ1.ACTIVE 20 | COUNTER2.TRIG=SEQ1.OUTA 21 | COUNTER2.OUT.CAPTURE=Triggered 22 | BITS.A=0 23 | BITS.B=0 24 | BITS.C=0 25 | BITS.D=0 26 | SEQ1.PRESCALE.RAW=125 27 | SEQ1.TABLE_CYCLE=1 28 | SEQ1.TABLE< 29 | 10 30 | 520109824 31 | 1 32 | 1 33 | 10 34 | 788545280 35 | 1 36 | 1 37 | 10 38 | 1325416192 39 | 1 40 | 1 41 | 10 42 | 2399158016 43 | 1 44 | 1 45 | 10 46 | 2550152960 47 | 1 48 | 1 49 | 10 50 | 4026547968 51 | 1 52 | 1 53 | 54 | SEQ1.ENABLE=PCAP.ACTIVE 55 | SEQ1.INPA=BITS.OUTA 56 | SEQ1.INPB=BITS.OUTB 57 | SEQ1.INPC=BITS.OUTC 58 | SEQ1.INPD=BITS.OUTD 59 | PCAP.ENABLE=SEQ1.ACTIVE 60 | PCAP.FRAME=BITS.ZERO 61 | PCAP.CAPTURE=SEQ1.OUTA 62 | PCAP.CAPTURE_TS.CAPTURE=Trigger 63 | *PCAP.ARM= 64 | -------------------------------------------------------------------------------- /old/tests/fpga_tests/table: -------------------------------------------------------------------------------- 1 | *VERBOSE=1 2 | *PCAP.DISARM= 3 | *CAPTURE= 4 | PGEN1.CYCLES=1 5 | PGEN1.ENABLE=PCAP.ACTIVE 6 | PGEN1.TRIG=SEQ1.OUTA 7 | PGEN1.OUT.CAPTURE=Triggered 8 | PGEN2.CYCLES=1 9 | PGEN2.ENABLE=PCAP.ACTIVE 10 | PGEN2.TRIG=SEQ1.OUTA 11 | PGEN2.OUT.CAPTURE=Triggered 12 | SEQ1.PRESCALE.RAW=125 13 | SEQ1.TABLE_CYCLE=1 14 | SEQ1.TABLE< 15 | 262144 16 | 520109824 17 | 1 18 | 1 19 | 20 | SEQ1.ENABLE=PCAP.ACTIVE 21 | SEQ1.INPA=BITS.ONE 22 | PCAP.ENABLE=SEQ1.ACTIVE 23 | PCAP.FRAME=BITS.ZERO 24 | PCAP.CAPTURE=SEQ1.OUTA 25 | *PCAP.ARM= 26 | -------------------------------------------------------------------------------- /old/tests/sim/panda_biss/bench/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.15 2011/08/25 22:54:30 fphillip Exp $ 2 | 3 | `timescale 1 ps / 1 ps 4 | 5 | module glbl (); 6 | 7 | parameter ROC_WIDTH = 100000; 8 | parameter TOC_WIDTH = 0; 9 | 10 | //-------- STARTUP Globals -------------- 11 | wire GSR; 12 | wire GTS; 13 | wire GWE; 14 | wire PRLD; 15 | tri1 p_up_tmp; 16 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 17 | 18 | wire PROGB_GLBL; 19 | wire CCLKO_GLBL; 20 | 21 | reg GSR_int; 22 | reg GTS_int; 23 | reg PRLD_int; 24 | 25 | //-------- JTAG Globals -------------- 26 | wire JTAG_TDO_GLBL; 27 | wire JTAG_TCK_GLBL; 28 | wire JTAG_TDI_GLBL; 29 | wire JTAG_TMS_GLBL; 30 | wire JTAG_TRST_GLBL; 31 | 32 | reg JTAG_CAPTURE_GLBL; 33 | reg JTAG_RESET_GLBL; 34 | reg JTAG_SHIFT_GLBL; 35 | reg JTAG_UPDATE_GLBL; 36 | reg JTAG_RUNTEST_GLBL; 37 | 38 | reg JTAG_SEL1_GLBL = 0; 39 | reg JTAG_SEL2_GLBL = 0 ; 40 | reg JTAG_SEL3_GLBL = 0; 41 | reg JTAG_SEL4_GLBL = 0; 42 | 43 | reg JTAG_USER_TDO1_GLBL = 1'bz; 44 | reg JTAG_USER_TDO2_GLBL = 1'bz; 45 | reg JTAG_USER_TDO3_GLBL = 1'bz; 46 | reg JTAG_USER_TDO4_GLBL = 1'bz; 47 | 48 | assign (weak1, weak0) GSR = GSR_int; 49 | assign (weak1, weak0) GTS = GTS_int; 50 | assign (weak1, weak0) PRLD = PRLD_int; 51 | 52 | initial begin 53 | GSR_int = 1'b1; 54 | PRLD_int = 1'b1; 55 | #(ROC_WIDTH) 56 | GSR_int = 1'b0; 57 | PRLD_int = 1'b0; 58 | end 59 | 60 | initial begin 61 | GTS_int = 1'b1; 62 | #(TOC_WIDTH) 63 | GTS_int = 1'b0; 64 | end 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /old/tests/sim/panda_slowctrl/bench/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.15 2011/08/25 22:54:30 fphillip Exp $ 2 | 3 | `timescale 1 ps / 1 ps 4 | 5 | module glbl (); 6 | 7 | parameter ROC_WIDTH = 100000; 8 | parameter TOC_WIDTH = 0; 9 | 10 | //-------- STARTUP Globals -------------- 11 | wire GSR; 12 | wire GTS; 13 | wire GWE; 14 | wire PRLD; 15 | tri1 p_up_tmp; 16 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 17 | 18 | wire PROGB_GLBL; 19 | wire CCLKO_GLBL; 20 | 21 | reg GSR_int; 22 | reg GTS_int; 23 | reg PRLD_int; 24 | 25 | //-------- JTAG Globals -------------- 26 | wire JTAG_TDO_GLBL; 27 | wire JTAG_TCK_GLBL; 28 | wire JTAG_TDI_GLBL; 29 | wire JTAG_TMS_GLBL; 30 | wire JTAG_TRST_GLBL; 31 | 32 | reg JTAG_CAPTURE_GLBL; 33 | reg JTAG_RESET_GLBL; 34 | reg JTAG_SHIFT_GLBL; 35 | reg JTAG_UPDATE_GLBL; 36 | reg JTAG_RUNTEST_GLBL; 37 | 38 | reg JTAG_SEL1_GLBL = 0; 39 | reg JTAG_SEL2_GLBL = 0 ; 40 | reg JTAG_SEL3_GLBL = 0; 41 | reg JTAG_SEL4_GLBL = 0; 42 | 43 | reg JTAG_USER_TDO1_GLBL = 1'bz; 44 | reg JTAG_USER_TDO2_GLBL = 1'bz; 45 | reg JTAG_USER_TDO3_GLBL = 1'bz; 46 | reg JTAG_USER_TDO4_GLBL = 1'bz; 47 | 48 | assign (weak1, weak0) GSR = GSR_int; 49 | assign (weak1, weak0) GTS = GTS_int; 50 | assign (weak1, weak0) PRLD = PRLD_int; 51 | 52 | initial begin 53 | GSR_int = 1'b1; 54 | PRLD_int = 1'b1; 55 | #(ROC_WIDTH) 56 | GSR_int = 1'b0; 57 | PRLD_int = 1'b0; 58 | end 59 | 60 | initial begin 61 | GTS_int = 1'b1; 62 | #(TOC_WIDTH) 63 | GTS_int = 1'b0; 64 | end 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /old/tests/system_tests/testseq: -------------------------------------------------------------------------------- 1 | *PCAP.DISARM= 2 | *CAPTURE= 3 | COUNTER1.STEP=50 4 | COUNTER1.START=100 5 | COUNTER1.ENABLE=SEQ1.ACTIVE 6 | COUNTER1.TRIG=SEQ1.OUTA 7 | COUNTER1.OUT.CAPTURE=Triggered 8 | SEQ1.PRESCALE=0.05 9 | SEQ1.TABLE_CYCLE=1 10 | SEQ1.TABLE< 11 | 10 12 | 520109824 13 | 1 14 | 1 15 | 16 | SEQ1.ENABLE=PCAP.ACTIVE 17 | SEQ1.INPA=BITS.ONE 18 | PCAP.ENABLE=SEQ1.ACTIVE 19 | PCAP.FRAME=BITS.ZERO 20 | PCAP.CAPTURE=SEQ1.OUTA 21 | PCAP.CAPTURE_TS.CAPTURE=Trigger 22 | *PCAP.ARM= 23 | -------------------------------------------------------------------------------- /old/tests/test_zebra2/test_simulation/test_block.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import unittest 3 | import sys 4 | import os 5 | 6 | # Module import 7 | from pkg_resources import require 8 | require("numpy") 9 | 10 | sys.path.append(os.path.join(os.path.dirname(__file__), 11 | "..", "..", "..", "python")) 12 | config_dir = os.path.join(os.path.dirname(__file__), 13 | "..", "..", "..", "config_d") 14 | from zebra2.simulation.block import Block 15 | 16 | 17 | class BlockTest(unittest.TestCase): 18 | 19 | def test_attrs(self): 20 | class Pulse(Block): 21 | pass 22 | Block.load_config(config_dir) 23 | p = Pulse() 24 | self.assertEqual(p.WIDTH_L, 0) 25 | self.assertEqual(p.config_block.WIDTH_L, "WIDTH_L") 26 | p.WIDTH_L = 32 27 | self.assertEqual(p._changes, dict(WIDTH_L=32)) 28 | 29 | if __name__=="__main__": 30 | unittest.main(verbosity=2) 31 | -------------------------------------------------------------------------------- /targets/PandABox/PandABox.target.ini: -------------------------------------------------------------------------------- 1 | # Ini file for the carrier blocks for PandABox. This replaces the panda_carrier 2 | # module. The config files for each carrier block can be found in 3 | # blocks/blockname 4 | [.] 5 | io: sfp: mgt, 3 6 | fmc: 1 7 | fmc_mgt: mgt, 1* 8 | options: pcap_std_dev, PICXO 9 | 10 | [TTLIN] 11 | number: 6 12 | 13 | [TTLOUT] 14 | number: 10 15 | 16 | [LVDSIN] 17 | number: 2 18 | 19 | [LVDSOUT] 20 | number: 2 21 | 22 | [INENC] 23 | number: 4 24 | 25 | [OUTENC] 26 | number: 4 27 | 28 | [PCAP] 29 | number: 1 30 | 31 | [SYSTEM] 32 | number: 1 33 | -------------------------------------------------------------------------------- /targets/PandABox/const/FMC_MGT1_pins.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # FMC MGT pins - Bank 112 3 | # ------------------------------------------------------------------- 4 | 5 | set_property PACKAGE_PIN AA7 [get_ports {FMC_DP_M2C_P[0]}]; 6 | set_property PACKAGE_PIN AB7 [get_ports {FMC_DP_M2C_N[0]}]; 7 | set_property PACKAGE_PIN AA3 [get_ports {FMC_DP_C2M_P[0]}]; 8 | set_property PACKAGE_PIN AB3 [get_ports {FMC_DP_C2M_N[0]}]; 9 | 10 | -------------------------------------------------------------------------------- /targets/PandABox/const/PandABox-clks_impl.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # Define asynchronous clocks 3 | # ------------------------------------------------------------------- 4 | 5 | set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks clk_fpga_0] 6 | set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks EXTCLK_P] 7 | set_clock_groups -asynchronous -group GTXCLK0_P 8 | set_clock_groups -asynchronous -group GTXCLK1_P 9 | 10 | set_clock_groups -quiet -logically_exclusive -group fclk_clk -group fclk_clk_1 -group fclk_clk_2 11 | set_clock_groups -quiet -logically_exclusive -group fclk_clk_2x -group fclk_clk_2x_1 -group fclk_clk_2x_2 12 | set_clock_groups -quiet -logically_exclusive -group pll2_clkfbout -group pll2_clkfbout_1 -group pll2_clkfbout_2 13 | 14 | set_clock_groups -quiet -logically_exclusive -group fclk_clk -group fclk_clk_2x_1 15 | set_clock_groups -quiet -logically_exclusive -group fclk_clk -group fclk_clk_2x_2 16 | set_clock_groups -quiet -logically_exclusive -group fclk_clk_1 -group fclk_clk_2x 17 | set_clock_groups -quiet -logically_exclusive -group fclk_clk_1 -group fclk_clk_2x_2 18 | set_clock_groups -quiet -logically_exclusive -group fclk_clk_2 -group fclk_clk_2x 19 | set_clock_groups -quiet -logically_exclusive -group fclk_clk_2 -group fclk_clk_2x_1 20 | 21 | -------------------------------------------------------------------------------- /targets/PandABox/const/PandABox-freq.xdc: -------------------------------------------------------------------------------- 1 | # Programmable oscillator for SFPs (default frequency - 125 MHz) 2 | create_clock -period 8.000 [get_ports GTXCLK0_P] 3 | # Programmable oscillator for SFPs (default frequency - 125 MHz) 4 | create_clock -period 8.000 [get_ports GTXCLK1_P] 5 | # External SMA clock (default frequency - 125 MHz) 6 | create_clock -period 8.000 [get_ports EXTCLK_P] 7 | -------------------------------------------------------------------------------- /targets/PandABox/const/SFP1_pins.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # SFP3 MGT - Bank 112 3 | # ------------------------------------------------------------------- 4 | 5 | set_property PACKAGE_PIN W6 [get_ports {SFP_RX_P[2] }]; #SFP3_rx 6 | set_property PACKAGE_PIN Y6 [get_ports {SFP_RX_N[2] }]; #SFP3_rx 7 | set_property PACKAGE_PIN W2 [get_ports {SFP_TX_P[2] }]; #SFP3_tx 8 | set_property PACKAGE_PIN Y2 [get_ports {SFP_TX_N[2] }]; #SFP3_tx 9 | 10 | -------------------------------------------------------------------------------- /targets/PandABox/const/SFP2_pins.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # SFP2 MGT - Bank 112 3 | # ------------------------------------------------------------------- 4 | 5 | set_property PACKAGE_PIN AA9 [get_ports {SFP_RX_P[1] }]; #SFP2_rx 6 | set_property PACKAGE_PIN AB9 [get_ports {SFP_RX_N[1] }]; #SFP2_rx 7 | set_property PACKAGE_PIN AA5 [get_ports {SFP_TX_P[1] }]; #SFP2_tx 8 | set_property PACKAGE_PIN AB5 [get_ports {SFP_TX_N[1] }]; #SFP2_tx 9 | 10 | -------------------------------------------------------------------------------- /targets/PandABox/const/SFP3_pins.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # SFP1 MGT - Bank 112 3 | # ------------------------------------------------------------------- 4 | 5 | set_property PACKAGE_PIN W8 [get_ports {SFP_RX_P[0] }]; #SFP1_rx 6 | set_property PACKAGE_PIN Y8 [get_ports {SFP_RX_N[0] }]; #SFP1_rx 7 | set_property PACKAGE_PIN W4 [get_ports {SFP_TX_P[0] }]; #SFP1_tx 8 | set_property PACKAGE_PIN Y4 [get_ports {SFP_TX_N[0] }]; #SFP1_tx 9 | 10 | -------------------------------------------------------------------------------- /targets/PandABox/etc/panda-fpga.list: -------------------------------------------------------------------------------- 1 | # Directory structure 2 | d share/panda-fpga/config_d 3 | d share/template_designs 4 | d share/www 5 | d lib/python/site-packages/i2c 6 | d etc/www 7 | d bin 8 | d firmware 9 | 10 | # Configuration files 11 | b share/panda-fpga/config_d autogen/config_d/config 12 | b share/panda-fpga/config_d autogen/config_d/registers 13 | b share/panda-fpga/config_d autogen/config_d/description 14 | b share/panda-fpga ipmi.ini 15 | 16 | # Server startup and helper code 17 | B share/panda-fpga extensions 18 | t share/panda-fpga targets/PandABox/etc/load-panda-firmware 19 | 20 | # IPMI python support 21 | T lib/python/site-packages/i2c etc/i2c/*.py 22 | t bin etc/check_ipmi 23 | t bin etc/show_ipmi 24 | t bin etc/write_eeprom 25 | 26 | # Firmware 27 | b share/panda-fpga FPGA/panda_top.bin 28 | 29 | # Docs (built once for all zpkgs) 30 | t etc/www etc/panda-fpga.docs.html 31 | T share/template_designs docs/tutorials/*.json 32 | B share/www/panda-fpga ../../html 33 | -------------------------------------------------------------------------------- /targets/PandABox/etc/target-defs: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # LED daemon definitions 3 | LED_GPIO_BASE=906 4 | STA_LED_OFFSET=51 5 | DIA_LED_OFFSET=50 6 | 7 | get_mac_address() 8 | { 9 | cat /qspi/MAC 10 | } 11 | -------------------------------------------------------------------------------- /targets/PandABox/platform_incl.make: -------------------------------------------------------------------------------- 1 | # Define target platform for cross-compiler 2 | # Either 'zynq' for Zynq-7000 (Default) or 'zynqmp' for Zynq UltraScale+ MPSoC 3 | PLATFORM = zynq 4 | # UBOOT_DTS must match the name in uboot/kernel sources /arch/arm/dts 5 | UBOOT_DTS = "zynq-zc702" 6 | # If appropriate DTS file is not included in the kernel sources, \ 7 | # we can specify to use the built DTB for the target instead. \ 8 | # Note this does NOT work for ZedBoard but does for PandABox. 9 | # UBOOT_USE_EXT_DTB = 10 | 11 | -------------------------------------------------------------------------------- /targets/PandABox/target_incl.tcl: -------------------------------------------------------------------------------- 1 | set FPGA_PART xc7z030sbg485-1 2 | set HDL_TOP PandABox_top 3 | 4 | # Target specific Constriants to be read 5 | # NB: we could just read the entire directory with 'add_files [glob $TARGET_DIR/const/*.xdc] 6 | set CONSTRAINTS { \ 7 | PandABox-pins_impl.xdc \ 8 | PandABox-freq.xdc \ 9 | PandABox-clks_impl.xdc 10 | } 11 | 12 | -------------------------------------------------------------------------------- /targets/PandABrick/PandABrick.target.ini: -------------------------------------------------------------------------------- 1 | # Ini file for the carrier blocks for PandABox. This replaces the panda_carrier 2 | # module. The config files for each carrier block can be found in 3 | # blocks/blockname 4 | [.] 5 | io: sfp: mgt, 1 6 | options: pcap_std_dev 7 | 8 | [TTLIN] 9 | number: 2 10 | 11 | [TTLOUT] 12 | number: 2 13 | 14 | [ABSENC] 15 | number: 8 16 | 17 | [INCENC] 18 | number: 8 19 | 20 | [PMACENC] 21 | number: 8 22 | 23 | [PCAP] 24 | number: 1 25 | 26 | [US_SYSTEM] 27 | number: 1 28 | 29 | [PANDABRICK_TEST] 30 | number: 1 31 | 32 | -------------------------------------------------------------------------------- /targets/PandABrick/const/PandABrick-clks.xdc: -------------------------------------------------------------------------------- 1 | # Clock constraints for clocks provided as inputs to the core 2 | # Note: the IP core-level XDC constrains clocks produced by the core, which drive user clocks via helper blocks 3 | # ---------------------------------------------------------------------------------------------------------------------- 4 | create_clock -period 8.000 -name clk_mgtrefclk1_x0y1_p [get_ports mgtrefclk1_x0y1_p] 5 | set_clock_groups -asynchronous -group clk_mgtrefclk1_x0y1_p 6 | 7 | -------------------------------------------------------------------------------- /targets/PandABrick/const/SFP1_pins.xdc: -------------------------------------------------------------------------------- 1 | 2 | # Tx and Rx Pins... 3 | 4 | set_property PACKAGE_PIN V2 [get_ports ch1_gthrxp_in] 5 | set_property PACKAGE_PIN V1 [get_ports ch1_gthrxn_in] 6 | set_property PACKAGE_PIN U4 [get_ports ch1_gthtxp_out] 7 | set_property PACKAGE_PIN U3 [get_ports ch1_gthtxn_out] 8 | 9 | -------------------------------------------------------------------------------- /targets/PandABrick/etc/load-panda-firmware: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Script to load Panda FPGA image 4 | 5 | # This is called directly by the /opt/etc/init.d/panda-server script and relies 6 | # on panda-server being installed 7 | 8 | # File locations 9 | carrier_firmware=/opt/share/panda-fpga/panda_top.bin 10 | check_ipmi=/opt/bin/check_ipmi 11 | 12 | fail() 13 | { 14 | echo >&2 "$@" 15 | exit 1 16 | } 17 | 18 | load_fpga() 19 | { 20 | local bitstream="$1" 21 | local name="$(basename $bitstream)" 22 | # Set flags for loading full bitstream 23 | echo 0 > /sys/class/fpga_manager/fpga0/flags 24 | ln -sf $bitstream /opt/firmware/$name 25 | echo $name > /sys/class/fpga_manager/fpga0/firmware 26 | } 27 | 28 | [ -e $carrier_firmware ] || 29 | fail "Firmware not installed" 30 | 31 | # Check whether the FMC IPMI configuration matches that expected by the FPGA 32 | $check_ipmi && 33 | 34 | # If FMC passes then load the carrier firmware 35 | load_fpga $carrier_firmware 36 | 37 | -------------------------------------------------------------------------------- /targets/PandABrick/etc/panda-fpga.list: -------------------------------------------------------------------------------- 1 | # Directory structure 2 | d share/panda-fpga/config_d 3 | d share/template_designs 4 | d share/www 5 | d lib/python/site-packages/i2c 6 | d etc/www 7 | d bin 8 | d firmware 9 | 10 | # Configuration files 11 | b share/panda-fpga/config_d autogen/config_d/config 12 | b share/panda-fpga/config_d autogen/config_d/registers 13 | b share/panda-fpga/config_d autogen/config_d/description 14 | b share/panda-fpga ipmi.ini 15 | 16 | # Server startup and helper code 17 | B share/panda-fpga extensions 18 | t share/panda-fpga targets/xu5_st1/etc/load-panda-firmware 19 | 20 | # IPMI python support 21 | T lib/python/site-packages/i2c etc/i2c/*.py 22 | t bin etc/check_ipmi 23 | t bin etc/show_ipmi 24 | 25 | # Firmware 26 | b share/panda-fpga FPGA/panda_top.bin 27 | 28 | # Docs (built once for all zpkgs) 29 | t etc/www etc/panda-fpga.docs.html 30 | T share/template_designs docs/tutorials/*.json 31 | B share/www/panda-fpga ../../html 32 | -------------------------------------------------------------------------------- /targets/PandABrick/etc/target-defs: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # LED daemon definitions 4 | LED_GPIO_BASE=334 5 | STA_LED_OFFSET=40 6 | DIA_LED_OFFSET=41 7 | 8 | get_mac_address() { 9 | # Trying to address 0 sends a 0 byte which wakes up the EEPROM 10 | i2ctransfer -a -y 0 r1@0x0 &>/dev/null 11 | # Send command to read 32 bytes of OTP zone starting at offset 0 12 | # See script atsha240a-gen for more information, it was used to 13 | # generate the bytes in the request 14 | i2ctransfer -y 0 w8@0x64 0x3 0x7 0x2 0x81 0x0 0x0 0x0a 0x27 15 | # Reply structure: length(1b) + data(32b) + crc16(2b) 16 | resp=$(i2ctransfer -y 0 r35@0x64) 17 | # Extract the MAC address and format it 18 | resp=${resp:85:29} 19 | resp=${resp//0x/} 20 | echo ${resp// /:} 21 | } 22 | -------------------------------------------------------------------------------- /targets/PandABrick/hdl/sim/run_xsim.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/sh 2 | 3 | VIVADO=/dls_sw/FPGA/Xilinx/Vivado/2022.2 4 | 5 | . $VIVADO/settings64.sh 6 | 7 | mkdir -p build && cd build 8 | 9 | xvlog $VIVADO/data/verilog/src/glbl.v ../../Adaptor_PIC_SPI.v && 10 | xvhdl ../Adaptor_PIC_SPI_tb.vhd && 11 | xelab -L unisims_ver -debug typical Adaptor_PIC_SPI_tb glbl && 12 | xsim work.Adaptor_PIC_SPI_tb#work.glbl -gui --autoloadwcfg -t ../xsim.tcl 13 | 14 | -------------------------------------------------------------------------------- /targets/PandABrick/hdl/sim/xsim.tcl: -------------------------------------------------------------------------------- 1 | create_wave_config; add_wave /; set_property needs_save false [current_wave_config] 2 | run all 3 | -------------------------------------------------------------------------------- /targets/PandABrick/platform_incl.make: -------------------------------------------------------------------------------- 1 | # Define target platform for cross-compiler 2 | # Either 'zynq' for Zynq-7000 (Default) or 'zynqmp' for Zynq UltraScale+ MPSoC 3 | PLATFORM = zynqmp 4 | UBOOT_USE_EXT_DTB = 1 5 | -------------------------------------------------------------------------------- /targets/PandABrick/target-top.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /include/ "system-top.dts.tmp" 3 | 4 | &sdhci1 { 5 | disable-wp; 6 | no-1-8-v; 7 | }; 8 | 9 | &i2c0 { 10 | clock-frequency = <100000>; 11 | }; 12 | 13 | &qspi { 14 | is-dual = <0>; 15 | num-cs = <1>; 16 | flash0: s25fl512s@0 { 17 | reg = <0x0>; 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | compatible = "s25fl512s"; 21 | spi-max-frequency = <0x2faf080>; 22 | spi-tx-bus-width = <0x1>; 23 | spi-rx-bus-width = <0x4>; 24 | partition@0x00000000 { 25 | label = "boot"; 26 | reg = <0x0 0x500000>; 27 | }; 28 | partition@0x00500000 { 29 | label = "bootenv"; 30 | reg = <0x500000 0x40000>; 31 | }; 32 | partition@0x00540000 { 33 | label = "data"; 34 | reg = <0x540000 0xb00000>; 35 | }; 36 | }; 37 | }; 38 | 39 | / { 40 | amba_pl: amba_pl { 41 | #address-cells = <1>; 42 | #size-cells = <1>; 43 | compatible = "simple-bus"; 44 | ranges ; 45 | panda_pcap_0: panda_pcap@a0000000 { 46 | compatible = "xlnx,panda-pcap-1.0"; 47 | reg = <0xa0000000 0x20000>; 48 | interrupt-parent = <&gic>; 49 | interrupts = <0 89 1>; 50 | }; 51 | }; 52 | }; 53 | -------------------------------------------------------------------------------- /targets/PandABrick/target_incl.tcl: -------------------------------------------------------------------------------- 1 | set FPGA_PART xczu4cg-sfvc784-1-e 2 | set HDL_TOP PandABrick_top 3 | 4 | # Target specific Constriants to be read 5 | # NB: we could just read the entire directory with 'add_files [glob $TARGET_DIR/const/*.xdc] 6 | set CONSTRAINTS { \ 7 | PandABrick-pins_impl.xdc \ 8 | PandABrick-clks.xdc 9 | } 10 | 11 | -------------------------------------------------------------------------------- /targets/ZedBoard/ZedBoard.target.ini: -------------------------------------------------------------------------------- 1 | # Ini file for the carrier blocks for PandABox. This replaces the panda_carrier 2 | # module. The config files for each carrier block can be found in 3 | # blocks/blockname 4 | [.] 5 | io: fmc: 1 6 | 7 | [PCAP] 8 | number: 1 9 | 10 | [ZEDBOARD_DEMO] 11 | number:1 12 | 13 | -------------------------------------------------------------------------------- /targets/ZedBoard/etc/load-panda-firmware: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Script to load Panda FPGA image 4 | 5 | # This is called directly by the /opt/etc/init.d/panda-server script and relies 6 | # on panda-server being installed 7 | 8 | # File locations 9 | carrier_firmware=/opt/share/panda-fpga/panda_top.bin 10 | check_ipmi=/opt/bin/check_ipmi 11 | 12 | fail() 13 | { 14 | echo >&2 "$@" 15 | exit 1 16 | } 17 | 18 | load_fpga() 19 | { 20 | local bitstream="$1" 21 | local name="$(basename $bitstream)" 22 | # Set flags for loading full bitstream 23 | echo 0 > /sys/class/fpga_manager/fpga0/flags 24 | ln -sf $bitstream /opt/firmware/$name 25 | echo $name > /sys/class/fpga_manager/fpga0/firmware 26 | } 27 | 28 | [ -e $carrier_firmware ] || 29 | fail "Firmware not installed" 30 | 31 | # Check whether the FMC IPMI configuration matches that expected by the FPGA 32 | $check_ipmi && 33 | 34 | # If FMC passes then load the carrier firmware 35 | load_fpga $carrier_firmware 36 | 37 | -------------------------------------------------------------------------------- /targets/ZedBoard/etc/panda-fpga.list: -------------------------------------------------------------------------------- 1 | # Directory structure 2 | d share/panda-fpga/config_d 3 | d share/template_designs 4 | d share/www 5 | d lib/python/site-packages/i2c 6 | d etc/www 7 | d bin 8 | d firmware 9 | 10 | # Configuration files 11 | b share/panda-fpga/config_d autogen/config_d/config 12 | b share/panda-fpga/config_d autogen/config_d/registers 13 | b share/panda-fpga/config_d autogen/config_d/description 14 | b share/panda-fpga ipmi.ini 15 | 16 | # Server startup and helper code 17 | B share/panda-fpga extensions 18 | t share/panda-fpga targets/ZedBoard/etc/load-panda-firmware 19 | 20 | # IPMI python support 21 | T lib/python/site-packages/i2c etc/i2c/*.py 22 | t bin etc/check_ipmi 23 | t bin etc/show_ipmi 24 | 25 | # Firmware 26 | b share/panda-fpga FPGA/panda_top.bin 27 | 28 | # Docs (built once for all zpkgs) 29 | t etc/www etc/panda-fpga.docs.html 30 | T share/template_designs docs/tutorials/*.json 31 | B share/www/panda-fpga ../../html 32 | -------------------------------------------------------------------------------- /targets/ZedBoard/etc/target-defs: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Disable led-daemon 4 | LED_GPIO_BASE= 5 | 6 | get_mac_address() { :; } 7 | -------------------------------------------------------------------------------- /targets/ZedBoard/platform_incl.make: -------------------------------------------------------------------------------- 1 | # Define target platform for cross-compiler 2 | # Either 'zynq' for Zynq-7000 (Default) or 'zynqmp' for Zynq UltraScale+ MPSoC 3 | PLATFORM = zynq 4 | # UBOOT_DTS must match the name in uboot/kernel sources /arch/arm/dts 5 | UBOOT_DTS = "zynq-zed" 6 | # If appropriate DTS file is not included in the kernel sources, \ 7 | # we can specify to use the built DTB for the target instead. \ 8 | # Note this does NOT work for ZedBoard but does for PandABox. 9 | # UBOOT_USE_EXT_DTB = 10 | 11 | -------------------------------------------------------------------------------- /targets/ZedBoard/target-top.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /include/ "system-top.dts.tmp" 3 | 4 | / { 5 | model = "ZedBoard"; 6 | aliases { 7 | ethernet0 = &gem0; 8 | serial0 = &uart1; 9 | }; 10 | chosen { 11 | bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; 12 | }; 13 | memory { 14 | device_type = "memory"; 15 | reg = <0x0 0x20000000>; 16 | }; 17 | }; 18 | 19 | &usb0 { 20 | dr_mode = "host"; 21 | phy_type = "ulpi"; 22 | status = "okay"; 23 | usb-reset = <&gpio0 7 0>; 24 | }; 25 | 26 | &clkc { 27 | fclk-enable = <0xf>; 28 | ps-clk-frequency = <33333333>; 29 | }; 30 | 31 | &qspi { 32 | #address-cells = <1>; 33 | #size-cells = <0>; 34 | flash0: flash@0 { 35 | compatible = "micron,n25q128a13"; 36 | reg = <0x0>; 37 | #address-cells = <1>; 38 | #size-cells = <1>; 39 | spi-max-frequency = <50000000>; 40 | partition@0x00000000 { 41 | label = "boot"; 42 | reg = <0x0 0x500000>; 43 | }; 44 | partition@0x00500000 { 45 | label = "bootenv"; 46 | reg = <0x500000 0x20000>; 47 | }; 48 | partition@0x00520000 { 49 | label = "data"; 50 | reg = <0x520000 0xae0000>; 51 | }; 52 | }; 53 | }; 54 | 55 | / { 56 | amba_pl: amba_pl { 57 | #address-cells = <1>; 58 | #size-cells = <1>; 59 | compatible = "simple-bus"; 60 | ranges ; 61 | panda_pcap_0: panda_pcap@43c00000 { 62 | compatible = "xlnx,panda-pcap-1.0"; 63 | interrupt-parent = <&intc>; 64 | interrupts = <0 29 1>; 65 | reg = <0x43c00000 0x20000>; 66 | xlnx,s00-axi-addr-width = <0x17>; 67 | xlnx,s00-axi-data-width = <0x20>; 68 | }; 69 | }; 70 | }; 71 | -------------------------------------------------------------------------------- /targets/ZedBoard/target_incl.tcl: -------------------------------------------------------------------------------- 1 | set FPGA_PART xc7z020clg484-1 2 | set HDL_TOP ZedBoard_top 3 | 4 | # Target specific Constriants to be read 5 | # NB: we could just read the entire directory with 'add_files [glob $TARGET_DIR/const/*.xdc] 6 | set CONSTRAINTS { \ 7 | ZedBoard-pins_impl.xdc 8 | } 9 | 10 | -------------------------------------------------------------------------------- /targets/xu5_st1/const/FMC_MGT1_pins.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # FMC MGT1 pins - Bank 224 3 | # ------------------------------------------------------------------- 4 | 5 | set_property PACKAGE_PIN Y2 [get_ports {FMC_DP_M2C_P[0]}]; 6 | set_property PACKAGE_PIN Y1 [get_ports {FMC_DP_M2C_N[0]}]; 7 | set_property PACKAGE_PIN W4 [get_ports {FMC_DP_C2M_P[0]}]; 8 | set_property PACKAGE_PIN W3 [get_ports {FMC_DP_C2M_N[0]}]; 9 | 10 | -------------------------------------------------------------------------------- /targets/xu5_st1/const/FMC_MGT2_pins.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # FMC MGT2 pins - Bank 224 3 | # ------------------------------------------------------------------- 4 | 5 | set_property PACKAGE_PIN V2 [get_ports {FMC_DP_M2C_P[1]}]; 6 | set_property PACKAGE_PIN V1 [get_ports {FMC_DP_M2C_N[1]}]; 7 | set_property PACKAGE_PIN U4 [get_ports {FMC_DP_C2M_P[1]}]; 8 | set_property PACKAGE_PIN U3 [get_ports {FMC_DP_C2M_N[1]}]; 9 | 10 | -------------------------------------------------------------------------------- /targets/xu5_st1/const/FMC_MGT3_pins.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # FMC MGT3 pins - Bank 224 3 | # ------------------------------------------------------------------- 4 | 5 | set_property PACKAGE_PIN T2 [get_ports {FMC_DP_M2C_P[2]}]; 6 | set_property PACKAGE_PIN T1 [get_ports {FMC_DP_M2C_N[2]}]; 7 | set_property PACKAGE_PIN R4 [get_ports {FMC_DP_C2M_P[2]}]; 8 | set_property PACKAGE_PIN R3 [get_ports {FMC_DP_C2M_N[2]}]; 9 | 10 | -------------------------------------------------------------------------------- /targets/xu5_st1/const/FMC_MGT4_pins.xdc: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------- 2 | # FMC MGT4 pins - Bank 224 3 | # ------------------------------------------------------------------- 4 | 5 | set_property PACKAGE_PIN P2 [get_ports {FMC_DP_M2C_P[3]}]; 6 | set_property PACKAGE_PIN P1 [get_ports {FMC_DP_M2C_N[3]}]; 7 | set_property PACKAGE_PIN N4 [get_ports {FMC_DP_C2M_P[3]}]; 8 | set_property PACKAGE_PIN N3 [get_ports {FMC_DP_C2M_N[3]}]; 9 | 10 | -------------------------------------------------------------------------------- /targets/xu5_st1/const/xu5_st1-clks.xdc: -------------------------------------------------------------------------------- 1 | # Clock constraints for clocks provided as inputs to the core 2 | # Note: the IP core-level XDC constrains clocks produced by the core, which drive user clocks via helper blocks 3 | # ---------------------------------------------------------------------------------------------------------------------- 4 | create_clock -period 8.000 [get_ports GTXCLK0_P] 5 | create_clock -period 8.000 [get_ports GTXCLK1_P] 6 | 7 | set_clock_groups -asynchronous -group GTXCLK0_P 8 | set_clock_groups -asynchronous -group GTXCLK1_P 9 | 10 | -------------------------------------------------------------------------------- /targets/xu5_st1/etc/load-panda-firmware: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Script to load Panda FPGA image 4 | 5 | # This is called directly by the /opt/etc/init.d/panda-server script and relies 6 | # on panda-server being installed 7 | 8 | # File locations 9 | carrier_firmware=/opt/share/panda-fpga/panda_top.bin 10 | check_ipmi=/opt/bin/check_ipmi 11 | 12 | fail() 13 | { 14 | echo >&2 "$@" 15 | exit 1 16 | } 17 | 18 | load_fpga() 19 | { 20 | local bitstream="$1" 21 | local name="$(basename $bitstream)" 22 | # Set flags for loading full bitstream 23 | echo 0 > /sys/class/fpga_manager/fpga0/flags 24 | ln -sf $bitstream /opt/firmware/$name 25 | echo $name > /sys/class/fpga_manager/fpga0/firmware 26 | } 27 | 28 | [ -e $carrier_firmware ] || 29 | fail "Firmware not installed" 30 | 31 | # Check whether the FMC IPMI configuration matches that expected by the FPGA 32 | $check_ipmi && 33 | 34 | # If FMC passes then load the carrier firmware 35 | load_fpga $carrier_firmware 36 | 37 | -------------------------------------------------------------------------------- /targets/xu5_st1/etc/panda-fpga.list: -------------------------------------------------------------------------------- 1 | # Directory structure 2 | d share/panda-fpga/config_d 3 | d share/template_designs 4 | d share/www 5 | d lib/python/site-packages/i2c 6 | d etc/www 7 | d bin 8 | d firmware 9 | 10 | # Configuration files 11 | b share/panda-fpga/config_d autogen/config_d/config 12 | b share/panda-fpga/config_d autogen/config_d/registers 13 | b share/panda-fpga/config_d autogen/config_d/description 14 | b share/panda-fpga ipmi.ini 15 | 16 | # Server startup and helper code 17 | B share/panda-fpga extensions 18 | t share/panda-fpga targets/xu5_st1/etc/load-panda-firmware 19 | 20 | # IPMI python support 21 | T lib/python/site-packages/i2c etc/i2c/*.py 22 | t bin etc/check_ipmi 23 | t bin etc/show_ipmi 24 | 25 | # Firmware 26 | b share/panda-fpga FPGA/panda_top.bin 27 | 28 | # Docs (built once for all zpkgs) 29 | t etc/www etc/panda-fpga.docs.html 30 | T share/template_designs docs/tutorials/*.json 31 | B share/www/panda-fpga ../../html 32 | -------------------------------------------------------------------------------- /targets/xu5_st1/etc/target-defs: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # LED daemon definitions 4 | LED_GPIO_BASE=334 5 | STA_LED_OFFSET=25 6 | DIA_LED_OFFSET=24 7 | 8 | get_mac_address() { :; } 9 | 10 | target_specific_start() { 11 | # Show hostname, IP and link status in the OLED display 12 | if [ -e /sys/class/graphics/fb0 ]; then 13 | cat /sys/class/graphics/fb0/modes > /sys/class/graphics/fb0/mode 14 | cat < /var/run/show-status.sh 15 | #!/bin/sh 16 | while true; do 17 | clear; hostname -s 18 | ip addr show eth0 | head -n3 | tail -n1 | cut -d' ' -f 6 19 | [ \$(cat /sys/class/net/eth0/carrier) -eq 1 ] && 20 | echo "Link up" || echo "Link down" 21 | sleep 2 22 | done 23 | EOF 24 | chmod +x /var/run/show-status.sh 25 | fbpad /var/run/show-status.sh & 26 | fi 27 | } 28 | -------------------------------------------------------------------------------- /targets/xu5_st1/platform_incl.make: -------------------------------------------------------------------------------- 1 | # Define target platform for cross-compiler 2 | # Either 'zynq' for Zynq-7000 (Default) or 'zynqmp' for Zynq UltraScale+ MPSoC 3 | PLATFORM = zynqmp 4 | UBOOT_USE_EXT_DTB = 1 5 | -------------------------------------------------------------------------------- /targets/xu5_st1/target-top.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /include/ "system-top.dts.tmp" 3 | 4 | &sdhci1 { 5 | disable-wp; 6 | no-1-8-v; 7 | }; 8 | 9 | &i2c0 { 10 | clock-frequency = <100000>; 11 | ssd1306: oled@0x3c { 12 | compatible = "solomon,ssd1306"; 13 | reg = <0x3c>; 14 | solomon,height = <64>; 15 | solomon,width = <128>; 16 | solomon,page-offset = <0>; 17 | solomon,segment-no-remap; 18 | }; 19 | }; 20 | 21 | &qspi { 22 | is-dual = <0>; 23 | num-cs = <1>; 24 | flash0: s25fl512s@0 { 25 | reg = <0x0>; 26 | #address-cells = <1>; 27 | #size-cells = <1>; 28 | compatible = "s25fl512s"; 29 | spi-max-frequency = <0x2faf080>; 30 | spi-tx-bus-width = <0x1>; 31 | spi-rx-bus-width = <0x4>; 32 | partition@0x00000000 { 33 | label = "boot"; 34 | reg = <0x0 0x500000>; 35 | }; 36 | partition@0x00500000 { 37 | label = "bootenv"; 38 | reg = <0x500000 0x40000>; 39 | }; 40 | partition@0x00540000 { 41 | label = "data"; 42 | reg = <0x540000 0xb00000>; 43 | }; 44 | }; 45 | }; 46 | 47 | / { 48 | amba_pl: amba_pl { 49 | #address-cells = <1>; 50 | #size-cells = <1>; 51 | compatible = "simple-bus"; 52 | ranges ; 53 | panda_pcap_0: panda_pcap@a0000000 { 54 | compatible = "xlnx,panda-pcap-1.0"; 55 | reg = <0xa0000000 0x20000>; 56 | interrupt-parent = <&gic>; 57 | interrupts = <0 89 1>; 58 | }; 59 | }; 60 | }; 61 | -------------------------------------------------------------------------------- /targets/xu5_st1/target_incl.tcl: -------------------------------------------------------------------------------- 1 | set FPGA_PART xczu4ev-sfvc784-1-i 2 | set HDL_TOP xu5_st1_top 3 | 4 | # Target specific Constriants to be read 5 | # NB: we could just read the entire directory with 'add_files [glob $TARGET_DIR/const/*.xdc] 6 | set CONSTRAINTS { \ 7 | xu5_st1-pins_impl.xdc \ 8 | xu5_st1-clks.xdc 9 | } 10 | 11 | -------------------------------------------------------------------------------- /targets/xu5_st1/xu5_st1.target.ini: -------------------------------------------------------------------------------- 1 | # Ini file for the carrier blocks for PandABox. This replaces the panda_carrier 2 | # module. The config files for each carrier block can be found in 3 | # blocks/blockname 4 | [.] 5 | io: fmc: 1 6 | fmc_mgt: mgt, 4* 7 | 8 | [TTLIN] 9 | number: 1 10 | 11 | [PCAP] 12 | number: 1 13 | 14 | [US_SYSTEM] 15 | number: 1 16 | -------------------------------------------------------------------------------- /tests/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/tests/__init__.py -------------------------------------------------------------------------------- /tests/python/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/PandABlocks/PandABlocks-FPGA/61de7b013800c8503b19cf51ac46cc182e87e699/tests/python/__init__.py -------------------------------------------------------------------------------- /tests/python/build/etc/panda-fpga.list: -------------------------------------------------------------------------------- 1 | # AUTOGENERATED 2 | # Configuration files 3 | d share/panda/config_d 4 | t share/panda/config_d apps/test/config_d/config 5 | t share/panda/config_d apps/test/config_d/registers 6 | t share/panda/config_d apps/test/config_d/description 7 | # Firmware 8 | b share/panda apps/test/panda_top.bit 9 | b share/panda apps/test/SlowFPGA/slow_top.bin 10 | -------------------------------------------------------------------------------- /tests/python/test_block_simulation.py: -------------------------------------------------------------------------------- 1 | try: 2 | from pkg_resources import require 3 | except ImportError: 4 | pass 5 | else: 6 | require("numpy") 7 | 8 | import unittest 9 | 10 | from common.python.simulations import BlockSimulation, properties_from_ini 11 | 12 | 13 | # Finding relative to a file, give it something in the test_data dir 14 | NAMES, PROPERTIES = properties_from_ini(__file__.replace( 15 | "/test_block_simulation.py", "/test_data/anything.py"), "test.block.ini") 16 | 17 | 18 | class MyTest(BlockSimulation): 19 | FUNC, A, INPA, OUT = PROPERTIES 20 | 21 | 22 | class TestBlockSimulation(unittest.TestCase): 23 | maxDiff = None 24 | 25 | def setUp(self): 26 | self.o = MyTest() 27 | 28 | def test_setter(self): 29 | assert self.o.changes is None 30 | self.o.OUT = 45 31 | assert self.o.OUT == 45 32 | assert self.o.changes == dict(OUT=45) 33 | self.o.A = 46 34 | assert self.o.changes == dict(OUT=45, A=46) 35 | self.o.OUT = 48 36 | assert self.o.OUT == 48 37 | assert self.o.changes == dict(OUT=48, A=46) 38 | 39 | def test_bad_fields(self): 40 | with self.assertRaises(AssertionError) as cm: 41 | class MyBad(BlockSimulation): 42 | BAD, A, INPA, OUT = PROPERTIES 43 | 44 | assert str(cm.exception) == \ 45 | "Property BAD mismatch with Config name FUNC" 46 | 47 | 48 | if __name__ == '__main__': 49 | unittest.main() -------------------------------------------------------------------------------- /tests/python/test_configs.py: -------------------------------------------------------------------------------- 1 | import unittest 2 | 3 | from common.python.configs import BlockConfig, FieldConfig 4 | 5 | 6 | class TestConfigs(unittest.TestCase): 7 | def test_bad_block_name(self): 8 | with self.assertRaises(AssertionError) as cm: 9 | BlockConfig("LUT3", "soft", 1, "path/to/block.ini") 10 | self.assertEqual( 11 | "Expected BLOCK_NAME with no trailing numbers, got 'LUT3'", 12 | str(cm.exception)) 13 | 14 | def test_bad_field_name(self): 15 | with self.assertRaises(AssertionError) as cm: 16 | FieldConfig("bad_field", 1, "param", "", {}) 17 | self.assertEqual("Expected FIELD_NAME, got 'bad_field'", 18 | str(cm.exception)) 19 | -------------------------------------------------------------------------------- /tests/python/test_data/app-expected/config_d/config: -------------------------------------------------------------------------------- 1 | *METADATA 2 | APPNAME constant =test 3 | DESIGN string 4 | LAYOUT multiline 5 | EXPORTS multiline 6 | LABEL_LUT1 string 7 | LABEL_LUT2 string 8 | LABEL_LUT3 string 9 | LABEL_LUT4 string 10 | LABEL_LUT5 string 11 | LABEL_LUT6 string 12 | LABEL_LUT7 string 13 | LABEL_LUT8 string 14 | 15 | LUT[8] 16 | INPA bit_mux 17 | INPB bit_mux 18 | INPC bit_mux 19 | INPD bit_mux 20 | INPE bit_mux 21 | TYPEA param enum 22 | 0 Input-Level 23 | 1 Pulse-On-Rising-Edge 24 | 2 Pulse-On-Falling-Edge 25 | 3 Pulse-On-Either-Edge 26 | TYPEB param enum 27 | 0 Input-Level 28 | 1 Pulse-On-Rising-Edge 29 | 2 Pulse-On-Falling-Edge 30 | 3 Pulse-On-Either-Edge 31 | TYPEC param enum 32 | 0 Input-Level 33 | 1 Pulse-On-Rising-Edge 34 | 2 Pulse-On-Falling-Edge 35 | 3 Pulse-On-Either-Edge 36 | TYPED param enum 37 | 0 Input-Level 38 | 1 Pulse-On-Rising-Edge 39 | 2 Pulse-On-Falling-Edge 40 | 3 Pulse-On-Either-Edge 41 | TYPEE param enum 42 | 0 Input-Level 43 | 1 Pulse-On-Rising-Edge 44 | 2 Pulse-On-Falling-Edge 45 | 3 Pulse-On-Either-Edge 46 | FUNC param lut 47 | OUT bit_out 48 | 49 | -------------------------------------------------------------------------------- /tests/python/test_data/app-expected/config_d/description: -------------------------------------------------------------------------------- 1 | LUT Lookup table 2 | INPA Input A 3 | INPB Input B 4 | INPC Input C 5 | INPD Input D 6 | INPE Input E 7 | TYPEA Source of the value of A for calculation 8 | TYPEB Source of the value of B for calculation 9 | TYPEC Source of the value of C for calculation 10 | TYPED Source of the value of D for calculation 11 | TYPEE Source of the value of E for calculation 12 | FUNC Input func 13 | OUT Lookup table output 14 | 15 | -------------------------------------------------------------------------------- /tests/python/test_data/app-expected/usage.txt: -------------------------------------------------------------------------------- 1 | #################################### 2 | # Resource usage 3 | # Block addresses: 3/32 4 | # Bit bus: 8/128 5 | # Pos bus: 0/32 6 | # Ext bus: 0/32 7 | #################################### 8 | -------------------------------------------------------------------------------- /tests/python/test_data/test.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Test app with only 8 LUTs 3 | target: 4 | options: pcap_std_dev 5 | 6 | [LUT] 7 | number: 8 8 | -------------------------------------------------------------------------------- /tests/python/test_data/test.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Block simulation for test 3 | entity: testblock 4 | 5 | [FUNC] 6 | type: param lut 7 | description: Input func 8 | wstb: true 9 | 10 | [A] 11 | type: param enum 12 | description: Source of the value of A for calculation 13 | 0: Input Value 14 | 1: Rising Edge 15 | 2: Falling Edge 16 | 3: Either Edge 17 | 18 | [INPA] 19 | type: bit_mux 20 | description: Input A 21 | 22 | [OUT] 23 | type: bit_out 24 | description: Lookup table output 25 | -------------------------------------------------------------------------------- /tests/python/test_data/test.timing.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Timing diagrams for test block 3 | scope: test.block.ini 4 | 5 | [First test] 6 | 3 : FUNC=0x36566 -> OUT=1 7 | 5 : -> OUT=0 8 | 6 : FUNC=34 9 | 8 : INPA=1 -> OUT=1 10 | 11 | [Second test] 12 | 3 : A=1 13 | -------------------------------------------------------------------------------- /tests/python/test_data/timing-expected/testblock.tcl: -------------------------------------------------------------------------------- 1 | # AUTOGENERATED 2 | # This is a script to add all of the tests and required hdl code for the 3 | # testblock module to the vivado project 4 | 5 | set_property SOURCE_SET sources_1 [get_filesets sim_1] 6 | 7 | array set tests { 8 | testblock_1_tb 1 9 | testblock_2_tb 1 10 | } 11 | 12 | # add the module vhd code 13 | add_files -norecurse $TOP_DIR/modules/testblock/hdl 14 | 15 | # read xci files for any IP required by module 16 | 17 | add_files -fileset sim_1 -norecurse \ 18 | $BUILD_DIR/hdl_timing/testblock/timing001/hdl_timing.sv \ 19 | $BUILD_DIR/hdl_timing/testblock/timing001/1testblockexpected.csv \ 20 | $BUILD_DIR/hdl_timing/testblock/timing002/hdl_timing.sv \ 21 | $BUILD_DIR/hdl_timing/testblock/timing002/2testblockexpected.csv \ 22 | $TOP_DIR/modules/testblock/ 23 | -------------------------------------------------------------------------------- /tests/python/test_data/timing-expected/timing001/1testblockexpected.csv: -------------------------------------------------------------------------------- 1 | TS FUNC FUNC_wstb A INPA OUT 2 | 3 222566 1 0 0 0 3 | 4 222566 0 0 0 1 4 | 6 34 1 0 0 0 5 | 7 34 0 0 0 0 6 | 8 34 0 0 1 0 7 | 9 34 0 0 1 1 8 | -------------------------------------------------------------------------------- /tests/python/test_data/timing-expected/timing002/2testblockexpected.csv: -------------------------------------------------------------------------------- 1 | TS FUNC FUNC_wstb A INPA OUT 2 | 3 0 0 1 0 0 3 | -------------------------------------------------------------------------------- /tests/python/test_data_calc_extensions/calc_extension.app.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Test app with only 8 LUTs 3 | target: 4 | 5 | [DUMMY] 6 | number: 5 7 | 8 | [INTERVAL] 9 | number: 3 10 | 11 | [FMC] 12 | module: fmc_acq427 13 | -------------------------------------------------------------------------------- /tests/python/test_data_calc_extensions/dummy/dummy.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Dummy test extension registers 3 | entity: dummy 4 | 5 | [DUMMY_READ_0] 6 | description: 7 | type: extension_read 8 | 9 | [DUMMY_READ_1] 10 | description: 11 | type: extension_read 12 | 13 | [DUMMY_READ_2] 14 | description: 15 | type: extension_read 16 | 17 | [DUMMY_READ_3] 18 | description: 19 | type: extension_read 20 | 21 | [DUMMY_WRITE] 22 | description: 23 | type: extension_write 24 | 25 | [DUMMY_R] 26 | description: Reads a single register 27 | type: read 28 | extension: dummy 29 | extension_read: DUMMY_READ_0 DUMMY_READ_1 DUMMY_READ_2 DUMMY_READ_3 30 | 31 | [DUMMY_W] 32 | description: Writes a single register 33 | type: write 34 | extension: dummy 35 | extension_read: DUMMY_READ_0 DUMMY_READ_1 DUMMY_READ_2 DUMMY_READ_3 36 | extension_write: DUMMY_WRITE 37 | 38 | [POLY_R] 39 | description: Reads a group of registers 40 | type: read 41 | extension: poly 42 | extension_read: DUMMY_READ_0 DUMMY_READ_1 DUMMY_READ_2 DUMMY_READ_3 43 | 44 | [POLY_W] 45 | description: Writes a group of registers 46 | type: write 47 | extension: poly 48 | extension_read: DUMMY_READ_0 DUMMY_READ_1 DUMMY_READ_2 DUMMY_READ_3 49 | extension_write: DUMMY_READ_0 DUMMY_READ_1 DUMMY_READ_2 DUMMY_READ_3 DUMMY_WRITE 50 | 51 | -------------------------------------------------------------------------------- /tests/python/test_data_calc_extensions/interval/interval.block.ini: -------------------------------------------------------------------------------- 1 | [.] 2 | description: Calculated registers interval test 3 | entity: interval 4 | 5 | [BOTTOM] 6 | description: 7 | type: extension_write 8 | 9 | [CENTRE] 10 | description: 11 | type: param 12 | extension: centre 13 | extension_write: BOTTOM TOP 14 | 15 | [RANGE] 16 | description: 17 | type: param 18 | extension: range 19 | extension_write: BOTTOM TOP 20 | initial_value: 0 21 | 22 | [TOP] 23 | description: 24 | type: extension_write 25 | -------------------------------------------------------------------------------- /tests/python/test_parse_git_version.py: -------------------------------------------------------------------------------- 1 | import unittest 2 | from common.python.parse_git_version import parse_git_version 3 | 4 | 5 | class TestParseGitVersion(unittest.TestCase): 6 | def test_clean_value(self): 7 | self.assertEqual("00000300", 8 | parse_git_version("0.3")) 9 | 10 | def test_dirty_value(self): 11 | self.assertEqual("00000300", 12 | parse_git_version("0.3-dirty")) 13 | 14 | def test_clean_value_with_changes(self): 15 | self.assertEqual("0b000100", 16 | parse_git_version("0.1-11-g5539563")) 17 | 18 | def test_dirty_value_with_changes(self): 19 | self.assertEqual("0b000100", 20 | parse_git_version("0.1-11-g5539563-dirty")) 21 | 22 | def test_bad_value(self): 23 | with self.assertRaises(AssertionError): 24 | parse_git_version("loads_of_junk") 25 | 26 | 27 | if __name__ == '__main__': 28 | unittest.main() 29 | -------------------------------------------------------------------------------- /tests/requirements.txt: -------------------------------------------------------------------------------- 1 | numpy 2 | jinja2 3 | -------------------------------------------------------------------------------- /tests/sim/finedelay/bench/finedelay_tb_compile.tcl: -------------------------------------------------------------------------------- 1 | set TOP [lindex $argv 0] 2 | set BUILD_DIR [lindex $argv 1] 3 | set MODE [lindex $argv 2] 4 | 5 | create_project finedelay_tb $BUILD_DIR/build/tests/finedelay_tb -force -part xc7z030sbg485-1 6 | 7 | set_property top finedelay_tb [current_fileset -simset] 8 | add_files [glob $TOP/common/hdl/*.vhd] 9 | add_files $TOP/tests/sim/finedelay/bench 10 | set_property FILE_TYPE "VHDL 2008" [get_files $TOP/tests/sim/finedelay/bench/*.vhd] 11 | 12 | launch_simulation 13 | restart 14 | run -all 15 | -------------------------------------------------------------------------------- /tests/sim/sequencer_double_table/bench/sequencer_double_table_tb_compile.tcl: -------------------------------------------------------------------------------- 1 | set TOP [lindex $argv 0] 2 | set BUILD_DIR [lindex $argv 1] 3 | set MODE [lindex $argv 2] 4 | set TARGET sequencer_double_table 5 | set TEST ${TARGET}_tb 6 | 7 | create_project $TEST $BUILD_DIR/build/tests/$TEST -force -part xc7z030sbg485-1 8 | 9 | set_property top $TEST [current_fileset -simset] 10 | add_files $TOP/common/hdl/ 11 | add_files [glob $TOP/modules/seq/hdl/*.vhd] 12 | add_files $TOP/tests/sim/$TARGET/bench 13 | set_property FILE_TYPE "VHDL 2008" [get_files *.vhd] 14 | 15 | launch_simulation 16 | run -all 17 | -------------------------------------------------------------------------------- /tests/sim/sequencer_double_table/bench/top_defines_gen.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package top_defines_gen is 5 | 6 | -------------------------------------------------------------------------- 7 | -- !!! Remember to add aliases for any new entities here to top_defines 8 | -------------------------------------------------------------------------- 9 | 10 | -- Bit Bus Width, Multiplexer Select Width ------------------------------- 11 | constant BBUSW : natural := 128; 12 | constant BBUSBW : natural := 7; 13 | 14 | -- Position Bus Width, Multiplexer Select Width. 15 | constant PBUSW : natural := 26; 16 | constant PBUSBW : natural := 5; 17 | 18 | -- Extended Position Bus Width. 19 | constant EBUSW : natural := 12; 20 | -------------------------------------------------------------------------- 21 | 22 | -- FPGA options 23 | constant PCAP_STD_DEV_OPTION : std_logic := '1'; 24 | constant FINE_DELAY_OPTION : std_logic := '0'; 25 | 26 | end top_defines_gen; 27 | --------------------------------------------------------------------------------