├── MAC ├── adder │ ├── buffer2.v │ ├── compshift.v │ ├── faddsub.v │ ├── fpadd.v │ ├── normalized.v │ └── test_bench.v ├── fp_add.JPG ├── fp_mac.JPG ├── fp_mac.v ├── fp_mul.JPG ├── multiplier │ ├── bigalu23bit.v │ ├── carrysaveadder.v │ ├── fpmul.v │ ├── full_adder.v │ ├── half_adder.v │ ├── mux32bit2_1.v │ ├── nleftshift.v │ ├── nrightshift.v │ ├── rca24bit.v │ ├── round.v │ ├── smallalu.v │ ├── test_bench.v │ ├── twoscompliment.v │ └── wallace_tree.v └── test_bench.v └── README.md /MAC/adder/buffer2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 29.11.2018 11:45:41 7 | // Design Name: 8 | // Module Name: buffer2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module buffer2(mxy1,s3,sr1,ex,sn3,sn4,clk,mxy2,ex3,sn5,sn6,s4,sr2); 23 | input [24:0]mxy1; 24 | input s3,clk,sr1,sn3,sn4; 25 | input [7:0]ex; 26 | output reg[24:0]mxy2; 27 | output reg[7:0]ex3; 28 | output reg s4,sn5,sn6,sr2; 29 | always@(posedge clk) 30 | begin 31 | sr2=sr1; 32 | sn5=sn3; 33 | sn6=sn4; 34 | ex3=ex; 35 | mxy2=mxy1; 36 | s4=s3; 37 | end 38 | endmodule -------------------------------------------------------------------------------- /MAC/adder/compshift.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 29.11.2018 11:49:07 7 | // Design Name: 8 | // Module Name: compshift 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module cmpshift(e1,e2,s1,s2,m1,m2,clk,ex,ey,mx,my,s,sx1,sy1); //module for copare &shift 23 | input [7:0]e1,e2; 24 | input [23:0]m1,m2; 25 | input clk,s1,s2; 26 | output reg[7:0]ex,ey; 27 | output reg[23:0]mx,my; 28 | output reg s,sx1,sy1; 29 | reg [7:0]diff; 30 | always@(posedge clk) 31 | begin 32 | sx1=s1; 33 | sy1=s2; 34 | if(e1==e2) 35 | begin 36 | ex=e1+8'b1; 37 | ey=e2+8'b1; 38 | mx=m1; 39 | my=m2; 40 | s=1'b1; 41 | end 42 | else if(e1>e2) 43 | begin 44 | diff=e1-e2; 45 | ex=e1+8'b1; 46 | ey=e1+8'b1; 47 | mx=m1; 48 | my=m2>>diff; 49 | s=1'b1; 50 | end 51 | else 52 | begin 53 | diff=e2-e1; 54 | ex=e2+8'b1; 55 | ey=e2+8'b1; 56 | mx=m2; 57 | my=m1>>diff; 58 | s=1'b0; 59 | end 60 | end 61 | endmodule -------------------------------------------------------------------------------- /MAC/adder/faddsub.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 29.11.2018 11:48:07 7 | // Design Name: 8 | // Module Name: faddsub 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module faddsub(a,b,s1,s2,sn,ex1,clk,out,ex2,sn3,sn4,s,sr1); //submodule for addition or subtraction 23 | input [23:0]a,b; 24 | input[7:0]ex1; 25 | input s1,s2,clk,sn; 26 | output reg [23:0]ex2; 27 | output reg[24:0]out; 28 | output reg s,sn3,sn4,sr1; 29 | always@(posedge clk) 30 | begin 31 | ex2=ex1; 32 | sr1=sn; 33 | sn3=s1; 34 | sn4=s2; 35 | s=s1^s2; 36 | if(s) 37 | begin 38 | out=a-b; 39 | end 40 | else 41 | begin 42 | out=a+b; 43 | end 44 | end 45 | endmodule -------------------------------------------------------------------------------- /MAC/adder/fpadd.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16.11.2018 11:53:54 7 | // Design Name: 8 | // Module Name: add 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module fpadd(a,b,clk,out); 23 | input[31:0]a,b; 24 | input clk; 25 | output [31:0]out; 26 | wire [7:0]e1,e2,ex,ey,exy,ex1,ey1,ex2,ex3; 27 | wire s1,s2,s,s3,sr,sn,s4,sx1,sy1,sn1,sn2,sn3,sn4,sr1,sr2,sn5,sn6; 28 | wire [23:0]m1,m2,mx,my,mxy,mx1,my1; 29 | wire [24:0]mxy1,mxy2; 30 | assign s1=a[31]; 31 | assign s2=b[31]; 32 | assign e1=a[30:23]; 33 | assign e2=b[30:23]; 34 | assign m1[23]=1'b1; 35 | assign m2[23]=1'b1; 36 | assign m1[22:0]=a[22:0]; 37 | assign m2[22:0]=b[22:0]; 38 | //submodule for compare and shfit 39 | cmpshift as(e1[7:0],e2[7:0],s1,s2,m1[23:0],m2[23:0],clk,ex,ey,mx,my,s,sx1,sy1); 40 | //buffer1 buff1(ex,ey,sx1,sy1,mx,my,s,clk,ex1,ey1,mx1,my1,sn,sn1,sn2); 41 | //sub module for mantissa addition snd subtraction 42 | faddsub as1(mx,my,sx1,sy1,s,ex,clk,mxy1,ex2,sn3,sn4,s3,sr1); 43 | //faddsub as1(mx1,my1,sn1,sn2,sn,ex1,clk,mxy1,ex2,sn3,sn4,s3,sr1); 44 | buffer2 buff2(mxy1,s3,sr1,ex2,sn3,sn4,clk,mxy2,ex3,sn5,sn6,s4,sr2); 45 | //sub module for normalization 46 | //normalized as2(mxy1,sr1,sn3,sn4,s3,clk,ex3,sr,exy,mxy); 47 | normalized as2(mxy2,sr2,sn5,sn6,s4,clk,ex3,sr,exy,mxy); 48 | assign out={sr,exy,mxy[22:0]}; 49 | endmodule 50 | 51 | -------------------------------------------------------------------------------- /MAC/adder/normalized.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 29.11.2018 11:46:33 7 | // Design Name: 8 | // Module Name: normalise 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module normalized(mxy1,s,s1,s2,s3,clk,ex,sr,exy,mxy); 23 | input[24:0]mxy1; 24 | input s,s1,s2,s3,clk; 25 | input[7:0]ex; 26 | output reg sr; 27 | output reg[7:0]exy; 28 | output reg[23:0]mxy; 29 | reg [24:0]mxy2; 30 | always@(posedge clk) 31 | begin 32 | sr=s?s1^(mxy1[24]&s3):s2^(mxy1[24]&s3); 33 | mxy2=(mxy1[24]&s3)?~mxy1+25'b1:mxy1; 34 | mxy=mxy2[24:1]; 35 | exy=ex; 36 | repeat(24) 37 | begin 38 | if(mxy[23]==1'b0) 39 | begin 40 | mxy=mxy<<1'b1; 41 | exy=exy-8'b1; 42 | end 43 | end 44 | end 45 | endmodule -------------------------------------------------------------------------------- /MAC/adder/test_bench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 28.11.2018 23:37:47 7 | // Design Name: 8 | // Module Name: test_bench 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module test_bench; 24 | 25 | // Inputs 26 | reg clk; 27 | reg [31:0] a; 28 | reg [31:0] b; 29 | 30 | // Outputs 31 | wire [31:0] fadd; 32 | 33 | // Instantiate the Unit Under Test (UUT) 34 | fpadd uut ( 35 | .a(a), 36 | .b(b), 37 | .clk(clk), 38 | .out(fadd) 39 | ); 40 | 41 | initial begin 42 | // Initialize Inputs 43 | clk = 0; 44 | a = 0; 45 | b = 0; 46 | 47 | // Wait 10 ns for global reset to finish 48 | #10; 49 | clk = 0;//01000001101010010100011110101110==21.16 50 | a = 32'b11000000100100110011001100110011;//-4.6; 51 | b = 32'b11000000100100110011001100110011;//-4.6 52 | // Add stimulus here 53 | #20; 54 | clk = 0;//11000000001100001010001111010111==-2.76 55 | a = 32'b11000000100100110011001100110011;//-4.6; 56 | b = 32'b00111111000110011001100110011010;//0.6 57 | // Add stimulus here 58 | #30; 59 | 60 | clk = 0;//10111111111101011100001010001111==-1.92 61 | a = 32'b01000000010011001100110011001101;//3.2; 62 | b = 32'b10111111000110011001100110011010;//-0.6 63 | // Add stimulus here 64 | #40; 65 | clk = 0;//01001010100101010000111101101110==4884407.0 66 | a = 32'b01000101000010100111000011001101;//2215.05; 67 | b = 32'b01000101000010011101000110011010;//2205.10 68 | // Add stimulus here 69 | #50; 70 | clk = 0; 71 | a = 32'b00000100000101001110010100101100;//1750.25; 72 | b = 32'b00000010010100001001100010000010;//1525.19; 73 | // Add stimulus here 74 | #60; 75 | end 76 | always #5 clk=(~clk); 77 | endmodule 78 | -------------------------------------------------------------------------------- /MAC/fp_add.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Parimala6/Floating-point-MAC-verilog/9ffc32bbae5648e415c38900edc098ca2507c6af/MAC/fp_add.JPG -------------------------------------------------------------------------------- /MAC/fp_mac.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Parimala6/Floating-point-MAC-verilog/9ffc32bbae5648e415c38900edc098ca2507c6af/MAC/fp_mac.JPG -------------------------------------------------------------------------------- /MAC/fp_mac.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 29.11.2018 14:33:51 7 | // Design Name: 8 | // Module Name: fp_mac 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module fp_mac(a,b,clk,reset,out); 23 | input[31:0]a,b; 24 | input clk, reset; 25 | output reg [31:0]out; 26 | wire [31:0] fprod, fadd; 27 | reg [31:0] data_a, data_b, fprod1; 28 | 29 | fpmul mul(clk,reset,data_a,data_b,fprod); 30 | fpadd add(fprod1,out,clk,fadd); 31 | 32 | always @(posedge clk) 33 | begin 34 | if(reset) 35 | begin 36 | data_a <= 32'b0; 37 | data_b <= 32'b0; 38 | fprod1 <= 32'b0; 39 | out <= 32'b0; 40 | end 41 | else 42 | begin 43 | data_a <= a; 44 | data_b <= b; 45 | fprod1 <= fprod; 46 | out <= fadd; 47 | end 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /MAC/fp_mul.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Parimala6/Floating-point-MAC-verilog/9ffc32bbae5648e415c38900edc098ca2507c6af/MAC/fp_mul.JPG -------------------------------------------------------------------------------- /MAC/multiplier/bigalu23bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:12:40 04/08/2017 7 | // Design Name: 8 | // Module Name: bigalu23bit 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module bigalu23bit(clk,reset, input1,input2,opcode,alu_out,carry); 22 | parameter width=26; 23 | output reg [width-1:0]alu_out; 24 | output reg carry; 25 | input [width-1:0]input1,input2; 26 | input [3:0]opcode; 27 | input clk,reset; 28 | reg [4:0]lsb5; 29 | always@(posedge clk) 30 | begin 31 | if (reset) 32 | begin 33 | 34 | alu_out=25'b0; 35 | carry=1'b0; 36 | end 37 | else 38 | begin 39 | case(opcode) 40 | 4'b0000: {carry,alu_out} = input1 + input2; 41 | 4'b0001: {carry,alu_out} = input1 - input2; 42 | 4'b0010: alu_out = input1 * input2; 43 | 4'b0011: alu_out = input1 & input2; 44 | 4'b0100: alu_out = input1 | input2; 45 | 4'b0101: alu_out = ~ input1; 46 | 4'b0110: begin 47 | lsb5 = input2[4:0]; 48 | alu_out = input1 << lsb5; 49 | end 50 | 4'b0111: begin 51 | lsb5 = input2[4:0]; 52 | alu_out = input1 >>> lsb5; 53 | end 54 | 4'b1110: begin 55 | lsb5 = input1[4:0]; 56 | alu_out = input1 << lsb5; 57 | end 58 | 4'b1101: begin 59 | lsb5 = input1[4:0]; 60 | alu_out = input1 >>> lsb5; 61 | end 62 | 4'b1111: alu_out[0] = input1[0]; 63 | default: alu_out=25'b0; 64 | 65 | endcase 66 | end 67 | end 68 | endmodule 69 | -------------------------------------------------------------------------------- /MAC/multiplier/carrysaveadder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:30:32 04/03/2017 7 | // Design Name: 8 | // Module Name: carrysaveadder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module carrysaveadder(carry,sum,inp1,inp2,inp3); 22 | parameter width=50; 23 | input [width-1:0]inp1; 24 | 25 | input [width-1:0]inp2; 26 | 27 | input [width-1:0]inp3; 28 | 29 | output [width-1:0]sum; 30 | 31 | output [width:0]carry; 32 | 33 | assign carry[0]=1'b0; 34 | 35 | genvar i; 36 | generate 37 | for(i=0;i<=width-1;i=i+1) 38 | begin:stage 39 | full_adder f1(inp1[i],inp2[i],inp3[i],sum[i],carry[i+1]); 40 | 41 | end 42 | endgenerate 43 | // 44 | //fulladder f2(inp1[1],inp2[1],inp3[1],sum[1],carry[2]); 45 | // 46 | //fulladder f3(inp1[2],inp2[2],inp3[2],sum[2],carry[3]); 47 | // 48 | //fulladder f4(inp1[3],inp2[3],inp3[3],sum[3],carry[4]); 49 | // 50 | //fulladder f5(inp1[4],inp2[4],inp3[4],sum[4],carry[5]); 51 | // 52 | //fulladder f6(inp1[5],inp2[5],inp3[5],sum[5],carry[6]); 53 | // 54 | //fulladder f7(inp1[6],inp2[6],inp3[6],sum[6],carry[7]); 55 | // 56 | //fulladder f8(inp1[7],inp2[7],inp3[7],sum[7],carry[8]); 57 | // 58 | //fulladder f9(inp1[8],inp2[8],inp3[8],sum[8],carry[9]); 59 | // 60 | //fulladder f10(inp1[9],inp2[9],inp3[9],sum[9],carry[10]); 61 | // 62 | //fulladder f11(inp1[10],inp2[10],inp3[10],sum[10],carry[11]); 63 | // 64 | //fulladder f12(inp1[11],inp2[11],inp3[11],sum[11],carry[12]); 65 | // 66 | //fulladder f13(inp1[12],inp2[12],inp3[12],sum[12],carry[13]); 67 | // 68 | //fulladder f14(inp1[13],inp2[13],inp3[13],sum[13],carry[14]); 69 | // 70 | //fulladder f15(inp1[14],inp2[14],inp3[14],sum[14],carry[15]); 71 | // 72 | //fulladder f16(inp1[15],inp2[15],inp3[15],sum[15],carry[16]); 73 | // 74 | //fulladder f17(inp1[16],inp2[16],inp3[16],sum[16],carry[17]); 75 | // 76 | //fulladder f18(inp1[17],inp2[17],inp3[17],sum[17],carry[18]); 77 | // 78 | //fulladder f19(inp1[18],inp2[18],inp3[18],sum[18],carry[19]); 79 | // 80 | //fulladder f20(inp1[19],inp2[19],inp3[19],sum[19],carry[20]); 81 | // 82 | //fulladder f21(inp1[20],inp2[20],inp3[20],sum[20],carry[21]); 83 | // 84 | //fulladder f22(inp1[21],inp2[21],inp3[21],sum[21],carry[22]); 85 | // 86 | //fulladder f23(inp1[22],inp2[22],inp3[22],sum[22],carry[23]); 87 | // 88 | //fulladder f24(inp1[23],inp2[23],inp3[23],sum[23],carry[24]); 89 | // 90 | //fulladder f25(inp1[24],inp2[24],inp3[24],sum[24],carry[25]); 91 | // 92 | //fulladder f26(inp1[25],inp2[25],inp3[25],sum[25],carry[26]); 93 | // 94 | //fulladder f27(inp1[26],inp2[26],inp3[26],sum[26],carry[27]); 95 | // 96 | //fulladder f28(inp1[27],inp2[27],inp3[27],sum[27],carry[28]); 97 | // 98 | //fulladder f29(inp1[28],inp2[28],inp3[28],sum[28],carry[29]); 99 | // 100 | //fulladder f30(inp1[29],inp2[29],inp3[29],sum[29],carry[30]); 101 | // 102 | //fulladder f31(inp1[30],inp2[30],inp3[30],sum[30],carry[31]); 103 | // 104 | //fulladder f32(inp1[31],inp2[31],inp3[31],sum[31],carry[32]); 105 | // 106 | //fulladder f33(inp1[32],inp2[32],inp3[32],sum[32],carry[33]); 107 | // 108 | //fulladder f34(inp1[33],inp2[33],inp3[33],sum[33],carry[34]); 109 | // 110 | //fulladder f35(inp1[34],inp2[34],inp3[34],sum[34],carry[35]); 111 | // 112 | //fulladder f36(inp1[35],inp2[35],inp3[35],sum[35],carry[36]); 113 | // 114 | //fulladder f37(inp1[36],inp2[36],inp3[36],sum[36],carry[37]); 115 | // 116 | //fulladder f38(inp1[37],inp2[37],inp3[37],sum[37],carry[38]); 117 | // 118 | //fulladder f39(inp1[38],inp2[38],inp3[38],sum[38],carry[39]); 119 | // 120 | //fulladder f40(inp1[39],inp2[39],inp3[39],sum[39],carry[40]); 121 | // 122 | //fulladder f41(inp1[40],inp2[40],inp3[40],sum[40],carry[41]); 123 | // 124 | //fulladder f42(inp1[41],inp2[41],inp3[41],sum[41],carry[42]); 125 | // 126 | //fulladder f43(inp1[42],inp2[42],inp3[42],sum[42],carry[43]); 127 | // 128 | //fulladder f44(inp1[43],inp2[43],inp3[43],sum[43],carry[44]); 129 | // 130 | //fulladder f45(inp1[44],inp2[44],inp3[44],sum[44],carry[45]); 131 | // 132 | //fulladder f46(inp1[45],inp2[45],inp3[45],sum[45],carry[46]); 133 | // 134 | //fulladder f47(inp1[46],inp2[46],inp3[46],sum[46],carry[47]); 135 | // 136 | //fulladder f48(inp1[47],inp2[47],inp3[47],sum[47],carry[48]); 137 | // 138 | //fulladder f49(inp1[48],inp2[48],inp3[48],sum[48],carry[49]); 139 | // 140 | //fulladder f50(inp1[49],inp2[49],inp3[49],sum[49],carry[50]); 141 | // 142 | //fulladder f51(inp1[50],inp2[50],inp3[50],sum[50],carry[51]); 143 | // 144 | //fulladder f52(inp1[51],inp2[51],inp3[51],sum[51],carry[52]); 145 | // 146 | //fulladder f53(inp1[52],inp2[52],inp3[52],sum[52],carry[53]); 147 | // 148 | //fulladder f54(inp1[53],inp2[53],inp3[53],sum[53],carry[54]); 149 | // 150 | //fulladder f55(inp1[54],inp2[54],inp3[54],sum[54],carry[55]); 151 | // 152 | //fulladder f56(inp1[55],inp2[55],inp3[55],sum[55],carry[56]); 153 | // 154 | //fulladder f57(inp1[56],inp2[56],inp3[56],sum[56],carry[57]); 155 | // 156 | //fulladder f58(inp1[57],inp2[57],inp3[57],sum[57],carry[58]); 157 | // 158 | //fulladder f59(inp1[58],inp2[58],inp3[58],sum[58],carry[59]); 159 | // 160 | //fulladder f60(inp1[59],inp2[59],inp3[59],sum[59],carry[60]); 161 | // 162 | //fulladder f61(inp1[60],inp2[60],inp3[60],sum[60],carry[61]); 163 | // 164 | //fulladder f62(inp1[61],inp2[61],inp3[61],sum[61],carry[62]); 165 | // 166 | //fulladder f63(inp1[62],inp2[62],inp3[62],sum[62],carry[63]); 167 | // 168 | //fulladder f64(inp1[63],inp2[63],inp3[63],sum[63],carry[64]); 169 | 170 | //assign sum[64]=1'b0; 171 | 172 | endmodule 173 | 174 | 175 | 176 | -------------------------------------------------------------------------------- /MAC/multiplier/fpmul.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 29.11.2018 16:55:48 7 | // Design Name: 8 | // Module Name: fpmul 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module fpmul(clk,reset,a,b,fprod); 23 | parameter w=32; 24 | input [w-1:0] a,b; 25 | input clk,reset; 26 | 27 | output [w-1:0] fprod; 28 | 29 | wire [w-1:0]s1,s2; 30 | wire [w-1-8:0] m1,m2; 31 | wire [w-1-6:0] routm; 32 | wire [w-1-24:0] e1,e2,oe; 33 | wire signa,signb,carry; 34 | 35 | wire [47:0] prod1; 36 | reg [7:0] oute; 37 | reg signout; 38 | reg [47:0] prod; 39 | reg [w-1-6:0]outm; 40 | 41 | assign s1=a; 42 | assign s2=b; 43 | assign e1=s1[30:23]; 44 | assign e2=s2[30:23]; 45 | assign m1[23]=1; 46 | assign m1[22:0]=s1[22:0]; 47 | assign m2[23]=1; 48 | assign m2[22:0]=s2[22:0]; 49 | assign signa=s1[31]; 50 | assign signb=s2[31]; 51 | 52 | smallalu ee(0,clk,reset,e1,e2,oe); 53 | //assign oute=oe+7'b01111111; 54 | //assign signout=(signa^signb); 55 | 56 | wallace_tree v1 (carry,prod1,m1,m2); 57 | 58 | //wallacemultiplier(carryf,product1,inp1,inp2); 59 | 60 | always @ (posedge clk) 61 | begin 62 | if (reset) 63 | begin 64 | outm=26'b0; 65 | oute=8'b0; 66 | signout=1'b0; 67 | prod=48'b0; 68 | end 69 | else if (prod1[47]) 70 | begin 71 | prod=prod1>>1; 72 | outm=prod[46:20]; 73 | oute=oe+8'b01111111+8'b00000001; 74 | signout=(signa^signb); 75 | 76 | end 77 | else 78 | begin 79 | outm=prod1[47:21]; 80 | oute=oe+8'b01111111+8'b00000010; 81 | signout=(signa^signb); 82 | 83 | end 84 | 85 | 86 | 87 | end//always 88 | 89 | round rr (clk,reset,outm,routm); 90 | 91 | assign fprod[31]=signout; 92 | assign fprod[30:23]=oute; 93 | assign fprod[22:0]=routm[24:2]; 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /MAC/multiplier/full_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:45:47 04/15/2017 7 | // Design Name: 8 | // Module Name: full_adder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module full_adder(a,b,cin,sout,cout); 22 | input a,b,cin; 23 | output sout,cout; 24 | assign sout=a^b^cin; 25 | assign cout=(a&b)|(b&cin)|(cin&a); 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /MAC/multiplier/half_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:40:36 04/15/2017 7 | // Design Name: 8 | // Module Name: half_adder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module half_adder(a,b,s,c); 22 | input a,b; 23 | output s,c; 24 | assign s=a^b; 25 | assign c=a&b; 26 | 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /MAC/multiplier/mux32bit2_1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:06:08 04/08/2017 7 | // Design Name: 8 | // Module Name: mux32bit2_1 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mux32bit21( clk,reset,a,b,sel,out); 22 | parameter width=32; 23 | input [width-1:0]a,b; 24 | input sel,clk,reset; 25 | output reg [width-1:0] out; 26 | 27 | always@(posedge clk) 28 | begin 29 | if (reset) 30 | out=32'b0; 31 | 32 | else if (sel) 33 | out=b; 34 | else 35 | out=a; 36 | end 37 | endmodule -------------------------------------------------------------------------------- /MAC/multiplier/nleftshift.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 04:30:37 04/12/2017 7 | // Design Name: 8 | // Module Name: sp 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | ////////////////////////////////////////////////////////////////////////////////// 24 | // Company: 25 | // Engineer: 26 | // 27 | // Create Date: 01:31:59 04/08/2017 28 | // Design Name: 29 | // Module Name: nleftshit 30 | // Project Name: 31 | // Target Devices: 32 | // Tool versions: 33 | // Description: 34 | // 35 | // Dependencies: 36 | // 37 | // Revision: 38 | // Revision 0.01 - File Created 39 | // Additional Comments: 40 | // 41 | ////////////////////////////////////////////////////////////////////////////////// 42 | module nleftshift( clk,reset,a,out,m); 43 | parameter width= 26; 44 | input [width-1:0] a; 45 | input clk,reset; 46 | //wire j[25:0]; 47 | output [width-1:0]out; 48 | output reg [width-1:0]m; 49 | reg [width-1:0]k,s; 50 | //reg n=25'b0; 51 | //integer i; 52 | //assign s=a; 53 | always@( posedge clk) 54 | begin 55 | if(reset) 56 | begin 57 | s=a; 58 | m=25'b0; 59 | k=25'b0; 60 | 61 | end 62 | else if(a[width-1]==0 && s[width-1]==0) 63 | begin 64 | k=s<<1; 65 | s=k; 66 | m=m+1'b1; 67 | //n=m; 68 | end 69 | else 70 | s=k; 71 | 72 | 73 | end //end f 74 | //end always 75 | assign out=k; 76 | 77 | endmodule 78 | 79 | 80 | 81 | 82 | -------------------------------------------------------------------------------- /MAC/multiplier/nrightshift.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 01:37:19 04/08/2017 7 | // Design Name: 8 | // Module Name: nrightshift 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module nrightshift( clk,reset,a,shift,out); 22 | 23 | parameter width= 26; 24 | input [width-1:0] a; 25 | input [width-19:0]shift; 26 | input clk,reset; 27 | output reg [width-1:0] out; 28 | 29 | always@ (posedge clk) 30 | begin 31 | if (reset) 32 | out=26'b0; 33 | else 34 | out = a>>shift; 35 | end 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /MAC/multiplier/rca24bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:59:05 04/03/2017 7 | // Design Name: 8 | // Module Name: rca24bit 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | //`include "rca32bit.v" 22 | 23 | module rca24bit(inp1,inp2,cin,sum,cout); 24 | parameter width=50; 25 | input [width-1:0]inp1; 26 | 27 | input [width-1:0]inp2; 28 | input cin; 29 | 30 | output [width-1:0]sum; 31 | 32 | wire [width:0]c1; 33 | 34 | 35 | output cout; 36 | 37 | assign c1[0]=cin; 38 | assign cout=c1[width]; 39 | genvar i; 40 | generate 41 | for(i=0;i<=width-1;i=i+1) 42 | begin:stage 43 | full_adder f1(inp1[i],inp2[i],c1[i],sum[i],c1[i+1]); 44 | 45 | end 46 | endgenerate 47 | 48 | 49 | 50 | 51 | // 52 | //input [64:0]a; 53 | //input [64:0]b; 54 | // 55 | //input cin; 56 | //output [64:0]sum; 57 | // 58 | //assign sum[64]=1'b0; 59 | // 60 | //output carry; 61 | // 62 | //wire c1; 63 | // 64 | //rca32bit r1(a[31:0],b[31:0],cin,sum[31:0],c1); 65 | // 66 | //rca32bit r2(a[63:32],b[63:32],c1,sum[63:32],carry); 67 | // 68 | endmodule 69 | // 70 | -------------------------------------------------------------------------------- /MAC/multiplier/round.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12:33:20 04/09/2017 7 | // Design Name: 8 | // Module Name: round 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module round(clk,reset,a,out); 22 | parameter width=26; 23 | 24 | input clk,reset; 25 | input [width-1:0] a; 26 | output reg [width-1:0] out; 27 | 28 | reg [width-1:0] temp; 29 | 30 | 31 | 32 | 33 | always @ (posedge clk) 34 | begin 35 | if (reset) 36 | out=26'b0; 37 | else 38 | begin 39 | case (a[2:0]) 40 | 3'b000 : begin 41 | out=a; //round to zero 42 | end 43 | 3'b001 : begin 44 | out=a; //round to zero 45 | end 46 | 3'b010 : begin 47 | out=a; //round to zero 48 | end 49 | 50 | 3'b011 : begin 51 | out={a[25:3] ,3'b100}; 52 | end 53 | 3'b100 : begin 54 | out={a[25:3] ,3'b100}; 55 | end 56 | 3'b101 : begin 57 | out={a[25:3] ,3'b100}; 58 | end 59 | 3'b110 :begin 60 | temp={a[25:3] ,3'b100}; 61 | out[25:2]=temp[25:2]+1; 62 | out[1:0]=2'b0; 63 | end 64 | 3'b111:begin 65 | temp={a[25:3] ,3'b100}; 66 | out[25:2]=temp[25:2]+1; 67 | out[1:0]=2'b0; 68 | end 69 | 70 | default: begin 71 | out=a; 72 | end 73 | endcase 74 | end 75 | end 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /MAC/multiplier/smallalu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:04:23 04/08/2017 7 | // Design Name: 8 | // Module Name: smallalu 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module smallalu(sel,clk,reset,a,b,out ); 22 | 23 | parameter width=8; 24 | input [1:0] sel ; 25 | input reset, clk; 26 | input [width-1:0] a; 27 | input [width-1:0] b; 28 | output reg [width-1:0] out; 29 | 30 | wire [7:0] MUX [0:3]; 31 | 32 | assign MUX[0] = a+b; 33 | assign MUX[1] = a-b; 34 | assign MUX[2] = a^b; 35 | assign MUX[3] = a&b; 36 | 37 | always@(posedge clk) 38 | begin 39 | if (reset) 40 | out<=7'b0; 41 | else 42 | out <= MUX[sel]; 43 | end 44 | endmodule 45 | 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /MAC/multiplier/test_bench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 29.11.2018 16:57:00 7 | // Design Name: 8 | // Module Name: test_bench 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module test_bench; 23 | 24 | // Inputs 25 | reg clk,reset; 26 | reg [31:0] a; 27 | reg [31:0] b; 28 | 29 | // Outputs 30 | wire [31:0] fprod; 31 | 32 | // Instantiate the Unit Under Test (UUT) 33 | fpmul uut ( 34 | .clk(clk), 35 | .reset(reset), 36 | .a(a), 37 | .b(b), 38 | .fprod(fprod) 39 | ); 40 | 41 | initial begin 42 | // Initialize Inputs 43 | clk = 0; 44 | reset = 0; 45 | a = 0; 46 | b = 0; 47 | 48 | // Wait 100 ns for global reset to finish 49 | #100; 50 | clk = 0;//01000001101010010100011110101110==21.16 51 | a = 32'b11000000100100110011001100110011;//-4.6; 52 | b = 32'b11000000100100110011001100110011;//-4.6 53 | // Add stimulus here 54 | #200; 55 | clk = 0;//11000000001100001010001111010111==-2.76 56 | a = 32'b11000000100100110011001100110011;//-4.6; 57 | b = 32'b00111111000110011001100110011010;//0.6 58 | // Add stimulus here 59 | #300; 60 | 61 | clk = 0;//10111111111101011100001010001111==-1.92 62 | a = 32'b01000000010011001100110011001101;//3.2; 63 | b = 32'b10111111000110011001100110011010;//-0.6 64 | // Add stimulus here 65 | #400; 66 | clk = 0;//01001010100101010000111101101110==4884407.0 67 | a = 32'b01000101000010100111000011001101;//2215.05; 68 | b = 32'b01000101000010011101000110011010;//2205.10 69 | // Add stimulus here 70 | #500; 71 | end 72 | always #50 clk=(~clk); 73 | endmodule 74 | -------------------------------------------------------------------------------- /MAC/multiplier/twoscompliment.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:54:39 04/08/2017 7 | // Design Name: 8 | // Module Name: twoscompliment 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module twoscompliment(clk,reset,a,out); 22 | parameter width=32; 23 | input clk,reset; 24 | input [width-1:0] a; 25 | output reg [width-1:0] out; 26 | //reg [width-1:0] y; 27 | always@ (posedge clk) 28 | begin 29 | if (reset) 30 | out=32'b0; 31 | else 32 | out=(~a)+1; 33 | end 34 | 35 | //assign out =y; 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /MAC/multiplier/wallace_tree.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:48:55 04/03/2017 7 | // Design Name: 8 | // Module Name: wallacemultiplier 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | //`include "rca64bit.v" 22 | //`include "carrysaveadder.v" 23 | module wallace_tree(carryf,product1,inp1,inp2); 24 | 25 | input [23:0]inp1; 26 | input [23:0]inp2; 27 | 28 | wire [47:0]product; 29 | 30 | output [47:0]product1; 31 | 32 | output carryf; 33 | 34 | wire [49:0]p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24; 35 | 36 | //wire[64:0]p2; 37 | // 38 | //wire [64:0]p3; 39 | // 40 | //wire [64:0]p4; 41 | // 42 | //wire [64:0]p5; 43 | // 44 | //wire [64:0]p6; 45 | // 46 | //wire [64:0]p7 47 | // 48 | //wire [64:0]p8; 49 | // 50 | //wire [64:0]p9; 51 | // 52 | //wire [64:0]p10; 53 | // 54 | //wire [64:0]p11; 55 | // 56 | //wire [64:0]p12; 57 | // 58 | //wire [64:0]p13; 59 | // 60 | //wire [64:0]p14; 61 | // 62 | //wire [64:0]p15; 63 | // 64 | //wire [64:0]p16; 65 | // 66 | //wire [64:0]p17; 67 | // 68 | //wire [64:0]p18; 69 | // 70 | //wire [64:0]p19; 71 | // 72 | //wire [64:0]p20; 73 | // 74 | //wire [64:0]p21; 75 | // 76 | //wire [64:0]p22; 77 | // 78 | //wire [64:0]p23; 79 | // 80 | //wire [64:0]p24; 81 | // 82 | //wire [64:0]p25; 83 | // 84 | //wire [64:0]p26; 85 | // 86 | //wire [64:0]p27; 87 | // 88 | //wire [64:0]p28; 89 | // 90 | //wire [64:0]p29; 91 | // 92 | //wire [64:0]p30; 93 | // 94 | //wire [64:0]p31; 95 | // 96 | //wire [64:0]p32; 97 | 98 | wire [49:0]carry1,carry2,carry3,carry4,carry5,carry6,carry7,carry8,carry9,carry10,carry11,carry12,carry13,carry14,carry15,carry16,carry17,carry18,carry19,carry20,carry21,carry22; 99 | 100 | //wire [64:0]carry2; 101 | // 102 | //wire [64:0]carry3; 103 | // 104 | //wire [64:0]carry4; 105 | //c2, 106 | //wire [64:0]carry5; 107 | // 108 | //wire [64:0]carry6; 109 | // 110 | //wire [64:0]carry7; 111 | // 112 | //wire [64:0]carry8; 113 | // 114 | //wire [64:0]carry9; 115 | // 116 | //wire [64:0]carry10; 117 | // 118 | //wire [64:0]carry11; 119 | // 120 | //wire [64:0]carry12; 121 | // 122 | //wire [64:0]carry13; 123 | // 124 | //wire [64:0]carry14; 125 | // 126 | //wire [64:0]carry15; 127 | // 128 | //wire [64:0]carry16; 129 | // 130 | //wire [64:0]carry17; 131 | // 132 | //wire [64:0]carry18; 133 | // 134 | //wire [64:0]carry19; 135 | // 136 | //wire [64:0]carry20; 137 | // 138 | //wire [64:0]carry21; 139 | // 140 | //wire [64:0]carry22; 141 | // 142 | //wire [64:0]carry23; 143 | // 144 | //wire [64:0]carry24; 145 | // 146 | //wire [64:0]carry25; 147 | // 148 | //wire [64:0]carry26; 149 | // 150 | //wire [64:0]carry27; 151 | // 152 | //wire [64:0]carry28; 153 | // 154 | //wire [64:0]carry29; 155 | // 156 | //wire [64:0]carry30; 157 | 158 | wire [49:0]sum1,sum2,sum3,sum4,sum5,sum6,sum7,sum8,sum9,sum10,sum11,sum12,sum13,sum14,sum15,sum16,sum17,sum18,sum19,sum20,sum21,sum22; 159 | // 160 | //wire [64:0]sum2; 161 | // 162 | //wire [64:0]sum3; 163 | // 164 | //wire [64:0]sum4; 165 | // 166 | //wire [64:0]sum5; 167 | // 168 | //wire [64:0]sum6; 169 | // 170 | //wire [64:0]sum7; 171 | // 172 | //wire [64:0]sum8; 173 | // 174 | //wire [64:0]sum9; 175 | // 176 | //wire [64:0]sum10; 177 | // 178 | //wire [64:0]sum11; 179 | // 180 | //wire [64:0]sum12; 181 | // 182 | //wire [64:0]sum13; 183 | // 184 | //wire [64:0]sum14; 185 | // 186 | //wire [64:0]sum15; 187 | // 188 | //wire [64:0]sum16; 189 | // 190 | //wire [64:0]sum17; 191 | // 192 | //wire [64:0]sum18; 193 | // 194 | //wire [64:0]sum19; 195 | // 196 | //wire [64:0]sum20; 197 | // 198 | //wire [64:0]sum21; 199 | // 200 | //wire [64:0]sum22; 201 | // 202 | //wire [64:0]sum23; 203 | // 204 | //wire [64:0]sum24; 205 | // 206 | //wire [64:0]sum25; 207 | // 208 | //wire [64:0]sum26; 209 | // 210 | //wire [64:0]sum27; 211 | // 212 | //wire [64:0]sum28; 213 | // 214 | //wire [64:0]sum29; 215 | // 216 | //wire [64:0]sum30; 217 | 218 | assign p1=(inp2[0]==1'b1)?{25'b0,inp1}:50'h00000000; 219 | 220 | assign p2=(inp2[1]==1'b1)?{24'b0,inp1,1'b0}:50'h00000000; 221 | 222 | assign p3=(inp2[2]==1'b1)?{23'b0,inp1,2'b0}:50'h00000000; 223 | 224 | assign p4=(inp2[3]==1'b1)?{22'b0,inp1,3'b0}:50'h00000000; 225 | 226 | assign p5=(inp2[4]==1'b1)?{21'b0,inp1,4'b0}:50'h00000000; 227 | 228 | assign p6=(inp2[5]==1'b1)?{20'b0,inp1,5'b0}:50'h00000000; 229 | 230 | assign p7=(inp2[6]==1'b1)?{19'b0,inp1,6'b0}:50'h00000000; 231 | 232 | assign p8=(inp2[7]==1'b1)?{18'b0,inp1,7'b0}:50'h00000000; 233 | 234 | assign p9=(inp2[8]==1'b1)?{17'b0,inp1,8'b0}:50'h00000000; 235 | 236 | assign p10=(inp2[9]==1'b1)?{16'b0,inp1,9'b0}:50'h00000000; 237 | 238 | assign p11=(inp2[10]==1'b1)?{15'b0,inp1,10'b0}:50'h00000000; 239 | 240 | assign p12=(inp2[11]==1'b1)?{14'b0,inp1,11'b0}:50'h00000000; 241 | 242 | assign p13=(inp2[12]==1'b1)?{13'b0,inp1,12'b0}:50'h00000000; 243 | 244 | assign p14=(inp2[13]==1'b1)?{12'b0,inp1,13'b0}:50'h00000000; 245 | 246 | assign p15=(inp2[14]==1'b1)?{11'b0,inp1,14'b0}:50'h00000000; 247 | 248 | assign p16=(inp2[15]==1'b1)?{10'b0,inp1,15'b0}:50'h00000000; 249 | 250 | assign p17=(inp2[16]==1'b1)?{9'b0,inp1,16'b0}:50'h00000000; 251 | 252 | assign p18=(inp2[17]==1'b1)?{8'b0,inp1,17'b0}:50'h00000000; 253 | 254 | assign p19=(inp2[18]==1'b1)?{7'b0,inp1,18'b0}:50'h00000000; 255 | 256 | assign p20=(inp2[19]==1'b1)?{6'b0,inp1,19'b0}:50'h00000000; 257 | 258 | assign p21=(inp2[20]==1'b1)?{5'b0,inp1,20'b0}:50'h00000000; 259 | 260 | assign p22=(inp2[21]==1'b1)?{4'b0,inp1,21'b0}:50'h00000000; 261 | 262 | assign p23=(inp2[22]==1'b1)?{3'b0,inp1,22'b0}:50'h00000000; 263 | 264 | assign p24=(inp2[23]==1'b1)?{2'b0,inp1,23'b0}:50'h00000000; 265 | 266 | //assign p25[64:0]=(inp2[24]==1'b1)?{9'b0,inp1,24'b0}:64'h00000000; 267 | // 268 | //assign p26[64:0]=(inp2[25]==1'b1)?{8'b0,inp1,25'b0}:64'h00000000; 269 | // 270 | //assign p27[64:0]=(inp2[26]==1'b1)?{7'b0,inp1,26'b0}:64'h00000000; 271 | // 272 | //assign p28[64:0]=(inp2[27]==1'b1)?{6'b0,inp1,27'b0}:64'h00000000; 273 | // 274 | //assign p29[64:0]=(inp2[28]==1'b1)?{5'b0,inp1,28'b0}:64'h00000000; 275 | // 276 | //assign p30[64:0]=(inp2[29]==1'b1)?{4'b0,inp1,29'b0}:64'h00000000; 277 | // 278 | //assign p31[64:0]=(inp2[30]==1'b1)?{3'b0,inp1,30'b0}:64'h00000000; 279 | // 280 | //assign p32[64:0]=(inp2[31]==1'b1)?{2'b0,inp1,31'b0}:64'h00000000; 281 | 282 | carrysaveadder c1(carry1,sum1,p1,p2,p3); 283 | 284 | carrysaveadder c2(carry2,sum2,p4,p5,p6); 285 | 286 | carrysaveadder c3(carry3,sum3,p7,p8,p9); 287 | 288 | carrysaveadder c4(carry4,sum4,p10,p11,p12); 289 | 290 | carrysaveadder c5(carry5,sum5,p13,p14,p15); 291 | 292 | carrysaveadder c6(carry6,sum6,p16,p17,p18); 293 | 294 | carrysaveadder c7(carry7,sum7,p19,p20,p21); 295 | 296 | carrysaveadder c8(carry8,sum8,p22,p23,p24); 297 | 298 | // 299 | 300 | carrysaveadder c9(carry9,sum9,sum1,carry1,sum2); 301 | 302 | carrysaveadder c10(carry10,sum10,carry2,sum3,carry3); 303 | 304 | carrysaveadder c11(carry11,sum11,sum4,carry4,sum5); 305 | 306 | carrysaveadder c12(carry12,sum12,carry5,sum6,carry6); 307 | 308 | carrysaveadder c13(carry13,sum13,sum7,carry7,sum8); 309 | 310 | // 311 | 312 | carrysaveadder c14(carry14,sum14,sum9,carry9,sum10); 313 | 314 | carrysaveadder c15(carry15,sum15,carry10,sum11,carry11); 315 | 316 | carrysaveadder c16(carry16,sum16,sum12,carry12,sum13); 317 | 318 | // 319 | 320 | carrysaveadder c17(carry17,sum17,sum14,carry14,sum15); 321 | 322 | carrysaveadder c18(carry18,sum18,carry15,sum16,carry16); 323 | 324 | // 325 | 326 | carrysaveadder c19(carry19,sum19,sum17,carry17,sum18); 327 | 328 | carrysaveadder c20(carry20,sum20,carry18,carry13,carry8); 329 | 330 | // 331 | 332 | carrysaveadder c21(carry21,sum21,sum19,carry19,sum20); 333 | 334 | // 335 | 336 | carrysaveadder c22(carry22,sum22,sum21,carry21,carry20); 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | //carrysaveadder c9(carry9,sum9,p25,p26,p27); 345 | // 346 | //carrysaveadder c10(carry10,sum10,p28,p29,p30); 347 | // 348 | //carrysaveadder c11(carry11,sum11,sum1,carry1,sum2); 349 | // 350 | //carrysaveadder c12(carry12,sum12,carry2,sum3,carry3); 351 | // 352 | //carrysaveadder c13(carry13,sum13,sum4,carry4,sum5); 353 | // 354 | //carrysaveadder c14(carry14,sum14,carry5,sum6,carry6); 355 | // 356 | //carrysaveadder c15(carry15,sum15,sum7,carry7,sum8); 357 | // 358 | //carrysaveadder c16(carry16,sum16,carry8,sum9,carry9); 359 | // 360 | //carrysaveadder c17(carry17,sum17,sum10,carry10,p31); 361 | // 362 | //carrysaveadder c18(carry18,sum18,sum11,carry11,sum12); 363 | // 364 | //carrysaveadder c19(carry19,sum19,carry12,sum13,carry13); 365 | // 366 | //carrysaveadder c20(carry20,sum20,sum14,carry14,sum15); 367 | // 368 | //carrysaveadder c21(carry21,sum21,carry15,sum16,carry16); 369 | // 370 | //carrysaveadder c22(carry22,sum22,sum17,carry17,p32); 371 | // 372 | //carrysaveadder c23(carry23,sum23,sum18,carry18,sum19); 373 | // 374 | //carrysaveadder c24(carry24,sum24,carry19,sum20,carry20); 375 | // 376 | //carrysaveadder c25(carry25,sum25,sum21,carry21,sum22); 377 | // 378 | //carrysaveadder c26(carry26,sum26,sum23,carry23,sum24); 379 | // 380 | //carrysaveadder c27(carry27,sum27,carry24,sum25,carry25); 381 | // 382 | //carrysaveadder c28(carry28,sum28,sum26,carry26,sum27); 383 | // 384 | //carrysaveadder c29(carry29,sum29,sum28,carry28,carry27); 385 | // 386 | //carrysaveadder c30(carry30,sum30,sum29,carry29,carry22); 387 | 388 | rca24bit add1(sum22,carry22,1'b0,product,carryf); 389 | 390 | assign product1 = product[47:0]; 391 | 392 | endmodule 393 | 394 | 395 | -------------------------------------------------------------------------------- /MAC/test_bench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 29.11.2018 16:21:09 7 | // Design Name: 8 | // Module Name: test_bench 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module test_bench; 24 | reg clk, reset; 25 | reg [31:0] a; 26 | reg [31:0] b; 27 | 28 | // Outputs 29 | wire [31:0] out; 30 | 31 | // Instantiate the Unit Under Test (UUT) 32 | fp_mac uut ( 33 | .a(a), 34 | .b(b), 35 | .clk(clk), 36 | .reset(reset), 37 | .out(out) 38 | ); 39 | 40 | initial begin 41 | // Initialize Inputs 42 | reset = 1; 43 | clk = 0; 44 | a = 0; 45 | b = 0; 46 | 47 | // Wait 100 ns for global reset to finish 48 | #10; 49 | reset = 0; 50 | clk = 0;//01000001101010010100011110101110==21.16 51 | a = 32'h40DD0000;//-4.6; 52 | b = 32'h00DD0000;//-4.6 53 | // Add stimulus here 54 | #20; 55 | //clk = 0;//11000000001100001010001111010111==-2.76 56 | //reset = 0; 57 | a = 32'h40400000;//-4.6; 58 | b = 32'h40000000;//0.6 59 | // Add stimulus here 60 | #30; 61 | /* 62 | clk = 0;//10111111111101011100001010001111==-1.92 63 | //reset = 0; 64 | a = 32'b01000000010011001100110011001101;//3.2; 65 | b = 32'b10111111000110011001100110011010;//-0.6 66 | // Add stimulus here 67 | #40; 68 | clk = 0;//01001010100101010000111101101110==4884407.0 69 | //reset = 0; 70 | a = 32'b01000101000010100111000011001101;//2215.05; 71 | b = 32'b01000101000010011101000110011010;//2205.10 72 | // Add stimulus here 73 | #50; 74 | clk = 0; 75 | //reset = 0; 76 | a = 32'b00000100000101001110010100101100;//1750.25; 77 | b = 32'b00000010010100001001100010000010;//1525.19; 78 | // Add stimulus here 79 | #60;*/ 80 | end 81 | always #1 clk=(~clk); 82 | endmodule 83 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Floating-point-MAC-verilog 2 | 32 - bit floating point Multiplier Accumulator Unit (MAC) 3 | 4 | The proposed MAC unit is implemented in Xilinx ISE Design suite 2018.2 on ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1). 5 | Both Floating Point adder and multiplier are fully synthesizable. 6 | The above approach has been adapted from [Implementation of 32 Bit Floating Point MAC Unit to Feed Weighted Inputs to Neural Networks]. 7 | 8 | 9 | 10 | 11 | ## Simulation 12 | The result can be verified from the screenshot here. 13 | 14 | --------------------------------------------------------------------------------