4 | Deserialized data can be used to analyze protocol traffic, detecting errors and so on.
5 | The first implementation involves an adapter print to connect PCI-Express lanes to PCS-Block in FPGA and an evaluation board with ECP5UM(G).
6 | The adapter print should be connected to the eval. board through VERSA Expansion headers and SMA-Cables. 7 | 8 | https://www.latticesemi.com/products/developmentboardsandkits/ecp5evaluationboard 9 | # VERSA Expansion Headers 10 |  11 | # Eval Board top view 12 |  13 | 14 |  15 | 16 | # Eval Board bottom view 17 |  18 | 19 | # PCB 20 | 21 | Preparing for applying solder paste 22 |  23 | 24 | Mounting of SMT Stencil 25 |  26 | 27 | Applying solder paste 28 |  29 | 30 | PCB 31 |  32 | 33 | PCB with solder paste 34 |  35 | 36 | Mounted PCB 37 |  38 | 39 | # Python script usage 40 | 41 | ## record data (on raspberry pi) 42 | 43 | ``` 44 | pi@raspberrypi:~/github/ECP5_PCIE_Analyzer/py_script $ python3 analyzer.py 45 | ['analyzer.py'] 46 | file removed 47 | Time: 11.82167429399999 s 48 | ``` 49 | 50 | ## analyze data 51 | 52 | copy data to local 53 | ``` 54 | scp -r pi@192.168.178.29:~/github/ECP5_PCIE_Analyzer/py_script/*.csv . 55 | ``` 56 | -------------------------------------------------------------------------------- /hardware/common/libs/pretty/C_0402.kicad_mod: -------------------------------------------------------------------------------- 1 | (module C_0402 (layer F.Cu) (tedit 610F9322) 2 | (attr smd) 3 | (fp_text reference REF** (at 0 1.1) (layer F.SilkS) 4 | (effects (font (size 0.75 0.75) (thickness 0.15))) 5 | ) 6 | (fp_text value C_0402R (at 0 2) (layer F.Fab) hide 7 | (effects (font (size 0.75 0.75) (thickness 0.15))) 8 | ) 9 | (fp_line (start -1.016 0.508) (end -1.016 -0.508) (layer F.Fab) (width 0.15)) 10 | (fp_line (start -1.016 -0.508) (end 1.016 -0.508) (layer F.Fab) (width 0.15)) 11 | (fp_line (start 1.016 -0.508) (end 1.016 0.508) (layer F.Fab) (width 0.15)) 12 | (fp_line (start 1.016 0.508) (end -1.016 0.508) (layer F.Fab) (width 0.15)) 13 | (fp_line (start -1.016 -0.508) (end -1.016 0.508) (layer F.CrtYd) (width 0.15)) 14 | (fp_line (start -1.016 0.508) (end 1.016 0.508) (layer F.CrtYd) (width 0.15)) 15 | (fp_line (start 1.016 -0.508) (end 1.016 0.508) (layer F.CrtYd) (width 0.15)) 16 | (fp_line (start -1.016 -0.508) (end 1.016 -0.508) (layer F.CrtYd) (width 0.15)) 17 | (fp_line (start -1.016 -0.508) (end 1.016 -0.508) (layer F.SilkS) (width 0.15)) 18 | (fp_line (start 1.016 -0.508) (end 1.016 0.508) (layer F.SilkS) (width 0.15)) 19 | (fp_line (start 1.016 0.508) (end -1.016 0.508) (layer F.SilkS) (width 0.15)) 20 | (fp_line (start -1.016 0.508) (end -1.016 -0.508) (layer F.SilkS) (width 0.15)) 21 | (fp_text user %R (at 0 0) (layer F.Fab) hide 22 | (effects (font (size 0.5 0.5) (thickness 0.125))) 23 | ) 24 | (fp_text user %R (at 0 0) (layer F.Fab) 25 | (effects (font (size 0.5 0.5) (thickness 0.125))) 26 | ) 27 | (pad 1 smd rect (at -0.508 0) (size 0.56 0.56) (layers F.Cu F.Paste F.Mask)) 28 | (pad 2 smd rect (at 0.508 0) (size 0.56 0.56) (layers F.Cu F.Paste F.Mask)) 29 | (model ${KIPRJMOD}/../../common/libs/3dshapes/C_0402.wrl 30 | (at (xyz 0 0 0)) 31 | (scale (xyz 1 1 1)) 32 | (rotate (xyz 0 0 0)) 33 | ) 34 | ) 35 | -------------------------------------------------------------------------------- /hardware/common/libs/pretty/SMA_Amphenol_132291_Vertical.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SMA_Amphenol_132291_Vertical (layer F.Cu) (tedit 611B79BF) 2 | (descr https://www.amphenolrf.com/downloads/dl/file/id/3222/product/2918/132291_customer_drawing.pdf) 3 | (tags "SMA THT Female Jack Vertical Bulkhead") 4 | (fp_text reference REF** (at 0 -4.75) (layer F.SilkS) 5 | (effects (font (size 1 1) (thickness 0.15))) 6 | ) 7 | (fp_text value SMA_Amphenol_132291_Vertical (at 0 5) (layer F.Fab) 8 | (effects (font (size 1 1) (thickness 0.15))) 9 | ) 10 | (fp_circle (center 0 0) (end 3.175 0) (layer F.Fab) (width 0.1)) 11 | (fp_line (start 4.17 4.17) (end -4.17 4.17) (layer F.CrtYd) (width 0.05)) 12 | (fp_line (start 4.17 4.17) (end 4.17 -4.17) (layer F.CrtYd) (width 0.05)) 13 | (fp_line (start -4.17 -4.17) (end -4.17 4.17) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start -4.17 -4.17) (end 4.17 -4.17) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start -3.5 -3.5) (end 3.5 -3.5) (layer F.Fab) (width 0.1)) 16 | (fp_line (start -3.5 -3.5) (end -3.5 3.5) (layer F.Fab) (width 0.1)) 17 | (fp_line (start -3.5 3.5) (end 3.5 3.5) (layer F.Fab) (width 0.1)) 18 | (fp_line (start 3.5 -3.5) (end 3.5 3.5) (layer F.Fab) (width 0.1)) 19 | (fp_line (start -3.61 -1.66) (end -3.61 1.66) (layer F.SilkS) (width 0.12)) 20 | (fp_line (start 3.61 -1.66) (end 3.61 1.66) (layer F.SilkS) (width 0.12)) 21 | (fp_line (start -1.66 3.61) (end 1.66 3.61) (layer F.SilkS) (width 0.12)) 22 | (fp_line (start -1.66 -3.61) (end 1.66 -3.61) (layer F.SilkS) (width 0.12)) 23 | (fp_text user %R (at 0 0) (layer F.Fab) 24 | (effects (font (size 1 1) (thickness 0.15))) 25 | ) 26 | (pad 1 thru_hole circle (at 0 0) (size 2.05 2.05) (drill 1.5) (layers *.Cu *.Mask)) 27 | (pad 5 thru_hole circle (at 2.54 2.54) (size 2.25 2.25) (drill 1.7) (layers *.Cu *.Mask)) 28 | (pad 3 thru_hole circle (at 2.54 -2.54) (size 2.25 2.25) (drill 1.7) (layers *.Cu *.Mask)) 29 | (pad 2 thru_hole circle (at -2.54 -2.54) (size 2.25 2.25) (drill 1.7) (layers *.Cu *.Mask)) 30 | (pad 4 thru_hole circle (at -2.54 2.54) (size 2.25 2.25) (drill 1.7) (layers *.Cu *.Mask)) 31 | (model ${KIPRJMOD}/../../common/libs/3dshapes/SMA-J-P-H-ST-TH1.stp 32 | (at (xyz 0 0 0)) 33 | (scale (xyz 1 1 1)) 34 | (rotate (xyz -90 0 0)) 35 | ) 36 | ) 37 | -------------------------------------------------------------------------------- /fpga_logic/src/cores/pcie/pcie.lpc: -------------------------------------------------------------------------------- 1 | [Device] 2 | Family=sa5p00m 3 | OperatingCondition=IND 4 | Package=CABGA381 5 | PartName=LFE5UM-85F-8BG381I 6 | PartType=LFE5UM-85F 7 | SpeedGrade=8 8 | Status=P 9 | [IP] 10 | CoreName=PCI Express Endpoint Core 11 | CoreRevision=6.7 12 | CoreStatus=Demo 13 | CoreType=IPCFG 14 | Date=02/04/2021 15 | ModuleName=pcie 16 | ParameterFileVersion=1.0 17 | SourceFormat=vhdl 18 | Time=13:05:57 19 | VendorName=Lattice Semiconductor Corporation 20 | [Parameters] 21 | AER=0 22 | AER_CAP_VER=1 23 | BAR0=FFFF0000 24 | BAR1=FFFFFF00 25 | BAR2=FFFE0000 26 | BAR3=FFFFFF80 27 | BAR4=00000000 28 | BAR5=00000000 29 | BAR_REG_PORTS=0 30 | BIST=00 31 | BusWidth=1 32 | CAP_VERSION=2 33 | CARDBUS_CIS_POINTER=00000000 34 | CH_MODE=Rx and Tx 35 | CLASS_CODE=FF0000 36 | CORE_SYNP=1 37 | Channel=CH0 38 | Config=X1 39 | DATA_SCALE=0 40 | DCUA=DCU0 41 | DEV_CAP_REG=0000000 42 | DEV_CAP_REG2=11 43 | DEV_ID=0001 44 | DEV_SER_NUM=0000000000000000 45 | DSN_CAP_VER=1 46 | DataWidth=8 47 | ECRC=0 48 | EN_ALL_TLPS=0 49 | EN_BAR0=1 50 | EN_BAR1=1 51 | EN_BAR2=1 52 | EN_BAR3=1 53 | EN_BAR4=0 54 | EN_BAR5=0 55 | EN_DYN_ID=0 56 | EN_ER_BAR=0 57 | ERO_HW=1 58 | ER_BAR=00000000 59 | GEN2=Gen 2 60 | GSR=1 61 | HEADER_TYPE=00 62 | LANE_WIDTH=X1 Native 63 | LEGACY_EP=PCI Express Endpoint 64 | LINK_CAP_REG=00 65 | LINK_STA_REG_12=1 66 | LPEVCC=0 67 | MASTER_LB=0 68 | MAX_LINK_WIDTH=1 69 | MAX_PAYLOAD_SIZE=128 70 | MSI_FACE=1 71 | NEXT_CAP_POINT=60 72 | NOT_CFG_REG=0 73 | NO_DSN=0 74 | NPD_FC_0=32 75 | NPD_FREQ=8 76 | NPH_FC_0=32 77 | NPH_FREQ=8 78 | NUM_CHS=1 79 | NUM_MSG_RQST=8 80 | NUM_VC=1 81 | PD_FC_0=0 82 | PD_FREQ=255 83 | PD_INFINITE=1 84 | PH_FC_0=0 85 | PH_FREQ=8 86 | PH_INFINITE=1 87 | PROTOCOL=PCIE 88 | PWR_CONSUME_D0=00 89 | PWR_CONSUME_D1=00 90 | PWR_CONSUME_D2=00 91 | PWR_CONSUME_D3=00 92 | PWR_DISSIPATE_D0=00 93 | PWR_DISSIPATE_D1=00 94 | PWR_DISSIPATE_D2=00 95 | PWR_DISSIPATE_D3=00 96 | PWR_MG_CAP_REG=0003 97 | QUAD_LOC=UR 98 | QUAD_LOC_ECP3=PCSA 99 | REFCLK_RATE=100.0000 100 | REV_ID=00 101 | SBP=1 102 | SUBSYSTEM_ID=0000 103 | SUBSYSTEM_VENDOR_ID=0000 104 | StsWidth=3 105 | TXPLLMULT=25X 106 | TX_MAX_RATE=2.5 107 | UPDATE_TIMER=4095 108 | USR_EXT_CAP_ADDR=17C 109 | VCT=none 110 | VENDOR_ID=0BAE 111 | WISHBONE=0 112 | pcie_pcs.txt=pcs_module 113 | pcs_pipe_8b_x1.txt=pcs_module 114 | pcs_pipe_8b_x4.txt=pcs_module 115 | pcs_pipe_bb.v=black_box_verilog 116 | [SYSTEMPNR] 117 | LN0=DCU0_CH0 118 | -------------------------------------------------------------------------------- /fpga_logic/src/pdpram.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_unsigned.all; 4 | 5 | entity pdpram is 6 | generic ( 7 | addr_width : natural := 16; 8 | data_width : natural := 36); 9 | port ( 10 | write_en : in std_logic; 11 | waddr : in std_logic_vector (addr_width - 1 downto 0); 12 | wclk : in std_logic; 13 | raddr : in std_logic_vector (addr_width - 1 downto 0); 14 | rclk : in std_logic; 15 | din : in std_logic_vector (data_width - 1 downto 0); 16 | dout : out std_logic_vector (data_width - 1 downto 0)); 17 | end pdpram; 18 | 19 | architecture rtl of pdpram is 20 | type mem_type is array (0 to (2 ** addr_width) - 1) of std_logic_vector(35 downto 0); 21 | 22 | signal mem : mem_type;/* := ( 23 | ('1' & X"00" & '0' & X"CD" & '0' & X"EF" & '0' & X"FF"), -- 1 24 | ('0' & X"D0" & '0' & X"D1" & '0' & X"D2" & '0' & X"D3"), -- 2 25 | ('1' & X"D4" & '0' & X"D5" & '0' & X"D6" & '0' & X"D7"), -- 3 26 | ('0' & X"D8" & '0' & X"D9" & '0' & X"DA" & '0' & X"DB"), -- 4 27 | ('0' & X"DC" & '0' & X"DD" & '0' & X"DE" & '0' & X"DF"), -- 5 28 | ('0' & X"10" & '0' & X"11" & '0' & X"12" & '0' & X"13"), -- 6 29 | ('0' & X"14" & '0' & X"15" & '0' & X"16" & '0' & X"17"), -- 7 30 | ('0' & X"18" & '0' & X"19" & '0' & X"1A" & '0' & X"1B"), -- 8 31 | ('1' & X"AB" & '0' & X"CD" & '0' & X"EF" & '0' & X"FF"), -- 1 32 | ('0' & X"20" & '0' & X"21" & '0' & X"22" & '0' & X"23"), -- 2 33 | ('0' & X"24" & '0' & X"25" & '0' & X"26" & '0' & X"27"), -- 3 34 | ('0' & X"28" & '0' & X"29" & '0' & X"2A" & '0' & X"2B"), -- 4 35 | ('0' & X"2C" & '0' & X"2D" & '0' & X"2E" & '0' & X"2F"), -- 5 36 | ('0' & X"30" & '0' & X"31" & '0' & X"32" & '0' & X"33"), -- 6 37 | ('0' & X"34" & '0' & X"35" & '0' & X"36" & '0' & X"37"), -- 7 38 | ('0' & X"38" & '0' & X"39" & '0' & X"3A" & '0' & X"3B"), -- 8 39 | others => (others =>'0') 40 | ); 41 | */ 42 | 43 | attribute syn_ramstyle : string; 44 | attribute syn_ramstyle of mem: signal is "no_rw_check"; 45 | begin 46 | process (wclk) -- Write memory. 47 | begin 48 | if (wclk'event and wclk = '1') then 49 | if (write_en = '1') then 50 | mem(conv_integer(waddr)) <= din; -- Using write address bus. 51 | end if; 52 | end if; 53 | end process; 54 | 55 | process (rclk) -- Read memory. 56 | begin 57 | if (rclk'event and rclk = '1') then 58 | dout <= mem(conv_integer(raddr)); -- Using read address bus. 59 | end if; 60 | end process; 61 | end rtl; -------------------------------------------------------------------------------- /hardware/common/libs/pretty/VQFN-16.kicad_mod: -------------------------------------------------------------------------------- 1 | (module VQFN-16 (layer F.Cu) (tedit 611BAC4D) 2 | (fp_text reference REF** (at 0 -2.525) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value VQFN-16 (at 0 10.16) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1.5 -1.5) (end -1.5 -1) (layer F.SilkS) (width 0.12)) 9 | (fp_line (start -1.5 -1.5) (end -1 -1.5) (layer F.SilkS) (width 0.12)) 10 | (fp_line (start -1.5 1.5) (end -1 1.5) (layer F.SilkS) (width 0.12)) 11 | (fp_line (start 1.5 1.5) (end 1.5 1) (layer F.SilkS) (width 0.12)) 12 | (fp_line (start 1.5 -1.5) (end 1 -1.5) (layer F.SilkS) (width 0.12)) 13 | (fp_line (start -1.5 1.5) (end -1.5 1) (layer F.SilkS) (width 0.12)) 14 | (fp_line (start 1.5 1.5) (end 1 1.5) (layer F.SilkS) (width 0.12)) 15 | (fp_line (start 1.5 -1.5) (end 1.5 -1) (layer F.SilkS) (width 0.12)) 16 | (fp_line (start -1.5 -1) (end -1 -1.5) (layer F.SilkS) (width 0.12)) 17 | (fp_line (start -1 -1.5) (end -1.45 -1.2) (layer F.SilkS) (width 0.12)) 18 | (fp_line (start -1.45 -1.2) (end -1.25 -1.425) (layer F.SilkS) (width 0.12)) 19 | (fp_line (start -1.25 -1.425) (end -1.425 -1.35) (layer F.SilkS) (width 0.12)) 20 | (fp_line (start -1.425 -1.35) (end -1.425 -1.45) (layer F.SilkS) (width 0.12)) 21 | (fp_line (start -1.5 -1.5) (end 1.5 -1.5) (layer F.CrtYd) (width 0.12)) 22 | (fp_line (start 1.5 -1.5) (end 1.5 1.5) (layer F.CrtYd) (width 0.12)) 23 | (fp_line (start 1.5 1.5) (end -1.5 1.5) (layer F.CrtYd) (width 0.12)) 24 | (fp_line (start -1.5 1.5) (end -1.5 -1.5) (layer F.CrtYd) (width 0.12)) 25 | (pad 1 smd rect (at -1.4 -0.75) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 26 | (pad 2 smd rect (at -1.4 -0.25) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 27 | (pad 3 smd rect (at -1.4 0.25) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 28 | (pad 4 smd rect (at -1.4 0.75) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 29 | (pad 5 smd rect (at -0.75 1.4 90) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 30 | (pad 6 smd rect (at -0.25 1.4 90) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 31 | (pad 7 smd rect (at 0.25 1.4 90) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 32 | (pad 8 smd rect (at 0.75 1.4 90) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 33 | (pad 9 smd rect (at 1.4 0.75) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 34 | (pad 10 smd rect (at 1.4 0.25) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 35 | (pad 11 smd rect (at 1.4 -0.25) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 36 | (pad 12 smd rect (at 1.4 -0.75) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 37 | (pad 13 smd rect (at 0.75 -1.4 90) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 38 | (pad 14 smd rect (at 0.25 -1.4 90) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 39 | (pad 15 smd rect (at -0.25 -1.4 90) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 40 | (pad 16 smd rect (at -0.75 -1.4 90) (size 0.6 0.24) (layers F.Cu F.Paste F.Mask)) 41 | (pad EP smd roundrect (at 0 0 90) (size 1.68 1.68) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.06)) 42 | (model ${KIPRJMOD}/../../common/libs/3dshapes/vson.step 43 | (at (xyz 0 0 0)) 44 | (scale (xyz 1 1 1)) 45 | (rotate (xyz 0 0 0)) 46 | ) 47 | ) 48 | -------------------------------------------------------------------------------- /fpga_logic/src/pll.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.3.469 2 | -- Module Version: 5.7 3 | --C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 25.00 -fclkop 100.00 -fclkop_tol 0.0 -phase_cntl STATIC -lock -fb_mode 1 -fdc C:/Users/grpa/Documents/WORK/ECP5_PCIE_Analyzer/fpga_logic/impl/ip_cores/pll/pll.fdc 4 | 5 | -- Wed Jan 19 09:46:06 2022 6 | 7 | library IEEE; 8 | use IEEE.std_logic_1164.all; 9 | library ecp5um; 10 | use ecp5um.components.all; 11 | 12 | entity pll is 13 | port ( 14 | CLKI: in std_logic; 15 | CLKOP: out std_logic; 16 | LOCK: out std_logic); 17 | end pll; 18 | 19 | architecture Structure of pll is 20 | 21 | -- internal signal declarations 22 | signal REFCLK: std_logic; 23 | signal CLKOP_t: std_logic; 24 | signal scuba_vhi: std_logic; 25 | signal scuba_vlo: std_logic; 26 | 27 | attribute FREQUENCY_PIN_CLKOP : string; 28 | attribute FREQUENCY_PIN_CLKI : string; 29 | attribute ICP_CURRENT : string; 30 | attribute LPF_RESISTOR : string; 31 | attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000"; 32 | attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "25.000000"; 33 | attribute ICP_CURRENT of PLLInst_0 : label is "5"; 34 | attribute LPF_RESISTOR of PLLInst_0 : label is "16"; 35 | attribute syn_keep : boolean; 36 | attribute NGD_DRC_MASK : integer; 37 | attribute NGD_DRC_MASK of Structure : architecture is 1; 38 | 39 | begin 40 | -- component instantiation statements 41 | scuba_vhi_inst: VHI 42 | port map (Z=>scuba_vhi); 43 | 44 | scuba_vlo_inst: VLO 45 | port map (Z=>scuba_vlo); 46 | 47 | PLLInst_0: EHXPLLL 48 | generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 49 | STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 50 | CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, 51 | CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0, 52 | CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 5, PLL_LOCK_MODE=> 0, 53 | CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", 54 | CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", 55 | OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 56 | OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", 57 | OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", 58 | OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, 59 | CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 6, CLKFB_DIV=> 4, 60 | CLKI_DIV=> 1, FEEDBK_PATH=> "CLKOP") 61 | port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 62 | PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 63 | PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 64 | STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 65 | ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 66 | ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, 67 | CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 68 | REFCLK=>REFCLK, CLKINTFB=>open); 69 | 70 | CLKOP <= CLKOP_t; 71 | end Structure; 72 | -------------------------------------------------------------------------------- /fpga_logic/src/pll_200.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.3.469 2 | -- Module Version: 5.7 3 | --C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n pll_200 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type pll -fin 200 -fclkop 125.00 -fclkop_tol 0.0 -phase_cntl STATIC -lock -fb_mode 1 -fdc C:/Users/grpa/Documents/WORK/ECP5_PCIE_Analyzer/fpga_logic/impl/ip_cores/pll_200/pll_200.fdc 4 | 5 | -- Fri Jan 21 12:46:58 2022 6 | 7 | library IEEE; 8 | use IEEE.std_logic_1164.all; 9 | library ecp5um; 10 | use ecp5um.components.all; 11 | 12 | entity pll_200 is 13 | port ( 14 | CLKI: in std_logic; 15 | CLKOP: out std_logic; 16 | LOCK: out std_logic); 17 | end pll_200; 18 | 19 | architecture Structure of pll_200 is 20 | 21 | -- internal signal declarations 22 | signal REFCLK: std_logic; 23 | signal CLKOP_t: std_logic; 24 | signal scuba_vhi: std_logic; 25 | signal scuba_vlo: std_logic; 26 | 27 | attribute FREQUENCY_PIN_CLKOP : string; 28 | attribute FREQUENCY_PIN_CLKI : string; 29 | attribute ICP_CURRENT : string; 30 | attribute LPF_RESISTOR : string; 31 | attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000"; 32 | attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; 33 | attribute ICP_CURRENT of PLLInst_0 : label is "5"; 34 | attribute LPF_RESISTOR of PLLInst_0 : label is "16"; 35 | attribute syn_keep : boolean; 36 | attribute NGD_DRC_MASK : integer; 37 | attribute NGD_DRC_MASK of Structure : architecture is 1; 38 | 39 | begin 40 | -- component instantiation statements 41 | scuba_vhi_inst: VHI 42 | port map (Z=>scuba_vhi); 43 | 44 | scuba_vlo_inst: VLO 45 | port map (Z=>scuba_vlo); 46 | 47 | PLLInst_0: EHXPLLL 48 | generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 49 | STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 50 | CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, 51 | CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0, 52 | CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 4, PLL_LOCK_MODE=> 0, 53 | CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", 54 | CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", 55 | OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 56 | OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", 57 | OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", 58 | OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, 59 | CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 5, CLKFB_DIV=> 5, 60 | CLKI_DIV=> 8, FEEDBK_PATH=> "CLKOP") 61 | port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 62 | PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 63 | PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 64 | STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 65 | ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 66 | ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, 67 | CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 68 | REFCLK=>REFCLK, CLKINTFB=>open); 69 | 70 | CLKOP <= CLKOP_t; 71 | end Structure; 72 | -------------------------------------------------------------------------------- /fpga_logic/script/make_sim.tcl: -------------------------------------------------------------------------------- 1 | 2 | cd .. 3 | set ProjectPath [pwd] 4 | set SrcPath $ProjectPath/SRC 5 | 6 | puts "Clear project" 7 | 8 | file delete -force sim_core 9 | 10 | file mkdir sim_core 11 | cd $ProjectPath/sim_core 12 | 13 | puts "Creating new backplane project" 14 | 15 | prj_project new -name "pcie_core" -impl "pcie_core" -dev LFE5UM-85F-8BG381I -synthesis "synplify" 16 | prj_project save 17 | 18 | puts "Copying core files" 19 | 20 | file mkdir ip_cores/pcie 21 | file mkdir ip_cores/extref 22 | file copy -force $ProjectPath/src/cores/pcie/pcie.lpc $ProjectPath/sim_core/ip_cores/pcie/pcie.lpc 23 | file copy -force $ProjectPath/src/cores/pcie/generate_core.tcl $ProjectPath/sim_core/ip_cores/pcie/generate_core.tcl 24 | file copy -force $ProjectPath/src/cores/pcie/generate_ngd.tcl $ProjectPath/sim_core/ip_cores/pcie/generate_ngd.tcl 25 | file copy -force $ProjectPath/src/cores/extref/extref.lpc $ProjectPath/sim_core/ip_cores/extref/extref.lpc 26 | file copy -force $ProjectPath/src/cores/extref/generate_core.tcl $ProjectPath/sim_core/ip_cores/extref/generate_core.tcl 27 | file copy -force $ProjectPath/src/cores/extref/generate_ngd.tcl $ProjectPath/sim_core/ip_cores/extref/generate_ngd.tcl 28 | 29 | set currentPath [pwd];set tmp_autopath $auto_path 30 | 31 | file copy -force $ProjectPath/src/cores/ip_cores.sbx $ProjectPath/sim_core/ip_cores/ip_cores.sbx 32 | 33 | prj_src add "ip_cores/ip_cores.sbx" 34 | sbp_design open -dsgn ip_cores/ip_cores.sbx 35 | 36 | puts "Creating PICExpress core" 37 | 38 | cd "$ProjectPath/sim_core/ip_cores/pcie" 39 | source "$ProjectPath/sim_core/ip_cores/pcie/generate_core.tcl" 40 | set auto_path $tmp_autopath;cd $currentPath 41 | set currentPath [pwd];set tmp_autopath $auto_path 42 | cd "$ProjectPath/sim_core/ip_cores/pcie" 43 | source "$ProjectPath/sim_core/ip_cores/pcie/generate_ngd.tcl" 44 | 45 | cd $currentPath 46 | 47 | sbp_builder export_add -comp {ip_cores/pcie} 48 | 49 | puts "Placing DCUCHANNEL" 50 | sbp_resource place -rsc {ip_cores/pcie/DCUCHANNEL} -id 5 51 | 52 | puts "Creating Extref core" 53 | 54 | cd "$ProjectPath/sim_core/ip_cores/extref" 55 | source "$ProjectPath/sim_core/ip_cores/extref/generate_core.tcl" 56 | set auto_path $tmp_autopath;cd $currentPath 57 | set currentPath [pwd];set tmp_autopath $auto_path 58 | cd "$ProjectPath/sim_core/ip_cores/extref" 59 | source "$ProjectPath/sim_core/ip_cores/extref/generate_ngd.tcl" 60 | 61 | sbp_builder export_add -comp {ip_cores/extref} 62 | puts "Placing EXTREF" 63 | 64 | sbp_resource place -rsc {ip_cores/extref/EXTREF} -id 3 65 | 66 | puts "Generating PCIExpress core" 67 | 68 | sbp_design gen 69 | 70 | sbp_design save 71 | 72 | sbp_design close 73 | 74 | prj_src add "$ProjectPath/src/pci_core_wrapper.vhd" 75 | prj_src add "$ProjectPath/src/pci_wrapper_pkg.vhd" 76 | prj_src add "$ProjectPath/src/pcie_rx_engine.vhd" 77 | prj_src add "$ProjectPath/src/pcie_tx_engine.vhd" 78 | prj_src add "$ProjectPath/src/pci_read_request_fifo.vhd" 79 | prj_src add "$ProjectPath/src/top_pkg.vhd" 80 | prj_src add "$ProjectPath/src/top.vhd" 81 | 82 | 83 | prj_src add "$ProjectPath/SRC/constrains.lpf" 84 | prj_src enable "$ProjectPath/SRC/constrains.lpf" 85 | prj_src remove "$ProjectPath/sim_core/bpl100.lpf" 86 | file delete -force $ProjectPath/sim_core/bpl100.lpf 87 | 88 | prj_strgy set_value -strategy Strategy1 syn_vhdl2008=True 89 | prj_project save -------------------------------------------------------------------------------- /fpga_logic/src/pulse_filt.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------- 2 | -- Module: pulse_filt 3 | -- File: pulse_filt.vhd 4 | ----------------------------------------------------------------------------- 5 | -- COPYRIGHT BY G BACHMANN ELECTRONIC GMBH 2014 6 | ----------------------------------------------------------------------------- 7 | 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | 12 | 13 | --! @author WANA 14 | --! @brief Configurable filter 15 | --! @details This entity defines a configurable filter. The filter is build with an up / down counter. 16 | --! When the input x is high the counter is incremented until it reaches the value filter_len_sel. Then the output y goes to high. 17 | --! When the input x is low the counter is decremented until it reaches the value 0. Then the output y goes to low. 18 | 19 | entity pulse_filt is 20 | generic ( 21 | constant FILT_LEN : integer := 8 --! length of the filter constant 22 | ); 23 | port ( 24 | clk : in std_logic; --! clock input 25 | rst : in std_logic; --! reset (active high) 26 | -- Filter len select 27 | filt_len_sel : std_logic_vector(FILT_LEN-1 downto 0); --! filter value 28 | x : in std_logic; --! signal to filter 29 | y : out std_logic --! filtered signal 30 | ); 31 | end; 32 | 33 | architecture rtl of pulse_filt is 34 | 35 | type reg_t is record 36 | filter_count : unsigned(FILT_LEN-1 downto 0); 37 | y : std_logic; 38 | end record reg_t; 39 | 40 | -- Initial values after reset 41 | constant REG_T_INIT : reg_t := ( 42 | filter_count => (others => '0'), 43 | y => '0' 44 | ); 45 | 46 | 47 | 48 | signal r, rin : reg_t; 49 | 50 | begin 51 | 52 | -- Combinatorial process 53 | comb : process (r,x, filt_len_sel) is 54 | variable v : reg_t; 55 | begin 56 | v := r; 57 | -- Workaround for filt_len = 0 58 | if unsigned(filt_len_sel) = 0 then 59 | v.y := x; 60 | v.filter_count := (others=>'0'); -- Reset filter counter 61 | else 62 | -- Pulse counter with saturation 63 | if x='1' then 64 | if r.filter_count < unsigned(filt_len_sel) then 65 | v.filter_count:= r.filter_count + 1; 66 | end if; 67 | else 68 | if r.filter_count > 0 then 69 | v.filter_count := r.filter_count - 1; 70 | end if; 71 | end if; 72 | 73 | -- set/reset logic for filter output 74 | if r.filter_count = unsigned(filt_len_sel) then 75 | v.y := '1'; 76 | elsif r.filter_count = 0 then 77 | v.y := '0'; 78 | end if; 79 | end if; 80 | 81 | -- Output assignments 82 | y <= v.y; 83 | 84 | rin <= v; 85 | end process comb; 86 | 87 | -- Register process 88 | regs : process (clk) is 89 | begin 90 | -- Synchronous reset 91 | if rising_edge(clk) then 92 | if rst = '1' then 93 | r <= REG_T_INIT; 94 | else 95 | r <= rin; 96 | end if; 97 | end if; 98 | end process regs; 99 | end; 100 | -------------------------------------------------------------------------------- /fpga_logic/script/make.tcl: -------------------------------------------------------------------------------- 1 | cd .. 2 | set ProjectPath [pwd] 3 | set SrcPath $ProjectPath/SRC 4 | 5 | puts "Clear project" 6 | 7 | file delete -force impl 8 | 9 | file mkdir impl 10 | cd $ProjectPath/impl 11 | 12 | puts "Creating new backplane project" 13 | 14 | prj_project new -name "analyzer" -impl "analyzer" -dev LFE5UM5G-85F-8BG381C -synthesis "synplify" 15 | prj_project save 16 | 17 | #puts "Copying core files" 18 | # 19 | #file mkdir ip_cores/pcie 20 | #file mkdir ip_cores/extref 21 | #file copy -force $ProjectPath/src/cores/pcie/pcie.lpc $ProjectPath/impl/ip_cores/pcie/pcie.lpc 22 | #file copy -force $ProjectPath/src/cores/pcie/generate_core.tcl $ProjectPath/impl/ip_cores/pcie/generate_core.tcl 23 | #file copy -force $ProjectPath/src/cores/pcie/generate_ngd.tcl $ProjectPath/impl/ip_cores/pcie/generate_ngd.tcl 24 | #file copy -force $ProjectPath/src/cores/extref/extref.lpc $ProjectPath/impl/ip_cores/extref/extref.lpc 25 | #file copy -force $ProjectPath/src/cores/extref/generate_core.tcl $ProjectPath/impl/ip_cores/extref/generate_core.tcl 26 | #file copy -force $ProjectPath/src/cores/extref/generate_ngd.tcl $ProjectPath/impl/ip_cores/extref/generate_ngd.tcl 27 | 28 | #set currentPath [pwd];set tmp_autopath $auto_path 29 | # 30 | #file copy -force $ProjectPath/src/cores/ip_cores.sbx $ProjectPath/impl/ip_cores/ip_cores.sbx 31 | # 32 | #prj_src add "ip_cores/ip_cores.sbx" 33 | #sbp_design open -dsgn ip_cores/ip_cores.sbx 34 | # 35 | #puts "Creating PICExpress core" 36 | # 37 | #cd "$ProjectPath/impl/ip_cores/pcie" 38 | #source "$ProjectPath/impl/ip_cores/pcie/generate_core.tcl" 39 | #set auto_path $tmp_autopath;cd $currentPath 40 | #set currentPath [pwd];set tmp_autopath $auto_path 41 | #cd "$ProjectPath/impl/ip_cores/pcie" 42 | #source "$ProjectPath/impl/ip_cores/pcie/generate_ngd.tcl" 43 | 44 | #cd $currentPath 45 | # 46 | #sbp_builder export_add -comp {ip_cores/pcie} 47 | # 48 | #puts "Placing DCUCHANNEL" 49 | #sbp_resource place -rsc {ip_cores/pcie/DCUCHANNEL} -id 5 50 | # 51 | #puts "Creating Extref core" 52 | # 53 | #cd "$ProjectPath/impl/ip_cores/extref" 54 | #source "$ProjectPath/impl/ip_cores/extref/generate_core.tcl" 55 | #set auto_path $tmp_autopath;cd $currentPath 56 | #set currentPath [pwd];set tmp_autopath $auto_path 57 | #cd "$ProjectPath/impl/ip_cores/extref" 58 | #source "$ProjectPath/impl/ip_cores/extref/generate_ngd.tcl" 59 | # 60 | #sbp_builder export_add -comp {ip_cores/extref} 61 | #puts "Placing EXTREF" 62 | # 63 | #sbp_resource place -rsc {ip_cores/extref/EXTREF} -id 3 64 | # 65 | #puts "Generating PCIExpress core" 66 | # 67 | #sbp_design gen 68 | # 69 | #sbp_design save 70 | # 71 | #sbp_design close 72 | 73 | prj_src add "$ProjectPath/src/analyzer_pkg.vhd" 74 | prj_src add "$ProjectPath/src/analyzer.vhd" 75 | prj_src add "$ProjectPath/src/packet_ram.vhd" 76 | prj_src add "$ProjectPath/src/lfsr_scrambler.vhd" 77 | prj_src add "$ProjectPath/src/controller.vhd" 78 | prj_src add "$ProjectPath/src/top_pkg.vhd" 79 | prj_src add "$ProjectPath/src/top.vhd" 80 | prj_src add "$ProjectPath/src/spi_slave.vhd" 81 | prj_src add "$ProjectPath/src/pulse_filt.vhd" 82 | prj_src add "$ProjectPath/src/rev_analyzer.vhd" 83 | prj_src add "$ProjectPath/src/extref.vhd" 84 | prj_src add "$ProjectPath/src/pcs_pci_rx.vhd" 85 | prj_src add "$ProjectPath/src/pcs_pci_tx.vhd" 86 | prj_src add "$ProjectPath/src/pll.vhd" 87 | prj_src add "$ProjectPath/src/pll_200.vhd" 88 | 89 | 90 | prj_src add "$ProjectPath/SRC/analyzer.lpf" 91 | prj_src enable "$ProjectPath/SRC/analyzer.lpf" 92 | 93 | prj_strgy set_value -strategy Strategy1 syn_vhdl2008=True 94 | prj_project save -------------------------------------------------------------------------------- /fpga_logic/src/cores/pcie/generate_core.tcl: -------------------------------------------------------------------------------- 1 | 2 | #!/usr/local/bin/wish 3 | 4 | set cpu $tcl_platform(machine) 5 | 6 | switch $cpu { 7 | intel - 8 | i*86* { 9 | set cpu ix86 10 | } 11 | x86_64 { 12 | if {$tcl_platform(wordSize) == 4} { 13 | set cpu ix86 14 | } 15 | } 16 | } 17 | 18 | switch $tcl_platform(platform) { 19 | windows { 20 | set Para(os_platform) windows 21 | if {$cpu == "amd64"} { 22 | # Do not check wordSize, win32-x64 is an IL32P64 platform. 23 | set cpu x86_64 24 | } 25 | } 26 | unix { 27 | if {$tcl_platform(os) == "Linux"} { 28 | set Para(os_platform) linux 29 | } else { 30 | set Para(os_platform) unix 31 | } 32 | } 33 | } 34 | 35 | if {$cpu == "x86_64"} { 36 | set NTPATH nt64 37 | set LINPATH lin64 38 | } else { 39 | set NTPATH nt 40 | set LINPATH lin 41 | } 42 | 43 | if {$Para(os_platform) == "linux" } { 44 | set os $LINPATH 45 | set idxfile [file join $env(HOME) ipsetting_l.lst] 46 | } else { 47 | set os $NTPATH 48 | set idxfile [file join c:/lsc_env ipsetting.lst] 49 | } 50 | 51 | set Para(cmd) "" 52 | if ![catch {set temp $argc} result] { 53 | if {$argc > 0} { 54 | for {set i 0} {$i < $argc} {incr i 2} { 55 | set temp [lindex $argv $i] 56 | set temp [string range $temp 1 end] 57 | lappend argv_list $temp 58 | lappend value_list [lindex $argv [expr $i+1]] 59 | } 60 | foreach argument $argv_list value $value_list { 61 | switch $argument { 62 | "cmd" {set Para(cmd) $value;} 63 | } 64 | } 65 | } 66 | } 67 | 68 | set Para(ProjectPath) [file dirname [info script]] 69 | package forget core_template 70 | package forget LatticeIPCore 71 | package forget IP_Control 72 | package forget Core_Generate 73 | package forget IP_Generate 74 | package forget IP_Templates 75 | set auto_path "$auto_path" 76 | set Para(install_dir) $env(TOOLRTF) 77 | set Para(CoreIndex) "pci_express_endpoint_v6.7" 78 | set Para(CoreRoot) "" 79 | set fid [open $idxfile r] 80 | while {[gets $fid line ]>=0} { 81 | if [regexp {([^=]*)=(.*)} $line match parameter value] { 82 | if [regexp {([ |\t]*;)} $parameter match] {continue} 83 | set parameter [string trim $parameter] 84 | set value [string trim $value] 85 | if {$parameter==$Para(CoreIndex)} { 86 | if [regexp {(.*)[ |\t]*;} $value match temp] { 87 | set Para(CoreRoot) $temp 88 | } else { 89 | set Para(CoreRoot) $value 90 | } 91 | } 92 | } 93 | } 94 | if {[string length $Para(CoreRoot)]==0} { 95 | puts stderr "Error: IP $Para(CoreIndex) is not found!" 96 | exit 97 | } 98 | 99 | set Para(ModuleName) "pcie" 100 | set Para(lib) "[file join $Para(CoreRoot) $Para(CoreIndex) lib]" 101 | set Para(CoreName) "PCI Express Endpoint Core" 102 | set Para(arch) "sa5p00m" 103 | set Para(family) "ecp5um" 104 | set Para(Family) "ecp5um" 105 | set Para(design) "vhdl" 106 | set Para(Bin) "[file join $Para(install_dir) bin $os]" 107 | set Para(SpeedGrade) "7" 108 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $os]" 109 | 110 | lappend auto_path "[file join $Para(CoreRoot) $Para(CoreIndex) gui]" 111 | 112 | lappend auto_path "[file join $Para(CoreRoot) $Para(CoreIndex) script]" 113 | package require Core_Generate 114 | 115 | lappend auto_path "$Para(install_dir)/tcltk/lib/ipwidgets/ispipbuilder/../runproc" 116 | package require runcmd 117 | 118 | 119 | set Para(result) [GenerateCore] 120 | -------------------------------------------------------------------------------- /fpga_logic/src/lfsr_scrambler.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Copyright (C) 2009 OutputLogic.com 3 | -- This source file may be used and distributed without restriction 4 | -- provided that this copyright statement is not removed from the file 5 | -- and that any derivative work contains the original copyright notice 6 | -- and the associated disclaimer. 7 | -- 8 | -- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS 9 | -- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 10 | -- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 11 | ------------------------------------------------------------------------------- 12 | -- scrambler module for data(7:0) 13 | -- lfsr(15:0)=1+x^3+x^4+x^5+x^16; 14 | ------------------------------------------------------------------------------- 15 | library ieee; 16 | use ieee.std_logic_1164.all; 17 | use work.analyzer_pkg.all; 18 | 19 | entity lfsr_scrambler is 20 | port ( 21 | clk : in std_logic; 22 | rst : in std_logic; 23 | data_in : in std_logic_vector (7 downto 0); 24 | rx_k : in std_logic; 25 | data_out : out std_logic_vector (7 downto 0); 26 | rx_k_out : out std_logic 27 | ); 28 | end lfsr_scrambler; 29 | 30 | architecture imp_scrambler of lfsr_scrambler is 31 | signal data_c : std_logic_vector (7 downto 0); 32 | signal lfsr_q : std_logic_vector (15 downto 0); 33 | signal lfsr_c : std_logic_vector (15 downto 0); 34 | signal scram_en : std_logic; 35 | signal scram_rst : std_logic; 36 | begin 37 | lfsr_c(0) <= lfsr_q(8); 38 | lfsr_c(1) <= lfsr_q(9); 39 | lfsr_c(2) <= lfsr_q(10); 40 | lfsr_c(3) <= lfsr_q(8) xor lfsr_q(11); 41 | lfsr_c(4) <= lfsr_q(8) xor lfsr_q(9) xor lfsr_q(12); 42 | lfsr_c(5) <= lfsr_q(8) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(13); 43 | lfsr_c(6) <= lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(14); 44 | lfsr_c(7) <= lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(15); 45 | lfsr_c(8) <= lfsr_q(0) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13); 46 | lfsr_c(9) <= lfsr_q(1) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14); 47 | lfsr_c(10) <= lfsr_q(2) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15); 48 | lfsr_c(11) <= lfsr_q(3) xor lfsr_q(14) xor lfsr_q(15); 49 | lfsr_c(12) <= lfsr_q(4) xor lfsr_q(15); 50 | lfsr_c(13) <= lfsr_q(5); 51 | lfsr_c(14) <= lfsr_q(6); 52 | lfsr_c(15) <= lfsr_q(7); 53 | 54 | data_c(0) <= data_in(0) xor lfsr_q(15); 55 | data_c(1) <= data_in(1) xor lfsr_q(14); 56 | data_c(2) <= data_in(2) xor lfsr_q(13); 57 | data_c(3) <= data_in(3) xor lfsr_q(12); 58 | data_c(4) <= data_in(4) xor lfsr_q(11); 59 | data_c(5) <= data_in(5) xor lfsr_q(10); 60 | data_c(6) <= data_in(6) xor lfsr_q(9); 61 | data_c(7) <= data_in(7) xor lfsr_q(8); 62 | 63 | scram_rst <= '1' when rx_k = '1' and data_in = K_COM_SYM_28_5 else '0'; 64 | scram_en <= '0' when rx_k = '1' and data_in = K_COM_SYM_28_5 else 65 | '0' when rx_k = '1' and data_in = K_PAD_SKP_28_0 else 66 | '1'; 67 | 68 | process (clk,rst) begin 69 | if (rst = '1') then 70 | lfsr_q <= b"1111111111111111"; 71 | data_out <= b"00000000"; 72 | elsif (clk'EVENT and clk = '1') then 73 | rx_k_out <= rx_k; 74 | if (scram_rst = '1') then 75 | lfsr_q <= b"1111111111111111"; 76 | elsif (scram_en = '1') then 77 | lfsr_q <= lfsr_c; 78 | end if; 79 | 80 | if (scram_en = '1' and rx_k = '0') then 81 | data_out <= data_c; 82 | else 83 | data_out <= data_in; 84 | end if; 85 | end if; 86 | end process; 87 | end architecture imp_scrambler; 88 | -------------------------------------------------------------------------------- /fpga_logic/src/cores/extref/generate_ngd.tcl: -------------------------------------------------------------------------------- 1 | #!/usr/local/bin/wish 2 | 3 | proc GetPlatform {} { 4 | global tcl_platform 5 | 6 | set cpu $tcl_platform(machine) 7 | 8 | switch $cpu { 9 | intel - 10 | i*86* { 11 | set cpu ix86 12 | } 13 | x86_64 { 14 | if {$tcl_platform(wordSize) == 4} { 15 | set cpu ix86 16 | } 17 | } 18 | } 19 | 20 | switch $tcl_platform(platform) { 21 | windows { 22 | if {$cpu == "amd64"} { 23 | # Do not check wordSize, win32-x64 is an IL32P64 platform. 24 | set cpu x86_64 25 | } 26 | if {$cpu == "x86_64"} { 27 | return "nt64" 28 | } else { 29 | return "nt" 30 | } 31 | } 32 | unix { 33 | if {$tcl_platform(os) == "Linux"} { 34 | if {$cpu == "x86_64"} { 35 | return "lin64" 36 | } else { 37 | return "lin" 38 | } 39 | } else { 40 | return "sol" 41 | } 42 | } 43 | } 44 | return "nt" 45 | } 46 | 47 | set platformpath [GetPlatform] 48 | set Para(sbp_path) [file dirname [info script]] 49 | set Para(install_dir) $env(TOOLRTF) 50 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" 51 | set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" 52 | 53 | set Para(ModuleName) "extref" 54 | set Para(Module) "EXTREF" 55 | set Para(libname) ecp5um 56 | set Para(arch_name) sa5p00m 57 | set Para(PartType) "LFE5UM-85F" 58 | 59 | set Para(tech_syn) ecp5um 60 | set Para(tech_cae) ecp5um 61 | set Para(Package) "CABGA381" 62 | set Para(SpeedGrade) "7" 63 | set Para(FMax) "100" 64 | set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" 65 | 66 | #create response file(*.cmd) for Synpwrap 67 | proc CreateCmdFile {} { 68 | global Para 69 | 70 | file mkdir "$Para(sbp_path)/syn_results" 71 | if [catch {open $Para(ModuleName).cmd w} rspFile] { 72 | puts "Cannot create response file $Para(ModuleName).cmd." 73 | exit -1 74 | } else { 75 | puts $rspFile "PROJECT: $Para(ModuleName) 76 | working_path: \"$Para(sbp_path)/syn_results\" 77 | module: $Para(ModuleName) 78 | verilog_file_list: \"$Para(sbp_path)/$Para(ModuleName).vhd\" 79 | vlog_std_v2001: true 80 | constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\" 81 | suffix_name: edn 82 | output_file_name: $Para(ModuleName) 83 | write_prf: true 84 | disable_io_insertion: true 85 | force_gsr: false 86 | frequency: $Para(FMax) 87 | fanout_limit: 50 88 | retiming: false 89 | pipe: false 90 | part: $Para(PartType) 91 | speed_grade: $Para(SpeedGrade) 92 | " 93 | close $rspFile 94 | } 95 | } 96 | 97 | #synpwrap 98 | CreateCmdFile 99 | set synpwrap "$Para(bin_dir)/synpwrap" 100 | if {[file exists $fdcfile] == 0} { 101 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg] 102 | } else { 103 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg] 104 | } 105 | #puts $msg 106 | 107 | #edif2ngd 108 | set edif2ngd "$Para(FPGAPath)/edif2ngd" 109 | set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg] 110 | #puts $msg 111 | 112 | #ngdbuild 113 | set ngdbuild "$Para(FPGAPath)/ngdbuild" 114 | set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] 115 | #puts $msg 116 | -------------------------------------------------------------------------------- /fpga_logic/src/top_pkg.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Entity: BP_pkg 3 | -- Date:2016-12-09 4 | -- Author: GRPA 5 | -- 6 | -- Description: 7 | -------------------------------------------------------------------------------- 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use std.textio.all; 12 | 13 | package top_pkg is 14 | 15 | constant MODUL_NUM_CONST : integer := 32; --! deprecated, not used in new design 16 | 17 | -- debug settings 18 | constant PCIE_RX_DEBUG_ENA : BOOLEAN := FALSE; -- reveal analyzer inserter 19 | 20 | -- SIO commands 21 | constant SET_DATA_4 : std_logic_vector (7 downto 0) := X"24"; 22 | constant INIT_ISR : std_logic_vector (7 downto 0) := X"30"; 23 | 24 | -- function to calculate FirstDW and LastDW fields 25 | function dw_assign (addr : std_logic_vector(1 downto 0); len : std_logic_vector (6 downto 0)) return std_logic_vector; 26 | -- function to calculate LENGTH field for TLP Header 27 | function len_calc (addr : std_logic_vector (1 downto 0); len : std_logic_vector (6 downto 0)) return std_logic_vector; 28 | 29 | end package; 30 | 31 | 32 | package body top_pkg is 33 | 34 | -------------------------------------------------------------------------------- 35 | -- assign dw field 36 | -------------------------------------------------------------------------------- 37 | function dw_assign (addr : std_logic_vector(1 downto 0); len : std_logic_vector (6 downto 0)) return std_logic_vector is 38 | variable dw : std_logic_vector (7 downto 0); 39 | variable len_temp : std_logic_vector (6 downto 0); 40 | variable l : std_logic_vector (6 downto 0); 41 | begin 42 | dw := "00000000"; 43 | if (unsigned(len)) < 5 then 44 | l := std_logic_vector(unsigned(len) - 1); 45 | else 46 | l := "0000011"; 47 | end if; 48 | -- assign first DW 49 | -- is solved with Karnaugh map 50 | dw(0) := (not addr(0)) and (not addr(1)); 51 | dw(1) := (addr(0) and (not addr(1))) or (l(0) and (not addr(1))) or (l(1) and (not addr(1))); 52 | dw(2) := ((not addr(0)) and addr(1)) or (l(1) and (not addr(1))) or (l(0) and addr(0) and (not addr(1))); 53 | dw(3) := (l(1) or addr(1)) and (l(0) or addr(0) or addr(1)) and (l(0) or l(1) or addr(0)); 54 | -- assign last DW 55 | len_temp := std_logic_vector(unsigned(len) - dw(0) - dw(1) - dw(2) - dw(3)); 56 | if (unsigned(len_temp)) > 0 then 57 | case len_temp(1 downto 0) is 58 | when "00" => dw(7 downto 4) := "1111"; 59 | when "01" => dw(7 downto 4) := "0001"; 60 | when "10" => dw(7 downto 4) := "0011"; 61 | when "11" => dw(7 downto 4) := "0111"; 62 | when others => 63 | end case; 64 | end if; 65 | return dw; 66 | end dw_assign; 67 | 68 | -------------------------------------------------------------------------------- 69 | -- length field in TLP packet calculate 70 | -------------------------------------------------------------------------------- 71 | function len_calc (addr : std_logic_vector (1 downto 0); len : std_logic_vector (6 downto 0)) return std_logic_vector is 72 | variable len_t : std_logic_vector (9 downto 0); 73 | begin 74 | if (unsigned(len)) >= 4 then 75 | -- lenght = (len + addr + 3)/4 76 | len_t := std_logic_vector(unsigned(addr) + ("000"&(unsigned(len)) + 3)); 77 | else 78 | len_t := "0000000100"; 79 | if (unsigned(len)) = 2 and (unsigned(addr)) = 3 then len_t := "0000001000"; end if; 80 | if (unsigned(len)) = 3 and (unsigned(addr)) > 1 then len_t := "0000001000"; end if; 81 | end if; 82 | return "00" & len_t (9 downto 2); 83 | end len_calc; 84 | 85 | end package body; 86 | -------------------------------------------------------------------------------- /html/test.htm: -------------------------------------------------------------------------------- 1 | 2 | 3 |
4 | 45 | 46 | 47 | 48 |To make a cell span more than one column, use the colspan attribute.
50 | 51 || Packet | 54 |R ← | 55 |TLP | 56 |Cpl | 57 |CplD | 58 |Length | 59 |RequesterID | 60 |Tag | 61 |CompleterID | 62 |Status | 63 |BCM | 64 |Byte Cnt | 65 |Lwr Addr | 66 |Data | 67 |LCRC | 68 |Time Delta | 69 |Time | 70 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 142 | 73 |184 | 74 |010:01010 | 75 |1 | 76 |000:00:0 | 77 |0 | 78 |000:00:0 | 79 |SC | 80 |0 | 81 |4 | 82 |0x0C | 83 |
84 | 10 dword
85 | 0xfb000040, 0x00000400, 0x00, 0x54, 0xff, 0x70, 0x01, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x84, 0x90, 0xc7, 0x6e, 0xfd
86 |
87 |
88 | |
89 | 0xE2C9329D | 90 |576.000 ns | 91 |1000 ns | 92 |
| Packet | 97 |R → | 98 |TLP | 99 |Cpl | 100 |CplD | 101 |Length | 102 |RequesterID | 103 |Tag | 104 |CompleterID | 105 |Status | 106 |BCM | 107 |Byte Cnt | 108 |Lwr Addr | 109 |Data | 110 |LCRC | 111 |Time Delta | 112 |Time | 113 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 144 | 116 |184 | 117 |010:01010 | 118 |1 | 119 |000:00:0 | 120 |0 | 121 |000:00:0 | 122 |SC | 123 |0 | 124 |4 | 125 |0x0C | 126 |DATA | 127 |0xE2C9329D | 128 |576.000 ns | 129 |1000 ns | 130 |