├── LIB
├── PCE.INC
└── PCE_VECTOR.ASM
├── PSG
└── PlaySample
│ ├── LIB
│ ├── PCE.INC
│ └── PCE_VECTOR.ASM
│ ├── PlaySample.asm
│ ├── PlaySample.pce
│ └── make.bat
├── README.md
└── VDC
├── GreenSpace
├── GreenSpace.asm
├── GreenSpace.pce
├── GreenSpace.png
├── LIB
│ ├── PCE.INC
│ └── PCE_VECTOR.ASM
└── make.bat
└── HelloWorld
├── Font8x8.asm
├── HelloWorld.asm
├── HelloWorld.pce
├── HelloWorld.png
├── LIB
├── PCE.INC
└── PCE_VECTOR.ASM
└── make.bat
/LIB/PCE.INC:
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1 | //=================== (Key: R=Read, W=Write)
2 | // PC-Engine Include
3 | //===================
4 | // Memory Map
5 | // Physical Address | Segment : Address
6 | // $000000..$0FFFFF | $00:0000..$7F:1FFF - HuCard/TurboChip ROM 1MB/R
7 | // $1F0000..$1F7FFF | $F8:0000..$FB:1FFF - Work RAM (8KB, Mirrored Four Times) 32KB/RW
8 | // $1FE000..$1FE3FF | $FF:0000..$FF:03FF - VDC Registers (HuC6270) 1KB/RW
9 | // $1FE400..$1FE7FF | $FF:0400..$FF:07FF - VCE Registers (HuC6260) 1KB/RW
10 | // $1FE800..$1FEBFF | $FF:0800..$FF:0BFF - PSG Registers 1KB/RW
11 | // $1FF000..$1FF3FF | $FF:1000..$FF:13FF - 8-Bit I/O Port 1KB/RW
12 | // $1FF400..$1FF7FF | $FF:1400..$FF:17FF - Interrupt Controller 1KB/RW
13 |
14 | // Segment Registers (Use TMA/TAM To Read/Write Segment Registers, Can Write To Multiple Registers At Once)
15 | constant MPR0($01) // MPR0 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
16 | constant MPR1($02) // MPR1 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
17 | constant MPR2($04) // MPR2 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
18 | constant MPR3($08) // MPR3 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
19 | constant MPR4($10) // MPR4 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
20 | constant MPR5($20) // MPR5 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
21 | constant MPR6($40) // MPR6 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
22 | constant MPR7($80) // MPR7 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
23 |
24 | // VDC Registers (HuC6270) (Mapped To Segment $FF:XXXX)
25 | constant VDC_STATUS($0000) // VDC Status Register 2B/R
26 | constant VDC_CR_FLAG($01) // VDC Status Read: Bit 0 - CR Flag (Set On Sprite #0 Collision) 1Bit/R
27 | constant VDC_OR_FLAG($02) // VDC Status Read: Bit 1 - OR Flag (Set On Sprite Overflow) 1Bit/R
28 | constant VDC_PR_FLAG($04) // VDC Status Read: Bit 2 - PR Flag (Set On Scanline Interrupt) 1Bit/R
29 | constant VDC_DS_FLAG($08) // VDC Status Read: Bit 3 - DS Flag (Set On VRAM -> SATB Transfer Complete) 1Bit/R
30 | constant VDC_DV_FLAG($10) // VDC Status Read: Bit 4 - DV Flag (Set On VRAM DMA Transfer Complete) 1Bit/R
31 | constant VDC_VD_FLAG($20) // VDC Status Read: Bit 5 - VD Flag (Set On Vertical Blank) 1Bit/R
32 | constant VDC_BSY_FLAG($40) // VDC Status Read: Bit 6 - BSY Flag (Set On VRAM DMA Transfer Busy) 1Bit/R
33 | // VDC Status Read: Bit 7..15 - Unused 9Bit/R
34 |
35 | constant VDC_ADDR($0000) // VDC Address Register: ST0 Opcode Can Store Immediate Value Here 2B/W
36 | // VDC Address Write: Bit 0..4 - VDC Register Address Access 5Bit/W
37 | // VDC Address Write: Bit 5..15 - Unused 11Bit/W
38 |
39 | constant VDC_DATAL($0002) // VDC Data LSB Register: ST1 Opcode Can Store Immediate Value Here 1B/RW
40 | constant VDC_DATAH($0003) // VDC Data MSB Register: ST2 Opcode Can Store Immediate Value Here 1B/RW
41 |
42 | // VDC Memory Map (Read/Write 2 Byte VDC Data To These Register Addresses)
43 | // VDC VRAM Registers
44 | constant VDC_MAWR($00) // VDC MAWR - Memory Address Write Register (VRAM Write Address) 2B/RW
45 | constant VDC_MARR($01) // VDC MARR - Memory Address Read Register (VRAM Read Address) 2B/RW
46 | constant VDC_VWR($02) // VDC VWR - VRAM Data Write Register 2B/RW
47 | constant VDC_VRR($02) // VDC VRR - VRAM Data Read Register 2B/RW
48 |
49 | constant VDC_CR($05) // VDC CR - Control Register 2B/RW
50 | // VDC L CR Read: Bit 0 - CR Flag (Set On Sprite #0 Collision) 1Bit/R
51 | // VDC L CR Read: Bit 1 - OR Flag (Set On Sprite Overflow) 1Bit/R
52 | // VDC L CR Read: Bit 2 - PR Flag (Set On Scanline Interrupt) 1Bit/R
53 | // VDC L CR Read: Bit 3 - VD Flag (Set On Vertical Blank) 1Bit/R
54 | // VDC L CR Read: Bit 4..15 - Unused 12Bit/R
55 |
56 | constant VDC_IE0($01) // VDC L CR Write: Bit 0 - IE Flag 0 (Interrupt Enable/Disable) 1Bit/W
57 | constant VDC_IE1($02) // VDC L CR Write: Bit 1 - IE Flag 1 (Interrupt Enable/Disable) 1Bit/W
58 | constant VDC_IE2($04) // VDC L CR Write: Bit 2 - IE Flag 2 (Interrupt Enable/Disable) 1Bit/W
59 | constant VDC_IE3($08) // VDC L CR Write: Bit 3 - IE Flag 3 (Interrupt Enable/Disable) 1Bit/W
60 | constant VDC_EXH($10) // VDC L CR Write: Bit 4 - EX Horizontal Sync (Signal Input/Output) 1Bit/W
61 | constant VDC_EXV($20) // VDC L CR Write: Bit 5 - EX Vertical Sync (Signal Input/Output) 1Bit/W
62 | constant VDC_SB($40) // VDC L CR Write: Bit 6 - SB Flag (Sprites Enable/Disable) 1Bit/W
63 | constant VDC_BB($80) // VDC L CR Write: Bit 7 - BB Flag (Background Enable/Disable) 1Bit/W
64 | constant VDC_DISP($00) // VDC H CR Write: Bit 8..9 - DR Selects DISP Terminal Output (%00) 2Bit/W
65 | constant VDC_BURST($01) // VDC H CR Write: Bit 8..9 - DR Selects BURST Terminal Output (%01) 2Bit/W
66 | constant VDC_INTHSYNC($02) // VDC H CR Write: Bit 8..9 - DR Selects INTHSYNC Terminal Output (%10) 2Bit/W
67 | // VDC H CR Write: Bit 8..9 - DR Selects Unused Terminal Output (%11) 2Bit/W
68 | constant VDC_DR($04) // VDC H CR Write: Bit 10 - DR Flag (Dynamic RAM Refresh Enable/Disable) 1Bit/W
69 | constant VDC_INC01($00) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $01 (%00) 2Bit/W
70 | constant VDC_INC20($08) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $20 (%01) 2Bit/W
71 | constant VDC_INC40($10) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $40 (%10) 2Bit/W
72 | constant VDC_INC80($18) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $80 (%11) 2Bit/W
73 | // VDC H CR Write: Bit 13..15 - Unused 3Bit/W
74 |
75 | constant VDC_RCR($06) // VDC RCR - Raster Counter Register 2B/RW
76 |
77 | constant VDC_BXR($07) // VDC BXR - Background X-Scroll Register 2B/RW
78 | // VDC BXR: Bit 0..9 - Screen X-Offset (In Pixels) 10Bit/RW
79 | // VDC BXR: Bit 10..15 - Unused 6Bit/RW
80 |
81 | constant VDC_BYR($08) // VDC BYR - Background Y-Scroll Register 2B/RW
82 | // VDC BYR: Bit 0..8 - Screen Y-Offset (In Pixels) 9Bit/RW
83 | // VDC BYR: Bit 9..15 - Unused 7Bit/RW
84 |
85 | constant VDC_MWR($09) // VDC MWR - Memory Width Register 2B/RW
86 | constant VDC_VW0($00) // VDC MWR: Bit 0..1 - VRAM Pixel Width 0 (%00) 2Bit/RW
87 | constant VDC_VW1($01) // VDC MWR: Bit 0..1 - VRAM Pixel Width 1 (%01) 2Bit/RW
88 | constant VDC_VW2($02) // VDC MWR: Bit 0..1 - VRAM Pixel Width 2 (%10) 2Bit/RW
89 | constant VDC_VW3($03) // VDC MWR: Bit 0..1 - VRAM Pixel Width 3 (%11) 2Bit/RW
90 | constant VDC_SW0($00) // VDC MWR: Bit 2..3 - Sprite Pixel Width 0 (%00) 2Bit/RW
91 | constant VDC_SW1($04) // VDC MWR: Bit 2..3 - Sprite Pixel Width 1 (%01) 2Bit/RW
92 | constant VDC_SW2($08) // VDC MWR: Bit 2..3 - Sprite Pixel Width 2 (%10) 2Bit/RW
93 | constant VDC_SW3($0C) // VDC MWR: Bit 2..3 - Sprite Pixel Width 3 (%11) 2Bit/RW
94 | constant VDC_SCRW32($00) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 32 (256 Pixels) (%00) 2Bit/RW
95 | constant VDC_SCRW64($10) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 64 (512 Pixels) (%01) 2Bit/RW
96 | constant VDC_SCRW128($20) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 128 (1024 Pixels) (%10) 2Bit/RW
97 | constant VDC_SCRW128B($30) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 128 (1024 Pixels) (%11) 2Bit/RW
98 | constant VDC_SCRH32($00) // VDC MWR: Bit 6 - Virtual Screen Tile Height 32 (256 Pixels) (%0) 1Bit/RW
99 | constant VDC_SCRH64($40) // VDC MWR: Bit 6 - Virtual Screen Tile Height 64 (512 Pixels) (%1) 1Bit/RW
100 | constant VDC_CM($80) // VDC MWR: Bit 7 - CM (Color Mode) 1Bit/RW
101 | // VDC MWR: Bit 8..15 - Unused 8Bit/RW
102 |
103 | // VDC Display Registers
104 | constant VDC_HSR($0A) // VDC HSR - Horizontal Synchronous Register 2B/RW
105 | constant VDC_HSW($1F) // VDC L HSR: Bit 0..4 - HSW (Horizontal Synchronous Pulse Width) 5Bit/RW
106 | // VDC L HSR: Bit 5..7 - Unused 3Bit/RW
107 | constant VDC_HDS($7F) // VDC H HSR: Bit 8..14 - HDS (Horizontal Display Starting Position) 7Bit/RW
108 | // VDC H HSR: Bit 15 - Unused 1Bit/RW
109 |
110 | constant VDC_HDR($0B) // VDC HDR - Horizontal Display Register 2B/RW
111 | constant VDC_HDW($7F) // VDC L HDR: Bit 0..6 - HDW (Horizontal Display Width) 7Bit/RW
112 | // VDC L HDR: Bit 7 - Unused 1Bit/RW
113 | constant VDC_HDE($7F) // VDC H HDR: Bit 8..14 - HDE (Horizontal Display End) 7Bit/RW
114 | // VDC H HDR: Bit 15 - Unused 1Bit/RW
115 |
116 | constant VDC_VSR($0C) // VDC VSR - Vertical Synchronous Register 2B/RW
117 | constant VDC_VSW($1F) // VDC L VSR: Bit 0..4 - VSW (Vertical Synchronous Pulse Width) 5Bit/RW
118 | // VDC L VSR: Bit 5..7 - Unused 3Bit/RW
119 | constant VDC_VDS($FF) // VDC H VSR: Bit 8..15 - VDS (Vertical Display Starting Position) 8Bit/RW
120 |
121 | constant VDC_VDR($0D) // VDC VDR - Vertical Display Register 2B/RW
122 | constant VDC_VCR($0E) // VDC VCR - Vertical Display Ending Postition Register 2B/RW
123 |
124 | // VDC DMA Registers
125 | constant VDC_DCR($0F) // VDC DCR - DMA Control Register 2B/RW
126 | constant VDC_DSC($01) // VDC DCR: Bit 0 - DSC VRAM & Sprite Attribute Table (Interrupt Enable/Disable) 1Bit/RW
127 | constant VDC_DVC($02) // VDC DCR: Bit 1 - DVC VRAM To VRAM Transfer (Interrupt Enable/Disable) 1Bit/RW
128 | constant VDC_SID($04) // VDC DCR: Bit 2 - SID VRAM To VRAM Source Increment/Decrement (1/0) 1Bit/RW
129 | constant VDC_DID($08) // VDC DCR: Bit 3 - DID VRAM To VRAM Destination Increment/Decrement (1/0) 1Bit/RW
130 | // VDC DCR: Bit 4 - Unused 1Bit/RW
131 | constant VDC_DSR($20) // VDC DCR: Bit 5 - DSR VRAM & Sprite Attribute Table Repetition (Enable/Disable) 1Bit/RW
132 | // VDC DCR: Bit 6..15 - Unused 10Bit/RW
133 |
134 | constant VDC_SOUR($10) // VDC SOUR - Source Address Register 2B/RW
135 | constant VDC_DESR($11) // VDC DESR - DMA Destination Address Register 2B/RW
136 | constant VDC_LENR($12) // VDC LENR - DMA Block Length Register 2B/RW
137 | constant VDC_SATB($13) // VDC SATB - Sprite Attribute Table Address Register 2B/RW
138 |
139 | // VCE Registers (HuC6260) (Mapped To Segment $FF:XXXX)
140 | constant VCE_CR($0400) // VCE CR - Control Register 2B/W
141 | constant VCE_PCC0($00) // VCE CR: Bit 0..1 - PCC 5.3693175 MHz (Pixel Clock Control) (%00) 2Bit/W
142 | constant VCE_PCC1($01) // VCE CR: Bit 0..1 - PCC 7.15909 MHz (Pixel Clock Control) (%01) 2Bit/W
143 | constant VCE_PCC2($02) // VCE CR: Bit 0..1 - PCC 10.738635 MHz (Pixel Clock Control) (%10) 2Bit/W
144 | constant VCE_PCC3($03) // VCE CR: Bit 0..1 - PCC 10.738635 MHz (Pixel Clock Control) (%11) 2Bit/W
145 | constant VCE_FC0($00) // VCE CR: Bit 2 - FC 262 Line Frame (Frame/Field Configuration) (%0) 1Bit/W
146 | constant VCE_FC1($04) // VCE CR: Bit 2 - FC 263 Line Frame (Frame/Field Configuration) (%1) 1Bit/W
147 | // VCE CR: Bit 3..6 - Unused 4Bit/W
148 | constant VCE_SC0($00) // VCE CR: Bit 7 - SC Colorburst Intact (Strip Colorburst) (%0) 1Bit/W
149 | constant VCE_SC1($08) // VCE CR: Bit 7 - SC Strip Colorburst (Strip Colorburst) (%1) 1Bit/W
150 | // VCE CR: Bit 8..15 - Unused 8Bit/W
151 |
152 | constant VCE_CTA($0402) // VCE CTA - Color Table Address Register 2B/W
153 | // VCE CTA: Bit 0..8 - Color Table Index (0..511) 9Bit/W
154 | // VCE CTA: Bit 9..15 - Unused 7Bit/W
155 |
156 | constant VCE_CTRW($0404) // VCE CTRW - Color Table Read/Write Register (BRG333) 2B/RW
157 | // VCE CTRW: Bit 0..2 - Blue 3Bit/RW
158 | // VCE CTRW: Bit 3..5 - Red 3Bit/RW
159 | // VCE CTRW: Bit 6..8 - Green 3Bit/RW
160 | // VCE CTRW: Bit 9..15 - Unused 7Bit/RW
161 |
162 | // PSG Registers (Mapped To Segment $FF:XXXX) (Write Only)
163 | constant PSG_R0($0800) // PSG Register 0 - Channel Select (Selects Channel For Use With PSG Registers R2..R9) 1B/W
164 | // PSG Register 0: Bit 0..2 - Channel Number (Only 0..5 Valid) 3Bit/W
165 | // PSG Register 0: Bit 3..7 - Unused 5Bit/W
166 |
167 | constant PSG_R1($0801) // PSG Register 1 - Global Sound Balance (Overall Sound Volume For Mixed Channels) 1B/W
168 | // PSG Register 1: Bit 0..3 - Volume From Right Output 4Bit/W
169 | // PSG Register 1: Bit 4..7 - Volume From Left Output 4Bit/W
170 |
171 | constant PSG_R2($0802) // PSG Register 2 - Fine Frequency Adjust (Lower 8-Bits Of 12-Bit Channel Frequency) 1B/W
172 | // PSG Register 2: Bit 0..7 - Fine Frequency Adjust 8Bit/W
173 |
174 | constant PSG_R3($0803) // PSG Register 3 - Rough Frequency Adjust (Upper 4-Bits Of 12-Bit Channel Frequency) 1B/W
175 | // PSG Register 3: Bit 0..3 - Rough Frequency Adjust 4Bit/W
176 | // PSG Register 3: Bit 4..7 - Unused 4Bit/W
177 |
178 | constant PSG_R4($0804) // PSG Register 4 - Channel Enable, DDA Enable, Channel Volume 1B/W
179 | // PSG Register 4: Bit 0..4 - Overall Channel Volume 5Bit/W
180 | // PSG Register 4: Bit 5 - Unused 1Bit/W
181 | constant PSG_DDA($40) // PSG Register 4: Bit 6 - DDA Output Enable/Disable (1/0) 1Bit/W
182 | constant PSG_CHAN($80) // PSG Register 4: Bit 7 - Channel Enable/Disable (1/0) 1Bit/W
183 |
184 | constant PSG_R5($0805) // PSG Register 5 - Channel Balance (Volume Balance Of An Individual Channel) 1B/W
185 | // PSG Register 5: Bit 0..3 - Volume To Right Output 4Bit/W
186 | // PSG Register 5: Bit 4..7 - Volume To Left Output 4Bit/W
187 |
188 | constant PSG_R6($0806) // PSG Register 6 - Channel Sound Data (5-Bit Unsigned Linear Sample Data) 1B/W
189 | // PSG Register 6: Bit 0..4 - 5-Bit Unsigned Linear Sample Data 5Bit/W
190 | // PSG Register 6: Bit 5..7 - Unused 3Bit/W
191 |
192 | constant PSG_R7($0807) // PSG Register 7 - Noise Enable, Noise Frequency (Only Effective For Channels 4 & 5) 1B/W
193 | // PSG Register 7: Bit 0..4 - Noise Frequency 5Bit/W
194 | // PSG Register 7: Bit 5..6 - Unused 2Bit/W
195 | constant PSG_NOISE($80) // PSG Register 7: Bit 7 - Noise Enable/Disable (1/0)
196 |
197 | constant PSG_R8($0808) // PSG Register 8 - LFO Frequency (Uses Channel 1 Waveform Buffer As Frequency Modulation) 1B/W
198 |
199 | constant PSG_R9($0809) // PSG Register 9 - LFO Trigger, LFO Control 1B/W
200 | constant PSG_LFO0($00) // PSG Register 9: Bit 0..1 - No Frequency Modulation Is Performed (LFO Control) %00 2Bit/W
201 | constant PSG_LFO1($01) // PSG Register 9: Bit 0..1 - FM Data Added To Channel 0 Frequency (LFO Control) %01 2Bit/W
202 | constant PSG_LFO2($02) // PSG Register 9: Bit 0..1 - FM Data << 4 Then Added To The Frequency (LFO Control) %10 2Bit/W
203 | constant PSG_LFO3($03) // PSG Register 9: Bit 0..1 - FM Data << 8 Then Added To The Frequency (LFO Control) %11 2Bit/W
204 | // PSG Register 9: Bit 2..6 - Unused 5Bit/W
205 | constant PSG_LFO($80) // PSG Register 9: Bit 7 - LFO Trigger Enable/Disable (0/1) 1Bit/W
206 |
207 | // 8-Bit I/O Port (Mapped To Segment $FF:XXXX)
208 | constant JOYIO($1000) // JOYIO - Joypad I/O Port Register 1B/R
209 | constant TRG1($01) // JOYIO: Bit 0 - Joypad Trigger 1 1Bit/R
210 | constant TRG2($02) // JOYIO: Bit 1 - Joypad Trigger 2 1Bit/R
211 | constant SEL($04) // JOYIO: Bit 2 - Joypad Select Button 1Bit/R
212 | constant RUN($08) // JOYIO: Bit 3 - Joypad Run Button 1Bit/R
213 | constant UP($10) // JOYIO: Bit 4 - Joypad Direction Up 1Bit/R
214 | constant RIGHT($20) // JOYIO: Bit 5 - Joypad Direction Right 1Bit/R
215 | constant DOWN($40) // JOYIO: Bit 6 - Joypad Direction Down 1Bit/R
216 | constant LEFT($80) // JOYIO: Bit 7 - Joypad Direction Left 1Bit/R
217 |
218 | // PC-Engine Initialisation
219 | macro PCE_INIT() {
220 | // VDC: Set VRAM Write Address To Zero
221 | st0 #VDC_MAWR // VDC: Set VDC Address To Memory Address Write Register (VRAM Write Address) (MAWR)
222 | st1 #0 // VDC: Data = 0 (Lo Byte)
223 | st2 #0 // VDC: Data = 0 (Hi Byte)
224 |
225 | // VDC: Clear 65536 VRAM Bytes To Zero
226 | st0 #VDC_VWR // VDC: Set VDC Address To VRAM Data Write Register (VWR)
227 | ldx #0
228 | ldy #128
229 | -
230 | st1 #0 // VDC: Data = 0 (Lo Byte)
231 | st2 #0 // VDC: Data = 0 (Hi Byte)
232 | dex
233 | bne -
234 | dey
235 | bne -
236 | }
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/LIB/PCE_VECTOR.ASM:
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1 | //==================
2 | // PC-Engine VECTOR
3 | //==================
4 | seek($FFF6)
5 | // VECTOR (HuC6280 Mode)
6 | dw $0000 // IRQ2 VECTOR (BRK)
7 | dw $0000 // IRQ1 VECTOR (VDC)
8 | dw $0000 // TIMER VECTOR
9 | dw $0000 // NMI VECTOR
10 | dw $0000 // RESET VECTOR
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/PSG/PlaySample/LIB/PCE.INC:
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1 | //=================== (Key: R=Read, W=Write)
2 | // PC-Engine Include
3 | //===================
4 | // Memory Map
5 | // Physical Address | Segment : Address
6 | // $000000..$0FFFFF | $00:0000..$7F:1FFF - HuCard/TurboChip ROM 1MB/R
7 | // $1F0000..$1F7FFF | $F8:0000..$FB:1FFF - Work RAM (8KB, Mirrored Four Times) 32KB/RW
8 | // $1FE000..$1FE3FF | $FF:0000..$FF:03FF - VDC Registers (HuC6270) 1KB/RW
9 | // $1FE400..$1FE7FF | $FF:0400..$FF:07FF - VCE Registers (HuC6260) 1KB/RW
10 | // $1FE800..$1FEBFF | $FF:0800..$FF:0BFF - PSG Registers 1KB/RW
11 | // $1FF000..$1FF3FF | $FF:1000..$FF:13FF - 8-Bit I/O Port 1KB/RW
12 | // $1FF400..$1FF7FF | $FF:1400..$FF:17FF - Interrupt Controller 1KB/RW
13 |
14 | // Segment Registers (Use TMA/TAM To Read/Write Segment Registers, Can Write To Multiple Registers At Once)
15 | constant MPR0($01) // MPR0 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
16 | constant MPR1($02) // MPR1 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
17 | constant MPR2($04) // MPR2 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
18 | constant MPR3($08) // MPR3 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
19 | constant MPR4($10) // MPR4 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
20 | constant MPR5($20) // MPR5 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
21 | constant MPR6($40) // MPR6 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
22 | constant MPR7($80) // MPR7 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
23 |
24 | // VDC Registers (HuC6270) (Mapped To Segment $FF:XXXX)
25 | constant VDC_STATUS($0000) // VDC Status Register 2B/R
26 | constant VDC_CR_FLAG($01) // VDC Status Read: Bit 0 - CR Flag (Set On Sprite #0 Collision) 1Bit/R
27 | constant VDC_OR_FLAG($02) // VDC Status Read: Bit 1 - OR Flag (Set On Sprite Overflow) 1Bit/R
28 | constant VDC_PR_FLAG($04) // VDC Status Read: Bit 2 - PR Flag (Set On Scanline Interrupt) 1Bit/R
29 | constant VDC_DS_FLAG($08) // VDC Status Read: Bit 3 - DS Flag (Set On VRAM -> SATB Transfer Complete) 1Bit/R
30 | constant VDC_DV_FLAG($10) // VDC Status Read: Bit 4 - DV Flag (Set On VRAM DMA Transfer Complete) 1Bit/R
31 | constant VDC_VD_FLAG($20) // VDC Status Read: Bit 5 - VD Flag (Set On Vertical Blank) 1Bit/R
32 | constant VDC_BSY_FLAG($40) // VDC Status Read: Bit 6 - BSY Flag (Set On VRAM DMA Transfer Busy) 1Bit/R
33 | // VDC Status Read: Bit 7..15 - Unused 9Bit/R
34 |
35 | constant VDC_ADDR($0000) // VDC Address Register: ST0 Opcode Can Store Immediate Value Here 2B/W
36 | // VDC Address Write: Bit 0..4 - VDC Register Address Access 5Bit/W
37 | // VDC Address Write: Bit 5..15 - Unused 11Bit/W
38 |
39 | constant VDC_DATAL($0002) // VDC Data LSB Register: ST1 Opcode Can Store Immediate Value Here 1B/RW
40 | constant VDC_DATAH($0003) // VDC Data MSB Register: ST2 Opcode Can Store Immediate Value Here 1B/RW
41 |
42 | // VDC Memory Map (Read/Write 2 Byte VDC Data To These Register Addresses)
43 | // VDC VRAM Registers
44 | constant VDC_MAWR($00) // VDC MAWR - Memory Address Write Register (VRAM Write Address) 2B/RW
45 | constant VDC_MARR($01) // VDC MARR - Memory Address Read Register (VRAM Read Address) 2B/RW
46 | constant VDC_VWR($02) // VDC VWR - VRAM Data Write Register 2B/RW
47 | constant VDC_VRR($02) // VDC VRR - VRAM Data Read Register 2B/RW
48 |
49 | constant VDC_CR($05) // VDC CR - Control Register 2B/RW
50 | // VDC L CR Read: Bit 0 - CR Flag (Set On Sprite #0 Collision) 1Bit/R
51 | // VDC L CR Read: Bit 1 - OR Flag (Set On Sprite Overflow) 1Bit/R
52 | // VDC L CR Read: Bit 2 - PR Flag (Set On Scanline Interrupt) 1Bit/R
53 | // VDC L CR Read: Bit 3 - VD Flag (Set On Vertical Blank) 1Bit/R
54 | // VDC L CR Read: Bit 4..15 - Unused 12Bit/R
55 |
56 | constant VDC_IE0($01) // VDC L CR Write: Bit 0 - IE Flag 0 (Interrupt Enable/Disable) 1Bit/W
57 | constant VDC_IE1($02) // VDC L CR Write: Bit 1 - IE Flag 1 (Interrupt Enable/Disable) 1Bit/W
58 | constant VDC_IE2($04) // VDC L CR Write: Bit 2 - IE Flag 2 (Interrupt Enable/Disable) 1Bit/W
59 | constant VDC_IE3($08) // VDC L CR Write: Bit 3 - IE Flag 3 (Interrupt Enable/Disable) 1Bit/W
60 | constant VDC_EXH($10) // VDC L CR Write: Bit 4 - EX Horizontal Sync (Signal Input/Output) 1Bit/W
61 | constant VDC_EXV($20) // VDC L CR Write: Bit 5 - EX Vertical Sync (Signal Input/Output) 1Bit/W
62 | constant VDC_SB($40) // VDC L CR Write: Bit 6 - SB Flag (Sprites Enable/Disable) 1Bit/W
63 | constant VDC_BB($80) // VDC L CR Write: Bit 7 - BB Flag (Background Enable/Disable) 1Bit/W
64 | constant VDC_DISP($00) // VDC H CR Write: Bit 8..9 - DR Selects DISP Terminal Output (%00) 2Bit/W
65 | constant VDC_BURST($01) // VDC H CR Write: Bit 8..9 - DR Selects BURST Terminal Output (%01) 2Bit/W
66 | constant VDC_INTHSYNC($02) // VDC H CR Write: Bit 8..9 - DR Selects INTHSYNC Terminal Output (%10) 2Bit/W
67 | // VDC H CR Write: Bit 8..9 - DR Selects Unused Terminal Output (%11) 2Bit/W
68 | constant VDC_DR($04) // VDC H CR Write: Bit 10 - DR Flag (Dynamic RAM Refresh Enable/Disable) 1Bit/W
69 | constant VDC_INC01($00) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $01 (%00) 2Bit/W
70 | constant VDC_INC20($08) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $20 (%01) 2Bit/W
71 | constant VDC_INC40($10) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $40 (%10) 2Bit/W
72 | constant VDC_INC80($18) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $80 (%11) 2Bit/W
73 | // VDC H CR Write: Bit 13..15 - Unused 3Bit/W
74 |
75 | constant VDC_RCR($06) // VDC RCR - Raster Counter Register 2B/RW
76 |
77 | constant VDC_BXR($07) // VDC BXR - Background X-Scroll Register 2B/RW
78 | // VDC BXR: Bit 0..9 - Screen X-Offset (In Pixels) 10Bit/RW
79 | // VDC BXR: Bit 10..15 - Unused 6Bit/RW
80 |
81 | constant VDC_BYR($08) // VDC BYR - Background Y-Scroll Register 2B/RW
82 | // VDC BYR: Bit 0..8 - Screen Y-Offset (In Pixels) 9Bit/RW
83 | // VDC BYR: Bit 9..15 - Unused 7Bit/RW
84 |
85 | constant VDC_MWR($09) // VDC MWR - Memory Width Register 2B/RW
86 | constant VDC_VW0($00) // VDC MWR: Bit 0..1 - VRAM Pixel Width 0 (%00) 2Bit/RW
87 | constant VDC_VW1($01) // VDC MWR: Bit 0..1 - VRAM Pixel Width 1 (%01) 2Bit/RW
88 | constant VDC_VW2($02) // VDC MWR: Bit 0..1 - VRAM Pixel Width 2 (%10) 2Bit/RW
89 | constant VDC_VW3($03) // VDC MWR: Bit 0..1 - VRAM Pixel Width 3 (%11) 2Bit/RW
90 | constant VDC_SW0($00) // VDC MWR: Bit 2..3 - Sprite Pixel Width 0 (%00) 2Bit/RW
91 | constant VDC_SW1($04) // VDC MWR: Bit 2..3 - Sprite Pixel Width 1 (%01) 2Bit/RW
92 | constant VDC_SW2($08) // VDC MWR: Bit 2..3 - Sprite Pixel Width 2 (%10) 2Bit/RW
93 | constant VDC_SW3($0C) // VDC MWR: Bit 2..3 - Sprite Pixel Width 3 (%11) 2Bit/RW
94 | constant VDC_SCRW32($00) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 32 (256 Pixels) (%00) 2Bit/RW
95 | constant VDC_SCRW64($10) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 64 (512 Pixels) (%01) 2Bit/RW
96 | constant VDC_SCRW128($20) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 128 (1024 Pixels) (%10) 2Bit/RW
97 | constant VDC_SCRW128B($30) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 128 (1024 Pixels) (%11) 2Bit/RW
98 | constant VDC_SCRH32($00) // VDC MWR: Bit 6 - Virtual Screen Tile Height 32 (256 Pixels) (%0) 1Bit/RW
99 | constant VDC_SCRH64($40) // VDC MWR: Bit 6 - Virtual Screen Tile Height 64 (512 Pixels) (%1) 1Bit/RW
100 | constant VDC_CM($80) // VDC MWR: Bit 7 - CM (Color Mode) 1Bit/RW
101 | // VDC MWR: Bit 8..15 - Unused 8Bit/RW
102 |
103 | // VDC Display Registers
104 | constant VDC_HSR($0A) // VDC HSR - Horizontal Synchronous Register 2B/RW
105 | constant VDC_HSW($1F) // VDC L HSR: Bit 0..4 - HSW (Horizontal Synchronous Pulse Width) 5Bit/RW
106 | // VDC L HSR: Bit 5..7 - Unused 3Bit/RW
107 | constant VDC_HDS($7F) // VDC H HSR: Bit 8..14 - HDS (Horizontal Display Starting Position) 7Bit/RW
108 | // VDC H HSR: Bit 15 - Unused 1Bit/RW
109 |
110 | constant VDC_HDR($0B) // VDC HDR - Horizontal Display Register 2B/RW
111 | constant VDC_HDW($7F) // VDC L HDR: Bit 0..6 - HDW (Horizontal Display Width) 7Bit/RW
112 | // VDC L HDR: Bit 7 - Unused 1Bit/RW
113 | constant VDC_HDE($7F) // VDC H HDR: Bit 8..14 - HDE (Horizontal Display End) 7Bit/RW
114 | // VDC H HDR: Bit 15 - Unused 1Bit/RW
115 |
116 | constant VDC_VSR($0C) // VDC VSR - Vertical Synchronous Register 2B/RW
117 | constant VDC_VSW($1F) // VDC L VSR: Bit 0..4 - VSW (Vertical Synchronous Pulse Width) 5Bit/RW
118 | // VDC L VSR: Bit 5..7 - Unused 3Bit/RW
119 | constant VDC_VDS($FF) // VDC H VSR: Bit 8..15 - VDS (Vertical Display Starting Position) 8Bit/RW
120 |
121 | constant VDC_VDR($0D) // VDC VDR - Vertical Display Register 2B/RW
122 | constant VDC_VCR($0E) // VDC VCR - Vertical Display Ending Postition Register 2B/RW
123 |
124 | // VDC DMA Registers
125 | constant VDC_DCR($0F) // VDC DCR - DMA Control Register 2B/RW
126 | constant VDC_DSC($01) // VDC DCR: Bit 0 - DSC VRAM & Sprite Attribute Table (Interrupt Enable/Disable) 1Bit/RW
127 | constant VDC_DVC($02) // VDC DCR: Bit 1 - DVC VRAM To VRAM Transfer (Interrupt Enable/Disable) 1Bit/RW
128 | constant VDC_SID($04) // VDC DCR: Bit 2 - SID VRAM To VRAM Source Increment/Decrement (1/0) 1Bit/RW
129 | constant VDC_DID($08) // VDC DCR: Bit 3 - DID VRAM To VRAM Destination Increment/Decrement (1/0) 1Bit/RW
130 | // VDC DCR: Bit 4 - Unused 1Bit/RW
131 | constant VDC_DSR($20) // VDC DCR: Bit 5 - DSR VRAM & Sprite Attribute Table Repetition (Enable/Disable) 1Bit/RW
132 | // VDC DCR: Bit 6..15 - Unused 10Bit/RW
133 |
134 | constant VDC_SOUR($10) // VDC SOUR - Source Address Register 2B/RW
135 | constant VDC_DESR($11) // VDC DESR - DMA Destination Address Register 2B/RW
136 | constant VDC_LENR($12) // VDC LENR - DMA Block Length Register 2B/RW
137 | constant VDC_SATB($13) // VDC SATB - Sprite Attribute Table Address Register 2B/RW
138 |
139 | // VCE Registers (HuC6260) (Mapped To Segment $FF:XXXX)
140 | constant VCE_CR($0400) // VCE CR - Control Register 2B/W
141 | constant VCE_PCC0($00) // VCE CR: Bit 0..1 - PCC 5.3693175 MHz (Pixel Clock Control) (%00) 2Bit/W
142 | constant VCE_PCC1($01) // VCE CR: Bit 0..1 - PCC 7.15909 MHz (Pixel Clock Control) (%01) 2Bit/W
143 | constant VCE_PCC2($02) // VCE CR: Bit 0..1 - PCC 10.738635 MHz (Pixel Clock Control) (%10) 2Bit/W
144 | constant VCE_PCC3($03) // VCE CR: Bit 0..1 - PCC 10.738635 MHz (Pixel Clock Control) (%11) 2Bit/W
145 | constant VCE_FC0($00) // VCE CR: Bit 2 - FC 262 Line Frame (Frame/Field Configuration) (%0) 1Bit/W
146 | constant VCE_FC1($04) // VCE CR: Bit 2 - FC 263 Line Frame (Frame/Field Configuration) (%1) 1Bit/W
147 | // VCE CR: Bit 3..6 - Unused 4Bit/W
148 | constant VCE_SC0($00) // VCE CR: Bit 7 - SC Colorburst Intact (Strip Colorburst) (%0) 1Bit/W
149 | constant VCE_SC1($08) // VCE CR: Bit 7 - SC Strip Colorburst (Strip Colorburst) (%1) 1Bit/W
150 | // VCE CR: Bit 8..15 - Unused 8Bit/W
151 |
152 | constant VCE_CTA($0402) // VCE CTA - Color Table Address Register 2B/W
153 | // VCE CTA: Bit 0..8 - Color Table Index (0..511) 9Bit/W
154 | // VCE CTA: Bit 9..15 - Unused 7Bit/W
155 |
156 | constant VCE_CTRW($0404) // VCE CTRW - Color Table Read/Write Register (BRG333) 2B/RW
157 | // VCE CTRW: Bit 0..2 - Blue 3Bit/RW
158 | // VCE CTRW: Bit 3..5 - Red 3Bit/RW
159 | // VCE CTRW: Bit 6..8 - Green 3Bit/RW
160 | // VCE CTRW: Bit 9..15 - Unused 7Bit/RW
161 |
162 | // PSG Registers (Mapped To Segment $FF:XXXX) (Write Only)
163 | constant PSG_R0($0800) // PSG Register 0 - Channel Select (Selects Channel For Use With PSG Registers R2..R9) 1B/W
164 | // PSG Register 0: Bit 0..2 - Channel Number (Only 0..5 Valid) 3Bit/W
165 | // PSG Register 0: Bit 3..7 - Unused 5Bit/W
166 |
167 | constant PSG_R1($0801) // PSG Register 1 - Global Sound Balance (Overall Sound Volume For Mixed Channels) 1B/W
168 | // PSG Register 1: Bit 0..3 - Volume From Right Output 4Bit/W
169 | // PSG Register 1: Bit 4..7 - Volume From Left Output 4Bit/W
170 |
171 | constant PSG_R2($0802) // PSG Register 2 - Fine Frequency Adjust (Lower 8-Bits Of 12-Bit Channel Frequency) 1B/W
172 | // PSG Register 2: Bit 0..7 - Fine Frequency Adjust 8Bit/W
173 |
174 | constant PSG_R3($0803) // PSG Register 3 - Rough Frequency Adjust (Upper 4-Bits Of 12-Bit Channel Frequency) 1B/W
175 | // PSG Register 3: Bit 0..3 - Rough Frequency Adjust 4Bit/W
176 | // PSG Register 3: Bit 4..7 - Unused 4Bit/W
177 |
178 | constant PSG_R4($0804) // PSG Register 4 - Channel Enable, DDA Enable, Channel Volume 1B/W
179 | // PSG Register 4: Bit 0..4 - Overall Channel Volume 5Bit/W
180 | // PSG Register 4: Bit 5 - Unused 1Bit/W
181 | constant PSG_DDA($40) // PSG Register 4: Bit 6 - DDA Output Enable/Disable (1/0) 1Bit/W
182 | constant PSG_CHAN($80) // PSG Register 4: Bit 7 - Channel Enable/Disable (1/0) 1Bit/W
183 |
184 | constant PSG_R5($0805) // PSG Register 5 - Channel Balance (Volume Balance Of An Individual Channel) 1B/W
185 | // PSG Register 5: Bit 0..3 - Volume To Right Output 4Bit/W
186 | // PSG Register 5: Bit 4..7 - Volume To Left Output 4Bit/W
187 |
188 | constant PSG_R6($0806) // PSG Register 6 - Channel Sound Data (5-Bit Unsigned Linear Sample Data) 1B/W
189 | // PSG Register 6: Bit 0..4 - 5-Bit Unsigned Linear Sample Data 5Bit/W
190 | // PSG Register 6: Bit 5..7 - Unused 3Bit/W
191 |
192 | constant PSG_R7($0807) // PSG Register 7 - Noise Enable, Noise Frequency (Only Effective For Channels 4 & 5) 1B/W
193 | // PSG Register 7: Bit 0..4 - Noise Frequency 5Bit/W
194 | // PSG Register 7: Bit 5..6 - Unused 2Bit/W
195 | constant PSG_NOISE($80) // PSG Register 7: Bit 7 - Noise Enable/Disable (1/0)
196 |
197 | constant PSG_R8($0808) // PSG Register 8 - LFO Frequency (Uses Channel 1 Waveform Buffer As Frequency Modulation) 1B/W
198 |
199 | constant PSG_R9($0809) // PSG Register 9 - LFO Trigger, LFO Control 1B/W
200 | constant PSG_LFO0($00) // PSG Register 9: Bit 0..1 - No Frequency Modulation Is Performed (LFO Control) %00 2Bit/W
201 | constant PSG_LFO1($01) // PSG Register 9: Bit 0..1 - FM Data Added To Channel 0 Frequency (LFO Control) %01 2Bit/W
202 | constant PSG_LFO2($02) // PSG Register 9: Bit 0..1 - FM Data << 4 Then Added To The Frequency (LFO Control) %10 2Bit/W
203 | constant PSG_LFO3($03) // PSG Register 9: Bit 0..1 - FM Data << 8 Then Added To The Frequency (LFO Control) %11 2Bit/W
204 | // PSG Register 9: Bit 2..6 - Unused 5Bit/W
205 | constant PSG_LFO($80) // PSG Register 9: Bit 7 - LFO Trigger Enable/Disable (0/1) 1Bit/W
206 |
207 | // 8-Bit I/O Port (Mapped To Segment $FF:XXXX)
208 | constant JOYIO($1000) // JOYIO - Joypad I/O Port Register 1B/R
209 | constant TRG1($01) // JOYIO: Bit 0 - Joypad Trigger 1 1Bit/R
210 | constant TRG2($02) // JOYIO: Bit 1 - Joypad Trigger 2 1Bit/R
211 | constant SEL($04) // JOYIO: Bit 2 - Joypad Select Button 1Bit/R
212 | constant RUN($08) // JOYIO: Bit 3 - Joypad Run Button 1Bit/R
213 | constant UP($10) // JOYIO: Bit 4 - Joypad Direction Up 1Bit/R
214 | constant RIGHT($20) // JOYIO: Bit 5 - Joypad Direction Right 1Bit/R
215 | constant DOWN($40) // JOYIO: Bit 6 - Joypad Direction Down 1Bit/R
216 | constant LEFT($80) // JOYIO: Bit 7 - Joypad Direction Left 1Bit/R
217 |
218 | // PC-Engine Initialisation
219 | macro PCE_INIT() {
220 | // VDC: Set VRAM Write Address To Zero
221 | st0 #VDC_MAWR // VDC: Set VDC Address To Memory Address Write Register (VRAM Write Address) (MAWR)
222 | st1 #0 // VDC: Data = 0 (Lo Byte)
223 | st2 #0 // VDC: Data = 0 (Hi Byte)
224 |
225 | // VDC: Clear 65536 VRAM Bytes To Zero
226 | st0 #VDC_VWR // VDC: Set VDC Address To VRAM Data Write Register (VWR)
227 | ldx #0
228 | ldy #128
229 | -
230 | st1 #0 // VDC: Data = 0 (Lo Byte)
231 | st2 #0 // VDC: Data = 0 (Hi Byte)
232 | dex
233 | bne -
234 | dey
235 | bne -
236 | }
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/PSG/PlaySample/LIB/PCE_VECTOR.ASM:
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1 | //==================
2 | // PC-Engine VECTOR
3 | //==================
4 | seek($FFF6)
5 | // VECTOR (HuC6280 Mode)
6 | dw $0000 // IRQ2 VECTOR (BRK)
7 | dw $0000 // IRQ1 VECTOR (VDC)
8 | dw $0000 // TIMER VECTOR
9 | dw $0000 // NMI VECTOR
10 | dw Start // RESET VECTOR
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/PSG/PlaySample/PlaySample.asm:
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1 | // PC-Engine Play Sample Demo by krom (Peter Lemon):
2 | arch pce.cpu
3 | output "PlaySample.pce", create
4 |
5 | macro seek(variable offset) {
6 | origin (offset - $E000)
7 | base offset
8 | }
9 |
10 | // PRG BANK 0 (8KB)
11 | seek($E000); fill $2000 // Fill Bank 0 With Zero Bytes
12 | include "LIB/PCE.INC" // Include PC-Engine Definitions
13 | include "LIB/PCE_VECTOR.ASM" // Include Vector Table
14 |
15 | seek($E000); Start:
16 | PCE_INIT() // Run PC-Engine Initialisation Routine
17 |
18 | lda #$FF // A = $FF (Segment To Access I/O Ports)
19 | tam #MPR6 // MPR6 = A
20 |
21 | // PSG: Write Sample Data To Channel 0 Waveform RAM
22 | tin Sample,(6<<13)+PSG_R6,32 // MPR6:PSG_R6 = SOURCE ($FF:0806)
23 |
24 | // PSG: Reset LFO Trigger
25 | lda #PSG_LFO // A = $80 (LFO Trigger Disable)
26 | sta (6<<13)+PSG_R9 // MPR6:PSG_R9 = $80 ($FF:0809)
27 |
28 | // PSG: Set Global Sound Balance (Overall Sound Volume For Mixed Channels)
29 | lda #$FF // A = $FF (Left/Right 100% Volume)
30 | sta (6<<13)+PSG_R1 // MPR6:PSG_R1 = $FF ($FF:0801)
31 |
32 | // PSG: Set Channel 0 Balance (Volume Balance Of An Individual Channel)
33 | lda #$FF // A = $FF (Left/Right 100% Volume)
34 | sta (6<<13)+PSG_R5 // MPR6:PSG_R5 = $FF ($FF:0805)
35 |
36 | // PSG: Set 12-Bit Waveform Frequency For Channel 0
37 | lda #$FE // A = $FE (440 Hz)
38 | sta (6<<13)+PSG_R2 // MPR6:PSG_R2 = $FE ($FF:0802) (Lo Byte)
39 | lda #$00 // A = $00
40 | sta (6<<13)+PSG_R3 // MPR6:PSG_R3 = $04 ($FF:0803) (Hi Byte)
41 |
42 | // PSG: Set Channel 0 Volume & Enable Output
43 | lda #PSG_CHAN+$F // A = $8F (Enable Channel, 100% Volume)
44 | sta (6<<13)+PSG_R4 // MPR6:PSG_R4 = $8F ($FF:0804)
45 |
46 | Loop:
47 | bra Loop
48 |
49 | Sample: // 5-Bit Unsigned Linear Sample Data (32 Bytes)
50 | // db $0F, $12, $15, $17, $19, $1B, $1D, $1E // Sine Wave
51 | // db $1E, $1E, $1D, $1B, $19, $17, $15, $12
52 | // db $0F, $0C, $09, $07, $05, $03, $01, $00
53 | // db $00, $00, $01, $03, $05, $07, $09, $0C
54 |
55 | db $1F, $1F, $1F, $1F, $1F, $1F, $1F, $1F // Square Wave
56 | db $1F, $1F, $1F, $1F, $1F, $1F, $1F, $1F
57 | db $00, $00, $00, $00, $00, $00, $00, $00
58 | db $00, $00, $00, $00, $00, $00, $00, $00
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/PSG/PlaySample/PlaySample.pce:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/PeterLemon/PCE/3fcf708899ce67f166a667f9bc2da0f18d54a743/PSG/PlaySample/PlaySample.pce
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/PSG/PlaySample/make.bat:
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1 | bass PlaySample.asm
2 |
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/README.md:
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1 | PCE
2 | ===
3 |
4 | PC-Engine Assembly Code by krom (Peter Lemon).
5 |
6 | All code compiles out of box with the bass assembler by byuu.
7 | I use a special version of bass by ARM9 which has been updated with PCE HuC6280 output:
8 | https://github.com/ARM9/bass
9 | I have included binaries of all the demos.
10 |
11 | I used the PCEDEV wiki to help get me started: http://www.archaicpixels.com
12 |
13 | Howto Compile:
14 | All the code compiles into a single binary (ROMNAME.pce) file.
15 | Using bass Run: make.bat
16 |
17 | Howto Run:
18 | I only test with a real PC-Engine using a flash cartridge.
19 |
20 | You can also use PC-Engine emulators like MAME PCE Driver.
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/VDC/GreenSpace/GreenSpace.asm:
--------------------------------------------------------------------------------
1 | // PC-Engine Green Space Demo by krom (Peter Lemon):
2 | arch pce.cpu
3 | output "GreenSpace.pce", create
4 |
5 | macro seek(variable offset) {
6 | origin (offset - $E000)
7 | base offset
8 | }
9 |
10 | // PRG BANK 0 (8KB)
11 | seek($E000); fill $2000 // Fill Bank 0 With Zero Bytes
12 | include "LIB/PCE.INC" // Include PC-Engine Definitions
13 | include "LIB/PCE_VECTOR.ASM" // Include Vector Table
14 |
15 | seek($E000); Start:
16 | PCE_INIT() // Run PC-Engine Initialisation Routine
17 |
18 | lda #$FF // A = $FF (Segment To Access I/O Ports)
19 | tam #MPR6 // MPR6 = A
20 |
21 | // VCE: Set Color Table Address (CTA) To Zero
22 | stz (6<<13)+VCE_CTA // MPR6:VCE_CTA = 0 ($FF:0402) (Lo Byte)
23 | stz (6<<13)+VCE_CTA+1 // MPR6:VCE_CTA+1 = 0 ($FF:0403) (Hi Byte)
24 |
25 | // VCE: Set Color Table (CTRW) Index 0 To Green (9-Bit GRB333)
26 | lda #%11000000 // A = %11000000
27 | sta (6<<13)+VCE_CTRW // MPR6:VCE_CTRW = A ($FF:0404) (Lo Byte)
28 | lda #%00000001 // A = %00000001
29 | sta (6<<13)+VCE_CTRW+1 // MPR6:VCE_CTRW+1 = A ($FF:0405) (Hi Byte)
30 |
31 | // VDC: Turn On BG Screen
32 | st0 #VDC_CR // VDC: Set VDC Address To Control Register (CR)
33 | st1 #VDC_BB // VDC: Data = BB Flag (Background Enable/Disable) (Lo Byte)
34 | st2 #0 // VDC: Data = 0 (Hi Byte)
35 |
36 | Loop:
37 | bra Loop
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/VDC/GreenSpace/GreenSpace.pce:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/PeterLemon/PCE/3fcf708899ce67f166a667f9bc2da0f18d54a743/VDC/GreenSpace/GreenSpace.pce
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/VDC/GreenSpace/GreenSpace.png:
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https://raw.githubusercontent.com/PeterLemon/PCE/3fcf708899ce67f166a667f9bc2da0f18d54a743/VDC/GreenSpace/GreenSpace.png
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/VDC/GreenSpace/LIB/PCE.INC:
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1 | //=================== (Key: R=Read, W=Write)
2 | // PC-Engine Include
3 | //===================
4 | // Memory Map
5 | // Physical Address | Segment : Address
6 | // $000000..$0FFFFF | $00:0000..$7F:1FFF - HuCard/TurboChip ROM 1MB/R
7 | // $1F0000..$1F7FFF | $F8:0000..$FB:1FFF - Work RAM (8KB, Mirrored Four Times) 32KB/RW
8 | // $1FE000..$1FE3FF | $FF:0000..$FF:03FF - VDC Registers (HuC6270) 1KB/RW
9 | // $1FE400..$1FE7FF | $FF:0400..$FF:07FF - VCE Registers (HuC6260) 1KB/RW
10 | // $1FE800..$1FEBFF | $FF:0800..$FF:0BFF - PSG Registers 1KB/RW
11 | // $1FF000..$1FF3FF | $FF:1000..$FF:13FF - 8-Bit I/O Port 1KB/RW
12 | // $1FF400..$1FF7FF | $FF:1400..$FF:17FF - Interrupt Controller 1KB/RW
13 |
14 | // Segment Registers (Use TMA/TAM To Read/Write Segment Registers, Can Write To Multiple Registers At Once)
15 | constant MPR0($01) // MPR0 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
16 | constant MPR1($02) // MPR1 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
17 | constant MPR2($04) // MPR2 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
18 | constant MPR3($08) // MPR3 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
19 | constant MPR4($10) // MPR4 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
20 | constant MPR5($20) // MPR5 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
21 | constant MPR6($40) // MPR6 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
22 | constant MPR7($80) // MPR7 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
23 |
24 | // VDC Registers (HuC6270) (Mapped To Segment $FF:XXXX)
25 | constant VDC_STATUS($0000) // VDC Status Register 2B/R
26 | constant VDC_CR_FLAG($01) // VDC Status Read: Bit 0 - CR Flag (Set On Sprite #0 Collision) 1Bit/R
27 | constant VDC_OR_FLAG($02) // VDC Status Read: Bit 1 - OR Flag (Set On Sprite Overflow) 1Bit/R
28 | constant VDC_PR_FLAG($04) // VDC Status Read: Bit 2 - PR Flag (Set On Scanline Interrupt) 1Bit/R
29 | constant VDC_DS_FLAG($08) // VDC Status Read: Bit 3 - DS Flag (Set On VRAM -> SATB Transfer Complete) 1Bit/R
30 | constant VDC_DV_FLAG($10) // VDC Status Read: Bit 4 - DV Flag (Set On VRAM DMA Transfer Complete) 1Bit/R
31 | constant VDC_VD_FLAG($20) // VDC Status Read: Bit 5 - VD Flag (Set On Vertical Blank) 1Bit/R
32 | constant VDC_BSY_FLAG($40) // VDC Status Read: Bit 6 - BSY Flag (Set On VRAM DMA Transfer Busy) 1Bit/R
33 | // VDC Status Read: Bit 7..15 - Unused 9Bit/R
34 |
35 | constant VDC_ADDR($0000) // VDC Address Register: ST0 Opcode Can Store Immediate Value Here 2B/W
36 | // VDC Address Write: Bit 0..4 - VDC Register Address Access 5Bit/W
37 | // VDC Address Write: Bit 5..15 - Unused 11Bit/W
38 |
39 | constant VDC_DATAL($0002) // VDC Data LSB Register: ST1 Opcode Can Store Immediate Value Here 1B/RW
40 | constant VDC_DATAH($0003) // VDC Data MSB Register: ST2 Opcode Can Store Immediate Value Here 1B/RW
41 |
42 | // VDC Memory Map (Read/Write 2 Byte VDC Data To These Register Addresses)
43 | // VDC VRAM Registers
44 | constant VDC_MAWR($00) // VDC MAWR - Memory Address Write Register (VRAM Write Address) 2B/RW
45 | constant VDC_MARR($01) // VDC MARR - Memory Address Read Register (VRAM Read Address) 2B/RW
46 | constant VDC_VWR($02) // VDC VWR - VRAM Data Write Register 2B/RW
47 | constant VDC_VRR($02) // VDC VRR - VRAM Data Read Register 2B/RW
48 |
49 | constant VDC_CR($05) // VDC CR - Control Register 2B/RW
50 | // VDC L CR Read: Bit 0 - CR Flag (Set On Sprite #0 Collision) 1Bit/R
51 | // VDC L CR Read: Bit 1 - OR Flag (Set On Sprite Overflow) 1Bit/R
52 | // VDC L CR Read: Bit 2 - PR Flag (Set On Scanline Interrupt) 1Bit/R
53 | // VDC L CR Read: Bit 3 - VD Flag (Set On Vertical Blank) 1Bit/R
54 | // VDC L CR Read: Bit 4..15 - Unused 12Bit/R
55 |
56 | constant VDC_IE0($01) // VDC L CR Write: Bit 0 - IE Flag 0 (Interrupt Enable/Disable) 1Bit/W
57 | constant VDC_IE1($02) // VDC L CR Write: Bit 1 - IE Flag 1 (Interrupt Enable/Disable) 1Bit/W
58 | constant VDC_IE2($04) // VDC L CR Write: Bit 2 - IE Flag 2 (Interrupt Enable/Disable) 1Bit/W
59 | constant VDC_IE3($08) // VDC L CR Write: Bit 3 - IE Flag 3 (Interrupt Enable/Disable) 1Bit/W
60 | constant VDC_EXH($10) // VDC L CR Write: Bit 4 - EX Horizontal Sync (Signal Input/Output) 1Bit/W
61 | constant VDC_EXV($20) // VDC L CR Write: Bit 5 - EX Vertical Sync (Signal Input/Output) 1Bit/W
62 | constant VDC_SB($40) // VDC L CR Write: Bit 6 - SB Flag (Sprites Enable/Disable) 1Bit/W
63 | constant VDC_BB($80) // VDC L CR Write: Bit 7 - BB Flag (Background Enable/Disable) 1Bit/W
64 | constant VDC_DISP($00) // VDC H CR Write: Bit 8..9 - DR Selects DISP Terminal Output (%00) 2Bit/W
65 | constant VDC_BURST($01) // VDC H CR Write: Bit 8..9 - DR Selects BURST Terminal Output (%01) 2Bit/W
66 | constant VDC_INTHSYNC($02) // VDC H CR Write: Bit 8..9 - DR Selects INTHSYNC Terminal Output (%10) 2Bit/W
67 | // VDC H CR Write: Bit 8..9 - DR Selects Unused Terminal Output (%11) 2Bit/W
68 | constant VDC_DR($04) // VDC H CR Write: Bit 10 - DR Flag (Dynamic RAM Refresh Enable/Disable) 1Bit/W
69 | constant VDC_INC01($00) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $01 (%00) 2Bit/W
70 | constant VDC_INC20($08) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $20 (%01) 2Bit/W
71 | constant VDC_INC40($10) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $40 (%10) 2Bit/W
72 | constant VDC_INC80($18) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $80 (%11) 2Bit/W
73 | // VDC H CR Write: Bit 13..15 - Unused 3Bit/W
74 |
75 | constant VDC_RCR($06) // VDC RCR - Raster Counter Register 2B/RW
76 |
77 | constant VDC_BXR($07) // VDC BXR - Background X-Scroll Register 2B/RW
78 | // VDC BXR: Bit 0..9 - Screen X-Offset (In Pixels) 10Bit/RW
79 | // VDC BXR: Bit 10..15 - Unused 6Bit/RW
80 |
81 | constant VDC_BYR($08) // VDC BYR - Background Y-Scroll Register 2B/RW
82 | // VDC BYR: Bit 0..8 - Screen Y-Offset (In Pixels) 9Bit/RW
83 | // VDC BYR: Bit 9..15 - Unused 7Bit/RW
84 |
85 | constant VDC_MWR($09) // VDC MWR - Memory Width Register 2B/RW
86 | constant VDC_VW0($00) // VDC MWR: Bit 0..1 - VRAM Pixel Width 0 (%00) 2Bit/RW
87 | constant VDC_VW1($01) // VDC MWR: Bit 0..1 - VRAM Pixel Width 1 (%01) 2Bit/RW
88 | constant VDC_VW2($02) // VDC MWR: Bit 0..1 - VRAM Pixel Width 2 (%10) 2Bit/RW
89 | constant VDC_VW3($03) // VDC MWR: Bit 0..1 - VRAM Pixel Width 3 (%11) 2Bit/RW
90 | constant VDC_SW0($00) // VDC MWR: Bit 2..3 - Sprite Pixel Width 0 (%00) 2Bit/RW
91 | constant VDC_SW1($04) // VDC MWR: Bit 2..3 - Sprite Pixel Width 1 (%01) 2Bit/RW
92 | constant VDC_SW2($08) // VDC MWR: Bit 2..3 - Sprite Pixel Width 2 (%10) 2Bit/RW
93 | constant VDC_SW3($0C) // VDC MWR: Bit 2..3 - Sprite Pixel Width 3 (%11) 2Bit/RW
94 | constant VDC_SCRW32($00) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 32 (256 Pixels) (%00) 2Bit/RW
95 | constant VDC_SCRW64($10) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 64 (512 Pixels) (%01) 2Bit/RW
96 | constant VDC_SCRW128($20) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 128 (1024 Pixels) (%10) 2Bit/RW
97 | constant VDC_SCRW128B($30) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 128 (1024 Pixels) (%11) 2Bit/RW
98 | constant VDC_SCRH32($00) // VDC MWR: Bit 6 - Virtual Screen Tile Height 32 (256 Pixels) (%0) 1Bit/RW
99 | constant VDC_SCRH64($40) // VDC MWR: Bit 6 - Virtual Screen Tile Height 64 (512 Pixels) (%1) 1Bit/RW
100 | constant VDC_CM($80) // VDC MWR: Bit 7 - CM (Color Mode) 1Bit/RW
101 | // VDC MWR: Bit 8..15 - Unused 8Bit/RW
102 |
103 | // VDC Display Registers
104 | constant VDC_HSR($0A) // VDC HSR - Horizontal Synchronous Register 2B/RW
105 | constant VDC_HSW($1F) // VDC L HSR: Bit 0..4 - HSW (Horizontal Synchronous Pulse Width) 5Bit/RW
106 | // VDC L HSR: Bit 5..7 - Unused 3Bit/RW
107 | constant VDC_HDS($7F) // VDC H HSR: Bit 8..14 - HDS (Horizontal Display Starting Position) 7Bit/RW
108 | // VDC H HSR: Bit 15 - Unused 1Bit/RW
109 |
110 | constant VDC_HDR($0B) // VDC HDR - Horizontal Display Register 2B/RW
111 | constant VDC_HDW($7F) // VDC L HDR: Bit 0..6 - HDW (Horizontal Display Width) 7Bit/RW
112 | // VDC L HDR: Bit 7 - Unused 1Bit/RW
113 | constant VDC_HDE($7F) // VDC H HDR: Bit 8..14 - HDE (Horizontal Display End) 7Bit/RW
114 | // VDC H HDR: Bit 15 - Unused 1Bit/RW
115 |
116 | constant VDC_VSR($0C) // VDC VSR - Vertical Synchronous Register 2B/RW
117 | constant VDC_VSW($1F) // VDC L VSR: Bit 0..4 - VSW (Vertical Synchronous Pulse Width) 5Bit/RW
118 | // VDC L VSR: Bit 5..7 - Unused 3Bit/RW
119 | constant VDC_VDS($FF) // VDC H VSR: Bit 8..15 - VDS (Vertical Display Starting Position) 8Bit/RW
120 |
121 | constant VDC_VDR($0D) // VDC VDR - Vertical Display Register 2B/RW
122 | constant VDC_VCR($0E) // VDC VCR - Vertical Display Ending Postition Register 2B/RW
123 |
124 | // VDC DMA Registers
125 | constant VDC_DCR($0F) // VDC DCR - DMA Control Register 2B/RW
126 | constant VDC_DSC($01) // VDC DCR: Bit 0 - DSC VRAM & Sprite Attribute Table (Interrupt Enable/Disable) 1Bit/RW
127 | constant VDC_DVC($02) // VDC DCR: Bit 1 - DVC VRAM To VRAM Transfer (Interrupt Enable/Disable) 1Bit/RW
128 | constant VDC_SID($04) // VDC DCR: Bit 2 - SID VRAM To VRAM Source Increment/Decrement (1/0) 1Bit/RW
129 | constant VDC_DID($08) // VDC DCR: Bit 3 - DID VRAM To VRAM Destination Increment/Decrement (1/0) 1Bit/RW
130 | // VDC DCR: Bit 4 - Unused 1Bit/RW
131 | constant VDC_DSR($20) // VDC DCR: Bit 5 - DSR VRAM & Sprite Attribute Table Repetition (Enable/Disable) 1Bit/RW
132 | // VDC DCR: Bit 6..15 - Unused 10Bit/RW
133 |
134 | constant VDC_SOUR($10) // VDC SOUR - Source Address Register 2B/RW
135 | constant VDC_DESR($11) // VDC DESR - DMA Destination Address Register 2B/RW
136 | constant VDC_LENR($12) // VDC LENR - DMA Block Length Register 2B/RW
137 | constant VDC_SATB($13) // VDC SATB - Sprite Attribute Table Address Register 2B/RW
138 |
139 | // VCE Registers (HuC6260) (Mapped To Segment $FF:XXXX)
140 | constant VCE_CR($0400) // VCE CR - Control Register 2B/W
141 | constant VCE_PCC0($00) // VCE CR: Bit 0..1 - PCC 5.3693175 MHz (Pixel Clock Control) (%00) 2Bit/W
142 | constant VCE_PCC1($01) // VCE CR: Bit 0..1 - PCC 7.15909 MHz (Pixel Clock Control) (%01) 2Bit/W
143 | constant VCE_PCC2($02) // VCE CR: Bit 0..1 - PCC 10.738635 MHz (Pixel Clock Control) (%10) 2Bit/W
144 | constant VCE_PCC3($03) // VCE CR: Bit 0..1 - PCC 10.738635 MHz (Pixel Clock Control) (%11) 2Bit/W
145 | constant VCE_FC0($00) // VCE CR: Bit 2 - FC 262 Line Frame (Frame/Field Configuration) (%0) 1Bit/W
146 | constant VCE_FC1($04) // VCE CR: Bit 2 - FC 263 Line Frame (Frame/Field Configuration) (%1) 1Bit/W
147 | // VCE CR: Bit 3..6 - Unused 4Bit/W
148 | constant VCE_SC0($00) // VCE CR: Bit 7 - SC Colorburst Intact (Strip Colorburst) (%0) 1Bit/W
149 | constant VCE_SC1($08) // VCE CR: Bit 7 - SC Strip Colorburst (Strip Colorburst) (%1) 1Bit/W
150 | // VCE CR: Bit 8..15 - Unused 8Bit/W
151 |
152 | constant VCE_CTA($0402) // VCE CTA - Color Table Address Register 2B/W
153 | // VCE CTA: Bit 0..8 - Color Table Index (0..511) 9Bit/W
154 | // VCE CTA: Bit 9..15 - Unused 7Bit/W
155 |
156 | constant VCE_CTRW($0404) // VCE CTRW - Color Table Read/Write Register (BRG333) 2B/RW
157 | // VCE CTRW: Bit 0..2 - Blue 3Bit/RW
158 | // VCE CTRW: Bit 3..5 - Red 3Bit/RW
159 | // VCE CTRW: Bit 6..8 - Green 3Bit/RW
160 | // VCE CTRW: Bit 9..15 - Unused 7Bit/RW
161 |
162 | // PSG Registers (Mapped To Segment $FF:XXXX) (Write Only)
163 | constant PSG_R0($0800) // PSG Register 0 - Channel Select (Selects Channel For Use With PSG Registers R2..R9) 1B/W
164 | // PSG Register 0: Bit 0..2 - Channel Number (Only 0..5 Valid) 3Bit/W
165 | // PSG Register 0: Bit 3..7 - Unused 5Bit/W
166 |
167 | constant PSG_R1($0801) // PSG Register 1 - Global Sound Balance (Overall Sound Volume For Mixed Channels) 1B/W
168 | // PSG Register 1: Bit 0..3 - Volume From Right Output 4Bit/W
169 | // PSG Register 1: Bit 4..7 - Volume From Left Output 4Bit/W
170 |
171 | constant PSG_R2($0802) // PSG Register 2 - Fine Frequency Adjust (Lower 8-Bits Of 12-Bit Channel Frequency) 1B/W
172 | // PSG Register 2: Bit 0..7 - Fine Frequency Adjust 8Bit/W
173 |
174 | constant PSG_R3($0803) // PSG Register 3 - Rough Frequency Adjust (Upper 4-Bits Of 12-Bit Channel Frequency) 1B/W
175 | // PSG Register 3: Bit 0..3 - Rough Frequency Adjust 4Bit/W
176 | // PSG Register 3: Bit 4..7 - Unused 4Bit/W
177 |
178 | constant PSG_R4($0804) // PSG Register 4 - Channel Enable, DDA Enable, Channel Volume 1B/W
179 | // PSG Register 4: Bit 0..4 - Overall Channel Volume 5Bit/W
180 | // PSG Register 4: Bit 5 - Unused 1Bit/W
181 | constant PSG_DDA($40) // PSG Register 4: Bit 6 - DDA Output Enable/Disable (1/0) 1Bit/W
182 | constant PSG_CHAN($80) // PSG Register 4: Bit 7 - Channel Enable/Disable (1/0) 1Bit/W
183 |
184 | constant PSG_R5($0805) // PSG Register 5 - Channel Balance (Volume Balance Of An Individual Channel) 1B/W
185 | // PSG Register 5: Bit 0..3 - Volume To Right Output 4Bit/W
186 | // PSG Register 5: Bit 4..7 - Volume To Left Output 4Bit/W
187 |
188 | constant PSG_R6($0806) // PSG Register 6 - Channel Sound Data (5-Bit Unsigned Linear Sample Data) 1B/W
189 | // PSG Register 6: Bit 0..4 - 5-Bit Unsigned Linear Sample Data 5Bit/W
190 | // PSG Register 6: Bit 5..7 - Unused 3Bit/W
191 |
192 | constant PSG_R7($0807) // PSG Register 7 - Noise Enable, Noise Frequency (Only Effective For Channels 4 & 5) 1B/W
193 | // PSG Register 7: Bit 0..4 - Noise Frequency 5Bit/W
194 | // PSG Register 7: Bit 5..6 - Unused 2Bit/W
195 | constant PSG_NOISE($80) // PSG Register 7: Bit 7 - Noise Enable/Disable (1/0)
196 |
197 | constant PSG_R8($0808) // PSG Register 8 - LFO Frequency (Uses Channel 1 Waveform Buffer As Frequency Modulation) 1B/W
198 |
199 | constant PSG_R9($0809) // PSG Register 9 - LFO Trigger, LFO Control 1B/W
200 | constant PSG_LFO0($00) // PSG Register 9: Bit 0..1 - No Frequency Modulation Is Performed (LFO Control) %00 2Bit/W
201 | constant PSG_LFO1($01) // PSG Register 9: Bit 0..1 - FM Data Added To Channel 0 Frequency (LFO Control) %01 2Bit/W
202 | constant PSG_LFO2($02) // PSG Register 9: Bit 0..1 - FM Data << 4 Then Added To The Frequency (LFO Control) %10 2Bit/W
203 | constant PSG_LFO3($03) // PSG Register 9: Bit 0..1 - FM Data << 8 Then Added To The Frequency (LFO Control) %11 2Bit/W
204 | // PSG Register 9: Bit 2..6 - Unused 5Bit/W
205 | constant PSG_LFO($80) // PSG Register 9: Bit 7 - LFO Trigger Enable/Disable (0/1) 1Bit/W
206 |
207 | // 8-Bit I/O Port (Mapped To Segment $FF:XXXX)
208 | constant JOYIO($1000) // JOYIO - Joypad I/O Port Register 1B/R
209 | constant TRG1($01) // JOYIO: Bit 0 - Joypad Trigger 1 1Bit/R
210 | constant TRG2($02) // JOYIO: Bit 1 - Joypad Trigger 2 1Bit/R
211 | constant SEL($04) // JOYIO: Bit 2 - Joypad Select Button 1Bit/R
212 | constant RUN($08) // JOYIO: Bit 3 - Joypad Run Button 1Bit/R
213 | constant UP($10) // JOYIO: Bit 4 - Joypad Direction Up 1Bit/R
214 | constant RIGHT($20) // JOYIO: Bit 5 - Joypad Direction Right 1Bit/R
215 | constant DOWN($40) // JOYIO: Bit 6 - Joypad Direction Down 1Bit/R
216 | constant LEFT($80) // JOYIO: Bit 7 - Joypad Direction Left 1Bit/R
217 |
218 | // PC-Engine Initialisation
219 | macro PCE_INIT() {
220 | // VDC: Set VRAM Write Address To Zero
221 | st0 #VDC_MAWR // VDC: Set VDC Address To Memory Address Write Register (VRAM Write Address) (MAWR)
222 | st1 #0 // VDC: Data = 0 (Lo Byte)
223 | st2 #0 // VDC: Data = 0 (Hi Byte)
224 |
225 | // VDC: Clear 65536 VRAM Bytes To Zero
226 | st0 #VDC_VWR // VDC: Set VDC Address To VRAM Data Write Register (VWR)
227 | ldx #0
228 | ldy #128
229 | -
230 | st1 #0 // VDC: Data = 0 (Lo Byte)
231 | st2 #0 // VDC: Data = 0 (Hi Byte)
232 | dex
233 | bne -
234 | dey
235 | bne -
236 | }
--------------------------------------------------------------------------------
/VDC/GreenSpace/LIB/PCE_VECTOR.ASM:
--------------------------------------------------------------------------------
1 | //==================
2 | // PC-Engine VECTOR
3 | //==================
4 | seek($FFF6)
5 | // VECTOR (HuC6280 Mode)
6 | dw $0000 // IRQ2 VECTOR (BRK)
7 | dw $0000 // IRQ1 VECTOR (VDC)
8 | dw $0000 // TIMER VECTOR
9 | dw $0000 // NMI VECTOR
10 | dw Start // RESET VECTOR
--------------------------------------------------------------------------------
/VDC/GreenSpace/make.bat:
--------------------------------------------------------------------------------
1 | bass GreenSpace.asm
2 |
--------------------------------------------------------------------------------
/VDC/HelloWorld/Font8x8.asm:
--------------------------------------------------------------------------------
1 | // $20: Space " "
2 | db %00000000
3 | db %00000000
4 | db %00000000
5 | db %00000000
6 | db %00000000
7 | db %00000000
8 | db %00000000
9 | db %00000000
10 | db %00000000
11 | db %00000000
12 | db %00000000
13 | db %00000000
14 | db %00000000
15 | db %00000000
16 | db %00000000
17 | db %00000000
18 |
19 | db %00000000
20 | db %00000000
21 | db %00000000
22 | db %00000000
23 | db %00000000
24 | db %00000000
25 | db %00000000
26 | db %00000000
27 | db %00000000
28 | db %00000000
29 | db %00000000
30 | db %00000000
31 | db %00000000
32 | db %00000000
33 | db %00000000
34 | db %00000000
35 |
36 | // $21: Exclamation mark "!"
37 | db %00011000
38 | db %00000000
39 | db %00011000
40 | db %00000000
41 | db %00011000
42 | db %00000000
43 | db %00011000
44 | db %00000000
45 | db %00000000
46 | db %00000000
47 | db %00011000
48 | db %00000000
49 | db %00000000
50 | db %00000000
51 | db %00000000
52 | db %00000000
53 |
54 | db %00000000
55 | db %00000000
56 | db %00000000
57 | db %00000000
58 | db %00000000
59 | db %00000000
60 | db %00000000
61 | db %00000000
62 | db %00000000
63 | db %00000000
64 | db %00000000
65 | db %00000000
66 | db %00000000
67 | db %00000000
68 | db %00000000
69 | db %00000000
70 |
71 | // $22: Quotation mark """
72 | db %01100110
73 | db %00000000
74 | db %01100110
75 | db %00000000
76 | db %01000100
77 | db %00000000
78 | db %00000000
79 | db %00000000
80 | db %00000000
81 | db %00000000
82 | db %00000000
83 | db %00000000
84 | db %00000000
85 | db %00000000
86 | db %00000000
87 | db %00000000
88 |
89 | db %00000000
90 | db %00000000
91 | db %00000000
92 | db %00000000
93 | db %00000000
94 | db %00000000
95 | db %00000000
96 | db %00000000
97 | db %00000000
98 | db %00000000
99 | db %00000000
100 | db %00000000
101 | db %00000000
102 | db %00000000
103 | db %00000000
104 | db %00000000
105 |
106 | // $23: Cross hatch "#"
107 | db %00010100
108 | db %00000000
109 | db %00010100
110 | db %00000000
111 | db %01111110
112 | db %00000000
113 | db %00101000
114 | db %00000000
115 | db %01111110
116 | db %00000000
117 | db %00101000
118 | db %00000000
119 | db %00000000
120 | db %00000000
121 | db %00000000
122 | db %00000000
123 |
124 | db %00000000
125 | db %00000000
126 | db %00000000
127 | db %00000000
128 | db %00000000
129 | db %00000000
130 | db %00000000
131 | db %00000000
132 | db %00000000
133 | db %00000000
134 | db %00000000
135 | db %00000000
136 | db %00000000
137 | db %00000000
138 | db %00000000
139 | db %00000000
140 |
141 | // $24: Dollar sign "$"
142 | db %00111100
143 | db %00000000
144 | db %01101010
145 | db %00000000
146 | db %01111100
147 | db %00000000
148 | db %00111110
149 | db %00000000
150 | db %01010110
151 | db %00000000
152 | db %00111100
153 | db %00000000
154 | db %00010000
155 | db %00000000
156 | db %00000000
157 | db %00000000
158 |
159 | db %00000000
160 | db %00000000
161 | db %00000000
162 | db %00000000
163 | db %00000000
164 | db %00000000
165 | db %00000000
166 | db %00000000
167 | db %00000000
168 | db %00000000
169 | db %00000000
170 | db %00000000
171 | db %00000000
172 | db %00000000
173 | db %00000000
174 | db %00000000
175 |
176 | // $25: Percent sign "%"
177 | db %00100010
178 | db %00000000
179 | db %01010100
180 | db %00000000
181 | db %00101000
182 | db %00000000
183 | db %00010100
184 | db %00000000
185 | db %00101010
186 | db %00000000
187 | db %01000100
188 | db %00000000
189 | db %00000000
190 | db %00000000
191 | db %00000000
192 | db %00000000
193 |
194 | db %00000000
195 | db %00000000
196 | db %00000000
197 | db %00000000
198 | db %00000000
199 | db %00000000
200 | db %00000000
201 | db %00000000
202 | db %00000000
203 | db %00000000
204 | db %00000000
205 | db %00000000
206 | db %00000000
207 | db %00000000
208 | db %00000000
209 | db %00000000
210 |
211 | // $26: Ampersand "&"
212 | db %00110000
213 | db %00000000
214 | db %01001000
215 | db %00000000
216 | db %00110010
217 | db %00000000
218 | db %01001100
219 | db %00000000
220 | db %01001100
221 | db %00000000
222 | db %00110010
223 | db %00000000
224 | db %00000000
225 | db %00000000
226 | db %00000000
227 | db %00000000
228 |
229 | db %00000000
230 | db %00000000
231 | db %00000000
232 | db %00000000
233 | db %00000000
234 | db %00000000
235 | db %00000000
236 | db %00000000
237 | db %00000000
238 | db %00000000
239 | db %00000000
240 | db %00000000
241 | db %00000000
242 | db %00000000
243 | db %00000000
244 | db %00000000
245 |
246 | // $27: Closing single quote "'"
247 | db %00011000
248 | db %00000000
249 | db %00011000
250 | db %00000000
251 | db %00010000
252 | db %00000000
253 | db %00000000
254 | db %00000000
255 | db %00000000
256 | db %00000000
257 | db %00000000
258 | db %00000000
259 | db %00000000
260 | db %00000000
261 | db %00000000
262 | db %00000000
263 |
264 | db %00000000
265 | db %00000000
266 | db %00000000
267 | db %00000000
268 | db %00000000
269 | db %00000000
270 | db %00000000
271 | db %00000000
272 | db %00000000
273 | db %00000000
274 | db %00000000
275 | db %00000000
276 | db %00000000
277 | db %00000000
278 | db %00000000
279 | db %00000000
280 |
281 | // $28: Opening parentheses "("
282 | db %00001100
283 | db %00000000
284 | db %00011000
285 | db %00000000
286 | db %00110000
287 | db %00000000
288 | db %00110000
289 | db %00000000
290 | db %00110000
291 | db %00000000
292 | db %00110000
293 | db %00000000
294 | db %00011000
295 | db %00000000
296 | db %00001100
297 | db %00000000
298 |
299 | db %00000000
300 | db %00000000
301 | db %00000000
302 | db %00000000
303 | db %00000000
304 | db %00000000
305 | db %00000000
306 | db %00000000
307 | db %00000000
308 | db %00000000
309 | db %00000000
310 | db %00000000
311 | db %00000000
312 | db %00000000
313 | db %00000000
314 | db %00000000
315 |
316 | // $29: Closing parentheses ")"
317 | db %00110000
318 | db %00000000
319 | db %00011000
320 | db %00000000
321 | db %00001100
322 | db %00000000
323 | db %00001100
324 | db %00000000
325 | db %00001100
326 | db %00000000
327 | db %00001100
328 | db %00000000
329 | db %00011000
330 | db %00000000
331 | db %00110000
332 | db %00000000
333 |
334 | db %00000000
335 | db %00000000
336 | db %00000000
337 | db %00000000
338 | db %00000000
339 | db %00000000
340 | db %00000000
341 | db %00000000
342 | db %00000000
343 | db %00000000
344 | db %00000000
345 | db %00000000
346 | db %00000000
347 | db %00000000
348 | db %00000000
349 | db %00000000
350 |
351 | // $2A: Asterisk "*"
352 | db %00011000
353 | db %00000000
354 | db %01111110
355 | db %00000000
356 | db %00011000
357 | db %00000000
358 | db %00100100
359 | db %00000000
360 | db %00000000
361 | db %00000000
362 | db %00000000
363 | db %00000000
364 | db %00000000
365 | db %00000000
366 | db %00000000
367 | db %00000000
368 |
369 | db %00000000
370 | db %00000000
371 | db %00000000
372 | db %00000000
373 | db %00000000
374 | db %00000000
375 | db %00000000
376 | db %00000000
377 | db %00000000
378 | db %00000000
379 | db %00000000
380 | db %00000000
381 | db %00000000
382 | db %00000000
383 | db %00000000
384 | db %00000000
385 |
386 | // $2B: Plus "+"
387 | db %00000000
388 | db %00000000
389 | db %00011000
390 | db %00000000
391 | db %00011000
392 | db %00000000
393 | db %01111110
394 | db %00000000
395 | db %00011000
396 | db %00000000
397 | db %00011000
398 | db %00000000
399 | db %00000000
400 | db %00000000
401 | db %00000000
402 | db %00000000
403 |
404 | db %00000000
405 | db %00000000
406 | db %00000000
407 | db %00000000
408 | db %00000000
409 | db %00000000
410 | db %00000000
411 | db %00000000
412 | db %00000000
413 | db %00000000
414 | db %00000000
415 | db %00000000
416 | db %00000000
417 | db %00000000
418 | db %00000000
419 | db %00000000
420 |
421 | // $2C: Comma ","
422 | db %00000000
423 | db %00000000
424 | db %00000000
425 | db %00000000
426 | db %00000000
427 | db %00000000
428 | db %00000000
429 | db %00000000
430 | db %00011000
431 | db %00000000
432 | db %00011000
433 | db %00000000
434 | db %00010000
435 | db %00000000
436 | db %00000000
437 | db %00000000
438 |
439 | db %00000000
440 | db %00000000
441 | db %00000000
442 | db %00000000
443 | db %00000000
444 | db %00000000
445 | db %00000000
446 | db %00000000
447 | db %00000000
448 | db %00000000
449 | db %00000000
450 | db %00000000
451 | db %00000000
452 | db %00000000
453 | db %00000000
454 | db %00000000
455 |
456 | // $2D: Hyphen "-"
457 | db %00000000
458 | db %00000000
459 | db %00000000
460 | db %00000000
461 | db %00000000
462 | db %00000000
463 | db %00111100
464 | db %00000000
465 | db %00000000
466 | db %00000000
467 | db %00000000
468 | db %00000000
469 | db %00000000
470 | db %00000000
471 | db %00000000
472 | db %00000000
473 |
474 | db %00000000
475 | db %00000000
476 | db %00000000
477 | db %00000000
478 | db %00000000
479 | db %00000000
480 | db %00000000
481 | db %00000000
482 | db %00000000
483 | db %00000000
484 | db %00000000
485 | db %00000000
486 | db %00000000
487 | db %00000000
488 | db %00000000
489 | db %00000000
490 |
491 | // $2E: Period "."
492 | db %00000000
493 | db %00000000
494 | db %00000000
495 | db %00000000
496 | db %00000000
497 | db %00000000
498 | db %00000000
499 | db %00000000
500 | db %00011000
501 | db %00000000
502 | db %00011000
503 | db %00000000
504 | db %00000000
505 | db %00000000
506 | db %00000000
507 | db %00000000
508 |
509 | db %00000000
510 | db %00000000
511 | db %00000000
512 | db %00000000
513 | db %00000000
514 | db %00000000
515 | db %00000000
516 | db %00000000
517 | db %00000000
518 | db %00000000
519 | db %00000000
520 | db %00000000
521 | db %00000000
522 | db %00000000
523 | db %00000000
524 | db %00000000
525 |
526 | // $2F: Forward slash "/"
527 | db %00000010
528 | db %00000000
529 | db %00000110
530 | db %00000000
531 | db %00001100
532 | db %00000000
533 | db %00011000
534 | db %00000000
535 | db %00110000
536 | db %00000000
537 | db %01100000
538 | db %00000000
539 | db %01000000
540 | db %00000000
541 | db %00000000
542 | db %00000000
543 |
544 | db %00000000
545 | db %00000000
546 | db %00000000
547 | db %00000000
548 | db %00000000
549 | db %00000000
550 | db %00000000
551 | db %00000000
552 | db %00000000
553 | db %00000000
554 | db %00000000
555 | db %00000000
556 | db %00000000
557 | db %00000000
558 | db %00000000
559 | db %00000000
560 |
561 | //////////////////////////////////////////
562 | // $30: 0
563 | db %00111010
564 | db %00000000
565 | db %01100100
566 | db %00000000
567 | db %01001010
568 | db %00000000
569 | db %01010010
570 | db %00000000
571 | db %00100110
572 | db %00000000
573 | db %01011100
574 | db %00000000
575 | db %00000000
576 | db %00000000
577 | db %00000000
578 | db %00000000
579 |
580 | db %00000000
581 | db %00000000
582 | db %00000000
583 | db %00000000
584 | db %00000000
585 | db %00000000
586 | db %00000000
587 | db %00000000
588 | db %00000000
589 | db %00000000
590 | db %00000000
591 | db %00000000
592 | db %00000000
593 | db %00000000
594 | db %00000000
595 | db %00000000
596 |
597 | // $31: 1
598 | db %00011000
599 | db %00000000
600 | db %00111000
601 | db %00000000
602 | db %00011000
603 | db %00000000
604 | db %00011000
605 | db %00000000
606 | db %00011000
607 | db %00000000
608 | db %00111100
609 | db %00000000
610 | db %00000000
611 | db %00000000
612 | db %00000000
613 | db %00000000
614 |
615 | db %00000000
616 | db %00000000
617 | db %00000000
618 | db %00000000
619 | db %00000000
620 | db %00000000
621 | db %00000000
622 | db %00000000
623 | db %00000000
624 | db %00000000
625 | db %00000000
626 | db %00000000
627 | db %00000000
628 | db %00000000
629 | db %00000000
630 | db %00000000
631 |
632 | // $32: 2
633 | db %00111000
634 | db %00000000
635 | db %01001100
636 | db %00000000
637 | db %00001100
638 | db %00000000
639 | db %00011000
640 | db %00000000
641 | db %00110000
642 | db %00000000
643 | db %01111110
644 | db %00000000
645 | db %00000000
646 | db %00000000
647 | db %00000000
648 | db %00000000
649 |
650 | db %00000000
651 | db %00000000
652 | db %00000000
653 | db %00000000
654 | db %00000000
655 | db %00000000
656 | db %00000000
657 | db %00000000
658 | db %00000000
659 | db %00000000
660 | db %00000000
661 | db %00000000
662 | db %00000000
663 | db %00000000
664 | db %00000000
665 | db %00000000
666 |
667 | // $33: 3
668 | db %00111100
669 | db %00000000
670 | db %01000110
671 | db %00000000
672 | db %00011100
673 | db %00000000
674 | db %00000110
675 | db %00000000
676 | db %01000110
677 | db %00000000
678 | db %00111100
679 | db %00000000
680 | db %00000000
681 | db %00000000
682 | db %00000000
683 | db %00000000
684 |
685 | db %00000000
686 | db %00000000
687 | db %00000000
688 | db %00000000
689 | db %00000000
690 | db %00000000
691 | db %00000000
692 | db %00000000
693 | db %00000000
694 | db %00000000
695 | db %00000000
696 | db %00000000
697 | db %00000000
698 | db %00000000
699 | db %00000000
700 | db %00000000
701 |
702 | // $34: 4
703 | db %00001100
704 | db %00000000
705 | db %00011100
706 | db %00000000
707 | db %00101100
708 | db %00000000
709 | db %01001100
710 | db %00000000
711 | db %01111110
712 | db %00000000
713 | db %00001100
714 | db %00000000
715 | db %00000000
716 | db %00000000
717 | db %00000000
718 | db %00000000
719 |
720 | db %00000000
721 | db %00000000
722 | db %00000000
723 | db %00000000
724 | db %00000000
725 | db %00000000
726 | db %00000000
727 | db %00000000
728 | db %00000000
729 | db %00000000
730 | db %00000000
731 | db %00000000
732 | db %00000000
733 | db %00000000
734 | db %00000000
735 | db %00000000
736 |
737 | // $35: 5
738 | db %01111110
739 | db %00000000
740 | db %01100000
741 | db %00000000
742 | db %01111100
743 | db %00000000
744 | db %00000110
745 | db %00000000
746 | db %01000110
747 | db %00000000
748 | db %00111100
749 | db %00000000
750 | db %00000000
751 | db %00000000
752 | db %00000000
753 | db %00000000
754 |
755 | db %00000000
756 | db %00000000
757 | db %00000000
758 | db %00000000
759 | db %00000000
760 | db %00000000
761 | db %00000000
762 | db %00000000
763 | db %00000000
764 | db %00000000
765 | db %00000000
766 | db %00000000
767 | db %00000000
768 | db %00000000
769 | db %00000000
770 | db %00000000
771 |
772 | // $36: 6
773 | db %00111100
774 | db %00000000
775 | db %01100000
776 | db %00000000
777 | db %01111100
778 | db %00000000
779 | db %01100110
780 | db %00000000
781 | db %01100110
782 | db %00000000
783 | db %00111100
784 | db %00000000
785 | db %00000000
786 | db %00000000
787 | db %00000000
788 | db %00000000
789 |
790 | db %00000000
791 | db %00000000
792 | db %00000000
793 | db %00000000
794 | db %00000000
795 | db %00000000
796 | db %00000000
797 | db %00000000
798 | db %00000000
799 | db %00000000
800 | db %00000000
801 | db %00000000
802 | db %00000000
803 | db %00000000
804 | db %00000000
805 | db %00000000
806 |
807 | // $37: 7
808 | db %01111110
809 | db %00000000
810 | db %01100110
811 | db %00000000
812 | db %00001100
813 | db %00000000
814 | db %00111110
815 | db %00000000
816 | db %00011000
817 | db %00000000
818 | db %00011000
819 | db %00000000
820 | db %00000000
821 | db %00000000
822 | db %00000000
823 | db %00000000
824 |
825 | db %00000000
826 | db %00000000
827 | db %00000000
828 | db %00000000
829 | db %00000000
830 | db %00000000
831 | db %00000000
832 | db %00000000
833 | db %00000000
834 | db %00000000
835 | db %00000000
836 | db %00000000
837 | db %00000000
838 | db %00000000
839 | db %00000000
840 | db %00000000
841 |
842 | // $38: 8
843 | db %00111100
844 | db %00000000
845 | db %01100110
846 | db %00000000
847 | db %00111100
848 | db %00000000
849 | db %01100110
850 | db %00000000
851 | db %01100110
852 | db %00000000
853 | db %00111100
854 | db %00000000
855 | db %00000000
856 | db %00000000
857 | db %00000000
858 | db %00000000
859 |
860 | db %00000000
861 | db %00000000
862 | db %00000000
863 | db %00000000
864 | db %00000000
865 | db %00000000
866 | db %00000000
867 | db %00000000
868 | db %00000000
869 | db %00000000
870 | db %00000000
871 | db %00000000
872 | db %00000000
873 | db %00000000
874 | db %00000000
875 | db %00000000
876 |
877 | // $39: 9
878 | db %00111100
879 | db %00000000
880 | db %01100110
881 | db %00000000
882 | db %01100110
883 | db %00000000
884 | db %00111110
885 | db %00000000
886 | db %00000110
887 | db %00000000
888 | db %00111100
889 | db %00000000
890 | db %00000000
891 | db %00000000
892 | db %00000000
893 | db %00000000
894 |
895 | db %00000000
896 | db %00000000
897 | db %00000000
898 | db %00000000
899 | db %00000000
900 | db %00000000
901 | db %00000000
902 | db %00000000
903 | db %00000000
904 | db %00000000
905 | db %00000000
906 | db %00000000
907 | db %00000000
908 | db %00000000
909 | db %00000000
910 | db %00000000
911 |
912 | //////////////////////////////////////////
913 | // $3A: Colon ":"
914 | db %00000000
915 | db %00000000
916 | db %00011000
917 | db %00000000
918 | db %00011000
919 | db %00000000
920 | db %00000000
921 | db %00000000
922 | db %00011000
923 | db %00000000
924 | db %00011000
925 | db %00000000
926 | db %00000000
927 | db %00000000
928 | db %00000000
929 | db %00000000
930 |
931 | db %00000000
932 | db %00000000
933 | db %00000000
934 | db %00000000
935 | db %00000000
936 | db %00000000
937 | db %00000000
938 | db %00000000
939 | db %00000000
940 | db %00000000
941 | db %00000000
942 | db %00000000
943 | db %00000000
944 | db %00000000
945 | db %00000000
946 | db %00000000
947 |
948 | // $3B: Semicolon ";"
949 | db %00000000
950 | db %00000000
951 | db %00011000
952 | db %00000000
953 | db %00011000
954 | db %00000000
955 | db %00000000
956 | db %00000000
957 | db %00011000
958 | db %00000000
959 | db %00011000
960 | db %00000000
961 | db %00010000
962 | db %00000000
963 | db %00000000
964 | db %00000000
965 |
966 | db %00000000
967 | db %00000000
968 | db %00000000
969 | db %00000000
970 | db %00000000
971 | db %00000000
972 | db %00000000
973 | db %00000000
974 | db %00000000
975 | db %00000000
976 | db %00000000
977 | db %00000000
978 | db %00000000
979 | db %00000000
980 | db %00000000
981 | db %00000000
982 |
983 | // $3C: Less than sign "<"
984 | db %00000000
985 | db %00000000
986 | db %00000110
987 | db %00000000
988 | db %00011000
989 | db %00000000
990 | db %01100000
991 | db %00000000
992 | db %00011000
993 | db %00000000
994 | db %00000110
995 | db %00000000
996 | db %00000000
997 | db %00000000
998 | db %00000000
999 | db %00000000
1000 |
1001 | db %00000000
1002 | db %00000000
1003 | db %00000000
1004 | db %00000000
1005 | db %00000000
1006 | db %00000000
1007 | db %00000000
1008 | db %00000000
1009 | db %00000000
1010 | db %00000000
1011 | db %00000000
1012 | db %00000000
1013 | db %00000000
1014 | db %00000000
1015 | db %00000000
1016 | db %00000000
1017 |
1018 | // $3D: Equals sign "="
1019 | db %00000000
1020 | db %00000000
1021 | db %00000000
1022 | db %00000000
1023 | db %01111110
1024 | db %00000000
1025 | db %00000000
1026 | db %00000000
1027 | db %01111110
1028 | db %00000000
1029 | db %00000000
1030 | db %00000000
1031 | db %00000000
1032 | db %00000000
1033 | db %00000000
1034 | db %00000000
1035 |
1036 | db %00000000
1037 | db %00000000
1038 | db %00000000
1039 | db %00000000
1040 | db %00000000
1041 | db %00000000
1042 | db %00000000
1043 | db %00000000
1044 | db %00000000
1045 | db %00000000
1046 | db %00000000
1047 | db %00000000
1048 | db %00000000
1049 | db %00000000
1050 | db %00000000
1051 | db %00000000
1052 |
1053 | // $3E: Greater than sign ">"
1054 | db %00000000
1055 | db %00000000
1056 | db %01100000
1057 | db %00000000
1058 | db %00011000
1059 | db %00000000
1060 | db %00000110
1061 | db %00000000
1062 | db %00011000
1063 | db %00000000
1064 | db %01100000
1065 | db %00000000
1066 | db %00000000
1067 | db %00000000
1068 | db %00000000
1069 | db %00000000
1070 |
1071 | db %00000000
1072 | db %00000000
1073 | db %00000000
1074 | db %00000000
1075 | db %00000000
1076 | db %00000000
1077 | db %00000000
1078 | db %00000000
1079 | db %00000000
1080 | db %00000000
1081 | db %00000000
1082 | db %00000000
1083 | db %00000000
1084 | db %00000000
1085 | db %00000000
1086 | db %00000000
1087 |
1088 | // $3F: Question mark "?"
1089 | db %00111100
1090 | db %00000000
1091 | db %01100110
1092 | db %00000000
1093 | db %01100110
1094 | db %00000000
1095 | db %00001100
1096 | db %00000000
1097 | db %00011000
1098 | db %00000000
1099 | db %00000000
1100 | db %00000000
1101 | db %00011000
1102 | db %00000000
1103 | db %00000000
1104 | db %00000000
1105 |
1106 | db %00000000
1107 | db %00000000
1108 | db %00000000
1109 | db %00000000
1110 | db %00000000
1111 | db %00000000
1112 | db %00000000
1113 | db %00000000
1114 | db %00000000
1115 | db %00000000
1116 | db %00000000
1117 | db %00000000
1118 | db %00000000
1119 | db %00000000
1120 | db %00000000
1121 | db %00000000
1122 |
1123 | // $40: At sign "@"
1124 | db %01111100
1125 | db %00000000
1126 | db %10000010
1127 | db %00000000
1128 | db %10111010
1129 | db %00000000
1130 | db %10101010
1131 | db %00000000
1132 | db %10111110
1133 | db %00000000
1134 | db %01000000
1135 | db %00000000
1136 | db %00111110
1137 | db %00000000
1138 | db %00000000
1139 | db %00000000
1140 |
1141 | db %00000000
1142 | db %00000000
1143 | db %00000000
1144 | db %00000000
1145 | db %00000000
1146 | db %00000000
1147 | db %00000000
1148 | db %00000000
1149 | db %00000000
1150 | db %00000000
1151 | db %00000000
1152 | db %00000000
1153 | db %00000000
1154 | db %00000000
1155 | db %00000000
1156 | db %00000000
1157 |
1158 | //////////////////////////////////////////
1159 | // $41: A
1160 | db %00011000
1161 | db %00000000
1162 | db %00111100
1163 | db %00000000
1164 | db %00100100
1165 | db %00000000
1166 | db %01111110
1167 | db %00000000
1168 | db %01100110
1169 | db %00000000
1170 | db %01100110
1171 | db %00000000
1172 | db %00000000
1173 | db %00000000
1174 | db %00000000
1175 | db %00000000
1176 |
1177 | db %00000000
1178 | db %00000000
1179 | db %00000000
1180 | db %00000000
1181 | db %00000000
1182 | db %00000000
1183 | db %00000000
1184 | db %00000000
1185 | db %00000000
1186 | db %00000000
1187 | db %00000000
1188 | db %00000000
1189 | db %00000000
1190 | db %00000000
1191 | db %00000000
1192 | db %00000000
1193 |
1194 | // $42: B
1195 | db %01111100
1196 | db %00000000
1197 | db %01100110
1198 | db %00000000
1199 | db %01111100
1200 | db %00000000
1201 | db %01100110
1202 | db %00000000
1203 | db %01100110
1204 | db %00000000
1205 | db %01111100
1206 | db %00000000
1207 | db %00000000
1208 | db %00000000
1209 | db %00000000
1210 | db %00000000
1211 |
1212 | db %00000000
1213 | db %00000000
1214 | db %00000000
1215 | db %00000000
1216 | db %00000000
1217 | db %00000000
1218 | db %00000000
1219 | db %00000000
1220 | db %00000000
1221 | db %00000000
1222 | db %00000000
1223 | db %00000000
1224 | db %00000000
1225 | db %00000000
1226 | db %00000000
1227 | db %00000000
1228 |
1229 | // $43: C
1230 | db %00111100
1231 | db %00000000
1232 | db %01100110
1233 | db %00000000
1234 | db %01100000
1235 | db %00000000
1236 | db %01100010
1237 | db %00000000
1238 | db %01111110
1239 | db %00000000
1240 | db %00111100
1241 | db %00000000
1242 | db %00000000
1243 | db %00000000
1244 | db %00000000
1245 | db %00000000
1246 |
1247 | db %00000000
1248 | db %00000000
1249 | db %00000000
1250 | db %00000000
1251 | db %00000000
1252 | db %00000000
1253 | db %00000000
1254 | db %00000000
1255 | db %00000000
1256 | db %00000000
1257 | db %00000000
1258 | db %00000000
1259 | db %00000000
1260 | db %00000000
1261 | db %00000000
1262 | db %00000000
1263 |
1264 | // $44: D
1265 | db %01111100
1266 | db %00000000
1267 | db %01100110
1268 | db %00000000
1269 | db %01100110
1270 | db %00000000
1271 | db %01100110
1272 | db %00000000
1273 | db %01111110
1274 | db %00000000
1275 | db %01111100
1276 | db %00000000
1277 | db %00000000
1278 | db %00000000
1279 | db %00000000
1280 | db %00000000
1281 |
1282 | db %00000000
1283 | db %00000000
1284 | db %00000000
1285 | db %00000000
1286 | db %00000000
1287 | db %00000000
1288 | db %00000000
1289 | db %00000000
1290 | db %00000000
1291 | db %00000000
1292 | db %00000000
1293 | db %00000000
1294 | db %00000000
1295 | db %00000000
1296 | db %00000000
1297 | db %00000000
1298 |
1299 | // $45: E
1300 | db %01111110
1301 | db %00000000
1302 | db %01100000
1303 | db %00000000
1304 | db %01111100
1305 | db %00000000
1306 | db %01100000
1307 | db %00000000
1308 | db %01111110
1309 | db %00000000
1310 | db %01111110
1311 | db %00000000
1312 | db %00000000
1313 | db %00000000
1314 | db %00000000
1315 | db %00000000
1316 |
1317 | db %00000000
1318 | db %00000000
1319 | db %00000000
1320 | db %00000000
1321 | db %00000000
1322 | db %00000000
1323 | db %00000000
1324 | db %00000000
1325 | db %00000000
1326 | db %00000000
1327 | db %00000000
1328 | db %00000000
1329 | db %00000000
1330 | db %00000000
1331 | db %00000000
1332 | db %00000000
1333 |
1334 | // $46: F
1335 | db %01111110
1336 | db %00000000
1337 | db %01100000
1338 | db %00000000
1339 | db %01111100
1340 | db %00000000
1341 | db %01100000
1342 | db %00000000
1343 | db %01100000
1344 | db %00000000
1345 | db %01100000
1346 | db %00000000
1347 | db %00000000
1348 | db %00000000
1349 | db %00000000
1350 | db %00000000
1351 |
1352 | db %00000000
1353 | db %00000000
1354 | db %00000000
1355 | db %00000000
1356 | db %00000000
1357 | db %00000000
1358 | db %00000000
1359 | db %00000000
1360 | db %00000000
1361 | db %00000000
1362 | db %00000000
1363 | db %00000000
1364 | db %00000000
1365 | db %00000000
1366 | db %00000000
1367 | db %00000000
1368 |
1369 | // $47: G
1370 | db %00111100
1371 | db %00000000
1372 | db %01100110
1373 | db %00000000
1374 | db %01100000
1375 | db %00000000
1376 | db %01101110
1377 | db %00000000
1378 | db %01100110
1379 | db %00000000
1380 | db %00111100
1381 | db %00000000
1382 | db %00000000
1383 | db %00000000
1384 | db %00000000
1385 | db %00000000
1386 |
1387 | db %00000000
1388 | db %00000000
1389 | db %00000000
1390 | db %00000000
1391 | db %00000000
1392 | db %00000000
1393 | db %00000000
1394 | db %00000000
1395 | db %00000000
1396 | db %00000000
1397 | db %00000000
1398 | db %00000000
1399 | db %00000000
1400 | db %00000000
1401 | db %00000000
1402 | db %00000000
1403 |
1404 | // $48: H
1405 | db %01100110
1406 | db %00000000
1407 | db %01100110
1408 | db %00000000
1409 | db %01111110
1410 | db %00000000
1411 | db %01100110
1412 | db %00000000
1413 | db %01100110
1414 | db %00000000
1415 | db %01100110
1416 | db %00000000
1417 | db %00000000
1418 | db %00000000
1419 | db %00000000
1420 | db %00000000
1421 |
1422 | db %00000000
1423 | db %00000000
1424 | db %00000000
1425 | db %00000000
1426 | db %00000000
1427 | db %00000000
1428 | db %00000000
1429 | db %00000000
1430 | db %00000000
1431 | db %00000000
1432 | db %00000000
1433 | db %00000000
1434 | db %00000000
1435 | db %00000000
1436 | db %00000000
1437 | db %00000000
1438 |
1439 | // $49: I
1440 | db %01111110
1441 | db %00000000
1442 | db %00011000
1443 | db %00000000
1444 | db %00011000
1445 | db %00000000
1446 | db %00011000
1447 | db %00000000
1448 | db %01111110
1449 | db %00000000
1450 | db %01111110
1451 | db %00000000
1452 | db %00000000
1453 | db %00000000
1454 | db %00000000
1455 | db %00000000
1456 |
1457 | db %00000000
1458 | db %00000000
1459 | db %00000000
1460 | db %00000000
1461 | db %00000000
1462 | db %00000000
1463 | db %00000000
1464 | db %00000000
1465 | db %00000000
1466 | db %00000000
1467 | db %00000000
1468 | db %00000000
1469 | db %00000000
1470 | db %00000000
1471 | db %00000000
1472 | db %00000000
1473 |
1474 | // $4A: J
1475 | db %00111110
1476 | db %00000000
1477 | db %00001100
1478 | db %00000000
1479 | db %00001100
1480 | db %00000000
1481 | db %01001100
1482 | db %00000000
1483 | db %01111100
1484 | db %00000000
1485 | db %00111000
1486 | db %00000000
1487 | db %00000000
1488 | db %00000000
1489 | db %00000000
1490 | db %00000000
1491 |
1492 | db %00000000
1493 | db %00000000
1494 | db %00000000
1495 | db %00000000
1496 | db %00000000
1497 | db %00000000
1498 | db %00000000
1499 | db %00000000
1500 | db %00000000
1501 | db %00000000
1502 | db %00000000
1503 | db %00000000
1504 | db %00000000
1505 | db %00000000
1506 | db %00000000
1507 | db %00000000
1508 |
1509 | // $4B: K
1510 | db %01100110
1511 | db %00000000
1512 | db %01101100
1513 | db %00000000
1514 | db %01111000
1515 | db %00000000
1516 | db %01111000
1517 | db %00000000
1518 | db %01101100
1519 | db %00000000
1520 | db %01100110
1521 | db %00000000
1522 | db %00000000
1523 | db %00000000
1524 | db %00000000
1525 | db %00000000
1526 |
1527 | db %00000000
1528 | db %00000000
1529 | db %00000000
1530 | db %00000000
1531 | db %00000000
1532 | db %00000000
1533 | db %00000000
1534 | db %00000000
1535 | db %00000000
1536 | db %00000000
1537 | db %00000000
1538 | db %00000000
1539 | db %00000000
1540 | db %00000000
1541 | db %00000000
1542 | db %00000000
1543 |
1544 | // $4C: L
1545 | db %01100000
1546 | db %00000000
1547 | db %01100000
1548 | db %00000000
1549 | db %01100000
1550 | db %00000000
1551 | db %01100000
1552 | db %00000000
1553 | db %01111110
1554 | db %00000000
1555 | db %01111110
1556 | db %00000000
1557 | db %00000000
1558 | db %00000000
1559 | db %00000000
1560 | db %00000000
1561 |
1562 | db %00000000
1563 | db %00000000
1564 | db %00000000
1565 | db %00000000
1566 | db %00000000
1567 | db %00000000
1568 | db %00000000
1569 | db %00000000
1570 | db %00000000
1571 | db %00000000
1572 | db %00000000
1573 | db %00000000
1574 | db %00000000
1575 | db %00000000
1576 | db %00000000
1577 | db %00000000
1578 |
1579 | // $4D: M
1580 | db %01000010
1581 | db %00000000
1582 | db %01100110
1583 | db %00000000
1584 | db %01111110
1585 | db %00000000
1586 | db %01011010
1587 | db %00000000
1588 | db %01011010
1589 | db %00000000
1590 | db %01000010
1591 | db %00000000
1592 | db %00000000
1593 | db %00000000
1594 | db %00000000
1595 | db %00000000
1596 |
1597 | db %00000000
1598 | db %00000000
1599 | db %00000000
1600 | db %00000000
1601 | db %00000000
1602 | db %00000000
1603 | db %00000000
1604 | db %00000000
1605 | db %00000000
1606 | db %00000000
1607 | db %00000000
1608 | db %00000000
1609 | db %00000000
1610 | db %00000000
1611 | db %00000000
1612 | db %00000000
1613 |
1614 | // $4E: N
1615 | db %01000110
1616 | db %00000000
1617 | db %01100110
1618 | db %00000000
1619 | db %01110110
1620 | db %00000000
1621 | db %01111110
1622 | db %00000000
1623 | db %01101110
1624 | db %00000000
1625 | db %01100110
1626 | db %00000000
1627 | db %00000000
1628 | db %00000000
1629 | db %00000000
1630 | db %00000000
1631 |
1632 | db %00000000
1633 | db %00000000
1634 | db %00000000
1635 | db %00000000
1636 | db %00000000
1637 | db %00000000
1638 | db %00000000
1639 | db %00000000
1640 | db %00000000
1641 | db %00000000
1642 | db %00000000
1643 | db %00000000
1644 | db %00000000
1645 | db %00000000
1646 | db %00000000
1647 | db %00000000
1648 |
1649 | // $4F: O
1650 | db %00111100
1651 | db %00000000
1652 | db %01100110
1653 | db %00000000
1654 | db %01100110
1655 | db %00000000
1656 | db %01100110
1657 | db %00000000
1658 | db %01111110
1659 | db %00000000
1660 | db %00111100
1661 | db %00000000
1662 | db %00000000
1663 | db %00000000
1664 | db %00000000
1665 | db %00000000
1666 |
1667 | db %00000000
1668 | db %00000000
1669 | db %00000000
1670 | db %00000000
1671 | db %00000000
1672 | db %00000000
1673 | db %00000000
1674 | db %00000000
1675 | db %00000000
1676 | db %00000000
1677 | db %00000000
1678 | db %00000000
1679 | db %00000000
1680 | db %00000000
1681 | db %00000000
1682 | db %00000000
1683 |
1684 | // $50: P
1685 | db %01111100
1686 | db %00000000
1687 | db %01100110
1688 | db %00000000
1689 | db %01111110
1690 | db %00000000
1691 | db %01111100
1692 | db %00000000
1693 | db %01100000
1694 | db %00000000
1695 | db %01100000
1696 | db %00000000
1697 | db %00000000
1698 | db %00000000
1699 | db %00000000
1700 | db %00000000
1701 |
1702 | db %00000000
1703 | db %00000000
1704 | db %00000000
1705 | db %00000000
1706 | db %00000000
1707 | db %00000000
1708 | db %00000000
1709 | db %00000000
1710 | db %00000000
1711 | db %00000000
1712 | db %00000000
1713 | db %00000000
1714 | db %00000000
1715 | db %00000000
1716 | db %00000000
1717 | db %00000000
1718 |
1719 | // $51: Q
1720 | db %00111100
1721 | db %00000000
1722 | db %01100110
1723 | db %00000000
1724 | db %01100010
1725 | db %00000000
1726 | db %01101010
1727 | db %00000000
1728 | db %01111110
1729 | db %00000000
1730 | db %00111100
1731 | db %00000000
1732 | db %00000010
1733 | db %00000000
1734 | db %00000000
1735 | db %00000000
1736 |
1737 | db %00000000
1738 | db %00000000
1739 | db %00000000
1740 | db %00000000
1741 | db %00000000
1742 | db %00000000
1743 | db %00000000
1744 | db %00000000
1745 | db %00000000
1746 | db %00000000
1747 | db %00000000
1748 | db %00000000
1749 | db %00000000
1750 | db %00000000
1751 | db %00000000
1752 | db %00000000
1753 |
1754 | // $52: R
1755 | db %01111100
1756 | db %00000000
1757 | db %01100110
1758 | db %00000000
1759 | db %01111110
1760 | db %00000000
1761 | db %01111100
1762 | db %00000000
1763 | db %01101100
1764 | db %00000000
1765 | db %01100110
1766 | db %00000000
1767 | db %00000000
1768 | db %00000000
1769 | db %00000000
1770 | db %00000000
1771 |
1772 | db %00000000
1773 | db %00000000
1774 | db %00000000
1775 | db %00000000
1776 | db %00000000
1777 | db %00000000
1778 | db %00000000
1779 | db %00000000
1780 | db %00000000
1781 | db %00000000
1782 | db %00000000
1783 | db %00000000
1784 | db %00000000
1785 | db %00000000
1786 | db %00000000
1787 | db %00000000
1788 |
1789 | // $53: S
1790 | db %00111100
1791 | db %00000000
1792 | db %01100010
1793 | db %00000000
1794 | db %01111100
1795 | db %00000000
1796 | db %00111110
1797 | db %00000000
1798 | db %01000110
1799 | db %00000000
1800 | db %00111100
1801 | db %00000000
1802 | db %00000000
1803 | db %00000000
1804 | db %00000000
1805 | db %00000000
1806 |
1807 | db %00000000
1808 | db %00000000
1809 | db %00000000
1810 | db %00000000
1811 | db %00000000
1812 | db %00000000
1813 | db %00000000
1814 | db %00000000
1815 | db %00000000
1816 | db %00000000
1817 | db %00000000
1818 | db %00000000
1819 | db %00000000
1820 | db %00000000
1821 | db %00000000
1822 | db %00000000
1823 |
1824 | // $54: T
1825 | db %01111110
1826 | db %00000000
1827 | db %00011000
1828 | db %00000000
1829 | db %00011000
1830 | db %00000000
1831 | db %00011000
1832 | db %00000000
1833 | db %00011000
1834 | db %00000000
1835 | db %00011000
1836 | db %00000000
1837 | db %00000000
1838 | db %00000000
1839 | db %00000000
1840 | db %00000000
1841 |
1842 | db %00000000
1843 | db %00000000
1844 | db %00000000
1845 | db %00000000
1846 | db %00000000
1847 | db %00000000
1848 | db %00000000
1849 | db %00000000
1850 | db %00000000
1851 | db %00000000
1852 | db %00000000
1853 | db %00000000
1854 | db %00000000
1855 | db %00000000
1856 | db %00000000
1857 | db %00000000
1858 |
1859 | // $55: U
1860 | db %01100110
1861 | db %00000000
1862 | db %01100110
1863 | db %00000000
1864 | db %01100110
1865 | db %00000000
1866 | db %01100110
1867 | db %00000000
1868 | db %01111110
1869 | db %00000000
1870 | db %00111100
1871 | db %00000000
1872 | db %00000000
1873 | db %00000000
1874 | db %00000000
1875 | db %00000000
1876 |
1877 | db %00000000
1878 | db %00000000
1879 | db %00000000
1880 | db %00000000
1881 | db %00000000
1882 | db %00000000
1883 | db %00000000
1884 | db %00000000
1885 | db %00000000
1886 | db %00000000
1887 | db %00000000
1888 | db %00000000
1889 | db %00000000
1890 | db %00000000
1891 | db %00000000
1892 | db %00000000
1893 |
1894 | // $56: V
1895 | db %01100110
1896 | db %00000000
1897 | db %01100110
1898 | db %00000000
1899 | db %01100110
1900 | db %00000000
1901 | db %00100100
1902 | db %00000000
1903 | db %00111100
1904 | db %00000000
1905 | db %00011000
1906 | db %00000000
1907 | db %00000000
1908 | db %00000000
1909 | db %00000000
1910 | db %00000000
1911 |
1912 | db %00000000
1913 | db %00000000
1914 | db %00000000
1915 | db %00000000
1916 | db %00000000
1917 | db %00000000
1918 | db %00000000
1919 | db %00000000
1920 | db %00000000
1921 | db %00000000
1922 | db %00000000
1923 | db %00000000
1924 | db %00000000
1925 | db %00000000
1926 | db %00000000
1927 | db %00000000
1928 |
1929 | // $57: W
1930 | db %01000010
1931 | db %00000000
1932 | db %01011010
1933 | db %00000000
1934 | db %01011010
1935 | db %00000000
1936 | db %01111110
1937 | db %00000000
1938 | db %01100110
1939 | db %00000000
1940 | db %01000010
1941 | db %00000000
1942 | db %00000000
1943 | db %00000000
1944 | db %00000000
1945 | db %00000000
1946 |
1947 | db %00000000
1948 | db %00000000
1949 | db %00000000
1950 | db %00000000
1951 | db %00000000
1952 | db %00000000
1953 | db %00000000
1954 | db %00000000
1955 | db %00000000
1956 | db %00000000
1957 | db %00000000
1958 | db %00000000
1959 | db %00000000
1960 | db %00000000
1961 | db %00000000
1962 | db %00000000
1963 |
1964 | // $58: X
1965 | db %01100110
1966 | db %00000000
1967 | db %00111100
1968 | db %00000000
1969 | db %00011000
1970 | db %00000000
1971 | db %00111100
1972 | db %00000000
1973 | db %01100110
1974 | db %00000000
1975 | db %01000010
1976 | db %00000000
1977 | db %00000000
1978 | db %00000000
1979 | db %00000000
1980 | db %00000000
1981 |
1982 | db %00000000
1983 | db %00000000
1984 | db %00000000
1985 | db %00000000
1986 | db %00000000
1987 | db %00000000
1988 | db %00000000
1989 | db %00000000
1990 | db %00000000
1991 | db %00000000
1992 | db %00000000
1993 | db %00000000
1994 | db %00000000
1995 | db %00000000
1996 | db %00000000
1997 | db %00000000
1998 |
1999 | // $59: Y
2000 | db %01100110
2001 | db %00000000
2002 | db %01100110
2003 | db %00000000
2004 | db %00111100
2005 | db %00000000
2006 | db %00011000
2007 | db %00000000
2008 | db %00011000
2009 | db %00000000
2010 | db %00011000
2011 | db %00000000
2012 | db %00000000
2013 | db %00000000
2014 | db %00000000
2015 | db %00000000
2016 |
2017 | db %00000000
2018 | db %00000000
2019 | db %00000000
2020 | db %00000000
2021 | db %00000000
2022 | db %00000000
2023 | db %00000000
2024 | db %00000000
2025 | db %00000000
2026 | db %00000000
2027 | db %00000000
2028 | db %00000000
2029 | db %00000000
2030 | db %00000000
2031 | db %00000000
2032 | db %00000000
2033 |
2034 | // $5A: Z
2035 | db %01111110
2036 | db %00000000
2037 | db %00001100
2038 | db %00000000
2039 | db %00011000
2040 | db %00000000
2041 | db %00110000
2042 | db %00000000
2043 | db %01111110
2044 | db %00000000
2045 | db %01111110
2046 | db %00000000
2047 | db %00000000
2048 | db %00000000
2049 | db %00000000
2050 | db %00000000
2051 |
2052 | db %00000000
2053 | db %00000000
2054 | db %00000000
2055 | db %00000000
2056 | db %00000000
2057 | db %00000000
2058 | db %00000000
2059 | db %00000000
2060 | db %00000000
2061 | db %00000000
2062 | db %00000000
2063 | db %00000000
2064 | db %00000000
2065 | db %00000000
2066 | db %00000000
2067 | db %00000000
2068 |
2069 | //////////////////////////////////////////
2070 | // $5B: Opening square bracket "["
2071 | db %00011100
2072 | db %00000000
2073 | db %00011000
2074 | db %00000000
2075 | db %00011000
2076 | db %00000000
2077 | db %00011000
2078 | db %00000000
2079 | db %00011000
2080 | db %00000000
2081 | db %00011000
2082 | db %00000000
2083 | db %00011000
2084 | db %00000000
2085 | db %00011100
2086 | db %00000000
2087 |
2088 | db %00000000
2089 | db %00000000
2090 | db %00000000
2091 | db %00000000
2092 | db %00000000
2093 | db %00000000
2094 | db %00000000
2095 | db %00000000
2096 | db %00000000
2097 | db %00000000
2098 | db %00000000
2099 | db %00000000
2100 | db %00000000
2101 | db %00000000
2102 | db %00000000
2103 | db %00000000
2104 |
2105 | // $5C: Back slash "\"
2106 | db %01000000
2107 | db %00000000
2108 | db %01100000
2109 | db %00000000
2110 | db %00110000
2111 | db %00000000
2112 | db %00011000
2113 | db %00000000
2114 | db %00001100
2115 | db %00000000
2116 | db %00000110
2117 | db %00000000
2118 | db %00000010
2119 | db %00000000
2120 | db %00000000
2121 | db %00000000
2122 |
2123 | db %00000000
2124 | db %00000000
2125 | db %00000000
2126 | db %00000000
2127 | db %00000000
2128 | db %00000000
2129 | db %00000000
2130 | db %00000000
2131 | db %00000000
2132 | db %00000000
2133 | db %00000000
2134 | db %00000000
2135 | db %00000000
2136 | db %00000000
2137 | db %00000000
2138 | db %00000000
2139 |
2140 | // $5D: Closing square bracket "]"
2141 | db %00111000
2142 | db %00000000
2143 | db %00011000
2144 | db %00000000
2145 | db %00011000
2146 | db %00000000
2147 | db %00011000
2148 | db %00000000
2149 | db %00011000
2150 | db %00000000
2151 | db %00011000
2152 | db %00000000
2153 | db %00011000
2154 | db %00000000
2155 | db %00111000
2156 | db %00000000
2157 |
2158 | db %00000000
2159 | db %00000000
2160 | db %00000000
2161 | db %00000000
2162 | db %00000000
2163 | db %00000000
2164 | db %00000000
2165 | db %00000000
2166 | db %00000000
2167 | db %00000000
2168 | db %00000000
2169 | db %00000000
2170 | db %00000000
2171 | db %00000000
2172 | db %00000000
2173 | db %00000000
2174 |
2175 | // $5E: Caret "^"
2176 | db %00011000
2177 | db %00000000
2178 | db %00100100
2179 | db %00000000
2180 | db %01000010
2181 | db %00000000
2182 | db %00000000
2183 | db %00000000
2184 | db %00000000
2185 | db %00000000
2186 | db %00000000
2187 | db %00000000
2188 | db %00000000
2189 | db %00000000
2190 | db %00000000
2191 | db %00000000
2192 |
2193 | db %00000000
2194 | db %00000000
2195 | db %00000000
2196 | db %00000000
2197 | db %00000000
2198 | db %00000000
2199 | db %00000000
2200 | db %00000000
2201 | db %00000000
2202 | db %00000000
2203 | db %00000000
2204 | db %00000000
2205 | db %00000000
2206 | db %00000000
2207 | db %00000000
2208 | db %00000000
2209 |
2210 | // $5F: Underscore "_"
2211 | db %00000000
2212 | db %00000000
2213 | db %00000000
2214 | db %00000000
2215 | db %00000000
2216 | db %00000000
2217 | db %00000000
2218 | db %00000000
2219 | db %00000000
2220 | db %00000000
2221 | db %00000000
2222 | db %00000000
2223 | db %00000000
2224 | db %00000000
2225 | db %11111111
2226 | db %00000000
2227 |
2228 | db %00000000
2229 | db %00000000
2230 | db %00000000
2231 | db %00000000
2232 | db %00000000
2233 | db %00000000
2234 | db %00000000
2235 | db %00000000
2236 | db %00000000
2237 | db %00000000
2238 | db %00000000
2239 | db %00000000
2240 | db %00000000
2241 | db %00000000
2242 | db %00000000
2243 | db %00000000
2244 |
2245 | // $60: Opening single quote "`"
2246 | db %00011000
2247 | db %00000000
2248 | db %00011000
2249 | db %00000000
2250 | db %00001000
2251 | db %00000000
2252 | db %00000000
2253 | db %00000000
2254 | db %00000000
2255 | db %00000000
2256 | db %00000000
2257 | db %00000000
2258 | db %00000000
2259 | db %00000000
2260 | db %00000000
2261 | db %00000000
2262 |
2263 | db %00000000
2264 | db %00000000
2265 | db %00000000
2266 | db %00000000
2267 | db %00000000
2268 | db %00000000
2269 | db %00000000
2270 | db %00000000
2271 | db %00000000
2272 | db %00000000
2273 | db %00000000
2274 | db %00000000
2275 | db %00000000
2276 | db %00000000
2277 | db %00000000
2278 | db %00000000
2279 |
2280 | //////////////////////////////////////////
2281 | // $61: a
2282 | db %00000000
2283 | db %00000000
2284 | db %00000000
2285 | db %00000000
2286 | db %00111000
2287 | db %00000000
2288 | db %01100100
2289 | db %00000000
2290 | db %01100100
2291 | db %00000000
2292 | db %00111010
2293 | db %00000000
2294 | db %00000000
2295 | db %00000000
2296 | db %00000000
2297 | db %00000000
2298 |
2299 | db %00000000
2300 | db %00000000
2301 | db %00000000
2302 | db %00000000
2303 | db %00000000
2304 | db %00000000
2305 | db %00000000
2306 | db %00000000
2307 | db %00000000
2308 | db %00000000
2309 | db %00000000
2310 | db %00000000
2311 | db %00000000
2312 | db %00000000
2313 | db %00000000
2314 | db %00000000
2315 |
2316 | // $62: b
2317 | db %00110000
2318 | db %00000000
2319 | db %00110000
2320 | db %00000000
2321 | db %00111100
2322 | db %00000000
2323 | db %00110010
2324 | db %00000000
2325 | db %00110010
2326 | db %00000000
2327 | db %01011100
2328 | db %00000000
2329 | db %00000000
2330 | db %00000000
2331 | db %00000000
2332 | db %00000000
2333 |
2334 | db %00000000
2335 | db %00000000
2336 | db %00000000
2337 | db %00000000
2338 | db %00000000
2339 | db %00000000
2340 | db %00000000
2341 | db %00000000
2342 | db %00000000
2343 | db %00000000
2344 | db %00000000
2345 | db %00000000
2346 | db %00000000
2347 | db %00000000
2348 | db %00000000
2349 | db %00000000
2350 |
2351 | // $63: c
2352 | db %00000000
2353 | db %00000000
2354 | db %00000000
2355 | db %00000000
2356 | db %00111100
2357 | db %00000000
2358 | db %01100000
2359 | db %00000000
2360 | db %01100010
2361 | db %00000000
2362 | db %00111100
2363 | db %00000000
2364 | db %00000000
2365 | db %00000000
2366 | db %00000000
2367 | db %00000000
2368 |
2369 | db %00000000
2370 | db %00000000
2371 | db %00000000
2372 | db %00000000
2373 | db %00000000
2374 | db %00000000
2375 | db %00000000
2376 | db %00000000
2377 | db %00000000
2378 | db %00000000
2379 | db %00000000
2380 | db %00000000
2381 | db %00000000
2382 | db %00000000
2383 | db %00000000
2384 | db %00000000
2385 |
2386 | // $64: d
2387 | db %00001100
2388 | db %00000000
2389 | db %00001100
2390 | db %00000000
2391 | db %00111100
2392 | db %00000000
2393 | db %01001100
2394 | db %00000000
2395 | db %01001100
2396 | db %00000000
2397 | db %00111010
2398 | db %00000000
2399 | db %00000000
2400 | db %00000000
2401 | db %00000000
2402 | db %00000000
2403 |
2404 | db %00000000
2405 | db %00000000
2406 | db %00000000
2407 | db %00000000
2408 | db %00000000
2409 | db %00000000
2410 | db %00000000
2411 | db %00000000
2412 | db %00000000
2413 | db %00000000
2414 | db %00000000
2415 | db %00000000
2416 | db %00000000
2417 | db %00000000
2418 | db %00000000
2419 | db %00000000
2420 |
2421 | // $65: e
2422 | db %00000000
2423 | db %00000000
2424 | db %00000000
2425 | db %00000000
2426 | db %00111000
2427 | db %00000000
2428 | db %01101000
2429 | db %00000000
2430 | db %01110010
2431 | db %00000000
2432 | db %00111100
2433 | db %00000000
2434 | db %00000000
2435 | db %00000000
2436 | db %00000000
2437 | db %00000000
2438 |
2439 | db %00000000
2440 | db %00000000
2441 | db %00000000
2442 | db %00000000
2443 | db %00000000
2444 | db %00000000
2445 | db %00000000
2446 | db %00000000
2447 | db %00000000
2448 | db %00000000
2449 | db %00000000
2450 | db %00000000
2451 | db %00000000
2452 | db %00000000
2453 | db %00000000
2454 | db %00000000
2455 |
2456 | // $66: f
2457 | db %00000000
2458 | db %00000000
2459 | db %00000000
2460 | db %00000000
2461 | db %00011100
2462 | db %00000000
2463 | db %00110010
2464 | db %00000000
2465 | db %00110000
2466 | db %00000000
2467 | db %01111100
2468 | db %00000000
2469 | db %00110000
2470 | db %00000000
2471 | db %00110000
2472 | db %00000000
2473 |
2474 | db %00000000
2475 | db %00000000
2476 | db %00000000
2477 | db %00000000
2478 | db %00000000
2479 | db %00000000
2480 | db %00000000
2481 | db %00000000
2482 | db %00000000
2483 | db %00000000
2484 | db %00000000
2485 | db %00000000
2486 | db %00000000
2487 | db %00000000
2488 | db %00000000
2489 | db %00000000
2490 |
2491 | // $67: g
2492 | db %00000000
2493 | db %00000000
2494 | db %00000000
2495 | db %00000000
2496 | db %00111010
2497 | db %00000000
2498 | db %01100110
2499 | db %00000000
2500 | db %01100110
2501 | db %00000000
2502 | db %00111110
2503 | db %00000000
2504 | db %01000110
2505 | db %00000000
2506 | db %00111100
2507 | db %00000000
2508 |
2509 | db %00000000
2510 | db %00000000
2511 | db %00000000
2512 | db %00000000
2513 | db %00000000
2514 | db %00000000
2515 | db %00000000
2516 | db %00000000
2517 | db %00000000
2518 | db %00000000
2519 | db %00000000
2520 | db %00000000
2521 | db %00000000
2522 | db %00000000
2523 | db %00000000
2524 | db %00000000
2525 |
2526 | // $68: h
2527 | db %01100000
2528 | db %00000000
2529 | db %01100000
2530 | db %00000000
2531 | db %01111100
2532 | db %00000000
2533 | db %01100010
2534 | db %00000000
2535 | db %01100010
2536 | db %00000000
2537 | db %01100010
2538 | db %00000000
2539 | db %00000000
2540 | db %00000000
2541 | db %00000000
2542 | db %00000000
2543 |
2544 | db %00000000
2545 | db %00000000
2546 | db %00000000
2547 | db %00000000
2548 | db %00000000
2549 | db %00000000
2550 | db %00000000
2551 | db %00000000
2552 | db %00000000
2553 | db %00000000
2554 | db %00000000
2555 | db %00000000
2556 | db %00000000
2557 | db %00000000
2558 | db %00000000
2559 | db %00000000
2560 |
2561 | // $69: i
2562 | db %00110000
2563 | db %00000000
2564 | db %00000000
2565 | db %00000000
2566 | db %00110000
2567 | db %00000000
2568 | db %00110000
2569 | db %00000000
2570 | db %00110100
2571 | db %00000000
2572 | db %00011000
2573 | db %00000000
2574 | db %00000000
2575 | db %00000000
2576 | db %00000000
2577 | db %00000000
2578 |
2579 | db %00000000
2580 | db %00000000
2581 | db %00000000
2582 | db %00000000
2583 | db %00000000
2584 | db %00000000
2585 | db %00000000
2586 | db %00000000
2587 | db %00000000
2588 | db %00000000
2589 | db %00000000
2590 | db %00000000
2591 | db %00000000
2592 | db %00000000
2593 | db %00000000
2594 | db %00000000
2595 |
2596 | // $6A: j
2597 | db %00000110
2598 | db %00000000
2599 | db %00000000
2600 | db %00000000
2601 | db %00000110
2602 | db %00000000
2603 | db %00000110
2604 | db %00000000
2605 | db %00000110
2606 | db %00000000
2607 | db %00000110
2608 | db %00000000
2609 | db %01000110
2610 | db %00000000
2611 | db %00111100
2612 | db %00000000
2613 |
2614 | db %00000000
2615 | db %00000000
2616 | db %00000000
2617 | db %00000000
2618 | db %00000000
2619 | db %00000000
2620 | db %00000000
2621 | db %00000000
2622 | db %00000000
2623 | db %00000000
2624 | db %00000000
2625 | db %00000000
2626 | db %00000000
2627 | db %00000000
2628 | db %00000000
2629 | db %00000000
2630 |
2631 | // $6B: k
2632 | db %01100000
2633 | db %00000000
2634 | db %01100100
2635 | db %00000000
2636 | db %01101000
2637 | db %00000000
2638 | db %01111000
2639 | db %00000000
2640 | db %01100100
2641 | db %00000000
2642 | db %01100010
2643 | db %00000000
2644 | db %00000000
2645 | db %00000000
2646 | db %00000000
2647 | db %00000000
2648 |
2649 | db %00000000
2650 | db %00000000
2651 | db %00000000
2652 | db %00000000
2653 | db %00000000
2654 | db %00000000
2655 | db %00000000
2656 | db %00000000
2657 | db %00000000
2658 | db %00000000
2659 | db %00000000
2660 | db %00000000
2661 | db %00000000
2662 | db %00000000
2663 | db %00000000
2664 | db %00000000
2665 |
2666 | // $6C: l
2667 | db %00110000
2668 | db %00000000
2669 | db %00110000
2670 | db %00000000
2671 | db %00110000
2672 | db %00000000
2673 | db %00110000
2674 | db %00000000
2675 | db %00110100
2676 | db %00000000
2677 | db %00011000
2678 | db %00000000
2679 | db %00000000
2680 | db %00000000
2681 | db %00000000
2682 | db %00000000
2683 |
2684 | db %00000000
2685 | db %00000000
2686 | db %00000000
2687 | db %00000000
2688 | db %00000000
2689 | db %00000000
2690 | db %00000000
2691 | db %00000000
2692 | db %00000000
2693 | db %00000000
2694 | db %00000000
2695 | db %00000000
2696 | db %00000000
2697 | db %00000000
2698 | db %00000000
2699 | db %00000000
2700 |
2701 | // $6D: m
2702 | db %00000000
2703 | db %00000000
2704 | db %00000000
2705 | db %00000000
2706 | db %01010100
2707 | db %00000000
2708 | db %01101010
2709 | db %00000000
2710 | db %01101010
2711 | db %00000000
2712 | db %01100010
2713 | db %00000000
2714 | db %00000000
2715 | db %00000000
2716 | db %00000000
2717 | db %00000000
2718 |
2719 | db %00000000
2720 | db %00000000
2721 | db %00000000
2722 | db %00000000
2723 | db %00000000
2724 | db %00000000
2725 | db %00000000
2726 | db %00000000
2727 | db %00000000
2728 | db %00000000
2729 | db %00000000
2730 | db %00000000
2731 | db %00000000
2732 | db %00000000
2733 | db %00000000
2734 | db %00000000
2735 |
2736 | // $6E: n
2737 | db %00000000
2738 | db %00000000
2739 | db %00000000
2740 | db %00000000
2741 | db %01011100
2742 | db %00000000
2743 | db %01100010
2744 | db %00000000
2745 | db %01100010
2746 | db %00000000
2747 | db %01100010
2748 | db %00000000
2749 | db %00000000
2750 | db %00000000
2751 | db %00000000
2752 | db %00000000
2753 |
2754 | db %00000000
2755 | db %00000000
2756 | db %00000000
2757 | db %00000000
2758 | db %00000000
2759 | db %00000000
2760 | db %00000000
2761 | db %00000000
2762 | db %00000000
2763 | db %00000000
2764 | db %00000000
2765 | db %00000000
2766 | db %00000000
2767 | db %00000000
2768 | db %00000000
2769 | db %00000000
2770 |
2771 | // $6F: o
2772 | db %00000000
2773 | db %00000000
2774 | db %00000000
2775 | db %00000000
2776 | db %00111100
2777 | db %00000000
2778 | db %01100010
2779 | db %00000000
2780 | db %01100010
2781 | db %00000000
2782 | db %00111100
2783 | db %00000000
2784 | db %00000000
2785 | db %00000000
2786 | db %00000000
2787 | db %00000000
2788 |
2789 | db %00000000
2790 | db %00000000
2791 | db %00000000
2792 | db %00000000
2793 | db %00000000
2794 | db %00000000
2795 | db %00000000
2796 | db %00000000
2797 | db %00000000
2798 | db %00000000
2799 | db %00000000
2800 | db %00000000
2801 | db %00000000
2802 | db %00000000
2803 | db %00000000
2804 | db %00000000
2805 |
2806 | // $70: p
2807 | db %00000000
2808 | db %00000000
2809 | db %00000000
2810 | db %00000000
2811 | db %01011100
2812 | db %00000000
2813 | db %01100110
2814 | db %00000000
2815 | db %01100110
2816 | db %00000000
2817 | db %01111100
2818 | db %00000000
2819 | db %01100000
2820 | db %00000000
2821 | db %01100000
2822 | db %00000000
2823 |
2824 | db %00000000
2825 | db %00000000
2826 | db %00000000
2827 | db %00000000
2828 | db %00000000
2829 | db %00000000
2830 | db %00000000
2831 | db %00000000
2832 | db %00000000
2833 | db %00000000
2834 | db %00000000
2835 | db %00000000
2836 | db %00000000
2837 | db %00000000
2838 | db %00000000
2839 | db %00000000
2840 |
2841 | // $71: q
2842 | db %00000000
2843 | db %00000000
2844 | db %00000000
2845 | db %00000000
2846 | db %00110100
2847 | db %00000000
2848 | db %01001100
2849 | db %00000000
2850 | db %01001100
2851 | db %00000000
2852 | db %00111100
2853 | db %00000000
2854 | db %00001110
2855 | db %00000000
2856 | db %00001100
2857 | db %00000000
2858 |
2859 | db %00000000
2860 | db %00000000
2861 | db %00000000
2862 | db %00000000
2863 | db %00000000
2864 | db %00000000
2865 | db %00000000
2866 | db %00000000
2867 | db %00000000
2868 | db %00000000
2869 | db %00000000
2870 | db %00000000
2871 | db %00000000
2872 | db %00000000
2873 | db %00000000
2874 | db %00000000
2875 |
2876 | // $72: r
2877 | db %00000000
2878 | db %00000000
2879 | db %00000000
2880 | db %00000000
2881 | db %01011100
2882 | db %00000000
2883 | db %01100010
2884 | db %00000000
2885 | db %01100000
2886 | db %00000000
2887 | db %01100000
2888 | db %00000000
2889 | db %00000000
2890 | db %00000000
2891 | db %00000000
2892 | db %00000000
2893 |
2894 | db %00000000
2895 | db %00000000
2896 | db %00000000
2897 | db %00000000
2898 | db %00000000
2899 | db %00000000
2900 | db %00000000
2901 | db %00000000
2902 | db %00000000
2903 | db %00000000
2904 | db %00000000
2905 | db %00000000
2906 | db %00000000
2907 | db %00000000
2908 | db %00000000
2909 | db %00000000
2910 |
2911 | // $73: s
2912 | db %00000000
2913 | db %00000000
2914 | db %00111100
2915 | db %00000000
2916 | db %01100010
2917 | db %00000000
2918 | db %00011000
2919 | db %00000000
2920 | db %01000110
2921 | db %00000000
2922 | db %00111100
2923 | db %00000000
2924 | db %00000000
2925 | db %00000000
2926 | db %00000000
2927 | db %00000000
2928 |
2929 | db %00000000
2930 | db %00000000
2931 | db %00000000
2932 | db %00000000
2933 | db %00000000
2934 | db %00000000
2935 | db %00000000
2936 | db %00000000
2937 | db %00000000
2938 | db %00000000
2939 | db %00000000
2940 | db %00000000
2941 | db %00000000
2942 | db %00000000
2943 | db %00000000
2944 | db %00000000
2945 |
2946 | // $74: t
2947 | db %00110000
2948 | db %00000000
2949 | db %00110000
2950 | db %00000000
2951 | db %01111000
2952 | db %00000000
2953 | db %00110000
2954 | db %00000000
2955 | db %00110010
2956 | db %00000000
2957 | db %00011100
2958 | db %00000000
2959 | db %00000000
2960 | db %00000000
2961 | db %00000000
2962 | db %00000000
2963 |
2964 | db %00000000
2965 | db %00000000
2966 | db %00000000
2967 | db %00000000
2968 | db %00000000
2969 | db %00000000
2970 | db %00000000
2971 | db %00000000
2972 | db %00000000
2973 | db %00000000
2974 | db %00000000
2975 | db %00000000
2976 | db %00000000
2977 | db %00000000
2978 | db %00000000
2979 | db %00000000
2980 |
2981 | // $75: u
2982 | db %00000000
2983 | db %00000000
2984 | db %00000000
2985 | db %00000000
2986 | db %01100110
2987 | db %00000000
2988 | db %01100110
2989 | db %00000000
2990 | db %01100110
2991 | db %00000000
2992 | db %00111010
2993 | db %00000000
2994 | db %00000000
2995 | db %00000000
2996 | db %00000000
2997 | db %00000000
2998 |
2999 | db %00000000
3000 | db %00000000
3001 | db %00000000
3002 | db %00000000
3003 | db %00000000
3004 | db %00000000
3005 | db %00000000
3006 | db %00000000
3007 | db %00000000
3008 | db %00000000
3009 | db %00000000
3010 | db %00000000
3011 | db %00000000
3012 | db %00000000
3013 | db %00000000
3014 | db %00000000
3015 |
3016 | // $76: v
3017 | db %00000000
3018 | db %00000000
3019 | db %00000000
3020 | db %00000000
3021 | db %01100010
3022 | db %00000000
3023 | db %01100010
3024 | db %00000000
3025 | db %00110100
3026 | db %00000000
3027 | db %00011000
3028 | db %00000000
3029 | db %00000000
3030 | db %00000000
3031 | db %00000000
3032 | db %00000000
3033 |
3034 | db %00000000
3035 | db %00000000
3036 | db %00000000
3037 | db %00000000
3038 | db %00000000
3039 | db %00000000
3040 | db %00000000
3041 | db %00000000
3042 | db %00000000
3043 | db %00000000
3044 | db %00000000
3045 | db %00000000
3046 | db %00000000
3047 | db %00000000
3048 | db %00000000
3049 | db %00000000
3050 |
3051 | // $77: w
3052 | db %00000000
3053 | db %00000000
3054 | db %00000000
3055 | db %00000000
3056 | db %01000010
3057 | db %00000000
3058 | db %01011010
3059 | db %00000000
3060 | db %01011010
3061 | db %00000000
3062 | db %00101100
3063 | db %00000000
3064 | db %00000000
3065 | db %00000000
3066 | db %00000000
3067 | db %00000000
3068 |
3069 | db %00000000
3070 | db %00000000
3071 | db %00000000
3072 | db %00000000
3073 | db %00000000
3074 | db %00000000
3075 | db %00000000
3076 | db %00000000
3077 | db %00000000
3078 | db %00000000
3079 | db %00000000
3080 | db %00000000
3081 | db %00000000
3082 | db %00000000
3083 | db %00000000
3084 | db %00000000
3085 |
3086 | // $78: x
3087 | db %00000000
3088 | db %00000000
3089 | db %00000000
3090 | db %00000000
3091 | db %01100010
3092 | db %00000000
3093 | db %00110100
3094 | db %00000000
3095 | db %00011000
3096 | db %00000000
3097 | db %01100110
3098 | db %00000000
3099 | db %00000000
3100 | db %00000000
3101 | db %00000000
3102 | db %00000000
3103 |
3104 | db %00000000
3105 | db %00000000
3106 | db %00000000
3107 | db %00000000
3108 | db %00000000
3109 | db %00000000
3110 | db %00000000
3111 | db %00000000
3112 | db %00000000
3113 | db %00000000
3114 | db %00000000
3115 | db %00000000
3116 | db %00000000
3117 | db %00000000
3118 | db %00000000
3119 | db %00000000
3120 |
3121 | // $79: y
3122 | db %00000000
3123 | db %00000000
3124 | db %00000000
3125 | db %00000000
3126 | db %01100110
3127 | db %00000000
3128 | db %01100110
3129 | db %00000000
3130 | db %01100110
3131 | db %00000000
3132 | db %00111110
3133 | db %00000000
3134 | db %01000110
3135 | db %00000000
3136 | db %00111100
3137 | db %00000000
3138 |
3139 | db %00000000
3140 | db %00000000
3141 | db %00000000
3142 | db %00000000
3143 | db %00000000
3144 | db %00000000
3145 | db %00000000
3146 | db %00000000
3147 | db %00000000
3148 | db %00000000
3149 | db %00000000
3150 | db %00000000
3151 | db %00000000
3152 | db %00000000
3153 | db %00000000
3154 | db %00000000
3155 |
3156 | // $7A: z
3157 | db %00000000
3158 | db %00000000
3159 | db %00000000
3160 | db %00000000
3161 | db %01111110
3162 | db %00000000
3163 | db %00001100
3164 | db %00000000
3165 | db %00110000
3166 | db %00000000
3167 | db %01111110
3168 | db %00000000
3169 | db %00000000
3170 | db %00000000
3171 | db %00000000
3172 | db %00000000
3173 |
3174 | db %00000000
3175 | db %00000000
3176 | db %00000000
3177 | db %00000000
3178 | db %00000000
3179 | db %00000000
3180 | db %00000000
3181 | db %00000000
3182 | db %00000000
3183 | db %00000000
3184 | db %00000000
3185 | db %00000000
3186 | db %00000000
3187 | db %00000000
3188 | db %00000000
3189 | db %00000000
3190 |
3191 | //////////////////////////////////////////
3192 | // $7B: Opening curly bracket "{"
3193 | db %00011100
3194 | db %00000000
3195 | db %00110000
3196 | db %00000000
3197 | db %00110000
3198 | db %00000000
3199 | db %00011000
3200 | db %00000000
3201 | db %00011000
3202 | db %00000000
3203 | db %00110000
3204 | db %00000000
3205 | db %00110000
3206 | db %00000000
3207 | db %00011100
3208 | db %00000000
3209 |
3210 | db %00000000
3211 | db %00000000
3212 | db %00000000
3213 | db %00000000
3214 | db %00000000
3215 | db %00000000
3216 | db %00000000
3217 | db %00000000
3218 | db %00000000
3219 | db %00000000
3220 | db %00000000
3221 | db %00000000
3222 | db %00000000
3223 | db %00000000
3224 | db %00000000
3225 | db %00000000
3226 |
3227 | // $7C: Vertical line "|"
3228 | db %00011000
3229 | db %00000000
3230 | db %00011000
3231 | db %00000000
3232 | db %00011000
3233 | db %00000000
3234 | db %00011000
3235 | db %00000000
3236 | db %00011000
3237 | db %00000000
3238 | db %00011000
3239 | db %00000000
3240 | db %00011000
3241 | db %00000000
3242 | db %00011000
3243 | db %00000000
3244 |
3245 | db %00000000
3246 | db %00000000
3247 | db %00000000
3248 | db %00000000
3249 | db %00000000
3250 | db %00000000
3251 | db %00000000
3252 | db %00000000
3253 | db %00000000
3254 | db %00000000
3255 | db %00000000
3256 | db %00000000
3257 | db %00000000
3258 | db %00000000
3259 | db %00000000
3260 | db %00000000
3261 |
3262 | // $7D: Closing curly bracket "{"
3263 | db %00111000
3264 | db %00000000
3265 | db %00001100
3266 | db %00000000
3267 | db %00001100
3268 | db %00000000
3269 | db %00011000
3270 | db %00000000
3271 | db %00011000
3272 | db %00000000
3273 | db %00001100
3274 | db %00000000
3275 | db %00001100
3276 | db %00000000
3277 | db %00111000
3278 | db %00000000
3279 |
3280 | db %00000000
3281 | db %00000000
3282 | db %00000000
3283 | db %00000000
3284 | db %00000000
3285 | db %00000000
3286 | db %00000000
3287 | db %00000000
3288 | db %00000000
3289 | db %00000000
3290 | db %00000000
3291 | db %00000000
3292 | db %00000000
3293 | db %00000000
3294 | db %00000000
3295 | db %00000000
3296 |
3297 | // $7E: Tilde "~"
3298 | db %00000000
3299 | db %00000000
3300 | db %00000000
3301 | db %00000000
3302 | db %01110000
3303 | db %00000000
3304 | db %01011010
3305 | db %00000000
3306 | db %00001110
3307 | db %00000000
3308 | db %00000000
3309 | db %00000000
3310 | db %00000000
3311 | db %00000000
3312 | db %00000000
3313 | db %00000000
3314 |
3315 | db %00000000
3316 | db %00000000
3317 | db %00000000
3318 | db %00000000
3319 | db %00000000
3320 | db %00000000
3321 | db %00000000
3322 | db %00000000
3323 | db %00000000
3324 | db %00000000
3325 | db %00000000
3326 | db %00000000
3327 | db %00000000
3328 | db %00000000
3329 | db %00000000
3330 | db %00000000
--------------------------------------------------------------------------------
/VDC/HelloWorld/HelloWorld.asm:
--------------------------------------------------------------------------------
1 | // PC-Engine "Hello, World!" Text Printing Demo by krom (Peter Lemon):
2 | arch pce.cpu
3 | output "HelloWorld.pce", create
4 |
5 | macro seek(variable offset) {
6 | origin (offset - $E000)
7 | base offset
8 | }
9 |
10 | // PRG BANK 0 (8KB)
11 | seek($E000); fill $2000 // Fill Bank 0 With Zero Bytes
12 | include "LIB/PCE.INC" // Include PC-Engine Definitions
13 | include "LIB/PCE_VECTOR.ASM" // Include Vector Table
14 |
15 | seek($E000); Start:
16 | PCE_INIT() // Run PC-Engine Initialisation Routine
17 |
18 | lda #$FF // A = $FF (Segment To Access I/O Ports)
19 | tam #MPR6 // MPR6 = A
20 |
21 | // VCE: Set Color Table Address (CTA) To Zero
22 | stz (6<<13)+VCE_CTA // MPR6:VCE_CTA = 0 ($FF:0402) (Lo Byte)
23 | stz (6<<13)+VCE_CTA+1 // MPR6:VCE_CTA+1 = 0 ($FF:0403) (Hi Byte)
24 |
25 | // VCE: Set Color Table (CTRW) Index 0 To Black (9-Bit GRB333)
26 | lda #%00000000 // A = %00000000
27 | sta (6<<13)+VCE_CTRW // MPR6:VCE_CTRW = A ($FF:0404) (Lo Byte)
28 | lda #%00000000 // A = %00000000
29 | sta (6<<13)+VCE_CTRW+1 // MPR6:VCE_CTRW+1 = A ($FF:0405) (Hi Byte)
30 |
31 | // VCE: Set Color Table (CTRW) Index 1 To White (9-Bit GRB333)
32 | lda #%11111111 // A = %11111111
33 | sta (6<<13)+VCE_CTRW // MPR6:VCE_CTRW = A ($FF:0404) (Lo Byte)
34 | lda #%00000001 // A = %00000001
35 | sta (6<<13)+VCE_CTRW+1 // MPR6:VCE_CTRW+1 = A ($FF:0405) (Hi Byte)
36 |
37 | // VDC: Set BG Screen X-Offset To Zero
38 | st0 #VDC_BXR // VDC: Set VDC Address To Background X-Scroll Register (BXR)
39 | st1 #0 // VDC: Data = 0 (Lo Byte)
40 | st2 #0 // VDC: Data = 0 (Hi Byte)
41 |
42 | // VDC: Set BG Screen Y-Offset To Zero
43 | st0 #VDC_BYR // VDC: Set VDC Address To Background Y-Scroll Register (BYR)
44 | st1 #0 // VDC: Data = 0 (Lo Byte)
45 | st2 #0 // VDC: Data = 0 (Hi Byte)
46 |
47 | // VDC: Set BG Virtual Screen Width & Height To 32x32 Tiles
48 | st0 #VDC_MWR // VDC: Set VDC Address To Memory Width Register (MWR)
49 | st1 #VDC_SCRW32+VDC_SCRH32 // VDC: Data = 0 (Lo Byte)
50 | st2 #0 // VDC: Data = 0 (Hi Byte)
51 |
52 | // Write Tile Data To VRAM
53 | // VDC: Set VRAM Write Address To $0400
54 | st0 #VDC_MAWR // VDC: Set VDC Address To Memory Address Write Register (VRAM Write Address) (MAWR)
55 | st1 #$00 // VDC: Data = $00 (Lo Byte)
56 | st2 #$04 // VDC: Data = $04 (Hi Byte)
57 |
58 | st0 #VDC_VWR // VDC: Set VDC Address To VRAM Data Write Register (VWR)
59 | tia BGCHR,(6<<13)+VDC_DATAL,3040 // MPR6:VDC_DATAL = SOURCE ($FF:0002) (Lo Byte)
60 |
61 | // Write Tile Map (BAT) To VRAM
62 | // VDC: Set VRAM Write Address To $012C
63 | st0 #VDC_MAWR // VDC: Set VDC Address To Memory Address Write Register (VRAM Write Address) (MAWR)
64 | st1 #$2C // VDC: Data = $2C (Lo Byte)
65 | st2 #$01 // VDC: Data = $01 (Hi Byte)
66 |
67 | st0 #VDC_VWR // VDC: Set VDC Address To VRAM Data Write Register (VWR)
68 | tia HELLOWORLD,(6<<13)+VDC_DATAL,26 // MPR6:VDC_DATAL = SOURCE ($FF:0002) (Lo Byte)
69 |
70 | // VDC: Turn On BG Screen
71 | st0 #VDC_CR // VDC: Set VDC Address To Control Register (CR)
72 | st1 #VDC_BB // VDC: Data = BB Flag (Background Enable/Disable) (Lo Byte)
73 | st2 #0 // VDC: Data = 0 (Hi Byte)
74 |
75 | Loop:
76 | bra Loop
77 |
78 | // Map Char Table
79 | map ' ', $0040, $5F
80 |
81 | HELLOWORLD:
82 | dw "Hello, World!" // Hello World Text (26 Bytes)
83 |
84 | BGCHR:
85 | include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (3040 Bytes)
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/VDC/HelloWorld/HelloWorld.pce:
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https://raw.githubusercontent.com/PeterLemon/PCE/3fcf708899ce67f166a667f9bc2da0f18d54a743/VDC/HelloWorld/HelloWorld.pce
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/VDC/HelloWorld/HelloWorld.png:
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https://raw.githubusercontent.com/PeterLemon/PCE/3fcf708899ce67f166a667f9bc2da0f18d54a743/VDC/HelloWorld/HelloWorld.png
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/VDC/HelloWorld/LIB/PCE.INC:
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1 | //=================== (Key: R=Read, W=Write)
2 | // PC-Engine Include
3 | //===================
4 | // Memory Map
5 | // Physical Address | Segment : Address
6 | // $000000..$0FFFFF | $00:0000..$7F:1FFF - HuCard/TurboChip ROM 1MB/R
7 | // $1F0000..$1F7FFF | $F8:0000..$FB:1FFF - Work RAM (8KB, Mirrored Four Times) 32KB/RW
8 | // $1FE000..$1FE3FF | $FF:0000..$FF:03FF - VDC Registers (HuC6270) 1KB/RW
9 | // $1FE400..$1FE7FF | $FF:0400..$FF:07FF - VCE Registers (HuC6260) 1KB/RW
10 | // $1FE800..$1FEBFF | $FF:0800..$FF:0BFF - PSG Registers 1KB/RW
11 | // $1FF000..$1FF3FF | $FF:1000..$FF:13FF - 8-Bit I/O Port 1KB/RW
12 | // $1FF400..$1FF7FF | $FF:1400..$FF:17FF - Interrupt Controller 1KB/RW
13 |
14 | // Segment Registers (Use TMA/TAM To Read/Write Segment Registers, Can Write To Multiple Registers At Once)
15 | constant MPR0($01) // MPR0 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
16 | constant MPR1($02) // MPR1 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
17 | constant MPR2($04) // MPR2 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
18 | constant MPR3($08) // MPR3 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
19 | constant MPR4($10) // MPR4 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
20 | constant MPR5($20) // MPR5 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
21 | constant MPR6($40) // MPR6 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
22 | constant MPR7($80) // MPR7 - 8-Bit Segment Register Concated With Lower 13-Bit Address (Hi 3-Bit Address = MPR)
23 |
24 | // VDC Registers (HuC6270) (Mapped To Segment $FF:XXXX)
25 | constant VDC_STATUS($0000) // VDC Status Register 2B/R
26 | constant VDC_CR_FLAG($01) // VDC Status Read: Bit 0 - CR Flag (Set On Sprite #0 Collision) 1Bit/R
27 | constant VDC_OR_FLAG($02) // VDC Status Read: Bit 1 - OR Flag (Set On Sprite Overflow) 1Bit/R
28 | constant VDC_PR_FLAG($04) // VDC Status Read: Bit 2 - PR Flag (Set On Scanline Interrupt) 1Bit/R
29 | constant VDC_DS_FLAG($08) // VDC Status Read: Bit 3 - DS Flag (Set On VRAM -> SATB Transfer Complete) 1Bit/R
30 | constant VDC_DV_FLAG($10) // VDC Status Read: Bit 4 - DV Flag (Set On VRAM DMA Transfer Complete) 1Bit/R
31 | constant VDC_VD_FLAG($20) // VDC Status Read: Bit 5 - VD Flag (Set On Vertical Blank) 1Bit/R
32 | constant VDC_BSY_FLAG($40) // VDC Status Read: Bit 6 - BSY Flag (Set On VRAM DMA Transfer Busy) 1Bit/R
33 | // VDC Status Read: Bit 7..15 - Unused 9Bit/R
34 |
35 | constant VDC_ADDR($0000) // VDC Address Register: ST0 Opcode Can Store Immediate Value Here 2B/W
36 | // VDC Address Write: Bit 0..4 - VDC Register Address Access 5Bit/W
37 | // VDC Address Write: Bit 5..15 - Unused 11Bit/W
38 |
39 | constant VDC_DATAL($0002) // VDC Data LSB Register: ST1 Opcode Can Store Immediate Value Here 1B/RW
40 | constant VDC_DATAH($0003) // VDC Data MSB Register: ST2 Opcode Can Store Immediate Value Here 1B/RW
41 |
42 | // VDC Memory Map (Read/Write 2 Byte VDC Data To These Register Addresses)
43 | // VDC VRAM Registers
44 | constant VDC_MAWR($00) // VDC MAWR - Memory Address Write Register (VRAM Write Address) 2B/RW
45 | constant VDC_MARR($01) // VDC MARR - Memory Address Read Register (VRAM Read Address) 2B/RW
46 | constant VDC_VWR($02) // VDC VWR - VRAM Data Write Register 2B/RW
47 | constant VDC_VRR($02) // VDC VRR - VRAM Data Read Register 2B/RW
48 |
49 | constant VDC_CR($05) // VDC CR - Control Register 2B/RW
50 | // VDC L CR Read: Bit 0 - CR Flag (Set On Sprite #0 Collision) 1Bit/R
51 | // VDC L CR Read: Bit 1 - OR Flag (Set On Sprite Overflow) 1Bit/R
52 | // VDC L CR Read: Bit 2 - PR Flag (Set On Scanline Interrupt) 1Bit/R
53 | // VDC L CR Read: Bit 3 - VD Flag (Set On Vertical Blank) 1Bit/R
54 | // VDC L CR Read: Bit 4..15 - Unused 12Bit/R
55 |
56 | constant VDC_IE0($01) // VDC L CR Write: Bit 0 - IE Flag 0 (Interrupt Enable/Disable) 1Bit/W
57 | constant VDC_IE1($02) // VDC L CR Write: Bit 1 - IE Flag 1 (Interrupt Enable/Disable) 1Bit/W
58 | constant VDC_IE2($04) // VDC L CR Write: Bit 2 - IE Flag 2 (Interrupt Enable/Disable) 1Bit/W
59 | constant VDC_IE3($08) // VDC L CR Write: Bit 3 - IE Flag 3 (Interrupt Enable/Disable) 1Bit/W
60 | constant VDC_EXH($10) // VDC L CR Write: Bit 4 - EX Horizontal Sync (Signal Input/Output) 1Bit/W
61 | constant VDC_EXV($20) // VDC L CR Write: Bit 5 - EX Vertical Sync (Signal Input/Output) 1Bit/W
62 | constant VDC_SB($40) // VDC L CR Write: Bit 6 - SB Flag (Sprites Enable/Disable) 1Bit/W
63 | constant VDC_BB($80) // VDC L CR Write: Bit 7 - BB Flag (Background Enable/Disable) 1Bit/W
64 | constant VDC_DISP($00) // VDC H CR Write: Bit 8..9 - DR Selects DISP Terminal Output (%00) 2Bit/W
65 | constant VDC_BURST($01) // VDC H CR Write: Bit 8..9 - DR Selects BURST Terminal Output (%01) 2Bit/W
66 | constant VDC_INTHSYNC($02) // VDC H CR Write: Bit 8..9 - DR Selects INTHSYNC Terminal Output (%10) 2Bit/W
67 | // VDC H CR Write: Bit 8..9 - DR Selects Unused Terminal Output (%11) 2Bit/W
68 | constant VDC_DR($04) // VDC H CR Write: Bit 10 - DR Flag (Dynamic RAM Refresh Enable/Disable) 1Bit/W
69 | constant VDC_INC01($00) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $01 (%00) 2Bit/W
70 | constant VDC_INC20($08) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $20 (%01) 2Bit/W
71 | constant VDC_INC40($10) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $40 (%10) 2Bit/W
72 | constant VDC_INC80($18) // VDC H CR Write: Bit 11..12 - VRAM Read/Write Address Auto-Increment $80 (%11) 2Bit/W
73 | // VDC H CR Write: Bit 13..15 - Unused 3Bit/W
74 |
75 | constant VDC_RCR($06) // VDC RCR - Raster Counter Register 2B/RW
76 |
77 | constant VDC_BXR($07) // VDC BXR - Background X-Scroll Register 2B/RW
78 | // VDC BXR: Bit 0..9 - Screen X-Offset (In Pixels) 10Bit/RW
79 | // VDC BXR: Bit 10..15 - Unused 6Bit/RW
80 |
81 | constant VDC_BYR($08) // VDC BYR - Background Y-Scroll Register 2B/RW
82 | // VDC BYR: Bit 0..8 - Screen Y-Offset (In Pixels) 9Bit/RW
83 | // VDC BYR: Bit 9..15 - Unused 7Bit/RW
84 |
85 | constant VDC_MWR($09) // VDC MWR - Memory Width Register 2B/RW
86 | constant VDC_VW0($00) // VDC MWR: Bit 0..1 - VRAM Pixel Width 0 (%00) 2Bit/RW
87 | constant VDC_VW1($01) // VDC MWR: Bit 0..1 - VRAM Pixel Width 1 (%01) 2Bit/RW
88 | constant VDC_VW2($02) // VDC MWR: Bit 0..1 - VRAM Pixel Width 2 (%10) 2Bit/RW
89 | constant VDC_VW3($03) // VDC MWR: Bit 0..1 - VRAM Pixel Width 3 (%11) 2Bit/RW
90 | constant VDC_SW0($00) // VDC MWR: Bit 2..3 - Sprite Pixel Width 0 (%00) 2Bit/RW
91 | constant VDC_SW1($04) // VDC MWR: Bit 2..3 - Sprite Pixel Width 1 (%01) 2Bit/RW
92 | constant VDC_SW2($08) // VDC MWR: Bit 2..3 - Sprite Pixel Width 2 (%10) 2Bit/RW
93 | constant VDC_SW3($0C) // VDC MWR: Bit 2..3 - Sprite Pixel Width 3 (%11) 2Bit/RW
94 | constant VDC_SCRW32($00) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 32 (256 Pixels) (%00) 2Bit/RW
95 | constant VDC_SCRW64($10) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 64 (512 Pixels) (%01) 2Bit/RW
96 | constant VDC_SCRW128($20) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 128 (1024 Pixels) (%10) 2Bit/RW
97 | constant VDC_SCRW128B($30) // VDC MWR: Bit 4..5 - Virtual Screen Tile Width 128 (1024 Pixels) (%11) 2Bit/RW
98 | constant VDC_SCRH32($00) // VDC MWR: Bit 6 - Virtual Screen Tile Height 32 (256 Pixels) (%0) 1Bit/RW
99 | constant VDC_SCRH64($40) // VDC MWR: Bit 6 - Virtual Screen Tile Height 64 (512 Pixels) (%1) 1Bit/RW
100 | constant VDC_CM($80) // VDC MWR: Bit 7 - CM (Color Mode) 1Bit/RW
101 | // VDC MWR: Bit 8..15 - Unused 8Bit/RW
102 |
103 | // VDC Display Registers
104 | constant VDC_HSR($0A) // VDC HSR - Horizontal Synchronous Register 2B/RW
105 | constant VDC_HSW($1F) // VDC L HSR: Bit 0..4 - HSW (Horizontal Synchronous Pulse Width) 5Bit/RW
106 | // VDC L HSR: Bit 5..7 - Unused 3Bit/RW
107 | constant VDC_HDS($7F) // VDC H HSR: Bit 8..14 - HDS (Horizontal Display Starting Position) 7Bit/RW
108 | // VDC H HSR: Bit 15 - Unused 1Bit/RW
109 |
110 | constant VDC_HDR($0B) // VDC HDR - Horizontal Display Register 2B/RW
111 | constant VDC_HDW($7F) // VDC L HDR: Bit 0..6 - HDW (Horizontal Display Width) 7Bit/RW
112 | // VDC L HDR: Bit 7 - Unused 1Bit/RW
113 | constant VDC_HDE($7F) // VDC H HDR: Bit 8..14 - HDE (Horizontal Display End) 7Bit/RW
114 | // VDC H HDR: Bit 15 - Unused 1Bit/RW
115 |
116 | constant VDC_VSR($0C) // VDC VSR - Vertical Synchronous Register 2B/RW
117 | constant VDC_VSW($1F) // VDC L VSR: Bit 0..4 - VSW (Vertical Synchronous Pulse Width) 5Bit/RW
118 | // VDC L VSR: Bit 5..7 - Unused 3Bit/RW
119 | constant VDC_VDS($FF) // VDC H VSR: Bit 8..15 - VDS (Vertical Display Starting Position) 8Bit/RW
120 |
121 | constant VDC_VDR($0D) // VDC VDR - Vertical Display Register 2B/RW
122 | constant VDC_VCR($0E) // VDC VCR - Vertical Display Ending Postition Register 2B/RW
123 |
124 | // VDC DMA Registers
125 | constant VDC_DCR($0F) // VDC DCR - DMA Control Register 2B/RW
126 | constant VDC_DSC($01) // VDC DCR: Bit 0 - DSC VRAM & Sprite Attribute Table (Interrupt Enable/Disable) 1Bit/RW
127 | constant VDC_DVC($02) // VDC DCR: Bit 1 - DVC VRAM To VRAM Transfer (Interrupt Enable/Disable) 1Bit/RW
128 | constant VDC_SID($04) // VDC DCR: Bit 2 - SID VRAM To VRAM Source Increment/Decrement (1/0) 1Bit/RW
129 | constant VDC_DID($08) // VDC DCR: Bit 3 - DID VRAM To VRAM Destination Increment/Decrement (1/0) 1Bit/RW
130 | // VDC DCR: Bit 4 - Unused 1Bit/RW
131 | constant VDC_DSR($20) // VDC DCR: Bit 5 - DSR VRAM & Sprite Attribute Table Repetition (Enable/Disable) 1Bit/RW
132 | // VDC DCR: Bit 6..15 - Unused 10Bit/RW
133 |
134 | constant VDC_SOUR($10) // VDC SOUR - Source Address Register 2B/RW
135 | constant VDC_DESR($11) // VDC DESR - DMA Destination Address Register 2B/RW
136 | constant VDC_LENR($12) // VDC LENR - DMA Block Length Register 2B/RW
137 | constant VDC_SATB($13) // VDC SATB - Sprite Attribute Table Address Register 2B/RW
138 |
139 | // VCE Registers (HuC6260) (Mapped To Segment $FF:XXXX)
140 | constant VCE_CR($0400) // VCE CR - Control Register 2B/W
141 | constant VCE_PCC0($00) // VCE CR: Bit 0..1 - PCC 5.3693175 MHz (Pixel Clock Control) (%00) 2Bit/W
142 | constant VCE_PCC1($01) // VCE CR: Bit 0..1 - PCC 7.15909 MHz (Pixel Clock Control) (%01) 2Bit/W
143 | constant VCE_PCC2($02) // VCE CR: Bit 0..1 - PCC 10.738635 MHz (Pixel Clock Control) (%10) 2Bit/W
144 | constant VCE_PCC3($03) // VCE CR: Bit 0..1 - PCC 10.738635 MHz (Pixel Clock Control) (%11) 2Bit/W
145 | constant VCE_FC0($00) // VCE CR: Bit 2 - FC 262 Line Frame (Frame/Field Configuration) (%0) 1Bit/W
146 | constant VCE_FC1($04) // VCE CR: Bit 2 - FC 263 Line Frame (Frame/Field Configuration) (%1) 1Bit/W
147 | // VCE CR: Bit 3..6 - Unused 4Bit/W
148 | constant VCE_SC0($00) // VCE CR: Bit 7 - SC Colorburst Intact (Strip Colorburst) (%0) 1Bit/W
149 | constant VCE_SC1($08) // VCE CR: Bit 7 - SC Strip Colorburst (Strip Colorburst) (%1) 1Bit/W
150 | // VCE CR: Bit 8..15 - Unused 8Bit/W
151 |
152 | constant VCE_CTA($0402) // VCE CTA - Color Table Address Register 2B/W
153 | // VCE CTA: Bit 0..8 - Color Table Index (0..511) 9Bit/W
154 | // VCE CTA: Bit 9..15 - Unused 7Bit/W
155 |
156 | constant VCE_CTRW($0404) // VCE CTRW - Color Table Read/Write Register (BRG333) 2B/RW
157 | // VCE CTRW: Bit 0..2 - Blue 3Bit/RW
158 | // VCE CTRW: Bit 3..5 - Red 3Bit/RW
159 | // VCE CTRW: Bit 6..8 - Green 3Bit/RW
160 | // VCE CTRW: Bit 9..15 - Unused 7Bit/RW
161 |
162 | // PSG Registers (Mapped To Segment $FF:XXXX) (Write Only)
163 | constant PSG_R0($0800) // PSG Register 0 - Channel Select (Selects Channel For Use With PSG Registers R2..R9) 1B/W
164 | // PSG Register 0: Bit 0..2 - Channel Number (Only 0..5 Valid) 3Bit/W
165 | // PSG Register 0: Bit 3..7 - Unused 5Bit/W
166 |
167 | constant PSG_R1($0801) // PSG Register 1 - Global Sound Balance (Overall Sound Volume For Mixed Channels) 1B/W
168 | // PSG Register 1: Bit 0..3 - Volume From Right Output 4Bit/W
169 | // PSG Register 1: Bit 4..7 - Volume From Left Output 4Bit/W
170 |
171 | constant PSG_R2($0802) // PSG Register 2 - Fine Frequency Adjust (Lower 8-Bits Of 12-Bit Channel Frequency) 1B/W
172 | // PSG Register 2: Bit 0..7 - Fine Frequency Adjust 8Bit/W
173 |
174 | constant PSG_R3($0803) // PSG Register 3 - Rough Frequency Adjust (Upper 4-Bits Of 12-Bit Channel Frequency) 1B/W
175 | // PSG Register 3: Bit 0..3 - Rough Frequency Adjust 4Bit/W
176 | // PSG Register 3: Bit 4..7 - Unused 4Bit/W
177 |
178 | constant PSG_R4($0804) // PSG Register 4 - Channel Enable, DDA Enable, Channel Volume 1B/W
179 | // PSG Register 4: Bit 0..4 - Overall Channel Volume 5Bit/W
180 | // PSG Register 4: Bit 5 - Unused 1Bit/W
181 | constant PSG_DDA($40) // PSG Register 4: Bit 6 - DDA Output Enable/Disable (1/0) 1Bit/W
182 | constant PSG_CHAN($80) // PSG Register 4: Bit 7 - Channel Enable/Disable (1/0) 1Bit/W
183 |
184 | constant PSG_R5($0805) // PSG Register 5 - Channel Balance (Volume Balance Of An Individual Channel) 1B/W
185 | // PSG Register 5: Bit 0..3 - Volume To Right Output 4Bit/W
186 | // PSG Register 5: Bit 4..7 - Volume To Left Output 4Bit/W
187 |
188 | constant PSG_R6($0806) // PSG Register 6 - Channel Sound Data (5-Bit Unsigned Linear Sample Data) 1B/W
189 | // PSG Register 6: Bit 0..4 - 5-Bit Unsigned Linear Sample Data 5Bit/W
190 | // PSG Register 6: Bit 5..7 - Unused 3Bit/W
191 |
192 | constant PSG_R7($0807) // PSG Register 7 - Noise Enable, Noise Frequency (Only Effective For Channels 4 & 5) 1B/W
193 | // PSG Register 7: Bit 0..4 - Noise Frequency 5Bit/W
194 | // PSG Register 7: Bit 5..6 - Unused 2Bit/W
195 | constant PSG_NOISE($80) // PSG Register 7: Bit 7 - Noise Enable/Disable (1/0)
196 |
197 | constant PSG_R8($0808) // PSG Register 8 - LFO Frequency (Uses Channel 1 Waveform Buffer As Frequency Modulation) 1B/W
198 |
199 | constant PSG_R9($0809) // PSG Register 9 - LFO Trigger, LFO Control 1B/W
200 | constant PSG_LFO0($00) // PSG Register 9: Bit 0..1 - No Frequency Modulation Is Performed (LFO Control) %00 2Bit/W
201 | constant PSG_LFO1($01) // PSG Register 9: Bit 0..1 - FM Data Added To Channel 0 Frequency (LFO Control) %01 2Bit/W
202 | constant PSG_LFO2($02) // PSG Register 9: Bit 0..1 - FM Data << 4 Then Added To The Frequency (LFO Control) %10 2Bit/W
203 | constant PSG_LFO3($03) // PSG Register 9: Bit 0..1 - FM Data << 8 Then Added To The Frequency (LFO Control) %11 2Bit/W
204 | // PSG Register 9: Bit 2..6 - Unused 5Bit/W
205 | constant PSG_LFO($80) // PSG Register 9: Bit 7 - LFO Trigger Enable/Disable (0/1) 1Bit/W
206 |
207 | // 8-Bit I/O Port (Mapped To Segment $FF:XXXX)
208 | constant JOYIO($1000) // JOYIO - Joypad I/O Port Register 1B/R
209 | constant TRG1($01) // JOYIO: Bit 0 - Joypad Trigger 1 1Bit/R
210 | constant TRG2($02) // JOYIO: Bit 1 - Joypad Trigger 2 1Bit/R
211 | constant SEL($04) // JOYIO: Bit 2 - Joypad Select Button 1Bit/R
212 | constant RUN($08) // JOYIO: Bit 3 - Joypad Run Button 1Bit/R
213 | constant UP($10) // JOYIO: Bit 4 - Joypad Direction Up 1Bit/R
214 | constant RIGHT($20) // JOYIO: Bit 5 - Joypad Direction Right 1Bit/R
215 | constant DOWN($40) // JOYIO: Bit 6 - Joypad Direction Down 1Bit/R
216 | constant LEFT($80) // JOYIO: Bit 7 - Joypad Direction Left 1Bit/R
217 |
218 | // PC-Engine Initialisation
219 | macro PCE_INIT() {
220 | // VDC: Set VRAM Write Address To Zero
221 | st0 #VDC_MAWR // VDC: Set VDC Address To Memory Address Write Register (VRAM Write Address) (MAWR)
222 | st1 #0 // VDC: Data = 0 (Lo Byte)
223 | st2 #0 // VDC: Data = 0 (Hi Byte)
224 |
225 | // VDC: Clear 65536 VRAM Bytes To Zero
226 | st0 #VDC_VWR // VDC: Set VDC Address To VRAM Data Write Register (VWR)
227 | ldx #0
228 | ldy #128
229 | -
230 | st1 #0 // VDC: Data = 0 (Lo Byte)
231 | st2 #0 // VDC: Data = 0 (Hi Byte)
232 | dex
233 | bne -
234 | dey
235 | bne -
236 | }
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/VDC/HelloWorld/LIB/PCE_VECTOR.ASM:
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1 | //==================
2 | // PC-Engine VECTOR
3 | //==================
4 | seek($FFF6)
5 | // VECTOR (HuC6280 Mode)
6 | dw $0000 // IRQ2 VECTOR (BRK)
7 | dw $0000 // IRQ1 VECTOR (VDC)
8 | dw $0000 // TIMER VECTOR
9 | dw $0000 // NMI VECTOR
10 | dw Start // RESET VECTOR
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/VDC/HelloWorld/make.bat:
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1 | bass HelloWorld.asm
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