├── .gitignore
├── AppleIntelInfo.xcodeproj
    └── project.pbxproj
├── AppleIntelInfo
    ├── AppleIntelInfo-Info.plist
    ├── AppleIntelInfo-Prefix.pch
    ├── AppleIntelInfo.cpp
    ├── AppleIntelInfo.h
    ├── essentials.h
    └── intel_family.h
├── AppleIntelRegisterDumper
    ├── AppleIntelRegisterDumper.h
    ├── intel_chipset.h
    └── intel_reg.h
└── README.md


/.gitignore:
--------------------------------------------------------------------------------
1 | .DS_Store
2 | .git
3 | 
4 | xcuserdata
5 | project.xcworkspace
6 | 
7 | /AppleIntelInfo/AppleIntelInfo.xcodeproj/xcuserdata
8 | /AppleIntelInfo/AppleIntelInfo.xcodeproj/project.xcworkspace
9 | 


--------------------------------------------------------------------------------
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/AppleIntelInfo/AppleIntelInfo-Info.plist:
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41 | 			<key>logIPGStyle</key>
42 | 			<true/>
43 | 			<key>logIntelRegs</key>
44 | 			<false/>
45 | 			<key>logMSRs</key>
46 | 			<true/>
47 | 			<key>enableHWP</key>
48 | 			<false/>
49 | 		</dict>
50 | 	</dict>
51 | 	<key>NSHumanReadableCopyright</key>
52 | 	<string>Copyright © 2014-2017 Pike R. Alpha. All rights reserved.</string>
53 | 	<key>OSBundleLibraries</key>
54 | 	<dict>
55 | 		<key>com.apple.kpi.bsd</key>
56 | 		<string>10.4</string>
57 | 		<key>com.apple.kpi.iokit</key>
58 | 		<string>10.4</string>
59 | 		<key>com.apple.kpi.libkern</key>
60 | 		<string>10.4</string>
61 | 		<key>com.apple.kpi.mach</key>
62 | 		<string>10.4</string>
63 | 		<key>com.apple.kpi.unsupported</key>
64 | 		<string>10.5</string>
65 | 	</dict>
66 | 	<key>OSBundleRequired</key>
67 | 	<string>Root</string>
68 | </dict>
69 | </plist>
70 | 


--------------------------------------------------------------------------------
/AppleIntelInfo/AppleIntelInfo-Prefix.pch:
--------------------------------------------------------------------------------
1 | //
2 | //  Prefix header
3 | //
4 | //  The contents of this file are implicitly included at the beginning of every source file.
5 | //
6 | 
7 | 


--------------------------------------------------------------------------------
/AppleIntelInfo/AppleIntelInfo.cpp:
--------------------------------------------------------------------------------
   1 | /*
   2 |  * Copyright (c) 2012-2017 Pike R. Alpha. All rights reserved.
   3 |  *
   4 |  * Original idea and initial development of MSRDumper.kext (c) 2011 by RevoGirl.
   5 |  *
   6 |  * Thanks to George for his help and continuation of Sam's work, but it is
   7 |  * time for us to push the envelope and add some really interesting stuff.
   8 |  *
   9 |  * This work is licensed under the Creative Commons Attribution-NonCommercial
  10 |  * 4.0 Unported License => http://creativecommons.org/licenses/by-nc/4.0
  11 |  */
  12 | 
  13 | #include "AppleIntelInfo.h"
  14 | 
  15 | 
  16 | #if WRITE_LOG_REPORT
  17 | //==============================================================================
  18 | 
  19 | int AppleIntelInfo::writeReport(void)
  20 | {
  21 | 	int error = 0;
  22 | 	int length = (int)strlen(logBuffer);
  23 | 
  24 | 	struct vnode * vp;
  25 | 	
  26 | 	if (mCtx)
  27 | 	{
  28 | 		if ((error = vnode_open(FILE_PATH, (O_TRUNC | O_CREAT | FWRITE | O_NOFOLLOW), S_IRUSR | S_IWUSR, VNODE_LOOKUP_NOFOLLOW, &vp, mCtx)))
  29 | 		{
  30 | 			IOLOG("AppleIntelInfo.kext: Error, vnode_open(%s) failed with error %d!\n", FILE_PATH, error);
  31 | 		}
  32 | 		else
  33 | 		{
  34 | 			if ((error = vnode_isreg(vp)) == VREG)
  35 | 			{
  36 | 				if ((error = vn_rdwr(UIO_WRITE, vp, logBuffer, length, reportFileOffset, UIO_SYSSPACE, IO_NOCACHE|IO_NODELOCKED|IO_UNIT, vfs_context_ucred(mCtx), (int *) 0, vfs_context_proc(mCtx))))
  37 | 				{
  38 | 					IOLOG("AppleIntelInfo.kext: Error, vn_rdwr(%s) failed with error %d!\n", FILE_PATH, error);
  39 | 				}
  40 | 				else
  41 | 				{
  42 | 					reportFileOffset += length;
  43 | 				}
  44 | 			}
  45 | 			else
  46 | 			{
  47 | 				IOLOG("AppleIntelInfo.kext: Error, vnode_isreg(%s) failed with error %d!\n", FILE_PATH, error);
  48 | 			}
  49 | 		
  50 | 			if ((error = vnode_close(vp, FWASWRITTEN, mCtx)))
  51 | 			{
  52 | 				IOLOG("AppleIntelInfo.kext: Error, vnode_close() failed with error %d!\n", error);
  53 | 			}
  54 | 		}
  55 | 	}
  56 | 	else
  57 | 	{
  58 | 		IOLOG("AppleIntelInfo.kext: mCtx == NULL!\n");
  59 | 		error = 0xFFFF;
  60 | 	}
  61 | 	
  62 | 	return error;
  63 | }
  64 | #endif
  65 | 
  66 | 
  67 | #if REPORT_RAPL_MSRS
  68 | //==============================================================================
  69 | 
  70 | bool AppleIntelInfo::supportsRAPL(UInt16 aTargetRAPLFeature)
  71 | {
  72 | 	UInt16 supportedRAPLFeatures = 0;
  73 | 
  74 | 	switch (gCpuModel)
  75 | 	{
  76 | 		case INTEL_FAM6_SANDYBRIDGE:		// 0x2A
  77 | 		case INTEL_FAM6_IVYBRIDGE:			// 0x3A
  78 | 		case INTEL_FAM6_HASWELL_CORE:		// 0x3C
  79 | 		case INTEL_FAM6_HASWELL_ULT:		// 0x45
  80 | 		case INTEL_FAM6_HASWELL_GT3E:		// 0x46
  81 | 		case INTEL_FAM6_BROADWELL_CORE:		// 0x3D
  82 | 		case INTEL_FAM6_BROADWELL_GT3E:		// 0x47
  83 | 			supportedRAPLFeatures = (RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO);
  84 | 			break;
  85 | 
  86 | 		case INTEL_FAM6_SKYLAKE_MOBILE:		// 0x4E
  87 | 		case INTEL_FAM6_SKYLAKE_DESKTOP:	// 0x5E
  88 | 		case INTEL_FAM6_CANNONLAKE_CORE:	// 0x66
  89 | 		case INTEL_FAM6_KABYLAKE_MOBILE:	// 0x8E
  90 | 		case INTEL_FAM6_KABYLAKE_DESKTOP:	// 0x9E
  91 | 			supportedRAPLFeatures = (RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO);
  92 | 			break;
  93 | 
  94 | 		case INTEL_FAM6_HASWELL_X:			// 0x3F
  95 | 		case INTEL_FAM6_SKYLAKE_X:			// 0x55
  96 | 		case INTEL_FAM6_BROADWELL_X:		// 0x56
  97 | 		case INTEL_FAM6_BROADWELL_XEON_D:	// 0x56
  98 | 		case INTEL_FAM6_XEON_PHI_KNL:		// 0x57
  99 |         case INTEL_FAM6_XEON_PHI_KNM:		// 0x85
 100 | 			supportedRAPLFeatures = (RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO);
 101 | 			break;
 102 | 
 103 | 		case INTEL_FAM6_SANDYBRIDGE_X:		// 0x2D
 104 | 		case INTEL_FAM6_IVYBRIDGE_X:		// 0x3E
 105 | 			supportedRAPLFeatures = (RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO);
 106 | 			break;
 107 | 	}
 108 | 	
 109 | 	if (supportedRAPLFeatures & aTargetRAPLFeature)
 110 | 	{
 111 | 		return true;
 112 | 	}
 113 | 	
 114 | 	return false;
 115 | }
 116 | 
 117 | 
 118 | //==============================================================================
 119 | 
 120 | void AppleIntelInfo::reportRAPL(UInt16 aTargetRAPL)
 121 | {
 122 | 	unsigned int Y = 0;
 123 | 	unsigned int Z = 0;
 124 | 	unsigned long long msr = rdmsr64(MSR_RAPL_POWER_UNIT);
 125 | 
 126 | 	uint8_t power_unit = bitfield32(msr, 3, 0);
 127 | 	uint8_t energy_status_unit = bitfield32(msr, 12, 8);
 128 | 	uint8_t time_unit = bitfield32(msr, 19, 16);
 129 | 
 130 | 	float joulesPerEnergyUnit = 1. / float(1ULL << energy_status_unit);
 131 | 
 132 | 	switch(aTargetRAPL)
 133 | 	{
 134 | 		case RAPL_BASE:				/* 0x606 MSR_RAPL_POWER_UNIT */
 135 | 			IOLOG("\nMSR_RAPL_POWER_UNIT..............(0x606) : 0x%llX\n", msr);
 136 | 			
 137 | 			if (msr)
 138 | 			{
 139 | 				IOLOG("------------------------------------------\n");
 140 | 				IOLOG(" - Power Units.......................... : %u (1/%d Watt)\n", power_unit, (1 << power_unit));
 141 | 				IOLOG(" - Energy Status Units.................. : %u (%sJoules)\n", energy_status_unit, getUnitText(energy_status_unit));
 142 | 				IOLOG(" - Time Units .......................... : %u (%sSeconds)\n", time_unit, getUnitText(time_unit));
 143 | 			}
 144 | 
 145 | 			break;
 146 | 
 147 | 		case RAPL_PKG:					/* 0x610 MSR_PKG_POWER_LIMIT / 0x611 MSR_PKG_ENERGY_STATUS */
 148 | 			msr = rdmsr64(MSR_PKG_POWER_LIMIT);
 149 | 			
 150 | 			IOLOG("\nMSR_PKG_POWER_LIMIT..............(0x610) : 0x%llX\n", msr);
 151 | 			
 152 | 			if (msr)
 153 | 			{
 154 | 				IOLOG("------------------------------------------\n");
 155 | 				IOLOG(" - Package Power Limit #1............... : %llu Watt\n", (bitfield32(msr, 14, 0) >> power_unit));
 156 | 				IOLOG(" - Enable Power Limit #1................ : %s\n", bitfield32(msr, 15, 15) ? "1 (enabled)": "0 (disabled)");
 157 | 				IOLOG(" - Package Clamping Limitation #1....... : %s\n", bitfield32(msr, 16, 16) ? "1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)": "0 (disabled)");
 158 | 				
 159 | 				Y = bitfield32(msr, 21, 17);
 160 | 				Z = bitfield32(msr, 23, 22);
 161 | 				
 162 | 				IOLOG(" - Time Window for Power Limit #1....... : %llu (%u milli-Seconds)\n", bitfield32(msr, 23, 17), (unsigned int)(((1 << Y) * (1.0 + Z) / 4.0) * time_unit));
 163 | 				IOLOG(" - Package Power Limit #2............... : %llu Watt\n", (bitfield32(msr, 46, 32) >> power_unit));
 164 | 				IOLOG(" - Enable Power Limit #2................ : %s\n", (msr & (1UL << 47)) ? "1 (enabled)": "0 (disabled)");
 165 | 				IOLOG(" - Package Clamping Limitation #2....... : %s\n", (msr & (1UL << 48)) ? "1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)": "0 (disabled)");
 166 | 				
 167 | 				Y = bitfield32(msr, 53, 49);
 168 | 				Z = bitfield32(msr, 55, 54);
 169 | 				
 170 | 				IOLOG(" - Time Window for Power Limit #2....... : %llu (%u milli-Seconds)\n", bitfield32(msr, 55, 49), (unsigned int)(((1 << Y) * (1.0 + Z) / 4.0) * time_unit));
 171 | 				IOLOG(" - Lock................................. : %s\n", bitfield32(msr, 63, 63) ? "1 (MSR locked until next reset)": "0 (MSR not locked)");
 172 | 			}
 173 | 			
 174 | 			msr = rdmsr64(MSR_PKG_ENERGY_STATUS);
 175 | 			
 176 | 			IOLOG("\nMSR_PKG_ENERGY_STATUS............(0x611) : 0x%llX\n", msr);
 177 | 			
 178 | 			if (msr)
 179 | 			{
 180 | 				IOLOG("------------------------------------------\n");
 181 | 				IOLOG(" - Total Energy Consumed................ : %llu Joules (Watt = Joules / seconds)\n", (long long unsigned)(bitfield32(msr, 31, 0) * joulesPerEnergyUnit));
 182 | 			}
 183 | 
 184 | 			break;
 185 | 
 186 | 		case RAPL_PKG_PERF_STATUS:		/* 0x613 MSR_PKG_PERF_STATUS */
 187 | 			break;
 188 | 
 189 | 		case RAPL_PKG_POWER_INFO:		/* 0x614 MSR_PKG_POWER_INFO */
 190 | 			msr = rdmsr64(MSR_PKG_POWER_INFO);
 191 | 			
 192 | 			IOLOG("\nMSR_PKG_POWER_INFO...............(0x614) : 0x%llX\n", msr);
 193 | 			
 194 | 			if (msr)
 195 | 			{
 196 | 				IOLOG("------------------------------------------\n");
 197 | 				IOLOG(" - Thermal Spec Power................... : %llu Watt\n", (bitfield32(msr, 14, 0) >> power_unit));
 198 | 				IOLOG(" - Minimum Power........................ : %llu\n", (bitfield32(msr, 16, 30) >> power_unit));
 199 | 				IOLOG(" - Maximum Power........................ : %llu\n", (bitfield32(msr, 46, 32) >> power_unit));
 200 | 				IOLOG(" - Maximum Time Window.................. : %llu\n", (bitfield32(msr, 58, 48) >> time_unit));
 201 | 			}
 202 | 
 203 | 			break;
 204 | 
 205 | 		case RAPL_DRAM:				/* 0x618 MSR_DRAM_POWER_LIMIT / 0x619 MSR_DRAM_ENERGY_STATUS */
 206 | 			break;
 207 | 
 208 | 		case RAPL_DRAM_PERF_STATUS:	/* 0x61b MSR_DRAM_PERF_STATUS */
 209 | 			break;
 210 | 
 211 | 		case RAPL_DRAM_POWER_INFO:	/* 0x61c MSR_DRAM_POWER_INFO */
 212 | 			break;
 213 | 
 214 | 		case RAPL_CORES:			/* 0x638 MSR_PP0_POWER_LIMIT / 0x639 MSR_PP0_ENERGY_STATUS */
 215 | 			msr = rdmsr64(MSR_PP0_POWER_LIMIT);
 216 | 			
 217 | 			IOLOG("\nMSR_PP0_POWER_LIMIT..............(0x638) : 0x%llX\n", msr);
 218 | 			
 219 | 			if (msr)
 220 | 			{
 221 | 				IOLOG("------------------------------------------\n");
 222 | 				IOLOG(" - Power Limit.......................... : %llu Watt\n", (bitfield32(msr, 14, 0) >> power_unit));
 223 | 				IOLOG(" - Enable Power Limit................... : %s\n", (msr & (1UL << 15)) ? "1 (enabled)": "0 (disabled)");
 224 | 				IOLOG(" - Clamping Limitation.................. : %s\n", (msr & (1UL << 16)) ? "1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)": "0 (disabled)");
 225 | 				
 226 | 				Y = bitfield32(msr, 21, 17);
 227 | 				Z = bitfield32(msr, 23, 22);
 228 | 				
 229 | 				IOLOG(" - Time Window for Power Limit.......... : %llu (%u milli-Seconds)\n", bitfield32(msr, 23, 17), (unsigned int)(((1 << Y) * (1.0 + Z)) * time_unit));
 230 | 				IOLOG(" - Lock................................. : %s\n", bitfield32(msr, 31, 31) ? "1 (MSR locked until next reset)": "0 (MSR not locked)");
 231 | 			}
 232 | 			
 233 | 			msr = rdmsr64(MSR_PP0_ENERGY_STATUS);
 234 | 			
 235 | 			IOLOG("\nMSR_PP0_ENERGY_STATUS............(0x639) : 0x%llX\n", msr);
 236 | 			
 237 | 			if (msr)
 238 | 			{
 239 | 				IOLOG("------------------------------------------\n");
 240 | 				IOLOG(" - Total Energy Consumed................ : %llu Joules (Watt = Joules / seconds)\n", (long long unsigned)(bitfield32(msr, 31, 0) * joulesPerEnergyUnit));
 241 | 			}
 242 | 
 243 | 			break;
 244 | 
 245 | 		case RAPL_CORE_POLICY:		/* 0x63a MSR_PP0_POLICY */
 246 | 			if (gCpuModel == INTEL_FAM6_SANDYBRIDGE) // 0x2A - Intel 325462.pdf Vol.3C 35-120
 247 | 			{
 248 | 				msr = rdmsr64(MSR_PP0_POLICY);
 249 | 				
 250 | 				IOLOG("\nMSR_PP0_POLICY...................(0x63a) : 0x%llX\n", msr);
 251 | 				
 252 | 				if (msr)
 253 | 				{
 254 | 					IOLOG("------------------------------------------\n");
 255 | 					IOLOG(" - Priority Level....................... : %llu\n", bitfield32(msr, 4, 0));
 256 | 				}
 257 | 			}
 258 | 
 259 | 			break;
 260 | 
 261 | 		case RAPL_GFX:				/* 0x640 MSR_PP1_POWER_LIMIT / 0x641 MSR_PP1_ENERGY_STATUS /0x642 MSR_PP1_POLICY */
 262 | 			msr = rdmsr64(MSR_PP1_POWER_LIMIT);
 263 | 
 264 | 			IOLOG("\nMSR_PP1_POWER_LIMIT..............(0x640) : 0x%llX\n", msr);
 265 | 			
 266 | 			if (msr)
 267 | 			{
 268 | 				IOLOG("------------------------------------------\n");
 269 | 				IOLOG(" - Power Limit.......................... : %llu Watt\n", (bitfield32(msr, 14, 0) >> power_unit));
 270 | 				IOLOG(" - Enable Power Limit................... : %s\n", (msr & (1UL << 15)) ? "1 (enabled)": "0 (disabled)");
 271 | 				IOLOG(" - Clamping Limitation.................. : %s\n", (msr & (1UL << 16)) ? "1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)": "0 (disabled)");
 272 | 				
 273 | 				Y = bitfield32(msr, 21, 17);
 274 | 				Z = bitfield32(msr, 23, 22);
 275 | 				
 276 | 				IOLOG(" - Time Window for Power Limit.......... : %llu (%u milli-Seconds)\n", bitfield32(msr, 23, 17), (unsigned int)(((1 << Y) * (1.0 + Z)) * time_unit));
 277 | 				IOLOG(" - Lock................................. : %s\n", bitfield32(msr, 31, 31) ? "1 (MSR locked until next reset)": "0 (MSR not locked)");
 278 | 			}
 279 | 			
 280 | 			msr = rdmsr64(MSR_PP1_ENERGY_STATUS);
 281 | 			
 282 | 			IOLOG("\nMSR_PP1_ENERGY_STATUS............(0x641) : 0x%llX\n", msr);
 283 | 			
 284 | 			if (msr)
 285 | 			{
 286 | 				IOLOG("------------------------------------------\n");
 287 | 				IOLOG(" - Total Energy Consumed................ : %llu Joules (Watt = Joules / seconds)\n", (long long unsigned)(bitfield32(msr, 31, 0) * joulesPerEnergyUnit));
 288 | 			}
 289 | 			
 290 | 			msr = rdmsr64(MSR_PP1_POLICY);
 291 | 			
 292 | 			IOLOG("\nMSR_PP1_POLICY...................(0x642) : 0x%llX\n", msr);
 293 | 			
 294 | 			if (msr)
 295 | 			{
 296 | 				IOLOG("------------------------------------------\n");
 297 | 				IOLOG(" - Priority Level....................... : %llu\n", bitfield32(msr, 4, 0));
 298 | 			}
 299 | 
 300 | 			break;
 301 | 	}
 302 | }
 303 | #endif
 304 | 
 305 | 
 306 | #if (REPORT_MSRS && REPORT_HWP)
 307 | //==============================================================================
 308 | 
 309 | void AppleIntelInfo::reportHWP(void)
 310 | {
 311 | 	uint32_t cpuid_reg[4];
 312 | 	unsigned long long msr;
 313 | 
 314 | 	do_cpuid(0x00000006, cpuid_reg);
 315 | 
 316 | 	if ((cpuid_reg[eax] & 0x80) == 0x80)
 317 | 	{
 318 | 		msr = rdmsr64(IA32_PM_ENABLE);
 319 | 
 320 | 		if (msr & 1)
 321 | 		{
 322 | 			short mantissa	= 0;
 323 | 			short exponent	= 0;
 324 | 
 325 | 			switch (gCpuModel)
 326 | 			{
 327 | 				case INTEL_FAM6_SKYLAKE_MOBILE:
 328 | 				case INTEL_FAM6_SKYLAKE_DESKTOP:
 329 | 				case INTEL_FAM6_KABYLAKE_MOBILE:
 330 | 				case INTEL_FAM6_KABYLAKE_DESKTOP:
 331 | 					UInt64 pPerf = rdmsr64(IA32_PPERF);
 332 | 					UInt64 aPerf = rdmsr64(IA32_APERF);
 333 | 					float busy = ((pPerf * 100) / aPerf);
 334 | 					UInt8 multiplier = (UInt8)(((gClockRatio + 0.5) * busy) / 100);
 335 | 
 336 | 					IOLOG("MSR_PPERF........................(0x63E) : 0x%llX (%d)\n", msr, multiplier);
 337 | 					break;
 338 | 			}
 339 | 
 340 | 			IOLOG("\nIA32_PM_ENABLE...................(0x770) : 0x%llX (HWP Supported and Enabled)\n", msr);
 341 | 			
 342 | 			msr = rdmsr64(IA32_HWP_CAPABILITIES);
 343 | 
 344 | 			IOLOG("\nIA32_HWP_CAPABILITIES............(0x771) : 0x%llX\n", msr);
 345 | 			IOLOG("-----------------------------------------\n");
 346 | 			IOLOG(" - Highest Performance.................. : %llu\n", bitfield32(msr, 7, 0));
 347 | 			IOLOG(" - Guaranteed Performance............... : %llu\n", bitfield32(msr, 15, 8));
 348 | 			IOLOG(" - Most Efficient Performance........... : %llu\n", bitfield32(msr, 23, 16));
 349 | 			IOLOG(" - Lowest Performance................... : %llu\n", bitfield32(msr, 31, 24));
 350 | 
 351 | 			if ((cpuid_reg[eax] & 0x800) == 0x800)
 352 | 			{
 353 | 				msr = rdmsr64(IA32_HWP_REQUEST_PKG);
 354 | 				
 355 | 				IOLOG("\nIA32_HWP_REQUEST_PKG.............(0x772) : 0x%llX\n", msr);
 356 | 				IOLOG("-----------------------------------------\n");
 357 | 				IOLOG(" - Minimum Performance.................. : %llu\n", bitfield32(msr, 7, 0));
 358 | 				IOLOG(" - Maximum Performance.................. : %llu\n", bitfield32(msr, 15, 8));
 359 | 				IOLOG(" - Desired Performance.................. : %llu\n", bitfield32(msr, 23, 16));
 360 | 				IOLOG(" - Energy Efficient Performance......... : %llu\n", bitfield32(msr, 31, 24));
 361 | 
 362 | 				mantissa = bitfield32(msr, 38, 32);
 363 | 				exponent = bitfield32(msr, 41, 39);
 364 | 
 365 | 				IOLOG(" - Activity Window...................... : %d, %d\n", mantissa, exponent);
 366 | 			}
 367 | 			
 368 | 			if ((cpuid_reg[eax] & 0x100) == 0x100)
 369 | 			{
 370 | 				msr = rdmsr64(IA32_HWP_INTERRUPT);
 371 | 
 372 | 				IOLOG("\nIA32_HWP_INTERRUPT...............(0x773) : 0x%llX\n", msr);
 373 | 				IOLOG("------------------------------------------\n");
 374 | 				IOLOG(" - Guaranteed Performance Change........ : %s\n", (msr & 1) ? "1 (Interrupt generated on change of)": "0 (Interrupt generation disabled)");
 375 | 				IOLOG(" - Excursion Minimum.................... : %s\n", (msr & 2) ? "1 (Interrupt generated when unable to meet)": "0 (Interrupt generation disabled)");
 376 | 			}
 377 | 			
 378 | 			msr = rdmsr64(IA32_HWP_REQUEST);
 379 | 			
 380 | 			IOLOG("\nIA32_HWP_REQUEST................(0x774) : 0x%llX\n", msr);
 381 | 			IOLOG("-----------------------------------------\n");
 382 | 			IOLOG(" - Minimum Performance................. : %llu\n", bitfield32(msr, 7, 0));
 383 | 			IOLOG(" - Maximum Performance................. : %llu\n", bitfield32(msr, 15, 8));
 384 | 			IOLOG(" - Desired Performance................. : %llu\n", bitfield32(msr, 23, 16));
 385 | 			IOLOG(" - Energy Efficient Performance........ : %llu\n", bitfield32(msr, 31, 24));
 386 | 
 387 | 			if ((cpuid_reg[eax] & 0x200) == 0x200)
 388 | 			{
 389 | 				mantissa = bitfield32(msr, 38, 32);
 390 | 				exponent = bitfield32(msr, 41, 39);
 391 | 
 392 | 				IOLOG(" - Activity Window..................... : %d, %d\n", mantissa, exponent);
 393 | 			}
 394 | 
 395 | 			IOLOG(" - Package Control..................... : %s\n", (msr & 0x40000000000) ? "1 (control inputs to be derived from IA32_HWP_REQUEST_PKG)": "0");
 396 | 			
 397 | 			msr = rdmsr64(IA32_HWP_STATUS);
 398 | 
 399 | 			IOLOG("\nIA32_HWP_STATUS..................(0x777) : 0x%llX\n", msr);
 400 | 			IOLOG("-----------------------------------------\n");
 401 | 			IOLOG(" - Guaranteed Performance Change....... : %s\n", (msr & 1) ? "1 (has occured)" : "0 (has not occured)");
 402 | 			IOLOG(" - Excursion To Minimum................ : %s\n", (msr & 4) ? "1 (has occured)" : "0 (has not occured)");
 403 | 		}
 404 | 		else
 405 | 		{
 406 | 			IOLOG("\nIA32_PM_ENABLE...................(0x770) : 0x%llX (HWP Supported but not, yet, enabled)\n", msr);
 407 | 		}
 408 | 	}
 409 | }
 410 | #endif
 411 | 
 412 | 
 413 | #if (REPORT_MSRS && REPORT_HDC)
 414 | //==============================================================================
 415 | 
 416 | void AppleIntelInfo::reportHDC(void)
 417 | {
 418 | 	uint8_t index = 0;
 419 | 	unsigned long long msr;
 420 | 
 421 | 	IOLOG("HDC Supported\n");
 422 | 
 423 | 	msr = rdmsr64(IA32_PKG_HDC_CTL);
 424 | 
 425 | 	IOLOG("\nIA32_PKG_HDC_CTL.................(0xDB0) : 0x%llX\n", msr);
 426 | 
 427 | 	if (msr)
 428 | 	{
 429 | 		IOLOG("------------------------------------------\n");
 430 | 		IOLOG("HDC Pkg Enable...................(0x652) : %s\n", bitfield32(msr, 0, 0) ? "1 (HDC allowed)" : "0 (HDC not allowed)");
 431 | 	}
 432 | 
 433 | 	msr = rdmsr64(IA32_PM_CTL1);
 434 | 
 435 | 	IOLOG("\nIA32_PM_CTL1.....................(0xDB1) : 0x%llX\n", msr);
 436 | 	
 437 | 	if (msr)
 438 | 	{
 439 | 		IOLOG("------------------------------------------\n");
 440 | 		IOLOG("HDC Allow Block..................(0xDB1) : %s\n", bitfield32(msr, 0, 0) ? "1 (HDC blocked)" : "0 (HDC not blocked/allowed)");
 441 | 	}
 442 | 
 443 | 	msr = rdmsr64(IA32_THREAD_STALL);
 444 | 	
 445 | 	IOLOG("\nIA32_THREAD_STALL................(0xDB2) : 0x%llX\n", msr);
 446 | 	
 447 | 	if (msr)
 448 | 	{
 449 | 
 450 | 		IOLOG("------------------------------------------\n");
 451 | 		IOLOG("Stall Cycle Counter...............(0xDB2) : %llu, %s\n", msr, msr ? "1 (forced-idle supported)" : "0 (forced-idle not supported)");
 452 | 	}
 453 | 
 454 | 	msr = rdmsr64(MSR_PKG_HDC_CONFIG);
 455 | 	index = bitfield32(msr, 2, 0);
 456 | 
 457 | 	IOLOG("\nMSR_PKG_HDC_CONFIG...............(0x652) : 0x%llX\n", msr);
 458 | 
 459 | 	if (msr)
 460 | 	{
 461 | 		const char * cxCountText[5] = { "no-counting", "count package C2 only", "count package C3 and deeper", "count package C6 and deeper", "count package C7 and deeper" };
 462 | 
 463 | 		IOLOG("------------------------------------------\n");
 464 | 		IOLOG("Pkg Cx Monitor ..................(0x652) : %d (%s)", index, cxCountText[index]);
 465 | 	}
 466 | 	
 467 | 	msr = rdmsr64(MSR_CORE_HDC_RESIDENCY);
 468 | 
 469 | 	IOLOG("\nMSR_CORE_HDC_RESIDENCY...........(0x653) : 0x%llX\n", msr);
 470 | 	
 471 | 	if (msr)
 472 | 	{
 473 | 		IOLOG("------------------------------------------\n");
 474 | 		IOLOG("Core Cx Duty Cycle Count................ : %llu %s\n", msr, msr ? "(forced-idle cycle count)": "(not supported/no forced-idle serviced)");
 475 | 		
 476 | 	}
 477 | 	
 478 | 	msr = rdmsr64(MSR_PKG_HDC_SHALLOW_RESIDENCY);
 479 | 
 480 | 	IOLOG("\nMSR_PKG_HDC_SHALLOW_RESIDENCY....(0x655) : 0x%llX\n", msr);
 481 | 	
 482 | 	if (msr)
 483 | 	{
 484 | 
 485 | 		IOLOG("------------------------------------------\n");
 486 | 		IOLOG("Pkg C2 Duty Cycle Count................. : %llu %s\n", msr, msr ? "(forced-idle cycle count)": "(not supported/no forced-idle serviced)");
 487 | 		
 488 | 	}
 489 | 	
 490 | 	msr = rdmsr64(MSR_PKG_HDC_DEEP_RESIDENCY);
 491 | 
 492 | 	IOLOG("\nMSR_PKG_HDC_DEEP_RESIDENCY.......(0x656) : 0x%llX\n", msr);
 493 | 	
 494 | 	if (msr)
 495 | 	{
 496 | 		const char * cxText[5] = { "x", "2", "3", "6", "7" };
 497 | 
 498 | 		IOLOG("------------------------------------------\n");
 499 | 		IOLOG("Pkg C%s Duty Cycle Count................ : %llu %s\n", cxText[index], msr, msr ? "(forced-idle cycle count)": "(not supported/no forced-idle serviced)");
 500 | 		
 501 | 	}
 502 | }
 503 | #endif
 504 | 
 505 | 
 506 | //==============================================================================
 507 | 
 508 | uint32_t AppleIntelInfo::getBusFrequency(void)
 509 | {
 510 | 	size_t size = 4;
 511 | 	uint32_t frequency = 0;
 512 | 
 513 | 	switch (gCpuModel)
 514 | 	{
 515 | 		case INTEL_FAM6_NEHALEM:
 516 |  		case INTEL_FAM6_NEHALEM_EP:
 517 |    		case INTEL_FAM6_NEHALEM_EX:
 518 | 		case INTEL_FAM6_WESTMERE:
 519 | 		case INTEL_FAM6_WESTMERE_EP:
 520 | 		case INTEL_FAM6_WESTMERE_EX:
 521 | 			return (133 * 1000000);
 522 | 			break;
 523 | 
 524 | 		default:
 525 | 			// Check sysctl hw.busfrequency to see if the setup is right or wrong.
 526 | 			if (sysctlbyname("hw.busfrequency", &frequency, &size, NULL, 0) == 0)
 527 | 			{
 528 | 				// Is it 100000000?
 529 | 				if ((frequency / 1000000) > 100)
 530 | 				{
 531 | 					// No. Log warning.
 532 | 					IOLOG("\nWarning: Clover hw.busfrequency error detected : %x\n", frequency);
 533 | 				}
 534 | 			}
 535 | 
 536 | 			return (100 * 1000000);
 537 | 			break;
 538 | 	}
 539 | 	return 0;
 540 | }
 541 | 
 542 | 
 543 | //==============================================================================
 544 | 
 545 | const char * AppleIntelInfo::getUnitText(uint8_t unit)
 546 | {
 547 | 	const char * milliText[10] = { "1 ", "500 milli-", "250 milli-", "125 milli-", "62.5 milli-", "31.2 milli-", "15.6 milli-", "7.8 milli-", "3.9 milli-", "2 milli-" };
 548 | 	const char * microText[7] = { "976.6 micro-", "488.3 micro-", "244.1 micro-", "122.1 micro-", "61 micro-", "30.5 micro-", "15.3 micro-" };
 549 | 
 550 | 	if (unit <= 9)
 551 | 	{
 552 | 		return milliText[unit];
 553 | 	}
 554 | 	else
 555 | 	{
 556 | 		return microText[unit-10];
 557 | 	}
 558 | 
 559 | 	return NULL;
 560 | }
 561 | 
 562 | 
 563 | #if REPORT_MSRS
 564 | //==============================================================================
 565 | 
 566 | bool AppleIntelInfo::hasCPUFeature(long targetCPUFeature)
 567 | {
 568 | 	uint32_t cpuid_reg[4];
 569 | 	do_cpuid(0x00000001, cpuid_reg);
 570 | 	
 571 | 	uint64_t cpuFeatures = cpuid_reg[ecx];
 572 | 	cpuFeatures = (cpuFeatures << 32) | cpuid_reg[eax];
 573 | 
 574 | 	if (cpuFeatures & targetCPUFeature)
 575 | 	{
 576 | 		return true;
 577 | 	}
 578 | 	
 579 | 	return false;
 580 | }
 581 | #endif
 582 | 
 583 | 
 584 | #if REPORT_MSRS
 585 | //==============================================================================
 586 | 
 587 | void AppleIntelInfo::reportMSRs(void)
 588 | {
 589 | 	uint8_t core_limit;
 590 | 	uint32_t performanceState;
 591 | 	uint32_t cpuid_reg[4];
 592 | 	uint64_t msr;
 593 | 
 594 | 	char brandstring[48];
 595 | 
 596 | 	do_cpuid(0x80000002, cpuid_reg);	// First 16 bytes.
 597 | 	bcopy((char *)cpuid_reg, &brandstring[0], 16);
 598 |  
 599 | 	do_cpuid(0x80000003, cpuid_reg);	// Next 16 bytes.
 600 | 	bcopy((char *)cpuid_reg, &brandstring[16], 16);
 601 | 	
 602 | 	do_cpuid(0x80000004, cpuid_reg);	// Last 16 bytes.
 603 | 	bcopy((char *)cpuid_reg, &brandstring[32], 16);
 604 | 	
 605 | 	IOLOG("\nProcessor Brandstring....................: %s\n", brandstring);
 606 | 
 607 | 	do_cpuid(0x00000001, cpuid_reg);
 608 | 	uint8_t model = (bitfield32(cpuid_reg[eax], 19, 16) << 4) + bitfield32(cpuid_reg[eax],  7,  4);
 609 | 
 610 | 	IOLOG("\nProcessor Signature..................... : 0x%X\n", cpuid_reg[eax]);
 611 | 	IOLOG("------------------------------------------\n");
 612 | 	IOLOG(" - Family............................... : %lu\n", bitfield32(cpuid_reg[eax], 11,  8));
 613 | 	IOLOG(" - Stepping............................. : %lu\n", bitfield32(cpuid_reg[eax],  3,  0));
 614 | 	IOLOG(" - Model................................ : 0x%X (%d)\n", model, model);
 615 | 
 616 | 	do_cpuid(0x00000006, cpuid_reg);
 617 | 
 618 | 	IOLOG("\nModel Specific Registers (MSRs)\n------------------------------------------\n");
 619 |     
 620 | 	msr = rdmsr64(MSR_IA32_PLATFORM_ID);
 621 |     
 622 | 	IOLOG("\nMSR_IA32_PLATFORM_ID.............(0x17)  : 0x%llX\n", msr);
 623 | 	IOLOG("------------------------------------------\n");
 624 |     IOLOG(" - Processor Flags...................... : %d\n", (uint8_t)bitfield32(msr, 52, 50));
 625 |     
 626 | 	msr = rdmsr64(MSR_CORE_THREAD_COUNT);
 627 |     
 628 | 	IOLOG("\nMSR_CORE_THREAD_COUNT............(0x35)  : 0x%llX\n", msr);
 629 | 	IOLOG("------------------------------------------\n");
 630 | 	IOLOG(" - Core Count........................... : %d\n", gCoreCount);
 631 | 	IOLOG(" - Thread Count......................... : %d\n", gThreadCount);
 632 | 
 633 | 	msr = rdmsr64(MSR_PLATFORM_INFO);
 634 | 	performanceState = bitfield32(msr, 15, 8);
 635 | 
 636 | 	IOLOG("\nMSR_PLATFORM_INFO................(0xCE)  : 0x%llX\n", msr);
 637 | 	IOLOG("------------------------------------------\n");
 638 | 	IOLOG(" - Maximum Non-Turbo Ratio.............. : 0x%X (%u MHz)\n", performanceState, (performanceState * gBclk));
 639 | 	IOLOG(" - Ratio Limit for Turbo Mode........... : %s\n", (msr & (1 << 28)) ? "1 (programmable)" : "0 (not programmable)");
 640 | 	IOLOG(" - TDP Limit for Turbo Mode............. : %s\n", (msr & (1 << 29)) ? "1 (programmable)" : "0 (not programmable)");
 641 | 	IOLOG(" - Low Power Mode Support............... : %s\n", (msr & (1UL << 32)) ? "1 (LPM supported)": "0 (LMP not supported)");
 642 | 
 643 | 	if (bitfield32(msr, 34, 33) == 0)
 644 | 	{
 645 | 		IOLOG(" - Number of ConfigTDP Levels........... : 0 (only base TDP level available)\n");
 646 | 	}
 647 | 	else
 648 | 	{
 649 | 		IOLOG(" - Number of ConfigTDP Levels........... : %llu (additional TDP level(s) available)\n", bitfield32(msr, 34, 33));
 650 | 	}
 651 | 
 652 | 	IOLOG(" - Maximum Efficiency Ratio............. : %llu\n", bitfield32(msr, 47, 40));
 653 | 	
 654 | 	if (bitfield32(msr, 55, 48) > 0)
 655 | 	{
 656 | 		IOLOG(" - Minimum Operating Ratio.............. : %llu\n", bitfield32(msr, 55, 48));
 657 | 	}
 658 | 
 659 | 	UInt64 msr_pmg_cst_config_control = rdmsr64(MSR_PKG_CST_CONFIG_CONTROL);
 660 | 
 661 | 	IOLOG("\nMSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x%llX\n", msr_pmg_cst_config_control);
 662 | 	IOLOG("------------------------------------------\n");
 663 | 	IOLOG(" - I/O MWAIT Redirection Enable......... : %s\n", (msr_pmg_cst_config_control & (1 << 10)) ? "1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)" : "0 (not enabled)");
 664 | 	IOLOG(" - CFG Lock............................. : %s\n", (msr_pmg_cst_config_control & (1 << 15)) ? "1 (MSR locked until next reset)" : "0 (MSR not locked)");
 665 | 
 666 | 	IOLOG(" - C3 State Auto Demotion............... : %s\n", (msr_pmg_cst_config_control & (1 << 25)) ? "1 (enabled)" : "0 (disabled/unsupported)");
 667 | 	IOLOG(" - C1 State Auto Demotion............... : %s\n", (msr_pmg_cst_config_control & (1 << 26)) ? "1 (enabled)" : "0 (disabled/unsupported)");
 668 | 
 669 | 	IOLOG(" - C3 State Undemotion.................. : %s\n", (msr_pmg_cst_config_control & (1 << 27)) ? "1 (enabled)" : "0 (disabled/unsupported)");
 670 | 	IOLOG(" - C1 State Undemotion.................. : %s\n", (msr_pmg_cst_config_control & (1 << 28)) ? "1 (enabled)" : "0 (disabled/unsupported)");
 671 | 
 672 | 	// Intel® CoreTM M Processors and 5th Generation Intel® CoreTM Processors
 673 | 	// Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture
 674 | 	IOLOG(" - Package C-State Auto Demotion........ : %s\n", (msr_pmg_cst_config_control & (1 << 29)) ? "1 (enabled)" : "0 (disabled/unsupported)");
 675 | 	IOLOG(" - Package C-State Undemotion........... : %s\n", (msr_pmg_cst_config_control & (1 << 30)) ? "1 (enabled)" : "0 (disabled/unsupported)");
 676 | 
 677 | 	msr = rdmsr64(MSR_PMG_IO_CAPTURE_BASE);
 678 | 
 679 | 	IOLOG("\nMSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x%llX\n", msr);
 680 | 
 681 | 	if (msr)
 682 | 	{
 683 | 		IOLOG("------------------------------------------\n");
 684 | 		IOLOG(" - LVL_2 Base Address................... : 0x%llx\n", bitfield32(msr, 15, 0));
 685 | 	}
 686 | 
 687 | 	if (msr_pmg_cst_config_control & (1 << 10))
 688 | 	{
 689 | 		switch(bitfield32(msr, 18, 16))
 690 | 		{
 691 | 			case 0: IOLOG(" - C-state Range........................ : %llu (%s)\n", bitfield32(msr, 18, 16), "C3 is the max C-State to include");
 692 | 				break;
 693 | 
 694 | 			case 1: IOLOG(" - C-state Range........................ : %llu (%s)\n", bitfield32(msr, 18, 16), "C6 is the max C-State to include");
 695 | 				break;
 696 | 
 697 | 			case 2: IOLOG(" - C-state Range........................ : %llu (%s)\n", bitfield32(msr, 18, 16), "C7 is the max C-State to include");
 698 | 				break;
 699 | 		}
 700 | 	}
 701 | 	else
 702 | 	{
 703 | 		IOLOG(" - C-state Range........................ : %llu (%s)\n", bitfield32(msr, 18, 16), "C-States not included, I/O MWAIT redirection not enabled");
 704 | 	}
 705 | 
 706 | 	if (bitfield32(cpuid_reg[ecx], 0, 0) == 1) // Are APERF and MPERF supported?
 707 | 	{
 708 | 		IOLOG("\nIA32_MPERF.......................(0xE7)  : 0x%llX\n", (unsigned long long)rdmsr64(IA32_MPERF));
 709 | 	
 710 | 		UInt64 aPerf = rdmsr64(IA32_APERF);
 711 | 
 712 | 		IOLOG("IA32_APERF.......................(0xE8)  : 0x%llX\n", aPerf);
 713 | 	}
 714 | 
 715 | 	if (gCpuModel == INTEL_FAM6_BROADWELL_X)
 716 | 	{
 717 | 		IOLOG("MSR_0x150........................(0x150) : 0x%llX\n", (unsigned long long)rdmsr64(0x150));
 718 | 	}
 719 | 
 720 | 	IOLOG("\nMSR_FLEX_RATIO...................(0x194) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_FLEX_RATIO));
 721 | 
 722 | 	if (msr)
 723 | 	{
 724 | 		IOLOG("------------------------------------------\n");
 725 | 	}
 726 | 
 727 | 	msr = rdmsr64(MSR_IA32_PERF_STATUS);
 728 | 	performanceState = bitfield32(msr, 15, 0);
 729 | 
 730 | 	IOLOG("\nMSR_IA32_PERF_STATUS.............(0x198) : 0x%llX\n", msr);
 731 | 
 732 | 	if (msr)
 733 | 	{
 734 | 		IOLOG("------------------------------------------\n");
 735 | 		IOLOG(" - Current Performance State Value...... : 0x%X (%u MHz)\n", performanceState, ((performanceState >> 8) * gBclk));
 736 | 	}
 737 | 
 738 | 	msr = rdmsr64(MSR_IA32_PERF_CONTROL);
 739 | 	performanceState = bitfield32(msr, 15, 0);
 740 | 
 741 | 	IOLOG("\nMSR_IA32_PERF_CONTROL............(0x199) : 0x%llX\n", msr);
 742 | 
 743 | 	if (msr)
 744 | 	{
 745 | 		IOLOG("------------------------------------------\n");
 746 | 		IOLOG(" - Target performance State Value....... : 0x%X (%u MHz)\n", performanceState, ((performanceState >> 8) * gBclk));
 747 | 	}
 748 | 
 749 | 	if (cpuid_reg[eax] & (1 << 0))
 750 | 	{
 751 | 		IOLOG(" - Intel Dynamic Acceleration........... : %s\n", (msr & (1UL << 32)) ? "1 (IDA disengaged)" : "0 (IDA engaged)");
 752 | 	}
 753 | 
 754 | 	do_cpuid(0x00000001, cpuid_reg);
 755 | 
 756 | 	if (bitfield32(cpuid_reg[edx], 22, 22) == 1)
 757 | 	{
 758 | 		IOLOG("\nIA32_CLOCK_MODULATION............(0x19A) : 0x%llX\n", (unsigned long long)rdmsr64(IA32_CLOCK_MODULATION));
 759 | 
 760 | 		msr = rdmsr64(IA32_THERM_INTERRUPT);
 761 | 
 762 | 		IOLOG("\nIA32_THERM_INTERRUPT.............(0x19B) : 0x%llX\n", msr);
 763 | 
 764 | 		if (msr)
 765 | 		{
 766 | 			IOLOG("------------------------------------------\n");
 767 | 			IOLOG(" - High-Temperature Interrupt Enable.... : %s\n", (msr & (1 <<  0)) ? "1 (enabled)" : "0 (disabled)");
 768 | 			IOLOG(" - Low-Temperature Interrupt Enable..... : %s\n", (msr & (1 <<  1)) ? "1 (enabled)" : "0 (disabled)");
 769 | 			IOLOG(" - PROCHOT# Interrupt Enable............ : %s\n", (msr & (1 <<  2)) ? "1 (enabled)" : "0 (disabled)");
 770 | 			IOLOG(" - FORCEPR# Interrupt Enable............ : %s\n", (msr & (1 <<  3)) ? "1 (enabled)" : "0 (disabled)");
 771 | 			IOLOG(" - Critical Temperature Interrupt Enable : %s\n", (msr & (1 <<  4)) ? "1 (enabled)" : "0 (disabled)");
 772 | 			// bit 7:5 Reserved.
 773 | 			IOLOG(" - Threshold #1 Value................... : %llu\n", bitfield32(msr, 14, 8));
 774 | 			IOLOG(" - Threshold #1 Interrupt Enable........ : %s\n", (msr & (1 << 15)) ? "1 (enabled)" : "0 (disabled)");
 775 | 			IOLOG(" - Threshold #2 Value................... : %llu\n", bitfield32(msr, 22, 16));
 776 | 			IOLOG(" - Threshold #2 Interrupt Enable........ : %s\n", (msr & (1 << 23)) ? "1 (enabled)" : "0 (disabled)");
 777 | 			IOLOG(" - Power Limit Notification Enable...... : %s\n", (msr & (1 << 24)) ? "1 (enabled)" : "0 (disabled)");
 778 | 			// bit 63:25 Reserved.
 779 | 		}
 780 | 
 781 | 		msr = rdmsr64(IA32_THERM_STATUS);
 782 | 
 783 | 		IOLOG("\nIA32_THERM_STATUS................(0x19C) : 0x%llX\n", msr);
 784 | 
 785 | 		if (msr)
 786 | 		{
 787 | 			IOLOG("------------------------------------------\n");
 788 | 			IOLOG(" - Thermal Status....................... : %s\n", (msr & (1 <<  0)) ? "1" : "0");
 789 | 			IOLOG(" - Thermal Log.......................... : %s\n", (msr & (1 <<  1)) ? "1" : "0");
 790 | 			IOLOG(" - PROCHOT # or FORCEPR# event.......... : %s\n", (msr & (1 <<  2)) ? "1" : "0");
 791 | 			IOLOG(" - PROCHOT # or FORCEPR# log............ : %s\n", (msr & (1 <<  3)) ? "1" : "0");
 792 | 			IOLOG(" - Critical Temperature Status.......... : %s\n", (msr & (1 <<  4)) ? "1" : "0");
 793 | 			IOLOG(" - Critical Temperature log............. : %s\n", (msr & (1 <<  5)) ? "1" : "0");
 794 | 			IOLOG(" - Thermal Threshold #1 Status.......... : %s\n", (msr & (1 <<  6)) ? "1" : "0");
 795 | 			IOLOG(" - Thermal Threshold #1 log............. : %s\n", (msr & (1 <<  7)) ? "1" : "0");
 796 | 			IOLOG(" - Thermal Threshold #2 Status.......... : %s\n", (msr & (1 <<  8)) ? "1" : "0");
 797 | 			IOLOG(" - Thermal Threshold #2 log............. : %s\n", (msr & (1 <<  9)) ? "1" : "0");
 798 | 			IOLOG(" - Power Limitation Status.............. : %s\n", (msr & (1 << 10)) ? "1" : "0");
 799 | 			IOLOG(" - Power Limitation log................. : %s\n", (msr & (1 << 11)) ? "1" : "0");
 800 | 			IOLOG(" - Current Limit Status................. : %s\n", (msr & (1 << 12)) ? "1" : "0");
 801 | 			IOLOG(" - Current Limit log.................... : %s\n", (msr & (1 << 13)) ? "1" : "0");
 802 | 			IOLOG(" - Cross Domain Limit Status............ : %s\n", (msr & (1 << 14)) ? "1" : "0");
 803 | 			IOLOG(" - Cross Domain Limit log............... : %s\n", (msr & (1 << 15)) ? "1" : "0");
 804 | 			IOLOG(" - Digital Readout...................... : %llu\n", bitfield32(msr, 22, 16));
 805 | 			// bit 23-26 Reserved.
 806 | 			IOLOG(" - Resolution in Degrees Celsius........ : %llu\n", bitfield32(msr, 30, 27));
 807 | 			IOLOG(" - Reading Valid........................ : %s\n", (msr & (1 << 31)) ? "1 (valid)" : "0 (invalid)");
 808 | 			// bit 63-32 Reserved.
 809 | 		}
 810 | 	}
 811 | 
 812 | 	if (hasCPUFeature(CPUID_FEATURE_TM2))
 813 | 	{
 814 | 		msr = rdmsr64(MSR_THERM2_CTL);
 815 | 
 816 | 		IOLOG("\nMSR_THERM2_CTL...................(0x19D) : 0x%llX\n", msr);
 817 | 
 818 | 		if (msr)
 819 | 		{
 820 | 			IOLOG("------------------------------------------\n");
 821 | 			IOLOG(" - Thermal Monitor Selection (TM1/TM2).. : %s\n", (msr & (1 << 16)) ? "1 (TM1 thermally-initiated on-die modulation of the stop-clock duty cycle)" : "0 (TM2 thermally-initiated frequency transitions)");
 822 | 		}
 823 | 	}
 824 | 
 825 | 	msr = rdmsr64(IA32_MISC_ENABLES);
 826 | 
 827 | 	IOLOG("\nIA32_MISC_ENABLES................(0x1A0) : 0x%llX\n", msr);
 828 | 
 829 | 	if (msr)
 830 | 	{
 831 | 		IOLOG("------------------------------------------\n");
 832 | 		IOLOG(" - Fast-Strings......................... : %s\n", (msr & (1 <<  0)) ? "1 (enabled)" : "0 (disabled)");
 833 | 		// bit 2:1 Reserved.
 834 | 		IOLOG(" - FOPCODE compatibility mode Enable.... : %llu\n", (msr & (1 <<  2)));
 835 | 		IOLOG(" - Automatic Thermal Control Circuit.... : %s\n", (msr & (1 <<  3)) ? "1 (enabled)" : "0 (disabled)");
 836 | 		// bit 6:4 Reserved.
 837 | 		IOLOG(" - Split-lock Disable................... : %llu\n", (msr & (1 <<  4)));
 838 | 		IOLOG(" - Performance Monitoring............... : %s\n", (msr & (1 <<  7)) ? "1 (available)" : "not available");
 839 | 		// bit 8 Reserved.
 840 | 		IOLOG(" - Bus Lock On Cache Line Splits Disable : %llu\n", (msr & (1 <<  8)));
 841 | 		IOLOG(" - Hardware prefetch Disable............ : %llu\n", (msr & (1 <<  9)));
 842 | 
 843 | 		IOLOG(" - Processor Event Based Sampling....... : %s\n", (msr & (1 << 12)) ? "1 (PEBS not supported)" : "0 (PEBS supported)");
 844 | 		IOLOG(" - GV1/2 legacy Enable.................. : %llu\n", (msr & (1 << 15)));
 845 | 		IOLOG(" - Enhanced Intel SpeedStep Technology.. : %s\n", (msr & (1 << 16)) ? "1 (enabled)" : "0 (disabled)");
 846 | 		IOLOG(" - MONITOR FSM.......................... : %s\n", (msr & (1 << 18)) ? "1 (MONITOR/MWAIT supported)" : "0 (MONITOR/MWAIT not supported)");
 847 | 		IOLOG(" - Adjacent sector prefetch Disable..... : %llu\n", (msr & (1 << 19)));
 848 | 		IOLOG(" - CFG Lock............................. : %s\n", (msr & (1 << 20)) ? "1 (MSR locked until next reset)" : "0 (MSR not locked)");
 849 | 		IOLOG(" - xTPR Message Disable................. : %s\n", (msr & (1 << 23)) ? "1 (disabled)" : "0 (enabled)");
 850 | 
 851 | 	}
 852 | 
 853 | 	msr = rdmsr64(MSR_TEMPERATURE_TARGET);
 854 | 	uint8_t time_unit = bitfield32(msr, 6, 0);
 855 | 
 856 | 	IOLOG("\nMSR_TEMPERATURE_TARGET...........(0x1A2) : 0x%llX\n", msr);
 857 | 	
 858 | 	if (msr)
 859 | 	{
 860 | 		char timeString[25];
 861 | 		memset(timeString, 0, 25);
 862 | 		IOLOG("------------------------------------------\n");
 863 | 
 864 | 		if (time_unit)
 865 | 		{
 866 | 			snprintf(timeString, 25, "(%sSeconds)", getUnitText(time_unit));
 867 | 		}
 868 | 
 869 | 		IOLOG(" - Turbo Attenuation Units.............. : %u %s\n", time_unit, timeString);
 870 | 		IOLOG(" - Temperature Target................... : %llu\n", bitfield32(msr, 23, 16));
 871 | 		IOLOG(" - TCC Activation Offset................ : %llu\n", bitfield32(msr, 29, 24));
 872 | 	}
 873 | 
 874 | 	msr = rdmsr64(MSR_MISC_PWR_MGMT);
 875 | 
 876 | 	IOLOG("\nMSR_MISC_PWR_MGMT................(0x1AA) : 0x%llX\n", msr);
 877 | 
 878 | 	if (msr)
 879 | 	{
 880 | 		IOLOG("------------------------------------------\n");
 881 | 		IOLOG(" - EIST Hardware Coordination........... : %s\n", (msr & (1 <<  0)) ? "1 (hardware coordination disabled)" : "0 (hardware coordination enabled)");
 882 | 
 883 | 		IOLOG(" - Energy/Performance Bias support...... : %lu\n", bitfield32(cpuid_reg[ecx],  3,  3) );
 884 | 		IOLOG(" - Energy/Performance Bias.............. : %s\n", (msr & (1 <<  1)) ? "1 (enabled/MSR visible to software)" : "0 (disabled/MSR not visible to software)");
 885 | 		
 886 | 		IOLOG(" - Thermal Interrupt Coordination Enable : %s\n", (msr & (1 << 22)) ? "1 (thermal interrupt routed to all cores)" : "0 (thermal interrupt not rerouted)");
 887 | 		
 888 | 		/* HWP related SpeedShift settings */
 889 | 		IOLOG(" - SpeedShift Technology Enable......... : %s\n", (msr & (1 <<  6)) ? "1 (enabled)" : "0 (disabled)");
 890 | 		IOLOG(" - SpeedShift Interrupt Coordination.... : %s\n", (msr & (1 <<  7)) ? "1 (enabled)" : "0 (disabled)");
 891 | 		IOLOG(" - SpeedShift Energy Efficient Perf..... : %s\n", (msr & (1 << 12)) ? "1 (enabled)" : "0 (disabled)");
 892 | 		IOLOG(" - SpeedShift Technology Setup for HWP.. : %s\n", (msr & 0x10c0) ? "Yes (setup for HWP)" : "No (not setup for HWP)");
 893 | 	}
 894 | 
 895 | 	msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);
 896 | 
 897 | 	IOLOG("\nMSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x%llX\n", msr);
 898 | 	IOLOG("------------------------------------------\n");
 899 | 
 900 | 	for (int i = 1; (i < 9) && (i <= gCoreCount); i++)
 901 | 	{
 902 | 		core_limit = bitfield32(msr, 7, 0);
 903 | 		
 904 | 		if (core_limit)
 905 | 		{
 906 | 			IOLOG(" - Maximum Ratio Limit for C%02d.......... : %X (%u MHz) %s\n", i, core_limit, (core_limit * gBclk), ((i > gCoreCount) && core_limit) ? "(garbage / unused)" : "");
 907 | 
 908 | 			msr = (msr >> 8);
 909 | 		}
 910 | 	}
 911 | 	//
 912 | 	// Intel® Xeon® Processor E5 v3 Family
 913 | 	//
 914 | 	if (gCoreCount > 8)
 915 | 	{
 916 | 		msr = rdmsr64(MSR_TURBO_RATIO_LIMIT1);
 917 | 	
 918 | 		IOLOG("\nMSR_TURBO_RATIO_LIMIT1...........(0x1AE) : 0x%llX\n", msr);
 919 | 		IOLOG("------------------------------------------\n");
 920 | 	
 921 | 		for (int i = 9; (i < 17) && (i <= gCoreCount); i++)
 922 | 		{
 923 | 			core_limit = bitfield32(msr, 7, 0);
 924 | 		
 925 | 			if (core_limit)
 926 | 			{
 927 | 				IOLOG(" - Maximum Ratio Limit for C%02d.......... : %X (%u MHz) %s\n", i, core_limit, (core_limit * gBclk), ((i > gCoreCount) && core_limit) ? "(garbage / unused)" : "");
 928 | 		
 929 | 				msr = (msr >> 8);
 930 | 			}
 931 | 		}
 932 | 	}
 933 | 	//
 934 | 	// Intel® Xeon® Processor E5 v3 Family
 935 | 	//
 936 | 	if (gCoreCount > 16)
 937 | 	{
 938 | 		msr = rdmsr64(MSR_TURBO_RATIO_LIMIT2);
 939 | 	
 940 | 		IOLOG("\nMSR_TURBO_RATIO_LIMIT2...........(0x1AF) : 0x%llX\n", msr);
 941 | 		IOLOG("------------------------------------------\n");
 942 | 	
 943 | 		for (int i = 17; (i < 33) && (i <= gCoreCount); i++)
 944 | 		{
 945 | 			core_limit = bitfield32(msr, 7, 0);
 946 | 		
 947 | 			if (core_limit)
 948 | 			{
 949 | 				IOLOG(" - Maximum Ratio Limit for C%02d.......... : %X (%u MHz) %s\n", i, core_limit, (core_limit * gBclk), ((i > gCoreCount) && core_limit) ? "(garbage / unused)" : "");
 950 | 		
 951 | 				msr = (msr >> 8);
 952 | 			}
 953 | 		}
 954 | 	}
 955 | 	
 956 | 	do_cpuid(0x00000006, cpuid_reg);
 957 | 
 958 | 	if (bitfield32(cpuid_reg[ecx], 3, 3) == 1)
 959 | 	{
 960 | 		msr = rdmsr64(IA32_ENERGY_PERF_BIAS);
 961 | 
 962 | 		IOLOG("\nIA32_ENERGY_PERF_BIAS............(0x1B0) : 0x%llX\n", msr);
 963 | 		
 964 | 		if (msr)
 965 | 		{
 966 | 			IOLOG("------------------------------------------\n");
 967 | 		
 968 | 			switch(bitfield32(msr, 3, 0))
 969 | 			{
 970 | 				case 0:
 971 | 				case 1:
 972 | 					IOLOG(" - Power Policy Preference...............: %llu (%s)\n", bitfield32(msr, 3, 0), "highest performance");
 973 | 					break;
 974 | 
 975 | 				case 5:
 976 | 					IOLOG(" - Power Policy Preference...............: %llu (%s)\n", bitfield32(msr, 3, 0), "balanced performance and energy saving");
 977 | 					break;
 978 | 
 979 | 				case 15:
 980 | 					IOLOG(" - Power Policy Preference...............: %llu (%s)\n", bitfield32(msr, 3, 0), "maximize energy saving");
 981 | 					break;
 982 | 			}
 983 | 		}
 984 | 	}
 985 | 
 986 | 	msr = rdmsr64(MSR_POWER_CTL);
 987 | 
 988 | 	IOLOG("\nMSR_POWER_CTL....................(0x1FC) : 0x%llX\n", msr);
 989 | 	
 990 | 	if (msr)
 991 | 	{
 992 | 		IOLOG("------------------------------------------\n");
 993 | 		IOLOG(" - Bi-Directional Processor Hot..........: %s\n", (msr & (1 <<  0)) ? "1 (enabled)" : "0 (disabled)");
 994 | 		IOLOG(" - C1E Enable............................: %s\n", (msr & (1 <<  1)) ? "1 (enabled)": "0 (disabled)");
 995 | 	}
 996 | 
 997 | 	if (supportsRAPL(RAPL_PKG))
 998 | 	{
 999 | 		reportRAPL(RAPL_BASE);
1000 | 	}
1001 | 
1002 | 	if (supportsRAPL(RAPL_PKG))
1003 | 	{
1004 | 		reportRAPL(RAPL_PKG);
1005 | 	}
1006 | 
1007 | 	if (gCpuModel == INTEL_FAM6_SANDYBRIDGE) // 0x2A - Intel 325462.pdf Vol.3C 35-120
1008 | 	{
1009 | 		IOLOG("\nMSR_PP0_CURRENT_CONFIG...........(0x601) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PP0_CURRENT_CONFIG));
1010 | 	}
1011 | 
1012 | 	if (supportsRAPL(RAPL_CORES))
1013 | 	{
1014 | 		reportRAPL(RAPL_CORES);
1015 | 	}
1016 | 
1017 | 	if (supportsRAPL(RAPL_CORE_POLICY))
1018 | 	{
1019 | 		reportRAPL(RAPL_CORES);
1020 | 	}
1021 | 
1022 | 	if (igpuEnabled && supportsRAPL(RAPL_GFX))
1023 | 	{
1024 | 		reportRAPL(RAPL_GFX);
1025 | 	}
1026 | 	
1027 | 	IOLOG("\n");
1028 | 
1029 | 	switch (gCpuModel)
1030 | 	{
1031 | 		case INTEL_FAM6_IVYBRIDGE:			// 0x3A - Intel 325462.pdf (Table 35-23) 35-174 Vol.3C
1032 |         case INTEL_FAM6_IVYBRIDGE_X:		// 0x3E
1033 | 			
1034 | 		case INTEL_FAM6_HASWELL_CORE:		// 0x3C - Intel 325462.pdf (Table 35-27) 35-192 Vol.3C
1035 | 		case INTEL_FAM6_HASWELL_X:			// 0x3F
1036 |         case INTEL_FAM6_HASWELL_ULT:		// 0x45
1037 | 			
1038 | 		case INTEL_FAM6_HASWELL_GT3E:		// 0x46
1039 | 		case INTEL_FAM6_BROADWELL_GT3E:		// 0x47
1040 | 		case INTEL_FAM6_SKYLAKE_MOBILE:		// 0x4E
1041 | 		case INTEL_FAM6_SKYLAKE_X:			// 0x55
1042 | 		case INTEL_FAM6_BROADWELL_XEON_D:
1043 | 		case INTEL_FAM6_XEON_PHI_KNL:		// 0x57 - Intel 325462.pdf (Table 35-40) Vol.3C 35-275
1044 |         case INTEL_FAM6_SKYLAKE_DESKTOP:	// 0x5E - Intel 325462.pdf (Table 35-27) 35-192 Vol.3C
1045 | 		case INTEL_FAM6_CANNONLAKE_CORE:	// 0x66
1046 | 		case INTEL_FAM6_KABYLAKE_MOBILE:	// 0x8E
1047 | 		case INTEL_FAM6_KABYLAKE_DESKTOP:	// 0x9E
1048 | 			
1049 | 			IOLOG("MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_CONFIG_TDP_NOMINAL));
1050 | 			IOLOG("MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_CONFIG_TDP_LEVEL1));
1051 | 			IOLOG("MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_CONFIG_TDP_LEVEL2));
1052 | 			IOLOG("MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_CONFIG_TDP_CONTROL));
1053 | 			IOLOG("MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_TURBO_ACTIVATION_RATIO));
1054 | 			break;
1055 | 	}
1056 | 
1057 | 	if (gCpuModel >= INTEL_FAM6_SANDYBRIDGE)
1058 | 	{
1059 | 		IOLOG("MSR_PKGC3_IRTL...................(0x60a) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKGC3_IRTL));
1060 | 		IOLOG("MSR_PKGC6_IRTL...................(0x60b) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKGC6_IRTL));
1061 | 
1062 | 		if (gCheckC7)
1063 | 		{
1064 | 			IOLOG("MSR_PKGC7_IRTL...................(0x60c) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKGC7_IRTL));
1065 | 		}
1066 | 	}
1067 | 
1068 | 	if (gCpuModel >= INTEL_FAM6_NEHALEM)
1069 | 	{
1070 | 		IOLOG("MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C2_RESIDENCY));
1071 | 		IOLOG("MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C3_RESIDENCY));
1072 | 
1073 | 		IOLOG("MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C2_RESIDENCY));
1074 | 		/*
1075 | 		 * Is package C3 auto-demotion/undemotion enabled i.e. is bit-25 or bit-27 set?
1076 | 		 */
1077 | 		if ((msr_pmg_cst_config_control & 0x2000000) || (msr_pmg_cst_config_control & 0x8000000))
1078 | 		{
1079 | 			IOLOG("MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C3_RESIDENCY));
1080 | 		}
1081 | 	}
1082 | 	
1083 | 	if (gCpuModel >= INTEL_FAM6_SANDYBRIDGE)
1084 | 	{
1085 | 		IOLOG("MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C6_RESIDENCY));
1086 | 	
1087 | 		if (gCheckC7)
1088 | 		{
1089 | 			IOLOG("MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C7_RESIDENCY));
1090 | 		}
1091 | 	}
1092 | 
1093 | 	switch (gCpuModel)
1094 | 	{
1095 | 		case INTEL_FAM6_BROADWELL_CORE:		// 0x3D
1096 | 		case INTEL_FAM6_HASWELL_ULT:		// 0x45 - Intel 325462.pdf Vol.3C 35-136
1097 | 		case INTEL_FAM6_SKYLAKE_MOBILE:		// 0x4E
1098 | 		case INTEL_FAM6_SKYLAKE_DESKTOP:	// 0x5E
1099 | 		case INTEL_FAM6_CANNONLAKE_CORE:	// 0x66
1100 |         case INTEL_FAM6_KABYLAKE_MOBILE:	// 0x8E
1101 | 		case INTEL_FAM6_KABYLAKE_DESKTOP:	// 0x9E
1102 | 			IOLOG("MSR_PKG_C8_RESIDENCY.............(0x630) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C8_RESIDENCY));
1103 | 			IOLOG("MSR_PKG_C9_RESIDENCY.............(0x631) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C9_RESIDENCY));
1104 | 			IOLOG("MSR_PKG_C10_RESIDENCY............(0x632) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C10_RESIDENCY));
1105 | 		
1106 | 			IOLOG("MSR_PKG_C8_LATENCY...............(0x633) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C8_RESIDENCY));
1107 | 			IOLOG("MSR_PKG_C9_LATENCY...............(0x634) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C9_RESIDENCY));
1108 | 			IOLOG("MSR_PKG_C10_LATENCY..............(0x635) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C10_RESIDENCY));
1109 | 			break;
1110 | 	}
1111 | 
1112 | 	switch (gCpuModel)
1113 | 	{
1114 | 		case INTEL_FAM6_SKYLAKE_MOBILE:		// 0x4E
1115 | 		case INTEL_FAM6_SKYLAKE_DESKTOP:	// 0x5E
1116 | 		case INTEL_FAM6_CANNONLAKE_CORE:	// 0x66
1117 | 		case INTEL_FAM6_KABYLAKE_MOBILE:	// 0x8E
1118 | 		case INTEL_FAM6_KABYLAKE_DESKTOP:	// 0x9E
1119 | 
1120 | 			msr = rdmsr64(MSR_PLATFORM_ENERGY_COUNTER);
1121 | 
1122 | 			IOLOG("\nMSR_PLATFORM_ENERGY_COUNTER......(0x64D) : 0x%llX %s\n", bitfield32(msr, 31, 0), (bitfield32(msr, 31, 0) == 0) ? "(not supported by hardware/BIOS)" : "");
1123 | 
1124 | 			if (msr)
1125 | 			{
1126 | 				IOLOG("------------------------------------------\n");
1127 | 			}
1128 | 		
1129 | 			msr = rdmsr64(MSR_PPERF);
1130 | 
1131 | 			IOLOG("\nMSR_PPERF........................(0x64E) : 0x%llX\n", msr);
1132 | 		
1133 | 			if (msr)
1134 | 			{
1135 | 				IOLOG("------------------------------------------\n");
1136 | 			
1137 | 				// busy = ((aPerf * 100) / msr);
1138 | 				IOLOG(" - Hardware workload scalability........ : %llu\n", bitfield32(msr, 63, 0));
1139 | 			}
1140 | 
1141 | 			msr = rdmsr64(MSR_CORE_PERF_LIMIT_REASONS);
1142 | 
1143 | 			IOLOG("\nMSR_CORE_PERF_LIMIT_REASONS......(0x64F) : 0x%llX\n", msr);
1144 | 		
1145 | 			if (msr)
1146 | 			{
1147 | 				IOLOG("------------------------------------------\n");
1148 | 				IOLOG(" - PROCHOT Status....................... : %s\n", bitfield32(msr,  1,  1) ? "1 (frequency reduced below OS request due to assertion of external PROCHOT)": "0");
1149 | 				IOLOG(" - Thermal Status....................... : %s\n", bitfield32(msr,  2,  2) ? "1 (frequency reduced below OS request due to a thermal event)": "0");
1150 | 				// bit  3 Reserved.
1151 | 				IOLOG(" - Residency State Regulation Status.... : %s\n", bitfield32(msr,  4,  4) ? "1 (frequency reduced below OS request due to residency state regulation limit)": "0");
1152 | 				IOLOG(" - Running Average Thermal Limit Status. : %s\n", bitfield32(msr,  5,  5) ? "1 (frequency reduced below OS request due to Running Average Thermal Limit)": "0");
1153 | 				IOLOG(" - VR Therm Alert Status................ : %s\n", bitfield32(msr,  6,  6) ? "1 (frequency reduced below OS request due to a thermal alert from a processor Voltage Regulator)" : "0");
1154 | 				IOLOG(" - VR Therm Design Current Status....... : %s\n", bitfield32(msr,  7,  7) ? "1 (frequency reduced below OS request due to VR thermal design current limit)" : "0");
1155 | 				IOLOG(" - Other Status......................... : %s\n", bitfield32(msr,  8,  8) ? "1 (frequency reduced below OS request due to electrical or other constraints)" : "0");
1156 | 				// bit  9 Reserved.
1157 | 				IOLOG(" - Package/Platform-Level #1 Power Limit : %s\n", bitfield32(msr, 10, 10) ? "1 (frequency reduced below OS request due to power limit)" : "0");
1158 | 				IOLOG(" - Package/Platform-Level #2 Power Limit : %s\n", bitfield32(msr, 11, 11) ? "1 (frequency reduced below OS request due to power limit)" : "0");
1159 | 				IOLOG(" - Max Turbo Limit Status............... : %s\n", bitfield32(msr, 12, 12) ? "1 (frequency reduced below OS request due to multi-core turbo limits)" : "0");
1160 | 				IOLOG(" - Turbo Transition Attenuation Status.. : %s\n", bitfield32(msr, 13, 13) ? "1 (frequency reduced below OS request due to turbo transition attenuation)": "0");
1161 | 				// bit 15-14 Reserved.
1162 | 				IOLOG(" - PROCHOT Log.......................... : %s\n", bitfield32(msr, 16, 16) ? "1 (status bit has asserted)" : "0");
1163 | 				IOLOG(" - Thermal Log.......................... : %s\n", bitfield32(msr, 17, 17) ? "1 (status bit has asserted)" : "0");
1164 | 				// bit 19-18 Reserved.
1165 | 				IOLOG(" - Residency State Regulation Log....... : %s\n", bitfield32(msr, 20, 20) ? "1 (status bit has asserted)" : "0");
1166 | 				IOLOG(" - Running Average Thermal Limit Log.... : %s\n", bitfield32(msr, 21, 21) ? "1 (status bit has asserted)" : "0");
1167 | 				IOLOG(" - VR Therm Alert Log................... : %s\n", bitfield32(msr, 22, 22) ? "1 (status bit has asserted)" : "0");
1168 | 				IOLOG(" - VR Thermal Design Current Log........ : %s\n", bitfield32(msr, 23, 23) ? "1 (status bit has asserted)" : "0");
1169 | 				IOLOG(" - Other Status Log..................... : %s\n", bitfield32(msr, 24, 24) ? "1 (status bit has asserted)" : "0");
1170 | 				// bit 25 Reserved.
1171 | 				IOLOG(" - Package/Platform-Level #1 Power Limit : %s\n", bitfield32(msr, 26, 26) ? "1 (status bit has asserted)" : "0");
1172 | 				IOLOG(" - Package/Platform-Level #2 Power Limit : %s\n", bitfield32(msr, 27, 27) ? "1 (status bit has asserted)" : "0");
1173 | 				IOLOG(" - Max Turbo Limit Log.................. : %s\n", bitfield32(msr, 28, 28) ? "1 (status bit has asserted)" : "0");
1174 | 				IOLOG(" - Turbo Transition Attenuation Log..... : %s\n", bitfield32(msr, 29, 29) ? "1 (status bit has asserted)" : "0");
1175 | 				// bit 63-30 Reserved.
1176 | 			}
1177 | #if REPORT_HDC
1178 | 			if ((cpuid_reg[eax] & 0x2000) == 0x2000) // bit-13 HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are supported if set.
1179 | 			{
1180 | 				reportHDC();
1181 | 			}
1182 | #endif
1183 | 	}
1184 | 	
1185 | 	do_cpuid(0x00000001, cpuid_reg);
1186 | 
1187 | 	if (bitfield32(cpuid_reg[ecx], 24, 24) == 1)
1188 | 	{
1189 | 		IOLOG("\nIA32_TSC_DEADLINE................(0x6E0) : 0x%llX\n", (unsigned long long)rdmsr64(IA32_TSC_DEADLINE));
1190 | 	}
1191 | 
1192 | #if REPORT_HWP
1193 | 	reportHWP();
1194 | #endif
1195 | }
1196 | #endif
1197 | 
1198 | 
1199 | #if REPORT_C_STATES
1200 | //==============================================================================
1201 | 
1202 | inline void getCStates(void *magic)
1203 | {
1204 | 	UInt32 logicalCoreNumber = cpu_number();
1205 | 
1206 | 	if (gCheckC3 && rdmsr64(MSR_CORE_C3_RESIDENCY) > 0)
1207 | 	{
1208 | 		gC3Cores |= (1 << logicalCoreNumber);
1209 | 	}
1210 | 
1211 | 	if (gCheckC6 && rdmsr64(MSR_CORE_C6_RESIDENCY) > 0)
1212 | 	{
1213 | 		gC6Cores |= (1 << logicalCoreNumber);
1214 | 	}
1215 | 
1216 | 	if (gCheckC7 && rdmsr64(MSR_CORE_C7_RESIDENCY) > 0)
1217 | 	{
1218 | 		gC7Cores |= (1 << logicalCoreNumber);
1219 | 	}
1220 | 
1221 | 	if (logicalCoreNumber < gThreadCount)
1222 | 	{
1223 | 		// wrmsr64(0x1FC, rdmsr64(0x1FC) & 0xFFFFFFFE);
1224 | 		// wrmsr64(0x1FC, rdmsr64(0x1FC) | 0x1);
1225 | 	}
1226 | 
1227 | 	uint64_t msr = rdmsr64(0x10);
1228 | 	gTSC = rdtsc64();
1229 | 	
1230 | 	// IOLOG("AICPUI: TSC of logical core %d is: msr(0x10) = 0x%llx, rdtsc = 0x%llx\n", logicalCoreNumber, msr, gTSC);
1231 | 
1232 | 	if (msr > (gTSC + 4096))
1233 | 	{
1234 | 		IOLog("Error: TSC of logical core %d is out of sync (0x%llx)!\n", logicalCoreNumber, msr);
1235 | 	}
1236 | }
1237 | #endif
1238 | 
1239 | 
1240 | //==============================================================================
1241 | 
1242 | IOReturn AppleIntelInfo::loopTimerEvent(void)
1243 | {
1244 | 	UInt8 currentMultiplier = (rdmsr64(MSR_IA32_PERF_STS) >> 8);
1245 | 	gCoreMultipliers |= (1ULL << currentMultiplier);
1246 | 
1247 | #if REPORT_IGPU_P_STATES
1248 | 	UInt8 currentIgpuMultiplier = 0;
1249 | 
1250 | 	if (igpuEnabled)
1251 | 	{
1252 | 		if (gCpuModel == INTEL_FAM6_SKYLAKE_MOBILE || gCpuModel == INTEL_FAM6_SKYLAKE_DESKTOP)
1253 | 		{
1254 | 			currentIgpuMultiplier = (UInt8)(((gMchbar[1] * 16.666) + 0.5) / 50);
1255 | 		}
1256 | 		else
1257 | 		{
1258 | 			currentIgpuMultiplier = (UInt8)gMchbar[1];
1259 | 		}
1260 | 
1261 | 		gIGPUMultipliers |= (1ULL << currentIgpuMultiplier);
1262 | 	}
1263 | #endif
1264 | 	
1265 | 	timerEventSource->setTimeoutTicks(Interval);
1266 | 
1267 | 	if (loopLock)
1268 | 	{
1269 | 		return kIOReturnTimeout;
1270 | 	}
1271 | 
1272 | 	loopLock = true;
1273 | 
1274 | #if REPORT_IPG_STYLE
1275 | 	UInt8 pState = 0;
1276 | 
1277 | 	if (logIPGStyle)
1278 | 	{
1279 | 		UInt64 aPerf = 0;
1280 | 		float busy = 0;
1281 | 
1282 | 		aPerf = (rdmsr64(IA32_APERF));
1283 | 		wrmsr64(IA32_APERF, 0ULL);
1284 | 
1285 | 		if (gHwpEnabled)
1286 | 		{
1287 | 			UInt64 pPerf = (rdmsr64(IA32_MPERF));
1288 | 			busy = ((aPerf * 100) / pPerf);
1289 | 		}
1290 | 		else
1291 | 		{
1292 | 			UInt64 mPerf = (rdmsr64(IA32_MPERF));
1293 | 			wrmsr64(IA32_MPERF, 0ULL);
1294 | 			busy = ((aPerf * 100) / mPerf);
1295 | 		}
1296 | 
1297 | 		pState = (UInt8)(((gClockRatio + 0.5) * busy) / 100);
1298 | 
1299 | /*		if (pState != currentMultiplier)
1300 | 		{ */
1301 | 			gCoreMultipliers |= (1ULL << pState);
1302 | 
1303 | 			if ((pState < currentMultiplier) && (pState < gMinRatio))
1304 | 			{
1305 | 				pState = gMinRatio;
1306 | 			}
1307 | 			/*
1308 | 			 * Commented out after fabio67 (fabiosun) confirmed that
1309 | 			 * the wrmsr() below triggered a KP on his configuration
1310 | 			 * wrmsr64(199, (pState << 8));
1311 | 			 */
1312 | 		// }
1313 | 	}
1314 | #endif
1315 | 
1316 | #if REPORT_C_STATES
1317 | 	if (logCStates)
1318 | 	{
1319 | 		UInt32 magic = 0;
1320 | 		mp_rendezvous_no_intrs(getCStates, &magic);
1321 | 		IOSleep(1);
1322 | 	}
1323 | #endif
1324 | 
1325 | 	int currentBit = 0;
1326 | 	UInt64 value = 0ULL;
1327 | 
1328 | #if REPORT_IGPU_P_STATES
1329 | 	if ((gCoreMultipliers != gTriggeredPStates) || (gIGPUMultipliers != gTriggeredIGPUPStates))
1330 | #else
1331 | 	#if REPORT_IPG_STYLE
1332 | 		if ((gCoreMultipliers != gTriggeredPStates) || (currentMultiplier != pState))
1333 | 	#else
1334 | 		if (gCoreMultipliers != gTriggeredPStates)
1335 | 	#endif
1336 | #endif
1337 | 		{
1338 | 			gTriggeredPStates = gCoreMultipliers;
1339 | 			IOLOG("CPU P-States [ ");
1340 | 
1341 | 			for (currentBit = gMinRatio; currentBit <= gMaxRatio; currentBit++)
1342 | 			{
1343 | 				value = (1ULL << currentBit);
1344 | 
1345 | 				if ((gTriggeredPStates & value) == value)
1346 | 				{
1347 | 					if (currentBit == currentMultiplier)
1348 | 					{
1349 | 						IOLOG("(%d) ", currentBit);
1350 | 					}
1351 | 					else
1352 | 					{
1353 | 						IOLOG("%d ", currentBit);
1354 | 					}
1355 | 				}
1356 | 			}
1357 | 
1358 | #if REPORT_IGPU_P_STATES
1359 | 			if (igpuEnabled)
1360 | 			{
1361 | 				gTriggeredIGPUPStates = gIGPUMultipliers;
1362 | 				IOLOG("] iGPU P-States [ ");
1363 | 
1364 | 				for (currentBit = 1; currentBit <= 32; currentBit++)
1365 | 				{
1366 | 					value = (1ULL << currentBit);
1367 | 
1368 | 					if ((gTriggeredIGPUPStates & value) == value)
1369 | 					{
1370 | 						if (currentBit == currentIgpuMultiplier)
1371 | 						{
1372 | 							IOLOG("(%d) ", currentBit);
1373 | 						}
1374 | 						else
1375 | 						{
1376 | 							IOLOG("%d ", currentBit);
1377 | 						}
1378 | 					}
1379 | 				}
1380 | 			}
1381 | #endif
1382 | 			IOLOG("]\n");
1383 | 		}
1384 | 
1385 | #if REPORT_C_STATES
1386 | 	if (gCheckC3 && (gTriggeredC3Cores != gC3Cores))
1387 | 	{
1388 | 		gTriggeredC3Cores = gC3Cores;
1389 | 		IOLOG("CPU C3-Cores [ ");
1390 | 
1391 | 		for (currentBit = 0; currentBit < gThreadCount; currentBit++)
1392 | 		{
1393 | 			value = (1ULL << currentBit);
1394 | 
1395 | 			if ((gTriggeredC3Cores & value) == value)
1396 | 			{
1397 | 				IOLOG("%d ", currentBit);
1398 | 			}
1399 | 		}
1400 | 
1401 | 		IOLOG("]\n");
1402 | 	}
1403 | 
1404 | 	if (gCheckC6 && (gTriggeredC6Cores != gC6Cores))
1405 | 	{
1406 | 		gTriggeredC6Cores = gC6Cores;
1407 | 		IOLOG("CPU C6-Cores [ ");
1408 | 
1409 | 		for (currentBit = 0; currentBit < gThreadCount; currentBit++)
1410 | 		{
1411 | 			value = (1ULL << currentBit);
1412 | 
1413 | 			if ((gTriggeredC6Cores & value) == value)
1414 | 			{
1415 | 				IOLOG("%d ", currentBit);
1416 | 			}
1417 | 		}
1418 | 
1419 | 		IOLOG("]\n");
1420 | 	}
1421 | 
1422 | 	if (gCheckC7 && (gTriggeredC7Cores != gC7Cores))
1423 | 	{
1424 | 		gTriggeredC7Cores = gC7Cores;
1425 | 		IOLOG("CPU C7-Cores [ ");
1426 | 
1427 | 		for (currentBit = 0; currentBit < gThreadCount; currentBit++)
1428 | 		{
1429 | 			value = (1ULL << currentBit);
1430 | 
1431 | 			if ((gTriggeredC7Cores & value) == value)
1432 | 			{
1433 | 				IOLOG("%d ", currentBit);
1434 | 			}
1435 | 		}
1436 | 
1437 | 		IOLOG("]\n");
1438 | 	}
1439 | #endif
1440 | 
1441 | 	loopLock = false;
1442 | 
1443 | 	return kIOReturnSuccess;
1444 | }
1445 | 
1446 | 
1447 | //==============================================================================
1448 | 
1449 | IOService* AppleIntelInfo::probe(IOService *provider, SInt32 *score)
1450 | {
1451 | 	IOService *ret = super::probe(provider, score);
1452 | 
1453 | 	if (ret != this)
1454 | 	{
1455 | 		return 0;
1456 | 	}
1457 | 
1458 | 	return ret;
1459 | }
1460 | 
1461 | 
1462 | //==============================================================================
1463 | 
1464 | bool AppleIntelInfo::start(IOService *provider)
1465 | {
1466 | 	if (IOService::start(provider))
1467 | 	{
1468 | 		simpleLock = IOSimpleLockAlloc();
1469 | 
1470 | 		if (simpleLock)
1471 | 		{
1472 | #if WRITE_LOG_REPORT
1473 | 			mCtx = vfs_context_create(NULL);
1474 | #endif
1475 | 			uint32_t cpuid_reg[4];
1476 | 
1477 | 			IOLOG("AppleIntelInfo.kext v%s Copyright © 2012-2017 Pike R. Alpha. All rights reserved.\n", VERSION);
1478 | 			
1479 | 			do_cpuid(0x00000006, cpuid_reg);
1480 | 			
1481 | 			if ((cpuid_reg[eax] & 0x80) == 0x80) // Is HWP supported?
1482 | 			{
1483 | 				if (rdmsr64(IA32_PM_ENABLE) & 1) // Yes. Is HWP enabled?
1484 | 				{
1485 | 					gHwpEnabled = true; // Yes.
1486 | 				}
1487 | #if ENABLE_HWP
1488 | 				else
1489 | 				{
1490 | 					/*
1491 | 					 * HWP is supported but not enabled (yet) and thus we
1492 | 					 * check the preference to see if we should enable it.
1493 | 					 */
1494 | 					OSBoolean * key_enableHWP = OSDynamicCast(OSBoolean, getProperty("enableHWP"));
1495 | 			
1496 | 					if (key_enableHWP) // Key found?
1497 | 					{
1498 | 						if ((bool)key_enableHWP->getValue()) // Yes. Check value.
1499 | 						{
1500 | 							wrmsr64(IA32_PM_ENABLE, 1); // Enable HWP.
1501 | 						}
1502 | 					}
1503 | 
1504 | 					IOLOG("enableHWP................................: %d\n", (bool)key_enableHWP->getValue());
1505 | 				}
1506 | #endif
1507 | 			}
1508 | 
1509 | #if REPORT_MSRS
1510 | 			OSBoolean * key_logMSRs = OSDynamicCast(OSBoolean, getProperty("logMSRs"));
1511 | 
1512 | 			if (key_logMSRs)
1513 | 			{
1514 | 				logMSRs = (bool)key_logMSRs->getValue();
1515 | 			}
1516 | 
1517 | 			IOLOG("\nSettings:\n------------------------------------------\nlogMSRs..................................: %d\n", logMSRs);
1518 | #endif
1519 | 
1520 | #if REPORT_IGPU_P_STATES
1521 | 			OSBoolean * key_logIGPU = OSDynamicCast(OSBoolean, getProperty("logIGPU"));
1522 | 
1523 | 			if (key_logIGPU)
1524 | 			{
1525 | 				igpuEnabled = (bool)key_logIGPU->getValue();
1526 | 			}
1527 | 
1528 | 			if (igpuEnabled)
1529 | 			{
1530 | 				if ((READ_PCI8_NB(DEVEN) & DEVEN_D2EN_MASK) == 0) // Is the IGPU enabled and visible?
1531 | 				{
1532 | 					igpuEnabled = false;
1533 | 				}
1534 | 			}
1535 | 
1536 | 			IOLOG("logIGPU..................................: %d\n", igpuEnabled);
1537 | #endif
1538 | 
1539 | #if REPORT_INTEL_REGS
1540 | 			OSBoolean * key_logIntelRegs = OSDynamicCast(OSBoolean, getProperty("logIntelRegs"));
1541 | 
1542 | 			if (key_logIntelRegs)
1543 | 			{
1544 | 				logIntelRegs = (bool)key_logIntelRegs->getValue();
1545 | 			}
1546 | 
1547 | 			IOLOG("logIntelRegs............................: %d\n", logIntelRegs);
1548 | #endif
1549 | 
1550 | #if REPORT_C_STATES
1551 | 			OSBoolean * key_logCStates = OSDynamicCast(OSBoolean, getProperty("logCStates"));
1552 | 
1553 | 			if (key_logCStates)
1554 | 			{
1555 | 				logCStates = (bool)key_logCStates->getValue();
1556 | 			}
1557 | 
1558 | 			IOLOG("logCStates...............................: %d\n", logCStates);
1559 | #endif
1560 | 
1561 | #if REPORT_IPG_STYLE
1562 | 			if ((cpuid_reg[ecx] & 1) == 1) // Are APERF and MPERF supported?
1563 | 			{
1564 | 				OSBoolean * key_logIPGStyle = OSDynamicCast(OSBoolean, getProperty("logIPGStyle"));
1565 | 			
1566 | 				if (key_logIPGStyle)
1567 | 				{
1568 | 					logIPGStyle = (bool)key_logIPGStyle->getValue();
1569 | 				}
1570 | 			}
1571 | 			else
1572 | 			{
1573 | 				logIPGStyle = false;
1574 | 			}
1575 | 
1576 | 			IOLOG("logIPGStyle..............................: %d\n", logIPGStyle);
1577 | #endif
1578 | 			
1579 | 			UInt64 msr = rdmsr64(MSR_PLATFORM_INFO);
1580 | 			gClockRatio = (UInt8)((msr >> 8) & 0xff);
1581 | 
1582 | 			msr = rdmsr64(MSR_IA32_PERF_STS);
1583 | 			gCoreMultipliers |= (1ULL << (msr >> 8));
1584 | 			
1585 | 			do_cpuid(0x00000001, cpuid_reg);
1586 | 			
1587 | 			gCpuModel = bitfield32(cpuid_reg[eax], 7,  4) + (bitfield32(cpuid_reg[eax], 19, 16) << 4);
1588 | 
1589 | 			gBclk = (getBusFrequency() / 1000000);
1590 | 
1591 | #if REPORT_C_STATES
1592 | 			switch (gCpuModel) // TODO: Verify me!
1593 | 			{
1594 | 				case INTEL_FAM6_SANDYBRIDGE:		// 0x2A - Intel 325462.pdf Vol.3C 35-111
1595 | 				case INTEL_FAM6_SANDYBRIDGE_X:		// 0x2D - Intel 325462.pdf Vol.3C 35-111
1596 | 				case INTEL_FAM6_IVYBRIDGE:			// 0x3A - Intel 325462.pdf Vol.3C 35-125 (Refering to Table 35-12)
1597 | 				case INTEL_FAM6_IVYBRIDGE_X:		// 0x3E - Intel 325462.pdf Vol.3C 35-125 (Refering to Table 35-12)
1598 | 					// No C7 support for Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 (Product Families Datasheet Volume One of Two page 19)
1599 | 				case INTEL_FAM6_HASWELL_CORE:		// 0x3C - Intel 325462.pdf Vol.3C 35-136
1600 | 				case INTEL_FAM6_BROADWELL_CORE:		// 0x3D
1601 | 				case INTEL_FAM6_HASWELL_ULT:		// 0x45 - Intel 325462.pdf Vol.3C 35-136
1602 | 				case INTEL_FAM6_HASWELL_GT3E:		// 0x46
1603 | 				case INTEL_FAM6_BROADWELL_X:		// 0x47
1604 | 				case INTEL_FAM6_SKYLAKE_MOBILE:		// 0x4E
1605 | 				case INTEL_FAM6_SKYLAKE_DESKTOP:	// 0x5E
1606 | 				case INTEL_FAM6_CANNONLAKE_CORE:	// 0x66
1607 | 				case INTEL_FAM6_KABYLAKE_MOBILE:	// 0x8E
1608 | 				case INTEL_FAM6_KABYLAKE_DESKTOP:	// 0x9E
1609 | 					gCheckC7 = true;
1610 | 					break;
1611 | 			}
1612 | #endif
1613 | 			
1614 | 			msr = rdmsr64(MSR_PLATFORM_INFO);
1615 | 			gMinRatio = (UInt8)((msr >> 40) & 0xff);
1616 | 			gClockRatio = (UInt8)((msr >> 8) & 0xff);
1617 | 			msr = rdmsr64(MSR_CORE_THREAD_COUNT);
1618 | 			gCoreCount = bitfield32(msr, 31, 16);
1619 | 			gThreadCount = bitfield32(msr, 15, 0);
1620 | 
1621 | #if REPORT_MSRS
1622 | 			gTSC = rdtsc64();
1623 | 			IOLOG("InitialTSC...............................: 0x%llx (%llu MHz)\n", gTSC, ((gTSC / gClockRatio) / 1000000000));
1624 | 
1625 | 			// MWAIT information
1626 | 			do_cpuid(0x00000005, cpuid_reg);
1627 | 			uint32_t supportedMwaitCStates = bitfield32(cpuid_reg[edx], 31,  0);
1628 | 
1629 | 			IOLOG("MWAIT C-States...........................: %d\n", supportedMwaitCStates);
1630 | 
1631 | 			if (logMSRs)
1632 | 			{
1633 | 				reportMSRs();
1634 | 			}
1635 | #endif
1636 | 
1637 | #if REPORT_INTEL_REGS
1638 | 			if (logIntelRegs)
1639 | 			{
1640 | 				outl(0xcf8, 0x80001000);
1641 | 				uint32_t value = inl(0xcfc);
1642 | 				
1643 | 				if ((value & 0x0000ffff) == 0x8086)
1644 | 				{
1645 | 					devid = ((value >> 16) & 0x0000ffff);
1646 | 					
1647 | 					reportIntelRegs();
1648 | 				}
1649 | 			}
1650 | #endif
1651 | 
1652 | 			IOLOG("\nCPU Ratio Info:\n------------------------------------------\nBase Clock Frequency (BLCK)............. : %d MHz\n", gBclk);
1653 | 			IOLOG("Maximum Efficiency Ratio/Frequency.......: %2d (%4d MHz)\n", gMinRatio, (gMinRatio * gBclk));
1654 | 			IOLOG("Maximum non-Turbo Ratio/Frequency........: %2d (%4d MHz)\n", gClockRatio, (gClockRatio * gBclk));
1655 | 			
1656 | 			if (!((rdmsr64(IA32_MISC_ENABLES) >> 32) & 0x40))	// Turbo Mode Enabled?
1657 | 			{
1658 | 				msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);
1659 | 				gMaxRatio = (UInt8)(msr & 0xff);
1660 | 				IOLOG("Maximum Turbo Ratio/Frequency............: %2d (%4d MHz)\n", gMaxRatio, (gMaxRatio * gBclk));
1661 | 			}
1662 | 			else
1663 | 			{
1664 | 				gMaxRatio = gClockRatio;
1665 | 				IOLOG("Maximum Ratio/Frequency..................: %2d (%4d MHz)\n", gMaxRatio, (gMaxRatio * gBclk));
1666 | 			}
1667 | 
1668 | #if REPORT_IGPU_P_STATES
1669 | 			if (igpuEnabled)
1670 | 			{
1671 | 				IOPhysicalAddress address = (IOPhysicalAddress)(0xFED10000 + 0x5948);
1672 | 				memDescriptor = IOMemoryDescriptor::withPhysicalAddress(address, 0x53, kIODirectionInOut);
1673 | 
1674 | 				if (memDescriptor != NULL)
1675 | 				{
1676 | 					if ((result = memDescriptor->prepare()) == kIOReturnSuccess)
1677 | 					{
1678 | 						memoryMap = memDescriptor->map();
1679 | 
1680 | 						if (memoryMap != NULL)
1681 | 						{
1682 | 							gMchbar = (UInt8 *)memoryMap->getVirtualAddress();
1683 | 
1684 | 							// Preventing a stupid (UEFI) BIOS limit.
1685 | 							if (gMchbar[0x4C] < gMchbar[0x50])
1686 | 							{
1687 | 								gMchbar[0x4C] = gMchbar[0x50];
1688 | 							}
1689 | 
1690 | 							//
1691 | 							// Examples IGPU multiplier:	17 (multiplier) * 50 (frequency in MHz) =  850 MHz
1692 | 							//								22 (multiplier) * 50 (frequency in MHz) = 1100 MHz
1693 | 							//								6 P-States: 850, 900, 950, 1000, 1050 and 1100 MHz
1694 | 							//
1695 | 							// Current RP-State, when the graphics engine is in RC6, this reflects the last used ratio.
1696 | 							IOLOG("\nIGPU Info:\n------------------------------------------\n");
1697 | 							IOLOG("IGPU Current Frequency...................: %4d MHz\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x01])); // RP_STATE_RATIO (CURRENT_FREQUENCY)
1698 | 							// Maximum RPN base frequency capability for the Integrated GFX Engine (GT).
1699 | 							IOLOG("IGPU Minimum Frequency...................: %4d MHz\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x52])); // RPN_CAP (MIN_FREQUENCY) See also: DSDT->RPNC
1700 | 							// Maximum RP1 base frequency capability for the Integrated GFX Engine (GT).
1701 | 							IOLOG("IGPU Maximum Non-Turbo Frequency.........: %4d MHz\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x51])); // RP1_CAP (MAX_NON_TURBO) See also: DSDT->RP1C
1702 | 							// Maximum RP0 base frequency capability for the Integrated GFX Engine (GT).
1703 | 							IOLOG("IGPU Maximum Turbo Frequency.............: %4d MHz\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x50])); // RP0_CAP (MAX_TURBO)) See also: DSDT->RP0C
1704 | 
1705 | 							// Maximum base frequency limit for the Integrated GFX Engine (GT) allowed during run-time.
1706 | 							if (gMchbar[0x4C] == 255)
1707 | 							{
1708 | 								IOLOG("IGPU Maximum limit.......................: No Limit\n\n"); // RPSTT_LIM
1709 | 							}
1710 | 							else
1711 | 							{
1712 | 								IOLOG("IGPU Maximum limit.......................: %4d MHz\n\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x4C])); // RPSTT_LIM
1713 | 							}
1714 | 						}
1715 | 						else
1716 | 						{
1717 | 							IOLOG("Error: memoryMap == NULL\n");
1718 | 						}
1719 | 					}
1720 | 					else
1721 | 					{
1722 | 						IOLOG("Error: memDescriptor->prepare() failed!\n");
1723 | 					}
1724 | 				}
1725 | 				else
1726 | 				{
1727 | 					IOLOG("Error: memDescriptor == NULL\n");
1728 | 				}
1729 | 			}
1730 | #endif
1731 | 			IOLOG("P-State ratio * %d = Frequency in MHz\n------------------------------------------\n", gBclk);
1732 | 
1733 | 			timerEventSource = IOTimerEventSource::timerEventSource(this, OSMemberFunctionCast(IOTimerEventSource::Action, this, &AppleIntelInfo::loopTimerEvent));
1734 | 			workLoop = getWorkLoop();
1735 | 
1736 | 			if (timerEventSource && workLoop && (kIOReturnSuccess == workLoop->addEventSource(timerEventSource)))
1737 | 			{
1738 | 				this->registerService(0);
1739 | 				timerEventSource->setTimeoutMS(1000);
1740 | 
1741 | 				return true;
1742 | 			}
1743 | 		}
1744 | 	}
1745 | 
1746 | 	return false;
1747 | }
1748 | 
1749 | 
1750 | //==============================================================================
1751 | 
1752 | void AppleIntelInfo::stop(IOService *provider)
1753 | {
1754 | #if	WRITE_LOG_REPORT
1755 | 	if (mCtx)
1756 | 	{
1757 | 		vfs_context_rele(mCtx);
1758 | 	}
1759 | #endif
1760 | 
1761 | 	if (simpleLock)
1762 | 	{
1763 | 		IOSimpleLockFree(simpleLock);
1764 | 	}
1765 | 
1766 | 	if (timerEventSource)
1767 | 	{
1768 | 		if (workLoop)
1769 | 		{
1770 | 			timerEventSource->cancelTimeout();
1771 | 			workLoop->removeEventSource(timerEventSource);
1772 | 		}
1773 | 
1774 | 		timerEventSource->release();
1775 | 		timerEventSource = NULL;
1776 | 	}
1777 | 
1778 | 	super::stop(provider);
1779 | }
1780 | 
1781 | 
1782 | //==============================================================================
1783 | 
1784 | void AppleIntelInfo::free()
1785 | {
1786 | #if REPORT_IGPU_P_STATES
1787 | 	if (igpuEnabled)
1788 | 	{
1789 | 		if (memoryMap)
1790 | 		{
1791 | 			memoryMap->release();
1792 | 			memoryMap = NULL;
1793 | 		}
1794 | 
1795 | 		if (memDescriptor)
1796 | 		{
1797 | 			memDescriptor->release();
1798 | 			memDescriptor = NULL;
1799 | 		}
1800 | 	}
1801 | #endif
1802 | 
1803 | 	super::free();
1804 | }
1805 | 


--------------------------------------------------------------------------------
/AppleIntelInfo/AppleIntelInfo.h:
--------------------------------------------------------------------------------
  1 | /*
  2 |  * Copyright (c) 2012-2017 Pike R. Alpha. All rights reserved.
  3 |  *
  4 |  * Original idea and initial development of MSRDumper.kext (c) 2011 by † RevoGirl.
  5 |  *
  6 |  * A big thank you to George for his help and continuation of Sam's work, but it
  7 |  * was time for me to push the envelope and add some really interesting stuff.
  8 |  *
  9 |  * This work is licensed under the Creative Commons Attribution-NonCommercial
 10 |  * 4.0 Unported License => http://creativecommons.org/licenses/by-nc/4.0
 11 |  */
 12 | 
 13 | #pragma clang diagnostic push
 14 | #pragma clang diagnostic ignored "-Wdeprecated-register"
 15 | #include <IOKit/IOLib.h>
 16 | #pragma clang diagnostic pop
 17 | 
 18 | #include <IOKit/IOService.h>
 19 | #include <IOKit/IOWorkLoop.h>
 20 | #include <IOKit/IOMemoryDescriptor.h>
 21 | #include <IOKit/IOTimerEventSource.h>
 22 | 
 23 | #include <sys/vnode.h>
 24 | #include <sys/fcntl.h>
 25 | #include <sys/proc.h>
 26 | #include <i386/cpuid.h>
 27 | 
 28 | #include <libkern/sysctl.h>
 29 | 
 30 | #pragma clang diagnostic push
 31 | #pragma clang diagnostic ignored "-Wdeprecated-register"
 32 | #include <i386/proc_reg.h>
 33 | #pragma clang diagnostic pop
 34 | 
 35 | #include <essentials.h>
 36 | 
 37 | #define super IOService
 38 | 
 39 | #define VERSION					"2.9"
 40 | 
 41 | /*
 42 |  * Build settings (0 = disable feature / 1 = enable feature)
 43 |  */
 44 | 
 45 | #define REPORT_MSRS				1
 46 | #define REPORT_RAPL_MSRS		1
 47 | #define REPORT_HWP				1
 48 | #define REPORT_HDC				1
 49 | 
 50 | #define REPORT_IGPU_P_STATES	1
 51 | #define REPORT_C_STATES			1
 52 | #define REPORT_IPG_STYLE		1
 53 | #define REPORT_INTEL_REGS		0
 54 | 
 55 | #define ENABLE_HWP				1
 56 | 
 57 | #define WRITE_LOG_REPORT		1
 58 | 
 59 | #define MMIO_READ8(Address)			(*(volatile UInt8  *)(Address))
 60 | #define MMIO_READ16(Address)		(*(volatile UInt16 *)(Address))
 61 | #define MMIO_READ32(Address)		(*(volatile UInt32 *)(gMMIOAddress + Address))
 62 | 
 63 | #define NB_BUS	0x00
 64 | #define NB_DEV	0x00
 65 | #define NB_FUN	0x00
 66 | 
 67 | #define DEVEN	(0x54)
 68 | #define DEVEN_D2EN_MASK	(0x10)
 69 | 
 70 | #define NB_PCICFG_SPACE_INDEX_REG	0xcf8
 71 | #define NB_PCICFG_SPACE_DATA_REG	0xcfc
 72 | 
 73 | #define BIT31						0x80000000
 74 | 
 75 | #define PCIEX_BASE_ADDRESS			0xF8000000
 76 | #define NB_MCH_BASE_ADDRESS			0xFED10000	// (G)MCH Memory Mapped Register Range Base Address (D0:F0:Rx48).
 77 | 
 78 | #define READ_PCI8(Bx, Dx, Fx, Rx)	ReadPci8(Bx, Dx, Fx, Rx)
 79 | #define READ_PCI8_NB(Rx)			READ_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx)
 80 | 
 81 | #define IGPU_RATIO_TO_FREQUENCY(ratio)	((ratio * 100) / 2)
 82 | 
 83 | #define NB_PCI_CFG_ADDRESS(bus, dev, func, reg) \
 84 | (UInt64) ((((UInt8)(bus) << 24) + ((UInt8)(dev) << 16) + \
 85 | ((UInt8)(func) << 8) + ((UInt8)(reg))) & 0xffffffff)
 86 | 
 87 | #define NB_PCIE_CFG_ADDRESS(bus, dev, func, reg) \
 88 | ((UInt32)(PCIEX_BASE_ADDRESS + ((UInt8)(bus) << 20) + \
 89 | ((UInt8)(dev) << 15) + ((UInt8)(func) << 12) + (reg)))
 90 | 
 91 | #if WRITE_LOG_REPORT
 92 | 	#define	FILE_PATH "/tmp/AppleIntelInfo.dat"
 93 | 
 94 | 	#define TEMP_BUFFER_SIZE	256
 95 | 	#define WRITE_BUFFER_SIZE	1024
 96 | 
 97 | 	#define IOLOG(format, args...)							\
 98 | 	memset(logBuffer, 0, TEMP_BUFFER_SIZE);					\
 99 | 	snprintf(logBuffer, TEMP_BUFFER_SIZE, format, ##args);	\
100 | 	writeReport();
101 | #else
102 | 	#define IOLOG(fmt, args...) IOLog(fmt, ##args)
103 | 	/*
104 | 	 * macOS Sierra only!
105 | 	 */
106 | 	#include <os/log.h>
107 | 	#define IOLOG(fmt, args...) os_log_with_type(OS_LOG_DEFAULT, OS_LOG_TYPE_INFO, fmt, ##args)
108 | #endif
109 | 
110 | 
111 | #define RAPL_BASE					0
112 | 
113 | #define RAPL_PKG					(1 << 0)
114 | 												/* 0x610 MSR_PKG_POWER_LIMIT */
115 | 												/* 0x611 MSR_PKG_ENERGY_STATUS */
116 | 
117 | #define RAPL_PKG_PERF_STATUS		(1 << 1)
118 | 												/* 0x613 MSR_PKG_PERF_STATUS */
119 | 
120 | #define RAPL_PKG_POWER_INFO			(1 << 2)
121 | 												/* 0x614 MSR_PKG_POWER_INFO */
122 | 
123 | #define RAPL_DRAM					(1 << 3)
124 | 												/* 0x618 MSR_DRAM_POWER_LIMIT */
125 | 												/* 0x619 MSR_DRAM_ENERGY_STATUS */
126 | 
127 | #define RAPL_DRAM_PERF_STATUS		(1 << 4)
128 | 												/* 0x61b MSR_DRAM_PERF_STATUS */
129 | 
130 | #define RAPL_DRAM_POWER_INFO		(1 << 5)
131 | 												/* 0x61c MSR_DRAM_POWER_INFO */
132 | 
133 | #define RAPL_CORES_POWER_LIMIT		(1 << 6)
134 | 												/* 0x638 MSR_PP0_POWER_LIMIT */
135 | 
136 | #define RAPL_CORE_POLICY			(1 << 7)
137 | 												/* 0x63a MSR_PP0_POLICY */
138 | 
139 | #define RAPL_GFX					(1 << 8)
140 | 												/* 0x640 MSR_PP1_POWER_LIMIT */
141 | 												/* 0x641 MSR_PP1_ENERGY_STATUS */
142 | 												/* 0x642 MSR_PP1_POLICY */
143 | 
144 | #define RAPL_CORES_ENERGY_STATUS	(1 << 9)
145 | 												/* 0x639 MSR_PP0_ENERGY_STATUS */
146 | 
147 | #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
148 | 
149 | 
150 | //------------------------------------------------------------------------------
151 | 
152 | static __inline__ void outl(UInt16 port, UInt32 value)
153 | {
154 | 	__asm__ volatile("outl %0, %w1" : : "a" (value), "Nd" (port));
155 | }
156 | 
157 | //------------------------------------------------------------------------------
158 | 
159 | static __inline__ unsigned char inb(UInt16 port)
160 | {
161 | 	UInt8 value;
162 | 	__asm__ volatile("inb %w1, %b0" : "=a" (value) : "Nd" (port));
163 | 	return (value);
164 | }
165 | 
166 | //------------------------------------------------------------------------------
167 | 
168 | static __inline__ unsigned int inl(UInt16 port)
169 | {
170 | 	UInt32 value;
171 | 	__asm__ volatile("inl %w1, %0" : "=a" (value) : "Nd" (port));
172 | 	return (value);
173 | }
174 | 
175 | //------------------------------------------------------------------------------
176 | 
177 | UInt8 ReadPci8(UInt8 Bus, UInt8 Dev, UInt8 Fun, UInt16 Reg)
178 | {
179 | 	if (Reg >= 0x100)
180 | 	{
181 | 		return MMIO_READ8((UInt64)NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg));
182 | 	}
183 | 	else
184 | 	{
185 | 		outl(NB_PCICFG_SPACE_INDEX_REG, BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc));
186 | 		return inb(NB_PCICFG_SPACE_DATA_REG | (UInt8)(Reg & 3));
187 | 	}
188 | }
189 | 
190 | extern "C" void mp_rendezvous_no_intrs(void (*action_func)(void *), void * arg);
191 | extern "C" int cpu_number(void);
192 | 
193 | //------------------------------------------------------------------------------
194 | 
195 | class AppleIntelInfo : public IOService
196 | {
197 | 	OSDeclareDefaultStructors (AppleIntelInfo);
198 | 	
199 | private:
200 | 	IOSimpleLock		*simpleLock;
201 | 	IOWorkLoop			*workLoop;
202 | 	IOTimerEventSource	*timerEventSource;
203 | 	
204 | #ifdef REPORT_IGPU_P_STATES
205 | 	IOMemoryDescriptor	*memDescriptor;
206 | 	IOMemoryMap			*memoryMap;
207 | 
208 | 	bool igpuEnabled	= false;	// Set <key>logIGPU</key> to <true/> in Info.plist to enable this feature.
209 | #endif
210 | 	
211 | 	IOReturn result		= kIOReturnSuccess;
212 | 	
213 | 	virtual IOReturn loopTimerEvent(void);
214 | 
215 | 	int writeReport(void);
216 | 
217 | #ifdef REPORT_RAPL_MSRS
218 | 	bool supportsRAPL(UInt16 aTargetRAPLFeature);
219 | 	void reportRAPL(UInt16 aTargetRAPL);
220 | #endif
221 | 
222 | #ifdef REPORT_MSRS
223 | 	void reportMSRs(void);
224 | 
225 | 	#ifdef REPORT_HWP
226 | 	void reportHWP(void);
227 | 	#endif
228 | 
229 | 	#ifdef REPORT_HWP
230 | 	void reportHDC(void);
231 | 	#endif
232 | 
233 | 	bool hasCPUFeature(long targetCPUFeature);
234 | 
235 | 	bool logMSRs		= true;		// Set <key>logIGPU</key> to <false/> in Info.plist to disable this feature.
236 | #endif
237 | 
238 | 	bool gHwpEnabled	= false;
239 | 
240 | 	bool loopLock		= false;
241 | 
242 | #ifdef REPORT_C_STATES
243 | 	bool logCStates		= true;		//  Set <key>logCStates</key> to <false/> in Info.plist to disable this feature.
244 | #endif
245 | 
246 | #ifdef REPORT_IPG_STYLE
247 | 	bool logIPGStyle	= true;		//  Set <key>logIPGStyle</key> to <false/> in Info.plist to disable this feature.
248 | #endif
249 | 
250 | #ifdef REPORT_INTEL_REGS
251 | 	bool logIntelRegs	= true;		//  Set <key>logIntelRegs</key> to <false/> in Info.plist to disable this feature.
252 | 
253 | 	#define DEBUGSTRING(func) void func(char *result, int len, UInt32 reg, UInt32 val)
254 | 	#define DEFINEREG2(reg, func) { reg, #reg, func, 0 }
255 | 
256 | 	#define DEFINE_FUNC_VOID(func) void func(void)
257 | 	#define DEFINE_FUNC_DUMP(func) void func(struct reg_debug *regs, uint32_t count)
258 | 	
259 | 	void intel_dump_other_regs(void);
260 | 	void dumpRegisters(struct reg_debug *regs, uint32_t count);
261 | 	void getPCHDeviceID(void);
262 | 	void reportIntelRegs(void);
263 | #endif
264 | 
265 | 	uint32_t getBusFrequency(void);
266 | 
267 | 	const char * getUnitText(uint8_t unit);
268 | 
269 | 	UInt16 Interval					= 50;
270 | 	uint16_t gBclk					= 0;
271 | 
272 | 	UInt64	gCoreMultipliers		= 0ULL;
273 | 	UInt64	gTriggeredPStates		= 0ULL;
274 | 	
275 | 	UInt64	gIGPUMultipliers		= 0ULL;
276 | 	UInt64	gTriggeredIGPUPStates	= 0ULL;
277 | 
278 | #if WRITE_LOG_REPORT
279 | 	vfs_context_t mCtx				= NULL;
280 | 	long reportFileOffset			= 0L;
281 | 
282 | 	char tempBuffer[TEMP_BUFFER_SIZE];
283 | 	char logBuffer[WRITE_BUFFER_SIZE];
284 | #endif
285 | 
286 | public:
287 | 	virtual IOService *	probe(IOService * provider, SInt32 * score) override;
288 | 	virtual bool start(IOService * provider) override;
289 | 	virtual void stop(IOService * provider) override;
290 | 	virtual void free(void) override;
291 | 	
292 | 	UInt8	gMinRatio		= 0;
293 | 	UInt8	gClockRatio		= 0;
294 | 	UInt8	gMaxRatio		= 0;
295 | 	UInt8	gCpuModel		= 0;
296 | 	UInt8	gCoreCount		= 0;
297 | };
298 | 
299 | OSDefineMetaClassAndStructors(AppleIntelInfo, IOService)
300 | 
301 | UInt8	gThreadCount	= 0;
302 | UInt8	gCoreStates	= 0ULL;
303 | 
304 | #if REPORT_C_STATES
305 | 	bool	gCheckC3	= true;
306 | 	bool	gCheckC6	= true;
307 | 	bool	gCheckC7	= false;
308 | 
309 | 	UInt64	gC3Cores	= 0;
310 | 	UInt64	gC6Cores	= 0;
311 | 	UInt64	gC7Cores	= 0;
312 | 
313 | 	UInt64	gTriggeredC3Cores	= 0;
314 | 	UInt64	gTriggeredC6Cores	= 0;
315 | 	UInt64	gTriggeredC7Cores	= 0;
316 | #endif
317 | 
318 | UInt64	gCoreMultipliers = 0ULL;
319 | 
320 | uint64_t gTSC = 0;
321 | 
322 | #ifdef REPORT_IGPU_P_STATES
323 | UInt8	* gMchbar	= NULL;
324 | #endif
325 | 
326 | #if REPORT_INTEL_REGS
327 | 	#include "../AppleIntelRegisterDumper/AppleIntelRegisterDumper.h"
328 | #endif
329 | 


--------------------------------------------------------------------------------
/AppleIntelInfo/essentials.h:
--------------------------------------------------------------------------------
  1 | /*
  2 |  * This work is licensed under the Creative Commons Attribution-NonCommercial
  3 |  * 4.0 Unported License => http://creativecommons.org/licenses/by-nc/4.0
  4 |  */
  5 | 
  6 | #ifndef __LIBSAIO_CPU_ESSENTIALS_H
  7 | #define __LIBSAIO_CPU_ESSENTIALS_H
  8 | 
  9 | #include "intel_family.h"
 10 | 
 11 | /* Copied from xnu/osfmk/cpuid.c (modified for 64-bit values) */
 12 | #define bit(n)				(1UL << (n))
 13 | #define bitmask64(h, l)		((bit(h) | (bit(h) - 1)) & ~ (bit(l) - 1))
 14 | #define bitfield32(x, h, l)	(((x) & bitmask64(h, l)) >> l)
 15 | 
 16 | // Added by DHP in 2010.
 17 | #define CPU_VENDOR_INTEL	0x756E6547
 18 | #define CPU_VENDOR_AMD		0x68747541
 19 | 
 20 | 
 21 | /* Copied from xnu/osfmk/cpuid.h */
 22 | #define CPU_STRING_UNKNOWN "Unknown CPU Typ"
 23 | 
 24 | // Copied from xnu/osfmk/proc_reg.h
 25 | #define MSR_IA32_PLATFORM_ID			0x17
 26 | #define	MSR_CORE_THREAD_COUNT			0x35
 27 | 
 28 | #ifndef MSR_PLATFORM_INFO
 29 | 	#define MSR_PLATFORM_INFO			0xCE
 30 | #endif
 31 | 
 32 | #define MSR_PKG_CST_CONFIG_CONTROL		0xE2	// MSR_PKG_CST_CONFIG_CONTROL
 33 | #define MSR_PMG_IO_CAPTURE_BASE			0xE4
 34 | #define IA32_MPERF						0xE7
 35 | #define IA32_APERF						0xE8
 36 | #define IA32_PPERF						0x64E
 37 | 
 38 | #define	MSR_IA32_PERF_STATUS			0x0198	// MSR_IA32_PERF_STS in XNU
 39 | #define	MSR_IA32_PERF_CONTROL			0x0199	// IA32_PERF_CTL
 40 | 
 41 | #ifndef MSR_FLEX_RATIO
 42 | 	#define MSR_FLEX_RATIO				0x0194
 43 | #endif
 44 | 
 45 | #define IA32_CLOCK_MODULATION			0x019A
 46 | #define IA32_THERM_INTERRUPT			0x019B
 47 | #define IA32_THERM_STATUS				0x019C
 48 | #define MSR_THERM2_CTL					0x019D
 49 | 
 50 | #define IA32_MISC_ENABLES				0x01A0
 51 | #define MSR_TEMPERATURE_TARGET			0x01A2
 52 | #define MSR_MISC_PWR_MGMT				0x01AA
 53 | #define	MSR_TURBO_RATIO_LIMIT			0x01AD
 54 | #define	MSR_TURBO_RATIO_LIMIT1			0x01AE
 55 | #define	MSR_TURBO_RATIO_LIMIT2			0x01AF
 56 | 
 57 | #define IA32_ENERGY_PERF_BIAS			0x01B0
 58 | #define IA32_PLATFORM_DCA_CAP			0x01F8
 59 | #define MSR_POWER_CTL					0x01FC
 60 | 
 61 | #define MSR_PKGC3_IRTL					0x60A
 62 | #define MSR_PKGC6_IRTL					0x60B
 63 | #define MSR_PKGC7_IRTL					0x60C
 64 | 
 65 | #define MSR_PKG_C2_RESIDENCY			0x60D
 66 | #define MSR_PKG_C3_RESIDENCY			0x3F8
 67 | #define MSR_PKG_C6_RESIDENCY			0x3F9
 68 | #define MSR_PKG_C7_RESIDENCY			0x3FA
 69 | 
 70 | #define MSR_CORE_C3_RESIDENCY			0x3FC
 71 | #define MSR_CORE_C6_RESIDENCY			0x3FD
 72 | #define MSR_CORE_C7_RESIDENCY			0x3FE
 73 | 
 74 | #define MSR_PP0_CURRENT_CONFIG			0x601
 75 | #define MSR_PP1_CURRENT_CONFIG			0x602
 76 | 
 77 | // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
 78 | #define MSR_RAPL_POWER_UNIT				0x606
 79 | 
 80 | #define MSR_PKG_POWER_LIMIT				0x610
 81 | #define MSR_PKG_ENERGY_STATUS			0x611
 82 | #define MSR_PKG_PERF_STATUS				0x613
 83 | #define MSR_PKG_POWER_INFO				0x614
 84 | 
 85 | // JakeTown only Memory MSR's.
 86 | #define MSR_DRAM_POWER_LIMIT			0x618
 87 | #define MSR_DRAM_ENERGY_STATUS			0x619
 88 | #define MSR_DRAM_PERF_STATUS			0x61B
 89 | #define MSR_DRAM_POWER_INFO				0x61C
 90 | 
 91 | #define MSR_UNCORE_RATIO_LIMIT			0x620
 92 | 
 93 | // Xeon (0x4F) Package residency MSR's.
 94 | // Haswell-ULT (0x45) Package residency MSR's.
 95 | #define MSR_PKG_C8_RESIDENCY			0x630
 96 | #define MSR_PKG_C9_RESIDENCY			0x631
 97 | #define MSR_PKG_C10_RESIDENCY			0x632
 98 | 
 99 | // Haswell-ULT C state latency control.
100 | #define MSR_PKG_C8_LATENCY				0x633
101 | #define MSR_PKG_C9_LATENCY				0x634
102 | #define MSR_PKG_C10_LATENCY				0x635
103 | 
104 | // Haswell-ULT VR configurations.
105 | #define VR_MISC_CONFIG2					0x636
106 | 
107 | // Haswell-ULT Alternate BCLK in deep Package C states.
108 | #define MSR_COUNTER_24_MHZ				0x637
109 | 
110 | // Sandy Bridge IA (Core) domain MSR's.
111 | #define MSR_PP0_POWER_LIMIT				0x638
112 | #define MSR_PP0_ENERGY_STATUS			0x639
113 | #define MSR_PP0_POLICY					0x63A
114 | #define MSR_PP0_PERF_STATUS				0x63B
115 | 
116 | // Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
117 | #define MSR_PP1_POWER_LIMIT				0x640
118 | #define MSR_PP1_ENERGY_STATUS			0x641
119 | #define MSR_PP1_POLICY					0x642
120 | 
121 | // Ivy Bridge Specific MSR's
122 | #define MSR_CONFIG_TDP_NOMINAL			0x648
123 | #define MSR_CONFIG_TDP_LEVEL1			0x649
124 | #define MSR_CONFIG_TDP_LEVEL2			0x64A
125 | #define MSR_CONFIG_TDP_CONTROL			0x64B
126 | #define MSR_TURBO_ACTIVATION_RATIO		0x64C
127 | 
128 | // Skylake Specific MSR's.
129 | #define MSR_PLATFORM_ENERGY_COUNTER		0x64D
130 | #define MSR_PPERF						0x64E
131 | #define MSR_CORE_PERF_LIMIT_REASONS		0x64F
132 | 
133 | #define MSR_PKG_HDC_CONFIG				0x652
134 | 
135 | #define MSR_CORE_HDC_RESIDENCY			0x653
136 | #define MSR_PKG_HDC_SHALLOW_RESIDENCY	0x655
137 | #define MSR_PKG_HDC_DEEP_RESIDENCY		0x656
138 | 
139 | #define MSR_WEIGHTED_CORE_C0			0x658
140 | #define MSR_ANY_CORE_C0					0x659
141 | #define MSR_ANY_GFXE_C0					0x65A
142 | #define MSR_CORE_GFXE_OVERLAP_C0		0x65B
143 | #define MSR_PLATFORM_POWER_LIMIT		0x65C
144 | 
145 | #define IA32_TSC_DEADLINE				0x6E0
146 | 
147 | #define IA32_PKG_HDC_CTL				0xDB0
148 | #define IA32_PM_CTL1					0xDB1
149 | #define IA32_THREAD_STALL				0xDB2
150 | 
151 | // HPW MSR's
152 | #define IA32_PM_ENABLE					0x770
153 | #define IA32_HWP_CAPABILITIES			0x771
154 | #define IA32_HWP_REQUEST_PKG			0x772
155 | #define IA32_HWP_INTERRUPT				0x773
156 | #define IA32_HWP_REQUEST				0x774
157 | #define IA32_HWP_STATUS					0x777
158 | 
159 | // CPUID leaf index values (pointing to the right spot in CPUID/LEAF array).
160 | 
161 | #define LEAF_0				0			// DHP: Formerly known as CPUID_n
162 | #define LEAF_1				1
163 | #define LEAF_2				2
164 | #define LEAF_4				3
165 | #define LEAF_5				4
166 | #define LEAF_6				5
167 | #define LEAF_B				6
168 | #define LEAF_80				7
169 | #define LEAF_81				8
170 | 
171 | #define MAX_CPUID_LEAVES	9			// DHP: Formerly known as MAX_CPUID
172 | 
173 | /* Copied from: xnu/osfmk/i386/cpuid.h
174 | #define CPU_MODEL_YONAH  			0x0E
175 | #define CPU_MODEL_MEROM				0x0F
176 | #define CPU_MODEL_PENRYN			0x17
177 | #define CPU_MODEL_NEHALEM			0x1A
178 | #define CPU_MODEL_ATOM				0x1C
179 | #define CPU_MODEL_FIELDS			0x1E	// Lynnfield, Clarksfield, Jasper (LGA 1156)
180 | #define CPU_MODEL_DALES				0x1F	// Havendale, Auburndale (LGA 1156)
181 | #define CPU_MODEL_DALES_32NM		0x25	// Clarkdale, Arrandale
182 | #define CPU_MODEL_SB_CORE			0x2A	// Sandy Bridge Core Processors (LGA 1155)
183 | #define CPU_MODEL_WESTMERE			0x2C	// Gulftown, Westmere-EP, Westmere-WS
184 | #define CPU_MODEL_SB_JAKETOWN		0x2D	// Sandy Bridge-EP, Sandy Bridge Xeon Processors (LGA 2011)
185 | #define CPU_MODEL_NEHALEM_EX		0x2E
186 | #define CPU_MODEL_WESTMERE_EX		0x2F
187 | #define CPU_MODEL_IB_CORE			0x3A	// Ivy Bridge Core Processors (LGA 1155)
188 | #define CPU_MODEL_IB_CORE_EX		0x3B	// Ivy Bridge Core Processors (LGA 2011)
189 | #define CPU_MODEL_IB_CORE_XEON		0x3E
190 | 
191 | #define CPU_MODEL_HASWELL			0x3C
192 | #define CPU_MODEL_HASWELL_SVR		0x3F
193 | #define CPU_MODEL_HASWELL_ULT		0x45
194 | #define CPU_MODEL_CRYSTALWELL		0x46
195 | 
196 | #define CPU_MODEL_BROADWELL			0x3D
197 | #define CPU_MODEL_BROADWELL_ULX		0x3D
198 | #define CPU_MODEL_BROADWELL_ULT		0x3D
199 | #define CPU_MODEL_BROADWELL_H		0x47
200 | #define CPU_MODEL_BRYSTALWELL		0x4C
201 | #define CPU_MODEL_BROADWELL_E		0x4F
202 | 
203 | #define CPU_MODEL_SKYLAKE			0x4E
204 | #define CPU_MODEL_SKYLAKE_ULT		0x4E
205 | #define CPU_MODEL_SKYLAKE_ULX		0x4E
206 | #define CPU_MODEL_SKYLAKE_X			0x55
207 | #define CPU_MODEL_SKYLAKE_DT		0x5E
208 | 
209 | #define CPU_MODEL_KABYLAKE			0x8E
210 | #define CPU_MODEL_KABYLAKE_DT		0x9E
211 | */
212 | 
213 | #define DALES_BRIDGE	1
214 | #define SANDY_BRIDGE	2
215 | #define IVY_BRIDGE		4
216 | #define HASWELL			8
217 | 
218 | #endif /* !__LIBSAIO_CPU_ESSENTIALS_H */
219 | 


--------------------------------------------------------------------------------
/AppleIntelInfo/intel_family.h:
--------------------------------------------------------------------------------
 1 | #ifndef _ASM_X86_INTEL_FAMILY_H
 2 | #define _ASM_X86_INTEL_FAMILY_H
 3 | 
 4 | /*
 5 |  * "Big Core" Processors (Branded as Core, Xeon, etc...)
 6 |  *
 7 |  * The "_X" parts are generally the EP and EX Xeons, or the
 8 |  * "Extreme" ones, like Broadwell-E.
 9 |  *
10 |  * Things ending in "2" are usually because we have no better
11 |  * name for them.  There's no processor called "SILVERMONT2".
12 |  */
13 | 
14 | #define INTEL_FAM6_CORE_YONAH		0x0E
15 | #define INTEL_FAM6_CORE2_MEROM		0x0F
16 | #define INTEL_FAM6_CORE2_MEROM_L	0x16
17 | #define INTEL_FAM6_CORE2_PENRYN		0x17
18 | #define INTEL_FAM6_CORE2_DUNNINGTON	0x1D
19 | 
20 | #define INTEL_FAM6_NEHALEM			0x1E
21 | #define INTEL_FAM6_NEHALEM_G		0x1F /* Auburndale / Havendale */
22 | #define INTEL_FAM6_NEHALEM_EP		0x1A
23 | #define INTEL_FAM6_NEHALEM_EX		0x2E
24 | #define INTEL_FAM6_WESTMERE			0x25
25 | #define INTEL_FAM6_WESTMERE_EP		0x2C
26 | #define INTEL_FAM6_WESTMERE_EX		0x2F
27 | 
28 | #define INTEL_FAM6_SANDYBRIDGE		0x2A
29 | #define INTEL_FAM6_SANDYBRIDGE_X	0x2D
30 | #define INTEL_FAM6_IVYBRIDGE		0x3A
31 | #define INTEL_FAM6_IVYBRIDGE_X		0x3E
32 | 
33 | #define INTEL_FAM6_HASWELL_CORE		0x3C
34 | #define INTEL_FAM6_HASWELL_X		0x3F
35 | #define INTEL_FAM6_HASWELL_ULT		0x45
36 | #define INTEL_FAM6_HASWELL_GT3E		0x46
37 | 
38 | #define INTEL_FAM6_BROADWELL_CORE	0x3D
39 | #define INTEL_FAM6_BROADWELL_XEON_D	0x56
40 | #define INTEL_FAM6_BROADWELL_GT3E	0x47
41 | #define INTEL_FAM6_BROADWELL_X		0x4F
42 | #define INTEL_FAM6_BROADWELL_XEON_D	0x56
43 | 
44 | #define INTEL_FAM6_SKYLAKE_MOBILE	0x4E
45 | #define INTEL_FAM6_SKYLAKE_DESKTOP	0x5E
46 | #define INTEL_FAM6_SKYLAKE_X		0x55
47 | #define INTEL_FAM6_KABYLAKE_MOBILE	0x8E
48 | #define INTEL_FAM6_KABYLAKE_DESKTOP	0x9E
49 | 
50 | #define INTEL_FAM6_CANNONLAKE_CORE	0x66
51 | 
52 | /* "Small Core" Processors (Atom) */
53 | 
54 | #define INTEL_FAM6_ATOM_PINEVIEW	0x1C
55 | #define INTEL_FAM6_ATOM_LINCROFT	0x26
56 | #define INTEL_FAM6_ATOM_PENWELL		0x27
57 | #define INTEL_FAM6_ATOM_CLOVERVIEW	0x35
58 | #define INTEL_FAM6_ATOM_CEDARVIEW	0x36
59 | #define INTEL_FAM6_ATOM_SILVERMONT1	0x37 /* BayTrail/BYT / Valleyview */
60 | #define INTEL_FAM6_ATOM_SILVERMONT2	0x4D /* Avaton/Rangely */
61 | #define INTEL_FAM6_ATOM_AIRMONT		0x4C /* CherryTrail / Braswell */
62 | #define INTEL_FAM6_ATOM_MERRIFIELD	0x4A /* Tangier */
63 | #define INTEL_FAM6_ATOM_MOOREFIELD	0x5A /* Anniedale */
64 | #define INTEL_FAM6_ATOM_GOLDMONT	0x5C
65 | #define INTEL_FAM6_ATOM_GEMINI_LAKE	0x7A
66 | #define INTEL_FAM6_ATOM_DENVERTON	0x5F /* Goldmont Microserver */
67 | 
68 | /* Xeon Phi */
69 | 
70 | #define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */
71 | #define INTEL_FAM6_XEON_PHI_KNM		0x85 /* Knights Mill */
72 | 
73 | #endif /* _ASM_X86_INTEL_FAMILY_H */
74 | 


--------------------------------------------------------------------------------
/AppleIntelRegisterDumper/AppleIntelRegisterDumper.h:
--------------------------------------------------------------------------------
   1 | 
   2 | /*
   3 |  * Copyright © 2006,2009 Intel Corporation
   4 |  *
   5 |  * Permission is hereby granted, free of charge, to any person obtaining a
   6 |  * copy of this software and associated documentation files (the "Software"),
   7 |  * to deal in the Software without restriction, including without limitation
   8 |  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 |  * and/or sell copies of the Software, and to permit persons to whom the
  10 |  * Software is furnished to do so, subject to the following conditions:
  11 |  *
  12 |  * The above copyright notice and this permission notice (including the next
  13 |  * paragraph) shall be included in all copies or substantial portions of the
  14 |  * Software.
  15 |  *
  16 |  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 |  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 |  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 |  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 |  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 |  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22 |  * SOFTWARE.
  23 |  *
  24 |  * Authors:
  25 |  *
  26 |  *    Eric Anholt <eric@anholt.net>
  27 |  *    Pike R. Alpha <pikeralpha@yahoo.com> (OS X port)
  28 |  *
  29 |  */
  30 | 
  31 | #include "intel_reg.h"
  32 | #include "intel_chipset.h"
  33 | 
  34 | #define DEBUGSTRING(func) void func(char *result, int len, UInt32 reg, UInt32 val)
  35 | 
  36 | #define DEFINEREG(reg) { reg, #reg, NULL, 0 }
  37 | #define DEFINEREG_16BIT(reg) { reg, #reg, i830_16bit_func, 0 }
  38 | #define DEFINEREG2(reg, func) { reg, #reg, func, 0 }
  39 | 
  40 | #define DEFINE_FUNC_DUMP(func) void func(struct reg_debug *regs, uint32_t count)
  41 | #define DEFINE_FUNC_VOID(func) void func(void)
  42 | 
  43 | #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
  44 | #define intel_dump_regs(regs) dumpRegisters(regs, ARRAY_SIZE(regs))
  45 | 
  46 | static uint32_t devid = 0;
  47 | 
  48 | UInt64 gMMIOAddress	= 0;
  49 | 
  50 | struct reg_debug
  51 | {
  52 | 	UInt32 reg;
  53 | 	const char *name;
  54 | 	void (*debug_output) (char *result, int len, UInt32 reg, UInt32 val);
  55 | 	UInt32 val;
  56 | };
  57 | 
  58 | //------------------------------------------------------------------------------
  59 | 
  60 | DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)
  61 | {
  62 | 	const char *enable, *port, *mode, *bpc, *vsync, *hsync, *edp_input;
  63 | 	const char *width;
  64 | 
  65 | 	enable = (val & (1<<31)) ? "enabled" : "disabled";
  66 | 	
  67 | 	switch ((val >> 28) & 7)
  68 | 	{
  69 | 		case 0:
  70 | 			port = "no port";
  71 | 			break;
  72 | 		case 1:
  73 | 			port = "DDIB";
  74 | 			break;
  75 | 		case 2:
  76 | 			port = "DDIC";
  77 | 			break;
  78 | 		case 3:
  79 | 			port = "DDID";
  80 | 			break;
  81 | 		case 4:
  82 | 			port = "DDIE";
  83 | 			break;
  84 | 		default:
  85 | 			port = "port reserved";
  86 | 			break;
  87 | 	}
  88 | 
  89 | 	switch ((val >> 24) & 7)
  90 | 	{
  91 | 		case 0:
  92 | 			mode = "HDMI";
  93 | 			break;
  94 | 		case 1:
  95 | 			mode = "DVI";
  96 | 			break;
  97 | 		case 2:
  98 | 			mode = "DP SST";
  99 | 			break;
 100 | 		case 3:
 101 | 			mode = "DP MST";
 102 | 			break;
 103 | 		case 4:
 104 | 			mode = "FDI";
 105 | 			break;
 106 | 		case 5:
 107 | 		default:
 108 | 			mode = "mode reserved";
 109 | 			break;
 110 | 	}
 111 | 
 112 | 	switch ((val >> 20) & 7)
 113 | 	{
 114 | 		case 0:
 115 | 			bpc = "8 bpc";
 116 | 			break;
 117 | 		case 1:
 118 | 			bpc = "10 bpc";
 119 | 			break;
 120 | 		case 2:
 121 | 			bpc = "6 bpc";
 122 | 			break;
 123 | 		case 3:
 124 | 			bpc = "12 bpc";
 125 | 			break;
 126 | 		default:
 127 | 			bpc = "bpc reserved";
 128 | 			break;
 129 | 	}
 130 | 
 131 | 	hsync = (val & (1<<16)) ? "+HSync" : "-HSync";
 132 | 	vsync = (val & (1<<17)) ? "+VSync" : "-VSync";
 133 | 
 134 | 	switch ((val >> 12) & 7)
 135 | 	{
 136 | 		case 0:
 137 | 			edp_input = "EDP A ON";
 138 | 			break;
 139 | 		case 4:
 140 | 			edp_input = "EDP A ONOFF";
 141 | 			break;
 142 | 		case 5:
 143 | 			edp_input = "EDP B ONOFF";
 144 | 			break;
 145 | 		case 6:
 146 | 			edp_input = "EDP C ONOFF";
 147 | 			break;
 148 | 		default:
 149 | 			edp_input = "EDP input reserved";
 150 | 			break;
 151 | 	}
 152 | 
 153 | 	switch ((val >> 1) & 7)
 154 | 	{
 155 | 		case 0:
 156 | 			width = "x1";
 157 | 			break;
 158 | 		case 1:
 159 | 			width = "x2";
 160 | 			break;
 161 | 		case 3:
 162 | 			width = "x4";
 163 | 			break;
 164 | 		default:
 165 | 			width = "reserved width";
 166 | 			break;
 167 | 	}
 168 | 
 169 | 	snprintf(result, len, "%s, %s, %s, %s, %s, %s, %s, %s", enable, port, mode, bpc, vsync, hsync, edp_input, width);
 170 | }
 171 | 
 172 | //------------------------------------------------------------------------------
 173 | 
 174 | DEBUGSTRING(hsw_debug_ddi_buf_ctl)
 175 | {
 176 | 	const char *enable, *reversal, *width, *detected;
 177 | 
 178 | 	enable = (val & (1<<31)) ? "enabled" : "disabled";
 179 | 	reversal = (val & (1<<16)) ? "reversed" : "not reversed";
 180 | 
 181 | 	switch ((val >> 1) & 7)
 182 | 	{
 183 | 		case 0:
 184 | 			width = "x1";
 185 | 			break;
 186 | 		case 1:
 187 | 			width = "x2";
 188 | 			break;
 189 | 		case 3:
 190 | 			width = "x4";
 191 | 			break;
 192 | 		default:
 193 | 			width = "reserved";
 194 | 			break;
 195 | 	}
 196 | 
 197 | 	detected = (val & 1) ? "detected" : "not detected";
 198 | 
 199 | 	snprintf(result, len, "%s %s %s %s", enable, reversal, width, detected);
 200 | }
 201 | 
 202 | //------------------------------------------------------------------------------
 203 | 
 204 | DEBUGSTRING(hsw_debug_port_clk_sel)
 205 | {
 206 | 	const char *clock = NULL;
 207 | 
 208 | 	switch ((val >> 29 ) & 7)
 209 | 	{
 210 | 		case 0:
 211 | 			clock = "LCPLL 2700";
 212 | 			break;
 213 | 		case 1:
 214 | 			clock = "LCPLL 1350";
 215 | 			break;
 216 | 		case 2:
 217 | 			clock = "LCPLL 810";
 218 | 			break;
 219 | 		case 3:
 220 | 			clock = "SPLL";
 221 | 			break;
 222 | 		case 4:
 223 | 			clock = "WRPLL 1";
 224 | 			break;
 225 | 		case 5:
 226 | 			clock = "WRPLL 2";
 227 | 			break;
 228 | 		case 6:
 229 | 			clock = "Reserved";
 230 | 			break;
 231 | 		case 7:
 232 | 			clock = "None";
 233 | 			break;
 234 | 	}
 235 | 
 236 | 	snprintf(result, len, "%s", clock);
 237 | }
 238 | 
 239 | //------------------------------------------------------------------------------
 240 | 
 241 | DEBUGSTRING(hsw_debug_pipe_clk_sel)
 242 | {
 243 | 	const char *clock;
 244 | 
 245 | 	switch ((val >> 29) & 7)
 246 | 	{
 247 | 		case 0:
 248 | 			clock = "None";
 249 | 			break;
 250 | 		case 2:
 251 | 			clock = "DDIB";
 252 | 			break;
 253 | 		case 3:
 254 | 			clock = "DDIC";
 255 | 			break;
 256 | 		case 4:
 257 | 			clock = "DDID";
 258 | 			break;
 259 | 		case 5:
 260 | 			clock = "DDIE";
 261 | 			break;
 262 | 		default:
 263 | 			clock = "Reserved";
 264 | 			break;
 265 | 	}
 266 | 
 267 | 	snprintf(result, len, "%s", clock);
 268 | }
 269 | 
 270 | //------------------------------------------------------------------------------
 271 | 
 272 | DEBUGSTRING(hsw_debug_sfuse_strap)
 273 | {
 274 | 	const char *display, *crt, *lane_reversal, *portb, *portc, *portd;
 275 | 
 276 | 	display = (val & (1<<7)) ? "disabled" : "enabled";
 277 | 	crt = (val & (1<<6)) ? "yes" : "no";
 278 | 	lane_reversal = (val & (1<<4)) ? "yes" : "no";
 279 | 	portb = (val & (1<<2)) ? "yes" : "no";
 280 | 	portc = (val & (1<<1)) ? "yes" : "no";
 281 | 	portd = (val & (1<<0)) ? "yes" : "no";
 282 | 
 283 | 	snprintf(result, len, "display %s, crt %s, lane reversal %s, "
 284 | 			 "port b %s, port c %s, port d %s", display, crt, lane_reversal,
 285 | 			 portb, portc, portd);
 286 | }
 287 | 
 288 | //------------------------------------------------------------------------------
 289 | 
 290 | DEBUGSTRING(i830_debug_yxminus1)
 291 | {
 292 | 	snprintf(result, len, "%d, %d", ((val & 0xffff0000) >> 16) + 1, (val & 0xffff) + 1);
 293 | }
 294 | 
 295 | //------------------------------------------------------------------------------
 296 | 
 297 | DEBUGSTRING(i830_debug_dspcntr)
 298 | {
 299 | 	const char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
 300 | 	char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A';
 301 | 
 302 | 	if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid))
 303 | 	{
 304 | 		snprintf(result, len, "%s", enabled);
 305 | 	}
 306 | 	else
 307 | 	{
 308 | 		snprintf(result, len, "%s, pipe %c", enabled, plane);
 309 | 	}
 310 | }
 311 | 
 312 | //------------------------------------------------------------------------------
 313 | 
 314 | DEBUGSTRING(ironlake_debug_dspstride)
 315 | {
 316 | 	snprintf(result, len, "%d", val >> 6);
 317 | }
 318 | 
 319 | //------------------------------------------------------------------------------
 320 | 
 321 | DEBUGSTRING(i830_debug_xyminus1)
 322 | {
 323 | 	snprintf(result, len, "%d, %d", (val & 0xffff) + 1, ((val & 0xffff0000) >> 16) + 1);
 324 | }
 325 | 
 326 | //------------------------------------------------------------------------------
 327 | 
 328 | DEBUGSTRING(i830_debug_xy)
 329 | {
 330 | 	snprintf(result, len, "%d, %d", (val & 0xffff), ((val & 0xffff0000) >> 16));
 331 | }
 332 | 
 333 | //------------------------------------------------------------------------------
 334 | 
 335 | DEBUGSTRING(i830_debug_pipeconf)
 336 | {
 337 | 	const char *enabled = val & PIPEACONF_ENABLE ? "enabled" : "disabled";
 338 | 	const char *bit30 = NULL;
 339 | 	const char *interlace = NULL;
 340 |     int interlace_mode;
 341 | 	char buf[256];
 342 | 	int buf_len;
 343 | 
 344 | 	if (IS_965(devid))
 345 | 	{
 346 | 		bit30 = val & I965_PIPECONF_ACTIVE ? "active" : "inactive";
 347 | 	}
 348 | 	else
 349 | 	{
 350 | 		bit30 = val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
 351 | 	}
 352 | 
 353 | 	if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid))
 354 | 	{
 355 | 		
 356 |         
 357 |         if (IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || IS_BROADWELL(devid) || IS_GEN9(devid))
 358 |         {
 359 |             interlace_mode = (val >> 21) & 3;
 360 |         }
 361 |         else
 362 |         {
 363 |             interlace_mode = (val >> 21) & 7;
 364 |         }
 365 | 
 366 | 		buf_len = snprintf(buf, sizeof(buf), "%s, %s", enabled, bit30);
 367 | 
 368 | 		switch (interlace_mode)
 369 | 		{
 370 | 			case 0:
 371 | 				interlace = "pf-pd";
 372 | 				break;
 373 | 			case 1:
 374 | 				interlace = "pf-id";
 375 | 				break;
 376 | 			case 3:
 377 | 				interlace = "if-id";
 378 | 				break;
 379 | 			case 4:
 380 | 				interlace = "if-id-dbl";
 381 | 				break;
 382 | 			case 5:
 383 | 				interlace = "pf-id-dbl";
 384 | 				break;
 385 | 			default:
 386 | 				interlace = "rsvd";
 387 | 				break;
 388 | 		}
 389 | 
 390 | 		if (buf_len < sizeof(buf))
 391 | 		{
 392 | 			buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, ", %s", interlace);
 393 | 		}
 394 | 		
 395 | 	}
 396 | 	else if (IS_GEN4(devid) || IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))
 397 | 	{
 398 | 		switch ((val >> 21) & 7)
 399 | 		{
 400 | 			case 0:
 401 | 			case 1:
 402 | 			case 2:
 403 | 			case 3:
 404 | 				interlace = "progressive";
 405 | 				break;
 406 | 			case 4:
 407 | 				interlace = "interlaced embedded";
 408 | 				break;
 409 | 			case 5:
 410 | 				interlace = "interlaced";
 411 | 				break;
 412 | 			case 6:
 413 | 				interlace = "interlaced sdvo";
 414 | 				break;
 415 | 			case 7:
 416 | 				interlace = "interlaced legacy";
 417 | 				break;
 418 | 		}
 419 | 
 420 | 		if (buf_len < sizeof(buf))
 421 | 		{
 422 | 			buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, ", %s", interlace);
 423 | 		}
 424 | 	}
 425 | 	
 426 | 	if (IS_HASWELL(devid) || IS_IVYBRIDGE(devid) || IS_GEN6(devid) || IS_GEN5(devid))
 427 | 	{
 428 | 		const char *rotation = NULL;
 429 | 
 430 | 		switch ((val >> 14) & 3)
 431 | 		{
 432 | 			case 0:
 433 | 				rotation = "rotate 0";
 434 | 				break;
 435 | 			case 1:
 436 | 				rotation = "rotate 90";
 437 | 				break;
 438 | 			case 2:
 439 | 				rotation = "rotate 180";
 440 | 				break;
 441 | 			case 3:
 442 | 				rotation = "rotate 270";
 443 | 				break;
 444 | 		}
 445 | 
 446 | 		if (buf_len < sizeof(buf))
 447 | 		{
 448 | 			buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, ", %s", rotation);
 449 | 		}
 450 | 	}
 451 | 
 452 | 	if (IS_IVYBRIDGE(devid) || IS_GEN6(devid) || IS_GEN5(devid))
 453 | 	{
 454 | 		const char *bpc = NULL;
 455 | 
 456 | 		switch (val & (7 << 5))
 457 | 		{
 458 | 			case PIPECONF_8BPP:
 459 | 				bpc = "8bpc";
 460 | 				break;
 461 | 			case PIPECONF_10BPP:
 462 | 				bpc = "10bpc";
 463 | 				break;
 464 | 			case PIPECONF_6BPP:
 465 | 				bpc = "6bpc";
 466 | 				break;
 467 | 			case PIPECONF_12BPP:
 468 | 				bpc = "12bpc";
 469 | 				break;
 470 | 			default:
 471 | 				bpc = "invalid bpc";
 472 | 				break;
 473 | 		}
 474 | 		
 475 | 		if (buf_len < sizeof(buf))
 476 | 		{
 477 | 			buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, ", %s", bpc);
 478 | 		}
 479 | 	}
 480 | 
 481 | 	snprintf(result, len, "%s", buf);
 482 | }
 483 | 
 484 | //------------------------------------------------------------------------------
 485 | 
 486 | DEBUGSTRING(i830_debug_hvtotal)
 487 | {
 488 | 	snprintf(result, len, "%d active, %d total", (val & 0xffff) + 1, ((val & 0xffff0000) >> 16) + 1);
 489 | }
 490 | 
 491 | //------------------------------------------------------------------------------
 492 | 
 493 | DEBUGSTRING(i830_debug_hvsyncblank)
 494 | {
 495 | 	snprintf(result, len, "%d start, %d end", (val & 0xffff) + 1, ((val & 0xffff0000) >> 16) + 1);
 496 | }
 497 | 
 498 | //------------------------------------------------------------------------------
 499 | 
 500 | DEBUGSTRING(ironlake_debug_m_tu)
 501 | {
 502 | 	snprintf(result, len, "TU %d, val 0x%x %d", (val >> 25) + 1, val & 0xffffff, val & 0xffffff);
 503 | }
 504 | 
 505 | //------------------------------------------------------------------------------
 506 | 
 507 | DEBUGSTRING(ironlake_debug_n)
 508 | {
 509 | 	snprintf(result, len, "val 0x%x %d", val & 0xffffff, val & 0xffffff);
 510 | }
 511 | 
 512 | //------------------------------------------------------------------------------
 513 | 
 514 | DEBUGSTRING(ironlake_debug_panel_fitting)
 515 | {
 516 | 	const char *vadapt = NULL;
 517 | 	const char *filter_sel = NULL;
 518 | 
 519 | 	switch (val & (3 << 25))
 520 | 	{
 521 | 		case 0:
 522 | 			vadapt = "least";
 523 | 			break;
 524 | 		case (1 << 25):
 525 | 			vadapt = "moderate";
 526 | 			break;
 527 | 		case (2 << 25):
 528 | 			vadapt = "reserved";
 529 | 			break;
 530 | 		case (3 << 25):
 531 | 			vadapt = "most";
 532 | 			break;
 533 | 	}
 534 | 
 535 | 	switch (val & (3 << 23))
 536 | 	{
 537 | 		case 0:
 538 | 			filter_sel = "programmed";
 539 | 			break;
 540 | 		case (1 << 23):
 541 | 			filter_sel = "hardcoded";
 542 | 			break;
 543 | 		case (2 << 23):
 544 | 			filter_sel = "edge_enhance";
 545 | 			break;
 546 | 		case (3 << 23):
 547 | 			filter_sel = "edge_soften";
 548 | 			break;
 549 | 	}
 550 | 
 551 | 	snprintf(result, len,
 552 | 			 "%s, auto_scale %s, auto_scale_cal %s, v_filter %s, vadapt %s, mode %s, filter_sel %s,"
 553 | 			 "chroma pre-filter %s, vert3tap %s, v_inter_invert %s",
 554 | 			 val & PF_ENABLE ? "enable" : "disable",
 555 | 			 val & (1 << 30) ? "no" : "yes",
 556 | 			 val & (1 << 29) ? "yes" : "no",
 557 | 			 val & (1 << 28) ? "bypass" : "enable",
 558 | 			 val & (1 << 27) ? "enable" : "disable",
 559 | 			 vadapt, filter_sel,
 560 | 			 val & (1 << 22) ? "enable" : "disable",
 561 | 			 val & (1 << 21) ? "force" : "auto",
 562 | 			 val & (1 << 20) ? "field 0" : "field 1");
 563 | }
 564 | 
 565 | //------------------------------------------------------------------------------
 566 | 
 567 | DEBUGSTRING(ironlake_debug_panel_fitting_2)
 568 | {
 569 | 	snprintf(result, len, "vscale %f", val / (float) (1<<15));
 570 | }
 571 | 
 572 | //------------------------------------------------------------------------------
 573 | 
 574 | DEBUGSTRING(ironlake_debug_panel_fitting_3)
 575 | {
 576 | 	snprintf(result, len, "vscale initial phase %f", val / (float) (1<<15));
 577 | }
 578 | 
 579 | //------------------------------------------------------------------------------
 580 | 
 581 | DEBUGSTRING(ironlake_debug_panel_fitting_4)
 582 | {
 583 | 	snprintf(result, len, "hscale %f", val / (float) (1<<15));
 584 | }
 585 | 
 586 | //------------------------------------------------------------------------------
 587 | 
 588 | DEBUGSTRING(ironlake_debug_pf_win)
 589 | {
 590 | 	int a = (val >> 16) & 0x1fff;
 591 | 	int b = val & 0xfff;
 592 | 
 593 | 	snprintf(result, len, "%d, %d", a, b);
 594 | }
 595 | 
 596 | //------------------------------------------------------------------------------
 597 | 
 598 | DEBUGSTRING(ironlake_debug_transconf)
 599 | {
 600 | 	const char *enable = val & TRANS_ENABLE ? "enable" : "disable";
 601 | 	const char *state = val & TRANS_STATE_ENABLE ? "active" : "inactive";
 602 | 	const char *interlace;
 603 | 	
 604 | 	switch ((val >> 21) & 7)
 605 | 	{
 606 | 		case 0:
 607 | 			interlace = "progressive";
 608 | 			break;
 609 | 		case 2:
 610 | 			if (IS_GEN5(devid))
 611 | 			{
 612 | 				interlace = "interlaced sdvo";
 613 | 			}
 614 | 			else
 615 | 			{
 616 | 				interlace = "rsvd";
 617 | 			}
 618 | 			break;
 619 | 		case 3:
 620 | 			interlace = "interlaced";
 621 | 			break;
 622 | 		default:
 623 | 			interlace = "rsvd";
 624 | 	}
 625 | 
 626 | 	snprintf(result, len, "%s, %s, %s", enable, state, interlace);
 627 | }
 628 | 
 629 | //------------------------------------------------------------------------------
 630 | 
 631 | DEBUGSTRING(ironlake_debug_fdi_rx_misc)
 632 | {
 633 | 	snprintf(result, len, "FDI Delay %d", val & ((1 << 13) - 1));
 634 | }
 635 | 
 636 | //------------------------------------------------------------------------------
 637 | 
 638 | DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl2)
 639 | {
 640 | 	int enable, blinking, granularity;
 641 | 	const char *pipe = NULL;
 642 | 
 643 | 	enable = (val >> 31) & 1;
 644 | 
 645 | 	if (IS_GEN5(devid) || IS_GEN6(devid))
 646 | 	{
 647 | 		pipe = ((val >> 29) & 1) ? "B" : "A";
 648 | 	}
 649 | 	else
 650 | 	{
 651 | 		switch ((val >> 29) & 3)
 652 | 		{
 653 | 			case 0:
 654 | 				pipe = "A";
 655 | 				break;
 656 | 			case 1:
 657 | 				pipe = "B";
 658 | 				break;
 659 | 			case 2:
 660 | 				pipe = "C";
 661 | 				break;
 662 | 			case 3:
 663 | 				if (IS_IVYBRIDGE(devid))
 664 | 				{
 665 | 					pipe = "reserved";
 666 | 				}
 667 | 				else
 668 | 				{
 669 | 					pipe = "EDP";
 670 | 				}
 671 | 				break;
 672 | 		}
 673 | 	}
 674 | 
 675 | 	if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid))
 676 | 	{
 677 | 		snprintf(result, len, "enable %d, pipe %s", enable, pipe);
 678 | 	}
 679 | 	else
 680 | 	{
 681 | 		blinking = (val >> 28) & 1;
 682 | 		granularity = ((val >> 27) & 1) ? 8 : 128;
 683 | 
 684 | 		snprintf(result, len, "enable %d, pipe %s, blinking %d, "
 685 | 				 "granularity %d", enable, pipe, blinking, granularity);
 686 | 	}
 687 | }
 688 | 
 689 | //------------------------------------------------------------------------------
 690 | 
 691 | DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl)
 692 | {
 693 | 	int cycle, freq;
 694 | 
 695 | 	cycle = (val & 0xFFFF);
 696 | 	
 697 | 	if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid))
 698 | 	{
 699 | 		snprintf(result, len, "cycle %d", cycle);
 700 | 	}
 701 | 	else
 702 | 	{
 703 | 		freq = (val >> 16) & 0xFFFF;
 704 | 
 705 | 		snprintf(result, len, "cycle %d, freq %d", cycle, freq);
 706 | 	}
 707 | }
 708 | 
 709 | //------------------------------------------------------------------------------
 710 | 
 711 | DEBUGSTRING(ibx_debug_blc_pwm_ctl1)
 712 | {
 713 | 	int enable, override, inverted_polarity;
 714 | 
 715 | 	enable = (val >> 31) & 1;
 716 | 	override = (val >> 30) & 1;
 717 | 	inverted_polarity = (val >> 29) & 1;
 718 | 
 719 | 	snprintf(result, len, "enable %d, override %d, inverted polarity %d",
 720 | 	enable, override, inverted_polarity);
 721 | }
 722 | 
 723 | //------------------------------------------------------------------------------
 724 | 
 725 | DEBUGSTRING(ibx_debug_blc_pwm_ctl2)
 726 | {
 727 | 	int freq, cycle;
 728 | 
 729 | 	freq = (val >> 16) & 0xFFFF;
 730 | 	cycle = val & 0xFFFF;
 731 | 
 732 | 	snprintf(result, len, "freq %d, cycle %d", freq, cycle);
 733 | }
 734 | 
 735 | //------------------------------------------------------------------------------
 736 | 
 737 | DEBUGSTRING(hsw_debug_blc_misc_ctl)
 738 | {
 739 | 	const char *sel;
 740 | 
 741 | 	sel = (val & 1) ? "PWM1-CPU PWM2-PCH" : "PWM1-PCH PWM2-CPU";
 742 | 
 743 | 	snprintf(result, len, "%s", sel);
 744 | }
 745 | 
 746 | //------------------------------------------------------------------------------
 747 | 
 748 | DEBUGSTRING(hsw_debug_util_pin_ctl)
 749 | {
 750 | 	int enable, data, inverted_polarity;
 751 | 	const char *transcoder = NULL;
 752 | 	const char *mode = NULL;
 753 | 
 754 | 	enable = (val >> 31) & 1;
 755 | 
 756 | 	switch ((val >> 29) & 3)
 757 | 	{
 758 | 		case 0:
 759 | 			transcoder = "A";
 760 | 			break;
 761 | 		case 1:
 762 | 			transcoder = "B";
 763 | 			break;
 764 | 		case 2:
 765 | 			transcoder = "C";
 766 | 			break;
 767 | 		case 3:
 768 | 			transcoder = "EDP";
 769 | 			break;
 770 | 	}
 771 | 
 772 | 	switch ((val >> 24) & 0xF)
 773 | 	{
 774 | 		case 0:
 775 | 			mode = "data";
 776 | 			break;
 777 | 		case 1:
 778 | 			mode = "PWM";
 779 | 			break;
 780 | 		case 4:
 781 | 			mode = "Vblank";
 782 | 			break;
 783 | 		case 5:
 784 | 			mode = "Vsync";
 785 | 			break;
 786 | 		default:
 787 | 			mode = "reserved";
 788 | 			break;
 789 | 	}
 790 | 
 791 | 	data = (val >> 23) & 1;
 792 | 	inverted_polarity = (val >> 22) & 1;
 793 | 
 794 | 	snprintf(result, len, "enable %d, transcoder %s, mode %s, data %d "
 795 | 			 "inverted polarity %d", enable, transcoder, mode, data,
 796 | 			 inverted_polarity);
 797 | }
 798 | 
 799 | //------------------------------------------------------------------------------
 800 | 
 801 | DEBUGSTRING(i830_debug_pp_status)
 802 | {
 803 | 	const char *status = val & PP_ON ? "on" : "off";
 804 | 	const char *ready = val & PP_READY ? "ready" : "not ready";
 805 | 	const char *seq = "unknown";
 806 | 
 807 | 	switch (val & PP_SEQUENCE_MASK)
 808 | 	{
 809 | 		case PP_SEQUENCE_NONE:
 810 | 			seq = "idle";
 811 | 			break;
 812 | 		case PP_SEQUENCE_ON:
 813 | 			seq = "on";
 814 | 			break;
 815 | 		case PP_SEQUENCE_OFF:
 816 | 			seq = "off";
 817 | 			break;
 818 | 	}
 819 | 
 820 | 	snprintf(result, len, "%s, %s, sequencing %s", status, ready, seq);
 821 | }
 822 | 
 823 | //------------------------------------------------------------------------------
 824 | 
 825 | DEBUGSTRING(ilk_debug_pp_control)
 826 | {
 827 | 	snprintf(result, len, "blacklight %s, %spower down on reset, panel %s",
 828 | 			 (val & (1 << 2)) ? "enabled" : "disabled",
 829 | 			 (val & (1 << 1)) ? "" : "do not ",
 830 | 			 (val & (1 << 0)) ? "on" : "off");
 831 | }
 832 | 
 833 | //------------------------------------------------------------------------------
 834 | 
 835 | DEBUGSTRING(hsw_debug_sinterrupt)
 836 | {
 837 | 	int portd, portc, portb, crt;
 838 | 	
 839 | 	portd = (val >> 23) & 1;
 840 | 	portc = (val >> 22) & 1;
 841 | 	portb = (val >> 21) & 1;
 842 | 	crt = (val >> 19) & 1;
 843 | 	
 844 | 	snprintf(result, len, "port d:%d, port c:%d, port b:%d, crt:%d", portd, portc, portb, crt);
 845 | }
 846 | 
 847 | //------------------------------------------------------------------------------
 848 | 
 849 | DEBUGSTRING(i830_debug_vgacntrl)
 850 | {
 851 | 	snprintf(result, len, "%s", val & VGA_DISP_DISABLE ? "disabled" : "enabled");
 852 | }
 853 | 
 854 | //------------------------------------------------------------------------------
 855 | 
 856 | DEBUGSTRING(ironlake_debug_rr_hw_ctl)
 857 | {
 858 | 	snprintf(result, len, "low %d, high %d", val & RR_HW_LOW_POWER_FRAMES_MASK, (val & RR_HW_HIGH_POWER_FRAMES_MASK) >> 8);
 859 | }
 860 | 
 861 | //------------------------------------------------------------------------------
 862 | 
 863 | DEBUGSTRING(ironlake_debug_dref_ctl)
 864 | {
 865 | 	const char *cpu_source;
 866 | 	const char *ssc_source = val & DREF_SSC_SOURCE_ENABLE ? "enable" : "disable";
 867 | 	const char *nonspread_source =
 868 | 	val & DREF_NONSPREAD_SOURCE_ENABLE ? "enable" : "disable";
 869 | 	const char *superspread_source =
 870 | 	val & DREF_SUPERSPREAD_SOURCE_ENABLE ? "enable" : "disable";
 871 | 	const char *ssc4_mode =
 872 | 	val & DREF_SSC4_CENTERSPREAD ? "centerspread" : "downspread";
 873 | 	const char *ssc1 = val & DREF_SSC1_ENABLE ? "enable" : "disable";
 874 | 	const char *ssc4 = val & DREF_SSC4_ENABLE ? "enable" : "disable";
 875 | 	
 876 | 	switch (val & DREF_CPU_SOURCE_OUTPUT_NONSPREAD)
 877 | 	{
 878 | 		case DREF_CPU_SOURCE_OUTPUT_DISABLE:
 879 | 			cpu_source = "disable";
 880 | 			break;
 881 | 		case DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD:
 882 | 			cpu_source = "downspread";
 883 | 			break;
 884 | 		case DREF_CPU_SOURCE_OUTPUT_NONSPREAD:
 885 | 			cpu_source = "nonspread";
 886 | 			break;
 887 | 		default:
 888 | 			cpu_source = "reserved";
 889 | 	}
 890 | 	snprintf(result, len, "cpu source %s, ssc_source %s, nonspread_source %s, "
 891 | 			 "superspread_source %s, ssc4_mode %s, ssc1 %s, ssc4 %s",
 892 | 			 cpu_source, ssc_source, nonspread_source,
 893 | 			 superspread_source, ssc4_mode, ssc1, ssc4);
 894 | }
 895 | 
 896 | //------------------------------------------------------------------------------
 897 | 
 898 | DEBUGSTRING(ironlake_debug_rawclk_freq)
 899 | {
 900 | 	const char *tp1 = NULL, *tp2 = NULL;
 901 | 	
 902 | 	switch (val & FDL_TP1_TIMER_MASK)
 903 | 	{
 904 | 		case 0:
 905 | 			tp1 = "0.5us";
 906 | 			break;
 907 | 		case (1 << 12):
 908 | 			tp1 = "1.0us";
 909 | 			break;
 910 | 		case (2 << 12):
 911 | 			tp1 = "2.0us";
 912 | 			break;
 913 | 		case (3 << 12):
 914 | 			tp1 = "4.0us";
 915 | 			break;
 916 | 	}
 917 | 
 918 | 	switch (val & FDL_TP2_TIMER_MASK)
 919 | 	{
 920 | 		case 0:
 921 | 			tp2 = "1.5us";
 922 | 			break;
 923 | 		case (1 << 10):
 924 | 			tp2 = "3.0us";
 925 | 			break;
 926 | 		case (2 << 10):
 927 | 			tp2 = "6.0us";
 928 | 			break;
 929 | 		case (3 << 10):
 930 | 			tp2 = "12.0us";
 931 | 			break;
 932 | 	}
 933 | 
 934 | 	snprintf(result, len, "FDL_TP1 timer %s, FDL_TP2 timer %s, freq %d", tp1, tp2, val & RAWCLK_FREQ_MASK);
 935 | }
 936 | 
 937 | DEBUGSTRING(snb_debug_dpll_sel)
 938 | {
 939 | 	const char *transa, *transb;
 940 | 	const char *dplla = NULL, *dpllb = NULL;
 941 | 
 942 | 	if (HAS_CPT)
 943 | 	{
 944 | 		if (val & TRANSA_DPLL_ENABLE)
 945 | 		{
 946 | 			transa = "enable";
 947 | 
 948 | 			if (val & TRANSA_DPLLB_SEL)
 949 | 			{
 950 | 				dplla = "B";
 951 | 			}
 952 | 			else
 953 | 			{
 954 | 				dplla = "A";
 955 | 			}
 956 | 		}
 957 | 		else
 958 | 		{
 959 | 			transa = "disable";
 960 | 		}
 961 | 
 962 | 		if (val & TRANSB_DPLL_ENABLE)
 963 | 		{
 964 | 			transb = "enable";
 965 | 
 966 | 			if (val & TRANSB_DPLLB_SEL)
 967 | 			{
 968 | 				dpllb = "B";
 969 | 			}
 970 | 			else
 971 | 			{
 972 | 				dpllb = "A";
 973 | 			}
 974 | 		}
 975 | 		else
 976 | 		{
 977 | 			transb = "disable";
 978 | 		}
 979 | 
 980 | 		snprintf(result, len, "TransA DPLL %s (DPLL %s), TransB DPLL %s (DPLL %s)", transa, dplla, transb, dpllb);
 981 | 	}
 982 | }
 983 | 
 984 | //------------------------------------------------------------------------------
 985 | 
 986 | DEBUGSTRING(ironlake_debug_pch_dpll)
 987 | {
 988 | 	const char *enable = val & DPLL_VCO_ENABLE ? "enable" : "disable";
 989 | 	const char *highspeed = val & DPLL_DVO_HIGH_SPEED ? "yes" : "no";
 990 | 	const char *mode = NULL;
 991 | 	const char *p2 = NULL;
 992 | 	int fpa0_p1, fpa1_p1;
 993 | 	const char *refclk = NULL;
 994 | 	int sdvo_mul;
 995 | 		
 996 | 	if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_LVDS)
 997 | 	{
 998 | 		mode = "LVDS";
 999 | 
1000 | 		if (val & DPLLB_LVDS_P2_CLOCK_DIV_7)
1001 | 		{
1002 | 			p2 = "Div 7";
1003 | 		}
1004 | 		else
1005 | 		{
1006 | 			p2 = "Div 14";
1007 | 		}
1008 | 	}
1009 | 	else if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_DAC_SERIAL)
1010 | 	{
1011 | 		mode = "Non-LVDS";
1012 | 
1013 | 		if (val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
1014 | 		{
1015 | 			p2 = "Div 5";
1016 | 		}
1017 | 		else
1018 | 		{
1019 | 			p2 = "Div 10";
1020 | 		}
1021 | 	}
1022 | 
1023 | 	fpa0_p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> 16);
1024 | 	fpa1_p1 = ffs((val & DPLL_FPA1_P1_POST_DIV_MASK));
1025 | 		
1026 | 	switch (val & PLL_REF_INPUT_MASK)
1027 | 	{
1028 | 		case PLL_REF_INPUT_DREFCLK:
1029 | 			refclk = "default 120Mhz";
1030 | 			break;
1031 | 		case PLL_REF_INPUT_SUPER_SSC:
1032 | 			refclk = "SuperSSC 120Mhz";
1033 | 			break;
1034 | 		case PLL_REF_INPUT_TVCLKINBC:
1035 | 			refclk = "SDVO TVClkIn";
1036 | 			break;
1037 | 		case PLLB_REF_INPUT_SPREADSPECTRUMIN:
1038 | 			refclk = "SSC";
1039 | 			break;
1040 | 		case PLL_REF_INPUT_DMICLK:
1041 | 			refclk = "DMI RefCLK";
1042 | 			break;
1043 | 	}
1044 | 		
1045 | 	sdvo_mul = ((val & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) >> 9) + 1;
1046 | 		
1047 | 	snprintf(result, len, "%s, sdvo high speed %s, mode %s, p2 %s, "
1048 | 			 "FPA0 P1 %d, FPA1 P1 %d, refclk %s, sdvo/hdmi mul %d",
1049 | 			 enable, highspeed, mode, p2, fpa0_p1, fpa1_p1, refclk, sdvo_mul);
1050 | }
1051 | 
1052 | //------------------------------------------------------------------------------
1053 | 
1054 | DEBUGSTRING(i830_debug_fp)
1055 | {
1056 | 	if (IS_IGD(devid))
1057 | 	{
1058 | 		snprintf(result, len, "n = %d, m1 = %d, m2 = %d",
1059 | 				 ffs((val & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1,
1060 | 				 ((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
1061 | 				 ((val & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT));
1062 | 	}
1063 | 
1064 | 	snprintf(result, len, "n = %d, m1 = %d, m2 = %d",
1065 | 			 ((val & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT),
1066 | 			 ((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
1067 | 			 ((val & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT));
1068 | }
1069 | 
1070 | //------------------------------------------------------------------------------
1071 | 
1072 | DEBUGSTRING(ironlake_debug_fdi_tx_ctl)
1073 | {
1074 | 	const char *train = NULL, *voltage = NULL, *pre_emphasis = NULL, *portw =
1075 | 	NULL;
1076 | 
1077 | 	switch (val & FDI_LINK_TRAIN_NONE)
1078 | 	{
1079 | 		case FDI_LINK_TRAIN_PATTERN_1:
1080 | 			train = "pattern_1";
1081 | 			break;
1082 | 		case FDI_LINK_TRAIN_PATTERN_2:
1083 | 			train = "pattern_2";
1084 | 			break;
1085 | 		case FDI_LINK_TRAIN_PATTERN_IDLE:
1086 | 			train = "pattern_idle";
1087 | 			break;
1088 | 		case FDI_LINK_TRAIN_NONE:
1089 | 			train = "not train";
1090 | 			break;
1091 | 	}
1092 | 
1093 | 	if (HAS_CPT)
1094 | 	{
1095 | 		/* SNB B0 */
1096 | 		switch (val & (0x3f << 22))
1097 | 		{
1098 | 			case FDI_LINK_TRAIN_400MV_0DB_SNB_B:
1099 | 				voltage = "0.4V";
1100 | 				pre_emphasis = "0dB";
1101 | 				break;
1102 | 			case FDI_LINK_TRAIN_400MV_6DB_SNB_B:
1103 | 				voltage = "0.4V";
1104 | 				pre_emphasis = "6dB";
1105 | 				break;
1106 | 			case FDI_LINK_TRAIN_600MV_3_5DB_SNB_B:
1107 | 				voltage = "0.6V";
1108 | 				pre_emphasis = "3.5dB";
1109 | 				break;
1110 | 			case FDI_LINK_TRAIN_800MV_0DB_SNB_B:
1111 | 				voltage = "0.8V";
1112 | 				pre_emphasis = "0dB";
1113 | 				break;
1114 | 		}
1115 | 	}
1116 | 	else
1117 | 	{
1118 | 		switch (val & (7 << 25))
1119 | 		{
1120 | 			case FDI_LINK_TRAIN_VOLTAGE_0_4V:
1121 | 				voltage = "0.4V";
1122 | 				break;
1123 | 			case FDI_LINK_TRAIN_VOLTAGE_0_6V:
1124 | 				voltage = "0.6V";
1125 | 				break;
1126 | 			case FDI_LINK_TRAIN_VOLTAGE_0_8V:
1127 | 				voltage = "0.8V";
1128 | 				break;
1129 | 			case FDI_LINK_TRAIN_VOLTAGE_1_2V:
1130 | 				voltage = "1.2V";
1131 | 				break;
1132 | 			default:
1133 | 				voltage = "reserved";
1134 | 		}
1135 | 		
1136 | 		switch (val & (7 << 22))
1137 | 		{
1138 | 			case FDI_LINK_TRAIN_PRE_EMPHASIS_NONE:
1139 | 				pre_emphasis = "none";
1140 | 				break;
1141 | 			case FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X:
1142 | 				pre_emphasis = "1.5x";
1143 | 				break;
1144 | 			case FDI_LINK_TRAIN_PRE_EMPHASIS_2X:
1145 | 				pre_emphasis = "2x";
1146 | 				break;
1147 | 			case FDI_LINK_TRAIN_PRE_EMPHASIS_3X:
1148 | 				pre_emphasis = "3x";
1149 | 				break;
1150 | 			default:
1151 | 				pre_emphasis = "reserved";
1152 | 		}
1153 | 		
1154 | 	}
1155 | 
1156 | 	switch (val & (7 << 19))
1157 | 	{
1158 | 		case FDI_DP_PORT_WIDTH_X1:
1159 | 			portw = "X1";
1160 | 			break;
1161 | 		case FDI_DP_PORT_WIDTH_X2:
1162 | 			portw = "X2";
1163 | 			break;
1164 | 		case FDI_DP_PORT_WIDTH_X3:
1165 | 			portw = "X3";
1166 | 			break;
1167 | 		case FDI_DP_PORT_WIDTH_X4:
1168 | 			portw = "X4";
1169 | 			break;
1170 | 	}
1171 | 
1172 | 	snprintf(result, len, "%s, train pattern %s, voltage swing %s,"
1173 | 			 "pre-emphasis %s, port width %s, enhanced framing %s, FDI PLL %s, scrambing %s, master mode %s",
1174 | 			 val & FDI_TX_ENABLE ? "enable" : "disable",
1175 | 			 train, voltage, pre_emphasis, portw,
1176 | 			 val & FDI_TX_ENHANCE_FRAME_ENABLE ? "enable" : "disable",
1177 | 			 val & FDI_TX_PLL_ENABLE ? "enable" : "disable",
1178 | 			 val & (1 << 7) ? "disable" : "enable",
1179 | 			 val & (1 << 0) ? "enable" : "disable");
1180 | }
1181 | 
1182 | //------------------------------------------------------------------------------
1183 | 
1184 | DEBUGSTRING(ironlake_debug_fdi_rx_ctl)
1185 | {
1186 | 	const char *train = NULL, *portw = NULL, *bpc = NULL;
1187 | 	
1188 | 	if (HAS_CPT)
1189 | 	{
1190 | 		switch (val & FDI_LINK_TRAIN_PATTERN_MASK_CPT)
1191 | 		{
1192 | 			case FDI_LINK_TRAIN_PATTERN_1_CPT:
1193 | 				train = "pattern_1";
1194 | 				break;
1195 | 			case FDI_LINK_TRAIN_PATTERN_2_CPT:
1196 | 				train = "pattern_2";
1197 | 				break;
1198 | 			case FDI_LINK_TRAIN_PATTERN_IDLE_CPT:
1199 | 				train = "pattern_idle";
1200 | 				break;
1201 | 			case FDI_LINK_TRAIN_NORMAL_CPT:
1202 | 				train = "not train";
1203 | 				break;
1204 | 		}
1205 | 	}
1206 | 	else
1207 | 	{
1208 | 		switch (val & FDI_LINK_TRAIN_NONE)
1209 | 		{
1210 | 			case FDI_LINK_TRAIN_PATTERN_1:
1211 | 				train = "pattern_1";
1212 | 				break;
1213 | 			case FDI_LINK_TRAIN_PATTERN_2:
1214 | 				train = "pattern_2";
1215 | 				break;
1216 | 			case FDI_LINK_TRAIN_PATTERN_IDLE:
1217 | 				train = "pattern_idle";
1218 | 				break;
1219 | 			case FDI_LINK_TRAIN_NONE:
1220 | 				train = "not train";
1221 | 				break;
1222 | 		}
1223 | 	}
1224 | 
1225 | 	switch (val & (7 << 19))
1226 | 	{
1227 | 		case FDI_DP_PORT_WIDTH_X1:
1228 | 			portw = "X1";
1229 | 			break;
1230 | 		case FDI_DP_PORT_WIDTH_X2:
1231 | 			portw = "X2";
1232 | 			break;
1233 | 		case FDI_DP_PORT_WIDTH_X3:
1234 | 			portw = "X3";
1235 | 			break;
1236 | 		case FDI_DP_PORT_WIDTH_X4:
1237 | 			portw = "X4";
1238 | 			break;
1239 | 	}
1240 | 	
1241 | 	switch (val & (7 << 16))
1242 | 	{
1243 | 		case FDI_8BPC:
1244 | 			bpc = "8bpc";
1245 | 			break;
1246 | 		case FDI_10BPC:
1247 | 			bpc = "10bpc";
1248 | 			break;
1249 | 		case FDI_6BPC:
1250 | 			bpc = "6bpc";
1251 | 			break;
1252 | 		case FDI_12BPC:
1253 | 			bpc = "12bpc";
1254 | 			break;
1255 | 	}
1256 | 	
1257 | 	snprintf(result, len, "%s, train pattern %s, port width %s, %s,"
1258 | 			 "link_reverse_strap_overwrite %s, dmi_link_reverse %s, FDI PLL %s,"
1259 | 			 "FS ecc %s, FE ecc %s, FS err report %s, FE err report %s,"
1260 | 			 "scrambing %s, enhanced framing %s, %s",
1261 | 			 val & FDI_RX_ENABLE ? "enable" : "disable",
1262 | 			 train, portw, bpc,
1263 | 			 val & FDI_LINK_REVERSE_OVERWRITE ? "yes" : "no",
1264 | 			 val & FDI_DMI_LINK_REVERSE_MASK ? "yes" : "no",
1265 | 			 val & FDI_RX_PLL_ENABLE ? "enable" : "disable",
1266 | 			 val & FDI_FS_ERR_CORRECT_ENABLE ? "enable" : "disable",
1267 | 			 val & FDI_FE_ERR_CORRECT_ENABLE ? "enable" : "disable",
1268 | 			 val & FDI_FS_ERR_REPORT_ENABLE ? "enable" : "disable",
1269 | 			 val & FDI_FE_ERR_REPORT_ENABLE ? "enable" : "disable",
1270 | 			 val & (1 << 7) ? "disable" : "enable",
1271 | 			 val & FDI_RX_ENHANCE_FRAME_ENABLE ? "enable" :
1272 | 			 "disable", val & FDI_SEL_PCDCLK ? "PCDClk" : "RawClk");
1273 | }
1274 | 
1275 | //------------------------------------------------------------------------------
1276 | 
1277 | DEBUGSTRING(i830_debug_adpa)
1278 | {
1279 | 	char disp_pipe = (val & ADPA_PIPE_B_SELECT) ? 'B' : 'A';
1280 | 	const char *enable = (val & ADPA_DAC_ENABLE) ? "enabled" : "disabled";
1281 | 	char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-';
1282 | 	char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-';
1283 | 
1284 | 	if (HAS_CPT)
1285 | 	{
1286 | 		disp_pipe = val & (1<<29) ? 'B' : 'A';
1287 | 	}
1288 | 	
1289 | 	if (HAS_PCH_SPLIT(devid))
1290 | 	{
1291 | 		snprintf(result, len, "%s, transcoder %c, %chsync, %cvsync", enable, disp_pipe, hsync, vsync);
1292 | 	}
1293 | 	else
1294 | 	{
1295 | 		snprintf(result, len, "%s, pipe %c, %chsync, %cvsync", enable, disp_pipe, hsync, vsync);
1296 | 	}
1297 | }
1298 | 
1299 | //------------------------------------------------------------------------------
1300 | 
1301 | DEBUGSTRING(ironlake_debug_hdmi)
1302 | {
1303 | 	int disp_pipe;
1304 | 	const char *enable, *bpc = NULL, *encoding;
1305 | 	const char *mode, *audio, *vsync, *hsync, *detect;
1306 | 	
1307 | 	if (val & PORT_ENABLE)
1308 | 	{
1309 | 		enable = "enabled";
1310 | 	}
1311 | 	else
1312 | 	{
1313 | 		enable = "disabled";
1314 | 	}
1315 | 	
1316 | 	if (HAS_CPT)
1317 | 	{
1318 | 		disp_pipe = (val & (3<<29)) >> 29;
1319 | 	}
1320 | 	else
1321 | 	{
1322 | 		disp_pipe = (val & TRANSCODER_B) >> 29;
1323 | 	}
1324 | 
1325 | 	switch (val & (7 << 26))
1326 | 	{
1327 | 		case COLOR_FORMAT_8bpc:
1328 | 			bpc = "8bpc";
1329 | 			break;
1330 | 		case COLOR_FORMAT_12bpc:
1331 | 			bpc = "12bpc";
1332 | 			break;
1333 | 	}
1334 | 
1335 | 	if ((val & (3 << 10)) == TMDS_ENCODING)
1336 | 	{
1337 | 		encoding = "TMDS";
1338 | 	}
1339 | 	else
1340 | 	{
1341 | 		encoding = "SDVO";
1342 | 	}
1343 | 
1344 | 	if (val & (1 << 9))
1345 | 	{
1346 | 		mode = "HDMI";
1347 | 	}
1348 | 	else
1349 | 	{
1350 | 		mode = "DVI";
1351 | 	}
1352 | 
1353 | 	if (val & AUDIO_ENABLE)
1354 | 	{
1355 | 		audio = "enabled";
1356 | 	}
1357 | 	else
1358 | 	{
1359 | 		audio = "disabled";
1360 | 	}
1361 | 
1362 | 	if (val & VSYNC_ACTIVE_HIGH)
1363 | 	{
1364 | 		vsync = "+vsync";
1365 | 	}
1366 | 	else
1367 | 	{
1368 | 		vsync = "-vsync";
1369 | 	}
1370 | 
1371 | 	if (val & HSYNC_ACTIVE_HIGH)
1372 | 	{
1373 | 		hsync = "+hsync";
1374 | 	}
1375 | 	else
1376 | 	{
1377 | 		hsync = "-hsync";
1378 | 	}
1379 | 	
1380 | 	if (val & PORT_DETECTED)
1381 | 	{
1382 | 		detect = "detected";
1383 | 	}
1384 | 	else
1385 | 	{
1386 | 		detect = "non-detected";
1387 | 	}
1388 | 	
1389 | 	snprintf(result, len, "%s pipe %c %s %s %s audio %s %s %s %s", enable, disp_pipe + 'A', bpc, encoding, mode, audio, vsync, hsync, detect);
1390 | }
1391 | 
1392 | //------------------------------------------------------------------------------
1393 | 
1394 | DEBUGSTRING(i830_debug_lvds)
1395 | {
1396 | 	char disp_pipe = val & LVDS_PIPEB_SELECT ? 'B' : 'A';
1397 | 	const char *enable = val & LVDS_PORT_EN ? "enabled" : "disabled";
1398 | 	int depth;
1399 | 	const char *channels;
1400 | 	
1401 | 	if ((val & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
1402 | 	{
1403 | 		depth = 24;
1404 | 	}
1405 | 	else
1406 | 	{
1407 | 		depth = 18;
1408 | 	}
1409 | 
1410 | 	if ((val & LVDS_B0B3_POWER_MASK) == LVDS_B0B3_POWER_UP)
1411 | 	{
1412 | 		channels = "2 channels";
1413 | 	}
1414 | 	else
1415 | 	{
1416 | 		channels = "1 channel";
1417 | 	}
1418 | 	
1419 | 	if (HAS_CPT)
1420 | 	{
1421 | 		disp_pipe = val & (1<<29) ? 'B' : 'A';
1422 | 	}
1423 | 
1424 | 	snprintf(result, len, "%s, pipe %c, %d bit, %s", enable, disp_pipe, depth, channels);
1425 | }
1426 | 
1427 | //------------------------------------------------------------------------------
1428 | 
1429 | DEBUGSTRING(snb_debug_trans_dp_ctl)
1430 | {
1431 | 	const char *enable, *port = NULL, *bpc = NULL, *vsync, *hsync;
1432 | 	
1433 | 	if (HAS_CPT)
1434 | 	{
1435 | 		if (val & TRANS_DP_OUTPUT_ENABLE)
1436 | 		{
1437 | 			enable = "enable";
1438 | 		}
1439 | 		else
1440 | 		{
1441 | 			enable = "disable";
1442 | 		}
1443 | 	
1444 | 		switch (val & TRANS_DP_PORT_SEL_MASK)
1445 | 		{
1446 | 			case TRANS_DP_PORT_SEL_B:
1447 | 				port = "B";
1448 | 				break;
1449 | 			case TRANS_DP_PORT_SEL_C:
1450 | 				port = "C";
1451 | 				break;
1452 | 			case TRANS_DP_PORT_SEL_D:
1453 | 				port = "D";
1454 | 				break;
1455 | 			default:
1456 | 				port = "none";
1457 | 				break;
1458 | 		}
1459 | 
1460 | 		switch (val & (7<<9))
1461 | 		{
1462 | 			case TRANS_DP_8BPC:
1463 | 				bpc = "8bpc";
1464 | 				break;
1465 | 			case TRANS_DP_10BPC:
1466 | 				bpc = "10bpc";
1467 | 				break;
1468 | 			case TRANS_DP_6BPC:
1469 | 				bpc = "6bpc";
1470 | 				break;
1471 | 			case TRANS_DP_12BPC:
1472 | 				bpc = "12bpc";
1473 | 				break;
1474 | 		}
1475 | 
1476 | 		if (val & TRANS_DP_VSYNC_ACTIVE_HIGH)
1477 | 		{
1478 | 			vsync = "+vsync";
1479 | 		}
1480 | 		else
1481 | 		{
1482 | 			vsync = "-vsync";
1483 | 		}
1484 | 
1485 | 		if (val & TRANS_DP_HSYNC_ACTIVE_HIGH)
1486 | 		{
1487 | 			hsync = "+hsync";
1488 | 		}
1489 | 		else
1490 | 		{
1491 | 			hsync = "-hsync";
1492 | 		}
1493 | 
1494 | 		snprintf(result, len, "%s port %s %s %s %s", enable, port, bpc, vsync, hsync);
1495 | 	}
1496 | }
1497 | 
1498 | //------------------------------------------------------------------------------
1499 | 
1500 | DEBUGSTRING(ivb_debug_port)
1501 | {
1502 | 	const char *drrs = NULL;
1503 | 
1504 | 	switch (val & (2 << 30))
1505 | 	{
1506 | 		case PORT_DBG_DRRS_HW_STATE_OFF:
1507 | 			drrs = "off";
1508 | 			break;
1509 | 		case PORT_DBG_DRRS_HW_STATE_LOW:
1510 | 			drrs = "low";
1511 | 			break;
1512 | 		/* case PORT_DBG_DRRS_HW_STATE_HIGH:
1513 | 			drrs = "high";
1514 | 			break; */
1515 | 	}
1516 | 
1517 | 	snprintf(result, len, "HW DRRS %s", drrs);
1518 | }
1519 | 
1520 | //------------------------------------------------------------------------------
1521 | 
1522 | DEBUGSTRING(i830_16bit_func)
1523 | {
1524 | 	snprintf(result, len, "0x%04x", (uint16_t) val);
1525 | }
1526 | 
1527 | //------------------------------------------------------------------------------
1528 | 
1529 | DEBUGSTRING(i830_debug_dcc)
1530 | {
1531 | 	const char *addressing = NULL;
1532 | 	
1533 | 	if (IS_MOBILE(devid))
1534 | 	{
1535 | 		if (IS_965(devid))
1536 | 		{
1537 | 			if (val & (1 << 1))
1538 | 			{
1539 | 				addressing = "dual channel interleaved";
1540 | 			}
1541 | 			else
1542 | 			{
1543 | 				addressing = "single or dual channel asymmetric";
1544 | 			}
1545 | 		}
1546 | 		else
1547 | 		{
1548 | 			switch (val & 3)
1549 | 			{
1550 | 				case 0:
1551 | 					addressing = "single channel";
1552 | 					break;
1553 | 				case 1:
1554 | 					addressing = "dual channel asymmetric";
1555 | 					break;
1556 | 				case 2:
1557 | 					addressing = "dual channel interleaved";
1558 | 					break;
1559 | 				case 3:
1560 | 					addressing = "unknown channel layout";
1561 | 					break;
1562 | 			}
1563 | 		}
1564 | 	
1565 | 		snprintf(result, len, "%s, XOR randomization: %sabled, XOR bit: %d",
1566 | 				 addressing, (val & (1 << 10)) ? "dis" : "en", (val & (1 << 9)) ? 17 : 11);
1567 | 	}
1568 | }
1569 | 
1570 | //------------------------------------------------------------------------------
1571 | 
1572 | DEBUGSTRING(i830_debug_chdecmisc)
1573 | {
1574 | 	const char *enhmodesel = NULL;
1575 | 	
1576 | 	switch ((val >> 5) & 3)
1577 | 	{
1578 | 		case 1:
1579 | 			enhmodesel = "XOR bank/rank";
1580 | 			break;
1581 | 		case 2:
1582 | 			enhmodesel = "swap bank";
1583 | 			break;
1584 | 		case 3:
1585 | 			enhmodesel = "XOR bank";
1586 | 			break;
1587 | 		case 0:
1588 | 			enhmodesel = "none";
1589 | 			break;
1590 | 	}
1591 | 	
1592 | 	snprintf(result, len,
1593 | 			 "%s, ch2 enh %sabled, ch1 enh %sabled, "
1594 | 			 "ch0 enh %sabled, "
1595 | 			 "flex %sabled, ep %spresent", enhmodesel,
1596 | 			 (val & (1 << 4)) ? "en" : "dis",
1597 | 			 (val & (1 << 3)) ? "en" : "dis",
1598 | 			 (val & (1 << 2)) ? "en" : "dis",
1599 | 			 (val & (1 << 1)) ? "en" : "dis",
1600 | 			 (val & (1 << 0)) ? "" : "not ");
1601 | }
1602 | 
1603 | //------------------------------------------------------------------------------
1604 | 
1605 | DEBUGSTRING(i830_debug_vga_pd)
1606 | {
1607 | 	int vga0_p1, vga0_p2, vga1_p1, vga1_p2;
1608 | 	
1609 | 	/* XXX: i9xx version */
1610 | 	
1611 | 	if (val & VGA0_PD_P1_DIV_2)
1612 | 	{
1613 | 		vga0_p1 = 2;
1614 | 	}
1615 | 	else
1616 | 	{
1617 | 		vga0_p1 = ((val & VGA0_PD_P1_MASK) >> VGA0_PD_P1_SHIFT) + 2;
1618 | 	}
1619 | 
1620 | 	vga0_p2 = (val & VGA0_PD_P2_DIV_4) ? 4 : 2;
1621 | 	
1622 | 	if (val & VGA1_PD_P1_DIV_2)
1623 | 	{
1624 | 		vga1_p1 = 2;
1625 | 	}
1626 | 	else
1627 | 	{
1628 | 		vga1_p1 = ((val & VGA1_PD_P1_MASK) >> VGA1_PD_P1_SHIFT) + 2;
1629 | 	}
1630 | 
1631 | 	vga1_p2 = (val & VGA1_PD_P2_DIV_4) ? 4 : 2;
1632 | 	
1633 | 	snprintf(result, len, "vga0 p1 = %d, p2 = %d, vga1 p1 = %d, p2 = %d", vga0_p1, vga0_p2, vga1_p1, vga1_p2);
1634 | }
1635 | 
1636 | //------------------------------------------------------------------------------
1637 | 
1638 | DEBUGSTRING(i830_debug_dpll_test)
1639 | {
1640 | 	const char *dpllandiv = val & DPLLA_TEST_N_BYPASS ? ", DPLLA N bypassed" : "";
1641 | 	const char *dpllamdiv = val & DPLLA_TEST_M_BYPASS ? ", DPLLA M bypassed" : "";
1642 | 	const char *dpllainput = val & DPLLA_INPUT_BUFFER_ENABLE ? "" : ", DPLLA input buffer disabled";
1643 | 	const char *dpllbndiv = val & DPLLB_TEST_N_BYPASS ? ", DPLLB N bypassed" : "";
1644 | 	const char *dpllbmdiv = val & DPLLB_TEST_M_BYPASS ? ", DPLLB M bypassed" : "";
1645 | 	const char *dpllbinput = val & DPLLB_INPUT_BUFFER_ENABLE ? "" : ", DPLLB input buffer disabled";
1646 | 	
1647 | 	snprintf(result, len, "%s%s%s%s%s%s", dpllandiv, dpllamdiv, dpllainput, dpllbndiv, dpllbmdiv, dpllbinput);
1648 | }
1649 | 
1650 | //------------------------------------------------------------------------------
1651 | 
1652 | DEBUGSTRING(i830_debug_dspclk_gate_d)
1653 | {
1654 | 	const char *DPUNIT_B = val & DPUNIT_B_CLOCK_GATE_DISABLE ? " DPUNIT_B" : "";
1655 | 	const char *VSUNIT = val & VSUNIT_CLOCK_GATE_DISABLE ? " VSUNIT" : "";
1656 | 	const char *VRHUNIT = val & VRHUNIT_CLOCK_GATE_DISABLE ? " VRHUNIT" : "";
1657 | 	const char *VRDUNIT = val & VRDUNIT_CLOCK_GATE_DISABLE ? " VRDUNIT" : "";
1658 | 	const char *AUDUNIT = val & AUDUNIT_CLOCK_GATE_DISABLE ? " AUDUNIT" : "";
1659 | 	const char *DPUNIT_A = val & DPUNIT_A_CLOCK_GATE_DISABLE ? " DPUNIT_A" : "";
1660 | 	const char *DPCUNIT = val & DPCUNIT_CLOCK_GATE_DISABLE ? " DPCUNIT" : "";
1661 | 	const char *TVRUNIT = val & TVRUNIT_CLOCK_GATE_DISABLE ? " TVRUNIT" : "";
1662 | 	const char *TVCUNIT = val & TVCUNIT_CLOCK_GATE_DISABLE ? " TVCUNIT" : "";
1663 | 	const char *TVFUNIT = val & TVFUNIT_CLOCK_GATE_DISABLE ? " TVFUNIT" : "";
1664 | 	const char *TVEUNIT = val & TVEUNIT_CLOCK_GATE_DISABLE ? " TVEUNIT" : "";
1665 | 	const char *DVSUNIT = val & DVSUNIT_CLOCK_GATE_DISABLE ? " DVSUNIT" : "";
1666 | 	const char *DSSUNIT = val & DSSUNIT_CLOCK_GATE_DISABLE ? " DSSUNIT" : "";
1667 | 	const char *DDBUNIT = val & DDBUNIT_CLOCK_GATE_DISABLE ? " DDBUNIT" : "";
1668 | 	const char *DPRUNIT = val & DPRUNIT_CLOCK_GATE_DISABLE ? " DPRUNIT" : "";
1669 | 	const char *DPFUNIT = val & DPFUNIT_CLOCK_GATE_DISABLE ? " DPFUNIT" : "";
1670 | 	const char *DPBMUNIT = val & DPBMUNIT_CLOCK_GATE_DISABLE ? " DPBMUNIT" : "";
1671 | 	const char *DPLSUNIT = val & DPLSUNIT_CLOCK_GATE_DISABLE ? " DPLSUNIT" : "";
1672 | 	const char *DPLUNIT = val & DPLUNIT_CLOCK_GATE_DISABLE ? " DPLUNIT" : "";
1673 | 	const char *DPOUNIT = val & DPOUNIT_CLOCK_GATE_DISABLE ? " DPOUNIT" : "";
1674 | 	const char *DPBUNIT = val & DPBUNIT_CLOCK_GATE_DISABLE ? " DPBUNIT" : "";
1675 | 	const char *DCUNIT = val & DCUNIT_CLOCK_GATE_DISABLE ? " DCUNIT" : "";
1676 | 	const char *DPUNIT = val & DPUNIT_CLOCK_GATE_DISABLE ? " DPUNIT" : "";
1677 | 	const char *VRUNIT = val & VRUNIT_CLOCK_GATE_DISABLE ? " VRUNIT" : "";
1678 | 	const char *OVHUNIT = val & OVHUNIT_CLOCK_GATE_DISABLE ? " OVHUNIT" : "";
1679 | 	const char *DPIOUNIT = val & DPIOUNIT_CLOCK_GATE_DISABLE ? " DPIOUNIT" : "";
1680 | 	const char *OVFUNIT = val & OVFUNIT_CLOCK_GATE_DISABLE ? " OVFUNIT" : "";
1681 | 	const char *OVBUNIT = val & OVBUNIT_CLOCK_GATE_DISABLE ? " OVBUNIT" : "";
1682 | 	const char *OVRUNIT = val & OVRUNIT_CLOCK_GATE_DISABLE ? " OVRUNIT" : "";
1683 | 	const char *OVCUNIT = val & OVCUNIT_CLOCK_GATE_DISABLE ? " OVCUNIT" : "";
1684 | 	const char *OVUUNIT = val & OVUUNIT_CLOCK_GATE_DISABLE ? " OVUUNIT" : "";
1685 | 	const char *OVLUNIT = val & OVLUNIT_CLOCK_GATE_DISABLE ? " OVLUNIT" : "";
1686 | 	
1687 | 	snprintf(result, len,
1688 | 			 "clock gates disabled:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1689 | 			 DPUNIT_B, VSUNIT, VRHUNIT, VRDUNIT, AUDUNIT, DPUNIT_A, DPCUNIT,
1690 | 			 TVRUNIT, TVCUNIT, TVFUNIT, TVEUNIT, DVSUNIT, DSSUNIT, DDBUNIT,
1691 | 			 DPRUNIT, DPFUNIT, DPBMUNIT, DPLSUNIT, DPLUNIT, DPOUNIT, DPBUNIT,
1692 | 			 DCUNIT, DPUNIT, VRUNIT, OVHUNIT, DPIOUNIT, OVFUNIT, OVBUNIT,
1693 | 			 OVRUNIT, OVCUNIT, OVUUNIT, OVLUNIT);
1694 | }
1695 | 
1696 | //------------------------------------------------------------------------------
1697 | 
1698 | DEBUGSTRING(i830_debug_sdvo)
1699 | {
1700 | 	const char *enable = val & SDVO_ENABLE ? "enabled" : "disabled";
1701 | 	char disp_pipe = val & SDVO_PIPE_B_SELECT ? 'B' : 'A';
1702 | 	const char *stall = val & SDVO_STALL_SELECT ? "enabled" : "disabled";
1703 | 	const char *detected = val & SDVO_DETECTED ? "" : "not ";
1704 | 	const char *gang = val & SDVOC_GANG_MODE ? ", gang mode" : "";
1705 | 	char sdvoextra[20];
1706 | 	
1707 | 	if (IS_915(devid))
1708 | 	{
1709 | 		snprintf(sdvoextra, len, ", SDVO mult %d", (int)((val & SDVO_PORT_MULTIPLY_MASK) >> SDVO_PORT_MULTIPLY_SHIFT) + 1);
1710 | 	}
1711 | 	else
1712 | 	{
1713 | 		sdvoextra[0] = '\0';
1714 | 	}
1715 | 	
1716 | 	snprintf(result, len, "%s, pipe %c, stall %s, %sdetected%s%s", enable, disp_pipe, stall, detected, sdvoextra, gang);
1717 | }
1718 | 
1719 | //------------------------------------------------------------------------------
1720 | 
1721 | DEBUGSTRING(i830_debug_dvo)
1722 | {
1723 | 	const char *enable = val & DVO_ENABLE ? "enabled" : "disabled";
1724 | 	char disp_pipe = val & DVO_PIPE_B_SELECT ? 'B' : 'A';
1725 | 	const char *stall;
1726 | 	char hsync = val & DVO_HSYNC_ACTIVE_HIGH ? '+' : '-';
1727 | 	char vsync = val & DVO_VSYNC_ACTIVE_HIGH ? '+' : '-';
1728 | 	
1729 | 	switch (val & DVO_PIPE_STALL_MASK)
1730 | 	{
1731 | 		case DVO_PIPE_STALL_UNUSED:
1732 | 			stall = "no stall";
1733 | 			break;
1734 | 		case DVO_PIPE_STALL:
1735 | 			stall = "stall";
1736 | 			break;
1737 | 		case DVO_PIPE_STALL_TV:
1738 | 			stall = "TV stall";
1739 | 			break;
1740 | 		default:
1741 | 			stall = "unknown stall";
1742 | 			break;
1743 | 	}
1744 | 	
1745 | 	snprintf(result, len, "%s, pipe %c, %s, %chsync, %cvsync", enable, disp_pipe, stall, hsync, vsync);
1746 | }
1747 | 
1748 | //------------------------------------------------------------------------------
1749 | 
1750 | DEBUGSTRING(i830_debug_pp_control)
1751 | {
1752 | 	snprintf(result, len, "power target: %s", val & POWER_TARGET_ON ? "on" : "off");
1753 | }
1754 | 
1755 | //------------------------------------------------------------------------------
1756 | 
1757 | DEBUGSTRING(i830_debug_dspstride)
1758 | {
1759 | 	snprintf(result, len, "%d bytes", val);
1760 | }
1761 | 
1762 | //------------------------------------------------------------------------------
1763 | 
1764 | DEBUGSTRING(i830_debug_pipestat)
1765 | {
1766 | 	const char *_FIFO_UNDERRUN = val & FIFO_UNDERRUN ? " FIFO_UNDERRUN" : "";
1767 | 	const char *_CRC_ERROR_ENABLE =
1768 | 	val & CRC_ERROR_ENABLE ? " CRC_ERROR_ENABLE" : "";
1769 | 	const char *_CRC_DONE_ENABLE =
1770 | 	val & CRC_DONE_ENABLE ? " CRC_DONE_ENABLE" : "";
1771 | 	const char *_GMBUS_EVENT_ENABLE =
1772 | 	val & GMBUS_EVENT_ENABLE ? " GMBUS_EVENT_ENABLE" : "";
1773 | 	const char *_VSYNC_INT_ENABLE =
1774 | 	val & VSYNC_INT_ENABLE ? " VSYNC_INT_ENABLE" : "";
1775 | 	const char *_DLINE_COMPARE_ENABLE =
1776 | 	val & DLINE_COMPARE_ENABLE ? " DLINE_COMPARE_ENABLE" : "";
1777 | 	const char *_DPST_EVENT_ENABLE =
1778 | 	val & DPST_EVENT_ENABLE ? " DPST_EVENT_ENABLE" : "";
1779 | 	const char *_LBLC_EVENT_ENABLE =
1780 | 	val & LBLC_EVENT_ENABLE ? " LBLC_EVENT_ENABLE" : "";
1781 | 	const char *_OFIELD_INT_ENABLE =
1782 | 	val & OFIELD_INT_ENABLE ? " OFIELD_INT_ENABLE" : "";
1783 | 	const char *_EFIELD_INT_ENABLE =
1784 | 	val & EFIELD_INT_ENABLE ? " EFIELD_INT_ENABLE" : "";
1785 | 	const char *_SVBLANK_INT_ENABLE =
1786 | 	val & SVBLANK_INT_ENABLE ? " SVBLANK_INT_ENABLE" : "";
1787 | 	const char *_VBLANK_INT_ENABLE =
1788 | 	val & VBLANK_INT_ENABLE ? " VBLANK_INT_ENABLE" : "";
1789 | 	const char *_OREG_UPDATE_ENABLE =
1790 | 	val & OREG_UPDATE_ENABLE ? " OREG_UPDATE_ENABLE" : "";
1791 | 	const char *_CRC_ERROR_INT_STATUS =
1792 | 	val & CRC_ERROR_INT_STATUS ? " CRC_ERROR_INT_STATUS" : "";
1793 | 	const char *_CRC_DONE_INT_STATUS =
1794 | 	val & CRC_DONE_INT_STATUS ? " CRC_DONE_INT_STATUS" : "";
1795 | 	const char *_GMBUS_INT_STATUS =
1796 | 	val & GMBUS_INT_STATUS ? " GMBUS_INT_STATUS" : "";
1797 | 	const char *_VSYNC_INT_STATUS =
1798 | 	val & VSYNC_INT_STATUS ? " VSYNC_INT_STATUS" : "";
1799 | 	const char *_DLINE_COMPARE_STATUS =
1800 | 	val & DLINE_COMPARE_STATUS ? " DLINE_COMPARE_STATUS" : "";
1801 | 	const char *_DPST_EVENT_STATUS =
1802 | 	val & DPST_EVENT_STATUS ? " DPST_EVENT_STATUS" : "";
1803 | 	const char *_LBLC_EVENT_STATUS =
1804 | 	val & LBLC_EVENT_STATUS ? " LBLC_EVENT_STATUS" : "";
1805 | 	const char *_OFIELD_INT_STATUS =
1806 | 	val & OFIELD_INT_STATUS ? " OFIELD_INT_STATUS" : "";
1807 | 	const char *_EFIELD_INT_STATUS =
1808 | 	val & EFIELD_INT_STATUS ? " EFIELD_INT_STATUS" : "";
1809 | 	const char *_SVBLANK_INT_STATUS =
1810 | 	val & SVBLANK_INT_STATUS ? " SVBLANK_INT_STATUS" : "";
1811 | 	const char *_VBLANK_INT_STATUS =
1812 | 	val & VBLANK_INT_STATUS ? " VBLANK_INT_STATUS" : "";
1813 | 	const char *_OREG_UPDATE_STATUS =
1814 | 	val & OREG_UPDATE_STATUS ? " OREG_UPDATE_STATUS" : "";
1815 | 	snprintf(result, len,
1816 | 			 "status:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1817 | 			 _FIFO_UNDERRUN,
1818 | 			 _CRC_ERROR_ENABLE,
1819 | 			 _CRC_DONE_ENABLE,
1820 | 			 _GMBUS_EVENT_ENABLE,
1821 | 			 _VSYNC_INT_ENABLE,
1822 | 			 _DLINE_COMPARE_ENABLE,
1823 | 			 _DPST_EVENT_ENABLE,
1824 | 			 _LBLC_EVENT_ENABLE,
1825 | 			 _OFIELD_INT_ENABLE,
1826 | 			 _EFIELD_INT_ENABLE,
1827 | 			 _SVBLANK_INT_ENABLE,
1828 | 			 _VBLANK_INT_ENABLE,
1829 | 			 _OREG_UPDATE_ENABLE,
1830 | 			 _CRC_ERROR_INT_STATUS,
1831 | 			 _CRC_DONE_INT_STATUS,
1832 | 			 _GMBUS_INT_STATUS,
1833 | 			 _VSYNC_INT_STATUS,
1834 | 			 _DLINE_COMPARE_STATUS,
1835 | 			 _DPST_EVENT_STATUS,
1836 | 			 _LBLC_EVENT_STATUS,
1837 | 			 _OFIELD_INT_STATUS,
1838 | 			 _EFIELD_INT_STATUS,
1839 | 			 _SVBLANK_INT_STATUS,
1840 | 			 _VBLANK_INT_STATUS,
1841 | 			 _OREG_UPDATE_STATUS);
1842 | }
1843 | 
1844 | //------------------------------------------------------------------------------
1845 | 
1846 | DEBUGSTRING(i830_debug_dpll)
1847 | {
1848 | 	const char *enabled = val & DPLL_VCO_ENABLE ? "enabled" : "disabled";
1849 | 	const char *dvomode = val & DPLL_DVO_HIGH_SPEED ? "dvo" : "non-dvo";
1850 | 	const char *vgamode = val & DPLL_VGA_MODE_DIS ? "" : ", VGA";
1851 | 	const char *mode = "unknown";
1852 | 	const char *clock = "unknown";
1853 | 	const char *fpextra = val & DISPLAY_RATE_SELECT_FPA1 ? ", using FPx1!" : "";
1854 | 	char sdvoextra[20];
1855 | 	int p1, p2 = 0;
1856 | 	
1857 | 	if (IS_GEN2(devid))
1858 | 	{
1859 | 		// char is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B);
1860 | 		char is_lvds = (MMIO_READ32(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B);
1861 | 		
1862 | 		if (is_lvds)
1863 | 		{
1864 | 			mode = "LVDS";
1865 | 			p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> DPLL_FPA01_P1_POST_DIV_SHIFT);
1866 | 
1867 | 			// if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
1868 | 			if ((MMIO_READ32(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
1869 | 			{
1870 | 				p2 = 7;
1871 | 			}
1872 | 			else
1873 | 			{
1874 | 				p2 = 14;
1875 | 			}
1876 | 		}
1877 | 		else
1878 | 		{
1879 | 			mode = "DAC/serial";
1880 | 
1881 | 			if (val & PLL_P1_DIVIDE_BY_TWO)
1882 | 			{
1883 | 				p1 = 2;
1884 | 			}
1885 | 			else
1886 | 			{
1887 | 				/* Map the number in the field to (3, 33) */
1888 | 				p1 = ((val & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1889 | 			}
1890 | 
1891 | 			if (val & PLL_P2_DIVIDE_BY_4)
1892 | 			{
1893 | 				p2 = 4;
1894 | 			}
1895 | 			else
1896 | 			{
1897 | 				p2 = 2;
1898 | 			}
1899 | 		}
1900 | 	}
1901 | 	else
1902 | 	{
1903 | 		if (IS_IGD(devid))
1904 | 		{
1905 | 			p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
1906 | 		}
1907 | 		else
1908 | 		{
1909 | 			p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> DPLL_FPA01_P1_POST_DIV_SHIFT);
1910 | 		}
1911 | 		switch (val & DPLL_MODE_MASK)
1912 | 		{
1913 | 			case DPLLB_MODE_DAC_SERIAL:
1914 | 				mode = "DAC/serial";
1915 | 				p2 = val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
1916 | 				break;
1917 | 			case DPLLB_MODE_LVDS:
1918 | 				mode = "LVDS";
1919 | 				p2 = val & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14;
1920 | 				break;
1921 | 		}
1922 | 	}
1923 | 	
1924 | 	switch (val & PLL_REF_INPUT_MASK)
1925 | 	{
1926 | 		case PLL_REF_INPUT_DREFCLK:
1927 | 			clock = "default";
1928 | 			break;
1929 | 		case PLL_REF_INPUT_TVCLKINA:
1930 | 			clock = "TV A";
1931 | 			break;
1932 | 		case PLL_REF_INPUT_TVCLKINBC:
1933 | 			clock = "TV B/C";
1934 | 			break;
1935 | 		case PLLB_REF_INPUT_SPREADSPECTRUMIN:
1936 | 			if (reg == DPLL_B)
1937 | 				clock = "spread spectrum";
1938 | 			break;
1939 | 	}
1940 | 	
1941 | 	if (IS_945(devid))
1942 | 	{
1943 | 		snprintf(sdvoextra, len, ", SDVO mult %d", (int)((val & SDVO_MULTIPLIER_MASK) >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1);
1944 | 	}
1945 | 	else
1946 | 	{
1947 | 		sdvoextra[0] = '\0';
1948 | 	}
1949 | 	
1950 | 	snprintf(result, len, "%s, %s%s, %s clock, %s mode, p1 = %d, p2 = %d%s%s",  enabled, dvomode, vgamode, clock, mode, p1, p2,  fpextra, sdvoextra);
1951 | }
1952 | 
1953 | //------------------------------------------------------------------------------
1954 | 
1955 | DEBUGSTRING(i810_debug_915_fence)
1956 | {
1957 | 	char format = (val & 1 << 12) ? 'Y' : 'X';
1958 | 	int pitch = 128 << ((val & 0x70) >> 4);
1959 | 	unsigned int offset = val & 0x0ff00000;
1960 | 	int size = (1024 * 1024) << ((val & 0x700) >> 8);
1961 | 	
1962 | 	if (IS_965(devid) || (IS_915(devid) && reg >= FENCE_NEW))
1963 | 	{
1964 | 		return;
1965 | 	}
1966 | 	
1967 | 	if (format == 'X')
1968 | 	{
1969 | 		pitch *= 4;
1970 | 	}
1971 | 
1972 | 	if (val & 1)
1973 | 	{
1974 | 		snprintf(result, len, "enabled, %c tiled, %4d pitch, 0x%08x - 0x%08x (%dkb)", format, pitch, offset, offset + size, size / 1024);
1975 | 	}
1976 | 	else
1977 | 	{
1978 | 		snprintf(result, len, "disabled");
1979 | 	}
1980 | }
1981 | 
1982 | //------------------------------------------------------------------------------
1983 | 
1984 | DEBUGSTRING(i810_debug_965_fence_start)
1985 | {
1986 | 	const char *enable = (val & FENCE_VALID) ? " enabled" : "disabled";
1987 | 	char format = (val & I965_FENCE_Y_MAJOR) ? 'Y' : 'X';
1988 | 	int pitch = ((val & 0xffc) >> 2) * 128 + 128;
1989 | 	unsigned int offset = val & 0xfffff000;
1990 | 	
1991 | 	if (IS_965(devid))
1992 | 	{
1993 | 		snprintf(result, len, "%s, %c tile walk, %4d pitch, 0x%08x start", enable, format, pitch, offset);
1994 | 	}
1995 | }
1996 | 
1997 | //------------------------------------------------------------------------------
1998 | 
1999 | DEBUGSTRING(i810_debug_965_fence_end)
2000 | {
2001 | 	unsigned int end = val & 0xfffff000;
2002 | 	
2003 | 	if (IS_965(devid))
2004 | 	{
2005 | 		snprintf(result, len, "                                   0x%08x end", end);
2006 | 	}
2007 | }
2008 | 
2009 | //------------------------------------------------------------------------------
2010 | 
2011 | DEBUGSTRING(gen6_rp_control)
2012 | {
2013 | 	snprintf(result, len, "%s", (val & (1 << 7)) ? "enabled" : "disabled");
2014 | }
2015 | 
2016 | //------------------------------------------------------------------------------
2017 | 
2018 | static struct reg_debug gen6_fences[] = {
2019 | #define DEFINEFENCE_SNB(i) \
2020 | { FENCE_REG_SANDYBRIDGE_0 + (i) * 8, "FENCE START "#i, NULL, 0 }, \
2021 | { FENCE_REG_SANDYBRIDGE_0 + (i) * 8 + 4, "FENCE END "#i, NULL, 0 }
2022 | 	DEFINEFENCE_SNB(0),
2023 | 	DEFINEFENCE_SNB(1),
2024 | 	DEFINEFENCE_SNB(2),
2025 | 	DEFINEFENCE_SNB(3),
2026 | 	DEFINEFENCE_SNB(4),
2027 | 	DEFINEFENCE_SNB(5),
2028 | 	DEFINEFENCE_SNB(6),
2029 | 	DEFINEFENCE_SNB(7),
2030 | 	DEFINEFENCE_SNB(8),
2031 | 	DEFINEFENCE_SNB(9),
2032 | 	DEFINEFENCE_SNB(10),
2033 | 	DEFINEFENCE_SNB(11),
2034 | 	DEFINEFENCE_SNB(12),
2035 | 	DEFINEFENCE_SNB(13),
2036 | 	DEFINEFENCE_SNB(14),
2037 | 	DEFINEFENCE_SNB(15),
2038 | 	DEFINEFENCE_SNB(16),
2039 | 	DEFINEFENCE_SNB(17),
2040 | 	DEFINEFENCE_SNB(18),
2041 | 	DEFINEFENCE_SNB(19),
2042 | 	DEFINEFENCE_SNB(20),
2043 | 	DEFINEFENCE_SNB(20),
2044 | 	DEFINEFENCE_SNB(21),
2045 | 	DEFINEFENCE_SNB(22),
2046 | 	DEFINEFENCE_SNB(23),
2047 | 	DEFINEFENCE_SNB(24),
2048 | 	DEFINEFENCE_SNB(25),
2049 | 	DEFINEFENCE_SNB(26),
2050 | 	DEFINEFENCE_SNB(27),
2051 | 	DEFINEFENCE_SNB(28),
2052 | 	DEFINEFENCE_SNB(29),
2053 | 	DEFINEFENCE_SNB(30),
2054 | 	DEFINEFENCE_SNB(31),
2055 | };
2056 | 
2057 | //------------------------------------------------------------------------------
2058 | 
2059 | static struct reg_debug gen6_rp_debug_regs[] = {
2060 | 	DEFINEREG2(GEN6_RP_CONTROL, gen6_rp_control),
2061 | 	DEFINEREG(GEN6_RPNSWREQ),
2062 | 	DEFINEREG(GEN6_RP_DOWN_TIMEOUT),
2063 | 	DEFINEREG(GEN6_RP_INTERRUPT_LIMITS),
2064 | 	DEFINEREG(GEN6_RP_UP_THRESHOLD),
2065 | 	DEFINEREG(GEN6_RP_UP_EI),
2066 | 	DEFINEREG(GEN6_RP_DOWN_EI),
2067 | 	DEFINEREG(GEN6_RP_IDLE_HYSTERSIS),
2068 | 	DEFINEREG(GEN6_RC_STATE),
2069 | 	DEFINEREG(GEN6_RC_CONTROL),
2070 | 	DEFINEREG(GEN6_RC1_WAKE_RATE_LIMIT),
2071 | 	DEFINEREG(GEN6_RC6_WAKE_RATE_LIMIT),
2072 | 	DEFINEREG(GEN6_RC_EVALUATION_INTERVAL),
2073 | 	DEFINEREG(GEN6_RC_IDLE_HYSTERSIS),
2074 | 	DEFINEREG(GEN6_RC_SLEEP),
2075 | 	DEFINEREG(GEN6_RC1e_THRESHOLD),
2076 | 	DEFINEREG(GEN6_RC6_THRESHOLD),
2077 | 	DEFINEREG(GEN6_RC_VIDEO_FREQ),
2078 | 	DEFINEREG(GEN6_PMIER),
2079 | 	DEFINEREG(GEN6_PMIMR),
2080 | 	DEFINEREG(GEN6_PMINTRMSK),
2081 | };
2082 | 
2083 | //------------------------------------------------------------------------------
2084 | 
2085 | static struct reg_debug intel_debug_regs[] = {
2086 | 	DEFINEREG2(DCC, i830_debug_dcc),
2087 | 	DEFINEREG2(CHDECMISC, i830_debug_chdecmisc),
2088 | 	DEFINEREG_16BIT(C0DRB0),
2089 | 	DEFINEREG_16BIT(C0DRB1),
2090 | 	DEFINEREG_16BIT(C0DRB2),
2091 | 	DEFINEREG_16BIT(C0DRB3),
2092 | 	DEFINEREG_16BIT(C1DRB0),
2093 | 	DEFINEREG_16BIT(C1DRB1),
2094 | 	DEFINEREG_16BIT(C1DRB2),
2095 | 	DEFINEREG_16BIT(C1DRB3),
2096 | 	DEFINEREG_16BIT(C0DRA01),
2097 | 	DEFINEREG_16BIT(C0DRA23),
2098 | 	DEFINEREG_16BIT(C1DRA01),
2099 | 	DEFINEREG_16BIT(C1DRA23),
2100 | 	
2101 | 	DEFINEREG(PGETBL_CTL),
2102 | 	
2103 | 	DEFINEREG2(VCLK_DIVISOR_VGA0, i830_debug_fp),
2104 | 	DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp),
2105 | 	DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd),
2106 | 	DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
2107 | 	DEFINEREG(CACHE_MODE_0),
2108 | 	DEFINEREG(D_STATE),
2109 | 	DEFINEREG2(DSPCLK_GATE_D, i830_debug_dspclk_gate_d),
2110 | 	DEFINEREG(RENCLK_GATE_D1),
2111 | 	DEFINEREG(RENCLK_GATE_D2),
2112 | 	/*  DEFINEREG(RAMCLK_GATE_D),	CRL only */
2113 | 	DEFINEREG2(SDVOB, i830_debug_sdvo),
2114 | 	DEFINEREG2(SDVOC, i830_debug_sdvo),
2115 | 	/*    DEFINEREG(UDIB_SVB_SHB_CODES), CRL only */
2116 | 	/*    DEFINEREG(UDIB_SHA_BLANK_CODES), CRL only */
2117 | 	DEFINEREG(SDVOUDI),
2118 | 	DEFINEREG(DSPARB),
2119 | 	DEFINEREG(FW_BLC),
2120 | 	DEFINEREG(FW_BLC2),
2121 | 	DEFINEREG(FW_BLC_SELF),
2122 | 	DEFINEREG(DSPFW1),
2123 | 	DEFINEREG(DSPFW2),
2124 | 	DEFINEREG(DSPFW3),
2125 | 	
2126 | 	DEFINEREG2(ADPA, i830_debug_adpa),
2127 | 	DEFINEREG2(LVDS, i830_debug_lvds),
2128 | 	DEFINEREG2(DVOA, i830_debug_dvo),
2129 | 	DEFINEREG2(DVOB, i830_debug_dvo),
2130 | 	DEFINEREG2(DVOC, i830_debug_dvo),
2131 | 	DEFINEREG(DVOA_SRCDIM),
2132 | 	DEFINEREG(DVOB_SRCDIM),
2133 | 	DEFINEREG(DVOC_SRCDIM),
2134 | 	
2135 | 	DEFINEREG(BLC_PWM_CTL),
2136 | 	DEFINEREG(BLC_PWM_CTL2),
2137 | 	
2138 | 	DEFINEREG2(PP_CONTROL, i830_debug_pp_control),
2139 | 	DEFINEREG2(PP_STATUS, i830_debug_pp_status),
2140 | 	DEFINEREG(PP_ON_DELAYS),
2141 | 	DEFINEREG(PP_OFF_DELAYS),
2142 | 	DEFINEREG(PP_DIVISOR),
2143 | 	DEFINEREG(PFIT_CONTROL),
2144 | 	DEFINEREG(PFIT_PGM_RATIOS),
2145 | 	DEFINEREG(PORT_HOTPLUG_EN),
2146 | 	DEFINEREG(PORT_HOTPLUG_STAT),
2147 | 	
2148 | 	DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
2149 | 	DEFINEREG2(DSPASTRIDE, i830_debug_dspstride),
2150 | 	DEFINEREG2(DSPAPOS, i830_debug_xy),
2151 | 	DEFINEREG2(DSPASIZE, i830_debug_xyminus1),
2152 | 	DEFINEREG(DSPABASE),
2153 | 	DEFINEREG(DSPASURF),
2154 | 	DEFINEREG(DSPATILEOFF),
2155 | 	DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
2156 | 	DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
2157 | 	DEFINEREG2(PIPEASTAT, i830_debug_pipestat),
2158 | 	DEFINEREG(PIPEA_GMCH_DATA_M),
2159 | 	DEFINEREG(PIPEA_GMCH_DATA_N),
2160 | 	DEFINEREG(PIPEA_DP_LINK_M),
2161 | 	DEFINEREG(PIPEA_DP_LINK_N),
2162 | 	DEFINEREG(CURSOR_A_BASE),
2163 | 	DEFINEREG(CURSOR_A_CONTROL),
2164 | 	DEFINEREG(CURSOR_A_POSITION),
2165 | 	
2166 | 	DEFINEREG2(FPA0, i830_debug_fp),
2167 | 	DEFINEREG2(FPA1, i830_debug_fp),
2168 | 	DEFINEREG2(DPLL_A, i830_debug_dpll),
2169 | 	DEFINEREG(DPLL_A_MD),
2170 | 	DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
2171 | 	DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
2172 | 	DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
2173 | 	DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
2174 | 	DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
2175 | 	DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
2176 | 	DEFINEREG(BCLRPAT_A),
2177 | 	DEFINEREG(VSYNCSHIFT_A),
2178 | 	
2179 | 	DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
2180 | 	DEFINEREG2(DSPBSTRIDE, i830_debug_dspstride),
2181 | 	DEFINEREG2(DSPBPOS, i830_debug_xy),
2182 | 	DEFINEREG2(DSPBSIZE, i830_debug_xyminus1),
2183 | 	DEFINEREG(DSPBBASE),
2184 | 	DEFINEREG(DSPBSURF),
2185 | 	DEFINEREG(DSPBTILEOFF),
2186 | 	DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
2187 | 	DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
2188 | 	DEFINEREG2(PIPEBSTAT, i830_debug_pipestat),
2189 | 	DEFINEREG(PIPEB_GMCH_DATA_M),
2190 | 	DEFINEREG(PIPEB_GMCH_DATA_N),
2191 | 	DEFINEREG(PIPEB_DP_LINK_M),
2192 | 	DEFINEREG(PIPEB_DP_LINK_N),
2193 | 	DEFINEREG(CURSOR_B_BASE),
2194 | 	DEFINEREG(CURSOR_B_CONTROL),
2195 | 	DEFINEREG(CURSOR_B_POSITION),
2196 | 	
2197 | 	DEFINEREG2(FPB0, i830_debug_fp),
2198 | 	DEFINEREG2(FPB1, i830_debug_fp),
2199 | 	DEFINEREG2(DPLL_B, i830_debug_dpll),
2200 | 	DEFINEREG(DPLL_B_MD),
2201 | 	DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
2202 | 	DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
2203 | 	DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
2204 | 	DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
2205 | 	DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
2206 | 	DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
2207 | 	DEFINEREG(BCLRPAT_B),
2208 | 	DEFINEREG(VSYNCSHIFT_B),
2209 | 	
2210 | 	DEFINEREG(VCLK_DIVISOR_VGA0),
2211 | 	DEFINEREG(VCLK_DIVISOR_VGA1),
2212 | 	DEFINEREG(VCLK_POST_DIV),
2213 | 	DEFINEREG2(VGACNTRL, i830_debug_vgacntrl),
2214 | 	
2215 | 	DEFINEREG(TV_CTL),
2216 | 	DEFINEREG(TV_DAC),
2217 | 	DEFINEREG(TV_CSC_Y),
2218 | 	DEFINEREG(TV_CSC_Y2),
2219 | 	DEFINEREG(TV_CSC_U),
2220 | 	DEFINEREG(TV_CSC_U2),
2221 | 	DEFINEREG(TV_CSC_V),
2222 | 	DEFINEREG(TV_CSC_V2),
2223 | 	DEFINEREG(TV_CLR_KNOBS),
2224 | 	DEFINEREG(TV_CLR_LEVEL),
2225 | 	DEFINEREG(TV_H_CTL_1),
2226 | 	DEFINEREG(TV_H_CTL_2),
2227 | 	DEFINEREG(TV_H_CTL_3),
2228 | 	DEFINEREG(TV_V_CTL_1),
2229 | 	DEFINEREG(TV_V_CTL_2),
2230 | 	DEFINEREG(TV_V_CTL_3),
2231 | 	DEFINEREG(TV_V_CTL_4),
2232 | 	DEFINEREG(TV_V_CTL_5),
2233 | 	DEFINEREG(TV_V_CTL_6),
2234 | 	DEFINEREG(TV_V_CTL_7),
2235 | 	DEFINEREG(TV_SC_CTL_1),
2236 | 	DEFINEREG(TV_SC_CTL_2),
2237 | 	DEFINEREG(TV_SC_CTL_3),
2238 | 	DEFINEREG(TV_WIN_POS),
2239 | 	DEFINEREG(TV_WIN_SIZE),
2240 | 	DEFINEREG(TV_FILTER_CTL_1),
2241 | 	DEFINEREG(TV_FILTER_CTL_2),
2242 | 	DEFINEREG(TV_FILTER_CTL_3),
2243 | 	DEFINEREG(TV_CC_CONTROL),
2244 | 	DEFINEREG(TV_CC_DATA),
2245 | 	DEFINEREG(TV_H_LUMA_0),
2246 | 	DEFINEREG(TV_H_LUMA_59),
2247 | 	DEFINEREG(TV_H_CHROMA_0),
2248 | 	DEFINEREG(TV_H_CHROMA_59),
2249 | 	
2250 | 	DEFINEREG(FBC_CFB_BASE),
2251 | 	DEFINEREG(FBC_LL_BASE),
2252 | 	DEFINEREG(FBC_CONTROL),
2253 | 	DEFINEREG(FBC_COMMAND),
2254 | 	DEFINEREG(FBC_STATUS),
2255 | 	DEFINEREG(FBC_CONTROL2),
2256 | 	DEFINEREG(FBC_FENCE_OFF),
2257 | 	DEFINEREG(FBC_MOD_NUM),
2258 | 	
2259 | 	DEFINEREG(MI_MODE),
2260 | 	/* DEFINEREG(MI_DISPLAY_POWER_DOWN), CRL only */
2261 | 	DEFINEREG(MI_ARB_STATE),
2262 | 	DEFINEREG(MI_RDRET_STATE),
2263 | 	DEFINEREG(ECOSKPD),
2264 | 	
2265 | 	DEFINEREG(DP_B),
2266 | 	DEFINEREG(DPB_AUX_CH_CTL),
2267 | 	DEFINEREG(DPB_AUX_CH_DATA1),
2268 | 	DEFINEREG(DPB_AUX_CH_DATA2),
2269 | 	DEFINEREG(DPB_AUX_CH_DATA3),
2270 | 	DEFINEREG(DPB_AUX_CH_DATA4),
2271 | 	DEFINEREG(DPB_AUX_CH_DATA5),
2272 | 	
2273 | 	DEFINEREG(DP_C),
2274 | 	DEFINEREG(DPC_AUX_CH_CTL),
2275 | 	DEFINEREG(DPC_AUX_CH_DATA1),
2276 | 	DEFINEREG(DPC_AUX_CH_DATA2),
2277 | 	DEFINEREG(DPC_AUX_CH_DATA3),
2278 | 	DEFINEREG(DPC_AUX_CH_DATA4),
2279 | 	DEFINEREG(DPC_AUX_CH_DATA5),
2280 | 	
2281 | 	DEFINEREG(DP_D),
2282 | 	DEFINEREG(DPD_AUX_CH_CTL),
2283 | 	DEFINEREG(DPD_AUX_CH_DATA1),
2284 | 	DEFINEREG(DPD_AUX_CH_DATA2),
2285 | 	DEFINEREG(DPD_AUX_CH_DATA3),
2286 | 	DEFINEREG(DPD_AUX_CH_DATA4),
2287 | 	DEFINEREG(DPD_AUX_CH_DATA5),
2288 | 	
2289 | 	DEFINEREG(AUD_CONFIG),
2290 | 	DEFINEREG(AUD_HDMIW_STATUS),
2291 | 	DEFINEREG(AUD_CONV_CHCNT),
2292 | 	DEFINEREG(VIDEO_DIP_CTL),
2293 | 	DEFINEREG(AUD_PINW_CNTR),
2294 | 	DEFINEREG(AUD_CNTL_ST),
2295 | 	DEFINEREG(AUD_PIN_CAP),
2296 | 	DEFINEREG(AUD_PINW_CAP),
2297 | 	DEFINEREG(AUD_PINW_UNSOLRESP),
2298 | 	DEFINEREG(AUD_OUT_DIG_CNVT),
2299 | 	DEFINEREG(AUD_OUT_CWCAP),
2300 | 	DEFINEREG(AUD_GRP_CAP),
2301 | 	
2302 | #define DEFINEFENCE_915(i) \
2303 | { FENCE+i*4, "FENCE  " #i, i810_debug_915_fence, 0 }
2304 | #define DEFINEFENCE_945(i)						\
2305 | { FENCE_NEW+(i - 8) * 4, "FENCE  " #i, i810_debug_915_fence, 0 }
2306 | 	
2307 | 	DEFINEFENCE_915(0),
2308 | 	DEFINEFENCE_915(1),
2309 | 	DEFINEFENCE_915(2),
2310 | 	DEFINEFENCE_915(3),
2311 | 	DEFINEFENCE_915(4),
2312 | 	DEFINEFENCE_915(5),
2313 | 	DEFINEFENCE_915(6),
2314 | 	DEFINEFENCE_915(7),
2315 | 	DEFINEFENCE_945(8),
2316 | 	DEFINEFENCE_945(9),
2317 | 	DEFINEFENCE_945(10),
2318 | 	DEFINEFENCE_945(11),
2319 | 	DEFINEFENCE_945(12),
2320 | 	DEFINEFENCE_945(13),
2321 | 	DEFINEFENCE_945(14),
2322 | 	DEFINEFENCE_945(15),
2323 | 	
2324 | #define DEFINEFENCE_965(i) \
2325 | { FENCE_NEW+i*8, "FENCE START " #i, i810_debug_965_fence_start, 0 }, \
2326 | { FENCE_NEW+i*8+4, "FENCE END " #i, i810_debug_965_fence_end, 0 }
2327 | 	
2328 | 	DEFINEFENCE_965(0),
2329 | 	DEFINEFENCE_965(1),
2330 | 	DEFINEFENCE_965(2),
2331 | 	DEFINEFENCE_965(3),
2332 | 	DEFINEFENCE_965(4),
2333 | 	DEFINEFENCE_965(5),
2334 | 	DEFINEFENCE_965(6),
2335 | 	DEFINEFENCE_965(7),
2336 | 	DEFINEFENCE_965(8),
2337 | 	DEFINEFENCE_965(9),
2338 | 	DEFINEFENCE_965(10),
2339 | 	DEFINEFENCE_965(11),
2340 | 	DEFINEFENCE_965(12),
2341 | 	DEFINEFENCE_965(13),
2342 | 	DEFINEFENCE_965(14),
2343 | 	DEFINEFENCE_965(15),
2344 | 	
2345 | 	DEFINEREG(INST_PM),
2346 | };
2347 | 
2348 | //------------------------------------------------------------------------------
2349 | 
2350 | static struct reg_debug ironlake_debug_regs[] = {
2351 | 	DEFINEREG(PGETBL_CTL),
2352 | 	DEFINEREG(INSTDONE_I965),
2353 | 	DEFINEREG(INSTDONE_1),
2354 | 	DEFINEREG2(CPU_VGACNTRL, i830_debug_vgacntrl),
2355 | 	DEFINEREG(DIGITAL_PORT_HOTPLUG_CNTRL),
2356 | 	
2357 | 	DEFINEREG2(RR_HW_CTL, ironlake_debug_rr_hw_ctl),
2358 | 	
2359 | 	DEFINEREG(FDI_PLL_BIOS_0),
2360 | 	DEFINEREG(FDI_PLL_BIOS_1),
2361 | 	DEFINEREG(FDI_PLL_BIOS_2),
2362 | 	
2363 | 	DEFINEREG(DISPLAY_PORT_PLL_BIOS_0),
2364 | 	DEFINEREG(DISPLAY_PORT_PLL_BIOS_1),
2365 | 	DEFINEREG(DISPLAY_PORT_PLL_BIOS_2),
2366 | 	
2367 | 	DEFINEREG(FDI_PLL_FREQ_CTL),
2368 | 	
2369 | 	/* pipe B */
2370 | 	
2371 | 	DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
2372 | 	
2373 | 	DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
2374 | 	DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
2375 | 	DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
2376 | 	DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
2377 | 	DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
2378 | 	DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
2379 | 	DEFINEREG(VSYNCSHIFT_A),
2380 | 	DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
2381 | 	
2382 | 	DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
2383 | 	DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
2384 | 	DEFINEREG2(PIPEA_DATA_M2, ironlake_debug_m_tu),
2385 | 	DEFINEREG2(PIPEA_DATA_N2, ironlake_debug_n),
2386 | 	
2387 | 	DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
2388 | 	DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
2389 | 	DEFINEREG2(PIPEA_LINK_M2, ironlake_debug_n),
2390 | 	DEFINEREG2(PIPEA_LINK_N2, ironlake_debug_n),
2391 | 	
2392 | 	DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
2393 | 	DEFINEREG(DSPABASE),
2394 | 	DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
2395 | 	DEFINEREG(DSPASURF),
2396 | 	DEFINEREG2(DSPATILEOFF, i830_debug_xy),
2397 | 	
2398 | 	/* pipe B */
2399 | 	
2400 | 	DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
2401 | 	
2402 | 	DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
2403 | 	DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
2404 | 	DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
2405 | 	DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
2406 | 	DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
2407 | 	DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
2408 | 	DEFINEREG(VSYNCSHIFT_B),
2409 | 	DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
2410 | 	
2411 | 	DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
2412 | 	DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
2413 | 	DEFINEREG2(PIPEB_DATA_M2, ironlake_debug_m_tu),
2414 | 	DEFINEREG2(PIPEB_DATA_N2, ironlake_debug_n),
2415 | 	
2416 | 	DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
2417 | 	DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
2418 | 	DEFINEREG2(PIPEB_LINK_M2, ironlake_debug_n),
2419 | 	DEFINEREG2(PIPEB_LINK_N2, ironlake_debug_n),
2420 | 	
2421 | 	DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
2422 | 	DEFINEREG(DSPBBASE),
2423 | 	DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
2424 | 	DEFINEREG(DSPBSURF),
2425 | 	DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
2426 | 	
2427 | 	/* pipe C */
2428 | 	
2429 | 	DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
2430 | 	
2431 | 	DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
2432 | 	DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
2433 | 	DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
2434 | 	DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
2435 | 	DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
2436 | 	DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
2437 | 	DEFINEREG(VSYNCSHIFT_C),
2438 | 	DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
2439 | 	
2440 | 	DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
2441 | 	DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
2442 | 	DEFINEREG2(PIPEC_DATA_M2, ironlake_debug_m_tu),
2443 | 	DEFINEREG2(PIPEC_DATA_N2, ironlake_debug_n),
2444 | 	
2445 | 	DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
2446 | 	DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
2447 | 	DEFINEREG2(PIPEC_LINK_M2, ironlake_debug_n),
2448 | 	DEFINEREG2(PIPEC_LINK_N2, ironlake_debug_n),
2449 | 	
2450 | 	DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
2451 | 	DEFINEREG(DSPCBASE),
2452 | 	DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
2453 | 	DEFINEREG(DSPCSURF),
2454 | 	DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
2455 | 	
2456 | 	/* Panel fitter */
2457 | 	
2458 | 	DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
2459 | 	DEFINEREG2(PFA_CTL_2, ironlake_debug_panel_fitting_2),
2460 | 	DEFINEREG2(PFA_CTL_3, ironlake_debug_panel_fitting_3),
2461 | 	DEFINEREG2(PFA_CTL_4, ironlake_debug_panel_fitting_4),
2462 | 	DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
2463 | 	DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
2464 | 	DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
2465 | 	DEFINEREG2(PFB_CTL_2, ironlake_debug_panel_fitting_2),
2466 | 	DEFINEREG2(PFB_CTL_3, ironlake_debug_panel_fitting_3),
2467 | 	DEFINEREG2(PFB_CTL_4, ironlake_debug_panel_fitting_4),
2468 | 	DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
2469 | 	DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
2470 | 	DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
2471 | 	DEFINEREG2(PFC_CTL_2, ironlake_debug_panel_fitting_2),
2472 | 	DEFINEREG2(PFC_CTL_3, ironlake_debug_panel_fitting_3),
2473 | 	DEFINEREG2(PFC_CTL_4, ironlake_debug_panel_fitting_4),
2474 | 	DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
2475 | 	DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
2476 | 	
2477 | 	/* PCH */
2478 | 	
2479 | 	DEFINEREG2(PCH_DREF_CONTROL, ironlake_debug_dref_ctl),
2480 | 	DEFINEREG2(PCH_RAWCLK_FREQ, ironlake_debug_rawclk_freq),
2481 | 	DEFINEREG(PCH_DPLL_TMR_CFG),
2482 | 	DEFINEREG(PCH_SSC4_PARMS),
2483 | 	DEFINEREG(PCH_SSC4_AUX_PARMS),
2484 | 	DEFINEREG2(PCH_DPLL_SEL, snb_debug_dpll_sel),
2485 | 	DEFINEREG(PCH_DPLL_ANALOG_CTL),
2486 | 	
2487 | 	DEFINEREG2(PCH_DPLL_A, ironlake_debug_pch_dpll),
2488 | 	DEFINEREG2(PCH_DPLL_B, ironlake_debug_pch_dpll),
2489 | 	DEFINEREG2(PCH_FPA0, i830_debug_fp),
2490 | 	DEFINEREG2(PCH_FPA1, i830_debug_fp),
2491 | 	DEFINEREG2(PCH_FPB0, i830_debug_fp),
2492 | 	DEFINEREG2(PCH_FPB1, i830_debug_fp),
2493 | 	
2494 | 	DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
2495 | 	DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
2496 | 	DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
2497 | 	DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
2498 | 	DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
2499 | 	DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
2500 | 	DEFINEREG(TRANS_VSYNCSHIFT_A),
2501 | 	
2502 | 	DEFINEREG2(TRANSA_DATA_M1, ironlake_debug_m_tu),
2503 | 	DEFINEREG2(TRANSA_DATA_N1, ironlake_debug_n),
2504 | 	DEFINEREG2(TRANSA_DATA_M2, ironlake_debug_m_tu),
2505 | 	DEFINEREG2(TRANSA_DATA_N2, ironlake_debug_n),
2506 | 	DEFINEREG2(TRANSA_DP_LINK_M1, ironlake_debug_n),
2507 | 	DEFINEREG2(TRANSA_DP_LINK_N1, ironlake_debug_n),
2508 | 	DEFINEREG2(TRANSA_DP_LINK_M2, ironlake_debug_n),
2509 | 	DEFINEREG2(TRANSA_DP_LINK_N2, ironlake_debug_n),
2510 | 	
2511 | 	DEFINEREG2(TRANS_HTOTAL_B, i830_debug_hvtotal),
2512 | 	DEFINEREG2(TRANS_HBLANK_B, i830_debug_hvsyncblank),
2513 | 	DEFINEREG2(TRANS_HSYNC_B, i830_debug_hvsyncblank),
2514 | 	DEFINEREG2(TRANS_VTOTAL_B, i830_debug_hvtotal),
2515 | 	DEFINEREG2(TRANS_VBLANK_B, i830_debug_hvsyncblank),
2516 | 	DEFINEREG2(TRANS_VSYNC_B, i830_debug_hvsyncblank),
2517 | 	DEFINEREG(TRANS_VSYNCSHIFT_B),
2518 | 	
2519 | 	DEFINEREG2(TRANSB_DATA_M1, ironlake_debug_m_tu),
2520 | 	DEFINEREG2(TRANSB_DATA_N1, ironlake_debug_n),
2521 | 	DEFINEREG2(TRANSB_DATA_M2, ironlake_debug_m_tu),
2522 | 	DEFINEREG2(TRANSB_DATA_N2, ironlake_debug_n),
2523 | 	DEFINEREG2(TRANSB_DP_LINK_M1, ironlake_debug_n),
2524 | 	DEFINEREG2(TRANSB_DP_LINK_N1, ironlake_debug_n),
2525 | 	DEFINEREG2(TRANSB_DP_LINK_M2, ironlake_debug_n),
2526 | 	DEFINEREG2(TRANSB_DP_LINK_N2, ironlake_debug_n),
2527 | 	
2528 | 	DEFINEREG2(TRANS_HTOTAL_C, i830_debug_hvtotal),
2529 | 	DEFINEREG2(TRANS_HBLANK_C, i830_debug_hvsyncblank),
2530 | 	DEFINEREG2(TRANS_HSYNC_C, i830_debug_hvsyncblank),
2531 | 	DEFINEREG2(TRANS_VTOTAL_C, i830_debug_hvtotal),
2532 | 	DEFINEREG2(TRANS_VBLANK_C, i830_debug_hvsyncblank),
2533 | 	DEFINEREG2(TRANS_VSYNC_C, i830_debug_hvsyncblank),
2534 | 	DEFINEREG(TRANS_VSYNCSHIFT_C),
2535 | 	
2536 | 	DEFINEREG2(TRANSC_DATA_M1, ironlake_debug_m_tu),
2537 | 	DEFINEREG2(TRANSC_DATA_N1, ironlake_debug_n),
2538 | 	DEFINEREG2(TRANSC_DATA_M2, ironlake_debug_m_tu),
2539 | 	DEFINEREG2(TRANSC_DATA_N2, ironlake_debug_n),
2540 | 	DEFINEREG2(TRANSC_DP_LINK_M1, ironlake_debug_n),
2541 | 	DEFINEREG2(TRANSC_DP_LINK_N1, ironlake_debug_n),
2542 | 	DEFINEREG2(TRANSC_DP_LINK_M2, ironlake_debug_n),
2543 | 	DEFINEREG2(TRANSC_DP_LINK_N2, ironlake_debug_n),
2544 | 	
2545 | 	DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
2546 | 	DEFINEREG2(TRANSBCONF, ironlake_debug_transconf),
2547 | 	DEFINEREG2(TRANSCCONF, ironlake_debug_transconf),
2548 | 	
2549 | 	DEFINEREG2(FDI_TXA_CTL, ironlake_debug_fdi_tx_ctl),
2550 | 	DEFINEREG2(FDI_TXB_CTL, ironlake_debug_fdi_tx_ctl),
2551 | 	DEFINEREG2(FDI_TXC_CTL, ironlake_debug_fdi_tx_ctl),
2552 | 	DEFINEREG2(FDI_RXA_CTL, ironlake_debug_fdi_rx_ctl),
2553 | 	DEFINEREG2(FDI_RXB_CTL, ironlake_debug_fdi_rx_ctl),
2554 | 	DEFINEREG2(FDI_RXC_CTL, ironlake_debug_fdi_rx_ctl),
2555 | 	
2556 | 	DEFINEREG(DPAFE_BMFUNC),
2557 | 	DEFINEREG(DPAFE_DL_IREFCAL0),
2558 | 	DEFINEREG(DPAFE_DL_IREFCAL1),
2559 | 	DEFINEREG(DPAFE_DP_IREFCAL),
2560 | 	
2561 | 	DEFINEREG(PCH_DSPCLK_GATE_D),
2562 | 	DEFINEREG(PCH_DSP_CHICKEN1),
2563 | 	DEFINEREG(PCH_DSP_CHICKEN2),
2564 | 	DEFINEREG(PCH_DSP_CHICKEN3),
2565 | 	
2566 | 	DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
2567 | 	DEFINEREG2(FDI_RXB_MISC, ironlake_debug_fdi_rx_misc),
2568 | 	DEFINEREG2(FDI_RXC_MISC, ironlake_debug_fdi_rx_misc),
2569 | 	DEFINEREG(FDI_RXA_TUSIZE1),
2570 | 	DEFINEREG(FDI_RXA_TUSIZE2),
2571 | 	DEFINEREG(FDI_RXB_TUSIZE1),
2572 | 	DEFINEREG(FDI_RXB_TUSIZE2),
2573 | 	DEFINEREG(FDI_RXC_TUSIZE1),
2574 | 	DEFINEREG(FDI_RXC_TUSIZE2),
2575 | 	
2576 | 	DEFINEREG(FDI_PLL_CTL_1),
2577 | 	DEFINEREG(FDI_PLL_CTL_2),
2578 | 	
2579 | 	DEFINEREG(FDI_RXA_IIR),
2580 | 	DEFINEREG(FDI_RXA_IMR),
2581 | 	DEFINEREG(FDI_RXB_IIR),
2582 | 	DEFINEREG(FDI_RXB_IMR),
2583 | 	
2584 | 	DEFINEREG2(PCH_ADPA, i830_debug_adpa),
2585 | 	DEFINEREG2(HDMIB, ironlake_debug_hdmi),
2586 | 	DEFINEREG2(HDMIC, ironlake_debug_hdmi),
2587 | 	DEFINEREG2(HDMID, ironlake_debug_hdmi),
2588 | 	DEFINEREG2(PCH_LVDS, i830_debug_lvds),
2589 | 	DEFINEREG(CPU_eDP_A),
2590 | 	DEFINEREG(PCH_DP_B),
2591 | 	DEFINEREG(PCH_DP_C),
2592 | 	DEFINEREG(PCH_DP_D),
2593 | 	DEFINEREG2(TRANS_DP_CTL_A, snb_debug_trans_dp_ctl),
2594 | 	DEFINEREG2(TRANS_DP_CTL_B, snb_debug_trans_dp_ctl),
2595 | 	DEFINEREG2(TRANS_DP_CTL_C, snb_debug_trans_dp_ctl),
2596 | 	
2597 | 	DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
2598 | 	DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
2599 | 	DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1),
2600 | 	DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2),
2601 | 	
2602 | 	DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
2603 | 	DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
2604 | 	DEFINEREG(PCH_PP_ON_DELAYS),
2605 | 	DEFINEREG(PCH_PP_OFF_DELAYS),
2606 | 	DEFINEREG(PCH_PP_DIVISOR),
2607 | 	
2608 | 	DEFINEREG2(PORT_DBG, ivb_debug_port),
2609 | 	
2610 | 	DEFINEREG(RC6_RESIDENCY_TIME),
2611 | 	DEFINEREG(RC6p_RESIDENCY_TIME),
2612 | 	DEFINEREG(RC6pp_RESIDENCY_TIME),
2613 | };
2614 | 
2615 | //------------------------------------------------------------------------------
2616 | 
2617 | static struct reg_debug haswell_debug_regs[] = {
2618 | 	/* Power wells */
2619 | 	DEFINEREG(HSW_PWR_WELL_CTL1),
2620 | 	DEFINEREG(HSW_PWR_WELL_CTL2),
2621 | 	DEFINEREG(HSW_PWR_WELL_CTL3),
2622 | 	DEFINEREG(HSW_PWR_WELL_CTL4),
2623 | 	DEFINEREG(HSW_PWR_WELL_CTL5),
2624 | 	DEFINEREG(HSW_PWR_WELL_CTL6),
2625 | 	
2626 | 	/* DDI pipe function */
2627 | 	DEFINEREG2(PIPE_DDI_FUNC_CTL_A, hsw_debug_pipe_ddi_func_ctl),
2628 | 	DEFINEREG2(PIPE_DDI_FUNC_CTL_B, hsw_debug_pipe_ddi_func_ctl),
2629 | 	DEFINEREG2(PIPE_DDI_FUNC_CTL_C, hsw_debug_pipe_ddi_func_ctl),
2630 | 	DEFINEREG2(PIPE_DDI_FUNC_CTL_EDP, hsw_debug_pipe_ddi_func_ctl),
2631 | 	
2632 | 	/* DP transport control */
2633 | 	DEFINEREG(DP_TP_CTL_A),
2634 | 	DEFINEREG(DP_TP_CTL_B),
2635 | 	DEFINEREG(DP_TP_CTL_C),
2636 | 	DEFINEREG(DP_TP_CTL_D),
2637 | 	DEFINEREG(DP_TP_CTL_E),
2638 | 	
2639 | 	/* DP status */
2640 | 	DEFINEREG(DP_TP_STATUS_A),
2641 | 	DEFINEREG(DP_TP_STATUS_B),
2642 | 	DEFINEREG(DP_TP_STATUS_C),
2643 | 	DEFINEREG(DP_TP_STATUS_D),
2644 | 	DEFINEREG(DP_TP_STATUS_E),
2645 | 	
2646 | 	/* DDI buffer control */
2647 | 	DEFINEREG2(DDI_BUF_CTL_A, hsw_debug_ddi_buf_ctl),
2648 | 	DEFINEREG2(DDI_BUF_CTL_B, hsw_debug_ddi_buf_ctl),
2649 | 	DEFINEREG2(DDI_BUF_CTL_C, hsw_debug_ddi_buf_ctl),
2650 | 	DEFINEREG2(DDI_BUF_CTL_D, hsw_debug_ddi_buf_ctl),
2651 | 	DEFINEREG2(DDI_BUF_CTL_E, hsw_debug_ddi_buf_ctl),
2652 | 	
2653 | 	/* Clocks */
2654 | 	DEFINEREG(SPLL_CTL),
2655 | 	DEFINEREG(LCPLL_CTL),
2656 | 	DEFINEREG(WRPLL_CTL1),
2657 | 	DEFINEREG(WRPLL_CTL2),
2658 | 	
2659 | 	/* DDI port clock control */
2660 | 	DEFINEREG2(PORT_CLK_SEL_A, hsw_debug_port_clk_sel),
2661 | 	DEFINEREG2(PORT_CLK_SEL_B, hsw_debug_port_clk_sel),
2662 | 	DEFINEREG2(PORT_CLK_SEL_C, hsw_debug_port_clk_sel),
2663 | 	DEFINEREG2(PORT_CLK_SEL_D, hsw_debug_port_clk_sel),
2664 | 	DEFINEREG2(PORT_CLK_SEL_E, hsw_debug_port_clk_sel),
2665 | 	
2666 | 	/* Pipe clock control */
2667 | 	DEFINEREG2(PIPE_CLK_SEL_A, hsw_debug_pipe_clk_sel),
2668 | 	DEFINEREG2(PIPE_CLK_SEL_B, hsw_debug_pipe_clk_sel),
2669 | 	DEFINEREG2(PIPE_CLK_SEL_C, hsw_debug_pipe_clk_sel),
2670 | 	
2671 | 	/* Fuses */
2672 | 	DEFINEREG2(SFUSE_STRAP, hsw_debug_sfuse_strap),
2673 | 	
2674 | 	/* Pipe A */
2675 | 	DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
2676 | 	DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
2677 | 	DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
2678 | 	DEFINEREG(DSPASURF),
2679 | 	DEFINEREG2(DSPATILEOFF, i830_debug_xy),
2680 | 	
2681 | 	/* Pipe B */
2682 | 	DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
2683 | 	DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
2684 | 	DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
2685 | 	DEFINEREG(DSPBSURF),
2686 | 	DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
2687 | 	
2688 | 	/* Pipe C */
2689 | 	DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
2690 | 	DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
2691 | 	DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
2692 | 	DEFINEREG(DSPCSURF),
2693 | 	DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
2694 | 	
2695 | 	/* Transcoder A */
2696 | 	DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
2697 | 	DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
2698 | 	DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
2699 | 	DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
2700 | 	DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
2701 | 	DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
2702 | 	DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
2703 | 	DEFINEREG(VSYNCSHIFT_A),
2704 | 	DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
2705 | 	DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
2706 | 	DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
2707 | 	DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
2708 | 	
2709 | 	/* Transcoder B */
2710 | 	DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
2711 | 	DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
2712 | 	DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
2713 | 	DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
2714 | 	DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
2715 | 	DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
2716 | 	DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
2717 | 	DEFINEREG(VSYNCSHIFT_B),
2718 | 	DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
2719 | 	DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
2720 | 	DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
2721 | 	DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
2722 | 	
2723 | 	/* Transcoder C */
2724 | 	DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
2725 | 	DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
2726 | 	DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
2727 | 	DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
2728 | 	DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
2729 | 	DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
2730 | 	DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
2731 | 	DEFINEREG(VSYNCSHIFT_C),
2732 | 	DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
2733 | 	DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
2734 | 	DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
2735 | 	DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
2736 | 	
2737 | 	/* Transcoder EDP */
2738 | 	DEFINEREG2(PIPEEDPCONF, i830_debug_pipeconf),
2739 | 	DEFINEREG2(HTOTAL_EDP, i830_debug_hvtotal),
2740 | 	DEFINEREG2(HBLANK_EDP, i830_debug_hvsyncblank),
2741 | 	DEFINEREG2(HSYNC_EDP, i830_debug_hvsyncblank),
2742 | 	DEFINEREG2(VTOTAL_EDP, i830_debug_hvtotal),
2743 | 	DEFINEREG2(VBLANK_EDP, i830_debug_hvsyncblank),
2744 | 	DEFINEREG2(VSYNC_EDP, i830_debug_hvsyncblank),
2745 | 	DEFINEREG(VSYNCSHIFT_EDP),
2746 | 	DEFINEREG2(PIPEEDP_DATA_M1, ironlake_debug_m_tu),
2747 | 	DEFINEREG2(PIPEEDP_DATA_N1, ironlake_debug_n),
2748 | 	DEFINEREG2(PIPEEDP_LINK_M1, ironlake_debug_n),
2749 | 	DEFINEREG2(PIPEEDP_LINK_N1, ironlake_debug_n),
2750 | 	
2751 | 	/* CPU Panel fitter */
2752 | 	DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
2753 | 	DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
2754 | 	DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
2755 | 	
2756 | 	DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
2757 | 	DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
2758 | 	DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
2759 | 	
2760 | 	DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
2761 | 	DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
2762 | 	DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
2763 | 	
2764 | 	/* LPT */
2765 | 	DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
2766 | 	DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
2767 | 	DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
2768 | 	DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
2769 | 	DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
2770 | 	DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
2771 | 	DEFINEREG(TRANS_VSYNCSHIFT_A),
2772 | 	
2773 | 	DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
2774 | 	
2775 | 	DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
2776 | 	DEFINEREG(FDI_RXA_TUSIZE1),
2777 | 	DEFINEREG(FDI_RXA_IIR),
2778 | 	DEFINEREG(FDI_RXA_IMR),
2779 | 	
2780 | 	DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
2781 | 	DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
2782 | 	DEFINEREG2(BLC_PWM2_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
2783 | 	DEFINEREG2(BLC_PWM2_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
2784 | 	DEFINEREG2(BLC_MISC_CTL, hsw_debug_blc_misc_ctl),
2785 | 	DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1),
2786 | 	DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2),
2787 | 	
2788 | 	DEFINEREG2(UTIL_PIN_CTL, hsw_debug_util_pin_ctl),
2789 | 	
2790 | 	DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
2791 | 	DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
2792 | 	DEFINEREG(PCH_PP_ON_DELAYS),
2793 | 	DEFINEREG(PCH_PP_OFF_DELAYS),
2794 | 	DEFINEREG(PCH_PP_DIVISOR),
2795 | 	
2796 | 	DEFINEREG(PIXCLK_GATE),
2797 | 	
2798 | 	DEFINEREG2(SDEISR, hsw_debug_sinterrupt),
2799 | 	
2800 | 	DEFINEREG(RC6_RESIDENCY_TIME)
2801 | };
2802 | 
2803 | //------------------------------------------------------------------------------
2804 | 
2805 | static struct reg_debug skylake_debug_regs[] = {
2806 | 	/* DDI pipe function */
2807 | 	DEFINEREG2(TRANS_DDI_FUNC_CTL_EDP,	hsw_debug_pipe_ddi_func_ctl),
2808 | 	DEFINEREG2(TRANS_DDI_FUNC_CTL_A, hsw_debug_pipe_ddi_func_ctl),
2809 | 	DEFINEREG2(TRANS_DDI_FUNC_CTL_B, hsw_debug_pipe_ddi_func_ctl),
2810 | 	DEFINEREG2(TRANS_DDI_FUNC_CTL_C, hsw_debug_pipe_ddi_func_ctl),
2811 | };
2812 | 
2813 | //------------------------------------------------------------------------------
2814 | 
2815 | static struct reg_debug i945gm_mi_regs[] = {
2816 | 	DEFINEREG(PGETBL_CTL),
2817 | 	DEFINEREG(PGTBL_ER),
2818 | 	DEFINEREG(EXCC),
2819 | 	DEFINEREG(HWS_PGA),
2820 | 	DEFINEREG(IPEIR),
2821 | 	DEFINEREG(IPEHR),
2822 | 	DEFINEREG(INSTDONE),
2823 | 	DEFINEREG(NOP_ID),
2824 | 	DEFINEREG(HWSTAM),
2825 | 	DEFINEREG(SCPD0),
2826 | 	DEFINEREG(IER),
2827 | 	DEFINEREG(IIR),
2828 | 	DEFINEREG(IMR),
2829 | 	DEFINEREG(ISR),
2830 | 	DEFINEREG(EIR),
2831 | 	DEFINEREG(EMR),
2832 | 	DEFINEREG(ESR),
2833 | 	DEFINEREG(INST_PM),
2834 | 	DEFINEREG(ECOSKPD),
2835 | };
2836 | 
2837 | //------------------------------------------------------------------------------
2838 | 
2839 | // void AppleIntelInto::intel_dump_other_regs(void)
2840 | 
2841 | DEFINE_FUNC_VOID(AppleIntelInfo::intel_dump_other_regs)
2842 | {
2843 | 	int i;
2844 | 	int fp, dpll;
2845 | 	int disp_pipe;
2846 | 	int n, m1, m2, m, p1, p2;
2847 | 	int ref;
2848 | 	int dot;
2849 | 	int phase;
2850 | 	
2851 | 	for (disp_pipe = 0; disp_pipe <= 1; disp_pipe++)
2852 | 	{
2853 | 		if (disp_pipe == 0)
2854 | 		{
2855 | 			fp = MMIO_READ32(FPA0);
2856 | 			dpll = MMIO_READ32(DPLL_A);
2857 | 		}
2858 | 		else
2859 | 		{
2860 | 			fp = MMIO_READ32(FPB0);
2861 | 			dpll = MMIO_READ32(DPLL_B);
2862 | 		}
2863 | 
2864 | 		if (IS_GEN2(devid))
2865 | 		{
2866 | 			uint32_t lvds = MMIO_READ32(LVDS);
2867 | 
2868 | 			if (devid == PCI_CHIP_I855_GM && (lvds & LVDS_PORT_EN) && (lvds & LVDS_PIPEB_SELECT) == (disp_pipe << 30))
2869 | 			{
2870 | 				if ((lvds & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
2871 | 				{
2872 | 					p2 = 7;
2873 | 				}
2874 | 				else
2875 | 				{
2876 | 					p2 = 14;
2877 | 				}
2878 | 
2879 | 				switch ((dpll >> 16) & 0x3f)
2880 | 				{
2881 | 					case 0x01:
2882 | 						p1 = 1;
2883 | 						break;
2884 | 					case 0x02:
2885 | 						p1 = 2;
2886 | 						break;
2887 | 					case 0x04:
2888 | 						p1 = 3;
2889 | 						break;
2890 | 					case 0x08:
2891 | 						p1 = 4;
2892 | 						break;
2893 | 					case 0x10:
2894 | 						p1 = 5;
2895 | 						break;
2896 | 					case 0x20:
2897 | 						p1 = 6;
2898 | 						break;
2899 | 					default:
2900 | 						p1 = 1;
2901 | 						IOLOG("LVDS P1 0x%x invalid encoding\n", (dpll >> 16) & 0x3f);
2902 | 						break;
2903 | 				}
2904 | 			}
2905 | 			else
2906 | 			{
2907 | 				if (dpll & (1 << 23))
2908 | 				{
2909 | 					p2 = 4;
2910 | 				}
2911 | 				else
2912 | 				{
2913 | 					p2 = 2;
2914 | 				}
2915 | 
2916 | 				if (dpll & PLL_P1_DIVIDE_BY_TWO)
2917 | 				{
2918 | 					p1 = 2;
2919 | 				}
2920 | 				else
2921 | 				{
2922 | 					p1 = ((dpll >> 16) & 0x3f) + 2;
2923 | 				}
2924 | 			}
2925 | 
2926 | 			switch ((dpll >> 13) & 0x3)
2927 | 			{
2928 | 				case 0:
2929 | 					ref = 48000;
2930 | 					break;
2931 | 				case 3:
2932 | 					ref = 66000;
2933 | 					break;
2934 | 				default:
2935 | 					ref = 0;
2936 | 					IOLOG("ref out of range\n");
2937 | 					break;
2938 | 			}
2939 | 		}
2940 | 		else
2941 | 		{
2942 | 			uint32_t lvds = MMIO_READ32(LVDS);
2943 | 
2944 | 			if ((lvds & LVDS_PORT_EN) && (lvds & LVDS_PIPEB_SELECT) == (disp_pipe << 30))
2945 | 			{
2946 | 				if ((lvds & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
2947 | 				{
2948 | 					p2 = 7;
2949 | 				}
2950 | 				else
2951 | 				{
2952 | 					p2 = 14;
2953 | 				}
2954 | 			}
2955 | 			else
2956 | 			{
2957 | 				switch ((dpll >> 24) & 0x3)
2958 | 				{
2959 | 					case 0:
2960 | 						p2 = 10;
2961 | 						break;
2962 | 					case 1:
2963 | 						p2 = 5;
2964 | 						break;
2965 | 					default:
2966 | 						p2 = 1;
2967 | 						IOLOG("p2 out of range\n");
2968 | 						break;
2969 | 				}
2970 | 			}
2971 | 
2972 | 			if (IS_IGD(devid))
2973 | 			{
2974 | 				i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT_IGD) & 0x1ff;
2975 | 			}
2976 | 			else
2977 | 			{
2978 | 				i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT) & 0xff;
2979 | 			}
2980 | 
2981 | 			switch (i)
2982 | 			{
2983 | 				case 1:
2984 | 					p1 = 1;
2985 | 					break;
2986 | 				case 2:
2987 | 					p1 = 2;
2988 | 					break;
2989 | 				case 4:
2990 | 					p1 = 3;
2991 | 					break;
2992 | 				case 8:
2993 | 					p1 = 4;
2994 | 					break;
2995 | 				case 16:
2996 | 					p1 = 5;
2997 | 					break;
2998 | 				case 32:
2999 | 					p1 = 6;
3000 | 					break;
3001 | 				case 64:
3002 | 					p1 = 7;
3003 | 					break;
3004 | 				case 128:
3005 | 					p1 = 8;
3006 | 					break;
3007 | 				case 256:
3008 | 					if (IS_IGD(devid))
3009 | 					{
3010 | 						p1 = 9;
3011 | 						break;
3012 | 					}	// fallback
3013 | 				default:
3014 | 					p1 = 1;
3015 | 					IOLOG("p1 out of range\n");
3016 | 					break;
3017 | 			}
3018 | 
3019 | 			switch ((dpll >> 13) & 0x3)
3020 | 			{
3021 | 				case 0:
3022 | 					ref = 96000;
3023 | 					break;
3024 | 				case 3:
3025 | 					ref = 100000;
3026 | 					break;
3027 | 				default:
3028 | 					ref = 0;
3029 | 					IOLOG("ref out of range\n");
3030 | 					break;
3031 | 			}
3032 | 		}
3033 | 
3034 | 		if (IS_965(devid))
3035 | 		{
3036 | 			phase = (dpll >> 9) & 0xf;
3037 | 
3038 | 			switch (phase)
3039 | 			{
3040 | 				case 6:
3041 | 					break;
3042 | 				default:
3043 | 					IOLOG("SDVO phase shift %d out of range -- probably not an issue.\n", phase);
3044 | 					break;
3045 | 			}
3046 | 		}
3047 | 
3048 | 		switch ((dpll >> 8) & 1)
3049 | 		{
3050 | 			case 0:
3051 | 				break;
3052 | 			default:
3053 | 				IOLOG("fp select out of range\n");
3054 | 				break;
3055 | 		}
3056 | 
3057 | 		m1 = ((fp >> 8) & 0x3f);
3058 | 
3059 | 		if (IS_IGD(devid))
3060 | 		{
3061 | 			n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3062 | 			m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3063 | 			m = m2 + 2;
3064 | 			dot = (ref * m) / n / (p1 * p2);
3065 | 		}
3066 | 		else
3067 | 		{
3068 | 			n = ((fp >> 16) & 0x3f);
3069 | 			m2 = ((fp >> 0) & 0x3f);
3070 | 			//m = 5 * (m1 + 2) + (m2 + 2);
3071 | 			dot = (ref * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)) / (p1 * p2);
3072 | 		}
3073 | 		
3074 | 		IOLOG("pipe %s dot %d n %d m1 %d m2 %d p1 %d p2 %d\n", disp_pipe == 0 ? "A" : "B", dot, n, m1, m2, p1, p2);
3075 | 	}
3076 | }
3077 | 
3078 | //------------------------------------------------------------------------------
3079 | // void AppleIntelInfo::dumpRegisters(struct reg_debug *regs, uint32_t count)
3080 | 
3081 | DEFINE_FUNC_DUMP(AppleIntelInfo::dumpRegisters)
3082 | {
3083 | 	char name[30];
3084 | 	char debug[1024];
3085 | 
3086 | 	for (int i = 0; i < count; i++)
3087 | 	{
3088 | 		UInt32 val = MMIO_READ32((UInt64)regs[i].reg);
3089 | 
3090 | 		memset(name, 0, 30);
3091 | 		memset(debug, 0, 1024);
3092 | 		memcpy(name, regs[i].name, strlen(regs[i].name));
3093 | 		//			  "123456789 123456789 1234567"
3094 | 		strncat(name, "...........................", (27 - strlen(regs[i].name)));
3095 | 
3096 | 		if (regs[i].debug_output != NULL)
3097 | 		{
3098 | 			regs[i].debug_output(debug, sizeof(debug), regs[i].reg, val);
3099 | 			IOLOG("%s: 0x%08x (%s)\n", name, val, debug);
3100 | 		}
3101 | 		else
3102 | 		{
3103 | 			IOLOG("%s: 0x%08x\n", name, val);
3104 | 		}
3105 | 	}
3106 | }
3107 | 
3108 | //------------------------------------------------------------------------------
3109 | // void AppleIntelInfo::getPCHDeviceID(void)
3110 | 
3111 | DEFINE_FUNC_VOID(AppleIntelInfo::getPCHDeviceID)
3112 | {
3113 | 	outl(0xcf8, 0x8000F800);
3114 | 	UInt64 pch_device = inl(0xcfc);
3115 | 
3116 | 	IOLOG("PCH device.................: 0x%llX\n", pch_device);
3117 | 
3118 | 	if ((pch_device & 0x0000ffff) == 0x8086)
3119 | 	{
3120 | 		switch ((pch_device & 0xff000000))
3121 | 		{
3122 | 			case 0x3b000000:
3123 | 				intel_pch = PCH_IBX;
3124 | 				break;
3125 | 			case 0x1c000000:
3126 | 			case 0x1e000000:
3127 | 				intel_pch = PCH_CPT;
3128 | 				break;
3129 | 			case 0x8c000000:
3130 | 			case 0x9c000000:
3131 | 				intel_pch = PCH_LPT;
3132 | 				break;
3133 | 			default:
3134 | 				intel_pch = PCH_NONE;
3135 | 		}
3136 | 	}
3137 | }
3138 | 
3139 | //------------------------------------------------------------------------------
3140 | // void AppleIntelInfo::reportIntelRegs(void)
3141 | 
3142 | DEFINE_FUNC_VOID(AppleIntelInfo::reportIntelRegs)
3143 | {
3144 | 	getPCHDeviceID();
3145 | 
3146 | 	outl(0xcf8, 0x80001010);
3147 | 	UInt64 mmio = (inl(0xcfc) & 0x7FFFC00000); // mask bits 38-22
3148 | 
3149 | 	IOPhysicalAddress address = (IOPhysicalAddress)(mmio);
3150 | 
3151 | 	// 16 MB combined for MMIO and Global GTT table aperture (2MB for MMIO, 6MB reserved and 8MB for GTT).
3152 | 	IOMemoryDescriptor * memDescriptor = IOMemoryDescriptor::withPhysicalAddress(address, 0x1000000, kIODirectionInOut);
3153 | 
3154 | 	if (memDescriptor != NULL)
3155 | 	{
3156 | 		IOReturn result = memDescriptor->prepare();
3157 | 
3158 | 		if (result == kIOReturnSuccess)
3159 | 		{
3160 | 			IOMemoryMap * memoryMap = memDescriptor->map();
3161 | 
3162 | 			if (memoryMap != NULL)
3163 | 			{
3164 | 				int64_t mmio = memoryMap->getVirtualAddress();
3165 | 				gMMIOAddress = mmio;
3166 | 
3167 | 				IOLOG("\nIntel Register Data\n------------------------------------\nCPU_VGACNTRL...............: 0x%X\n", MMIO_READ32(CPU_VGACNTRL));
3168 | 
3169 | 				if (IS_SKYLAKE(devid))
3170 | 				{
3171 | 					IOLOG("IS_SKYLAKE(devid)\n");
3172 | 					intel_dump_regs(haswell_debug_regs);
3173 | 					intel_dump_regs(skylake_debug_regs);
3174 | 				}
3175 | 				else if (IS_HASWELL(devid) || IS_BROADWELL(devid))
3176 | 				{
3177 | 					IOLOG("IS_HASWELL(devid) || IS_BROADWELL(devid)\n");
3178 | 					intel_dump_regs(haswell_debug_regs);
3179 | 				}
3180 | 				else if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid))
3181 | 				{
3182 | 					IOLOG("IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid)\n");
3183 | 					intel_dump_regs(ironlake_debug_regs);
3184 | 				}
3185 | 				else if (IS_945GM(devid))
3186 | 				{
3187 | 					IOLOG("IS_945GM(devid)\n");
3188 | 					intel_dump_regs(i945gm_mi_regs);
3189 | 					intel_dump_regs(intel_debug_regs);
3190 | 					intel_dump_other_regs();
3191 | 				}
3192 | 				else
3193 | 				{
3194 | 					IOLOG("IS_ELSE(devid)\n");
3195 | 					intel_dump_regs(intel_debug_regs);
3196 | 					intel_dump_other_regs();
3197 | 				}
3198 | 				
3199 | 				if (IS_GEN6(devid) || IS_GEN7(devid))
3200 | 				{
3201 | 					IOLOG("IS_GEN6(devid) || IS_GEN7(devid)\n");
3202 | 					intel_dump_regs(gen6_fences);
3203 | 					intel_dump_regs(gen6_rp_debug_regs);
3204 | 				}
3205 | 
3206 | 				memoryMap->release();
3207 | 				memoryMap = NULL;
3208 | 			}
3209 | 		}
3210 | 
3211 | 		memDescriptor->release();
3212 | 		memDescriptor = NULL;
3213 | 	}
3214 | }
3215 | 
3216 | 


--------------------------------------------------------------------------------
/AppleIntelRegisterDumper/intel_chipset.h:
--------------------------------------------------------------------------------
  1 | /*
  2 |  * Copyright © 2007 Intel Corporation
  3 |  *
  4 |  * Permission is hereby granted, free of charge, to any person obtaining a
  5 |  * copy of this software and associated documentation files (the "Software"),
  6 |  * to deal in the Software without restriction, including without limitation
  7 |  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 |  * and/or sell copies of the Software, and to permit persons to whom the
  9 |  * Software is furnished to do so, subject to the following conditions:
 10 |  *
 11 |  * The above copyright notice and this permission notice (including the next
 12 |  * paragraph) shall be included in all copies or substantial portions of the
 13 |  * Software.
 14 |  *
 15 |  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 |  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 |  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 |  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 |  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 |  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 |  * IN THE SOFTWARE.
 22 |  *
 23 |  * Authors:
 24 |  *    Eric Anholt <eric@anholt.net>
 25 |  *
 26 |  */
 27 | 
 28 | #ifndef _INTEL_CHIPSET_H
 29 | #define _INTEL_CHIPSET_H
 30 | 
 31 | UInt8 intel_pch = 0;
 32 | 
 33 | enum pch_type {
 34 | 	PCH_NONE,
 35 | 	PCH_IBX,
 36 | 	PCH_CPT,
 37 | 	PCH_LPT,
 38 | };
 39 | 
 40 | #define HAS_IBX (intel_pch == PCH_IBX)
 41 | #define HAS_CPT (intel_pch == PCH_CPT)
 42 | #define HAS_LPT (intel_pch == PCH_LPT)
 43 | 
 44 | /* Exclude chipset #defines, they just add noise */
 45 | #ifndef __GTK_DOC_IGNORE__
 46 | 
 47 | #define PCI_CHIP_I810			0x7121
 48 | #define PCI_CHIP_I810_DC100		0x7123
 49 | #define PCI_CHIP_I810_E			0x7125
 50 | #define PCI_CHIP_I815			0x1132
 51 | 
 52 | #define PCI_CHIP_I830_M			0x3577
 53 | #define PCI_CHIP_845_G			0x2562
 54 | #define PCI_CHIP_I855_GM		0x3582
 55 | #define PCI_CHIP_I865_G			0x2572
 56 | 
 57 | #define PCI_CHIP_I915_G			0x2582
 58 | #define PCI_CHIP_E7221_G		0x258A
 59 | #define PCI_CHIP_I915_GM		0x2592
 60 | #define PCI_CHIP_I945_G			0x2772
 61 | #define PCI_CHIP_I945_GM		0x27A2
 62 | #define PCI_CHIP_I945_GME		0x27AE
 63 | 
 64 | #define PCI_CHIP_Q35_G			0x29B2
 65 | #define PCI_CHIP_G33_G			0x29C2
 66 | #define PCI_CHIP_Q33_G			0x29D2
 67 | 
 68 | #define PCI_CHIP_IGD_GM			0xA011
 69 | #define PCI_CHIP_IGD_G			0xA001
 70 | 
 71 | #define IS_IGDGM(devid)		((devid) == PCI_CHIP_IGD_GM)
 72 | #define IS_IGDG(devid)		((devid) == PCI_CHIP_IGD_G)
 73 | #define IS_IGD(devid)		(IS_IGDG(devid) || IS_IGDGM(devid))
 74 | 
 75 | #define PCI_CHIP_I965_G			0x29A2
 76 | #define PCI_CHIP_I965_Q			0x2992
 77 | #define PCI_CHIP_I965_G_1		0x2982
 78 | #define PCI_CHIP_I946_GZ		0x2972
 79 | #define PCI_CHIP_I965_GM		0x2A02
 80 | #define PCI_CHIP_I965_GME		0x2A12
 81 | 
 82 | #define PCI_CHIP_GM45_GM		0x2A42
 83 | 
 84 | #define PCI_CHIP_IGD_E_G		0x2E02
 85 | #define PCI_CHIP_Q45_G			0x2E12
 86 | #define PCI_CHIP_G45_G			0x2E22
 87 | #define PCI_CHIP_G41_G			0x2E32
 88 | 
 89 | #define PCI_CHIP_ILD_G			0x0042
 90 | #define PCI_CHIP_ILM_G			0x0046
 91 | 
 92 | #define PCI_CHIP_SANDYBRIDGE_GT1	0x0102 /* desktop */
 93 | #define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
 94 | #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
 95 | #define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106 /* mobile */
 96 | #define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
 97 | #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
 98 | #define PCI_CHIP_SANDYBRIDGE_S		0x010A /* server */
 99 | 
100 | #define PCI_CHIP_IVYBRIDGE_GT1		0x0152 /* desktop */
101 | #define PCI_CHIP_IVYBRIDGE_GT2		0x0162
102 | #define PCI_CHIP_IVYBRIDGE_M_GT1	0x0156 /* mobile */
103 | #define PCI_CHIP_IVYBRIDGE_M_GT2	0x0166
104 | #define PCI_CHIP_IVYBRIDGE_S		0x015a /* server */
105 | #define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a /* server */
106 | 
107 | #define PCI_CHIP_HASWELL_GT1		0x0402 /* Desktop */
108 | #define PCI_CHIP_HASWELL_GT2		0x0412
109 | #define PCI_CHIP_HASWELL_GT3		0x0422
110 | #define PCI_CHIP_HASWELL_M_GT1		0x0406 /* Mobile */
111 | #define PCI_CHIP_HASWELL_M_GT2		0x0416
112 | #define PCI_CHIP_HASWELL_M_GT3		0x0426
113 | #define PCI_CHIP_HASWELL_S_GT1		0x040A /* Server */
114 | #define PCI_CHIP_HASWELL_S_GT2		0x041A
115 | #define PCI_CHIP_HASWELL_S_GT3		0x042A
116 | #define PCI_CHIP_HASWELL_B_GT1		0x040B /* Reserved */
117 | #define PCI_CHIP_HASWELL_B_GT2		0x041B
118 | #define PCI_CHIP_HASWELL_B_GT3		0x042B
119 | #define PCI_CHIP_HASWELL_E_GT1		0x040E /* Reserved */
120 | #define PCI_CHIP_HASWELL_E_GT2		0x041E
121 | #define PCI_CHIP_HASWELL_E_GT3		0x042E
122 | #define PCI_CHIP_HASWELL_SDV_GT1	0x0C02 /* Desktop */
123 | #define PCI_CHIP_HASWELL_SDV_GT2	0x0C12
124 | #define PCI_CHIP_HASWELL_SDV_GT3	0x0C22
125 | #define PCI_CHIP_HASWELL_SDV_M_GT1	0x0C06 /* Mobile */
126 | #define PCI_CHIP_HASWELL_SDV_M_GT2	0x0C16
127 | #define PCI_CHIP_HASWELL_SDV_M_GT3	0x0C26
128 | #define PCI_CHIP_HASWELL_SDV_S_GT1	0x0C0A /* Server */
129 | #define PCI_CHIP_HASWELL_SDV_S_GT2	0x0C1A
130 | #define PCI_CHIP_HASWELL_SDV_S_GT3	0x0C2A
131 | #define PCI_CHIP_HASWELL_SDV_B_GT1	0x0C0B /* Reserved */
132 | #define PCI_CHIP_HASWELL_SDV_B_GT2	0x0C1B
133 | #define PCI_CHIP_HASWELL_SDV_B_GT3	0x0C2B
134 | #define PCI_CHIP_HASWELL_SDV_E_GT1	0x0C0E /* Reserved */
135 | #define PCI_CHIP_HASWELL_SDV_E_GT2	0x0C1E
136 | #define PCI_CHIP_HASWELL_SDV_E_GT3	0x0C2E
137 | #define PCI_CHIP_HASWELL_ULT_GT1	0x0A02 /* Desktop */
138 | #define PCI_CHIP_HASWELL_ULT_GT2	0x0A12
139 | #define PCI_CHIP_HASWELL_ULT_GT3	0x0A22
140 | #define PCI_CHIP_HASWELL_ULT_M_GT1	0x0A06 /* Mobile */
141 | #define PCI_CHIP_HASWELL_ULT_M_GT2	0x0A16
142 | #define PCI_CHIP_HASWELL_ULT_M_GT3	0x0A26
143 | #define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A /* Server */
144 | #define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
145 | #define PCI_CHIP_HASWELL_ULT_S_GT3	0x0A2A
146 | #define PCI_CHIP_HASWELL_ULT_B_GT1	0x0A0B /* Reserved */
147 | #define PCI_CHIP_HASWELL_ULT_B_GT2	0x0A1B
148 | #define PCI_CHIP_HASWELL_ULT_B_GT3	0x0A2B
149 | #define PCI_CHIP_HASWELL_ULT_E_GT1	0x0A0E /* Reserved */
150 | #define PCI_CHIP_HASWELL_ULT_E_GT2	0x0A1E
151 | #define PCI_CHIP_HASWELL_ULT_E_GT3	0x0A2E
152 | #define PCI_CHIP_HASWELL_CRW_GT1	0x0D02 /* Desktop */
153 | #define PCI_CHIP_HASWELL_CRW_GT2	0x0D12
154 | #define PCI_CHIP_HASWELL_CRW_GT3	0x0D22
155 | #define PCI_CHIP_HASWELL_CRW_M_GT1	0x0D06 /* Mobile */
156 | #define PCI_CHIP_HASWELL_CRW_M_GT2	0x0D16
157 | #define PCI_CHIP_HASWELL_CRW_M_GT3	0x0D26
158 | #define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A /* Server */
159 | #define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
160 | #define PCI_CHIP_HASWELL_CRW_S_GT3	0x0D2A
161 | #define PCI_CHIP_HASWELL_CRW_B_GT1	0x0D0B /* Reserved */
162 | #define PCI_CHIP_HASWELL_CRW_B_GT2	0x0D1B
163 | #define PCI_CHIP_HASWELL_CRW_B_GT3	0x0D2B
164 | #define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E /* Reserved */
165 | #define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
166 | #define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
167 | #define BDW_SPARE					0x2
168 | #define BDW_ULT						0x6
169 | #define BDW_IRIS					0xb
170 | #define BDW_SERVER					0xa
171 | #define BDW_WORKSTATION				0xd
172 | #define BDW_ULX						0xe
173 | 
174 | #define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */
175 | #define PCI_CHIP_VALLEYVIEW_1		0x0f31
176 | #define PCI_CHIP_VALLEYVIEW_2		0x0f32
177 | #define PCI_CHIP_VALLEYVIEW_3		0x0f33
178 | 
179 | #define PCI_CHIP_CHERRYVIEW_0		0x22b0
180 | #define PCI_CHIP_CHERRYVIEW_1		0x22b1
181 | #define PCI_CHIP_CHERRYVIEW_2		0x22b2
182 | #define PCI_CHIP_CHERRYVIEW_3		0x22b3
183 | 
184 | #define PCI_CHIP_SKYLAKE_ULT_GT2	0x1916
185 | #define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
186 | #define PCI_CHIP_SKYLAKE_ULT_GT3	0x1926
187 | #define PCI_CHIP_SKYLAKE_ULT_GT2F	0x1921
188 | #define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E
189 | #define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
190 | #define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
191 | #define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
192 | #define PCI_CHIP_SKYLAKE_HALO_GT2	0x191B
193 | #define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B
194 | #define PCI_CHIP_SKYLAKE_HALO_GT1 	0x190B
195 | #define PCI_CHIP_SKYLAKE_SRV_GT2	0x191A
196 | #define PCI_CHIP_SKYLAKE_SRV_GT3	0x192A
197 | #define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
198 | #define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
199 | 
200 | #define PCI_CHIP_BROXTON_0			0x0A84
201 | #define PCI_CHIP_BROXTON_1			0x1A84
202 | #define PCI_CHIP_BROXTON_2			0x5A84
203 | 
204 | #endif /* __GTK_DOC_IGNORE__ */
205 | 
206 | #define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
207 | 				 (devid) == PCI_CHIP_I915_GM || \
208 | 				 (devid) == PCI_CHIP_I945_GM || \
209 | 				 (devid) == PCI_CHIP_I945_GME || \
210 | 				 (devid) == PCI_CHIP_I965_GM || \
211 | 				 (devid) == PCI_CHIP_I965_GME || \
212 | 				 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
213 | 				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
214 | 				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
215 | 
216 | #define IS_G45(devid)		((devid) == PCI_CHIP_IGD_E_G || \
217 | 				 (devid) == PCI_CHIP_Q45_G || \
218 | 				 (devid) == PCI_CHIP_G45_G || \
219 | 				 (devid) == PCI_CHIP_G41_G)
220 | #define IS_GM45(devid)		((devid) == PCI_CHIP_GM45_GM)
221 | #define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
222 | 
223 | #define IS_ILD(devid)		((devid) == PCI_CHIP_ILD_G)
224 | #define IS_ILM(devid)		((devid) == PCI_CHIP_ILM_G)
225 | 
226 | #define IS_915(devid)		((devid) == PCI_CHIP_I915_G || \
227 | 				 (devid) == PCI_CHIP_E7221_G || \
228 | 				 (devid) == PCI_CHIP_I915_GM)
229 | 
230 | #define IS_945GM(devid)		((devid) == PCI_CHIP_I945_GM || \
231 | 				 (devid) == PCI_CHIP_I945_GME)
232 | 
233 | #define IS_945(devid)		((devid) == PCI_CHIP_I945_G || \
234 | 				 (devid) == PCI_CHIP_I945_GM || \
235 | 				 (devid) == PCI_CHIP_I945_GME || \
236 | 				 IS_G33(devid))
237 | 
238 | #define IS_G33(devid)		((devid) == PCI_CHIP_G33_G || \
239 | 				 (devid) == PCI_CHIP_Q33_G || \
240 | 				 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
241 | 
242 | #define IS_GEN2(devid)		((devid) == PCI_CHIP_I830_M || \
243 | 				 (devid) == PCI_CHIP_845_G || \
244 | 				 (devid) == PCI_CHIP_I855_GM || \
245 | 				 (devid) == PCI_CHIP_I865_G)
246 | 
247 | #define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
248 | 
249 | #define IS_GEN4(devid)		((devid) == PCI_CHIP_I965_G || \
250 | 				 (devid) == PCI_CHIP_I965_Q || \
251 | 				 (devid) == PCI_CHIP_I965_G_1 || \
252 | 				 (devid) == PCI_CHIP_I965_GM || \
253 | 				 (devid) == PCI_CHIP_I965_GME || \
254 | 				 (devid) == PCI_CHIP_I946_GZ || \
255 | 				 IS_G4X(devid))
256 | 
257 | #define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
258 | 
259 | #define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
260 | 				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
261 | 				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
262 | 				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
263 | 				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
264 | 				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
265 | 				 (devid) == PCI_CHIP_SANDYBRIDGE_S)
266 | 
267 | #define IS_GEN7(devid)		(IS_IVYBRIDGE(devid) || \
268 | 				 IS_HASWELL(devid) || \
269 | 				 IS_VALLEYVIEW(devid))
270 | 
271 | #define IS_IVYBRIDGE(devid)	((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
272 | 				 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
273 | 				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
274 | 				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
275 | 				 (devid) == PCI_CHIP_IVYBRIDGE_S || \
276 | 				 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
277 | 
278 | #define IS_VALLEYVIEW(devid)	((devid) == PCI_CHIP_VALLEYVIEW_PO || \
279 | 				 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
280 | 				 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
281 | 				 (devid) == PCI_CHIP_VALLEYVIEW_3)
282 | 
283 | #define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \
284 | 				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
285 | 				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
286 | 				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
287 | 				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
288 | 				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
289 | 				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
290 | 				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
291 | 				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
292 | 				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
293 | 				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
294 | 				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
295 | 				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
296 | 				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
297 | 				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
298 | 				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
299 | 				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
300 | 				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
301 | 				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
302 | 				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
303 | #define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \
304 | 				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
305 | 				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
306 | 				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
307 | 				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
308 | 				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
309 | 				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
310 | 				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
311 | 				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
312 | 				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
313 | 				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
314 | 				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
315 | 				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
316 | 				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
317 | 				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
318 | 				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
319 | 				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
320 | 				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
321 | 				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
322 | 				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
323 | #define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \
324 | 				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
325 | 				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
326 | 				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
327 | 				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
328 | 				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
329 | 				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
330 | 				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
331 | 				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
332 | 				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
333 | 				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
334 | 				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
335 | 				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
336 | 				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
337 | 				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
338 | 				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
339 | 				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
340 | 				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
341 | 				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
342 | 				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
343 | 
344 | #define IS_HASWELL(devid)	(IS_HSW_GT1(devid) || \
345 | 				 IS_HSW_GT2(devid) || \
346 | 				 IS_HSW_GT3(devid))
347 | 
348 | #define IS_BROADWELL(devid)	((((devid) & 0xff00) != 0x1600) ? 0 : \
349 | 				((((devid) & 0x00f0) >> 4) > 3) ? 0 : \
350 | 				 (((devid) & 0x000f) == BDW_SPARE) ? 1 : \
351 | 				 (((devid) & 0x000f) == BDW_ULT) ? 1 : \
352 | 				 (((devid) & 0x000f) == BDW_IRIS) ? 1 : \
353 | 				 (((devid) & 0x000f) == BDW_SERVER) ? 1 : \
354 | 				 (((devid) & 0x000f) == BDW_WORKSTATION) ? 1 : \
355 | 				 (((devid) & 0x000f) == BDW_ULX) ? 1 : 0)
356 | 
357 | #define IS_CHERRYVIEW(devid)	((devid) == PCI_CHIP_CHERRYVIEW_0 || \
358 | 				 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
359 | 				 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
360 | 				 (devid) == PCI_CHIP_CHERRYVIEW_3)
361 | 
362 | #define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
363 | 				 IS_CHERRYVIEW(devid))
364 | 
365 | #define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
366 | 				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
367 | 				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
368 | 				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT1	|| \
369 | 				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
370 | 
371 | #define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
372 | 				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F	|| \
373 | 				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
374 | 				 (devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
375 | 				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
376 | 				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
377 | 				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
378 | 
379 | #define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3	|| \
380 | 				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
381 | 				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
382 | 
383 | #define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
384 | 				 IS_SKL_GT2(devid) || \
385 | 				 IS_SKL_GT3(devid))
386 | 
387 | #define IS_BROXTON(devid)	((devid) == PCI_CHIP_BROXTON_0	|| \
388 | 				 (devid) == PCI_CHIP_BROXTON_1	|| \
389 | 				 (devid) == PCI_CHIP_BROXTON_2)
390 | 
391 | #define IS_GEN9(devid)		(IS_SKYLAKE(devid) || \
392 | 				 IS_BROXTON(devid))
393 | 
394 | #define IS_965(devid)		(IS_GEN4(devid) || \
395 | 				 IS_GEN5(devid) || \
396 | 				 IS_GEN6(devid) || \
397 | 				 IS_GEN7(devid) || \
398 | 				 IS_GEN8(devid))
399 | 
400 | #define IS_9XX(devid)		(IS_GEN3(devid) || \
401 | 				 IS_GEN4(devid) || \
402 | 				 IS_GEN5(devid) || \
403 | 				 IS_GEN6(devid) || \
404 | 				 IS_GEN7(devid) || \
405 | 				 IS_GEN8(devid) || \
406 | 				 IS_GEN9(devid))
407 | 
408 | #define IS_INTEL(devid)		(IS_GEN2(devid) || \
409 | 				 IS_GEN3(devid) || \
410 | 				 IS_GEN4(devid) || \
411 | 				 IS_GEN5(devid) || \
412 | 				 IS_GEN6(devid) || \
413 | 				 IS_GEN7(devid) || \
414 | 				 IS_GEN8(devid))
415 | 
416 | #define HAS_PCH_SPLIT(devid)	(IS_GEN5(devid) || \
417 | 				 IS_GEN6(devid) || \
418 | 				 IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
419 | 				 IS_BROADWELL(devid) || \
420 | 				 IS_SKYLAKE(devid))
421 | 
422 | #define HAS_BLT_RING(devid)	(IS_GEN6(devid) || \
423 | 				 IS_GEN7(devid) || \
424 | 				 IS_GEN8(devid))
425 | 
426 | #define HAS_BSD_RING(devid)	(IS_GEN5(devid) || \
427 | 				 IS_GEN6(devid) || \
428 | 				 IS_GEN7(devid) || \
429 | 				 IS_GEN8(devid))
430 | 
431 | #define IS_BROADWATER(devid)	((devid) == PCI_CHIP_I946_GZ || \
432 | 				 (devid) == PCI_CHIP_I965_G_1 || \
433 | 				 (devid) == PCI_CHIP_I965_Q || \
434 | 				 (devid) == PCI_CHIP_I965_G)
435 | 
436 | #define IS_CRESTLINE(devid)	((devid) == PCI_CHIP_I965_GM || \
437 | 				 (devid) == PCI_CHIP_I965_GME)
438 | 
439 | #define HAS_VEBOX_RING(devid)   (IS_HASWELL(devid))
440 | 
441 | #endif /* _INTEL_CHIPSET_H */
442 | 


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
 1 | AppleIntelInfo.kext
 2 | ===================
 3 | 
 4 | What do I need to do?
 5 | 
 6 | Step 1.) Download the project from Github and compile it with Xcode.
 7 | 
 8 | Step 2.) Fix file ownership and permissions.
 9 | 
10 | ``` sh
11 | sudo chown -R root:wheel AppleIntelInfo.kext
12 | sudo chmod -R 755 AppleIntelInfo.kext
13 | ```
14 | 
15 | Step 3.) Load AppleIntelInfo.kext?
16 | 
17 | ``` sh
18 | sudo kextload AppleIntelInfo.kext
19 | 
20 | or with
21 | 
22 | sudo kextutil AppleIntelInfo.kext 
23 | ```
24 | Warning: Do not copy the kext to: /System/Library/Extensions or /Library/Extensions and do not inject it with help of the boot loader!
25 | 
26 | Step 4.) Unload AppleIntelInfo.kext?
27 | 
28 | ``` sh
29 | sudo kextunload AppleIntelInfo.kext
30 | ```
31 | 
32 | Where can I find the output?
33 | 
34 | 
35 | The output of AppleIntelInfo.kext can be found with
36 | ``` sh
37 | sudo cat /tmp/AppleIntelInfo.dat
38 | ```
39 | 
40 | Note: This has changed in version 1.2 (data no longer added to /var/log/system.log)
41 | 
42 | Settings
43 | --------
44 | 
45 | There are five (5) settings that you can change in AppleIntelInfo.kext/Contents/Info.plist:
46 | ```
47 | logCStates
48 | logIGPU
49 | logIPGStyle
50 | logIntelRegs
51 | logMSRs
52 | ```
53 | 
54 | All set to YES by default.
55 | 
56 | Bugs
57 | ----
58 | 
59 | All possible bugs (so called 'issues') should be filed at:
60 | 
61 | https://github.com/Piker-Alpha/AppleIntelInfo/issues
62 | 
63 | Please do **not** use my blog for this. Thank you!
64 | 


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