├── README.md ├── base_modules ├── carry_lookahead_logic_4_bit.v ├── full_adder.v ├── mux_2_bit.v ├── mux_2_bit_16_wide.v ├── mux_2_bit_4_wide.v ├── mux_5_bit.v ├── one_hot_4_bit.v └── one_hot_5_bit.v ├── fig_01_block_002.v ├── fig_04a_block_050.v ├── fig_04b_block_052.v ├── fig_04b_block_068_070_072_094_096.v ├── fig_04b_block_076.v ├── fig_04b_block_076_registers.v ├── fig_04b_block_076_x_select.v ├── fig_04b_block_076_y_select.v ├── fig_04b_block_078.v ├── fig_06_block_152.v ├── fig_07_block_206.v ├── fig_08a_block_200.v ├── fig_08b.v ├── fig_08b_bit_matrix.v ├── fig_08b_bit_plane.v ├── fig_14_block_094.v ├── fig_14_block_502.v ├── fig_14_block_502_subtractor.v ├── fig_14_block_506.v ├── fig_17_register_04.v ├── fig_17_register_15.v ├── mux_3_bit.v ├── mux_3_bit_8_wide.v ├── one_hot_3_bit.v ├── test_stimulus ├── fig_04a_block_050.tcl ├── fig_04b_block_068_070_072_094_096.tcl ├── fig_04b_block_078.tcl ├── fig_06_block_152.tcl ├── fig_07_block_206.tcl ├── fig_08b.tcl ├── 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