├── .gitignore ├── workspace └── .gitignore ├── crosshatch.dtb ├── azure-pipelines.yml ├── firstrun.sh ├── ci-build.sh ├── Pixel3XL ├── Pixel3XLDxe │ ├── Pixel3XLDxe.h │ ├── Pixel3XLDxe.inf │ └── Pixel3XLDxe.c ├── Library │ ├── InMemorySerialPortLib │ │ ├── InMemorySerialPortLib.uni │ │ ├── InMemorySerialPortLib.inf │ │ └── InMemorySerialPortLib.c │ └── Pixel3XLLib │ │ ├── Pixel3XLLib.inf │ │ ├── Pixel3XLHelper.S │ │ ├── Pixel3XL.c │ │ └── Pixel3XLMem.c ├── SimpleFbDxe │ ├── SimpleFbDxe.inf │ └── SimpleFbDxe.c ├── Pixel3XL.dec ├── Drivers │ └── SmbiosPlatformDxe │ │ ├── SmbiosPlatformDxe.inf │ │ └── SmbiosPlatformDxe.c ├── AcpiTables │ ├── AcpiTables.inf │ ├── Spcr.aslc │ ├── Dbg2.aslc │ ├── Gtdt.aslc │ ├── Fadt.aslc │ ├── Madt.aslc │ ├── AcpiSsdtRootPci.asl │ └── Dsdt.asl ├── Include │ └── ArmPlatform.h ├── CommonFdf.fdf.inc ├── Pixel3XL.fdf ├── Pixel3XL.dsc └── CommonDsc.dsc.inc └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | uefi.img 2 | -------------------------------------------------------------------------------- /workspace/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | -------------------------------------------------------------------------------- /crosshatch.dtb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Pixel3Dev/edk2-pixel3/HEAD/crosshatch.dtb -------------------------------------------------------------------------------- /azure-pipelines.yml: -------------------------------------------------------------------------------- 1 | trigger: 2 | - master 3 | 4 | pool: 5 | vmImage: 'Ubuntu-16.04' 6 | 7 | steps: 8 | - script: | 9 | ./ci-build.sh 10 | displayName: 'ci-build' 11 | -------------------------------------------------------------------------------- /firstrun.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # based on the instructions from edk2-platform 3 | # do this first: 4 | # https://github.com/tianocore/tianocore.github.io/wiki/Using-EDK-II-with-Native-GCC#Install_required_software_from_apt 5 | set -e 6 | . build_common.sh 7 | make -C ../edk2/BaseTools 8 | 9 | -------------------------------------------------------------------------------- /ci-build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | sudo apt update 4 | sudo apt install -y build-essential uuid-dev iasl git nasm gcc-aarch64-linux-gnu bc 5 | curdir="$PWD" 6 | cd .. 7 | git clone https://github.com/tianocore/edk2.git --recursive 8 | git clone https://github.com/tianocore/edk2-platforms.git 9 | cd "$curdir" 10 | ./firstrun.sh 11 | ./build.sh 12 | -------------------------------------------------------------------------------- /Pixel3XL/Pixel3XLDxe/Pixel3XLDxe.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | * 3 | * Copyright (c) 2018, Linaro Ltd. All rights reserved. 4 | * 5 | * This program and the accompanying materials 6 | * are licensed and made available under the terms and conditions of the BSD License 7 | * which accompanies this distribution. The full text of the license may be found at 8 | * http://opensource.org/licenses/bsd-license.php 9 | * 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 | * 13 | **/ 14 | 15 | #ifndef __PIXEL3XLDXE_H__ 16 | #define __PIXEL3XLDXE_H__ 17 | 18 | #endif /* __PIXEL3XLDXE_H__ */ 19 | -------------------------------------------------------------------------------- /Pixel3XL/Library/InMemorySerialPortLib/InMemorySerialPortLib.uni: -------------------------------------------------------------------------------- 1 | // /** @file 2 | // Null instance of Serial Port Library with empty functions. 3 | // 4 | // Null instance of Serial Port Library with empty functions. 5 | // 6 | // Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
7 | // 8 | // This program and the accompanying materials 9 | // are licensed and made available under the terms and conditions of the BSD License 10 | // which accompanies this distribution. The full text of the license may be found at 11 | // http://opensource.org/licenses/bsd-license.php. 12 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 | // 15 | // **/ 16 | 17 | 18 | #string STR_MODULE_ABSTRACT #language en-US "Serial Port Library that dumps everything written to in memory buffer" 19 | 20 | #string STR_MODULE_DESCRIPTION #language en-US "Serial Port Library that dumps everything written to in memory buffer" 21 | 22 | -------------------------------------------------------------------------------- /Pixel3XL/Library/InMemorySerialPortLib/InMemorySerialPortLib.inf: -------------------------------------------------------------------------------- 1 | ## @file 2 | # Null instance of Serial Port Library with empty functions. 3 | # 4 | # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
5 | # 6 | # This program and the accompanying materials 7 | # are licensed and made available under the terms and conditions of the BSD License 8 | # which accompanies this distribution. The full text of the license may be found at 9 | # http://opensource.org/licenses/bsd-license.php. 10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 | # 13 | # 14 | ## 15 | 16 | [Defines] 17 | INF_VERSION = 0x00010005 18 | BASE_NAME = InMemorySerialPortLib 19 | MODULE_UNI_FILE = InMemorySerialPortLib.uni 20 | FILE_GUID = 762fbf9a-984a-4960-9c7c-e0a076860304 21 | MODULE_TYPE = BASE 22 | VERSION_STRING = 1.0 23 | LIBRARY_CLASS = SerialPortLib 24 | 25 | 26 | # 27 | # VALID_ARCHITECTURES = IA32 X64 EBC 28 | # 29 | 30 | [Sources] 31 | InMemorySerialPortLib.c 32 | 33 | 34 | [Packages] 35 | MdePkg/MdePkg.dec 36 | 37 | [LibraryClasses] 38 | CacheMaintenanceLib 39 | 40 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Attempt to create a minimal EDK2 for Pixel 3 XL. 2 | 3 | [![Build Status](https://dev.azure.com/zhuoweizhang/edk2-pixel3/_apis/build/status/Pixel3Dev.edk2-pixel3?branchName=master)](https://dev.azure.com/zhuoweizhang/edk2-pixel3/_build/latest?definitionId=1&branchName=master) 4 | 5 | ## Status 6 | 7 | Can partially boot the Fedora 29 aarch64 kernel: there's no initrd, so the kernel panics when mounting root FS. 8 | 9 | Since there's no internal storage support yet, use the addlinux branch to embed a Linux kernel in the UEFI firmware. 10 | 11 | ## Building 12 | Tested on Ubuntu 18.04. 13 | 14 | First, clone EDK2. 15 | 16 | ``` 17 | cd .. 18 | git clone https://github.com/tianocore/edk2.git --recursive 19 | git clone https://github.com/tianocore/edk2-platforms.git 20 | ``` 21 | 22 | You should have all three directories side by side. 23 | 24 | Next, install dependencies: 25 | 26 | 18.04: 27 | 28 | ``` 29 | sudo apt install build-essential uuid-dev iasl git nasm python3-distutils gcc-aarch64-linux-gnu 30 | ``` 31 | 32 | Also see [EDK2 website](https://github.com/tianocore/tianocore.github.io/wiki/Using-EDK-II-with-Native-GCC#Install_required_software_from_apt) 33 | 34 | Finally, ./build.sh. 35 | 36 | Then fastboot boot uefi.img. 37 | 38 | # Credits 39 | 40 | SimpleFbDxe screen driver is from imbushuo's [Lumia950XLPkg](https://github.com/WOA-Project/Lumia950XLPkg). 41 | -------------------------------------------------------------------------------- /Pixel3XL/SimpleFbDxe/SimpleFbDxe.inf: -------------------------------------------------------------------------------- 1 | # SimpleFbDxe.inf: Implements Simple FrameBuffer in UEFI. 2 | 3 | [Defines] 4 | INF_VERSION = 0x00010005 5 | BASE_NAME = SimpleFbDxe 6 | FILE_GUID = dcfd1e6d-788d-4ffc-8e1b-ca2f75651a92 7 | MODULE_TYPE = DXE_DRIVER 8 | VERSION_STRING = 1.0 9 | ENTRY_POINT = SimpleFbDxeInitialize 10 | 11 | [Sources.common] 12 | SimpleFbDxe.c 13 | 14 | [Packages] 15 | MdePkg/MdePkg.dec 16 | MdeModulePkg/MdeModulePkg.dec 17 | EmbeddedPkg/EmbeddedPkg.dec 18 | ArmPkg/ArmPkg.dec 19 | Pixel3XL/Pixel3XL.dec 20 | 21 | [LibraryClasses] 22 | BaseLib 23 | ReportStatusCodeLib 24 | UefiLib 25 | UefiBootServicesTableLib 26 | UefiDriverEntryPoint 27 | BaseMemoryLib 28 | DebugLib 29 | PcdLib 30 | FrameBufferBltLib 31 | CacheMaintenanceLib 32 | 33 | [Protocols] 34 | gEfiGraphicsOutputProtocolGuid ## PRODUCES 35 | gEfiCpuArchProtocolGuid 36 | 37 | [FixedPcd] 38 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferAddress 39 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferWidth 40 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferHeight 41 | 42 | [Guids] 43 | gEfiMdeModulePkgTokenSpaceGuid 44 | 45 | [Pcd] 46 | gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution 47 | gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution 48 | 49 | [Depex] 50 | gEfiCpuArchProtocolGuid 51 | 52 | -------------------------------------------------------------------------------- /Pixel3XL/Pixel3XLDxe/Pixel3XLDxe.inf: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2018, Linaro Limited. All rights reserved. 3 | # 4 | # This program and the accompanying materials 5 | # are licensed and made available under the terms and conditions of the BSD License 6 | # which accompanies this distribution. The full text of the license may be found at 7 | # http://opensource.org/licenses/bsd-license.php 8 | # 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 | # 12 | 13 | [Defines] 14 | INF_VERSION = 0x0001001a 15 | BASE_NAME = Pixel3XLDxe 16 | FILE_GUID = 422BB380-0FFB-41EC-B86E-AE70F8A02DA3 17 | MODULE_TYPE = DXE_DRIVER 18 | VERSION_STRING = 1.0 19 | ENTRY_POINT = Pixel3XLEntryPoint 20 | 21 | [Sources.common] 22 | Pixel3XLDxe.c 23 | 24 | [Packages] 25 | EmbeddedPkg/EmbeddedPkg.dec 26 | MdeModulePkg/MdeModulePkg.dec 27 | MdePkg/MdePkg.dec 28 | 29 | [LibraryClasses] 30 | BaseMemoryLib 31 | CacheMaintenanceLib 32 | DxeServicesTableLib 33 | IoLib 34 | PcdLib 35 | TimerLib 36 | UefiDriverEntryPoint 37 | UefiLib 38 | 39 | [Protocols] 40 | gEfiDevicePathFromTextProtocolGuid 41 | gEfiLoadedImageProtocolGuid 42 | gEfiCpuArchProtocolGuid 43 | 44 | [Guids] 45 | gEfiEndOfDxeEventGroupGuid 46 | 47 | [Depex] 48 | gEfiCpuArchProtocolGuid 49 | -------------------------------------------------------------------------------- /Pixel3XL/Library/Pixel3XLLib/Pixel3XLLib.inf: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2018, Linaro Limited. All rights reserved. 3 | # 4 | # This program and the accompanying materials 5 | # are licensed and made available under the terms and conditions of the BSD License 6 | # which accompanies this distribution. The full text of the license may be found at 7 | # http://opensource.org/licenses/bsd-license.php 8 | # 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 | # 12 | 13 | [Defines] 14 | INF_VERSION = 0x00010019 15 | BASE_NAME = Pixel3XLLib 16 | FILE_GUID = 61620091-45BA-4EFF-8F58-F7ABF228CEBC 17 | MODULE_TYPE = BASE 18 | VERSION_STRING = 1.0 19 | LIBRARY_CLASS = ArmPlatformLib 20 | 21 | [Packages] 22 | ArmPkg/ArmPkg.dec 23 | ArmPlatformPkg/ArmPlatformPkg.dec 24 | EmbeddedPkg/EmbeddedPkg.dec 25 | MdePkg/MdePkg.dec 26 | MdeModulePkg/MdeModulePkg.dec 27 | 28 | [LibraryClasses] 29 | ArmLib 30 | HobLib 31 | IoLib 32 | MemoryAllocationLib 33 | SerialPortLib 34 | 35 | [Sources.common] 36 | Pixel3XL.c 37 | Pixel3XLHelper.S 38 | Pixel3XLMem.c 39 | 40 | [FixedPcd] 41 | gArmTokenSpaceGuid.PcdArmPrimaryCore 42 | gArmTokenSpaceGuid.PcdArmPrimaryCoreMask 43 | gArmTokenSpaceGuid.PcdSystemMemoryBase 44 | gArmTokenSpaceGuid.PcdSystemMemorySize 45 | gArmTokenSpaceGuid.PcdFdBaseAddress 46 | gArmTokenSpaceGuid.PcdFdSize 47 | -------------------------------------------------------------------------------- /Pixel3XL/Pixel3XL.dec: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2018, Linaro Limited. All rights reserved. 3 | # 4 | # This program and the accompanying materials 5 | # are licensed and made available under the terms and conditions of the BSD License 6 | # which accompanies this distribution. The full text of the license may be found at 7 | # http://opensource.org/licenses/bsd-license.php 8 | # 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 | # 12 | 13 | [Defines] 14 | DEC_SPECIFICATION = 0x0001001a 15 | PACKAGE_NAME = Pixel3XL 16 | PACKAGE_GUID = 7eb1de03-3910-4d1d-84ce-c17b53636b9a 17 | PACKAGE_VERSION = 0.1 18 | 19 | ################################################################################ 20 | # 21 | # Include Section - list of Include Paths that are provided by this package. 22 | # Comments are used for Keywords and Module Types. 23 | # 24 | # Supported Module Types: 25 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION 26 | # 27 | ################################################################################ 28 | [Includes.common] 29 | Include # Root include for the package 30 | 31 | [Guids.common] 32 | gPixel3XLTokenSpaceGuid = { 0x99a14446, 0xaad7, 0xe460, {0xb4, 0xe5, 0x1f, 0x79, 0xaa, 0xa4, 0x93, 0xfd } } 33 | 34 | [PcdsFixedAtBuild.common] 35 | # Simple FrameBuffer 36 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferAddress|0x00400000|UINT32|0x0000a400 37 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferWidth|1080|UINT32|0x0000a401 38 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferHeight|1920|UINT32|0x0000a402 39 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferPixelBpp|32|UINT32|0x0000a403 40 | -------------------------------------------------------------------------------- /Pixel3XL/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf: -------------------------------------------------------------------------------- 1 | ## @file 2 | # This driver installs SMBIOS information for ArmJuno 3 | # 4 | # Copyright (c) 2011, Bei Guan 5 | # Copyright (c) 2011, Intel Corporation. All rights reserved. 6 | # Copyright (c) 2015, ARM Limited. All rights reserved. 7 | # 8 | # This program and the accompanying materials 9 | # are licensed and made available under the terms and conditions of the BSD License 10 | # which accompanies this distribution. The full text of the license may be found at 11 | # http://opensource.org/licenses/bsd-license.php 12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 | # 15 | ## 16 | 17 | [Defines] 18 | INF_VERSION = 0x00010005 19 | BASE_NAME = SmbiosPlatformDxe 20 | FILE_GUID = B736DF5D-59ED-48C0-AC10-1EEE228D085B 21 | MODULE_TYPE = DXE_DRIVER 22 | VERSION_STRING = 1.0 23 | 24 | ENTRY_POINT = SmbiosTablePublishEntry 25 | 26 | # 27 | # The following information is for reference only and not required by the build tools. 28 | # 29 | # VALID_ARCHITECTURES = AARCH64 30 | # 31 | 32 | [Sources] 33 | SmbiosPlatformDxe.c 34 | 35 | [Packages] 36 | ArmPkg/ArmPkg.dec 37 | ArmPlatformPkg/ArmPlatformPkg.dec 38 | MdeModulePkg/MdeModulePkg.dec 39 | MdePkg/MdePkg.dec 40 | Pixel3XL/Pixel3XL.dec 41 | 42 | [LibraryClasses] 43 | ArmLib 44 | BaseMemoryLib 45 | BaseLib 46 | DebugLib 47 | HobLib 48 | IoLib 49 | MemoryAllocationLib 50 | PcdLib 51 | UefiBootServicesTableLib 52 | UefiDriverEntryPoint 53 | 54 | [Guids] 55 | gEfiGlobalVariableGuid 56 | 57 | [FixedPcd] 58 | gArmTokenSpaceGuid.PcdSystemMemoryBase 59 | gArmTokenSpaceGuid.PcdSystemMemorySize 60 | gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision 61 | 62 | [Protocols] 63 | gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED 64 | 65 | [Guids] 66 | 67 | [Depex] 68 | gEfiSmbiosProtocolGuid 69 | -------------------------------------------------------------------------------- /Pixel3XL/AcpiTables/AcpiTables.inf: -------------------------------------------------------------------------------- 1 | ## @file 2 | # 3 | # ACPI table data and ASL sources required to boot the platform. 4 | # 5 | # Copyright (c) 2014-2017, ARM Ltd. All rights reserved. 6 | # 7 | # This program and the accompanying materials 8 | # are licensed and made available under the terms and conditions of the BSD License 9 | # which accompanies this distribution. The full text of the license may be found at 10 | # http://opensource.org/licenses/bsd-license.php 11 | # 12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 | # 15 | ## 16 | 17 | [Defines] 18 | INF_VERSION = 0x00010005 19 | BASE_NAME = Pixel3XLAcpiTables 20 | FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD # Must be this 21 | MODULE_TYPE = USER_DEFINED 22 | VERSION_STRING = 1.0 23 | 24 | [Sources] 25 | Dsdt.asl 26 | Dbg2.aslc 27 | #Spcr.aslc 28 | Fadt.aslc 29 | Gtdt.aslc 30 | Madt.aslc 31 | #AcpiSsdtRootPci.asl # Juno R1 specific 32 | 33 | [Packages] 34 | ArmPkg/ArmPkg.dec 35 | ArmPlatformPkg/ArmPlatformPkg.dec 36 | EmbeddedPkg/EmbeddedPkg.dec 37 | MdePkg/MdePkg.dec 38 | MdeModulePkg/MdeModulePkg.dec 39 | Pixel3XL/Pixel3XL.dec 40 | 41 | [FixedPcd] 42 | gArmPlatformTokenSpaceGuid.PcdCoreCount 43 | gArmTokenSpaceGuid.PcdGicDistributorBase 44 | gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase 45 | gArmTokenSpaceGuid.PcdGicRedistributorsBase 46 | 47 | gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum 48 | gArmTokenSpaceGuid.PcdArmArchTimerIntrNum 49 | gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum 50 | gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum 51 | 52 | gArmTokenSpaceGuid.PcdGenericWatchdogControlBase 53 | gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase 54 | 55 | # 56 | # PL011 UART Settings for Serial Port Console Redirection 57 | # 58 | gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase 59 | gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate 60 | gArmPlatformTokenSpaceGuid.PL011UartClkInHz 61 | gArmPlatformTokenSpaceGuid.PL011UartInterrupt 62 | 63 | gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase 64 | 65 | gArmPlatformTokenSpaceGuid.PcdWatchdogCount 66 | -------------------------------------------------------------------------------- /Pixel3XL/Library/Pixel3XLLib/Pixel3XLHelper.S: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2018, Linaro Limited. All rights reserved. 3 | # 4 | # This program and the accompanying materials 5 | # are licensed and made available under the terms and conditions of the BSD License 6 | # which accompanies this distribution. The full text of the license may be found at 7 | # http://opensource.org/licenses/bsd-license.php 8 | # 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 | # 12 | # 13 | 14 | #include 15 | #include 16 | 17 | .text 18 | .align 3 19 | 20 | ASM_FUNC(ArmPlatformPeiBootAction) 21 | startlabel: 22 | // check if we're located at expected location 23 | adr x4, . 24 | ldr x5, =ArmPlatformPeiBootAction 25 | cmp x4, x5 26 | bne docopy 27 | ret 28 | docopy: 29 | // find our start address by getting our expected offset, then subtracting it from our actual address 30 | ldr x6, =FixedPcdGet64 (PcdFdBaseAddress) 31 | sub x5, x5, x6 // x5 now holds offset of ArmPlatformPeiBootAction from start of FD base 32 | sub x4, x4, x5 // x4 now holds address of actual FD base 33 | // tweak the return address 34 | // note: x30 is lr; gcc5 doesn't have the alias 35 | sub x30, x30, x4 36 | add x30, x30, x6 37 | ldr x5, =FixedPcdGet64 (PcdFdSize) 38 | // crap memcpy 39 | loop: 40 | ldp x2, x3, [x4], #16 41 | stp x2, x3, [x6], #16 42 | subs x5, x5, #16 43 | b.ne loop 44 | ret 45 | .ltorg 46 | 47 | //UINTN 48 | //ArmPlatformIsPrimaryCore ( 49 | // IN UINTN MpId 50 | // ); 51 | ASM_FUNC(ArmPlatformIsPrimaryCore) 52 | MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) 53 | and x0, x0, x1 54 | MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) 55 | cmp w0, w1 56 | cset x0, eq 57 | ret 58 | 59 | //UINTN 60 | //ArmPlatformGetPrimaryCoreMpId ( 61 | // VOID 62 | // ); 63 | ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) 64 | MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) 65 | ret 66 | 67 | //UINTN 68 | //ArmPlatformGetCorePosition ( 69 | // IN UINTN MpId 70 | // ); 71 | // With this function: CorePos = (ClusterId * 4) + CoreId 72 | ASM_FUNC(ArmPlatformGetCorePosition) 73 | and x1, x0, #ARM_CORE_MASK 74 | and x0, x0, #ARM_CLUSTER_MASK 75 | add x0, x1, x0, LSR #6 76 | ret 77 | -------------------------------------------------------------------------------- /Pixel3XL/Include/ArmPlatform.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | * 3 | * Copyright (c) 2013-2017, ARM Limited. All rights reserved. 4 | * 5 | * This program and the accompanying materials 6 | * are licensed and made available under the terms and conditions of the BSD License 7 | * which accompanies this distribution. The full text of the license may be found at 8 | * http://opensource.org/licenses/bsd-license.php 9 | * 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 | * 13 | **/ 14 | 15 | #ifndef __ARM_JUNO_H__ 16 | #define __ARM_JUNO_H__ 17 | 18 | //#include 19 | 20 | /*********************************************************************************** 21 | // Platform Memory Map 22 | ************************************************************************************/ 23 | 24 | // Motherboard Peripheral and On-chip peripheral 25 | 26 | // 27 | // ACPI table information used to initialize tables. 28 | // 29 | #define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long 30 | #define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long 31 | #define EFI_ACPI_ARM_OEM_REVISION 0x20140727 32 | #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ') 33 | #define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099 34 | 35 | // A macro to initialise the common header part of EFI ACPI tables as defined by 36 | // EFI_ACPI_DESCRIPTION_HEADER structure. 37 | #define ARM_ACPI_HEADER(Signature, Type, Revision) { \ 38 | Signature, /* UINT32 Signature */ \ 39 | sizeof (Type), /* UINT32 Length */ \ 40 | Revision, /* UINT8 Revision */ \ 41 | 0, /* UINT8 Checksum */ \ 42 | { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \ 43 | EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ 44 | EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \ 45 | EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \ 46 | EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ 47 | } 48 | 49 | // 50 | // Hardware platform identifiers 51 | // 52 | #define JUNO_REVISION_PROTOTYPE 0 53 | #define JUNO_REVISION_R0 1 54 | #define JUNO_REVISION_R1 2 55 | #define JUNO_REVISION_R2 3 56 | #define JUNO_REVISION_UKNOWN 0xFF 57 | 58 | // Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest 59 | //#define ARM_JUNO_ACPI_5_0 60 | 61 | // 62 | // Address of the system registers that contain the MAC address 63 | // assigned to the PCI Gigabyte Ethernet device. 64 | // 65 | 66 | /*********************************************************************************** 67 | // Motherboard memory-mapped peripherals 68 | ************************************************************************************/ 69 | 70 | // Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE) 71 | // 72 | // Sites where the peripheral is fitted 73 | // 74 | #endif 75 | -------------------------------------------------------------------------------- /Pixel3XL/Pixel3XLDxe/Pixel3XLDxe.c: -------------------------------------------------------------------------------- 1 | /** @file 2 | * 3 | * Copyright (c) 2018, Linaro Ltd. All rights reserved. 4 | * 5 | * This program and the accompanying materials 6 | * are licensed and made available under the terms and conditions of the BSD License 7 | * which accompanies this distribution. The full text of the license may be found at 8 | * http://opensource.org/licenses/bsd-license.php 9 | * 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 | * 13 | **/ 14 | 15 | #include 16 | 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | 31 | #include 32 | #include 33 | #include 34 | #include 35 | #include 36 | 37 | #include "Pixel3XLDxe.h" 38 | 39 | EFI_CPU_ARCH_PROTOCOL *gCpu; 40 | 41 | VOID 42 | InitPeripherals ( 43 | IN VOID 44 | ) 45 | { 46 | /* This also crashes. Do you really hate memory attributes or something? 47 | EFI_STATUS Status; 48 | // https://lists.01.org/pipermail/edk2-devel/2017-August/013417.html 49 | Status = gCpu->SetMemoryAttributes (gCpu, 0xa1a10000, 0x200000, 50 | EFI_MEMORY_UC | EFI_MEMORY_XP); 51 | ASSERT_EFI_ERROR (Status); 52 | Status = gCpu->SetMemoryAttributes (gCpu, 0x9d400000, 0x2400000, 53 | EFI_MEMORY_WC | EFI_MEMORY_XP); 54 | ASSERT_EFI_ERROR (Status); 55 | */ 56 | } 57 | 58 | /** 59 | Notification function of the event defined as belonging to the 60 | EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in 61 | the entry point of the driver. 62 | 63 | This function is called when an event belonging to the 64 | EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an 65 | event is signalled once at the end of the dispatching of all 66 | drivers (end of the so called DXE phase). 67 | 68 | @param[in] Event Event declared in the entry point of the driver whose 69 | notification function is being invoked. 70 | @param[in] Context NULL 71 | **/ 72 | STATIC 73 | VOID 74 | OnEndOfDxe ( 75 | IN EFI_EVENT Event, 76 | IN VOID *Context 77 | ) 78 | { 79 | } 80 | 81 | EFI_STATUS 82 | EFIAPI 83 | Pixel3XLEntryPoint ( 84 | IN EFI_HANDLE ImageHandle, 85 | IN EFI_SYSTEM_TABLE *SystemTable 86 | ) 87 | { 88 | EFI_STATUS Status; 89 | EFI_EVENT EndOfDxeEvent; 90 | 91 | Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu); 92 | ASSERT_EFI_ERROR(Status); 93 | 94 | InitPeripherals (); 95 | 96 | // 97 | // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group. 98 | // The "OnEndOfDxe()" function is declared as the call back function. 99 | // It will be called at the end of the DXE phase when an event of the 100 | // same group is signalled to inform about the end of the DXE phase. 101 | // Install the INSTALL_FDT_PROTOCOL protocol. 102 | // 103 | Status = gBS->CreateEventEx ( 104 | EVT_NOTIFY_SIGNAL, 105 | TPL_CALLBACK, 106 | OnEndOfDxe, 107 | NULL, 108 | &gEfiEndOfDxeEventGroupGuid, 109 | &EndOfDxeEvent 110 | ); 111 | return Status; 112 | } 113 | -------------------------------------------------------------------------------- /Pixel3XL/Library/Pixel3XLLib/Pixel3XL.c: -------------------------------------------------------------------------------- 1 | /** @file 2 | * 3 | * Copyright (c) 2018, Linaro Limited. All rights reserved. 4 | * 5 | * This program and the accompanying materials 6 | * are licensed and made available under the terms and conditions of the BSD License 7 | * which accompanies this distribution. The full text of the license may be found at 8 | * http://opensource.org/licenses/bsd-license.php 9 | * 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 | * 13 | **/ 14 | 15 | #include 16 | #include 17 | #include 18 | #include 19 | 20 | #include 21 | 22 | ARM_CORE_INFO mHiKey960InfoTable[] = { 23 | { 24 | // Cluster 0, Core 0 25 | 0x0, 0x0, 26 | 27 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value 28 | (UINT64)0xFFFFFFFF 29 | }, 30 | /* 31 | { 32 | // Cluster 0, Core 1 33 | 0x0, 0x1, 34 | 35 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value 36 | (UINT64)0xFFFFFFFF 37 | }, 38 | { 39 | // Cluster 0, Core 2 40 | 0x0, 0x2, 41 | 42 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value 43 | (UINT64)0xFFFFFFFF 44 | }, 45 | { 46 | // Cluster 0, Core 3 47 | 0x0, 0x3, 48 | 49 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value 50 | (UINT64)0xFFFFFFFF 51 | }, 52 | { 53 | // Cluster 1, Core 0 54 | 0x1, 0x0, 55 | 56 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value 57 | (UINT64)0xFFFFFFFF 58 | }, 59 | { 60 | // Cluster 1, Core 1 61 | 0x1, 0x1, 62 | 63 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value 64 | (UINT64)0xFFFFFFFF 65 | }, 66 | { 67 | // Cluster 1, Core 2 68 | 0x1, 0x2, 69 | 70 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value 71 | (UINT64)0xFFFFFFFF 72 | }, 73 | { 74 | // Cluster 1, Core 3 75 | 0x1, 0x3, 76 | 77 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value 78 | (UINT64)0xFFFFFFFF 79 | } 80 | */ 81 | }; 82 | 83 | /** 84 | Return the current Boot Mode 85 | 86 | This function returns the boot reason on the platform 87 | 88 | @return Return the current Boot Mode of the platform 89 | 90 | **/ 91 | EFI_BOOT_MODE 92 | ArmPlatformGetBootMode ( 93 | VOID 94 | ) 95 | { 96 | return BOOT_WITH_FULL_CONFIGURATION; 97 | } 98 | 99 | /** 100 | Initialize controllers that must setup in the normal world 101 | 102 | This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim 103 | in the PEI phase. 104 | 105 | **/ 106 | RETURN_STATUS 107 | ArmPlatformInitialize ( 108 | IN UINTN MpId 109 | ) 110 | { 111 | return RETURN_SUCCESS; 112 | } 113 | 114 | EFI_STATUS 115 | PrePeiCoreGetMpCoreInfo ( 116 | OUT UINTN *CoreCount, 117 | OUT ARM_CORE_INFO **ArmCoreTable 118 | ) 119 | { 120 | // Only support one cluster 121 | *CoreCount = sizeof(mHiKey960InfoTable) / sizeof(ARM_CORE_INFO); 122 | *ArmCoreTable = mHiKey960InfoTable; 123 | return EFI_SUCCESS; 124 | } 125 | 126 | // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore 127 | EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; 128 | ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; 129 | 130 | EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { 131 | { 132 | EFI_PEI_PPI_DESCRIPTOR_PPI, 133 | &mArmMpCoreInfoPpiGuid, 134 | &mMpCoreInfoPpi 135 | } 136 | }; 137 | 138 | VOID 139 | ArmPlatformGetPlatformPpiList ( 140 | OUT UINTN *PpiListSize, 141 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList 142 | ) 143 | { 144 | *PpiListSize = sizeof(gPlatformPpiTable); 145 | *PpiList = gPlatformPpiTable; 146 | } 147 | -------------------------------------------------------------------------------- /Pixel3XL/AcpiTables/Spcr.aslc: -------------------------------------------------------------------------------- 1 | /** @file 2 | * SPCR Table 3 | * 4 | * Copyright (c) 2014 - 2016, ARM Limited. All rights reserved. 5 | * 6 | * This program and the accompanying materials are licensed and made available 7 | * under the terms and conditions of the BSD License which accompanies this 8 | * distribution. The full text of the license may be found at 9 | * http://opensource.org/licenses/bsd-license.php 10 | * 11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 | * 14 | **/ 15 | 16 | #include "ArmPlatform.h" 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | 23 | /** 24 | * References: 25 | * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015 26 | **/ 27 | 28 | 29 | /// 30 | /// SPCR Flow Control 31 | /// 32 | #define SPCR_FLOW_CONTROL_NONE 0 33 | 34 | 35 | STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { 36 | ARM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, 37 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, 38 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), 39 | // UINT8 InterfaceType; 40 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, 41 | // UINT8 Reserved1[3]; 42 | { 43 | EFI_ACPI_RESERVED_BYTE, 44 | EFI_ACPI_RESERVED_BYTE, 45 | EFI_ACPI_RESERVED_BYTE 46 | }, 47 | // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; 48 | ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)), 49 | // UINT8 InterruptType; 50 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, 51 | // UINT8 Irq; 52 | 0, // Not used on ARM 53 | // UINT32 GlobalSystemInterrupt; 54 | FixedPcdGet32 (PL011UartInterrupt), 55 | // UINT8 BaudRate; 56 | #if (FixedPcdGet64 (PcdUartDefaultBaudRate) == 9600) 57 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600, 58 | #elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 19200) 59 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200, 60 | #elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 57600) 61 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600, 62 | #elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 115200) 63 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, 64 | #else 65 | #error Unsupported SPCR Baud Rate 66 | #endif 67 | // UINT8 Parity; 68 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, 69 | // UINT8 StopBits; 70 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, 71 | // UINT8 FlowControl; 72 | SPCR_FLOW_CONTROL_NONE, 73 | // UINT8 TerminalType; 74 | EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, 75 | // UINT8 Reserved2; 76 | EFI_ACPI_RESERVED_BYTE, 77 | // UINT16 PciDeviceId; 78 | 0xFFFF, 79 | // UINT16 PciVendorId; 80 | 0xFFFF, 81 | // UINT8 PciBusNumber; 82 | 0x00, 83 | // UINT8 PciDeviceNumber; 84 | 0x00, 85 | // UINT8 PciFunctionNumber; 86 | 0x00, 87 | // UINT32 PciFlags; 88 | 0x00000000, 89 | // UINT8 PciSegment; 90 | 0x00, 91 | // UINT32 Reserved3; 92 | EFI_ACPI_RESERVED_DWORD 93 | }; 94 | 95 | // 96 | // Reference the table being generated to prevent the optimizer from removing the 97 | // data structure from the executable 98 | // 99 | VOID* CONST ReferenceAcpiTable = &Spcr; 100 | -------------------------------------------------------------------------------- /Pixel3XL/AcpiTables/Dbg2.aslc: -------------------------------------------------------------------------------- 1 | /** @file 2 | * DBG2 Table 3 | * 4 | * Copyright (c) 2012-2016, ARM Limited. All rights reserved. 5 | * 6 | * This program and the accompanying materials 7 | * are licensed and made available under the terms and conditions of the BSD License 8 | * which accompanies this distribution. The full text of the license may be found at 9 | * http://opensource.org/licenses/bsd-license.php 10 | * 11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 | * 14 | **/ 15 | 16 | #include "ArmPlatform.h" 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | 23 | #pragma pack(1) 24 | 25 | #define DBG2_NUM_DEBUG_PORTS 0 26 | #define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1 27 | #define DBG2_NAMESPACESTRING_FIELD_SIZE 8 28 | #define PL011_UART_LENGTH 0x1000 29 | 30 | #define NAME_STR_UART1 {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'} 31 | 32 | typedef struct { 33 | EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; 34 | EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; 35 | UINT32 AddressSize; 36 | UINT8 NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE]; 37 | } DBG2_DEBUG_DEVICE_INFORMATION; 38 | 39 | typedef struct { 40 | EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; 41 | DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS]; 42 | } DBG2_TABLE; 43 | 44 | 45 | #define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \ 46 | { \ 47 | EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision */ \ 48 | sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length */ \ 49 | NumReg, /* UINT8 NumberofGenericAddressRegisters */ \ 50 | DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength */ \ 51 | OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset */ \ 52 | 0, /* UINT16 OemDataLength */ \ 53 | 0, /* UINT16 OemDataOffset */ \ 54 | EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type */ \ 55 | SubType, /* UINT16 Port Subtype */ \ 56 | {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2] */ \ 57 | OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset */ \ 58 | OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset */ \ 59 | }, \ 60 | ARM_GAS32 (UartBase), /* EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \ 61 | UartAddrLen, /* UINT32 AddressSize */ \ 62 | UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \ 63 | } 64 | 65 | 66 | STATIC DBG2_TABLE Dbg2 = { 67 | { 68 | ARM_ACPI_HEADER (EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE, 69 | DBG2_TABLE, 70 | EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION), 71 | OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), 72 | DBG2_NUM_DEBUG_PORTS /* UINT32 NumberDbgDeviceInfo */ 73 | }, 74 | { 75 | #if 0 76 | /* 77 | * Kernel Debug Port 78 | */ 79 | DBG2_DEBUG_PORT_DDI (DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS, 80 | EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART, 81 | FixedPcdGet64 (PcdSerialDbgRegisterBase), 82 | PL011_UART_LENGTH, 83 | NAME_STR_UART1), 84 | #endif 85 | } 86 | }; 87 | 88 | #pragma pack() 89 | 90 | // 91 | // Reference the table being generated to prevent the optimizer from removing 92 | // the data structure from the executable 93 | // 94 | VOID* CONST ReferenceAcpiTable = &Dbg2; 95 | -------------------------------------------------------------------------------- /Pixel3XL/AcpiTables/Gtdt.aslc: -------------------------------------------------------------------------------- 1 | /** @file 2 | * Generic Timer Description Table (GTDT) 3 | * 4 | * Copyright (c) 2012 - 2017, ARM Limited. All rights reserved. 5 | * 6 | * This program and the accompanying materials 7 | * are licensed and made available under the terms and conditions of the BSD License 8 | * which accompanies this distribution. The full text of the license may be found at 9 | * http://opensource.org/licenses/bsd-license.php 10 | * 11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 | * 14 | **/ 15 | 16 | #include "ArmPlatform.h" 17 | #include 18 | #include 19 | #include 20 | 21 | #define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT 22 | #define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 23 | #define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE 24 | #define GTDT_GLOBAL_FLAGS_LEVEL 0 25 | 26 | // Note: We could have a build flag that switches between memory mapped/non-memory mapped timer 27 | #ifdef SYSTEM_TIMER_BASE_ADDRESS 28 | #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) 29 | #else 30 | #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) 31 | #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF 32 | #endif 33 | 34 | #define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE 35 | #define GTDT_TIMER_LEVEL_TRIGGERED 0 36 | #define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY 37 | #define GTDT_TIMER_ACTIVE_HIGH 0 38 | 39 | #define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) 40 | 41 | #define JUNO_WATCHDOG_COUNT FixedPcdGet32 (PcdWatchdogCount) 42 | 43 | 44 | #ifdef ARM_JUNO_ACPI_5_0 45 | EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = { 46 | ARM_ACPI_HEADER( 47 | EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, 48 | EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE, 49 | EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 50 | ), 51 | SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress 52 | GTDT_GLOBAL_FLAGS, // UINT32 GlobalFlags 53 | FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV 54 | GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags 55 | FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV 56 | GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags 57 | FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV 58 | GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags 59 | FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV 60 | GTDT_GTIMER_FLAGS // UINT32 NonSecurePL2TimerFlags 61 | }; 62 | #else 63 | #pragma pack (1) 64 | 65 | typedef struct { 66 | EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; 67 | #if (JUNO_WATCHDOG_COUNT != 0) 68 | EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[JUNO_WATCHDOG_COUNT]; 69 | #endif 70 | } GENERIC_TIMER_DESCRIPTION_TABLE; 71 | 72 | #pragma pack () 73 | 74 | GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = { 75 | { 76 | ARM_ACPI_HEADER( 77 | EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, 78 | GENERIC_TIMER_DESCRIPTION_TABLE, 79 | EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 80 | ), 81 | SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress 82 | 0, // UINT32 Reserved 83 | FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV 84 | GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags 85 | FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV 86 | GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags 87 | FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV 88 | GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags 89 | FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV 90 | GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags 91 | 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress 92 | JUNO_WATCHDOG_COUNT, // UINT32 PlatformTimerCount 93 | #if (JUNO_WATCHDOG_COUNT != 0) 94 | sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset 95 | #else 96 | 0 97 | #endif 98 | }, 99 | #if (JUNO_WATCHDOG_COUNT != 0) 100 | { 101 | EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( 102 | FixedPcdGet64 (PcdGenericWatchdogRefreshBase), 103 | FixedPcdGet64 (PcdGenericWatchdogControlBase), 104 | 93, 105 | 0), 106 | EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( 107 | FixedPcdGet64 (PcdGenericWatchdogRefreshBase), 108 | FixedPcdGet64 (PcdGenericWatchdogControlBase), 109 | 94, 110 | EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) 111 | } 112 | #endif 113 | }; 114 | #endif 115 | 116 | // 117 | // Reference the table being generated to prevent the optimizer from removing the 118 | // data structure from the executable 119 | // 120 | VOID* CONST ReferenceAcpiTable = &Gtdt; 121 | -------------------------------------------------------------------------------- /Pixel3XL/CommonFdf.fdf.inc: -------------------------------------------------------------------------------- 1 | #/** @file 2 | # 3 | # Copyright (c) 2016, Hisilicon Limited. All rights reserved. 4 | # Copyright (c) 2016, Linaro Limited. All rights reserved. 5 | # 6 | # This program and the accompanying materials 7 | # are licensed and made available under the terms and conditions of the BSD License 8 | # which accompanies this distribution. The full text of the license may be found at 9 | # http://opensource.org/licenses/bsd-license.php 10 | # 11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 | # 14 | #**/ 15 | 16 | 17 | ################################################################################ 18 | # 19 | # Rules are use with the [FV] section's module INF type to define 20 | # how an FFS file is created for a given INF file. The following Rule are the default 21 | # rules for the different module type. User can add the customized rules to define the 22 | # content of the FFS file. 23 | # 24 | ################################################################################ 25 | 26 | 27 | ############################################################################ 28 | # Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # 29 | ############################################################################ 30 | # 31 | #[Rule.Common.DXE_DRIVER] 32 | # FILE DRIVER = $(NAMED_GUID) { 33 | # DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex 34 | # COMPRESS PI_STD { 35 | # GUIDED { 36 | # PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi 37 | # UI STRING="$(MODULE_NAME)" Optional 38 | # VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) 39 | # } 40 | # } 41 | # } 42 | # 43 | ############################################################################ 44 | 45 | [Rule.Common.SEC] 46 | FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { 47 | TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi 48 | } 49 | 50 | [Rule.Common.PEI_CORE] 51 | FILE PEI_CORE = $(NAMED_GUID) { 52 | TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi 53 | UI STRING ="$(MODULE_NAME)" Optional 54 | } 55 | 56 | [Rule.Common.PEIM] 57 | FILE PEIM = $(NAMED_GUID) { 58 | PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex 59 | TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi 60 | UI STRING="$(MODULE_NAME)" Optional 61 | } 62 | 63 | [Rule.Common.PEIM.BINARY] 64 | FILE PEIM = $(NAMED_GUID) { 65 | PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex 66 | TE TE Align = Auto |.efi 67 | UI STRING="$(MODULE_NAME)" Optional 68 | } 69 | 70 | [Rule.Common.PEIM.TIANOCOMPRESSED] 71 | FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { 72 | PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex 73 | GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { 74 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi 75 | UI STRING="$(MODULE_NAME)" Optional 76 | } 77 | } 78 | 79 | [Rule.Common.PEIM.FMP_IMAGE_DESC] 80 | FILE PEIM = $(NAMED_GUID) { 81 | RAW BIN |.acpi 82 | PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex 83 | PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi 84 | UI STRING="$(MODULE_NAME)" Optional 85 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) 86 | } 87 | 88 | [Rule.Common.DXE_CORE] 89 | FILE DXE_CORE = $(NAMED_GUID) { 90 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi 91 | UI STRING="$(MODULE_NAME)" Optional 92 | } 93 | 94 | [Rule.Common.UEFI_DRIVER] 95 | FILE DRIVER = $(NAMED_GUID) { 96 | DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex 97 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi 98 | UI STRING="$(MODULE_NAME)" Optional 99 | } 100 | 101 | [Rule.Common.DXE_DRIVER] 102 | FILE DRIVER = $(NAMED_GUID) { 103 | DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex 104 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi 105 | UI STRING="$(MODULE_NAME)" Optional 106 | } 107 | 108 | [Rule.Common.DXE_DRIVER.BINARY] 109 | FILE DRIVER = $(NAMED_GUID) { 110 | DXE_DEPEX DXE_DEPEX Optional |.depex 111 | PE32 PE32 |.efi 112 | UI STRING="$(MODULE_NAME)" Optional 113 | } 114 | 115 | [Rule.Common.DXE_RUNTIME_DRIVER] 116 | FILE DRIVER = $(NAMED_GUID) { 117 | DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex 118 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi 119 | UI STRING="$(MODULE_NAME)" Optional 120 | } 121 | 122 | [Rule.Common.UEFI_APPLICATION] 123 | FILE APPLICATION = $(NAMED_GUID) { 124 | UI STRING ="$(MODULE_NAME)" Optional 125 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi 126 | } 127 | 128 | [Rule.Common.UEFI_DRIVER.BINARY] 129 | FILE DRIVER = $(NAMED_GUID) { 130 | DXE_DEPEX DXE_DEPEX Optional |.depex 131 | PE32 PE32 |.efi 132 | UI STRING="$(MODULE_NAME)" Optional 133 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) 134 | } 135 | 136 | [Rule.Common.UEFI_APPLICATION.BINARY] 137 | FILE APPLICATION = $(NAMED_GUID) { 138 | PE32 PE32 |.efi 139 | UI STRING="$(MODULE_NAME)" Optional 140 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) 141 | } 142 | 143 | [Rule.Common.USER_DEFINED.ACPITABLE] 144 | FILE FREEFORM = $(NAMED_GUID) { 145 | RAW ACPI |.acpi 146 | RAW ASL |.aml 147 | } 148 | 149 | -------------------------------------------------------------------------------- /Pixel3XL/Library/Pixel3XLLib/Pixel3XLMem.c: -------------------------------------------------------------------------------- 1 | /** @file 2 | * 3 | * Copyright (c) 2018, Linaro Limited. All rights reserved. 4 | * 5 | * This program and the accompanying materials 6 | * are licensed and made available under the terms and conditions of the BSD License 7 | * which accompanies this distribution. The full text of the license may be found at 8 | * http://opensource.org/licenses/bsd-license.php 9 | * 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 | * 13 | **/ 14 | 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | 22 | // The total number of descriptors, including the final "end-of-table" descriptor. 23 | #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 24 | 25 | // DDR attributes 26 | #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK 27 | #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED 28 | 29 | #define SDM845_PERIPH_BASE 0x00000000 30 | #define SDM845_PERIPH_SZ 0x80000000 31 | 32 | #define HIKEY960_MEMORY_SIZE 0x0000000100000000 33 | 34 | STATIC struct Pixel3XLReservedMemory { 35 | EFI_PHYSICAL_ADDRESS Offset; 36 | EFI_PHYSICAL_ADDRESS Size; 37 | } Pixel3XLReservedMemoryBuffer [] = { 38 | { 0x85700000, 0x00600000 }, // hyp_region 39 | { 0x85e00000, 0x00100000 }, // xbl_region 40 | { 0x85fc0000, 0x02f40000 }, // removed_region 41 | { 0x8ab00000, 0x01400000 }, // qseecom_region 42 | }; 43 | 44 | /** 45 | Return the Virtual Memory Map of your platform 46 | 47 | This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. 48 | 49 | @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- 50 | Virtual Memory mapping. This array must be ended by a zero-filled 51 | entry 52 | 53 | **/ 54 | VOID 55 | ArmPlatformGetVirtualMemoryMap ( 56 | IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap 57 | ) 58 | { 59 | ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; 60 | ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; 61 | EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; 62 | UINTN Index = 0, Count, ReservedTop; 63 | EFI_PEI_HOB_POINTERS NextHob; 64 | UINT64 ResourceLength; 65 | EFI_PHYSICAL_ADDRESS ResourceTop; 66 | 67 | ResourceAttributes = ( 68 | EFI_RESOURCE_ATTRIBUTE_PRESENT | 69 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | 70 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | 71 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | 72 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | 73 | EFI_RESOURCE_ATTRIBUTE_TESTED 74 | ); 75 | 76 | // Create initial Base Hob for system memory. 77 | BuildResourceDescriptorHob ( 78 | EFI_RESOURCE_SYSTEM_MEMORY, 79 | ResourceAttributes, 80 | PcdGet64 (PcdSystemMemoryBase), 81 | PcdGet64 (PcdSystemMemorySize) 82 | ); 83 | 84 | NextHob.Raw = GetHobList (); 85 | Count = sizeof (Pixel3XLReservedMemoryBuffer) / sizeof (struct Pixel3XLReservedMemory); 86 | while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) 87 | { 88 | if (Index >= Count) 89 | break; 90 | if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) && 91 | (Pixel3XLReservedMemoryBuffer[Index].Offset >= NextHob.ResourceDescriptor->PhysicalStart) && 92 | ((Pixel3XLReservedMemoryBuffer[Index].Offset + Pixel3XLReservedMemoryBuffer[Index].Size) <= 93 | NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength)) 94 | { 95 | ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute; 96 | ResourceLength = NextHob.ResourceDescriptor->ResourceLength; 97 | ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength; 98 | ReservedTop = Pixel3XLReservedMemoryBuffer[Index].Offset + Pixel3XLReservedMemoryBuffer[Index].Size; 99 | 100 | // Create the System Memory HOB for the reserved buffer 101 | BuildResourceDescriptorHob ( 102 | EFI_RESOURCE_MEMORY_RESERVED, 103 | EFI_RESOURCE_ATTRIBUTE_PRESENT, 104 | Pixel3XLReservedMemoryBuffer[Index].Offset, 105 | Pixel3XLReservedMemoryBuffer[Index].Size 106 | ); 107 | // Update the HOB 108 | NextHob.ResourceDescriptor->ResourceLength = Pixel3XLReservedMemoryBuffer[Index].Offset - 109 | NextHob.ResourceDescriptor->PhysicalStart; 110 | 111 | // If there is some memory available on the top of the reserved memory then create a HOB 112 | if (ReservedTop < ResourceTop) 113 | { 114 | BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, 115 | ResourceAttributes, 116 | ReservedTop, 117 | ResourceTop - ReservedTop); 118 | } 119 | Index++; 120 | } 121 | NextHob.Raw = GET_NEXT_HOB (NextHob); 122 | } 123 | 124 | ASSERT (VirtualMemoryMap != NULL); 125 | 126 | VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages ( 127 | EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS) 128 | ); 129 | if (VirtualMemoryTable == NULL) { 130 | return; 131 | } 132 | 133 | CacheAttributes = DDR_ATTRIBUTES_CACHED; 134 | 135 | Index = 0; 136 | 137 | // DDR - 4.0GB section 138 | VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); 139 | VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); 140 | VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); 141 | VirtualMemoryTable[Index].Attributes = CacheAttributes; 142 | 143 | // SDM845 SOC peripherals 144 | VirtualMemoryTable[++Index].PhysicalBase = SDM845_PERIPH_BASE; 145 | VirtualMemoryTable[Index].VirtualBase = SDM845_PERIPH_BASE; 146 | VirtualMemoryTable[Index].Length = SDM845_PERIPH_SZ; 147 | VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 148 | 149 | // End of Table 150 | VirtualMemoryTable[++Index].PhysicalBase = 0; 151 | VirtualMemoryTable[Index].VirtualBase = 0; 152 | VirtualMemoryTable[Index].Length = 0; 153 | VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; 154 | 155 | ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); 156 | 157 | *VirtualMemoryMap = VirtualMemoryTable; 158 | } 159 | -------------------------------------------------------------------------------- /Pixel3XL/AcpiTables/Fadt.aslc: -------------------------------------------------------------------------------- 1 | /** @file 2 | * Fixed ACPI Description Table (FADT) 3 | * 4 | * Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. 5 | * 6 | * This program and the accompanying materials 7 | * are licensed and made available under the terms and conditions of the BSD License 8 | * which accompanies this distribution. The full text of the license may be found at 9 | * http://opensource.org/licenses/bsd-license.php 10 | * 11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 | * 14 | **/ 15 | 16 | #include "ArmPlatform.h" 17 | #include 18 | #include 19 | 20 | #ifdef ARM_JUNO_ACPI_5_0 21 | EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { 22 | ARM_ACPI_HEADER ( 23 | EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, 24 | EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE, 25 | EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 26 | ), 27 | #else 28 | EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { 29 | ARM_ACPI_HEADER ( 30 | EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, 31 | EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, 32 | EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 33 | ), 34 | #endif 35 | 0, // UINT32 FirmwareCtrl 36 | 0, // UINT32 Dsdt 37 | EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 38 | EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile 39 | 0, // UINT16 SciInt 40 | 0, // UINT32 SmiCmd 41 | 0, // UINT8 AcpiEnable 42 | 0, // UINT8 AcpiDisable 43 | 0, // UINT8 S4BiosReq 44 | 0, // UINT8 PstateCnt 45 | 0, // UINT32 Pm1aEvtBlk 46 | 0, // UINT32 Pm1bEvtBlk 47 | 0, // UINT32 Pm1aCntBlk 48 | 0, // UINT32 Pm1bCntBlk 49 | 0, // UINT32 Pm2CntBlk 50 | 0, // UINT32 PmTmrBlk 51 | 0, // UINT32 Gpe0Blk 52 | 0, // UINT32 Gpe1Blk 53 | 0, // UINT8 Pm1EvtLen 54 | 0, // UINT8 Pm1CntLen 55 | 0, // UINT8 Pm2CntLen 56 | 0, // UINT8 PmTmrLen 57 | 0, // UINT8 Gpe0BlkLen 58 | 0, // UINT8 Gpe1BlkLen 59 | 0, // UINT8 Gpe1Base 60 | 0, // UINT8 CstCnt 61 | 0, // UINT16 PLvl2Lat 62 | 0, // UINT16 PLvl3Lat 63 | 0, // UINT16 FlushSize 64 | 0, // UINT16 FlushStride 65 | 0, // UINT8 DutyOffset 66 | 0, // UINT8 DutyWidth 67 | 0, // UINT8 DayAlrm 68 | 0, // UINT8 MonAlrm 69 | 0, // UINT8 Century 70 | 0, // UINT16 IaPcBootArch 71 | 0, // UINT8 Reserved1 72 | EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags 73 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg 74 | 0, // UINT8 ResetValue 75 | #ifdef ARM_JUNO_ACPI_5_0 76 | {EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved2[3] 77 | #else 78 | EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags 79 | EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision 80 | #endif 81 | 0, // UINT64 XFirmwareCtrl 82 | 0, // UINT64 XDsdt 83 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk 84 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk 85 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk 86 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk 87 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk 88 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk 89 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk 90 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk 91 | NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg 92 | NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg 93 | }; 94 | 95 | // 96 | // Reference the table being generated to prevent the optimizer from removing the 97 | // data structure from the executable 98 | // 99 | VOID* CONST ReferenceAcpiTable = &Fadt; 100 | -------------------------------------------------------------------------------- /Pixel3XL/AcpiTables/Madt.aslc: -------------------------------------------------------------------------------- 1 | /** @file 2 | * Multiple APIC Description Table (MADT) 3 | * 4 | * Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. 5 | * 6 | * This program and the accompanying materials 7 | * are licensed and made available under the terms and conditions of the BSD License 8 | * which accompanies this distribution. The full text of the license may be found at 9 | * http://opensource.org/licenses/bsd-license.php 10 | * 11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 | * 14 | **/ 15 | 16 | #include "ArmPlatform.h" 17 | #include 18 | #include 19 | #include 20 | #include 21 | 22 | // 23 | // Multiple APIC Description Table 24 | // 25 | #ifdef ARM_JUNO_ACPI_5_0 26 | #pragma pack (1) 27 | 28 | typedef struct { 29 | EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; 30 | EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)]; 31 | EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; 32 | } EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE; 33 | 34 | #pragma pack () 35 | 36 | EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 37 | { 38 | ARM_ACPI_HEADER ( 39 | EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, 40 | EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE, 41 | EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 42 | ), 43 | // 44 | // MADT specific fields 45 | // 46 | 0, // LocalApicAddress 47 | 0, // Flags 48 | }, 49 | { 50 | // Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase) 51 | // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of 52 | // ACPI v5.0). 53 | // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the 54 | // Trusted Firmware. When supported, we will need to code to dynamically change the ordering. 55 | // For now we leave CPU2 (A53-0) at the first position. 56 | // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses 57 | // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. 58 | EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-0 59 | EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-1 60 | EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-2 61 | EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-3 62 | EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A57-0 63 | EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase)) // A57-1 64 | }, 65 | EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0) 66 | }; 67 | #else 68 | #pragma pack (1) 69 | 70 | typedef struct { 71 | EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; 72 | EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)]; 73 | EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; 74 | #if 0 75 | EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE MsiFrame; 76 | #endif 77 | EFI_ACPI_6_1_GICR_STRUCTURE Gicr; 78 | } MULTIPLE_APIC_DESCRIPTION_TABLE; 79 | 80 | #pragma pack () 81 | 82 | MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 83 | { 84 | ARM_ACPI_HEADER ( 85 | EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, 86 | MULTIPLE_APIC_DESCRIPTION_TABLE, 87 | EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 88 | ), 89 | // 90 | // MADT specific fields 91 | // 92 | 0, // LocalApicAddress 93 | 0, // Flags 94 | }, 95 | { 96 | // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, MpIdr, Flags, PmuIrq, GicBase, GicVBase, GicHBase, 97 | // GsivId, GicRBase) 98 | // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of 99 | // ACPI v5.1). 100 | // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the 101 | // Trusted Firmware. When supported, we will need to code to dynamically change the ordering. 102 | // For now we leave CPU2 (A53-0) at the first position. 103 | // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses 104 | // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. 105 | EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0 106 | 0, 0, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 107 | 0 /* GicVBase */, 0 /*GicHBase */, 25, 0 /* GicRBase */), 108 | #if 0 109 | EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1 110 | 3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 111 | 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), 112 | EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2 113 | 4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 114 | 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), 115 | EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3 116 | 5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 117 | 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), 118 | EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0 119 | 0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 120 | 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), 121 | EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1 122 | 1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 123 | 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), 124 | #endif 125 | }, 126 | // Format: EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) 127 | EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3), 128 | // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase) 129 | #if 0 130 | EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE) 131 | #endif 132 | /* GIC Redistributor */ 133 | { 134 | EFI_ACPI_6_1_GICR, // UINT8 Type 135 | sizeof(EFI_ACPI_6_1_GICR_STRUCTURE), // UINT8 Length 136 | EFI_ACPI_RESERVED_WORD, // UINT16 Reserved 137 | FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress 138 | 0x00100000, // UINT32 DiscoveryRangeLength 139 | } 140 | }; 141 | #endif 142 | 143 | // 144 | // Reference the table being generated to prevent the optimizer from removing the 145 | // data structure from the executable 146 | // 147 | VOID* CONST ReferenceAcpiTable = &Madt; 148 | -------------------------------------------------------------------------------- /Pixel3XL/AcpiTables/AcpiSsdtRootPci.asl: -------------------------------------------------------------------------------- 1 | /** @file 2 | Differentiated System Description Table Fields (SSDT) 3 | 4 | Copyright (c) 2014-2015, ARM Ltd. All rights reserved.
5 | This program and the accompanying materials 6 | are licensed and made available under the terms and conditions of the BSD License 7 | which accompanies this distribution. The full text of the license may be found at 8 | http://opensource.org/licenses/bsd-license.php 9 | 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 | 13 | **/ 14 | 15 | #include "ArmPlatform.h" 16 | 17 | /* 18 | See ACPI 6.1 Section 6.2.13 19 | 20 | There are two ways that _PRT can be used. ... 21 | 22 | In the first model, a PCI Link device is used to provide additional 23 | configuration information such as whether the interrupt is Level or 24 | Edge triggered, it is active High or Low, Shared or Exclusive, etc. 25 | 26 | In the second model, the PCI interrupts are hardwired to specific 27 | interrupt inputs on the interrupt controller and are not 28 | configurable. In this case, the Source field in _PRT does not 29 | reference a device, but instead contains the value zero, and the 30 | Source Index field contains the global system interrupt to which the 31 | PCI interrupt is hardwired. 32 | 33 | We use the first model with link indirection to set the correct 34 | interrupt type as PCI defaults (Level Triggered, Active Low) are not 35 | compatible with GICv2. 36 | */ 37 | #define LNK_DEVICE(Unique_Id, Link_Name, irq) \ 38 | Device(Link_Name) { \ 39 | Name(_HID, EISAID("PNP0C0F")) \ 40 | Name(_UID, Unique_Id) \ 41 | Name(_PRS, ResourceTemplate() { \ 42 | Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ 43 | }) \ 44 | Method (_CRS, 0) { Return (_PRS) } \ 45 | Method (_SRS, 1) { } \ 46 | Method (_DIS) { } \ 47 | } 48 | 49 | #define PRT_ENTRY(Address, Pin, Link) \ 50 | Package (4) { \ 51 | Address, /* uses the same format as _ADR */ \ 52 | Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \ 53 | Link, /* Interrupt allocated via Link device. */ \ 54 | Zero /* global system interrupt number (no used) */ \ 55 | } 56 | 57 | /* 58 | See Reference [1] 6.1.1 59 | "High word–Device #, Low word–Function #. (for example, device 3, function 2 is 60 | 0x00030002). To refer to all the functions on a device #, use a function number of FFFF)." 61 | */ 62 | #define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) 63 | // Device 0 for Bridge. 64 | 65 | 66 | DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) { 67 | Scope(_SB) { 68 | // 69 | // PCI Root Complex 70 | // 71 | LNK_DEVICE(1, LNKA, 168) 72 | LNK_DEVICE(2, LNKB, 169) 73 | LNK_DEVICE(3, LNKC, 170) 74 | LNK_DEVICE(4, LNKD, 171) 75 | 76 | Device(PCI0) 77 | { 78 | Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge 79 | Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge 80 | Name(_SEG, Zero) // PCI Segment Group number 81 | Name(_BBN, Zero) // PCI Base Bus Number 82 | Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1) 83 | 84 | // Root Complex 0 85 | Device (RP0) { 86 | Name(_ADR, 0xF0000000) // Dev 0, Func 0 87 | } 88 | 89 | // PCI Routing Table 90 | Name(_PRT, Package() { 91 | ROOT_PRT_ENTRY(0, LNKA), // INTA 92 | ROOT_PRT_ENTRY(1, LNKB), // INTB 93 | ROOT_PRT_ENTRY(2, LNKC), // INTC 94 | ROOT_PRT_ENTRY(3, LNKD), // INTD 95 | }) 96 | // Root complex resources 97 | Method (_CRS, 0, Serialized) { 98 | Name (RBUF, ResourceTemplate () { 99 | WordBusNumber ( // Bus numbers assigned to this root 100 | ResourceProducer, 101 | MinFixed, MaxFixed, PosDecode, 102 | 0, // AddressGranularity 103 | 0, // AddressMinimum - Minimum Bus Number 104 | 255, // AddressMaximum - Maximum Bus Number 105 | 0, // AddressTranslation - Set to 0 106 | 256 // RangeLength - Number of Busses 107 | ) 108 | 109 | DWordMemory ( // 32-bit BAR Windows 110 | ResourceProducer, PosDecode, 111 | MinFixed, MaxFixed, 112 | Cacheable, ReadWrite, 113 | 0x00000000, // Granularity 114 | 0x50000000, // Min Base Address 115 | 0x57FFFFFF, // Max Base Address 116 | 0x00000000, // Translate 117 | 0x08000000 // Length 118 | ) 119 | 120 | QWordMemory ( // 64-bit BAR Windows 121 | ResourceProducer, PosDecode, 122 | MinFixed, MaxFixed, 123 | Cacheable, ReadWrite, 124 | 0x00000000, // Granularity 125 | 0x4000000000, // Min Base Address 126 | 0x40FFFFFFFF, // Max Base Address 127 | 0x00000000, // Translate 128 | 0x100000000 // Length 129 | ) 130 | 131 | DWordIo ( // IO window 132 | ResourceProducer, 133 | MinFixed, 134 | MaxFixed, 135 | PosDecode, 136 | EntireRange, 137 | 0x00000000, // Granularity 138 | 0x00000000, // Min Base Address 139 | 0x007fffff, // Max Base Address 140 | 0x5f800000, // Translate 141 | 0x00800000, // Length 142 | ,,,TypeTranslation 143 | ) 144 | }) // Name(RBUF) 145 | 146 | Return (RBUF) 147 | } // Method(_CRS) 148 | 149 | // 150 | // OS Control Handoff 151 | // 152 | Name(SUPP, Zero) // PCI _OSC Support Field value 153 | Name(CTRL, Zero) // PCI _OSC Control Field value 154 | 155 | /* 156 | See [1] 6.2.10, [2] 4.5 157 | */ 158 | Method(_OSC,4) { 159 | // Check for proper UUID 160 | If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { 161 | // Create DWord-adressable fields from the Capabilities Buffer 162 | CreateDWordField(Arg3,0,CDW1) 163 | CreateDWordField(Arg3,4,CDW2) 164 | CreateDWordField(Arg3,8,CDW3) 165 | 166 | // Save Capabilities DWord2 & 3 167 | Store(CDW2,SUPP) 168 | Store(CDW3,CTRL) 169 | 170 | // Only allow native hot plug control if OS supports: 171 | // * ASPM 172 | // * Clock PM 173 | // * MSI/MSI-X 174 | If(LNotEqual(And(SUPP, 0x16), 0x16)) { 175 | And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) 176 | } 177 | 178 | // Always allow native PME, AER (no dependencies) 179 | 180 | // Never allow SHPC (no SHPC controller in this system) 181 | And(CTRL,0x1D,CTRL) 182 | 183 | #if 0 184 | If(LNot(And(CDW1,1))) { // Query flag clear? 185 | // Disable GPEs for features granted native control. 186 | If(And(CTRL,0x01)) { // Hot plug control granted? 187 | Store(0,HPCE) // clear the hot plug SCI enable bit 188 | Store(1,HPCS) // clear the hot plug SCI status bit 189 | } 190 | If(And(CTRL,0x04)) { // PME control granted? 191 | Store(0,PMCE) // clear the PME SCI enable bit 192 | Store(1,PMCS) // clear the PME SCI status bit 193 | } 194 | If(And(CTRL,0x10)) { // OS restoring PCIe cap structure? 195 | // Set status to not restore PCIe cap structure 196 | // upon resume from S3 197 | Store(1,S3CR) 198 | } 199 | } 200 | #endif 201 | 202 | If(LNotEqual(Arg1,One)) { // Unknown revision 203 | Or(CDW1,0x08,CDW1) 204 | } 205 | 206 | If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked 207 | Or(CDW1,0x10,CDW1) 208 | } 209 | // Update DWORD3 in the buffer 210 | Store(CTRL,CDW3) 211 | Return(Arg3) 212 | } Else { 213 | Or(CDW1,4,CDW1) // Unrecognized UUID 214 | Return(Arg3) 215 | } 216 | } // End _OSC 217 | } // PCI0 218 | } 219 | } 220 | -------------------------------------------------------------------------------- /Pixel3XL/Library/InMemorySerialPortLib/InMemorySerialPortLib.c: -------------------------------------------------------------------------------- 1 | /** @file 2 | Null Serial Port library instance with empty functions. 3 | 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
5 | This program and the accompanying materials 6 | are licensed and made available under the terms and conditions of the BSD License 7 | which accompanies this distribution. The full text of the license may be found at 8 | http://opensource.org/licenses/bsd-license.php. 9 | 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 | 13 | **/ 14 | 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | /** 21 | Initialize the serial device hardware. 22 | 23 | If no initialization is required, then return RETURN_SUCCESS. 24 | If the serial device was successfully initialized, then return RETURN_SUCCESS. 25 | If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. 26 | 27 | @retval RETURN_SUCCESS The serial device was initialized. 28 | @retval RETURN_DEVICE_ERROR The serial device could not be initialized. 29 | 30 | **/ 31 | RETURN_STATUS 32 | EFIAPI 33 | SerialPortInitialize ( 34 | VOID 35 | ) 36 | { 37 | #if 0 38 | UINT8* base = (UINT8*)0xa1a10000ull; 39 | for (UINTN i = 0; i < 0x200000; i++) { 40 | base[i] = 0; 41 | } 42 | #endif 43 | return RETURN_SUCCESS; 44 | } 45 | 46 | static void mem_putchar(UINT8 c) { 47 | static const UINTN size = 0x200000; 48 | static UINTN offset = 0; 49 | UINT8* base = (UINT8*)0xa1a10000ull; 50 | base[offset++] = c; 51 | if (offset >= size) { 52 | offset = 0; 53 | } 54 | WriteBackInvalidateDataCacheRange(base, size); 55 | } 56 | 57 | /** 58 | Write data from buffer to serial device. 59 | 60 | Writes NumberOfBytes data bytes from Buffer to the serial device. 61 | The number of bytes actually written to the serial device is returned. 62 | If the return value is less than NumberOfBytes, then the write operation failed. 63 | If Buffer is NULL, then ASSERT(). 64 | If NumberOfBytes is zero, then return 0. 65 | 66 | @param Buffer The pointer to the data buffer to be written. 67 | @param NumberOfBytes The number of bytes to written to the serial device. 68 | 69 | @retval 0 NumberOfBytes is 0. 70 | @retval >0 The number of bytes written to the serial device. 71 | If this value is less than NumberOfBytes, then the write operation failed. 72 | 73 | **/ 74 | UINTN 75 | EFIAPI 76 | SerialPortWrite ( 77 | IN UINT8 *Buffer, 78 | IN UINTN NumberOfBytes 79 | ) 80 | { 81 | for (UINTN i = 0; i < NumberOfBytes; i++) { 82 | mem_putchar(Buffer[i]); 83 | } 84 | return NumberOfBytes; 85 | } 86 | 87 | 88 | /** 89 | Read data from serial device and save the datas in buffer. 90 | 91 | Reads NumberOfBytes data bytes from a serial device into the buffer 92 | specified by Buffer. The number of bytes actually read is returned. 93 | If the return value is less than NumberOfBytes, then the rest operation failed. 94 | If Buffer is NULL, then ASSERT(). 95 | If NumberOfBytes is zero, then return 0. 96 | 97 | @param Buffer The pointer to the data buffer to store the data read from the serial device. 98 | @param NumberOfBytes The number of bytes which will be read. 99 | 100 | @retval 0 Read data failed; No data is to be read. 101 | @retval >0 The actual number of bytes read from serial device. 102 | 103 | **/ 104 | UINTN 105 | EFIAPI 106 | SerialPortRead ( 107 | OUT UINT8 *Buffer, 108 | IN UINTN NumberOfBytes 109 | ) 110 | { 111 | return 0; 112 | } 113 | 114 | /** 115 | Polls a serial device to see if there is any data waiting to be read. 116 | 117 | Polls a serial device to see if there is any data waiting to be read. 118 | If there is data waiting to be read from the serial device, then TRUE is returned. 119 | If there is no data waiting to be read from the serial device, then FALSE is returned. 120 | 121 | @retval TRUE Data is waiting to be read from the serial device. 122 | @retval FALSE There is no data waiting to be read from the serial device. 123 | 124 | **/ 125 | BOOLEAN 126 | EFIAPI 127 | SerialPortPoll ( 128 | VOID 129 | ) 130 | { 131 | return FALSE; 132 | } 133 | 134 | /** 135 | Sets the control bits on a serial device. 136 | 137 | @param Control Sets the bits of Control that are settable. 138 | 139 | @retval RETURN_SUCCESS The new control bits were set on the serial device. 140 | @retval RETURN_UNSUPPORTED The serial device does not support this operation. 141 | @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. 142 | 143 | **/ 144 | RETURN_STATUS 145 | EFIAPI 146 | SerialPortSetControl ( 147 | IN UINT32 Control 148 | ) 149 | { 150 | return RETURN_UNSUPPORTED; 151 | } 152 | 153 | /** 154 | Retrieve the status of the control bits on a serial device. 155 | 156 | @param Control A pointer to return the current control signals from the serial device. 157 | 158 | @retval RETURN_SUCCESS The control bits were read from the serial device. 159 | @retval RETURN_UNSUPPORTED The serial device does not support this operation. 160 | @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. 161 | 162 | **/ 163 | RETURN_STATUS 164 | EFIAPI 165 | SerialPortGetControl ( 166 | OUT UINT32 *Control 167 | ) 168 | { 169 | return RETURN_UNSUPPORTED; 170 | } 171 | 172 | /** 173 | Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, 174 | data bits, and stop bits on a serial device. 175 | 176 | @param BaudRate The requested baud rate. A BaudRate value of 0 will use the 177 | device's default interface speed. 178 | On output, the value actually set. 179 | @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the 180 | serial interface. A ReceiveFifoDepth value of 0 will use 181 | the device's default FIFO depth. 182 | On output, the value actually set. 183 | @param Timeout The requested time out for a single character in microseconds. 184 | This timeout applies to both the transmit and receive side of the 185 | interface. A Timeout value of 0 will use the device's default time 186 | out value. 187 | On output, the value actually set. 188 | @param Parity The type of parity to use on this serial device. A Parity value of 189 | DefaultParity will use the device's default parity value. 190 | On output, the value actually set. 191 | @param DataBits The number of data bits to use on the serial device. A DataBits 192 | vaule of 0 will use the device's default data bit setting. 193 | On output, the value actually set. 194 | @param StopBits The number of stop bits to use on this serial device. A StopBits 195 | value of DefaultStopBits will use the device's default number of 196 | stop bits. 197 | On output, the value actually set. 198 | 199 | @retval RETURN_SUCCESS The new attributes were set on the serial device. 200 | @retval RETURN_UNSUPPORTED The serial device does not support this operation. 201 | @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value. 202 | @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. 203 | 204 | **/ 205 | RETURN_STATUS 206 | EFIAPI 207 | SerialPortSetAttributes ( 208 | IN OUT UINT64 *BaudRate, 209 | IN OUT UINT32 *ReceiveFifoDepth, 210 | IN OUT UINT32 *Timeout, 211 | IN OUT EFI_PARITY_TYPE *Parity, 212 | IN OUT UINT8 *DataBits, 213 | IN OUT EFI_STOP_BITS_TYPE *StopBits 214 | ) 215 | { 216 | return RETURN_UNSUPPORTED; 217 | } 218 | 219 | -------------------------------------------------------------------------------- /Pixel3XL/Pixel3XL.fdf: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2018, Linaro Limited. All rights reserved. 3 | # 4 | # This program and the accompanying materials 5 | # are licensed and made available under the terms and conditions of the BSD License 6 | # which accompanies this distribution. The full text of the license may be found at 7 | # http://opensource.org/licenses/bsd-license.php 8 | # 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 | # 12 | 13 | ################################################################################ 14 | # 15 | # FD Section 16 | # The [FD] Section is made up of the definition statements and a 17 | # description of what goes into the Flash Device Image. Each FD section 18 | # defines one flash "device" image. A flash device image may be one of 19 | # the following: Removable media bootable image (like a boot floppy 20 | # image,) an Option ROM image (that would be "flashed" into an add-in 21 | # card,) a System "Flash" image (that would be burned into a system's 22 | # flash) or an Update ("Capsule") image that will be used to update and 23 | # existing system flash. 24 | # 25 | ################################################################################ 26 | 27 | [FD.PIXEL3XL_UEFI] 28 | BaseAddress = 0xd0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. 29 | Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device 30 | ErasePolarity = 1 31 | 32 | # This one is tricky, it must be: BlockSize * NumBlocks = Size 33 | BlockSize = 0x00001000 34 | NumBlocks = 0x200 35 | 36 | ################################################################################ 37 | # 38 | # Following are lists of FD Region layout which correspond to the locations of different 39 | # images within the flash device. 40 | # 41 | # Regions must be defined in ascending order and may not overlap. 42 | # 43 | # A Layout Region start with a eight digit hex offset (leading "0x" required) followed by 44 | # the pipe "|" character, followed by the size of the region, also in hex with the leading 45 | # "0x" characters. Like: 46 | # Offset|Size 47 | # PcdOffsetCName|PcdSizeCName 48 | # RegionType 49 | # 50 | ################################################################################ 51 | 52 | # from ArmVirtPkg/ArmVirtQemuKernel.fdf 53 | # 54 | # Implement the Linux kernel header layout so that the loader will identify 55 | # it as something bootable, and execute it with a FDT pointer in x0 or r2. 56 | # 57 | 0x00000000|0x00008000 58 | DATA = { 59 | 0x01, 0x00, 0x00, 0x10, # code0: adr x1, . 60 | 0xff, 0x1f, 0x00, 0x14, # code1: b 0x8000 61 | 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, # text_offset: 512 KB 62 | 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, # image_size: 2 MB 63 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # flags 64 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res2 65 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res3 66 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res4 67 | 0x41, 0x52, 0x4d, 0x64, # magic: "ARM\x64" 68 | 0x00, 0x00, 0x00, 0x00 # res5 69 | } 70 | 71 | 0x00008000|0x001f8000 72 | gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize 73 | FV = FVMAIN_COMPACT 74 | 75 | 76 | ################################################################################ 77 | # 78 | # FV Section 79 | # 80 | # [FV] section is used to define what components or modules are placed within a flash 81 | # device file. This section also defines order the components and modules are positioned 82 | # within the image. The [FV] section consists of define statements, set statements and 83 | # module statements. 84 | # 85 | ################################################################################ 86 | 87 | [FV.FvMain] 88 | BlockSize = 0x40 89 | NumBlocks = 0 # This FV gets compressed so make it just big enough 90 | FvAlignment = 8 # FV alignment and FV attributes setting. 91 | ERASE_POLARITY = 1 92 | MEMORY_MAPPED = TRUE 93 | STICKY_WRITE = TRUE 94 | LOCK_CAP = TRUE 95 | LOCK_STATUS = TRUE 96 | WRITE_DISABLED_CAP = TRUE 97 | WRITE_ENABLED_CAP = TRUE 98 | WRITE_STATUS = TRUE 99 | WRITE_LOCK_CAP = TRUE 100 | WRITE_LOCK_STATUS = TRUE 101 | READ_DISABLED_CAP = TRUE 102 | READ_ENABLED_CAP = TRUE 103 | READ_STATUS = TRUE 104 | READ_LOCK_CAP = TRUE 105 | READ_LOCK_STATUS = TRUE 106 | 107 | APRIORI DXE { 108 | INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf 109 | } 110 | 111 | INF MdeModulePkg/Core/Dxe/DxeMain.inf 112 | 113 | # 114 | # PI DXE Drivers producing Architectural Protocols (EFI Services) 115 | # 116 | INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf 117 | INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf 118 | INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf 119 | INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf 120 | INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf 121 | INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf 122 | INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf 123 | INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf 124 | 125 | # 126 | # Multiple Console IO support 127 | # 128 | INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf 129 | INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf 130 | INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf 131 | INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf 132 | INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf 133 | 134 | INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf 135 | INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf 136 | 137 | INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf 138 | 139 | INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf 140 | 141 | # 142 | # GPIO 143 | # 144 | 145 | # 146 | # Virtual Keyboard 147 | # 148 | INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf 149 | 150 | INF Pixel3XL/Pixel3XLDxe/Pixel3XLDxe.inf 151 | INF Pixel3XL/SimpleFbDxe/SimpleFbDxe.inf 152 | 153 | 154 | # 155 | # USB Host Support 156 | # 157 | INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf 158 | 159 | # 160 | # USB Mass Storage Support 161 | # 162 | INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf 163 | 164 | # 165 | # USB Peripheral Support 166 | # 167 | INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf 168 | 169 | # 170 | # Fastboot 171 | # 172 | INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf 173 | 174 | # 175 | # FAT filesystem + GPT/MBR partitioning 176 | # 177 | INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf 178 | INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf 179 | INF FatPkg/EnhancedFatDxe/Fat.inf 180 | INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf 181 | 182 | INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf 183 | 184 | INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf 185 | 186 | # 187 | # ACPI Support 188 | # 189 | INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf 190 | INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf 191 | INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf 192 | INF RuleOverride = ACPITABLE Pixel3XL/AcpiTables/AcpiTables.inf 193 | 194 | # 195 | # SMBIOS Support 196 | # 197 | INF Pixel3XL/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf 198 | INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf 199 | 200 | # 201 | # UEFI applications 202 | # 203 | INF ShellPkg/Application/Shell/Shell.inf 204 | !ifdef $(INCLUDE_TFTP_COMMAND) 205 | INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf 206 | !endif #$(INCLUDE_TFTP_COMMAND) 207 | 208 | # 209 | # Bds 210 | # 211 | INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf 212 | INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf 213 | INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf 214 | INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf 215 | INF MdeModulePkg/Application/UiApp/UiApp.inf 216 | 217 | [FV.FVMAIN_COMPACT] 218 | FvAlignment = 8 219 | ERASE_POLARITY = 1 220 | MEMORY_MAPPED = TRUE 221 | STICKY_WRITE = TRUE 222 | LOCK_CAP = TRUE 223 | LOCK_STATUS = TRUE 224 | WRITE_DISABLED_CAP = TRUE 225 | WRITE_ENABLED_CAP = TRUE 226 | WRITE_STATUS = TRUE 227 | WRITE_LOCK_CAP = TRUE 228 | WRITE_LOCK_STATUS = TRUE 229 | READ_DISABLED_CAP = TRUE 230 | READ_ENABLED_CAP = TRUE 231 | READ_STATUS = TRUE 232 | READ_LOCK_CAP = TRUE 233 | READ_LOCK_STATUS = TRUE 234 | 235 | INF ArmPlatformPkg/PrePi/PeiUniCore.inf 236 | 237 | FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { 238 | SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { 239 | SECTION FV_IMAGE = FVMAIN 240 | } 241 | } 242 | 243 | !include Pixel3XL/CommonFdf.fdf.inc 244 | -------------------------------------------------------------------------------- /Pixel3XL/SimpleFbDxe/SimpleFbDxe.c: -------------------------------------------------------------------------------- 1 | /* SimpleFbDxe: Simple FrameBuffer */ 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | 16 | /// Defines 17 | /* 18 | * Convert enum video_log2_bpp to bytes and bits. Note we omit the outer 19 | * brackets to allow multiplication by fractional pixels. 20 | */ 21 | #define VNBYTES(bpix) (1 << (bpix)) / 8 22 | #define VNBITS(bpix) (1 << (bpix)) 23 | 24 | #define FB_BITS_PER_PIXEL (32) 25 | #define FB_BYTES_PER_PIXEL (FB_BITS_PER_PIXEL / 8) 26 | 27 | /* 28 | * Bits per pixel selector. Each value n is such that the bits-per-pixel is 29 | * 2 ^ n 30 | */ 31 | enum video_log2_bpp { 32 | VIDEO_BPP1 = 0, 33 | VIDEO_BPP2, 34 | VIDEO_BPP4, 35 | VIDEO_BPP8, 36 | VIDEO_BPP16, 37 | VIDEO_BPP32, 38 | }; 39 | 40 | typedef struct { 41 | VENDOR_DEVICE_PATH DisplayDevicePath; 42 | EFI_DEVICE_PATH EndDevicePath; 43 | } DISPLAY_DEVICE_PATH; 44 | 45 | DISPLAY_DEVICE_PATH mDisplayDevicePath = 46 | { 47 | { 48 | { 49 | HARDWARE_DEVICE_PATH, 50 | HW_VENDOR_DP, 51 | { 52 | (UINT8)(sizeof(VENDOR_DEVICE_PATH)), 53 | (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8), 54 | } 55 | }, 56 | EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID 57 | }, 58 | { 59 | END_DEVICE_PATH_TYPE, 60 | END_ENTIRE_DEVICE_PATH_SUBTYPE, 61 | { 62 | sizeof(EFI_DEVICE_PATH_PROTOCOL), 63 | 0 64 | } 65 | } 66 | }; 67 | 68 | /// Declares 69 | 70 | STATIC FRAME_BUFFER_CONFIGURE *mFrameBufferBltLibConfigure; 71 | STATIC UINTN mFrameBufferBltLibConfigureSize; 72 | 73 | STATIC 74 | EFI_STATUS 75 | EFIAPI 76 | DisplayQueryMode 77 | ( 78 | IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, 79 | IN UINT32 ModeNumber, 80 | OUT UINTN *SizeOfInfo, 81 | OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info 82 | ); 83 | 84 | STATIC 85 | EFI_STATUS 86 | EFIAPI 87 | DisplaySetMode 88 | ( 89 | IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, 90 | IN UINT32 ModeNumber 91 | ); 92 | 93 | STATIC 94 | EFI_STATUS 95 | EFIAPI 96 | DisplayBlt 97 | ( 98 | IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, 99 | IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL 100 | IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, 101 | IN UINTN SourceX, 102 | IN UINTN SourceY, 103 | IN UINTN DestinationX, 104 | IN UINTN DestinationY, 105 | IN UINTN Width, 106 | IN UINTN Height, 107 | IN UINTN Delta OPTIONAL 108 | ); 109 | 110 | STATIC EFI_GRAPHICS_OUTPUT_PROTOCOL mDisplay = { 111 | DisplayQueryMode, 112 | DisplaySetMode, 113 | DisplayBlt, 114 | NULL 115 | }; 116 | 117 | STATIC 118 | EFI_STATUS 119 | EFIAPI 120 | DisplayQueryMode 121 | ( 122 | IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, 123 | IN UINT32 ModeNumber, 124 | OUT UINTN *SizeOfInfo, 125 | OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info 126 | ) 127 | { 128 | EFI_STATUS Status; 129 | Status = gBS->AllocatePool( 130 | EfiBootServicesData, 131 | sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), 132 | (VOID **) Info); 133 | 134 | ASSERT_EFI_ERROR(Status); 135 | 136 | *SizeOfInfo = sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); 137 | (*Info)->Version = This->Mode->Info->Version; 138 | (*Info)->HorizontalResolution = This->Mode->Info->HorizontalResolution; 139 | (*Info)->VerticalResolution = This->Mode->Info->VerticalResolution; 140 | (*Info)->PixelFormat = This->Mode->Info->PixelFormat; 141 | (*Info)->PixelsPerScanLine = This->Mode->Info->PixelsPerScanLine; 142 | 143 | return EFI_SUCCESS; 144 | } 145 | 146 | STATIC 147 | EFI_STATUS 148 | EFIAPI 149 | DisplaySetMode 150 | ( 151 | IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, 152 | IN UINT32 ModeNumber 153 | ) 154 | { 155 | return EFI_SUCCESS; 156 | } 157 | 158 | STATIC 159 | EFI_STATUS 160 | EFIAPI 161 | DisplayBlt 162 | ( 163 | IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, 164 | IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL 165 | IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, 166 | IN UINTN SourceX, 167 | IN UINTN SourceY, 168 | IN UINTN DestinationX, 169 | IN UINTN DestinationY, 170 | IN UINTN Width, 171 | IN UINTN Height, 172 | IN UINTN Delta OPTIONAL 173 | ) 174 | { 175 | 176 | RETURN_STATUS Status; 177 | EFI_TPL Tpl; 178 | // 179 | // We have to raise to TPL_NOTIFY, so we make an atomic write to the frame buffer. 180 | // We would not want a timer based event (Cursor, ...) to come in while we are 181 | // doing this operation. 182 | // 183 | Tpl = gBS->RaiseTPL (TPL_NOTIFY); 184 | Status = FrameBufferBlt ( 185 | mFrameBufferBltLibConfigure, 186 | BltBuffer, 187 | BltOperation, 188 | SourceX, SourceY, 189 | DestinationX, DestinationY, Width, Height, 190 | Delta 191 | ); 192 | gBS->RestoreTPL (Tpl); 193 | 194 | // zhuowei: hack: flush the cache manually since my memory maps are still broken 195 | WriteBackInvalidateDataCacheRange((void*)mDisplay.Mode->FrameBufferBase, 196 | mDisplay.Mode->FrameBufferSize); 197 | // zhuowei: end hack 198 | 199 | return RETURN_ERROR (Status) ? EFI_INVALID_PARAMETER : EFI_SUCCESS; 200 | } 201 | 202 | EFI_STATUS 203 | EFIAPI 204 | SimpleFbDxeInitialize 205 | ( 206 | IN EFI_HANDLE ImageHandle, 207 | IN EFI_SYSTEM_TABLE *SystemTable 208 | ) 209 | { 210 | 211 | EFI_STATUS Status = EFI_SUCCESS; 212 | EFI_HANDLE hUEFIDisplayHandle = NULL; 213 | 214 | /* Retrieve simple frame buffer from pre-SEC bootloader */ 215 | DEBUG((EFI_D_ERROR, "SimpleFbDxe: Retrieve MIPI FrameBuffer parameters from PCD\n")); 216 | UINT32 MipiFrameBufferAddr = FixedPcdGet32(PcdMipiFrameBufferAddress); 217 | UINT32 MipiFrameBufferWidth = FixedPcdGet32(PcdMipiFrameBufferWidth); 218 | UINT32 MipiFrameBufferHeight = FixedPcdGet32(PcdMipiFrameBufferHeight); 219 | 220 | /* Sanity check */ 221 | if (MipiFrameBufferAddr == 0 || MipiFrameBufferWidth == 0 || MipiFrameBufferHeight == 0) 222 | { 223 | DEBUG((EFI_D_ERROR, "SimpleFbDxe: Invalid FrameBuffer parameters\n")); 224 | return EFI_DEVICE_ERROR; 225 | } 226 | 227 | /* Prepare struct */ 228 | if (mDisplay.Mode == NULL) 229 | { 230 | Status = gBS->AllocatePool( 231 | EfiBootServicesData, 232 | sizeof(EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE), 233 | (VOID **) &mDisplay.Mode 234 | ); 235 | 236 | ASSERT_EFI_ERROR(Status); 237 | if (EFI_ERROR(Status)) return Status; 238 | 239 | ZeroMem(mDisplay.Mode, sizeof(EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE)); 240 | } 241 | 242 | if (mDisplay.Mode->Info == NULL) 243 | { 244 | Status = gBS->AllocatePool( 245 | EfiBootServicesData, 246 | sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), 247 | (VOID **) &mDisplay.Mode->Info 248 | ); 249 | 250 | ASSERT_EFI_ERROR(Status); 251 | if (EFI_ERROR(Status)) return Status; 252 | 253 | ZeroMem(mDisplay.Mode->Info, sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION)); 254 | } 255 | 256 | /* Set information */ 257 | mDisplay.Mode->MaxMode = 1; 258 | mDisplay.Mode->Mode = 0; 259 | mDisplay.Mode->Info->Version = 0; 260 | 261 | mDisplay.Mode->Info->HorizontalResolution = MipiFrameBufferWidth; 262 | mDisplay.Mode->Info->VerticalResolution = MipiFrameBufferHeight; 263 | 264 | /* SimpleFB runs on a8r8g8b8 (VIDEO_BPP32) for DB410c */ 265 | UINT32 LineLength = MipiFrameBufferWidth * VNBYTES(VIDEO_BPP32); 266 | UINT32 FrameBufferSize = LineLength * MipiFrameBufferHeight; 267 | EFI_PHYSICAL_ADDRESS FrameBufferAddress = MipiFrameBufferAddr; 268 | 269 | mDisplay.Mode->Info->PixelsPerScanLine = MipiFrameBufferWidth; 270 | mDisplay.Mode->Info->PixelFormat = PixelBlueGreenRedReserved8BitPerColor; 271 | mDisplay.Mode->SizeOfInfo = sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); 272 | mDisplay.Mode->FrameBufferBase = FrameBufferAddress; 273 | mDisplay.Mode->FrameBufferSize = FrameBufferSize; 274 | 275 | // 276 | // Create the FrameBufferBltLib configuration. 277 | // 278 | Status = FrameBufferBltConfigure ( 279 | (VOID *) (UINTN) mDisplay.Mode->FrameBufferBase, 280 | mDisplay.Mode->Info, 281 | mFrameBufferBltLibConfigure, 282 | &mFrameBufferBltLibConfigureSize 283 | ); 284 | if (Status == RETURN_BUFFER_TOO_SMALL) { 285 | mFrameBufferBltLibConfigure = AllocatePool (mFrameBufferBltLibConfigureSize); 286 | if (mFrameBufferBltLibConfigure != NULL) { 287 | Status = FrameBufferBltConfigure ( 288 | (VOID *) (UINTN) mDisplay.Mode->FrameBufferBase, 289 | mDisplay.Mode->Info, 290 | mFrameBufferBltLibConfigure, 291 | &mFrameBufferBltLibConfigureSize 292 | ); 293 | } 294 | } 295 | ASSERT_EFI_ERROR (Status); 296 | 297 | // zhuowei: clear the screen to black 298 | // UEFI standard requires this, since text is white - see OvmfPkg/QemuVideoDxe/Gop.c 299 | ZeroMem((void*)FrameBufferAddress, FrameBufferSize); 300 | // hack: clear cache 301 | WriteBackInvalidateDataCacheRange((void*)FrameBufferAddress, FrameBufferSize); 302 | // zhuowei: end 303 | 304 | /* Register handle */ 305 | Status = gBS->InstallMultipleProtocolInterfaces( 306 | &hUEFIDisplayHandle, 307 | &gEfiDevicePathProtocolGuid, 308 | &mDisplayDevicePath, 309 | &gEfiGraphicsOutputProtocolGuid, 310 | &mDisplay, 311 | NULL); 312 | 313 | ASSERT_EFI_ERROR (Status); 314 | 315 | return Status; 316 | 317 | } 318 | -------------------------------------------------------------------------------- /Pixel3XL/Pixel3XL.dsc: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2018, Linaro Limited. All rights reserved. 3 | # 4 | # This program and the accompanying materials 5 | # are licensed and made available under the terms and conditions of the BSD License 6 | # which accompanies this distribution. The full text of the license may be found at 7 | # http://opensource.org/licenses/bsd-license.php 8 | # 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 | # 12 | 13 | ################################################################################ 14 | # 15 | # Defines Section - statements that will be processed to create a Makefile. 16 | # 17 | ################################################################################ 18 | [Defines] 19 | PLATFORM_NAME = Pixel3XL 20 | PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee 21 | PLATFORM_VERSION = 0.1 22 | DSC_SPECIFICATION = 0x00010019 23 | OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) 24 | SUPPORTED_ARCHITECTURES = AARCH64 25 | BUILD_TARGETS = DEBUG|RELEASE 26 | SKUID_IDENTIFIER = DEFAULT 27 | FLASH_DEFINITION = Pixel3XL/Pixel3XL.fdf 28 | 29 | !include Pixel3XL/CommonDsc.dsc.inc 30 | 31 | [LibraryClasses.common] 32 | ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf 33 | ArmPlatformLib|Pixel3XL/Library/Pixel3XLLib/Pixel3XLLib.inf 34 | 35 | CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf 36 | UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf 37 | PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf 38 | CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf 39 | 40 | # UiApp dependencies 41 | ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf 42 | FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf 43 | DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf 44 | BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf 45 | 46 | SerialPortLib|Pixel3XL/Library/InMemorySerialPortLib/InMemorySerialPortLib.inf 47 | RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf 48 | TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf 49 | 50 | # USB Requirements 51 | UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf 52 | 53 | # Network Libraries 54 | UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf 55 | NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf 56 | DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf 57 | IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf 58 | UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf 59 | 60 | # VariableRuntimeDxe Requirements 61 | SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf 62 | AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf 63 | TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf 64 | VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf 65 | 66 | # SimpleFbDxe 67 | FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf 68 | 69 | [LibraryClasses.common.SEC] 70 | PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf 71 | ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf 72 | HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf 73 | MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf 74 | MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf 75 | PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf 76 | PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf 77 | 78 | ################################################################################ 79 | # 80 | # Pcd Section - list of all EDK II PCD Entries defined by this Platform 81 | # 82 | ################################################################################ 83 | 84 | [PcdsFeatureFlag.common] 85 | ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. 86 | # It could be set FALSE to save size. 87 | gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE 88 | gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE 89 | 90 | 91 | [PcdsFixedAtBuild.common] 92 | gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 93 | 94 | gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha" 95 | 96 | # System Memory (4GB) 97 | gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 98 | gArmTokenSpaceGuid.PcdSystemMemorySize|0xe0000000 99 | 100 | # We only boot one processor here! 101 | gArmPlatformTokenSpaceGuid.PcdCoreCount|1 102 | gArmPlatformTokenSpaceGuid.PcdClusterCount|1 103 | 104 | # 105 | # ARM PrimeCell 106 | # 107 | 108 | # 109 | # ARM General Interrupt Controller 110 | # 111 | gArmTokenSpaceGuid.PcdGicDistributorBase|0x17a00000 112 | gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x17a60000 113 | 114 | gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|0x12 115 | gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|0x13 116 | 117 | # GUID of the UI app 118 | gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } 119 | 120 | gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE 121 | 122 | gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 123 | 124 | # 125 | # 126 | # Fastboot 127 | # 128 | gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x18d1 129 | gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0xd00d 130 | 131 | # 132 | # Make VariableRuntimeDxe work at emulated non-volatile variable mode. 133 | # 134 | gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE 135 | 136 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferAddress|0x9d400000 137 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferWidth|1440 138 | gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferHeight|2960 139 | 140 | gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 141 | 142 | ################################################################################ 143 | # 144 | # Components Section - list of all EDK II Modules needed by this Platform 145 | # 146 | ################################################################################ 147 | [Components.common] 148 | # 149 | # PEI Phase modules 150 | # 151 | ArmPlatformPkg/PrePi/PeiUniCore.inf 152 | 153 | # 154 | # DXE 155 | # 156 | MdeModulePkg/Core/Dxe/DxeMain.inf { 157 | 158 | PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf 159 | NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf 160 | } 161 | 162 | # 163 | # Architectural Protocols 164 | # 165 | ArmPkg/Drivers/CpuDxe/CpuDxe.inf 166 | MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf 167 | MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf 168 | MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf 169 | EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf 170 | MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf 171 | EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf 172 | EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf 173 | 174 | MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf 175 | MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf 176 | MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf 177 | MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf 178 | MdeModulePkg/Universal/SerialDxe/SerialDxe.inf 179 | 180 | MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf 181 | 182 | ArmPkg/Drivers/ArmGic/ArmGicDxe.inf 183 | ArmPkg/Drivers/TimerDxe/TimerDxe.inf 184 | 185 | MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf 186 | 187 | MdeModulePkg/Universal/PCD/Dxe/Pcd.inf 188 | 189 | # 190 | # GPIO 191 | # 192 | 193 | # 194 | # Virtual Keyboard 195 | # 196 | EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf 197 | 198 | Pixel3XL/Pixel3XLDxe/Pixel3XLDxe.inf 199 | Pixel3XL/SimpleFbDxe/SimpleFbDxe.inf 200 | 201 | # 202 | # USB Host Support 203 | # 204 | MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf 205 | 206 | # 207 | # USB Mass Storage Support 208 | # 209 | MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf 210 | 211 | # 212 | # USB Peripheral Support 213 | # 214 | EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf 215 | 216 | # 217 | # Fastboot 218 | # 219 | EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf 220 | 221 | 222 | # 223 | # FAT filesystem + GPT/MBR partitioning 224 | # 225 | MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf 226 | MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf 227 | MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf 228 | FatPkg/EnhancedFatDxe/Fat.inf 229 | 230 | # 231 | # ACPI Support 232 | # 233 | MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf 234 | MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf 235 | MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf 236 | Pixel3XL/AcpiTables/AcpiTables.inf 237 | 238 | # 239 | # SMBIOS Support 240 | # 241 | Pixel3XL/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf 242 | MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf 243 | 244 | # 245 | # Bds 246 | # 247 | MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf 248 | MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf { 249 | 250 | PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf 251 | } 252 | MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf 253 | MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf 254 | MdeModulePkg/Universal/BdsDxe/BdsDxe.inf 255 | MdeModulePkg/Application/UiApp/UiApp.inf { 256 | 257 | NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf 258 | NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf 259 | NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf 260 | PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf 261 | } 262 | ShellPkg/Application/Shell/Shell.inf { 263 | 264 | ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf 265 | NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf 266 | NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf 267 | NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf 268 | NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf 269 | NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf 270 | NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf 271 | NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf 272 | NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf 273 | HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf 274 | PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf 275 | BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf 276 | 277 | gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF 278 | gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE 279 | gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 280 | } 281 | !ifdef $(INCLUDE_TFTP_COMMAND) 282 | ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf 283 | !endif #$(INCLUDE_TFTP_COMMAND) 284 | -------------------------------------------------------------------------------- /Pixel3XL/AcpiTables/Dsdt.asl: -------------------------------------------------------------------------------- 1 | /** @file 2 | Differentiated System Description Table Fields (DSDT) 3 | 4 | Copyright (c) 2014-2018, ARM Ltd. All rights reserved.
5 | This program and the accompanying materials 6 | are licensed and made available under the terms and conditions of the BSD License 7 | which accompanies this distribution. The full text of the license may be found at 8 | http://opensource.org/licenses/bsd-license.php 9 | 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 | 13 | **/ 14 | 15 | #include "ArmPlatform.h" 16 | 17 | DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) { 18 | Scope(_SB) { 19 | // 20 | // A57x2-A53x4 Processor declaration 21 | // 22 | Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities 23 | CreateDWordField (Arg3, 0x00, STS0) 24 | CreateDWordField (Arg3, 0x04, CAP0) 25 | #if 0 26 | If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */)) { 27 | If (!(Arg1 == One)) { 28 | STS0 &= ~0x1F 29 | STS0 |= 0x0A 30 | } Else { 31 | If ((CAP0 & 0x100)) { 32 | CAP0 &= ~0x100 /* No support for OS Initiated LPI */ 33 | STS0 &= ~0x1F 34 | STS0 |= 0x12 35 | } 36 | } 37 | } Else { 38 | STS0 &= ~0x1F 39 | STS0 |= 0x06 40 | } 41 | #endif // platformwide 42 | Return (Arg3) 43 | } 44 | Device (CLU0) { // Cluster0 state 45 | Name(_HID, "ACPI0010") 46 | Name(_UID, 1) 47 | #if 0 48 | Name (_LPI, Package() { 49 | 0, // Version 50 | 0, // Level Index 51 | 1, // Count 52 | Package() { // Power Gating state for Cluster 53 | 2500, // Min residency (uS) 54 | 1150, // Wake latency (uS) 55 | 1, // Flags 56 | 1, // Arch Context Flags 57 | 100, //Residency Counter Frequency 58 | 0, // No Parent State 59 | 0x01000000, // Integer Entry method 60 | ResourceTemplate() { // Null Residency Counter 61 | Register (SystemMemory, 0, 0, 0, 0) 62 | }, 63 | ResourceTemplate() { // Null Usage Counter 64 | Register (SystemMemory, 0, 0, 0, 0) 65 | }, 66 | "CluPwrDn" 67 | }, 68 | }) 69 | Name(PLPI, Package() { 70 | 0, // Version 71 | 0, // Level Index 72 | 2, // Count 73 | Package() { // WFI for CPU 74 | 1, // Min residency (uS) 75 | 1, // Wake latency (uS) 76 | 1, // Flags 77 | 0, // Arch Context Flags 78 | 100, //Residency Counter Frequency 79 | 0, // No parent state 80 | ResourceTemplate () { 81 | // Register Entry method 82 | Register (FFixedHW, 83 | 0x20, // Bit Width 84 | 0x00, // Bit Offset 85 | 0xFFFFFFFF, // Address 86 | 0x03, // Access Size 87 | ) 88 | }, 89 | ResourceTemplate() { // Null Residency Counter 90 | Register (SystemMemory, 0, 0, 0, 0) 91 | }, 92 | ResourceTemplate() { // Null Usage Counter 93 | Register (SystemMemory, 0, 0, 0, 0) 94 | }, 95 | "WFI", 96 | }, 97 | Package() { // Power Gating state for CPU 98 | 150, // Min residency (uS) 99 | 350, // Wake latency (uS) 100 | 1, // Flags 101 | 1, // Arch Context Flags 102 | 100, //Residency Counter Frequency 103 | 1, // Parent node can be in any state 104 | ResourceTemplate () { 105 | // Register Entry method 106 | Register (FFixedHW, 107 | 0x20, // Bit Width 108 | 0x00, // Bit Offset 109 | 0x00010000, // Address 110 | 0x03, // Access Size 111 | ) 112 | }, 113 | ResourceTemplate() { // Null Residency Counter 114 | Register (SystemMemory, 0, 0, 0, 0) 115 | }, 116 | ResourceTemplate() { // Null Usage Counter 117 | Register (SystemMemory, 0, 0, 0, 0) 118 | }, 119 | "CorePwrDn" 120 | }, 121 | }) 122 | #endif // power 123 | Device(CPU0) { // A57-0: Cluster 0, Cpu 0 124 | Name(_HID, "ACPI0007") 125 | Name(_UID, 0) 126 | #if 0 127 | Method (_LPI, 0, NotSerialized) { 128 | return(PLPI) 129 | } 130 | #endif 131 | } 132 | #if 0 133 | Device(CPU1) { // A57-1: Cluster 0, Cpu 1 134 | Name(_HID, "ACPI0007") 135 | Name(_UID, 5) 136 | Method (_LPI, 0, NotSerialized) { 137 | return(PLPI) 138 | } 139 | } 140 | #endif // cpu 0 141 | } 142 | #if 0 143 | Device (CLU1) { // Cluster1 state 144 | Name(_HID, "ACPI0010") 145 | Name(_UID, 2) 146 | Name (_LPI, Package() { 147 | 0, // Version 148 | 0, // Level Index 149 | 1, // Count 150 | Package() { // Power Gating state for Cluster 151 | 2500, // Min residency (uS) 152 | 1150, // Wake latency (uS) 153 | 1, // Flags 154 | 1, // Arch Context Flags 155 | 100, //Residency Counter Frequency 156 | 0, // No Parent State 157 | 0x01000000, // Integer Entry method 158 | ResourceTemplate() { // Null Residency Counter 159 | Register (SystemMemory, 0, 0, 0, 0) 160 | }, 161 | ResourceTemplate() { // Null Usage Counter 162 | Register (SystemMemory, 0, 0, 0, 0) 163 | }, 164 | "CluPwrDn" 165 | }, 166 | }) 167 | Name(PLPI, Package() { 168 | 0, // Version 169 | 0, // Level Index 170 | 2, // Count 171 | Package() { // WFI for CPU 172 | 1, // Min residency (uS) 173 | 1, // Wake latency (uS) 174 | 1, // Flags 175 | 0, // Arch Context Flags 176 | 100, //Residency Counter Frequency 177 | 0, // No parent state 178 | ResourceTemplate () { 179 | // Register Entry method 180 | Register (FFixedHW, 181 | 0x20, // Bit Width 182 | 0x00, // Bit Offset 183 | 0xFFFFFFFF, // Address 184 | 0x03, // Access Size 185 | ) 186 | }, 187 | ResourceTemplate() { // Null Residency Counter 188 | Register (SystemMemory, 0, 0, 0, 0) 189 | }, 190 | ResourceTemplate() { // Null Usage Counter 191 | Register (SystemMemory, 0, 0, 0, 0) 192 | }, 193 | "WFI", 194 | }, 195 | Package() { // Power Gating state for CPU 196 | 150, // Min residency (uS) 197 | 350, // Wake latency (uS) 198 | 1, // Flags 199 | 1, // Arch Context Flags 200 | 100, //Residency Counter Frequency 201 | 1, // Parent node can be in any state 202 | ResourceTemplate () { 203 | // Register Entry method 204 | Register (FFixedHW, 205 | 0x20, // Bit Width 206 | 0x00, // Bit Offset 207 | 0x00010000, // Address 208 | 0x03, // Access Size 209 | ) 210 | }, 211 | ResourceTemplate() { // Null Residency Counter 212 | Register (SystemMemory, 0, 0, 0, 0) 213 | }, 214 | ResourceTemplate() { // Null Usage Counter 215 | Register (SystemMemory, 0, 0, 0, 0) 216 | }, 217 | "CorePwrDn" 218 | }, 219 | }) 220 | Device(CPU2) { // A53-0: Cluster 1, Cpu 0 221 | Name(_HID, "ACPI0007") 222 | Name(_UID, 0) 223 | Method (_LPI, 0, NotSerialized) { 224 | return(PLPI) 225 | } 226 | } 227 | Device(CPU3) { // A53-1: Cluster 1, Cpu 1 228 | Name(_HID, "ACPI0007") 229 | Name(_UID, 1) 230 | Method (_LPI, 0, NotSerialized) { 231 | return(PLPI) 232 | } 233 | } 234 | Device(CPU4) { // A53-2: Cluster 1, Cpu 2 235 | Name(_HID, "ACPI0007") 236 | Name(_UID, 2) 237 | Method (_LPI, 0, NotSerialized) { 238 | return(PLPI) 239 | } 240 | } 241 | Device(CPU5) { // A53-3: Cluster 1, Cpu 3 242 | Name(_HID, "ACPI0007") 243 | Name(_UID, 3) 244 | Method (_LPI, 0, NotSerialized) { 245 | return(PLPI) 246 | } 247 | } 248 | } 249 | #endif // cluster 1 250 | 251 | #if 0 252 | // 253 | // Keyboard and Mouse 254 | // 255 | Device(KMI0) { 256 | Name(_HID, "ARMH0501") 257 | Name(_CID, "PL050_KBD") 258 | Name(_CRS, ResourceTemplate() { 259 | Memory32Fixed(ReadWrite, 0x1C060008, 0x4) 260 | Memory32Fixed(ReadWrite, 0x1C060000, 0x4) 261 | Memory32Fixed(ReadOnly, 0x1C060004, 0x4) 262 | Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 197 } 263 | }) 264 | } 265 | 266 | // 267 | // LAN9118 Ethernet 268 | // 269 | Device(ETH0) { 270 | Name(_HID, "ARMH9118") 271 | Name(_UID, Zero) 272 | Name(_CRS, ResourceTemplate() { 273 | Memory32Fixed(ReadWrite, 0x18000000, 0x1000) 274 | Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 192 } 275 | }) 276 | Name(_DSD, Package() { 277 | ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), 278 | Package() { 279 | Package(2) {"phy-mode", "mii"}, 280 | Package(2) {"reg-io-width", 4 }, 281 | Package(2) {"smsc,irq-active-high",1}, 282 | Package(2) {"smsc,irq-push-pull",1} 283 | } 284 | }) // _DSD() 285 | } 286 | 287 | // UART PL011 288 | Device(COM0) { 289 | Name(_HID, "ARMH0011") 290 | Name(_CID, "PL011") 291 | Name(_UID, Zero) 292 | Name(_CRS, ResourceTemplate() { 293 | Memory32Fixed(ReadWrite, 0x7FF80000, 0x1000) 294 | Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 } 295 | }) 296 | } 297 | 298 | // 299 | // USB EHCI Host Controller 300 | // 301 | Device(USB0){ 302 | Name(_HID, "ARMH0D20") 303 | Name(_CID, "PNP0D20") 304 | Name(_UID, 2) 305 | Name(_CCA, 0) //EHCI on this platform is not coherent! 306 | 307 | Method(_CRS, 0x0, Serialized){ 308 | Name(RBUF, ResourceTemplate(){ 309 | Memory32Fixed(ReadWrite, 0x7FFC0000, 0x10000) 310 | Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {149} // INT ID=149 GIC IRQ ID=117 for Juno SoC USB EHCI Controller 311 | }) 312 | Return(RBUF) 313 | } 314 | 315 | // 316 | // Root Hub 317 | // 318 | Device(RHUB){ 319 | Name(_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec 320 | 321 | // 322 | // Ports connected to Root Hub 323 | // 324 | Device(HUB1){ 325 | Name(_ADR, 0x00000001) 326 | Name(_UPC, Package(){ 327 | 0x00, // Port is NOT connectable 328 | 0xFF, // Don't care 329 | 0x00000000, // Reserved 0 must be zero 330 | 0x00000000 // Reserved 1 must be zero 331 | }) 332 | 333 | Device(PRT1){ 334 | Name(_ADR, 0x00000001) 335 | Name(_UPC, Package(){ 336 | 0xFF, // Port is connectable 337 | 0x00, // Port connector is A 338 | 0x00000000, 339 | 0x00000000 340 | }) 341 | Name(_PLD, Package(){ 342 | Buffer(0x10){ 343 | 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 344 | 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 345 | } 346 | }) 347 | } // USB0_RHUB_HUB1_PRT1 348 | Device(PRT2){ 349 | Name(_ADR, 0x00000002) 350 | Name(_UPC, Package(){ 351 | 0xFF, // Port is connectable 352 | 0x00, // Port connector is A 353 | 0x00000000, 354 | 0x00000000 355 | }) 356 | Name(_PLD, Package(){ 357 | Buffer(0x10){ 358 | 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 359 | 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 360 | } 361 | }) 362 | } // USB0_RHUB_HUB1_PRT2 363 | 364 | Device(PRT3){ 365 | Name(_ADR, 0x00000003) 366 | Name(_UPC, Package(){ 367 | 0xFF, // Port is connectable 368 | 0x00, // Port connector is A 369 | 0x00000000, 370 | 0x00000000 371 | }) 372 | Name(_PLD, Package(){ 373 | Buffer(0x10){ 374 | 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 375 | 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 376 | } 377 | }) 378 | } // USB0_RHUB_HUB1_PRT3 379 | 380 | Device(PRT4){ 381 | Name(_ADR, 0x00000004) 382 | Name(_UPC, Package(){ 383 | 0xFF, // Port is connectable 384 | 0x00, // Port connector is A 385 | 0x00000000, 386 | 0x00000000 387 | }) 388 | Name(_PLD, Package(){ 389 | Buffer(0x10){ 390 | 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 391 | 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 392 | } 393 | }) 394 | } // USB0_RHUB_HUB1_PRT4 395 | } // USB0_RHUB_HUB1 396 | } // USB0_RHUB 397 | } // USB0 398 | #endif 399 | } // Scope(_SB) 400 | } 401 | -------------------------------------------------------------------------------- /Pixel3XL/CommonDsc.dsc.inc: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2011-2012, ARM Limited. All rights reserved. 3 | # Copyright (c) 2016, Hisilicon Limited. All rights reserved. 4 | # Copyright (c) 2016, Linaro Limited. All rights reserved. 5 | # 6 | # This program and the accompanying materials 7 | # are licensed and made available under the terms and conditions of the BSD License 8 | # which accompanies this distribution. The full text of the license may be found at 9 | # http://opensource.org/licenses/bsd-license.php 10 | # 11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 | # 14 | # 15 | 16 | [LibraryClasses.common] 17 | !if $(TARGET) == RELEASE 18 | DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf 19 | !else 20 | DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf 21 | !endif 22 | DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf 23 | 24 | BaseLib|MdePkg/Library/BaseLib/BaseLib.inf 25 | BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf 26 | SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf 27 | SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf 28 | PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf 29 | PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf 30 | PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf 31 | PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf 32 | IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf 33 | UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf 34 | CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf 35 | 36 | UefiLib|MdePkg/Library/UefiLib/UefiLib.inf 37 | HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf 38 | UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf 39 | DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf 40 | UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf 41 | DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf 42 | UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf 43 | UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf 44 | HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf 45 | UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf 46 | 47 | UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf 48 | OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf 49 | # 50 | # Allow dynamic PCDs 51 | # 52 | PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf 53 | 54 | BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf 55 | 56 | # ARM Architectural Libraries 57 | CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf 58 | DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf 59 | CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf 60 | ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf 61 | ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf 62 | ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf 63 | ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf 64 | ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf 65 | ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf 66 | 67 | ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf 68 | 69 | # ARM PL011 UART Driver 70 | PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf 71 | PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf 72 | 73 | TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf 74 | 75 | UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf 76 | # 77 | # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window 78 | # in the debugger will show load and unload commands for symbols. You can cut and paste this 79 | # into the command window to load symbols. We should be able to use a script to do this, but 80 | # the version of RVD I have does not support scripts accessing system memory. 81 | # 82 | #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf 83 | #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf 84 | PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf 85 | 86 | DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf 87 | DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf 88 | 89 | SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf 90 | 91 | TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf 92 | AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf 93 | 94 | # BDS Libraries 95 | FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf 96 | UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf 97 | 98 | VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf 99 | 100 | ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf 101 | LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf 102 | 103 | NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf 104 | 105 | FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf 106 | ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf 107 | SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf 108 | 109 | CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf 110 | OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf 111 | IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf 112 | BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf 113 | FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf 114 | EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf 115 | IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf 116 | 117 | # 118 | # It is not possible to prevent the ARM compiler for generic intrinsic functions. 119 | # This library provides the instrinsic functions generate by a given compiler. 120 | # And NULL mean link this library into all ARM images. 121 | # 122 | NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf 123 | 124 | # Add support for GCC stack protector 125 | NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf 126 | 127 | [LibraryClasses.common.SEC] 128 | ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf 129 | PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf 130 | BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf 131 | 132 | [LibraryClasses.common.PEI_CORE] 133 | HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf 134 | PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf 135 | MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf 136 | PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf 137 | PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf 138 | ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf 139 | OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf 140 | PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf 141 | UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf 142 | ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf 143 | 144 | PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf 145 | PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf 146 | BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf 147 | 148 | [LibraryClasses.common.PEIM] 149 | HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf 150 | PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf 151 | MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf 152 | PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf 153 | PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf 154 | ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf 155 | OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf 156 | PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf 157 | PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf 158 | UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf 159 | ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf 160 | 161 | PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf 162 | 163 | ## Fixed compile error after upgrade to 14.10 164 | PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf 165 | PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf 166 | ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf 167 | BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf 168 | 169 | [LibraryClasses.common.DXE_CORE] 170 | HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf 171 | MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf 172 | DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf 173 | ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf 174 | ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf 175 | UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf 176 | DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf 177 | PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf 178 | 179 | [LibraryClasses.common.DXE_DRIVER] 180 | ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf 181 | DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf 182 | SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf 183 | PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf 184 | MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf 185 | 186 | [LibraryClasses.common.UEFI_APPLICATION] 187 | UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf 188 | PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf 189 | MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf 190 | HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf 191 | 192 | [LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION] 193 | DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf 194 | ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf 195 | UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf 196 | 197 | [LibraryClasses.common.UEFI_DRIVER] 198 | ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf 199 | UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf 200 | ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf 201 | PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf 202 | DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf 203 | MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf 204 | 205 | [LibraryClasses.common.DXE_RUNTIME_DRIVER] 206 | HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf 207 | MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf 208 | ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf 209 | CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf 210 | !ifndef CONFIG_NO_DEBUGLIB 211 | DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf 212 | !endif 213 | !if $(TARGET) != RELEASE 214 | DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf 215 | !endif 216 | 217 | [LibraryClasses.AARCH64] 218 | ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf 219 | 220 | [BuildOptions] 221 | RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG 222 | GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG 223 | 224 | [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] 225 | GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000 226 | GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 227 | 228 | ################################################################################ 229 | # 230 | # Pcd Section - list of all EDK II PCD Entries defined by this Platform 231 | # 232 | ################################################################################ 233 | 234 | [PcdsFeatureFlag.common] 235 | gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE 236 | gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE 237 | gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE 238 | gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE 239 | 240 | # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress 241 | gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE 242 | 243 | gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE 244 | 245 | gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE 246 | 247 | gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE 248 | 249 | gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE 250 | 251 | [PcdsFixedAtBuild.common] 252 | # 253 | # IO is mapped to memory space, so we use the same size of 254 | # PcdPrePiCpuMemorySize 255 | # 256 | gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 257 | gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 258 | gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 259 | gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 260 | gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 261 | gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF 262 | gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 263 | gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 264 | gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 265 | gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 266 | 267 | # DEBUG_ASSERT_ENABLED 0x01 268 | # DEBUG_PRINT_ENABLED 0x02 269 | # DEBUG_CODE_ENABLED 0x04 270 | # CLEAR_MEMORY_ENABLED 0x08 271 | # ASSERT_BREAKPOINT_ENABLED 0x10 272 | # ASSERT_DEADLOOP_ENABLED 0x20 273 | !if $(TARGET) == RELEASE 274 | gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e 275 | !else 276 | gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f 277 | !endif 278 | 279 | # DEBUG_INIT 0x00000001 // Initialization 280 | # DEBUG_WARN 0x00000002 // Warnings 281 | # DEBUG_LOAD 0x00000004 // Load events 282 | # DEBUG_FS 0x00000008 // EFI File system 283 | # DEBUG_POOL 0x00000010 // Alloc & Free's 284 | # DEBUG_PAGE 0x00000020 // Alloc & Free's 285 | # DEBUG_INFO 0x00000040 // Verbose 286 | # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers 287 | # DEBUG_VARIABLE 0x00000100 // Variable 288 | # DEBUG_BM 0x00000400 // Boot Manager 289 | # DEBUG_BLKIO 0x00001000 // BlkIo Driver 290 | # DEBUG_NET 0x00004000 // SNI Driver 291 | # DEBUG_UNDI 0x00010000 // UNDI Driver 292 | # DEBUG_LOADFILE 0x00020000 // UNDI Driver 293 | # DEBUG_EVENT 0x00080000 // Event messages 294 | # DEBUG_ERROR 0x80000000 // Error 295 | 296 | gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 297 | gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06 298 | 299 | # 300 | # Optional feature to help prevent EFI memory map fragments 301 | # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob 302 | # Values are in EFI Pages (4K). DXE Core will make sure that 303 | # at least this much of each type of memory can be allocated 304 | # from a single memory range. This way you only end up with 305 | # maximum of two fragements for each type in the memory map 306 | # (the memory used, and the free memory that was prereserved 307 | # but not used). 308 | # 309 | gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 310 | gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 311 | gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 312 | gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 313 | gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 314 | gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 315 | gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 316 | gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 317 | gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 318 | 319 | # Set timer interrupt to be triggerred in 1ms to avoid missing 320 | # serial terminal input characters. 321 | gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 322 | gArmTokenSpaceGuid.PcdVFPEnabled|1 323 | gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32 324 | 325 | [PcdsDynamicHii.common.DEFAULT] 326 | gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 # Variable: L"Timeout" 327 | 328 | -------------------------------------------------------------------------------- /Pixel3XL/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c: -------------------------------------------------------------------------------- 1 | /** @file 2 | This driver installs SMBIOS information for ARM Juno platforms 3 | 4 | Copyright (c) 2015, ARM Limited. All rights reserved. 5 | 6 | This program and the accompanying materials 7 | are licensed and made available under the terms and conditions of the BSD License 8 | which accompanies this distribution. The full text of the license may be found at 9 | http://opensource.org/licenses/bsd-license.php 10 | 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 | 14 | **/ 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | 29 | #define TYPE0_STRINGS \ 30 | "EFI Development Kit II / ARM LTD\0" /* Vendor */ \ 31 | "EDK II\0" /* BiosVersion */ \ 32 | __DATE__"\0" /* BiosReleaseDate */ 33 | 34 | #define TYPE1_STRINGS \ 35 | "Google\0" /* Manufacturer */ \ 36 | "Pixel 3 XL\0" /* Product Name */ \ 37 | "None\0" /* Version */ \ 38 | " \0" /* 20 character buffer */ 39 | 40 | #define TYPE2_STRINGS \ 41 | "Google\0" /* Manufacturer */ \ 42 | "Pixel 3 XL\0" /* Product Name */ \ 43 | "R0\0" /* Version */ \ 44 | "Serial Not Set\0" /* Serial */ \ 45 | "Base of Chassis\0" /* board location */ \ 46 | "R1\0" /* Version */ \ 47 | "R2\0" /* Version */ 48 | 49 | #define TYPE3_STRINGS \ 50 | "ARM LTD\0" /* Manufacturer */ \ 51 | "None\0" /* Version */ \ 52 | "Serial Not Set\0" /* Serial */ 53 | 54 | #define TYPE4_STRINGS \ 55 | "BGA-1156\0" /* socket type */ \ 56 | "ARM LTD\0" /* manufactuer */ \ 57 | "Cortex-A57\0" /* processor 1 description */ \ 58 | "Cortex-A53\0" /* processor 2 description */ \ 59 | "Cortex-A72\0" /* processor 2 description */ \ 60 | "0xd03\0" /* A53 part number */ \ 61 | "0xd07\0" /* A57 part number */ \ 62 | "0xd08\0" /* A72 part number */ 63 | 64 | #define TYPE7_STRINGS \ 65 | "L1 Instruction\0" /* L1I */ \ 66 | "L1 Data\0" /* L1D */ \ 67 | "L2\0" /* L2 */ 68 | 69 | #define TYPE9_STRINGS \ 70 | "PCIE_SLOT0\0" /* Slot0 */ \ 71 | "PCIE_SLOT1\0" /* Slot1 */ \ 72 | "PCIE_SLOT2\0" /* Slot2 */ \ 73 | "PCIE_SLOT3\0" /* Slot3 */ 74 | 75 | #define TYPE16_STRINGS \ 76 | "\0" /* nothing */ 77 | 78 | #define TYPE17_STRINGS \ 79 | "RIGHT SIDE\0" /* location */ \ 80 | "BANK 0\0" /* bank description */ 81 | 82 | #define TYPE19_STRINGS \ 83 | "\0" /* nothing */ 84 | 85 | #define TYPE32_STRINGS \ 86 | "\0" /* nothing */ 87 | 88 | 89 | // 90 | // Type definition and contents of the default SMBIOS table. 91 | // This table covers only the minimum structures required by 92 | // the SMBIOS specification (section 6.2, version 3.0) 93 | // 94 | #pragma pack(1) 95 | typedef struct { 96 | SMBIOS_TABLE_TYPE0 Base; 97 | INT8 Strings[sizeof(TYPE0_STRINGS)]; 98 | } ARM_TYPE0; 99 | 100 | typedef struct { 101 | SMBIOS_TABLE_TYPE1 Base; 102 | UINT8 Strings[sizeof(TYPE1_STRINGS)]; 103 | } ARM_TYPE1; 104 | 105 | typedef struct { 106 | SMBIOS_TABLE_TYPE2 Base; 107 | UINT8 Strings[sizeof(TYPE2_STRINGS)]; 108 | } ARM_TYPE2; 109 | 110 | typedef struct { 111 | SMBIOS_TABLE_TYPE3 Base; 112 | UINT8 Strings[sizeof(TYPE3_STRINGS)]; 113 | } ARM_TYPE3; 114 | 115 | typedef struct { 116 | SMBIOS_TABLE_TYPE4 Base; 117 | UINT8 Strings[sizeof(TYPE4_STRINGS)]; 118 | } ARM_TYPE4; 119 | 120 | typedef struct { 121 | SMBIOS_TABLE_TYPE7 Base; 122 | UINT8 Strings[sizeof(TYPE7_STRINGS)]; 123 | } ARM_TYPE7; 124 | 125 | typedef struct { 126 | SMBIOS_TABLE_TYPE9 Base; 127 | UINT8 Strings[sizeof(TYPE9_STRINGS)]; 128 | } ARM_TYPE9; 129 | 130 | typedef struct { 131 | SMBIOS_TABLE_TYPE16 Base; 132 | UINT8 Strings[sizeof(TYPE16_STRINGS)]; 133 | } ARM_TYPE16; 134 | 135 | typedef struct { 136 | SMBIOS_TABLE_TYPE17 Base; 137 | UINT8 Strings[sizeof(TYPE17_STRINGS)]; 138 | } ARM_TYPE17; 139 | 140 | typedef struct { 141 | SMBIOS_TABLE_TYPE19 Base; 142 | UINT8 Strings[sizeof(TYPE19_STRINGS)]; 143 | } ARM_TYPE19; 144 | 145 | typedef struct { 146 | SMBIOS_TABLE_TYPE32 Base; 147 | UINT8 Strings[sizeof(TYPE32_STRINGS)]; 148 | } ARM_TYPE32; 149 | 150 | // SMBIOS tables often reference each other using 151 | // fixed constants, define a list of these constants 152 | // for our hardcoded tables 153 | enum SMBIOS_REFRENCE_HANDLES { 154 | SMBIOS_HANDLE_A57_L1I = 0x1000, 155 | SMBIOS_HANDLE_A57_L1D, 156 | SMBIOS_HANDLE_A57_L2, 157 | SMBIOS_HANDLE_A53_L1I, 158 | SMBIOS_HANDLE_A53_L1D, 159 | SMBIOS_HANDLE_A53_L2, 160 | SMBIOS_HANDLE_MOTHERBOARD, 161 | SMBIOS_HANDLE_CHASSIS, 162 | SMBIOS_HANDLE_A72_CLUSTER, 163 | SMBIOS_HANDLE_A57_CLUSTER, 164 | SMBIOS_HANDLE_A53_CLUSTER, 165 | SMBIOS_HANDLE_MEMORY, 166 | SMBIOS_HANDLE_DIMM 167 | }; 168 | 169 | #define SERIAL_LEN 10 //this must be less than the buffer len allocated in the type1 structure 170 | 171 | #pragma pack() 172 | 173 | // BIOS information (section 7.1) 174 | STATIC ARM_TYPE0 mArmDefaultType0 = { 175 | { 176 | { // SMBIOS_STRUCTURE Hdr 177 | EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type 178 | sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length 179 | SMBIOS_HANDLE_PI_RESERVED, 180 | }, 181 | 1, // SMBIOS_TABLE_STRING Vendor 182 | 2, // SMBIOS_TABLE_STRING BiosVersion 183 | 0xE800,// UINT16 BiosSegment 184 | 3, // SMBIOS_TABLE_STRING BiosReleaseDate 185 | 0, // UINT8 BiosSize 186 | { 187 | 0,0,0,0,0,0, 188 | 1, //PCI supported 189 | 0, 190 | 1, //PNP supported 191 | 0, 192 | 1, //BIOS upgradable 193 | 0, 0, 0, 194 | 1, //Boot from CD 195 | 1, //selectable boot 196 | }, // MISC_BIOS_CHARACTERISTICS BiosCharacteristics 197 | { // BIOSCharacteristicsExtensionBytes[2] 198 | 0x3, 199 | 0xC, 200 | }, 201 | 0, // UINT8 SystemBiosMajorRelease 202 | 0, // UINT8 SystemBiosMinorRelease 203 | 0xFF, // UINT8 EmbeddedControllerFirmwareMajorRelease 204 | 0xFF // UINT8 EmbeddedControllerFirmwareMinorRelease 205 | }, 206 | // Text strings (unformatted area) 207 | TYPE0_STRINGS 208 | }; 209 | 210 | // System information (section 7.2) 211 | STATIC CONST ARM_TYPE1 mArmDefaultType1 = { 212 | { 213 | { // SMBIOS_STRUCTURE Hdr 214 | EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, 215 | sizeof(SMBIOS_TABLE_TYPE1), 216 | SMBIOS_HANDLE_PI_RESERVED, 217 | }, 218 | 1, //Manufacturer 219 | 2, //Product Name 220 | 3, //Version 221 | 4, //Serial 222 | { 0x8a95d198, 0x7f46, 0x11e5, { 0xbf,0x8b,0x08,0x00,0x27,0x04,0xd4,0x8e }}, //UUID 223 | 6, //Wakeup type 224 | 0, //SKU 225 | 0, //Family 226 | }, 227 | // Text strings (unformatted) 228 | TYPE1_STRINGS 229 | }; 230 | 231 | // Baseboard (section 7.3) 232 | STATIC ARM_TYPE2 mArmDefaultType2 = { 233 | { 234 | { // SMBIOS_STRUCTURE Hdr 235 | EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type 236 | sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length 237 | SMBIOS_HANDLE_MOTHERBOARD, 238 | }, 239 | 1, //Manufacturer 240 | 2, //Product Name 241 | 3, //Version 242 | 4, //Serial 243 | 0, //Asset tag 244 | {1}, //motherboard, not replaceable 245 | 5, //location of board 246 | SMBIOS_HANDLE_CHASSIS, 247 | BaseBoardTypeMotherBoard, 248 | 1, 249 | {SMBIOS_HANDLE_A53_CLUSTER}, //,SMBIOS_HANDLE_A53_CLUSTER,SMBIOS_HANDLE_MEMORY}, 250 | }, 251 | TYPE2_STRINGS 252 | }; 253 | 254 | // Enclosure 255 | STATIC CONST ARM_TYPE3 mArmDefaultType3 = { 256 | { 257 | { // SMBIOS_STRUCTURE Hdr 258 | EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type 259 | sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length 260 | SMBIOS_HANDLE_CHASSIS, 261 | }, 262 | 1, //Manufacturer 263 | 4, //enclosure type (low profile desktop) 264 | 2, //version 265 | 3, //serial 266 | 0, //asset tag 267 | ChassisStateUnknown, //boot chassis state 268 | ChassisStateSafe, //power supply state 269 | ChassisStateSafe, //thermal state 270 | ChassisSecurityStatusNone, //security state 271 | {0,0,0,0,}, //OEM defined 272 | 1, //1U height 273 | 1, //number of power cords 274 | 0, //no contained elements 275 | }, 276 | TYPE3_STRINGS 277 | }; 278 | 279 | // Processor 280 | STATIC CONST ARM_TYPE4 mArmDefaultType4_a72 = { 281 | { 282 | { // SMBIOS_STRUCTURE Hdr 283 | EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type 284 | sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length 285 | SMBIOS_HANDLE_A72_CLUSTER, 286 | }, 287 | 1, //socket type 288 | 3, //processor type CPU 289 | ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2 290 | 2, //manufactuer 291 | {{0,},{0.}}, //processor id 292 | 5, //version 293 | {0,0,0,0,0,1}, //voltage 294 | 0, //external clock 295 | 1200, //max speed 296 | 1200, //current speed 297 | 0x41, //status 298 | ProcessorUpgradeOther, 299 | SMBIOS_HANDLE_A57_L1I, //l1 cache handle 300 | SMBIOS_HANDLE_A57_L2, //l2 cache handle 301 | 0xFFFF, //l3 cache handle 302 | 0, //serial not set 303 | 0, //asset not set 304 | 8, //part number 305 | 2, //core count in socket 306 | 2, //enabled core count in socket 307 | 0, //threads per socket 308 | 0xEC, // processor characteristics 309 | ProcessorFamilyARM, //ARM core 310 | }, 311 | TYPE4_STRINGS 312 | }; 313 | 314 | STATIC CONST ARM_TYPE4 mArmDefaultType4_a57 = { 315 | { 316 | { // SMBIOS_STRUCTURE Hdr 317 | EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type 318 | sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length 319 | SMBIOS_HANDLE_A57_CLUSTER, 320 | }, 321 | 1, //socket type 322 | 3, //processor type CPU 323 | ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2 324 | 2, //manufactuer 325 | {{0,},{0.}}, //processor id 326 | 3, //version 327 | {0,0,0,0,0,1}, //voltage 328 | 0, //external clock 329 | 1200, //max speed 330 | 1200, //current speed 331 | 0x41, //status 332 | ProcessorUpgradeOther, 333 | SMBIOS_HANDLE_A57_L1I, //l1 cache handle 334 | SMBIOS_HANDLE_A57_L2, //l2 cache handle 335 | 0xFFFF, //l3 cache handle 336 | 0, //serial not set 337 | 0, //asset not set 338 | 7, //part number 339 | 2, //core count in socket 340 | 2, //enabled core count in socket 341 | 0, //threads per socket 342 | 0xEC, // processor characteristics 343 | ProcessorFamilyARM, //ARM core 344 | }, 345 | TYPE4_STRINGS 346 | }; 347 | 348 | STATIC CONST ARM_TYPE4 mArmDefaultType4_a53 = { 349 | { 350 | { // SMBIOS_STRUCTURE Hdr 351 | EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type 352 | sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length 353 | SMBIOS_HANDLE_A53_CLUSTER, 354 | }, 355 | 1, //socket type 356 | 3, //processor type CPU 357 | ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2 358 | 2, //manufactuer 359 | {{0,},{0.}}, //processor id 360 | 4, //version 361 | {0,0,0,0,0,1}, //voltage 362 | 0, //external clock 363 | 650, //max speed 364 | 650, //current speed 365 | 0x41, //status 366 | ProcessorUpgradeOther, 367 | SMBIOS_HANDLE_A53_L1I, //l1 cache handle 368 | SMBIOS_HANDLE_A53_L2, //l2 cache handle 369 | 0xFFFF, //l3 cache handle 370 | 0, //serial not set 371 | 0, //asset not set 372 | 6, //part number 373 | 4, //core count in socket 374 | 4, //enabled core count in socket 375 | 0, //threads per socket 376 | 0xEC, // processor characteristics 377 | ProcessorFamilyARM, //ARM core 378 | }, 379 | TYPE4_STRINGS 380 | }; 381 | 382 | // Cache 383 | STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1i = { 384 | { 385 | { // SMBIOS_STRUCTURE Hdr 386 | EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type 387 | sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length 388 | SMBIOS_HANDLE_A57_L1I, 389 | }, 390 | 1, 391 | 0x380, //L1 enabled, unknown WB 392 | 48, //48k i cache max 393 | 48, //48k installed 394 | {0,1}, //SRAM type 395 | {0,1}, //SRAM type 396 | 0, //unkown speed 397 | CacheErrorParity, //parity checking 398 | CacheTypeInstruction, //instruction cache 399 | CacheAssociativityOther, //three way 400 | }, 401 | TYPE7_STRINGS 402 | }; 403 | 404 | STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1i = { 405 | { 406 | { // SMBIOS_STRUCTURE Hdr 407 | EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type 408 | sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length 409 | SMBIOS_HANDLE_A53_L1I, 410 | }, 411 | 1, 412 | 0x380, //L1 enabled, unknown WB 413 | 32, //32k i cache max 414 | 32, //32k installed 415 | {0,1}, //SRAM type 416 | {0,1}, //SRAM type 417 | 0, //unkown speed 418 | CacheErrorParity, //parity checking 419 | CacheTypeInstruction, //instruction cache 420 | CacheAssociativity2Way, //two way 421 | }, 422 | TYPE7_STRINGS 423 | }; 424 | 425 | STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1d = { 426 | { 427 | { // SMBIOS_STRUCTURE Hdr 428 | EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type 429 | sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length 430 | SMBIOS_HANDLE_A57_L1D, 431 | }, 432 | 2, 433 | 0x180, //L1 enabled, WB 434 | 32, //32k d cache max 435 | 32, //32k installed 436 | {0,1}, //SRAM type 437 | {0,1}, //SRAM type 438 | 0, //unkown speed 439 | CacheErrorSingleBit, //ECC checking 440 | CacheTypeData, //instruction cache 441 | CacheAssociativity2Way, //two way associative 442 | }, 443 | TYPE7_STRINGS 444 | }; 445 | 446 | STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1d = { 447 | { 448 | { // SMBIOS_STRUCTURE Hdr 449 | EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type 450 | sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length 451 | SMBIOS_HANDLE_A53_L1D, 452 | }, 453 | 2, 454 | 0x180, //L1 enabled, WB 455 | 32, //32k d cache max 456 | 32, //32k installed 457 | {0,1}, //SRAM type 458 | {0,1}, //SRAM type 459 | 0, //unkown speed 460 | CacheErrorSingleBit, //ECC checking 461 | CacheTypeData, //instruction cache 462 | CacheAssociativity4Way, //four way associative 463 | }, 464 | TYPE7_STRINGS 465 | }; 466 | 467 | STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l2 = { 468 | { 469 | { // SMBIOS_STRUCTURE Hdr 470 | EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type 471 | sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length 472 | SMBIOS_HANDLE_A57_L2, 473 | }, 474 | 3, 475 | 0x181, //L2 enabled, WB 476 | 2048, //2M d cache max 477 | 2048, //2M installed 478 | {0,1}, //SRAM type 479 | {0,1}, //SRAM type 480 | 0, //unkown speed 481 | CacheErrorSingleBit, //ECC checking 482 | CacheTypeUnified, //instruction cache 483 | CacheAssociativity16Way, //16 way associative 484 | }, 485 | TYPE7_STRINGS 486 | }; 487 | 488 | STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l2 = { 489 | { 490 | { // SMBIOS_STRUCTURE Hdr 491 | EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type 492 | sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length 493 | SMBIOS_HANDLE_A53_L2, 494 | }, 495 | 3, 496 | 0x181, //L2 enabled, WB 497 | 1024, //1M D cache max 498 | 1024, //1M installed 499 | {0,1}, //SRAM type 500 | {0,1}, //SRAM type 501 | 0, //unkown speed 502 | CacheErrorSingleBit, //ECC checking 503 | CacheTypeUnified, //instruction cache 504 | CacheAssociativity16Way, //16 way associative 505 | }, 506 | TYPE7_STRINGS 507 | }; 508 | 509 | // Slots 510 | STATIC CONST ARM_TYPE9 mArmDefaultType9_0 = { 511 | { 512 | { // SMBIOS_STRUCTURE Hdr 513 | EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type 514 | sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length 515 | SMBIOS_HANDLE_PI_RESERVED, 516 | }, 517 | 1, //slot 0 518 | SlotTypePciExpressGen2X4, 519 | SlotDataBusWidth1X, 520 | SlotUsageUnknown, 521 | SlotLengthShort, 522 | 0, 523 | {1}, //unknown 524 | {1,0,1}, //PME and SMBUS 525 | 0, 526 | 2, 527 | 1, 528 | }, 529 | TYPE9_STRINGS 530 | }; 531 | 532 | STATIC CONST ARM_TYPE9 mArmDefaultType9_1 = { 533 | { 534 | { // SMBIOS_STRUCTURE Hdr 535 | EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type 536 | sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length 537 | SMBIOS_HANDLE_PI_RESERVED, 538 | }, 539 | 1, //slot 0 540 | SlotTypePciExpressGen2X4, 541 | SlotDataBusWidth1X, 542 | SlotUsageUnknown, 543 | SlotLengthShort, 544 | 0, 545 | {1}, 546 | {1,0,1}, //PME and SMBUS 547 | 0, 548 | 2, 549 | 2, 550 | }, 551 | TYPE9_STRINGS 552 | }; 553 | 554 | STATIC CONST ARM_TYPE9 mArmDefaultType9_2 = { 555 | { 556 | { // SMBIOS_STRUCTURE Hdr 557 | EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type 558 | sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length 559 | SMBIOS_HANDLE_PI_RESERVED, 560 | }, 561 | 1, //slot 0 562 | SlotTypePciExpressGen2X8, 563 | SlotDataBusWidth4X, 564 | SlotUsageUnknown, 565 | SlotLengthShort, 566 | 0, 567 | {1}, 568 | {1,0,1}, //PME and SMBUS 569 | 0, 570 | 2, 571 | 3, 572 | }, 573 | TYPE9_STRINGS 574 | }; 575 | 576 | STATIC CONST ARM_TYPE9 mArmDefaultType9_3 = { 577 | { 578 | { // SMBIOS_STRUCTURE Hdr 579 | EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type 580 | sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length 581 | SMBIOS_HANDLE_PI_RESERVED, 582 | }, 583 | 1, //slot 0 584 | SlotTypePciExpressGen2X16, 585 | SlotDataBusWidth4X, 586 | SlotUsageUnknown, 587 | SlotLengthShort, 588 | 0, 589 | {1}, 590 | {1,0,1}, //PME and SMBUS 591 | 0, 592 | 2, 593 | 0xc, 594 | }, 595 | TYPE9_STRINGS 596 | }; 597 | 598 | // Memory array 599 | STATIC CONST ARM_TYPE16 mArmDefaultType16 = { 600 | { 601 | { // SMBIOS_STRUCTURE Hdr 602 | EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type 603 | sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length 604 | SMBIOS_HANDLE_MEMORY, 605 | }, 606 | MemoryArrayLocationSystemBoard, //on motherboard 607 | MemoryArrayUseSystemMemory, //system RAM 608 | MemoryErrorCorrectionNone, //Juno doesn't have ECC RAM 609 | 0x800000, //8GB 610 | 0xFFFE, //No error information structure 611 | 0x1, //soldered memory 612 | }, 613 | TYPE16_STRINGS 614 | }; 615 | 616 | // Memory device 617 | STATIC CONST ARM_TYPE17 mArmDefaultType17 = { 618 | { 619 | { // SMBIOS_STRUCTURE Hdr 620 | EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type 621 | sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length 622 | SMBIOS_HANDLE_DIMM, 623 | }, 624 | SMBIOS_HANDLE_MEMORY, //array to which this module belongs 625 | 0xFFFE, //no errors 626 | 64, //single DIMM, no ECC is 64bits (for ecc this would be 72) 627 | 64, //data width of this device (64-bits) 628 | 0x2000, //8GB 629 | 0x0B, //row of chips 630 | 0, //not part of a set 631 | 1, //right side of board 632 | 2, //bank 0 633 | // MemoryTypeLpddr3, //LP DDR3, isn't defined yet 634 | MemoryTypeDdr3, //LP DDR3 635 | {0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, //unbuffered 636 | 1600, //1600Mhz DDR 637 | 0, //varies between diffrent production runs 638 | 0, //serial 639 | 0, //asset tag 640 | 0, //part number 641 | 0, //rank 642 | }, 643 | TYPE17_STRINGS 644 | }; 645 | 646 | // Memory array mapped address, this structure 647 | // is overridden by InstallMemoryStructure 648 | STATIC CONST ARM_TYPE19 mArmDefaultType19 = { 649 | { 650 | { // SMBIOS_STRUCTURE Hdr 651 | EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type 652 | sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length 653 | SMBIOS_HANDLE_PI_RESERVED, 654 | }, 655 | 0xFFFFFFFF, //invalid, look at extended addr field 656 | 0xFFFFFFFF, 657 | SMBIOS_HANDLE_DIMM, //handle 658 | 1, 659 | 0x080000000, //starting addr of first 2GB 660 | 0x100000000, //ending addr of first 2GB 661 | }, 662 | TYPE19_STRINGS 663 | }; 664 | 665 | // System boot info 666 | STATIC CONST ARM_TYPE32 mArmDefaultType32 = { 667 | { 668 | { // SMBIOS_STRUCTURE Hdr 669 | EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type 670 | sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length 671 | SMBIOS_HANDLE_PI_RESERVED, 672 | }, 673 | {0,0,0,0,0,0}, //reserved 674 | BootInformationStatusNoError, 675 | }, 676 | TYPE32_STRINGS 677 | }; 678 | 679 | STATIC CONST VOID *DefaultCommonTables[]= 680 | { 681 | &mArmDefaultType0, 682 | &mArmDefaultType1, 683 | &mArmDefaultType2, 684 | &mArmDefaultType3, 685 | &mArmDefaultType7_a53_l1i, 686 | &mArmDefaultType7_a53_l1d, 687 | &mArmDefaultType7_a53_l2, 688 | &mArmDefaultType4_a53, 689 | &mArmDefaultType9_0, 690 | &mArmDefaultType9_1, 691 | &mArmDefaultType9_2, 692 | &mArmDefaultType9_3, 693 | &mArmDefaultType16, 694 | &mArmDefaultType17, 695 | // &mArmDefaultType19, //memory range type 19 dynamically generated 696 | &mArmDefaultType32, 697 | NULL 698 | }; 699 | 700 | STATIC CONST VOID *DefaultTablesR0R1[]= 701 | { 702 | &mArmDefaultType7_a57_l1i, 703 | &mArmDefaultType7_a57_l1d, 704 | &mArmDefaultType7_a57_l2, 705 | &mArmDefaultType4_a57, 706 | NULL 707 | }; 708 | 709 | /* 710 | 711 | STATIC CONST VOID *DefaultTablesR2[]= 712 | { 713 | &mArmDefaultType7_a57_l1i, // Cache layout is the same on the A72 vs A57 714 | &mArmDefaultType7_a57_l1d, 715 | &mArmDefaultType7_a57_l2, 716 | &mArmDefaultType4_a72, 717 | NULL 718 | }; 719 | 720 | */ 721 | 722 | /** 723 | Installs a memory descriptor (type19) for the given address range 724 | 725 | @param Smbios SMBIOS protocol 726 | 727 | **/ 728 | EFI_STATUS 729 | InstallMemoryStructure ( 730 | IN EFI_SMBIOS_PROTOCOL *Smbios, 731 | IN UINT64 StartingAddress, 732 | IN UINT64 RegionLength 733 | ) 734 | { 735 | EFI_SMBIOS_HANDLE SmbiosHandle; 736 | ARM_TYPE19 MemoryDescriptor; 737 | EFI_STATUS Status = EFI_SUCCESS; 738 | 739 | CopyMem( &MemoryDescriptor, &mArmDefaultType19, sizeof(ARM_TYPE19)); 740 | 741 | MemoryDescriptor.Base.ExtendedStartingAddress = StartingAddress; 742 | MemoryDescriptor.Base.ExtendedEndingAddress = StartingAddress+RegionLength; 743 | SmbiosHandle = MemoryDescriptor.Base.Hdr.Handle; 744 | 745 | Status = Smbios->Add ( 746 | Smbios, 747 | NULL, 748 | &SmbiosHandle, 749 | (EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor 750 | ); 751 | return Status; 752 | } 753 | 754 | /** 755 | Install a whole table worth of structructures 756 | 757 | @parm 758 | **/ 759 | EFI_STATUS 760 | InstallStructures ( 761 | IN EFI_SMBIOS_PROTOCOL *Smbios, 762 | IN CONST VOID *DefaultTables[] 763 | ) 764 | { 765 | EFI_STATUS Status = EFI_SUCCESS; 766 | EFI_SMBIOS_HANDLE SmbiosHandle; 767 | 768 | int TableEntry; 769 | for ( TableEntry=0; DefaultTables[TableEntry] != NULL; TableEntry++) 770 | { 771 | SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER*)DefaultTables[TableEntry])->Handle; 772 | Status = Smbios->Add ( 773 | Smbios, 774 | NULL, 775 | &SmbiosHandle, 776 | (EFI_SMBIOS_TABLE_HEADER*) DefaultTables[TableEntry] 777 | ); 778 | if (EFI_ERROR(Status)) 779 | break; 780 | } 781 | return Status; 782 | } 783 | 784 | 785 | /** 786 | Install all structures from the DefaultTables structure 787 | 788 | @param Smbios SMBIOS protocol 789 | 790 | **/ 791 | EFI_STATUS 792 | InstallAllStructures ( 793 | IN EFI_SMBIOS_PROTOCOL *Smbios 794 | ) 795 | { 796 | EFI_STATUS Status = EFI_SUCCESS; 797 | VOID *ExtraTables = DefaultTablesR0R1; 798 | 799 | // 800 | // Add all Juno table entries 801 | // 802 | Status=InstallStructures (Smbios,DefaultCommonTables); 803 | ASSERT_EFI_ERROR (Status); 804 | 805 | Status=InstallStructures (Smbios,ExtraTables); 806 | ASSERT_EFI_ERROR (Status); 807 | 808 | // Generate memory descriptors for the two memory ranges we know about 809 | Status = InstallMemoryStructure ( Smbios, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemorySize)); 810 | ASSERT_EFI_ERROR (Status); 811 | 812 | return Status; 813 | } 814 | 815 | /** 816 | Installs SMBIOS information for ARM platforms 817 | 818 | @param ImageHandle Module's image handle 819 | @param SystemTable Pointer of EFI_SYSTEM_TABLE 820 | 821 | @retval EFI_SUCCESS Smbios data successfully installed 822 | @retval Other Smbios data was not installed 823 | 824 | **/ 825 | EFI_STATUS 826 | EFIAPI 827 | SmbiosTablePublishEntry ( 828 | IN EFI_HANDLE ImageHandle, 829 | IN EFI_SYSTEM_TABLE *SystemTable 830 | ) 831 | { 832 | EFI_STATUS Status; 833 | EFI_SMBIOS_PROTOCOL *Smbios; 834 | 835 | // 836 | // Find the SMBIOS protocol 837 | // 838 | Status = gBS->LocateProtocol ( 839 | &gEfiSmbiosProtocolGuid, 840 | NULL, 841 | (VOID**)&Smbios 842 | ); 843 | if (EFI_ERROR (Status)) { 844 | return Status; 845 | } 846 | 847 | Status = InstallAllStructures (Smbios); 848 | 849 | return Status; 850 | } 851 | --------------------------------------------------------------------------------