├── testcase ├── 1-3 │ ├── dmem.txt │ ├── imem.txt │ ├── README.md │ ├── README_EN.md │ ├── RFresult_ans.txt │ └── stateresult_ans.txt ├── 1-4 │ ├── dmem.txt │ ├── imem.txt │ ├── README.md │ ├── README_EN.md │ ├── RFresult_ans.txt │ └── stateresult_ans.txt ├── 3-3 │ ├── README.md │ ├── README_EN.md │ ├── dmem.txt │ ├── imem.txt │ ├── RFresult_ans.txt │ └── stateresult_ans.txt ├── 3-4 │ ├── README.md │ ├── README_EN.md │ ├── dmem.txt │ ├── imem.txt │ └── RFresult_ans.txt ├── 3-2 │ ├── README.md │ ├── README_EN.md │ ├── dmem.txt │ ├── imem.txt │ ├── RFresult_ans.txt │ └── stateresult_ans.txt ├── 0-1 │ ├── dmem.txt │ ├── README.md │ ├── README_EN.md │ ├── imem.txt │ ├── RFresult_ans.txt │ ├── stateresult_ans.txt │ └── dmemresult_ans.txt ├── 0-2 │ ├── dmem.txt │ ├── README.md │ ├── README_EN.md │ ├── imem.txt │ ├── RFresult_ans.txt │ ├── stateresult_ans.txt │ └── dmemresult_ans.txt ├── 1-1 │ ├── dmem.txt │ ├── README.md │ ├── imem.txt │ ├── README_EN.md │ ├── RFresult_ans.txt │ ├── stateresult_ans.txt │ └── dmemresult_ans.txt ├── 1-2 │ ├── dmem.txt │ ├── README.md │ ├── README_EN.md │ ├── imem.txt │ ├── RFresult_ans.txt │ ├── stateresult_ans.txt │ └── dmemresult_ans.txt ├── 1-6 │ ├── dmem.txt │ ├── imem.txt │ ├── README.md │ ├── README_EN.md │ ├── RFresult_ans.txt │ └── stateresult_ans.txt ├── 2-1 │ ├── dmem.txt │ ├── README.md │ ├── README_EN.md │ ├── imem.txt │ ├── RFresult_ans.txt │ └── stateresult_ans.txt ├── 3-1 │ ├── README.md │ ├── dmem.txt │ ├── README_EN.md │ ├── imem.txt │ ├── RFresult_ans.txt │ └── stateresult_ans.txt ├── 1-5 │ ├── dmem.txt │ ├── README.md │ ├── README_EN.md │ ├── imem.txt │ ├── RFresult_ans.txt │ └── stateresult_ans.txt ├── Makefile ├── 2-2 │ ├── dmem.txt │ ├── README.md │ ├── README_EN.md │ ├── imem.txt │ └── RFresult_ans.txt ├── README.md ├── test.sh └── README_EN.md ├── .gitattributes ├── assembler ├── README.md ├── README_EN.md ├── main.go └── assembler │ ├── assemble.go │ └── assemble_line.go ├── README_EN.md └── README.md /testcase/1-3/dmem.txt: -------------------------------------------------------------------------------- 1 | 11000000 2 | 00110000 3 | 00001100 4 | 00000011 -------------------------------------------------------------------------------- /testcase/1-4/dmem.txt: -------------------------------------------------------------------------------- 1 | 11000000 2 | 00110000 3 | 00001100 4 | 00000011 -------------------------------------------------------------------------------- /testcase/3-3/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 3-3 2 | 3 | testbench_hazards 4 | -------------------------------------------------------------------------------- /testcase/3-4/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 3-3 2 | 3 | testbench_hazards_beq 4 | -------------------------------------------------------------------------------- /testcase/3-2/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 3-2 2 | 3 | testbench_hazards_no_stall 4 | -------------------------------------------------------------------------------- /testcase/3-3/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 3-3 2 | 3 | testbench_hazards 4 | -------------------------------------------------------------------------------- /testcase/3-4/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 3-3 2 | 3 | testbench_hazards_beq 4 | -------------------------------------------------------------------------------- /testcase/3-2/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 3-2 2 | 3 | testbench_hazards_no_stall 4 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | -------------------------------------------------------------------------------- /testcase/0-1/dmem.txt: -------------------------------------------------------------------------------- 1 | 11111111 2 | 11111111 3 | 11111111 4 | 11111111 5 | 01111111 6 | 11111111 7 | 11111111 8 | 11111110 -------------------------------------------------------------------------------- /testcase/0-2/dmem.txt: -------------------------------------------------------------------------------- 1 | 11111111 2 | 11111111 3 | 11111111 4 | 11111111 5 | 01111111 6 | 11111111 7 | 11111111 8 | 11111110 -------------------------------------------------------------------------------- /testcase/1-1/dmem.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000001 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000010 -------------------------------------------------------------------------------- /testcase/1-2/dmem.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000001 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000010 -------------------------------------------------------------------------------- /testcase/1-6/dmem.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00001000 5 | 11000000 6 | 00110000 7 | 00001100 8 | 00000011 -------------------------------------------------------------------------------- /testcase/2-1/dmem.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000001 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000010 -------------------------------------------------------------------------------- /testcase/3-1/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 3-1 2 | 3 | Code-2018.zip 中的 Testbenches1 4 | 5 | **WARNING**: 原答案中的dmemresult有错误, 在此已经进行了修改 -------------------------------------------------------------------------------- /testcase/3-1/dmem.txt: -------------------------------------------------------------------------------- 1 | 11111111 2 | 11111111 3 | 11111111 4 | 11111111 5 | 01111111 6 | 11111111 7 | 11111111 8 | 11111110 -------------------------------------------------------------------------------- /testcase/3-2/dmem.txt: -------------------------------------------------------------------------------- 1 | 11111111 2 | 11111111 3 | 11111111 4 | 11111111 5 | 01111111 6 | 11111111 7 | 11111111 8 | 11111110 -------------------------------------------------------------------------------- /testcase/3-3/dmem.txt: -------------------------------------------------------------------------------- 1 | 11111111 2 | 11111111 3 | 11111111 4 | 11111111 5 | 01111111 6 | 11111111 7 | 11111111 8 | 11111110 -------------------------------------------------------------------------------- /testcase/3-1/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 3-1 2 | 3 | Testbenches1 in Code-2018.zip 4 | 5 | **WARNING**: the dmemresult in the origin answer has mistakes, and has been modified here -------------------------------------------------------------------------------- /testcase/1-3/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10101100 6 | 00000001 7 | 00000000 8 | 00000100 9 | 11111111 10 | 11111111 11 | 11111111 12 | 11111111 -------------------------------------------------------------------------------- /testcase/1-4/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00100001 7 | 00010000 8 | 00100001 9 | 11111111 10 | 11111111 11 | 11111111 12 | 11111111 -------------------------------------------------------------------------------- /testcase/1-5/dmem.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000001 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000010 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000100 -------------------------------------------------------------------------------- /testcase/3-4/dmem.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000011 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000001 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 -------------------------------------------------------------------------------- /testcase/Makefile: -------------------------------------------------------------------------------- 1 | MIPS_pipeline: 2 | c++ -O3 MIPS_pipeline.cpp -o MIPS_pipeline 3 | 4 | clean: 5 | rm MIPS_pipeline 6 | 7 | test: 8 | ./test.sh $(case) 9 | 10 | .PHONY: all test clean 11 | -------------------------------------------------------------------------------- /testcase/1-6/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00100010 7 | 11111111 8 | 11111100 9 | 10101100 10 | 00000010 11 | 00000000 12 | 00001000 13 | 11111111 14 | 11111111 15 | 11111111 16 | 11111111 -------------------------------------------------------------------------------- /testcase/2-2/dmem.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00010000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000100 9 | 00000000 10 | 00000000 11 | 00000000 12 | 01010000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000001 17 | -------------------------------------------------------------------------------- /assembler/README.md: -------------------------------------------------------------------------------- 1 | # assembler 2 | 3 | assembler是一个将ARM汇编语言翻译为机器码的汇编器 4 | 5 | 目前支持的指令有ADDU, SUBU, LW, SW, BEQ, HALT 6 | 7 | ### 网页版 8 | 9 | 由此链接进入网页版: [Assembler](https://va.poncirus.site/assembler) 10 | 11 | ### 手动运行 12 | 13 | 修改main函数中的ins为要翻译的ARM汇编语言，执行后会输出对应的机器码 -------------------------------------------------------------------------------- /testcase/1-6/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 1-6 2 | #### 包含的指令 3 | - [ ] ADDU 4 | - [ ] SUBU 5 | - [x] LW 6 | - [x] SW 7 | - [ ] BEQ 8 | 9 | #### 采分点 10 | - [x] RAW hazards 11 | - [ ] BEQ 12 | 13 | #### 汇编指令 14 | ``` 15 | LW R1, R0, 0 16 | LW R2, R1, -4 17 | SW R2, R0, 8 18 | HALT 19 | ``` -------------------------------------------------------------------------------- /testcase/1-4/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 1-4 2 | 3 | 这个测试用例针对 stall 设计 4 | 5 | #### 包含的指令 6 | - [x] ADDU 7 | - [ ] SUBU 8 | - [x] LW 9 | - [ ] SW 10 | - [ ] BEQ 11 | 12 | #### 采分点 13 | - [x] RAW hazards 14 | - [ ] BEQ 15 | 16 | #### 汇编指令 17 | ``` 18 | LW R1, R0, 0 19 | ADDU R2, R1, R1 20 | HALT 21 | ``` -------------------------------------------------------------------------------- /testcase/1-3/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 1-3 2 | 3 | 这个测试用例针对 MEM-MEM Forwarding 设计 4 | 5 | #### 包含的指令 6 | - [ ] ADDU 7 | - [ ] SUBU 8 | - [x] LW 9 | - [x] SW 10 | - [ ] BEQ 11 | 12 | #### 采分点 13 | - [x] RAW hazards 14 | - [ ] BEQ 15 | 16 | #### 汇编指令 17 | ``` 18 | LW R1, R0, 0 19 | SW R1, R0, 4 20 | HALT 21 | ``` -------------------------------------------------------------------------------- /testcase/1-6/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 1-6 2 | #### Instruction 3 | - [ ] ADDU 4 | - [ ] SUBU 5 | - [x] LW 6 | - [x] SW 7 | - [ ] BEQ 8 | 9 | #### Grading scheme 10 | - [x] RAW hazards 11 | - [ ] BEQ 12 | 13 | #### Assembly 14 | ``` 15 | LW R1, R0, 0 16 | LW R2, R1, -4 17 | SW R2, R0, 8 18 | HALT 19 | ``` -------------------------------------------------------------------------------- /testcase/1-4/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 1-4 2 | 3 | This testcase is designed for stalling 4 | 5 | #### Instruction 6 | - [x] ADDU 7 | - [ ] SUBU 8 | - [x] LW 9 | - [ ] SW 10 | - [ ] BEQ 11 | 12 | #### Grading scheme 13 | - [x] RAW hazards 14 | - [ ] BEQ 15 | 16 | #### Assembly 17 | ``` 18 | LW R1, R0, 0 19 | ADDU R2, R1, R1 20 | HALT 21 | ``` -------------------------------------------------------------------------------- /testcase/1-3/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 1-3 2 | 3 | This testcase is designed for MEM-MEM forwarding 4 | 5 | #### Instruction 6 | - [ ] ADDU 7 | - [ ] SUBU 8 | - [x] LW 9 | - [x] SW 10 | - [ ] BEQ 11 | 12 | #### Grading scheme 13 | - [x] RAW hazards 14 | - [ ] BEQ 15 | 16 | #### Assembly 17 | ``` 18 | LW R1, R0, 0 19 | SW R1, R0, 4 20 | HALT 21 | ``` -------------------------------------------------------------------------------- /testcase/2-1/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 2-1 2 | 3 | #### 包含的指令 4 | - [x] ADDU 5 | - [x] SUBU 6 | - [x] LW 7 | - [ ] SW 8 | - [x] BEQ 9 | 10 | #### 采分点 11 | - [ ] RAW hazards 12 | - [x] BEQ 13 | 14 | #### 汇编指令 15 | ``` 16 | LW R1, R0, 0 17 | LW R2, R0, 4 18 | ADDU R4, R5, R6 19 | ADDU R4, R5, R6 20 | BEQ R2, R1, 1 21 | SUBU R4, R2, R1 22 | ADDU R5, R2, R1 23 | HALT 24 | ``` -------------------------------------------------------------------------------- /testcase/0-1/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 0-1 2 | #### 包含的指令 3 | - [x] ADDU 4 | - [ ] SUBU 5 | - [x] LW 6 | - [x] SW 7 | - [ ] BEQ 8 | 9 | #### 采分点 10 | - [ ] RAW hazards 11 | - [ ] BEQ 12 | 13 | #### 汇编指令 14 | ``` 15 | LW R1, R0, 0 16 | LW R2, R0, 4 17 | ADDU R7, R8, r9 18 | ADDU R7, R8, r9 19 | ADDU R3, R1, R2 20 | ADDU R7, R8, r9 21 | ADDU R7, R8, r9 22 | SW R3, R0, 8 23 | HALT 24 | ``` -------------------------------------------------------------------------------- /testcase/0-2/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 0-2 2 | #### 包含的指令 3 | - [ ] ADDU 4 | - [x] SUBU 5 | - [x] LW 6 | - [x] SW 7 | - [ ] BEQ 8 | 9 | #### 采分点 10 | - [ ] RAW hazards 11 | - [ ] BEQ 12 | 13 | #### 汇编指令 14 | ``` 15 | LW R1, R0, 0 16 | LW R2, R0, 4 17 | ADDU R7, R8, r9 18 | ADDU R7, R8, r9 19 | SUBU R3, R1, R2 20 | ADDU R7, R8, r9 21 | ADDU R7, R8, r9 22 | SW R3, R0, 8 23 | HALT 24 | ``` -------------------------------------------------------------------------------- /testcase/2-1/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 2-1 2 | 3 | #### Instruction 4 | - [x] ADDU 5 | - [x] SUBU 6 | - [x] LW 7 | - [ ] SW 8 | - [x] BEQ 9 | 10 | #### Grading scheme 11 | - [ ] RAW hazards 12 | - [x] BEQ 13 | 14 | #### Assembly 15 | ``` 16 | LW R1, R0, 0 17 | LW R2, R0, 4 18 | ADDU R4, R5, R6 19 | ADDU R4, R5, R6 20 | BEQ R2, R1, 1 21 | SUBU R4, R2, R1 22 | ADDU R5, R2, R1 23 | HALT 24 | ``` -------------------------------------------------------------------------------- /testcase/0-1/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 0-1 2 | #### Instruction 3 | - [x] ADDU 4 | - [ ] SUBU 5 | - [x] LW 6 | - [x] SW 7 | - [ ] BEQ 8 | 9 | #### Grading scheme 10 | - [ ] RAW hazards 11 | - [ ] BEQ 12 | 13 | #### Assembly 14 | ``` 15 | LW R1, R0, 0 16 | LW R2, R0, 4 17 | ADDU R7, R8, r9 18 | ADDU R7, R8, r9 19 | ADDU R3, R1, R2 20 | ADDU R7, R8, r9 21 | ADDU R7, R8, r9 22 | SW R3, R0, 8 23 | HALT 24 | ``` -------------------------------------------------------------------------------- /testcase/0-2/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 0-2 2 | #### Instruction 3 | - [ ] ADDU 4 | - [x] SUBU 5 | - [x] LW 6 | - [x] SW 7 | - [ ] BEQ 8 | 9 | #### Grading scheme 10 | - [ ] RAW hazards 11 | - [ ] BEQ 12 | 13 | #### Assembly 14 | ``` 15 | LW R1, R0, 0 16 | LW R2, R0, 4 17 | ADDU R7, R8, r9 18 | ADDU R7, R8, r9 19 | SUBU R3, R1, R2 20 | ADDU R7, R8, r9 21 | ADDU R7, R8, r9 22 | SW R3, R0, 8 23 | HALT 24 | ``` -------------------------------------------------------------------------------- /testcase/1-1/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 1-1 2 | 3 | 这个测试用例针对 EX-EX Forwarding 设计 4 | 5 | #### 包含的指令 6 | - [x] ADDU 7 | - [ ] SUBU 8 | - [x] LW 9 | - [ ] SW 10 | - [ ] BEQ 11 | 12 | #### 采分点 13 | - [x] RAW hazards 14 | - [ ] BEQ 15 | 16 | #### 汇编指令 17 | ``` 18 | LW R1, R0, 0 19 | LW R2, R0, 4 20 | ADDU R7, R8, r9 21 | ADDU R7, R8, r9 22 | ADDU R3, R1, R2 23 | ADDU R4, R3, R2 24 | ADDU R5, R1, R4 25 | HALT 26 | ``` -------------------------------------------------------------------------------- /README_EN.md: -------------------------------------------------------------------------------- 1 | # CSA_Lab1_test 2 | 3 | ## testcase 4 | Folder testcase contains testcases for lab 1. 5 | 6 | Testcases are listed from easy to hard 7 | 8 | ## assembler 9 | 10 | The assembler is an assembler that translates ARM assembly language into machine code. 11 | 12 | Currently supported commands are ADDU, SUBU, LW, SW, BEQ, HALT 13 | 14 | #### Web 15 | 16 | Link to the website: [Assembler](https://va.poncirus.site/assembler) -------------------------------------------------------------------------------- /testcase/1-5/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 1-5 2 | 3 | #### 包含的指令 4 | - [x] ADDU 5 | - [ ] SUBU 6 | - [x] LW 7 | - [x] SW 8 | - [ ] BEQ 9 | 10 | #### 采分点 11 | - [x] RAW hazards 12 | - [ ] BEQ 13 | 14 | #### 汇编指令 15 | ``` 16 | LW R1, R0, 0 17 | LW R2, R0, 4 18 | ADDU R3, R1, R2 19 | ADDU R4, R3, R2 20 | ADDU R5, R3, R4 21 | LW R6, R0, 8 22 | ADDU R7, R6, R5 23 | SW R7, R0, 12 24 | LW R8, R0, 4 25 | SW R8, R0, 16 26 | HALT 27 | ``` -------------------------------------------------------------------------------- /testcase/1-1/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 00000001 10 | 00001001 11 | 00111000 12 | 00100001 13 | 00000001 14 | 00001001 15 | 00111000 16 | 00100001 17 | 00000000 18 | 00100010 19 | 00011000 20 | 00100001 21 | 00000000 22 | 01100010 23 | 00100000 24 | 00100001 25 | 00000000 26 | 00100100 27 | 00101000 28 | 00100001 29 | 11111111 30 | 11111111 31 | 11111111 32 | 11111111 -------------------------------------------------------------------------------- /testcase/2-1/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 00000000 10 | 10100110 11 | 00100000 12 | 00100001 13 | 00000000 14 | 10100110 15 | 00100000 16 | 00100001 17 | 00010000 18 | 01000001 19 | 00000000 20 | 00000001 21 | 00000000 22 | 01000001 23 | 00100000 24 | 00100011 25 | 00000000 26 | 01000001 27 | 00101000 28 | 00100001 29 | 11111111 30 | 11111111 31 | 11111111 32 | 11111111 -------------------------------------------------------------------------------- /assembler/README_EN.md: -------------------------------------------------------------------------------- 1 | # assembler 2 | 3 | The assembler is an assembler that translates ARM assembly language into machine code. 4 | 5 | Currently supported commands are ADDU, SUBU, LW, SW, BEQ, HALT 6 | 7 | ### Web 8 | 9 | Link to the website: [Assembler](https://va.poncirus.site/assembler) 10 | 11 | ### Manually operation 12 | 13 | Modify the ins in the main function to translate the ARM assembly language, and the output is the corresponding machine code. -------------------------------------------------------------------------------- /testcase/1-1/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 1-1 2 | 3 | This testcase is designed for EX-EX forwarding 4 | 5 | #### Instruction 6 | - [x] ADDU 7 | - [ ] SUBU 8 | - [x] LW 9 | - [ ] SW 10 | - [ ] BEQ 11 | 12 | #### Grading scheme 13 | - [x] RAW hazards 14 | - [ ] BEQ 15 | 16 | #### Assembly 17 | ``` 18 | LW R1, R0, 0 19 | LW R2, R0, 4 20 | ADDU R7, R8, r9 21 | ADDU R7, R8, r9 22 | ADDU R3, R1, R2 23 | ADDU R4, R3, R2 24 | ADDU R5, R1, R4 25 | HALT 26 | ``` -------------------------------------------------------------------------------- /testcase/1-2/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 1-2 2 | 3 | 这个测试用例针对 MEM-EX Forwarding 设计 4 | 5 | #### 包含的指令 6 | - [x] ADDU 7 | - [ ] SUBU 8 | - [x] LW 9 | - [ ] SW 10 | - [ ] BEQ 11 | 12 | #### 采分点 13 | - [x] RAW hazards 14 | - [ ] BEQ 15 | 16 | #### 汇编指令 17 | ``` 18 | LW R1, R0, 0 19 | LW R2, R0, 4 20 | ADDU R7, R8, r9 21 | ADDU R7, R8, r9 22 | ADDU R3, R1, R2 23 | ADDU R7, R8, r9 24 | ADDU R4, R3, R2 25 | ADDU R7, R8, r9 26 | ADDU R5, R1, R4 27 | HALT 28 | ``` -------------------------------------------------------------------------------- /testcase/1-5/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 1-5 2 | 3 | #### Instruction 4 | - [x] ADDU 5 | - [ ] SUBU 6 | - [x] LW 7 | - [x] SW 8 | - [ ] BEQ 9 | 10 | #### Grading scheme 11 | - [x] RAW hazards 12 | - [ ] BEQ 13 | 14 | #### Assembly 15 | ``` 16 | LW R1, R0, 0 17 | LW R2, R0, 4 18 | ADDU R3, R1, R2 19 | ADDU R4, R3, R2 20 | ADDU R5, R3, R4 21 | LW R6, R0, 8 22 | ADDU R7, R6, R5 23 | SW R7, R0, 12 24 | LW R8, R0, 4 25 | SW R8, R0, 16 26 | HALT 27 | ``` -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # CSA_Lab1_test 2 | 3 | [English Version](./README_EN.md) 4 | 5 | ## 贡献者 6 | 7 | 感谢为该项目提供支持和帮助的小伙伴 8 | - [ly4096x](https://github.com/ly4096x) 9 | - [zoeing00](https://github.com/Zoeing00) 10 | 11 | ## testcase 12 | 13 | 目录包含了Lab1的测试用例 14 | 15 | 测试用例从简单到困难进行排列 16 | 17 | ## assembler 18 | 19 | assembler是一个将ARM汇编语言翻译为机器码的汇编器 20 | 21 | 目前支持的指令有ADDU, SUBU, LW, SW, BEQ, HALT 22 | 23 | #### 网页版 24 | 25 | 由此链接进入网页版: [Assembler](https://va.poncirus.site/assembler) 26 | -------------------------------------------------------------------------------- /assembler/main.go: -------------------------------------------------------------------------------- 1 | package main 2 | 3 | import ( 4 | "fmt" 5 | 6 | "./assembler" 7 | ) 8 | 9 | func main() { 10 | ins := ` 11 | lw r1,r0,0 12 | Lw r2,r0,4 13 | Addu r3, r1,r2 14 | ADDU R4, R3, R2 15 | ADDU R5, R3, R4 16 | LW R6, R0, 8 17 | ADDU R7, R6, R5 18 | SW R7, R0, 12 19 | LW R8, R0, 4 20 | Sw r8,r0,16 21 | halt 22 | ` 23 | code, err := assembler.Assemble(ins) 24 | if err != 0 { 25 | fmt.Println("Error line: ", err) 26 | } else { 27 | fmt.Print(*code) 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /assembler/assembler/assemble.go: -------------------------------------------------------------------------------- 1 | package assembler 2 | 3 | import "strings" 4 | 5 | /* 6 | Assemble ARM instructions to machine code 7 | */ 8 | func Assemble(instrctions string) (code *string, errorLine int) { 9 | ins := strings.Split(strings.TrimSpace(instrctions), "\n") 10 | var b strings.Builder 11 | for i, v := range ins { 12 | if c := AssembleLine(v); c != nil { 13 | b.WriteString(*c) 14 | } else { 15 | return nil, i + 1 16 | } 17 | } 18 | c := b.String() 19 | return &c, 0 20 | } 21 | -------------------------------------------------------------------------------- /testcase/0-1/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 00000001 10 | 00001001 11 | 00111000 12 | 00100001 13 | 00000001 14 | 00001001 15 | 00111000 16 | 00100001 17 | 00000000 18 | 00100010 19 | 00011000 20 | 00100001 21 | 00000001 22 | 00001001 23 | 00111000 24 | 00100001 25 | 00000001 26 | 00001001 27 | 00111000 28 | 00100001 29 | 10101100 30 | 00000011 31 | 00000000 32 | 00001000 33 | 11111111 34 | 11111111 35 | 11111111 36 | 11111111 -------------------------------------------------------------------------------- /testcase/0-2/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 00000001 10 | 00001001 11 | 00111000 12 | 00100001 13 | 00000001 14 | 00001001 15 | 00111000 16 | 00100001 17 | 00000000 18 | 00100010 19 | 00011000 20 | 00100011 21 | 00000001 22 | 00001001 23 | 00111000 24 | 00100001 25 | 00000001 26 | 00001001 27 | 00111000 28 | 00100001 29 | 10101100 30 | 00000011 31 | 00000000 32 | 00001000 33 | 11111111 34 | 11111111 35 | 11111111 36 | 11111111 -------------------------------------------------------------------------------- /testcase/1-2/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 1-2 2 | 3 | This testcase is designed for MEM-EX forwarding 4 | 5 | #### Instruction 6 | - [x] ADDU 7 | - [ ] SUBU 8 | - [x] LW 9 | - [ ] SW 10 | - [ ] BEQ 11 | 12 | #### Grading scheme 13 | - [x] RAW hazards 14 | - [ ] BEQ 15 | 16 | #### Assembly 17 | ``` 18 | LW R1, R0, 0 19 | LW R2, R0, 4 20 | ADDU R7, R8, r9 21 | ADDU R7, R8, r9 22 | ADDU R3, R1, R2 23 | ADDU R7, R8, r9 24 | ADDU R4, R3, R2 25 | ADDU R7, R8, r9 26 | ADDU R5, R1, R4 27 | HALT 28 | ``` -------------------------------------------------------------------------------- /testcase/3-1/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 10001100 10 | 00000011 11 | 00000000 12 | 00000000 13 | 10001100 14 | 00000100 15 | 00000000 16 | 00000100 17 | 10001100 18 | 00000101 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00100010 23 | 00110000 24 | 00100001 25 | 00000000 26 | 00100010 27 | 00111000 28 | 00100011 29 | 10101100 30 | 00000001 31 | 00000000 32 | 00001000 33 | 11111111 34 | 11111111 35 | 11111111 36 | 11111111 37 | -------------------------------------------------------------------------------- /testcase/3-2/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 00000000 10 | 00000001 11 | 00110000 12 | 00100001 13 | 10001100 14 | 00000100 15 | 00000000 16 | 00000100 17 | 10101100 18 | 00000100 19 | 00000000 20 | 00000000 21 | 00000000 22 | 10000110 23 | 00110000 24 | 00100001 25 | 00000000 26 | 11000001 27 | 00111000 28 | 00100011 29 | 10101100 30 | 00000111 31 | 00000000 32 | 00001000 33 | 11111111 34 | 11111111 35 | 11111111 36 | 11111111 37 | -------------------------------------------------------------------------------- /testcase/3-3/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 00000000 10 | 00100010 11 | 00110000 12 | 00100001 13 | 10001100 14 | 00000100 15 | 00000000 16 | 00000100 17 | 10101100 18 | 00000100 19 | 00000000 20 | 00000000 21 | 00000000 22 | 10000110 23 | 00110000 24 | 00100001 25 | 00000000 26 | 11000001 27 | 00111000 28 | 00100011 29 | 10101100 30 | 00000111 31 | 00000000 32 | 00001000 33 | 11111111 34 | 11111111 35 | 11111111 36 | 11111111 37 | -------------------------------------------------------------------------------- /testcase/1-2/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 00000001 10 | 00001001 11 | 00111000 12 | 00100001 13 | 00000001 14 | 00001001 15 | 00111000 16 | 00100001 17 | 00000000 18 | 00100010 19 | 00011000 20 | 00100001 21 | 00000001 22 | 00001001 23 | 00111000 24 | 00100001 25 | 00000000 26 | 01100010 27 | 00100000 28 | 00100001 29 | 00000001 30 | 00001001 31 | 00111000 32 | 00100001 33 | 00000000 34 | 00100100 35 | 00101000 36 | 00100001 37 | 11111111 38 | 11111111 39 | 11111111 40 | 11111111 -------------------------------------------------------------------------------- /testcase/3-4/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 10001100 10 | 00000011 11 | 00000000 12 | 00000000 13 | 10001100 14 | 00000100 15 | 00000000 16 | 00000100 17 | 00000000 18 | 00100010 19 | 00001000 20 | 00100011 21 | 10001100 22 | 00000101 23 | 00000000 24 | 00001000 25 | 00000000 26 | 01100100 27 | 00100000 28 | 00100001 29 | 00010000 30 | 00100000 31 | 11111111 32 | 11111100 33 | 10101100 34 | 00000100 35 | 00000000 36 | 00001000 37 | 11111111 38 | 11111111 39 | 11111111 40 | 11111111 41 | -------------------------------------------------------------------------------- /testcase/1-5/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00000001 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00000010 7 | 00000000 8 | 00000100 9 | 00000000 10 | 00100010 11 | 00011000 12 | 00100001 13 | 00000000 14 | 01100010 15 | 00100000 16 | 00100001 17 | 00000000 18 | 01100100 19 | 00101000 20 | 00100001 21 | 10001100 22 | 00000110 23 | 00000000 24 | 00001000 25 | 00000000 26 | 11000101 27 | 00111000 28 | 00100001 29 | 10101100 30 | 00000111 31 | 00000000 32 | 00001100 33 | 10001100 34 | 00001000 35 | 00000000 36 | 00000100 37 | 10101100 38 | 00001000 39 | 00000000 40 | 00010000 41 | 11111111 42 | 11111111 43 | 11111111 44 | 11111111 -------------------------------------------------------------------------------- /testcase/2-2/README.md: -------------------------------------------------------------------------------- 1 | # 测试用例 2-2 2 | 3 | 斐波那契数列生成器 4 | Fibonacci sequence generator 5 | 6 | ``` 7 | .align 4 8 | [0] = Initial value 9 | [1] = Address step amount 10 | [2] = Stop address 11 | ``` 12 | 13 | #### 包含的指令 14 | - [x] ADDU 15 | - [x] SUBU 16 | - [x] LW 17 | - [x] SW 18 | - [x] BEQ 19 | 20 | #### 采分点 21 | - [x] RAW hazards 22 | - [x] BEQ 23 | 24 | #### 汇编指令 25 | ``` 26 | lw r10,r0,0 27 | lw r11,r0,4 28 | lw r12,r0,8 29 | addu r2,r0,r0 30 | lw r3,r0,12 31 | addu r1,r2,r0 32 | addu r2,r3,r0 33 | addu r3,r1,r2 34 | sw r3,r10,0 35 | addu r10,r10,r11 36 | subu r0,r0,r0 37 | subu r0,r0,r0 38 | beq r12,r10,-8 39 | halt 40 | ``` 41 | -------------------------------------------------------------------------------- /testcase/2-2/README_EN.md: -------------------------------------------------------------------------------- 1 | # TESTCASE 2-2 2 | 3 | Fibonacci sequence generator 4 | 5 | ``` 6 | .align 4 7 | [0] = Initial value 8 | [1] = Address step amount 9 | [2] = Stop address 10 | ``` 11 | 12 | #### Instruction 13 | - [x] ADDU 14 | - [x] SUBU 15 | - [x] LW 16 | - [x] SW 17 | - [x] BEQ 18 | 19 | 20 | #### Grading scheme 21 | - [x] RAW hazards 22 | - [x] BEQ 23 | 24 | #### Assembly 25 | ``` 26 | lw r10,r0,0 27 | lw r11,r0,4 28 | lw r12,r0,8 29 | addu r2,r0,r0 30 | lw r3,r0,12 31 | addu r1,r2,r0 32 | addu r2,r3,r0 33 | addu r3,r1,r2 34 | sw r3,r10,0 35 | addu r10,r10,r11 36 | subu r0,r0,r0 37 | subu r0,r0,r0 38 | beq r12,r10,-8 39 | halt 40 | ``` 41 | -------------------------------------------------------------------------------- /testcase/2-2/imem.txt: -------------------------------------------------------------------------------- 1 | 10001100 2 | 00001010 3 | 00000000 4 | 00000000 5 | 10001100 6 | 00001011 7 | 00000000 8 | 00000100 9 | 10001100 10 | 00001100 11 | 00000000 12 | 00001000 13 | 00000000 14 | 00000000 15 | 00010000 16 | 00100001 17 | 10001100 18 | 00000011 19 | 00000000 20 | 00001100 21 | 00000000 22 | 01000000 23 | 00001000 24 | 00100001 25 | 00000000 26 | 01100000 27 | 00010000 28 | 00100001 29 | 00000000 30 | 00100010 31 | 00011000 32 | 00100001 33 | 10101101 34 | 01000011 35 | 00000000 36 | 00000000 37 | 00000001 38 | 01001011 39 | 01010000 40 | 00100001 41 | 00000000 42 | 00000000 43 | 00000000 44 | 00100011 45 | 00000000 46 | 00000000 47 | 00000000 48 | 00100011 49 | 00010001 50 | 10001010 51 | 11111111 52 | 11111000 53 | 11111111 54 | 11111111 55 | 11111111 56 | 11111111 57 | -------------------------------------------------------------------------------- /testcase/README.md: -------------------------------------------------------------------------------- 1 | # testcase 2 | 3 | 目录包含了Lab1的测试用例 4 | 5 | 测试用例从简单到困难进行排列 6 | 7 | ## 自动测试方法 8 | 9 | **自动测试仅比较了dmemresult和RFresult, 在测试通过的情况下程序仍可能存在问题** 10 | 11 | 1. 安装git和vim: `sudo apt-get install git vim` 12 | 2. clone项目: `git clone https://github.com/LiaoHanwen/CSA_Lab1_test.git` 13 | 3. 进入testcase目录: `cd CSA_Lab1_test/testcase` 14 | 4. 将MIPS_pipeline.cpp源文件拷贝到目录下 15 | 5. 编译源文件: `make --always-make` 16 | 6. 进行自动测试: `make test` 17 | 7. 选择单个测试用例进行测试: `make test case=` 18 | 19 | ## 手动测试方法 20 | 21 | 将某一个测试用例的imem.txt和dmem.txt拷贝到目标目录下并运行程序，程序完成后将生成的dmemresult.txt，RFresult.txt和stateresult.txt与测试用例下的同名文件进行对比 22 | 23 | ## 测试用例简介 24 | 25 | ### GROUP 0 采分点 26 | - [ ] RAW hazards 27 | - [ ] BEQ 28 | 29 | ### GROUP 1 采分点 30 | - [x] RAW hazards 31 | - [ ] BEQ 32 | 33 | ### GROUP 2 采分点 34 | - [x] RAW hazards 35 | - [x] BEQ 36 | 37 | ### GROUP 3 38 | 39 | **GROUP 3**的测试用例来自于NYU Classes 40 | -------------------------------------------------------------------------------- /testcase/test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | DIFF=vimdiff 4 | DIFFEND="" 5 | if ! command -v vimdiff 2>&1 >/dev/null ; then 6 | DIFF="diff --side-by-side --color=always" 7 | DIFFEND="|less" 8 | fi 9 | 10 | testcase=$1 11 | if [[ "$testcase" == "" ]]; then 12 | testcase=$(ls -d -- */) 13 | fi 14 | 15 | for i in $testcase; do 16 | echo -e "=============================================================\n>>>> $i" 17 | cd $i 18 | for file in dmemresult.txt RFresult.txt stateresult.txt; do 19 | [ -e $file ] && rm $file 20 | done 21 | ../MIPS_pipeline 22 | diff -wq dmemresult* 23 | DMEM_SAME=$? 24 | diff -wq RFresult* 25 | RF_SAME=$? 26 | [[ "$DMEM_SAME" == "1" || "$RF_SAME" == "1" ]] && echo 'Result differs from answer. Press Enter to view.' && read 27 | [[ "$DMEM_SAME" == "1" ]] && eval "$DIFF dmemresult* $DIFFEND" 28 | [[ "$RF_SAME" == "1" ]] && eval "$DIFF RFresult* $DIFFEND" 29 | cd .. 30 | done 31 | -------------------------------------------------------------------------------- /testcase/0-1/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 11111111111111111111111111111111 4 | 01111111111111111111111111111110 5 | 01111111111111111111111111111101 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/0-2/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 11111111111111111111111111111111 4 | 01111111111111111111111111111110 5 | 10000000000000000000000000000001 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/1-1/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000001 4 | 00000000000000000000000000000010 5 | 00000000000000000000000000000011 6 | 00000000000000000000000000000101 7 | 00000000000000000000000000000110 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/1-2/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000001 4 | 00000000000000000000000000000010 5 | 00000000000000000000000000000011 6 | 00000000000000000000000000000101 7 | 00000000000000000000000000000110 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/1-3/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 11000000001100000000110000000011 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/1-4/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 11000000001100000000110000000011 4 | 10000000011000000001100000000110 5 | 00000000000000000000000000000000 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/1-5/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000001 4 | 00000000000000000000000000000010 5 | 00000000000000000000000000000011 6 | 00000000000000000000000000000101 7 | 00000000000000000000000000001000 8 | 00000000000000000000000000000100 9 | 00000000000000000000000000001100 10 | 00000000000000000000000000000010 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/1-6/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000001000 4 | 11000000001100000000110000000011 5 | 00000000000000000000000000000000 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/2-1/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000001 4 | 00000000000000000000000000000010 5 | 00000000000000000000000000000000 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000011 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/2-2/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 00000000000000000000001001100010 4 | 00000000000000000000001111011011 5 | 00000000000000000000011000111101 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000001010000 13 | 00000000000000000000000000000100 14 | 00000000000000000000000001010000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/3-1/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 11111111111111111111111111111111 4 | 01111111111111111111111111111110 5 | 11111111111111111111111111111111 6 | 01111111111111111111111111111110 7 | 11111111111111111111111111111111 8 | 01111111111111111111111111111101 9 | 10000000000000000000000000000001 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/3-2/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 11111111111111111111111111111111 4 | 01111111111111111111111111111110 5 | 00000000000000000000000000000000 6 | 01111111111111111111111111111110 7 | 00000000000000000000000000000000 8 | 01111111111111111111111111111101 9 | 01111111111111111111111111111110 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/3-3/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 11111111111111111111111111111111 4 | 01111111111111111111111111111110 5 | 00000000000000000000000000000000 6 | 01111111111111111111111111111110 7 | 00000000000000000000000000000000 8 | 11111111111111111111111111111011 9 | 11111111111111111111111111111100 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/3-4/RFresult_ans.txt: -------------------------------------------------------------------------------- 1 | State of RF: 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000001 5 | 00000000000000000000000000000011 6 | 00000000000000000000000000001010 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00000000000000000000000000000000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | -------------------------------------------------------------------------------- /testcase/README_EN.md: -------------------------------------------------------------------------------- 1 | # testcase 2 | 3 | Folder contains testcases for lab1 4 | 5 | Testcases are listed from easy to hard 6 | 7 | ## Automatic Testing 8 | 9 | **Automatic Testing only compares dmemresult and RFresult, the program may have problems even if passing the test** 10 | 11 | 1. install git and vim: `sudo apt-get install git vim` 12 | 2. clone project: `git clone https://github.com/LiaoHanwen/CSA_Lab1_test.git` 13 | 3. cd to testcase: `cd CSA_Lab1_test/testcase` 14 | 4. Put your `MIPS_pipeline.cpp` file in this directory. 15 | 5. Run `make --always-make` to build. 16 | 6. Run `make test` to begin testing for all test cases. 17 | 7. Optionally use `make test case=` to test a single case. 18 | 19 | ## Manually Testing method 20 | 21 | Copy the imem.txt and dmem.txt of a testcase to the target directory and run the program. After the program is completed, compare the generated dmemresult.txt, RFresult.txt and stateresult.txt with the file with the same name under the test case. 22 | 23 | ## Testcases Introduction 24 | 25 | ### GROUP 0 Grading scheme 26 | - [ ] RAW hazards 27 | - [ ] BEQ 28 | 29 | ### GROUP 1 Grading scheme 30 | - [x] RAW hazards 31 | - [ ] BEQ 32 | 33 | ### GROUP 2 Grading scheme 34 | - [x] RAW hazards 35 | - [x] BEQ 36 | 37 | ### GROUP 3 38 | 39 | testcases in **GROUP 3** are from NYU Classes 40 | -------------------------------------------------------------------------------- /assembler/assembler/assemble_line.go: -------------------------------------------------------------------------------- 1 | package assembler 2 | 3 | import ( 4 | "fmt" 5 | "strconv" 6 | "strings" 7 | ) 8 | 9 | /* 10 | AssembleLine assemble one line ARM instruction to machine code 11 | */ 12 | func AssembleLine(instrction string) *string { 13 | // to upper 14 | ins := strings.ToUpper(instrction) 15 | 16 | // remove space and \n 17 | ins = strings.TrimSpace(ins) 18 | 19 | // HALT 20 | if ins == "HALT" { 21 | code := "11111111\n11111111\n11111111\n11111111\n" 22 | return &code 23 | } 24 | 25 | // get instruction 26 | firstSpace := strings.Index(ins, " ") 27 | if firstSpace == -1 { 28 | return nil 29 | } 30 | i := ins[:firstSpace] 31 | 32 | // split parameters 33 | ins = ins[firstSpace:] 34 | paras, n := splitParameter(ins) 35 | 36 | // code 37 | c := "" 38 | 39 | // add opcode 40 | switch i { 41 | case "ADDU", "SUBU": 42 | c += iToA(0, 6) 43 | case "BEQ": 44 | c += iToA(0x4, 6) 45 | case "LW": 46 | c += iToA(0x23, 6) 47 | case "SW": 48 | c += iToA(0x2B, 6) 49 | default: 50 | return nil 51 | } 52 | 53 | // add other code 54 | switch i { 55 | case "ADDU", "SUBU": 56 | if n != 3 { 57 | return nil 58 | } 59 | 60 | if v, err := decodeR(paras[1], 5); err { 61 | c += *v 62 | } else { 63 | return nil 64 | } 65 | if v, err := decodeR(paras[2], 5); err { 66 | c += *v 67 | } else { 68 | return nil 69 | } 70 | if v, err := decodeR(paras[0], 5); err { 71 | c += *v 72 | } else { 73 | return nil 74 | } 75 | case "LW", "SW": 76 | if n != 3 { 77 | return nil 78 | } 79 | 80 | if v, err := decodeR(paras[1], 5); err { 81 | c += *v 82 | } else { 83 | return nil 84 | } 85 | if v, err := decodeR(paras[0], 5); err { 86 | c += *v 87 | } else { 88 | return nil 89 | } 90 | if i, err := strconv.Atoi(strings.TrimSpace(paras[2])); err == nil { 91 | c += iToA(i, 16) 92 | } else { 93 | return nil 94 | } 95 | case "BEQ": 96 | if n != 3 { 97 | return nil 98 | } 99 | 100 | if v, err := decodeR(paras[0], 5); err { 101 | c += *v 102 | } else { 103 | return nil 104 | } 105 | if v, err := decodeR(paras[1], 5); err { 106 | c += *v 107 | } else { 108 | return nil 109 | } 110 | if i, err := strconv.Atoi(strings.TrimSpace(paras[2])); err == nil { 111 | c += iToA(i, 16) 112 | } else { 113 | return nil 114 | } 115 | } 116 | 117 | // add funct 118 | switch i { 119 | case "ADDU": 120 | c += iToA(0x21, 11) 121 | case "SUBU": 122 | c += iToA(0x23, 11) 123 | } 124 | 125 | var b strings.Builder 126 | for i := 0; i < 4; i++ { 127 | b.WriteString(c[i*8 : (i+1)*8]) 128 | b.WriteByte('\n') 129 | } 130 | c = b.String() 131 | 132 | return &c 133 | } 134 | 135 | /* 136 | splitParameter split instrution to parameters 137 | */ 138 | func splitParameter(ins string) (paras []string, n int) { 139 | // remove space and \n 140 | ins = strings.TrimSpace(ins) 141 | 142 | p := strings.Split(ins, ",") 143 | for _, v := range p { 144 | v = strings.TrimSpace(v) 145 | } 146 | 147 | return p, len(p) 148 | } 149 | 150 | /* 151 | iToA returns the string representation of i, the length of the string is len 152 | */ 153 | func iToA(i int, length int) string { 154 | nega := i < 0 155 | if nega { 156 | i = -i - 1 157 | } 158 | 159 | s := strconv.FormatInt(int64(i), 2) 160 | 161 | if nega { 162 | var b strings.Builder 163 | for _, v := range s { 164 | if v == '1' { 165 | b.WriteByte('0') 166 | } else { 167 | b.WriteByte('1') 168 | } 169 | } 170 | s = b.String() 171 | } 172 | 173 | if len(s) > length { 174 | return s[:length] 175 | } 176 | 177 | var b strings.Builder 178 | for b.Len() < length-len(s) { 179 | if nega { 180 | fmt.Fprintf(&b, "1") 181 | } else { 182 | fmt.Fprintf(&b, "0") 183 | } 184 | } 185 | b.WriteString(s) 186 | 187 | return b.String() 188 | } 189 | 190 | /* 191 | decodeR decode register string to code 192 | */ 193 | func decodeR(c string, length int) (*string, bool) { 194 | c = strings.TrimSpace(c) 195 | if strings.HasPrefix(c, "R") { 196 | s := strings.TrimLeft(c, "R") 197 | if i, err := strconv.Atoi(s); err == nil { 198 | code := iToA(i, length) 199 | return &code, true 200 | } 201 | return nil, false 202 | } 203 | return nil, false 204 | } 205 | -------------------------------------------------------------------------------- /testcase/1-3/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 204 13 | EX.rd_mem: 204 14 | EX.wrt_mem: 204 15 | EX.alu_op: 204 16 | EX.wrt_enable: 204 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 204 24 | MEM.wrt_mem: 204 25 | MEM.wrt_enable: 204 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 204 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10101100000000010000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 204 56 | MEM.wrt_mem: 204 57 | MEM.wrt_enable: 204 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 204 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 8 67 | IF.nop: 1 68 | ID.Instr: 11111111111111111111111111111111 69 | ID.nop: 1 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00001 75 | EX.Wrt_reg_addr: 00001 76 | EX.is_I_type: 1 77 | EX.rd_mem: 0 78 | EX.wrt_mem: 1 79 | EX.alu_op: 1 80 | EX.wrt_enable: 0 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 204 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 8 99 | IF.nop: 1 100 | ID.Instr: 11111111111111111111111111111111 101 | ID.nop: 1 102 | EX.Read_data1: 00000000000000000000000000000000 103 | EX.Read_data2: 11000000001100000000110000000011 104 | EX.Imm: 0000000000000100 105 | EX.Rs: 00000 106 | EX.Rt: 00001 107 | EX.Wrt_reg_addr: 00001 108 | EX.is_I_type: 1 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 1 111 | EX.alu_op: 1 112 | EX.wrt_enable: 0 113 | EX.nop: 1 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 11000000001100000000110000000011 116 | MEM.Rs: 00000 117 | MEM.Rt: 00001 118 | MEM.Wrt_reg_addr: 00001 119 | MEM.rd_mem: 0 120 | MEM.wrt_mem: 1 121 | MEM.wrt_enable: 0 122 | MEM.nop: 0 123 | WB.Wrt_data: 11000000001100000000110000000011 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 8 131 | IF.nop: 1 132 | ID.Instr: 11111111111111111111111111111111 133 | ID.nop: 1 134 | EX.Read_data1: 00000000000000000000000000000000 135 | EX.Read_data2: 11000000001100000000110000000011 136 | EX.Imm: 0000000000000100 137 | EX.Rs: 00000 138 | EX.Rt: 00001 139 | EX.Wrt_reg_addr: 00001 140 | EX.is_I_type: 1 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 1 143 | EX.alu_op: 1 144 | EX.wrt_enable: 0 145 | EX.nop: 1 146 | MEM.ALUresult: 00000000000000000000000000000100 147 | MEM.Store_data: 11000000001100000000110000000011 148 | MEM.Rs: 00000 149 | MEM.Rt: 00001 150 | MEM.Wrt_reg_addr: 00001 151 | MEM.rd_mem: 0 152 | MEM.wrt_mem: 1 153 | MEM.wrt_enable: 0 154 | MEM.nop: 1 155 | WB.Wrt_data: 00000000000000000000000000000100 156 | WB.Rs: 00000 157 | WB.Rt: 00001 158 | WB.Wrt_reg_addr: 00001 159 | WB.wrt_enable: 0 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 8 163 | IF.nop: 1 164 | ID.Instr: 11111111111111111111111111111111 165 | ID.nop: 1 166 | EX.Read_data1: 00000000000000000000000000000000 167 | EX.Read_data2: 11000000001100000000110000000011 168 | EX.Imm: 0000000000000100 169 | EX.Rs: 00000 170 | EX.Rt: 00001 171 | EX.Wrt_reg_addr: 00001 172 | EX.is_I_type: 1 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 1 175 | EX.alu_op: 1 176 | EX.wrt_enable: 0 177 | EX.nop: 1 178 | MEM.ALUresult: 00000000000000000000000000000100 179 | MEM.Store_data: 11000000001100000000110000000011 180 | MEM.Rs: 00000 181 | MEM.Rt: 00001 182 | MEM.Wrt_reg_addr: 00001 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 1 185 | MEM.wrt_enable: 0 186 | MEM.nop: 1 187 | WB.Wrt_data: 00000000000000000000000000000100 188 | WB.Rs: 00000 189 | WB.Rt: 00001 190 | WB.Wrt_reg_addr: 00001 191 | WB.wrt_enable: 0 192 | WB.nop: 1 193 | -------------------------------------------------------------------------------- /testcase/1-4/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 204 13 | EX.rd_mem: 204 14 | EX.wrt_mem: 204 15 | EX.alu_op: 204 16 | EX.wrt_enable: 204 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 204 24 | MEM.wrt_mem: 204 25 | MEM.wrt_enable: 204 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 204 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 00000000001000010001000000100001 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 204 56 | MEM.wrt_mem: 204 57 | MEM.wrt_enable: 204 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 204 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 8 67 | IF.nop: 1 68 | ID.Instr: 11111111111111111111111111111111 69 | ID.nop: 1 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0001000000100001 73 | EX.Rs: 00001 74 | EX.Rt: 00001 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 0 77 | EX.rd_mem: 0 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 204 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 8 99 | IF.nop: 1 100 | ID.Instr: 11111111111111111111111111111111 101 | ID.nop: 1 102 | EX.Read_data1: 11000000001100000000110000000011 103 | EX.Read_data2: 11000000001100000000110000000011 104 | EX.Imm: 0001000000100001 105 | EX.Rs: 00001 106 | EX.Rt: 00001 107 | EX.Wrt_reg_addr: 00010 108 | EX.is_I_type: 0 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000000 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00001 118 | MEM.Wrt_reg_addr: 00001 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 1 123 | WB.Wrt_data: 11000000001100000000110000000011 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 8 131 | IF.nop: 1 132 | ID.Instr: 11111111111111111111111111111111 133 | ID.nop: 1 134 | EX.Read_data1: 11000000001100000000110000000011 135 | EX.Read_data2: 11000000001100000000110000000011 136 | EX.Imm: 0001000000100001 137 | EX.Rs: 00001 138 | EX.Rt: 00001 139 | EX.Wrt_reg_addr: 00010 140 | EX.is_I_type: 0 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 1 146 | MEM.ALUresult: 10000000011000000001100000000110 147 | MEM.Store_data: 11000000001100000000110000000011 148 | MEM.Rs: 00001 149 | MEM.Rt: 00001 150 | MEM.Wrt_reg_addr: 00010 151 | MEM.rd_mem: 0 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 0 155 | WB.Wrt_data: 11000000001100000000110000000011 156 | WB.Rs: 00000 157 | WB.Rt: 00001 158 | WB.Wrt_reg_addr: 00001 159 | WB.wrt_enable: 1 160 | WB.nop: 1 161 | State after executing cycle: 5 162 | IF.PC: 8 163 | IF.nop: 1 164 | ID.Instr: 11111111111111111111111111111111 165 | ID.nop: 1 166 | EX.Read_data1: 11000000001100000000110000000011 167 | EX.Read_data2: 11000000001100000000110000000011 168 | EX.Imm: 0001000000100001 169 | EX.Rs: 00001 170 | EX.Rt: 00001 171 | EX.Wrt_reg_addr: 00010 172 | EX.is_I_type: 0 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 0 175 | EX.alu_op: 1 176 | EX.wrt_enable: 1 177 | EX.nop: 1 178 | MEM.ALUresult: 10000000011000000001100000000110 179 | MEM.Store_data: 11000000001100000000110000000011 180 | MEM.Rs: 00001 181 | MEM.Rt: 00001 182 | MEM.Wrt_reg_addr: 00010 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 1 187 | WB.Wrt_data: 10000000011000000001100000000110 188 | WB.Rs: 00001 189 | WB.Rt: 00001 190 | WB.Wrt_reg_addr: 00010 191 | WB.wrt_enable: 1 192 | WB.nop: 0 193 | State after executing cycle: 6 194 | IF.PC: 8 195 | IF.nop: 1 196 | ID.Instr: 11111111111111111111111111111111 197 | ID.nop: 1 198 | EX.Read_data1: 11000000001100000000110000000011 199 | EX.Read_data2: 11000000001100000000110000000011 200 | EX.Imm: 0001000000100001 201 | EX.Rs: 00001 202 | EX.Rt: 00001 203 | EX.Wrt_reg_addr: 00010 204 | EX.is_I_type: 0 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 0 207 | EX.alu_op: 1 208 | EX.wrt_enable: 1 209 | EX.nop: 1 210 | MEM.ALUresult: 10000000011000000001100000000110 211 | MEM.Store_data: 11000000001100000000110000000011 212 | MEM.Rs: 00001 213 | MEM.Rt: 00001 214 | MEM.Wrt_reg_addr: 00010 215 | MEM.rd_mem: 0 216 | MEM.wrt_mem: 0 217 | MEM.wrt_enable: 1 218 | MEM.nop: 1 219 | WB.Wrt_data: 10000000011000000001100000000110 220 | WB.Rs: 00001 221 | WB.Rt: 00001 222 | WB.Wrt_reg_addr: 00010 223 | WB.wrt_enable: 1 224 | WB.nop: 1 225 | -------------------------------------------------------------------------------- /testcase/1-6/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 204 13 | EX.rd_mem: 204 14 | EX.wrt_mem: 204 15 | EX.alu_op: 204 16 | EX.wrt_enable: 204 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 204 24 | MEM.wrt_mem: 204 25 | MEM.wrt_enable: 204 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 204 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100001000101111111111111100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 204 56 | MEM.wrt_mem: 204 57 | MEM.wrt_enable: 204 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 204 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 10101100000000100000000000001000 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 1111111111111100 73 | EX.Rs: 00001 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 204 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 12 99 | IF.nop: 0 100 | ID.Instr: 10101100000000100000000000001000 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000001000 103 | EX.Read_data2: 00000000000000000000000000000000 104 | EX.Imm: 1111111111111100 105 | EX.Rs: 00001 106 | EX.Rt: 00010 107 | EX.Wrt_reg_addr: 00010 108 | EX.is_I_type: 1 109 | EX.rd_mem: 1 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000000 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00001 118 | MEM.Wrt_reg_addr: 00001 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 1 123 | WB.Wrt_data: 00000000000000000000000000001000 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 12 131 | IF.nop: 1 132 | ID.Instr: 11111111111111111111111111111111 133 | ID.nop: 1 134 | EX.Read_data1: 00000000000000000000000000000000 135 | EX.Read_data2: 00000000000000000000000000000100 136 | EX.Imm: 0000000000001000 137 | EX.Rs: 00000 138 | EX.Rt: 00010 139 | EX.Wrt_reg_addr: 00010 140 | EX.is_I_type: 1 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 1 143 | EX.alu_op: 1 144 | EX.wrt_enable: 0 145 | EX.nop: 0 146 | MEM.ALUresult: 00000000000000000000000000000100 147 | MEM.Store_data: 00000000000000000000000000000000 148 | MEM.Rs: 00001 149 | MEM.Rt: 00010 150 | MEM.Wrt_reg_addr: 00010 151 | MEM.rd_mem: 1 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 0 155 | WB.Wrt_data: 00000000000000000000000000001000 156 | WB.Rs: 00000 157 | WB.Rt: 00001 158 | WB.Wrt_reg_addr: 00001 159 | WB.wrt_enable: 1 160 | WB.nop: 1 161 | State after executing cycle: 5 162 | IF.PC: 12 163 | IF.nop: 1 164 | ID.Instr: 11111111111111111111111111111111 165 | ID.nop: 1 166 | EX.Read_data1: 00000000000000000000000000000000 167 | EX.Read_data2: 11000000001100000000110000000011 168 | EX.Imm: 0000000000001000 169 | EX.Rs: 00000 170 | EX.Rt: 00010 171 | EX.Wrt_reg_addr: 00010 172 | EX.is_I_type: 1 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 1 175 | EX.alu_op: 1 176 | EX.wrt_enable: 0 177 | EX.nop: 1 178 | MEM.ALUresult: 00000000000000000000000000001000 179 | MEM.Store_data: 11000000001100000000110000000011 180 | MEM.Rs: 00000 181 | MEM.Rt: 00010 182 | MEM.Wrt_reg_addr: 00010 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 1 185 | MEM.wrt_enable: 0 186 | MEM.nop: 0 187 | WB.Wrt_data: 11000000001100000000110000000011 188 | WB.Rs: 00001 189 | WB.Rt: 00010 190 | WB.Wrt_reg_addr: 00010 191 | WB.wrt_enable: 1 192 | WB.nop: 0 193 | State after executing cycle: 6 194 | IF.PC: 12 195 | IF.nop: 1 196 | ID.Instr: 11111111111111111111111111111111 197 | ID.nop: 1 198 | EX.Read_data1: 00000000000000000000000000000000 199 | EX.Read_data2: 11000000001100000000110000000011 200 | EX.Imm: 0000000000001000 201 | EX.Rs: 00000 202 | EX.Rt: 00010 203 | EX.Wrt_reg_addr: 00010 204 | EX.is_I_type: 1 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 1 207 | EX.alu_op: 1 208 | EX.wrt_enable: 0 209 | EX.nop: 1 210 | MEM.ALUresult: 00000000000000000000000000001000 211 | MEM.Store_data: 11000000001100000000110000000011 212 | MEM.Rs: 00000 213 | MEM.Rt: 00010 214 | MEM.Wrt_reg_addr: 00010 215 | MEM.rd_mem: 0 216 | MEM.wrt_mem: 1 217 | MEM.wrt_enable: 0 218 | MEM.nop: 1 219 | WB.Wrt_data: 00000000000000000000000000001000 220 | WB.Rs: 00000 221 | WB.Rt: 00010 222 | WB.Wrt_reg_addr: 00010 223 | WB.wrt_enable: 0 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 12 227 | IF.nop: 1 228 | ID.Instr: 11111111111111111111111111111111 229 | ID.nop: 1 230 | EX.Read_data1: 00000000000000000000000000000000 231 | EX.Read_data2: 11000000001100000000110000000011 232 | EX.Imm: 0000000000001000 233 | EX.Rs: 00000 234 | EX.Rt: 00010 235 | EX.Wrt_reg_addr: 00010 236 | EX.is_I_type: 1 237 | EX.rd_mem: 0 238 | EX.wrt_mem: 1 239 | EX.alu_op: 1 240 | EX.wrt_enable: 0 241 | EX.nop: 1 242 | MEM.ALUresult: 00000000000000000000000000001000 243 | MEM.Store_data: 11000000001100000000110000000011 244 | MEM.Rs: 00000 245 | MEM.Rt: 00010 246 | MEM.Wrt_reg_addr: 00010 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 1 249 | MEM.wrt_enable: 0 250 | MEM.nop: 1 251 | WB.Wrt_data: 00000000000000000000000000001000 252 | WB.Rs: 00000 253 | WB.Rt: 00010 254 | WB.Wrt_reg_addr: 00010 255 | WB.wrt_enable: 0 256 | WB.nop: 1 257 | -------------------------------------------------------------------------------- /testcase/1-1/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 204 13 | EX.rd_mem: 204 14 | EX.wrt_mem: 204 15 | EX.alu_op: 204 16 | EX.wrt_enable: 204 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 204 24 | MEM.wrt_mem: 204 25 | MEM.wrt_enable: 204 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 204 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100000000100000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 204 56 | MEM.wrt_mem: 204 57 | MEM.wrt_enable: 204 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 204 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 00000001000010010011100000100001 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 204 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 16 99 | IF.nop: 0 100 | ID.Instr: 00000001000010010011100000100001 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000000000 103 | EX.Read_data2: 00000000000000000000000000000000 104 | EX.Imm: 0011100000100001 105 | EX.Rs: 01000 106 | EX.Rt: 01001 107 | EX.Wrt_reg_addr: 00111 108 | EX.is_I_type: 0 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00010 118 | MEM.Wrt_reg_addr: 00010 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 0 123 | WB.Wrt_data: 00000000000000000000000000000001 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 20 131 | IF.nop: 0 132 | ID.Instr: 00000000001000100001100000100001 133 | ID.nop: 0 134 | EX.Read_data1: 00000000000000000000000000000000 135 | EX.Read_data2: 00000000000000000000000000000000 136 | EX.Imm: 0011100000100001 137 | EX.Rs: 01000 138 | EX.Rt: 01001 139 | EX.Wrt_reg_addr: 00111 140 | EX.is_I_type: 0 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 0 146 | MEM.ALUresult: 00000000000000000000000000000000 147 | MEM.Store_data: 00000000000000000000000000000000 148 | MEM.Rs: 01000 149 | MEM.Rt: 01001 150 | MEM.Wrt_reg_addr: 00111 151 | MEM.rd_mem: 0 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 0 155 | WB.Wrt_data: 00000000000000000000000000000010 156 | WB.Rs: 00000 157 | WB.Rt: 00010 158 | WB.Wrt_reg_addr: 00010 159 | WB.wrt_enable: 1 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 24 163 | IF.nop: 0 164 | ID.Instr: 00000000011000100010000000100001 165 | ID.nop: 0 166 | EX.Read_data1: 00000000000000000000000000000001 167 | EX.Read_data2: 00000000000000000000000000000010 168 | EX.Imm: 0001100000100001 169 | EX.Rs: 00001 170 | EX.Rt: 00010 171 | EX.Wrt_reg_addr: 00011 172 | EX.is_I_type: 0 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 0 175 | EX.alu_op: 1 176 | EX.wrt_enable: 1 177 | EX.nop: 0 178 | MEM.ALUresult: 00000000000000000000000000000000 179 | MEM.Store_data: 00000000000000000000000000000000 180 | MEM.Rs: 01000 181 | MEM.Rt: 01001 182 | MEM.Wrt_reg_addr: 00111 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 0 187 | WB.Wrt_data: 00000000000000000000000000000000 188 | WB.Rs: 01000 189 | WB.Rt: 01001 190 | WB.Wrt_reg_addr: 00111 191 | WB.wrt_enable: 1 192 | WB.nop: 0 193 | State after executing cycle: 6 194 | IF.PC: 28 195 | IF.nop: 0 196 | ID.Instr: 00000000001001000010100000100001 197 | ID.nop: 0 198 | EX.Read_data1: 00000000000000000000000000000011 199 | EX.Read_data2: 00000000000000000000000000000010 200 | EX.Imm: 0010000000100001 201 | EX.Rs: 00011 202 | EX.Rt: 00010 203 | EX.Wrt_reg_addr: 00100 204 | EX.is_I_type: 0 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 0 207 | EX.alu_op: 1 208 | EX.wrt_enable: 1 209 | EX.nop: 0 210 | MEM.ALUresult: 00000000000000000000000000000011 211 | MEM.Store_data: 00000000000000000000000000000010 212 | MEM.Rs: 00001 213 | MEM.Rt: 00010 214 | MEM.Wrt_reg_addr: 00011 215 | MEM.rd_mem: 0 216 | MEM.wrt_mem: 0 217 | MEM.wrt_enable: 1 218 | MEM.nop: 0 219 | WB.Wrt_data: 00000000000000000000000000000000 220 | WB.Rs: 01000 221 | WB.Rt: 01001 222 | WB.Wrt_reg_addr: 00111 223 | WB.wrt_enable: 1 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 28 227 | IF.nop: 1 228 | ID.Instr: 11111111111111111111111111111111 229 | ID.nop: 1 230 | EX.Read_data1: 00000000000000000000000000000001 231 | EX.Read_data2: 00000000000000000000000000000101 232 | EX.Imm: 0010100000100001 233 | EX.Rs: 00001 234 | EX.Rt: 00100 235 | EX.Wrt_reg_addr: 00101 236 | EX.is_I_type: 0 237 | EX.rd_mem: 0 238 | EX.wrt_mem: 0 239 | EX.alu_op: 1 240 | EX.wrt_enable: 1 241 | EX.nop: 0 242 | MEM.ALUresult: 00000000000000000000000000000101 243 | MEM.Store_data: 00000000000000000000000000000010 244 | MEM.Rs: 00011 245 | MEM.Rt: 00010 246 | MEM.Wrt_reg_addr: 00100 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 0 249 | MEM.wrt_enable: 1 250 | MEM.nop: 0 251 | WB.Wrt_data: 00000000000000000000000000000011 252 | WB.Rs: 00001 253 | WB.Rt: 00010 254 | WB.Wrt_reg_addr: 00011 255 | WB.wrt_enable: 1 256 | WB.nop: 0 257 | State after executing cycle: 8 258 | IF.PC: 28 259 | IF.nop: 1 260 | ID.Instr: 11111111111111111111111111111111 261 | ID.nop: 1 262 | EX.Read_data1: 00000000000000000000000000000001 263 | EX.Read_data2: 00000000000000000000000000000101 264 | EX.Imm: 0010100000100001 265 | EX.Rs: 00001 266 | EX.Rt: 00100 267 | EX.Wrt_reg_addr: 00101 268 | EX.is_I_type: 0 269 | EX.rd_mem: 0 270 | EX.wrt_mem: 0 271 | EX.alu_op: 1 272 | EX.wrt_enable: 1 273 | EX.nop: 1 274 | MEM.ALUresult: 00000000000000000000000000000110 275 | MEM.Store_data: 00000000000000000000000000000101 276 | MEM.Rs: 00001 277 | MEM.Rt: 00100 278 | MEM.Wrt_reg_addr: 00101 279 | MEM.rd_mem: 0 280 | MEM.wrt_mem: 0 281 | MEM.wrt_enable: 1 282 | MEM.nop: 0 283 | WB.Wrt_data: 00000000000000000000000000000101 284 | WB.Rs: 00011 285 | WB.Rt: 00010 286 | WB.Wrt_reg_addr: 00100 287 | WB.wrt_enable: 1 288 | WB.nop: 0 289 | State after executing cycle: 9 290 | IF.PC: 28 291 | IF.nop: 1 292 | ID.Instr: 11111111111111111111111111111111 293 | ID.nop: 1 294 | EX.Read_data1: 00000000000000000000000000000001 295 | EX.Read_data2: 00000000000000000000000000000101 296 | EX.Imm: 0010100000100001 297 | EX.Rs: 00001 298 | EX.Rt: 00100 299 | EX.Wrt_reg_addr: 00101 300 | EX.is_I_type: 0 301 | EX.rd_mem: 0 302 | EX.wrt_mem: 0 303 | EX.alu_op: 1 304 | EX.wrt_enable: 1 305 | EX.nop: 1 306 | MEM.ALUresult: 00000000000000000000000000000110 307 | MEM.Store_data: 00000000000000000000000000000101 308 | MEM.Rs: 00001 309 | MEM.Rt: 00100 310 | MEM.Wrt_reg_addr: 00101 311 | MEM.rd_mem: 0 312 | MEM.wrt_mem: 0 313 | MEM.wrt_enable: 1 314 | MEM.nop: 1 315 | WB.Wrt_data: 00000000000000000000000000000110 316 | WB.Rs: 00001 317 | WB.Rt: 00100 318 | WB.Wrt_reg_addr: 00101 319 | WB.wrt_enable: 1 320 | WB.nop: 0 321 | State after executing cycle: 10 322 | IF.PC: 28 323 | IF.nop: 1 324 | ID.Instr: 11111111111111111111111111111111 325 | ID.nop: 1 326 | EX.Read_data1: 00000000000000000000000000000001 327 | EX.Read_data2: 00000000000000000000000000000101 328 | EX.Imm: 0010100000100001 329 | EX.Rs: 00001 330 | EX.Rt: 00100 331 | EX.Wrt_reg_addr: 00101 332 | EX.is_I_type: 0 333 | EX.rd_mem: 0 334 | EX.wrt_mem: 0 335 | EX.alu_op: 1 336 | EX.wrt_enable: 1 337 | EX.nop: 1 338 | MEM.ALUresult: 00000000000000000000000000000110 339 | MEM.Store_data: 00000000000000000000000000000101 340 | MEM.Rs: 00001 341 | MEM.Rt: 00100 342 | MEM.Wrt_reg_addr: 00101 343 | MEM.rd_mem: 0 344 | MEM.wrt_mem: 0 345 | MEM.wrt_enable: 1 346 | MEM.nop: 1 347 | WB.Wrt_data: 00000000000000000000000000000110 348 | WB.Rs: 00001 349 | WB.Rt: 00100 350 | WB.Wrt_reg_addr: 00101 351 | WB.wrt_enable: 1 352 | WB.nop: 1 353 | -------------------------------------------------------------------------------- /testcase/2-1/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 204 13 | EX.rd_mem: 204 14 | EX.wrt_mem: 204 15 | EX.alu_op: 204 16 | EX.wrt_enable: 204 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 204 24 | MEM.wrt_mem: 204 25 | MEM.wrt_enable: 204 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 204 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100000000100000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 204 56 | MEM.wrt_mem: 204 57 | MEM.wrt_enable: 204 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 204 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 00000000101001100010000000100001 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 204 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 16 99 | IF.nop: 0 100 | ID.Instr: 00000000101001100010000000100001 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000000000 103 | EX.Read_data2: 00000000000000000000000000000000 104 | EX.Imm: 0010000000100001 105 | EX.Rs: 00101 106 | EX.Rt: 00110 107 | EX.Wrt_reg_addr: 00100 108 | EX.is_I_type: 0 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00010 118 | MEM.Wrt_reg_addr: 00010 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 0 123 | WB.Wrt_data: 00000000000000000000000000000001 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 20 131 | IF.nop: 0 132 | ID.Instr: 00010000010000010000000000000001 133 | ID.nop: 0 134 | EX.Read_data1: 00000000000000000000000000000000 135 | EX.Read_data2: 00000000000000000000000000000000 136 | EX.Imm: 0010000000100001 137 | EX.Rs: 00101 138 | EX.Rt: 00110 139 | EX.Wrt_reg_addr: 00100 140 | EX.is_I_type: 0 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 0 146 | MEM.ALUresult: 00000000000000000000000000000000 147 | MEM.Store_data: 00000000000000000000000000000000 148 | MEM.Rs: 00101 149 | MEM.Rt: 00110 150 | MEM.Wrt_reg_addr: 00100 151 | MEM.rd_mem: 0 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 0 155 | WB.Wrt_data: 00000000000000000000000000000010 156 | WB.Rs: 00000 157 | WB.Rt: 00010 158 | WB.Wrt_reg_addr: 00010 159 | WB.wrt_enable: 1 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 24 163 | IF.nop: 0 164 | ID.Instr: 00000000010000010010000000100011 165 | ID.nop: 1 166 | EX.Read_data1: 00000000000000000000000000000010 167 | EX.Read_data2: 00000000000000000000000000000001 168 | EX.Imm: 0000000000000001 169 | EX.Rs: 00010 170 | EX.Rt: 00001 171 | EX.Wrt_reg_addr: 00001 172 | EX.is_I_type: 1 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 0 175 | EX.alu_op: 0 176 | EX.wrt_enable: 0 177 | EX.nop: 1 178 | MEM.ALUresult: 00000000000000000000000000000000 179 | MEM.Store_data: 00000000000000000000000000000000 180 | MEM.Rs: 00101 181 | MEM.Rt: 00110 182 | MEM.Wrt_reg_addr: 00100 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 0 187 | WB.Wrt_data: 00000000000000000000000000000000 188 | WB.Rs: 00101 189 | WB.Rt: 00110 190 | WB.Wrt_reg_addr: 00100 191 | WB.wrt_enable: 1 192 | WB.nop: 0 193 | State after executing cycle: 6 194 | IF.PC: 28 195 | IF.nop: 0 196 | ID.Instr: 00000000010000010010100000100001 197 | ID.nop: 0 198 | EX.Read_data1: 00000000000000000000000000000010 199 | EX.Read_data2: 00000000000000000000000000000001 200 | EX.Imm: 0000000000000001 201 | EX.Rs: 00010 202 | EX.Rt: 00001 203 | EX.Wrt_reg_addr: 00001 204 | EX.is_I_type: 1 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 0 207 | EX.alu_op: 0 208 | EX.wrt_enable: 0 209 | EX.nop: 1 210 | MEM.ALUresult: 00000000000000000000000000000000 211 | MEM.Store_data: 00000000000000000000000000000000 212 | MEM.Rs: 00101 213 | MEM.Rt: 00110 214 | MEM.Wrt_reg_addr: 00100 215 | MEM.rd_mem: 0 216 | MEM.wrt_mem: 0 217 | MEM.wrt_enable: 1 218 | MEM.nop: 1 219 | WB.Wrt_data: 00000000000000000000000000000000 220 | WB.Rs: 00101 221 | WB.Rt: 00110 222 | WB.Wrt_reg_addr: 00100 223 | WB.wrt_enable: 1 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 28 227 | IF.nop: 1 228 | ID.Instr: 11111111111111111111111111111111 229 | ID.nop: 1 230 | EX.Read_data1: 00000000000000000000000000000010 231 | EX.Read_data2: 00000000000000000000000000000001 232 | EX.Imm: 0010100000100001 233 | EX.Rs: 00010 234 | EX.Rt: 00001 235 | EX.Wrt_reg_addr: 00101 236 | EX.is_I_type: 0 237 | EX.rd_mem: 0 238 | EX.wrt_mem: 0 239 | EX.alu_op: 1 240 | EX.wrt_enable: 1 241 | EX.nop: 0 242 | MEM.ALUresult: 00000000000000000000000000000000 243 | MEM.Store_data: 00000000000000000000000000000000 244 | MEM.Rs: 00101 245 | MEM.Rt: 00110 246 | MEM.Wrt_reg_addr: 00100 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 0 249 | MEM.wrt_enable: 1 250 | MEM.nop: 1 251 | WB.Wrt_data: 00000000000000000000000000000000 252 | WB.Rs: 00101 253 | WB.Rt: 00110 254 | WB.Wrt_reg_addr: 00100 255 | WB.wrt_enable: 1 256 | WB.nop: 1 257 | State after executing cycle: 8 258 | IF.PC: 28 259 | IF.nop: 1 260 | ID.Instr: 11111111111111111111111111111111 261 | ID.nop: 1 262 | EX.Read_data1: 00000000000000000000000000000010 263 | EX.Read_data2: 00000000000000000000000000000001 264 | EX.Imm: 0010100000100001 265 | EX.Rs: 00010 266 | EX.Rt: 00001 267 | EX.Wrt_reg_addr: 00101 268 | EX.is_I_type: 0 269 | EX.rd_mem: 0 270 | EX.wrt_mem: 0 271 | EX.alu_op: 1 272 | EX.wrt_enable: 1 273 | EX.nop: 1 274 | MEM.ALUresult: 00000000000000000000000000000011 275 | MEM.Store_data: 00000000000000000000000000000001 276 | MEM.Rs: 00010 277 | MEM.Rt: 00001 278 | MEM.Wrt_reg_addr: 00101 279 | MEM.rd_mem: 0 280 | MEM.wrt_mem: 0 281 | MEM.wrt_enable: 1 282 | MEM.nop: 0 283 | WB.Wrt_data: 00000000000000000000000000000000 284 | WB.Rs: 00101 285 | WB.Rt: 00110 286 | WB.Wrt_reg_addr: 00100 287 | WB.wrt_enable: 1 288 | WB.nop: 1 289 | State after executing cycle: 9 290 | IF.PC: 28 291 | IF.nop: 1 292 | ID.Instr: 11111111111111111111111111111111 293 | ID.nop: 1 294 | EX.Read_data1: 00000000000000000000000000000010 295 | EX.Read_data2: 00000000000000000000000000000001 296 | EX.Imm: 0010100000100001 297 | EX.Rs: 00010 298 | EX.Rt: 00001 299 | EX.Wrt_reg_addr: 00101 300 | EX.is_I_type: 0 301 | EX.rd_mem: 0 302 | EX.wrt_mem: 0 303 | EX.alu_op: 1 304 | EX.wrt_enable: 1 305 | EX.nop: 1 306 | MEM.ALUresult: 00000000000000000000000000000011 307 | MEM.Store_data: 00000000000000000000000000000001 308 | MEM.Rs: 00010 309 | MEM.Rt: 00001 310 | MEM.Wrt_reg_addr: 00101 311 | MEM.rd_mem: 0 312 | MEM.wrt_mem: 0 313 | MEM.wrt_enable: 1 314 | MEM.nop: 1 315 | WB.Wrt_data: 00000000000000000000000000000011 316 | WB.Rs: 00010 317 | WB.Rt: 00001 318 | WB.Wrt_reg_addr: 00101 319 | WB.wrt_enable: 1 320 | WB.nop: 0 321 | State after executing cycle: 10 322 | IF.PC: 28 323 | IF.nop: 1 324 | ID.Instr: 11111111111111111111111111111111 325 | ID.nop: 1 326 | EX.Read_data1: 00000000000000000000000000000010 327 | EX.Read_data2: 00000000000000000000000000000001 328 | EX.Imm: 0010100000100001 329 | EX.Rs: 00010 330 | EX.Rt: 00001 331 | EX.Wrt_reg_addr: 00101 332 | EX.is_I_type: 0 333 | EX.rd_mem: 0 334 | EX.wrt_mem: 0 335 | EX.alu_op: 1 336 | EX.wrt_enable: 1 337 | EX.nop: 1 338 | MEM.ALUresult: 00000000000000000000000000000011 339 | MEM.Store_data: 00000000000000000000000000000001 340 | MEM.Rs: 00010 341 | MEM.Rt: 00001 342 | MEM.Wrt_reg_addr: 00101 343 | MEM.rd_mem: 0 344 | MEM.wrt_mem: 0 345 | MEM.wrt_enable: 1 346 | MEM.nop: 1 347 | WB.Wrt_data: 00000000000000000000000000000011 348 | WB.Rs: 00010 349 | WB.Rt: 00001 350 | WB.Wrt_reg_addr: 00101 351 | WB.wrt_enable: 1 352 | WB.nop: 1 353 | -------------------------------------------------------------------------------- /testcase/3-1/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 0 13 | EX.rd_mem: 0 14 | EX.wrt_mem: 0 15 | EX.alu_op: 1 16 | EX.wrt_enable: 0 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 0 24 | MEM.wrt_mem: 0 25 | MEM.wrt_enable: 0 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 0 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100000000100000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 0 56 | MEM.wrt_mem: 0 57 | MEM.wrt_enable: 0 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 0 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 10001100000000110000000000000000 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 0 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 16 99 | IF.nop: 0 100 | ID.Instr: 10001100000001000000000000000100 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000000000 103 | EX.Read_data2: 00000000000000000000000000000000 104 | EX.Imm: 0000000000000000 105 | EX.Rs: 00000 106 | EX.Rt: 00011 107 | EX.Wrt_reg_addr: 00011 108 | EX.is_I_type: 1 109 | EX.rd_mem: 1 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00010 118 | MEM.Wrt_reg_addr: 00010 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 0 123 | WB.Wrt_data: 11111111111111111111111111111111 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 20 131 | IF.nop: 0 132 | ID.Instr: 10001100000001010000000000000000 133 | ID.nop: 0 134 | EX.Read_data1: 00000000000000000000000000000000 135 | EX.Read_data2: 00000000000000000000000000000000 136 | EX.Imm: 0000000000000100 137 | EX.Rs: 00000 138 | EX.Rt: 00100 139 | EX.Wrt_reg_addr: 00100 140 | EX.is_I_type: 1 141 | EX.rd_mem: 1 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 0 146 | MEM.ALUresult: 00000000000000000000000000000000 147 | MEM.Store_data: 00000000000000000000000000000000 148 | MEM.Rs: 00000 149 | MEM.Rt: 00011 150 | MEM.Wrt_reg_addr: 00011 151 | MEM.rd_mem: 1 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 0 155 | WB.Wrt_data: 01111111111111111111111111111110 156 | WB.Rs: 00000 157 | WB.Rt: 00010 158 | WB.Wrt_reg_addr: 00010 159 | WB.wrt_enable: 1 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 24 163 | IF.nop: 0 164 | ID.Instr: 00000000001000100011000000100001 165 | ID.nop: 0 166 | EX.Read_data1: 00000000000000000000000000000000 167 | EX.Read_data2: 00000000000000000000000000000000 168 | EX.Imm: 0000000000000000 169 | EX.Rs: 00000 170 | EX.Rt: 00101 171 | EX.Wrt_reg_addr: 00101 172 | EX.is_I_type: 1 173 | EX.rd_mem: 1 174 | EX.wrt_mem: 0 175 | EX.alu_op: 1 176 | EX.wrt_enable: 1 177 | EX.nop: 0 178 | MEM.ALUresult: 00000000000000000000000000000100 179 | MEM.Store_data: 00000000000000000000000000000000 180 | MEM.Rs: 00000 181 | MEM.Rt: 00100 182 | MEM.Wrt_reg_addr: 00100 183 | MEM.rd_mem: 1 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 0 187 | WB.Wrt_data: 11111111111111111111111111111111 188 | WB.Rs: 00000 189 | WB.Rt: 00011 190 | WB.Wrt_reg_addr: 00011 191 | WB.wrt_enable: 1 192 | WB.nop: 0 193 | State after executing cycle: 6 194 | IF.PC: 28 195 | IF.nop: 0 196 | ID.Instr: 00000000001000100011100000100011 197 | ID.nop: 0 198 | EX.Read_data1: 11111111111111111111111111111111 199 | EX.Read_data2: 01111111111111111111111111111110 200 | EX.Imm: 0011000000100001 201 | EX.Rs: 00001 202 | EX.Rt: 00010 203 | EX.Wrt_reg_addr: 00110 204 | EX.is_I_type: 0 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 0 207 | EX.alu_op: 1 208 | EX.wrt_enable: 1 209 | EX.nop: 0 210 | MEM.ALUresult: 00000000000000000000000000000000 211 | MEM.Store_data: 00000000000000000000000000000000 212 | MEM.Rs: 00000 213 | MEM.Rt: 00101 214 | MEM.Wrt_reg_addr: 00101 215 | MEM.rd_mem: 1 216 | MEM.wrt_mem: 0 217 | MEM.wrt_enable: 1 218 | MEM.nop: 0 219 | WB.Wrt_data: 01111111111111111111111111111110 220 | WB.Rs: 00000 221 | WB.Rt: 00100 222 | WB.Wrt_reg_addr: 00100 223 | WB.wrt_enable: 1 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 32 227 | IF.nop: 0 228 | ID.Instr: 10101100000000010000000000001000 229 | ID.nop: 0 230 | EX.Read_data1: 11111111111111111111111111111111 231 | EX.Read_data2: 01111111111111111111111111111110 232 | EX.Imm: 0011100000100011 233 | EX.Rs: 00001 234 | EX.Rt: 00010 235 | EX.Wrt_reg_addr: 00111 236 | EX.is_I_type: 0 237 | EX.rd_mem: 0 238 | EX.wrt_mem: 0 239 | EX.alu_op: 0 240 | EX.wrt_enable: 1 241 | EX.nop: 0 242 | MEM.ALUresult: 01111111111111111111111111111101 243 | MEM.Store_data: 01111111111111111111111111111110 244 | MEM.Rs: 00001 245 | MEM.Rt: 00010 246 | MEM.Wrt_reg_addr: 00110 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 0 249 | MEM.wrt_enable: 1 250 | MEM.nop: 0 251 | WB.Wrt_data: 11111111111111111111111111111111 252 | WB.Rs: 00000 253 | WB.Rt: 00101 254 | WB.Wrt_reg_addr: 00101 255 | WB.wrt_enable: 1 256 | WB.nop: 0 257 | State after executing cycle: 8 258 | IF.PC: 32 259 | IF.nop: 1 260 | ID.Instr: 11111111111111111111111111111111 261 | ID.nop: 1 262 | EX.Read_data1: 00000000000000000000000000000000 263 | EX.Read_data2: 11111111111111111111111111111111 264 | EX.Imm: 0000000000001000 265 | EX.Rs: 00000 266 | EX.Rt: 00001 267 | EX.Wrt_reg_addr: 00001 268 | EX.is_I_type: 1 269 | EX.rd_mem: 0 270 | EX.wrt_mem: 1 271 | EX.alu_op: 1 272 | EX.wrt_enable: 0 273 | EX.nop: 0 274 | MEM.ALUresult: 10000000000000000000000000000001 275 | MEM.Store_data: 01111111111111111111111111111110 276 | MEM.Rs: 00001 277 | MEM.Rt: 00010 278 | MEM.Wrt_reg_addr: 00111 279 | MEM.rd_mem: 0 280 | MEM.wrt_mem: 0 281 | MEM.wrt_enable: 1 282 | MEM.nop: 0 283 | WB.Wrt_data: 01111111111111111111111111111101 284 | WB.Rs: 00001 285 | WB.Rt: 00010 286 | WB.Wrt_reg_addr: 00110 287 | WB.wrt_enable: 1 288 | WB.nop: 0 289 | State after executing cycle: 9 290 | IF.PC: 32 291 | IF.nop: 1 292 | ID.Instr: 11111111111111111111111111111111 293 | ID.nop: 1 294 | EX.Read_data1: 00000000000000000000000000000000 295 | EX.Read_data2: 11111111111111111111111111111111 296 | EX.Imm: 0000000000001000 297 | EX.Rs: 00000 298 | EX.Rt: 00001 299 | EX.Wrt_reg_addr: 00001 300 | EX.is_I_type: 1 301 | EX.rd_mem: 0 302 | EX.wrt_mem: 1 303 | EX.alu_op: 1 304 | EX.wrt_enable: 0 305 | EX.nop: 1 306 | MEM.ALUresult: 00000000000000000000000000001000 307 | MEM.Store_data: 11111111111111111111111111111111 308 | MEM.Rs: 00000 309 | MEM.Rt: 00001 310 | MEM.Wrt_reg_addr: 00001 311 | MEM.rd_mem: 0 312 | MEM.wrt_mem: 1 313 | MEM.wrt_enable: 0 314 | MEM.nop: 0 315 | WB.Wrt_data: 10000000000000000000000000000001 316 | WB.Rs: 00001 317 | WB.Rt: 00010 318 | WB.Wrt_reg_addr: 00111 319 | WB.wrt_enable: 1 320 | WB.nop: 0 321 | State after executing cycle: 10 322 | IF.PC: 32 323 | IF.nop: 1 324 | ID.Instr: 11111111111111111111111111111111 325 | ID.nop: 1 326 | EX.Read_data1: 00000000000000000000000000000000 327 | EX.Read_data2: 11111111111111111111111111111111 328 | EX.Imm: 0000000000001000 329 | EX.Rs: 00000 330 | EX.Rt: 00001 331 | EX.Wrt_reg_addr: 00001 332 | EX.is_I_type: 1 333 | EX.rd_mem: 0 334 | EX.wrt_mem: 1 335 | EX.alu_op: 1 336 | EX.wrt_enable: 0 337 | EX.nop: 1 338 | MEM.ALUresult: 00000000000000000000000000001000 339 | MEM.Store_data: 11111111111111111111111111111111 340 | MEM.Rs: 00000 341 | MEM.Rt: 00001 342 | MEM.Wrt_reg_addr: 00001 343 | MEM.rd_mem: 0 344 | MEM.wrt_mem: 1 345 | MEM.wrt_enable: 0 346 | MEM.nop: 1 347 | WB.Wrt_data: 11111111111111111111111111111111 348 | WB.Rs: 00000 349 | WB.Rt: 00001 350 | WB.Wrt_reg_addr: 00001 351 | WB.wrt_enable: 0 352 | WB.nop: 0 353 | State after executing cycle: 11 354 | IF.PC: 32 355 | IF.nop: 1 356 | ID.Instr: 11111111111111111111111111111111 357 | ID.nop: 1 358 | EX.Read_data1: 00000000000000000000000000000000 359 | EX.Read_data2: 11111111111111111111111111111111 360 | EX.Imm: 0000000000001000 361 | EX.Rs: 00000 362 | EX.Rt: 00001 363 | EX.Wrt_reg_addr: 00001 364 | EX.is_I_type: 1 365 | EX.rd_mem: 0 366 | EX.wrt_mem: 1 367 | EX.alu_op: 1 368 | EX.wrt_enable: 0 369 | EX.nop: 1 370 | MEM.ALUresult: 00000000000000000000000000001000 371 | MEM.Store_data: 11111111111111111111111111111111 372 | MEM.Rs: 00000 373 | MEM.Rt: 00001 374 | MEM.Wrt_reg_addr: 00001 375 | MEM.rd_mem: 0 376 | MEM.wrt_mem: 1 377 | MEM.wrt_enable: 0 378 | MEM.nop: 1 379 | WB.Wrt_data: 11111111111111111111111111111111 380 | WB.Rs: 00000 381 | WB.Rt: 00001 382 | WB.Wrt_reg_addr: 00001 383 | WB.wrt_enable: 0 384 | WB.nop: 1 385 | -------------------------------------------------------------------------------- /testcase/3-2/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 0 13 | EX.rd_mem: 0 14 | EX.wrt_mem: 0 15 | EX.alu_op: 1 16 | EX.wrt_enable: 0 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 0 24 | MEM.wrt_mem: 0 25 | MEM.wrt_enable: 0 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 0 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100000000100000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 0 56 | MEM.wrt_mem: 0 57 | MEM.wrt_enable: 0 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 0 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 00000000000000010011000000100001 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 0 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 16 99 | IF.nop: 0 100 | ID.Instr: 10001100000001000000000000000100 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000000000 103 | EX.Read_data2: 00000000000000000000000000000000 104 | EX.Imm: 0011000000100001 105 | EX.Rs: 00000 106 | EX.Rt: 00001 107 | EX.Wrt_reg_addr: 00110 108 | EX.is_I_type: 0 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00010 118 | MEM.Wrt_reg_addr: 00010 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 0 123 | WB.Wrt_data: 11111111111111111111111111111111 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 20 131 | IF.nop: 0 132 | ID.Instr: 10101100000001000000000000000000 133 | ID.nop: 0 134 | EX.Read_data1: 00000000000000000000000000000000 135 | EX.Read_data2: 00000000000000000000000000000000 136 | EX.Imm: 0000000000000100 137 | EX.Rs: 00000 138 | EX.Rt: 00100 139 | EX.Wrt_reg_addr: 00100 140 | EX.is_I_type: 1 141 | EX.rd_mem: 1 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 0 146 | MEM.ALUresult: 11111111111111111111111111111111 147 | MEM.Store_data: 11111111111111111111111111111111 148 | MEM.Rs: 00000 149 | MEM.Rt: 00001 150 | MEM.Wrt_reg_addr: 00110 151 | MEM.rd_mem: 0 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 0 155 | WB.Wrt_data: 01111111111111111111111111111110 156 | WB.Rs: 00000 157 | WB.Rt: 00010 158 | WB.Wrt_reg_addr: 00010 159 | WB.wrt_enable: 1 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 24 163 | IF.nop: 0 164 | ID.Instr: 00000000100001100011000000100001 165 | ID.nop: 0 166 | EX.Read_data1: 00000000000000000000000000000000 167 | EX.Read_data2: 00000000000000000000000000000000 168 | EX.Imm: 0000000000000000 169 | EX.Rs: 00000 170 | EX.Rt: 00100 171 | EX.Wrt_reg_addr: 00100 172 | EX.is_I_type: 1 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 1 175 | EX.alu_op: 1 176 | EX.wrt_enable: 0 177 | EX.nop: 0 178 | MEM.ALUresult: 00000000000000000000000000000100 179 | MEM.Store_data: 00000000000000000000000000000000 180 | MEM.Rs: 00000 181 | MEM.Rt: 00100 182 | MEM.Wrt_reg_addr: 00100 183 | MEM.rd_mem: 1 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 0 187 | WB.Wrt_data: 11111111111111111111111111111111 188 | WB.Rs: 00000 189 | WB.Rt: 00001 190 | WB.Wrt_reg_addr: 00110 191 | WB.wrt_enable: 1 192 | WB.nop: 0 193 | State after executing cycle: 6 194 | IF.PC: 28 195 | IF.nop: 0 196 | ID.Instr: 00000000110000010011100000100011 197 | ID.nop: 0 198 | EX.Read_data1: 00000000000000000000000000000000 199 | EX.Read_data2: 11111111111111111111111111111111 200 | EX.Imm: 0011000000100001 201 | EX.Rs: 00100 202 | EX.Rt: 00110 203 | EX.Wrt_reg_addr: 00110 204 | EX.is_I_type: 0 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 0 207 | EX.alu_op: 1 208 | EX.wrt_enable: 1 209 | EX.nop: 0 210 | MEM.ALUresult: 00000000000000000000000000000000 211 | MEM.Store_data: 00000000000000000000000000000000 212 | MEM.Rs: 00000 213 | MEM.Rt: 00100 214 | MEM.Wrt_reg_addr: 00100 215 | MEM.rd_mem: 0 216 | MEM.wrt_mem: 1 217 | MEM.wrt_enable: 0 218 | MEM.nop: 0 219 | WB.Wrt_data: 01111111111111111111111111111110 220 | WB.Rs: 00000 221 | WB.Rt: 00100 222 | WB.Wrt_reg_addr: 00100 223 | WB.wrt_enable: 1 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 32 227 | IF.nop: 0 228 | ID.Instr: 10101100000001110000000000001000 229 | ID.nop: 0 230 | EX.Read_data1: 11111111111111111111111111111111 231 | EX.Read_data2: 11111111111111111111111111111111 232 | EX.Imm: 0011100000100011 233 | EX.Rs: 00110 234 | EX.Rt: 00001 235 | EX.Wrt_reg_addr: 00111 236 | EX.is_I_type: 0 237 | EX.rd_mem: 0 238 | EX.wrt_mem: 0 239 | EX.alu_op: 0 240 | EX.wrt_enable: 1 241 | EX.nop: 0 242 | MEM.ALUresult: 01111111111111111111111111111101 243 | MEM.Store_data: 11111111111111111111111111111111 244 | MEM.Rs: 00100 245 | MEM.Rt: 00110 246 | MEM.Wrt_reg_addr: 00110 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 0 249 | MEM.wrt_enable: 1 250 | MEM.nop: 0 251 | WB.Wrt_data: 01111111111111111111111111111110 252 | WB.Rs: 00000 253 | WB.Rt: 00100 254 | WB.Wrt_reg_addr: 00100 255 | WB.wrt_enable: 0 256 | WB.nop: 0 257 | State after executing cycle: 8 258 | IF.PC: 32 259 | IF.nop: 1 260 | ID.Instr: 11111111111111111111111111111111 261 | ID.nop: 1 262 | EX.Read_data1: 00000000000000000000000000000000 263 | EX.Read_data2: 00000000000000000000000000000000 264 | EX.Imm: 0000000000001000 265 | EX.Rs: 00000 266 | EX.Rt: 00111 267 | EX.Wrt_reg_addr: 00111 268 | EX.is_I_type: 1 269 | EX.rd_mem: 0 270 | EX.wrt_mem: 1 271 | EX.alu_op: 1 272 | EX.wrt_enable: 0 273 | EX.nop: 0 274 | MEM.ALUresult: 01111111111111111111111111111110 275 | MEM.Store_data: 11111111111111111111111111111111 276 | MEM.Rs: 00110 277 | MEM.Rt: 00001 278 | MEM.Wrt_reg_addr: 00111 279 | MEM.rd_mem: 0 280 | MEM.wrt_mem: 0 281 | MEM.wrt_enable: 1 282 | MEM.nop: 0 283 | WB.Wrt_data: 01111111111111111111111111111101 284 | WB.Rs: 00100 285 | WB.Rt: 00110 286 | WB.Wrt_reg_addr: 00110 287 | WB.wrt_enable: 1 288 | WB.nop: 0 289 | State after executing cycle: 9 290 | IF.PC: 32 291 | IF.nop: 1 292 | ID.Instr: 11111111111111111111111111111111 293 | ID.nop: 1 294 | EX.Read_data1: 00000000000000000000000000000000 295 | EX.Read_data2: 00000000000000000000000000000000 296 | EX.Imm: 0000000000001000 297 | EX.Rs: 00000 298 | EX.Rt: 00111 299 | EX.Wrt_reg_addr: 00111 300 | EX.is_I_type: 1 301 | EX.rd_mem: 0 302 | EX.wrt_mem: 1 303 | EX.alu_op: 1 304 | EX.wrt_enable: 0 305 | EX.nop: 1 306 | MEM.ALUresult: 00000000000000000000000000001000 307 | MEM.Store_data: 00000000000000000000000000000000 308 | MEM.Rs: 00000 309 | MEM.Rt: 00111 310 | MEM.Wrt_reg_addr: 00111 311 | MEM.rd_mem: 0 312 | MEM.wrt_mem: 1 313 | MEM.wrt_enable: 0 314 | MEM.nop: 0 315 | WB.Wrt_data: 01111111111111111111111111111110 316 | WB.Rs: 00110 317 | WB.Rt: 00001 318 | WB.Wrt_reg_addr: 00111 319 | WB.wrt_enable: 1 320 | WB.nop: 0 321 | State after executing cycle: 10 322 | IF.PC: 32 323 | IF.nop: 1 324 | ID.Instr: 11111111111111111111111111111111 325 | ID.nop: 1 326 | EX.Read_data1: 00000000000000000000000000000000 327 | EX.Read_data2: 00000000000000000000000000000000 328 | EX.Imm: 0000000000001000 329 | EX.Rs: 00000 330 | EX.Rt: 00111 331 | EX.Wrt_reg_addr: 00111 332 | EX.is_I_type: 1 333 | EX.rd_mem: 0 334 | EX.wrt_mem: 1 335 | EX.alu_op: 1 336 | EX.wrt_enable: 0 337 | EX.nop: 1 338 | MEM.ALUresult: 00000000000000000000000000001000 339 | MEM.Store_data: 00000000000000000000000000000000 340 | MEM.Rs: 00000 341 | MEM.Rt: 00111 342 | MEM.Wrt_reg_addr: 00111 343 | MEM.rd_mem: 0 344 | MEM.wrt_mem: 1 345 | MEM.wrt_enable: 0 346 | MEM.nop: 1 347 | WB.Wrt_data: 01111111111111111111111111111110 348 | WB.Rs: 00000 349 | WB.Rt: 00111 350 | WB.Wrt_reg_addr: 00111 351 | WB.wrt_enable: 0 352 | WB.nop: 0 353 | State after executing cycle: 11 354 | IF.PC: 32 355 | IF.nop: 1 356 | ID.Instr: 11111111111111111111111111111111 357 | ID.nop: 1 358 | EX.Read_data1: 00000000000000000000000000000000 359 | EX.Read_data2: 00000000000000000000000000000000 360 | EX.Imm: 0000000000001000 361 | EX.Rs: 00000 362 | EX.Rt: 00111 363 | EX.Wrt_reg_addr: 00111 364 | EX.is_I_type: 1 365 | EX.rd_mem: 0 366 | EX.wrt_mem: 1 367 | EX.alu_op: 1 368 | EX.wrt_enable: 0 369 | EX.nop: 1 370 | MEM.ALUresult: 00000000000000000000000000001000 371 | MEM.Store_data: 00000000000000000000000000000000 372 | MEM.Rs: 00000 373 | MEM.Rt: 00111 374 | MEM.Wrt_reg_addr: 00111 375 | MEM.rd_mem: 0 376 | MEM.wrt_mem: 1 377 | MEM.wrt_enable: 0 378 | MEM.nop: 1 379 | WB.Wrt_data: 01111111111111111111111111111110 380 | WB.Rs: 00000 381 | WB.Rt: 00111 382 | WB.Wrt_reg_addr: 00111 383 | WB.wrt_enable: 0 384 | WB.nop: 1 385 | -------------------------------------------------------------------------------- /testcase/0-1/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 204 13 | EX.rd_mem: 204 14 | EX.wrt_mem: 204 15 | EX.alu_op: 204 16 | EX.wrt_enable: 204 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 204 24 | MEM.wrt_mem: 204 25 | MEM.wrt_enable: 204 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 204 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100000000100000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 204 56 | MEM.wrt_mem: 204 57 | MEM.wrt_enable: 204 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 204 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 00000001000010010011100000100001 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 204 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 16 99 | IF.nop: 0 100 | ID.Instr: 00000001000010010011100000100001 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000000000 103 | EX.Read_data2: 00000000000000000000000000000000 104 | EX.Imm: 0011100000100001 105 | EX.Rs: 01000 106 | EX.Rt: 01001 107 | EX.Wrt_reg_addr: 00111 108 | EX.is_I_type: 0 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00010 118 | MEM.Wrt_reg_addr: 00010 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 0 123 | WB.Wrt_data: 11111111111111111111111111111111 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 20 131 | IF.nop: 0 132 | ID.Instr: 00000000001000100001100000100001 133 | ID.nop: 0 134 | EX.Read_data1: 00000000000000000000000000000000 135 | EX.Read_data2: 00000000000000000000000000000000 136 | EX.Imm: 0011100000100001 137 | EX.Rs: 01000 138 | EX.Rt: 01001 139 | EX.Wrt_reg_addr: 00111 140 | EX.is_I_type: 0 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 0 146 | MEM.ALUresult: 00000000000000000000000000000000 147 | MEM.Store_data: 00000000000000000000000000000000 148 | MEM.Rs: 01000 149 | MEM.Rt: 01001 150 | MEM.Wrt_reg_addr: 00111 151 | MEM.rd_mem: 0 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 0 155 | WB.Wrt_data: 01111111111111111111111111111110 156 | WB.Rs: 00000 157 | WB.Rt: 00010 158 | WB.Wrt_reg_addr: 00010 159 | WB.wrt_enable: 1 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 24 163 | IF.nop: 0 164 | ID.Instr: 00000001000010010011100000100001 165 | ID.nop: 0 166 | EX.Read_data1: 11111111111111111111111111111111 167 | EX.Read_data2: 01111111111111111111111111111110 168 | EX.Imm: 0001100000100001 169 | EX.Rs: 00001 170 | EX.Rt: 00010 171 | EX.Wrt_reg_addr: 00011 172 | EX.is_I_type: 0 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 0 175 | EX.alu_op: 1 176 | EX.wrt_enable: 1 177 | EX.nop: 0 178 | MEM.ALUresult: 00000000000000000000000000000000 179 | MEM.Store_data: 00000000000000000000000000000000 180 | MEM.Rs: 01000 181 | MEM.Rt: 01001 182 | MEM.Wrt_reg_addr: 00111 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 0 187 | WB.Wrt_data: 00000000000000000000000000000000 188 | WB.Rs: 01000 189 | WB.Rt: 01001 190 | WB.Wrt_reg_addr: 00111 191 | WB.wrt_enable: 1 192 | WB.nop: 0 193 | State after executing cycle: 6 194 | IF.PC: 28 195 | IF.nop: 0 196 | ID.Instr: 00000001000010010011100000100001 197 | ID.nop: 0 198 | EX.Read_data1: 00000000000000000000000000000000 199 | EX.Read_data2: 00000000000000000000000000000000 200 | EX.Imm: 0011100000100001 201 | EX.Rs: 01000 202 | EX.Rt: 01001 203 | EX.Wrt_reg_addr: 00111 204 | EX.is_I_type: 0 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 0 207 | EX.alu_op: 1 208 | EX.wrt_enable: 1 209 | EX.nop: 0 210 | MEM.ALUresult: 01111111111111111111111111111101 211 | MEM.Store_data: 01111111111111111111111111111110 212 | MEM.Rs: 00001 213 | MEM.Rt: 00010 214 | MEM.Wrt_reg_addr: 00011 215 | MEM.rd_mem: 0 216 | MEM.wrt_mem: 0 217 | MEM.wrt_enable: 1 218 | MEM.nop: 0 219 | WB.Wrt_data: 00000000000000000000000000000000 220 | WB.Rs: 01000 221 | WB.Rt: 01001 222 | WB.Wrt_reg_addr: 00111 223 | WB.wrt_enable: 1 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 32 227 | IF.nop: 0 228 | ID.Instr: 10101100000000110000000000001000 229 | ID.nop: 0 230 | EX.Read_data1: 00000000000000000000000000000000 231 | EX.Read_data2: 00000000000000000000000000000000 232 | EX.Imm: 0011100000100001 233 | EX.Rs: 01000 234 | EX.Rt: 01001 235 | EX.Wrt_reg_addr: 00111 236 | EX.is_I_type: 0 237 | EX.rd_mem: 0 238 | EX.wrt_mem: 0 239 | EX.alu_op: 1 240 | EX.wrt_enable: 1 241 | EX.nop: 0 242 | MEM.ALUresult: 00000000000000000000000000000000 243 | MEM.Store_data: 00000000000000000000000000000000 244 | MEM.Rs: 01000 245 | MEM.Rt: 01001 246 | MEM.Wrt_reg_addr: 00111 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 0 249 | MEM.wrt_enable: 1 250 | MEM.nop: 0 251 | WB.Wrt_data: 01111111111111111111111111111101 252 | WB.Rs: 00001 253 | WB.Rt: 00010 254 | WB.Wrt_reg_addr: 00011 255 | WB.wrt_enable: 1 256 | WB.nop: 0 257 | State after executing cycle: 8 258 | IF.PC: 32 259 | IF.nop: 1 260 | ID.Instr: 11111111111111111111111111111111 261 | ID.nop: 1 262 | EX.Read_data1: 00000000000000000000000000000000 263 | EX.Read_data2: 01111111111111111111111111111101 264 | EX.Imm: 0000000000001000 265 | EX.Rs: 00000 266 | EX.Rt: 00011 267 | EX.Wrt_reg_addr: 00011 268 | EX.is_I_type: 1 269 | EX.rd_mem: 0 270 | EX.wrt_mem: 1 271 | EX.alu_op: 1 272 | EX.wrt_enable: 0 273 | EX.nop: 0 274 | MEM.ALUresult: 00000000000000000000000000000000 275 | MEM.Store_data: 00000000000000000000000000000000 276 | MEM.Rs: 01000 277 | MEM.Rt: 01001 278 | MEM.Wrt_reg_addr: 00111 279 | MEM.rd_mem: 0 280 | MEM.wrt_mem: 0 281 | MEM.wrt_enable: 1 282 | MEM.nop: 0 283 | WB.Wrt_data: 00000000000000000000000000000000 284 | WB.Rs: 01000 285 | WB.Rt: 01001 286 | WB.Wrt_reg_addr: 00111 287 | WB.wrt_enable: 1 288 | WB.nop: 0 289 | State after executing cycle: 9 290 | IF.PC: 32 291 | IF.nop: 1 292 | ID.Instr: 11111111111111111111111111111111 293 | ID.nop: 1 294 | EX.Read_data1: 00000000000000000000000000000000 295 | EX.Read_data2: 01111111111111111111111111111101 296 | EX.Imm: 0000000000001000 297 | EX.Rs: 00000 298 | EX.Rt: 00011 299 | EX.Wrt_reg_addr: 00011 300 | EX.is_I_type: 1 301 | EX.rd_mem: 0 302 | EX.wrt_mem: 1 303 | EX.alu_op: 1 304 | EX.wrt_enable: 0 305 | EX.nop: 1 306 | MEM.ALUresult: 00000000000000000000000000001000 307 | MEM.Store_data: 01111111111111111111111111111101 308 | MEM.Rs: 00000 309 | MEM.Rt: 00011 310 | MEM.Wrt_reg_addr: 00011 311 | MEM.rd_mem: 0 312 | MEM.wrt_mem: 1 313 | MEM.wrt_enable: 0 314 | MEM.nop: 0 315 | WB.Wrt_data: 00000000000000000000000000000000 316 | WB.Rs: 01000 317 | WB.Rt: 01001 318 | WB.Wrt_reg_addr: 00111 319 | WB.wrt_enable: 1 320 | WB.nop: 0 321 | State after executing cycle: 10 322 | IF.PC: 32 323 | IF.nop: 1 324 | ID.Instr: 11111111111111111111111111111111 325 | ID.nop: 1 326 | EX.Read_data1: 00000000000000000000000000000000 327 | EX.Read_data2: 01111111111111111111111111111101 328 | EX.Imm: 0000000000001000 329 | EX.Rs: 00000 330 | EX.Rt: 00011 331 | EX.Wrt_reg_addr: 00011 332 | EX.is_I_type: 1 333 | EX.rd_mem: 0 334 | EX.wrt_mem: 1 335 | EX.alu_op: 1 336 | EX.wrt_enable: 0 337 | EX.nop: 1 338 | MEM.ALUresult: 00000000000000000000000000001000 339 | MEM.Store_data: 01111111111111111111111111111101 340 | MEM.Rs: 00000 341 | MEM.Rt: 00011 342 | MEM.Wrt_reg_addr: 00011 343 | MEM.rd_mem: 0 344 | MEM.wrt_mem: 1 345 | MEM.wrt_enable: 0 346 | MEM.nop: 1 347 | WB.Wrt_data: 00000000000000000000000000001000 348 | WB.Rs: 00000 349 | WB.Rt: 00011 350 | WB.Wrt_reg_addr: 00011 351 | WB.wrt_enable: 0 352 | WB.nop: 0 353 | State after executing cycle: 11 354 | IF.PC: 32 355 | IF.nop: 1 356 | ID.Instr: 11111111111111111111111111111111 357 | ID.nop: 1 358 | EX.Read_data1: 00000000000000000000000000000000 359 | EX.Read_data2: 01111111111111111111111111111101 360 | EX.Imm: 0000000000001000 361 | EX.Rs: 00000 362 | EX.Rt: 00011 363 | EX.Wrt_reg_addr: 00011 364 | EX.is_I_type: 1 365 | EX.rd_mem: 0 366 | EX.wrt_mem: 1 367 | EX.alu_op: 1 368 | EX.wrt_enable: 0 369 | EX.nop: 1 370 | MEM.ALUresult: 00000000000000000000000000001000 371 | MEM.Store_data: 01111111111111111111111111111101 372 | MEM.Rs: 00000 373 | MEM.Rt: 00011 374 | MEM.Wrt_reg_addr: 00011 375 | MEM.rd_mem: 0 376 | MEM.wrt_mem: 1 377 | MEM.wrt_enable: 0 378 | MEM.nop: 1 379 | WB.Wrt_data: 00000000000000000000000000001000 380 | WB.Rs: 00000 381 | WB.Rt: 00011 382 | WB.Wrt_reg_addr: 00011 383 | WB.wrt_enable: 0 384 | WB.nop: 1 385 | -------------------------------------------------------------------------------- /testcase/0-2/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 204 13 | EX.rd_mem: 204 14 | EX.wrt_mem: 204 15 | EX.alu_op: 204 16 | EX.wrt_enable: 204 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 204 24 | MEM.wrt_mem: 204 25 | MEM.wrt_enable: 204 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 204 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100000000100000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 204 56 | MEM.wrt_mem: 204 57 | MEM.wrt_enable: 204 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 204 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 00000001000010010011100000100001 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 204 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 16 99 | IF.nop: 0 100 | ID.Instr: 00000001000010010011100000100001 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000000000 103 | EX.Read_data2: 00000000000000000000000000000000 104 | EX.Imm: 0011100000100001 105 | EX.Rs: 01000 106 | EX.Rt: 01001 107 | EX.Wrt_reg_addr: 00111 108 | EX.is_I_type: 0 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00010 118 | MEM.Wrt_reg_addr: 00010 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 0 123 | WB.Wrt_data: 11111111111111111111111111111111 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 20 131 | IF.nop: 0 132 | ID.Instr: 00000000001000100001100000100011 133 | ID.nop: 0 134 | EX.Read_data1: 00000000000000000000000000000000 135 | EX.Read_data2: 00000000000000000000000000000000 136 | EX.Imm: 0011100000100001 137 | EX.Rs: 01000 138 | EX.Rt: 01001 139 | EX.Wrt_reg_addr: 00111 140 | EX.is_I_type: 0 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 0 146 | MEM.ALUresult: 00000000000000000000000000000000 147 | MEM.Store_data: 00000000000000000000000000000000 148 | MEM.Rs: 01000 149 | MEM.Rt: 01001 150 | MEM.Wrt_reg_addr: 00111 151 | MEM.rd_mem: 0 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 0 155 | WB.Wrt_data: 01111111111111111111111111111110 156 | WB.Rs: 00000 157 | WB.Rt: 00010 158 | WB.Wrt_reg_addr: 00010 159 | WB.wrt_enable: 1 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 24 163 | IF.nop: 0 164 | ID.Instr: 00000001000010010011100000100001 165 | ID.nop: 0 166 | EX.Read_data1: 11111111111111111111111111111111 167 | EX.Read_data2: 01111111111111111111111111111110 168 | EX.Imm: 0001100000100011 169 | EX.Rs: 00001 170 | EX.Rt: 00010 171 | EX.Wrt_reg_addr: 00011 172 | EX.is_I_type: 0 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 0 175 | EX.alu_op: 0 176 | EX.wrt_enable: 1 177 | EX.nop: 0 178 | MEM.ALUresult: 00000000000000000000000000000000 179 | MEM.Store_data: 00000000000000000000000000000000 180 | MEM.Rs: 01000 181 | MEM.Rt: 01001 182 | MEM.Wrt_reg_addr: 00111 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 0 187 | WB.Wrt_data: 00000000000000000000000000000000 188 | WB.Rs: 01000 189 | WB.Rt: 01001 190 | WB.Wrt_reg_addr: 00111 191 | WB.wrt_enable: 1 192 | WB.nop: 0 193 | State after executing cycle: 6 194 | IF.PC: 28 195 | IF.nop: 0 196 | ID.Instr: 00000001000010010011100000100001 197 | ID.nop: 0 198 | EX.Read_data1: 00000000000000000000000000000000 199 | EX.Read_data2: 00000000000000000000000000000000 200 | EX.Imm: 0011100000100001 201 | EX.Rs: 01000 202 | EX.Rt: 01001 203 | EX.Wrt_reg_addr: 00111 204 | EX.is_I_type: 0 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 0 207 | EX.alu_op: 1 208 | EX.wrt_enable: 1 209 | EX.nop: 0 210 | MEM.ALUresult: 10000000000000000000000000000001 211 | MEM.Store_data: 01111111111111111111111111111110 212 | MEM.Rs: 00001 213 | MEM.Rt: 00010 214 | MEM.Wrt_reg_addr: 00011 215 | MEM.rd_mem: 0 216 | MEM.wrt_mem: 0 217 | MEM.wrt_enable: 1 218 | MEM.nop: 0 219 | WB.Wrt_data: 00000000000000000000000000000000 220 | WB.Rs: 01000 221 | WB.Rt: 01001 222 | WB.Wrt_reg_addr: 00111 223 | WB.wrt_enable: 1 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 32 227 | IF.nop: 0 228 | ID.Instr: 10101100000000110000000000001000 229 | ID.nop: 0 230 | EX.Read_data1: 00000000000000000000000000000000 231 | EX.Read_data2: 00000000000000000000000000000000 232 | EX.Imm: 0011100000100001 233 | EX.Rs: 01000 234 | EX.Rt: 01001 235 | EX.Wrt_reg_addr: 00111 236 | EX.is_I_type: 0 237 | EX.rd_mem: 0 238 | EX.wrt_mem: 0 239 | EX.alu_op: 1 240 | EX.wrt_enable: 1 241 | EX.nop: 0 242 | MEM.ALUresult: 00000000000000000000000000000000 243 | MEM.Store_data: 00000000000000000000000000000000 244 | MEM.Rs: 01000 245 | MEM.Rt: 01001 246 | MEM.Wrt_reg_addr: 00111 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 0 249 | MEM.wrt_enable: 1 250 | MEM.nop: 0 251 | WB.Wrt_data: 10000000000000000000000000000001 252 | WB.Rs: 00001 253 | WB.Rt: 00010 254 | WB.Wrt_reg_addr: 00011 255 | WB.wrt_enable: 1 256 | WB.nop: 0 257 | State after executing cycle: 8 258 | IF.PC: 32 259 | IF.nop: 1 260 | ID.Instr: 11111111111111111111111111111111 261 | ID.nop: 1 262 | EX.Read_data1: 00000000000000000000000000000000 263 | EX.Read_data2: 10000000000000000000000000000001 264 | EX.Imm: 0000000000001000 265 | EX.Rs: 00000 266 | EX.Rt: 00011 267 | EX.Wrt_reg_addr: 00011 268 | EX.is_I_type: 1 269 | EX.rd_mem: 0 270 | EX.wrt_mem: 1 271 | EX.alu_op: 1 272 | EX.wrt_enable: 0 273 | EX.nop: 0 274 | MEM.ALUresult: 00000000000000000000000000000000 275 | MEM.Store_data: 00000000000000000000000000000000 276 | MEM.Rs: 01000 277 | MEM.Rt: 01001 278 | MEM.Wrt_reg_addr: 00111 279 | MEM.rd_mem: 0 280 | MEM.wrt_mem: 0 281 | MEM.wrt_enable: 1 282 | MEM.nop: 0 283 | WB.Wrt_data: 00000000000000000000000000000000 284 | WB.Rs: 01000 285 | WB.Rt: 01001 286 | WB.Wrt_reg_addr: 00111 287 | WB.wrt_enable: 1 288 | WB.nop: 0 289 | State after executing cycle: 9 290 | IF.PC: 32 291 | IF.nop: 1 292 | ID.Instr: 11111111111111111111111111111111 293 | ID.nop: 1 294 | EX.Read_data1: 00000000000000000000000000000000 295 | EX.Read_data2: 10000000000000000000000000000001 296 | EX.Imm: 0000000000001000 297 | EX.Rs: 00000 298 | EX.Rt: 00011 299 | EX.Wrt_reg_addr: 00011 300 | EX.is_I_type: 1 301 | EX.rd_mem: 0 302 | EX.wrt_mem: 1 303 | EX.alu_op: 1 304 | EX.wrt_enable: 0 305 | EX.nop: 1 306 | MEM.ALUresult: 00000000000000000000000000001000 307 | MEM.Store_data: 10000000000000000000000000000001 308 | MEM.Rs: 00000 309 | MEM.Rt: 00011 310 | MEM.Wrt_reg_addr: 00011 311 | MEM.rd_mem: 0 312 | MEM.wrt_mem: 1 313 | MEM.wrt_enable: 0 314 | MEM.nop: 0 315 | WB.Wrt_data: 00000000000000000000000000000000 316 | WB.Rs: 01000 317 | WB.Rt: 01001 318 | WB.Wrt_reg_addr: 00111 319 | WB.wrt_enable: 1 320 | WB.nop: 0 321 | State after executing cycle: 10 322 | IF.PC: 32 323 | IF.nop: 1 324 | ID.Instr: 11111111111111111111111111111111 325 | ID.nop: 1 326 | EX.Read_data1: 00000000000000000000000000000000 327 | EX.Read_data2: 10000000000000000000000000000001 328 | EX.Imm: 0000000000001000 329 | EX.Rs: 00000 330 | EX.Rt: 00011 331 | EX.Wrt_reg_addr: 00011 332 | EX.is_I_type: 1 333 | EX.rd_mem: 0 334 | EX.wrt_mem: 1 335 | EX.alu_op: 1 336 | EX.wrt_enable: 0 337 | EX.nop: 1 338 | MEM.ALUresult: 00000000000000000000000000001000 339 | MEM.Store_data: 10000000000000000000000000000001 340 | MEM.Rs: 00000 341 | MEM.Rt: 00011 342 | MEM.Wrt_reg_addr: 00011 343 | MEM.rd_mem: 0 344 | MEM.wrt_mem: 1 345 | MEM.wrt_enable: 0 346 | MEM.nop: 1 347 | WB.Wrt_data: 00000000000000000000000000001000 348 | WB.Rs: 00000 349 | WB.Rt: 00011 350 | WB.Wrt_reg_addr: 00011 351 | WB.wrt_enable: 0 352 | WB.nop: 0 353 | State after executing cycle: 11 354 | IF.PC: 32 355 | IF.nop: 1 356 | ID.Instr: 11111111111111111111111111111111 357 | ID.nop: 1 358 | EX.Read_data1: 00000000000000000000000000000000 359 | EX.Read_data2: 10000000000000000000000000000001 360 | EX.Imm: 0000000000001000 361 | EX.Rs: 00000 362 | EX.Rt: 00011 363 | EX.Wrt_reg_addr: 00011 364 | EX.is_I_type: 1 365 | EX.rd_mem: 0 366 | EX.wrt_mem: 1 367 | EX.alu_op: 1 368 | EX.wrt_enable: 0 369 | EX.nop: 1 370 | MEM.ALUresult: 00000000000000000000000000001000 371 | MEM.Store_data: 10000000000000000000000000000001 372 | MEM.Rs: 00000 373 | MEM.Rt: 00011 374 | MEM.Wrt_reg_addr: 00011 375 | MEM.rd_mem: 0 376 | MEM.wrt_mem: 1 377 | MEM.wrt_enable: 0 378 | MEM.nop: 1 379 | WB.Wrt_data: 00000000000000000000000000001000 380 | WB.Rs: 00000 381 | WB.Rt: 00011 382 | WB.Wrt_reg_addr: 00011 383 | WB.wrt_enable: 0 384 | WB.nop: 1 385 | -------------------------------------------------------------------------------- /testcase/3-3/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 0 13 | EX.rd_mem: 0 14 | EX.wrt_mem: 0 15 | EX.alu_op: 1 16 | EX.wrt_enable: 0 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 0 24 | MEM.wrt_mem: 0 25 | MEM.wrt_enable: 0 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 0 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100000000100000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 0 56 | MEM.wrt_mem: 0 57 | MEM.wrt_enable: 0 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 0 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 00000000001000100011000000100001 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 0 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 12 99 | IF.nop: 0 100 | ID.Instr: 00000000001000100011000000100001 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000000000 103 | EX.Read_data2: 00000000000000000000000000000000 104 | EX.Imm: 0011000000100001 105 | EX.Rs: 00001 106 | EX.Rt: 00010 107 | EX.Wrt_reg_addr: 00110 108 | EX.is_I_type: 0 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 1 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00010 118 | MEM.Wrt_reg_addr: 00010 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 0 123 | WB.Wrt_data: 11111111111111111111111111111111 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 16 131 | IF.nop: 0 132 | ID.Instr: 10001100000001000000000000000100 133 | ID.nop: 0 134 | EX.Read_data1: 11111111111111111111111111111111 135 | EX.Read_data2: 00000000000000000000000000000000 136 | EX.Imm: 0011000000100001 137 | EX.Rs: 00001 138 | EX.Rt: 00010 139 | EX.Wrt_reg_addr: 00110 140 | EX.is_I_type: 0 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 0 146 | MEM.ALUresult: 00000000000000000000000000000100 147 | MEM.Store_data: 00000000000000000000000000000000 148 | MEM.Rs: 00000 149 | MEM.Rt: 00010 150 | MEM.Wrt_reg_addr: 00010 151 | MEM.rd_mem: 1 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 1 155 | WB.Wrt_data: 01111111111111111111111111111110 156 | WB.Rs: 00000 157 | WB.Rt: 00010 158 | WB.Wrt_reg_addr: 00010 159 | WB.wrt_enable: 1 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 20 163 | IF.nop: 0 164 | ID.Instr: 10101100000001000000000000000000 165 | ID.nop: 0 166 | EX.Read_data1: 00000000000000000000000000000000 167 | EX.Read_data2: 00000000000000000000000000000000 168 | EX.Imm: 0000000000000100 169 | EX.Rs: 00000 170 | EX.Rt: 00100 171 | EX.Wrt_reg_addr: 00100 172 | EX.is_I_type: 1 173 | EX.rd_mem: 1 174 | EX.wrt_mem: 0 175 | EX.alu_op: 1 176 | EX.wrt_enable: 1 177 | EX.nop: 0 178 | MEM.ALUresult: 01111111111111111111111111111101 179 | MEM.Store_data: 01111111111111111111111111111110 180 | MEM.Rs: 00001 181 | MEM.Rt: 00010 182 | MEM.Wrt_reg_addr: 00110 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 0 187 | WB.Wrt_data: 01111111111111111111111111111110 188 | WB.Rs: 00000 189 | WB.Rt: 00010 190 | WB.Wrt_reg_addr: 00010 191 | WB.wrt_enable: 1 192 | WB.nop: 1 193 | State after executing cycle: 6 194 | IF.PC: 24 195 | IF.nop: 0 196 | ID.Instr: 00000000100001100011000000100001 197 | ID.nop: 0 198 | EX.Read_data1: 00000000000000000000000000000000 199 | EX.Read_data2: 00000000000000000000000000000000 200 | EX.Imm: 0000000000000000 201 | EX.Rs: 00000 202 | EX.Rt: 00100 203 | EX.Wrt_reg_addr: 00100 204 | EX.is_I_type: 1 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 1 207 | EX.alu_op: 1 208 | EX.wrt_enable: 0 209 | EX.nop: 0 210 | MEM.ALUresult: 00000000000000000000000000000100 211 | MEM.Store_data: 00000000000000000000000000000000 212 | MEM.Rs: 00000 213 | MEM.Rt: 00100 214 | MEM.Wrt_reg_addr: 00100 215 | MEM.rd_mem: 1 216 | MEM.wrt_mem: 0 217 | MEM.wrt_enable: 1 218 | MEM.nop: 0 219 | WB.Wrt_data: 01111111111111111111111111111101 220 | WB.Rs: 00001 221 | WB.Rt: 00010 222 | WB.Wrt_reg_addr: 00110 223 | WB.wrt_enable: 1 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 28 227 | IF.nop: 0 228 | ID.Instr: 00000000110000010011100000100011 229 | ID.nop: 0 230 | EX.Read_data1: 00000000000000000000000000000000 231 | EX.Read_data2: 01111111111111111111111111111101 232 | EX.Imm: 0011000000100001 233 | EX.Rs: 00100 234 | EX.Rt: 00110 235 | EX.Wrt_reg_addr: 00110 236 | EX.is_I_type: 0 237 | EX.rd_mem: 0 238 | EX.wrt_mem: 0 239 | EX.alu_op: 1 240 | EX.wrt_enable: 1 241 | EX.nop: 0 242 | MEM.ALUresult: 00000000000000000000000000000000 243 | MEM.Store_data: 00000000000000000000000000000000 244 | MEM.Rs: 00000 245 | MEM.Rt: 00100 246 | MEM.Wrt_reg_addr: 00100 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 1 249 | MEM.wrt_enable: 0 250 | MEM.nop: 0 251 | WB.Wrt_data: 01111111111111111111111111111110 252 | WB.Rs: 00000 253 | WB.Rt: 00100 254 | WB.Wrt_reg_addr: 00100 255 | WB.wrt_enable: 1 256 | WB.nop: 0 257 | State after executing cycle: 8 258 | IF.PC: 32 259 | IF.nop: 0 260 | ID.Instr: 10101100000001110000000000001000 261 | ID.nop: 0 262 | EX.Read_data1: 01111111111111111111111111111101 263 | EX.Read_data2: 11111111111111111111111111111111 264 | EX.Imm: 0011100000100011 265 | EX.Rs: 00110 266 | EX.Rt: 00001 267 | EX.Wrt_reg_addr: 00111 268 | EX.is_I_type: 0 269 | EX.rd_mem: 0 270 | EX.wrt_mem: 0 271 | EX.alu_op: 0 272 | EX.wrt_enable: 1 273 | EX.nop: 0 274 | MEM.ALUresult: 11111111111111111111111111111011 275 | MEM.Store_data: 01111111111111111111111111111101 276 | MEM.Rs: 00100 277 | MEM.Rt: 00110 278 | MEM.Wrt_reg_addr: 00110 279 | MEM.rd_mem: 0 280 | MEM.wrt_mem: 0 281 | MEM.wrt_enable: 1 282 | MEM.nop: 0 283 | WB.Wrt_data: 01111111111111111111111111111110 284 | WB.Rs: 00000 285 | WB.Rt: 00100 286 | WB.Wrt_reg_addr: 00100 287 | WB.wrt_enable: 0 288 | WB.nop: 0 289 | State after executing cycle: 9 290 | IF.PC: 32 291 | IF.nop: 1 292 | ID.Instr: 11111111111111111111111111111111 293 | ID.nop: 1 294 | EX.Read_data1: 00000000000000000000000000000000 295 | EX.Read_data2: 00000000000000000000000000000000 296 | EX.Imm: 0000000000001000 297 | EX.Rs: 00000 298 | EX.Rt: 00111 299 | EX.Wrt_reg_addr: 00111 300 | EX.is_I_type: 1 301 | EX.rd_mem: 0 302 | EX.wrt_mem: 1 303 | EX.alu_op: 1 304 | EX.wrt_enable: 0 305 | EX.nop: 0 306 | MEM.ALUresult: 11111111111111111111111111111100 307 | MEM.Store_data: 11111111111111111111111111111111 308 | MEM.Rs: 00110 309 | MEM.Rt: 00001 310 | MEM.Wrt_reg_addr: 00111 311 | MEM.rd_mem: 0 312 | MEM.wrt_mem: 0 313 | MEM.wrt_enable: 1 314 | MEM.nop: 0 315 | WB.Wrt_data: 11111111111111111111111111111011 316 | WB.Rs: 00100 317 | WB.Rt: 00110 318 | WB.Wrt_reg_addr: 00110 319 | WB.wrt_enable: 1 320 | WB.nop: 0 321 | State after executing cycle: 10 322 | IF.PC: 32 323 | IF.nop: 1 324 | ID.Instr: 11111111111111111111111111111111 325 | ID.nop: 1 326 | EX.Read_data1: 00000000000000000000000000000000 327 | EX.Read_data2: 00000000000000000000000000000000 328 | EX.Imm: 0000000000001000 329 | EX.Rs: 00000 330 | EX.Rt: 00111 331 | EX.Wrt_reg_addr: 00111 332 | EX.is_I_type: 1 333 | EX.rd_mem: 0 334 | EX.wrt_mem: 1 335 | EX.alu_op: 1 336 | EX.wrt_enable: 0 337 | EX.nop: 1 338 | MEM.ALUresult: 00000000000000000000000000001000 339 | MEM.Store_data: 00000000000000000000000000000000 340 | MEM.Rs: 00000 341 | MEM.Rt: 00111 342 | MEM.Wrt_reg_addr: 00111 343 | MEM.rd_mem: 0 344 | MEM.wrt_mem: 1 345 | MEM.wrt_enable: 0 346 | MEM.nop: 0 347 | WB.Wrt_data: 11111111111111111111111111111100 348 | WB.Rs: 00110 349 | WB.Rt: 00001 350 | WB.Wrt_reg_addr: 00111 351 | WB.wrt_enable: 1 352 | WB.nop: 0 353 | State after executing cycle: 11 354 | IF.PC: 32 355 | IF.nop: 1 356 | ID.Instr: 11111111111111111111111111111111 357 | ID.nop: 1 358 | EX.Read_data1: 00000000000000000000000000000000 359 | EX.Read_data2: 00000000000000000000000000000000 360 | EX.Imm: 0000000000001000 361 | EX.Rs: 00000 362 | EX.Rt: 00111 363 | EX.Wrt_reg_addr: 00111 364 | EX.is_I_type: 1 365 | EX.rd_mem: 0 366 | EX.wrt_mem: 1 367 | EX.alu_op: 1 368 | EX.wrt_enable: 0 369 | EX.nop: 1 370 | MEM.ALUresult: 00000000000000000000000000001000 371 | MEM.Store_data: 00000000000000000000000000000000 372 | MEM.Rs: 00000 373 | MEM.Rt: 00111 374 | MEM.Wrt_reg_addr: 00111 375 | MEM.rd_mem: 0 376 | MEM.wrt_mem: 1 377 | MEM.wrt_enable: 0 378 | MEM.nop: 1 379 | WB.Wrt_data: 11111111111111111111111111111100 380 | WB.Rs: 00000 381 | WB.Rt: 00111 382 | WB.Wrt_reg_addr: 00111 383 | WB.wrt_enable: 0 384 | WB.nop: 0 385 | State after executing cycle: 12 386 | IF.PC: 32 387 | IF.nop: 1 388 | ID.Instr: 11111111111111111111111111111111 389 | ID.nop: 1 390 | EX.Read_data1: 00000000000000000000000000000000 391 | EX.Read_data2: 00000000000000000000000000000000 392 | EX.Imm: 0000000000001000 393 | EX.Rs: 00000 394 | EX.Rt: 00111 395 | EX.Wrt_reg_addr: 00111 396 | EX.is_I_type: 1 397 | EX.rd_mem: 0 398 | EX.wrt_mem: 1 399 | EX.alu_op: 1 400 | EX.wrt_enable: 0 401 | EX.nop: 1 402 | MEM.ALUresult: 00000000000000000000000000001000 403 | MEM.Store_data: 00000000000000000000000000000000 404 | MEM.Rs: 00000 405 | MEM.Rt: 00111 406 | MEM.Wrt_reg_addr: 00111 407 | MEM.rd_mem: 0 408 | MEM.wrt_mem: 1 409 | MEM.wrt_enable: 0 410 | MEM.nop: 1 411 | WB.Wrt_data: 11111111111111111111111111111100 412 | WB.Rs: 00000 413 | WB.Rt: 00111 414 | WB.Wrt_reg_addr: 00111 415 | WB.wrt_enable: 0 416 | WB.nop: 1 417 | -------------------------------------------------------------------------------- /testcase/1-2/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 204 13 | EX.rd_mem: 204 14 | EX.wrt_mem: 204 15 | EX.alu_op: 204 16 | EX.wrt_enable: 204 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 204 24 | MEM.wrt_mem: 204 25 | MEM.wrt_enable: 204 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 204 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100000000100000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 204 56 | MEM.wrt_mem: 204 57 | MEM.wrt_enable: 204 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 204 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 00000001000010010011100000100001 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 204 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 16 99 | IF.nop: 0 100 | ID.Instr: 00000001000010010011100000100001 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000000000 103 | EX.Read_data2: 00000000000000000000000000000000 104 | EX.Imm: 0011100000100001 105 | EX.Rs: 01000 106 | EX.Rt: 01001 107 | EX.Wrt_reg_addr: 00111 108 | EX.is_I_type: 0 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00010 118 | MEM.Wrt_reg_addr: 00010 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 0 123 | WB.Wrt_data: 00000000000000000000000000000001 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 20 131 | IF.nop: 0 132 | ID.Instr: 00000000001000100001100000100001 133 | ID.nop: 0 134 | EX.Read_data1: 00000000000000000000000000000000 135 | EX.Read_data2: 00000000000000000000000000000000 136 | EX.Imm: 0011100000100001 137 | EX.Rs: 01000 138 | EX.Rt: 01001 139 | EX.Wrt_reg_addr: 00111 140 | EX.is_I_type: 0 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 0 146 | MEM.ALUresult: 00000000000000000000000000000000 147 | MEM.Store_data: 00000000000000000000000000000000 148 | MEM.Rs: 01000 149 | MEM.Rt: 01001 150 | MEM.Wrt_reg_addr: 00111 151 | MEM.rd_mem: 0 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 0 155 | WB.Wrt_data: 00000000000000000000000000000010 156 | WB.Rs: 00000 157 | WB.Rt: 00010 158 | WB.Wrt_reg_addr: 00010 159 | WB.wrt_enable: 1 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 24 163 | IF.nop: 0 164 | ID.Instr: 00000001000010010011100000100001 165 | ID.nop: 0 166 | EX.Read_data1: 00000000000000000000000000000001 167 | EX.Read_data2: 00000000000000000000000000000010 168 | EX.Imm: 0001100000100001 169 | EX.Rs: 00001 170 | EX.Rt: 00010 171 | EX.Wrt_reg_addr: 00011 172 | EX.is_I_type: 0 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 0 175 | EX.alu_op: 1 176 | EX.wrt_enable: 1 177 | EX.nop: 0 178 | MEM.ALUresult: 00000000000000000000000000000000 179 | MEM.Store_data: 00000000000000000000000000000000 180 | MEM.Rs: 01000 181 | MEM.Rt: 01001 182 | MEM.Wrt_reg_addr: 00111 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 0 187 | WB.Wrt_data: 00000000000000000000000000000000 188 | WB.Rs: 01000 189 | WB.Rt: 01001 190 | WB.Wrt_reg_addr: 00111 191 | WB.wrt_enable: 1 192 | WB.nop: 0 193 | State after executing cycle: 6 194 | IF.PC: 28 195 | IF.nop: 0 196 | ID.Instr: 00000000011000100010000000100001 197 | ID.nop: 0 198 | EX.Read_data1: 00000000000000000000000000000000 199 | EX.Read_data2: 00000000000000000000000000000000 200 | EX.Imm: 0011100000100001 201 | EX.Rs: 01000 202 | EX.Rt: 01001 203 | EX.Wrt_reg_addr: 00111 204 | EX.is_I_type: 0 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 0 207 | EX.alu_op: 1 208 | EX.wrt_enable: 1 209 | EX.nop: 0 210 | MEM.ALUresult: 00000000000000000000000000000011 211 | MEM.Store_data: 00000000000000000000000000000010 212 | MEM.Rs: 00001 213 | MEM.Rt: 00010 214 | MEM.Wrt_reg_addr: 00011 215 | MEM.rd_mem: 0 216 | MEM.wrt_mem: 0 217 | MEM.wrt_enable: 1 218 | MEM.nop: 0 219 | WB.Wrt_data: 00000000000000000000000000000000 220 | WB.Rs: 01000 221 | WB.Rt: 01001 222 | WB.Wrt_reg_addr: 00111 223 | WB.wrt_enable: 1 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 32 227 | IF.nop: 0 228 | ID.Instr: 00000001000010010011100000100001 229 | ID.nop: 0 230 | EX.Read_data1: 00000000000000000000000000000011 231 | EX.Read_data2: 00000000000000000000000000000010 232 | EX.Imm: 0010000000100001 233 | EX.Rs: 00011 234 | EX.Rt: 00010 235 | EX.Wrt_reg_addr: 00100 236 | EX.is_I_type: 0 237 | EX.rd_mem: 0 238 | EX.wrt_mem: 0 239 | EX.alu_op: 1 240 | EX.wrt_enable: 1 241 | EX.nop: 0 242 | MEM.ALUresult: 00000000000000000000000000000000 243 | MEM.Store_data: 00000000000000000000000000000000 244 | MEM.Rs: 01000 245 | MEM.Rt: 01001 246 | MEM.Wrt_reg_addr: 00111 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 0 249 | MEM.wrt_enable: 1 250 | MEM.nop: 0 251 | WB.Wrt_data: 00000000000000000000000000000011 252 | WB.Rs: 00001 253 | WB.Rt: 00010 254 | WB.Wrt_reg_addr: 00011 255 | WB.wrt_enable: 1 256 | WB.nop: 0 257 | State after executing cycle: 8 258 | IF.PC: 36 259 | IF.nop: 0 260 | ID.Instr: 00000000001001000010100000100001 261 | ID.nop: 0 262 | EX.Read_data1: 00000000000000000000000000000000 263 | EX.Read_data2: 00000000000000000000000000000000 264 | EX.Imm: 0011100000100001 265 | EX.Rs: 01000 266 | EX.Rt: 01001 267 | EX.Wrt_reg_addr: 00111 268 | EX.is_I_type: 0 269 | EX.rd_mem: 0 270 | EX.wrt_mem: 0 271 | EX.alu_op: 1 272 | EX.wrt_enable: 1 273 | EX.nop: 0 274 | MEM.ALUresult: 00000000000000000000000000000101 275 | MEM.Store_data: 00000000000000000000000000000010 276 | MEM.Rs: 00011 277 | MEM.Rt: 00010 278 | MEM.Wrt_reg_addr: 00100 279 | MEM.rd_mem: 0 280 | MEM.wrt_mem: 0 281 | MEM.wrt_enable: 1 282 | MEM.nop: 0 283 | WB.Wrt_data: 00000000000000000000000000000000 284 | WB.Rs: 01000 285 | WB.Rt: 01001 286 | WB.Wrt_reg_addr: 00111 287 | WB.wrt_enable: 1 288 | WB.nop: 0 289 | State after executing cycle: 9 290 | IF.PC: 36 291 | IF.nop: 1 292 | ID.Instr: 11111111111111111111111111111111 293 | ID.nop: 1 294 | EX.Read_data1: 00000000000000000000000000000001 295 | EX.Read_data2: 00000000000000000000000000000101 296 | EX.Imm: 0010100000100001 297 | EX.Rs: 00001 298 | EX.Rt: 00100 299 | EX.Wrt_reg_addr: 00101 300 | EX.is_I_type: 0 301 | EX.rd_mem: 0 302 | EX.wrt_mem: 0 303 | EX.alu_op: 1 304 | EX.wrt_enable: 1 305 | EX.nop: 0 306 | MEM.ALUresult: 00000000000000000000000000000000 307 | MEM.Store_data: 00000000000000000000000000000000 308 | MEM.Rs: 01000 309 | MEM.Rt: 01001 310 | MEM.Wrt_reg_addr: 00111 311 | MEM.rd_mem: 0 312 | MEM.wrt_mem: 0 313 | MEM.wrt_enable: 1 314 | MEM.nop: 0 315 | WB.Wrt_data: 00000000000000000000000000000101 316 | WB.Rs: 00011 317 | WB.Rt: 00010 318 | WB.Wrt_reg_addr: 00100 319 | WB.wrt_enable: 1 320 | WB.nop: 0 321 | State after executing cycle: 10 322 | IF.PC: 36 323 | IF.nop: 1 324 | ID.Instr: 11111111111111111111111111111111 325 | ID.nop: 1 326 | EX.Read_data1: 00000000000000000000000000000001 327 | EX.Read_data2: 00000000000000000000000000000101 328 | EX.Imm: 0010100000100001 329 | EX.Rs: 00001 330 | EX.Rt: 00100 331 | EX.Wrt_reg_addr: 00101 332 | EX.is_I_type: 0 333 | EX.rd_mem: 0 334 | EX.wrt_mem: 0 335 | EX.alu_op: 1 336 | EX.wrt_enable: 1 337 | EX.nop: 1 338 | MEM.ALUresult: 00000000000000000000000000000110 339 | MEM.Store_data: 00000000000000000000000000000101 340 | MEM.Rs: 00001 341 | MEM.Rt: 00100 342 | MEM.Wrt_reg_addr: 00101 343 | MEM.rd_mem: 0 344 | MEM.wrt_mem: 0 345 | MEM.wrt_enable: 1 346 | MEM.nop: 0 347 | WB.Wrt_data: 00000000000000000000000000000000 348 | WB.Rs: 01000 349 | WB.Rt: 01001 350 | WB.Wrt_reg_addr: 00111 351 | WB.wrt_enable: 1 352 | WB.nop: 0 353 | State after executing cycle: 11 354 | IF.PC: 36 355 | IF.nop: 1 356 | ID.Instr: 11111111111111111111111111111111 357 | ID.nop: 1 358 | EX.Read_data1: 00000000000000000000000000000001 359 | EX.Read_data2: 00000000000000000000000000000101 360 | EX.Imm: 0010100000100001 361 | EX.Rs: 00001 362 | EX.Rt: 00100 363 | EX.Wrt_reg_addr: 00101 364 | EX.is_I_type: 0 365 | EX.rd_mem: 0 366 | EX.wrt_mem: 0 367 | EX.alu_op: 1 368 | EX.wrt_enable: 1 369 | EX.nop: 1 370 | MEM.ALUresult: 00000000000000000000000000000110 371 | MEM.Store_data: 00000000000000000000000000000101 372 | MEM.Rs: 00001 373 | MEM.Rt: 00100 374 | MEM.Wrt_reg_addr: 00101 375 | MEM.rd_mem: 0 376 | MEM.wrt_mem: 0 377 | MEM.wrt_enable: 1 378 | MEM.nop: 1 379 | WB.Wrt_data: 00000000000000000000000000000110 380 | WB.Rs: 00001 381 | WB.Rt: 00100 382 | WB.Wrt_reg_addr: 00101 383 | WB.wrt_enable: 1 384 | WB.nop: 0 385 | State after executing cycle: 12 386 | IF.PC: 36 387 | IF.nop: 1 388 | ID.Instr: 11111111111111111111111111111111 389 | ID.nop: 1 390 | EX.Read_data1: 00000000000000000000000000000001 391 | EX.Read_data2: 00000000000000000000000000000101 392 | EX.Imm: 0010100000100001 393 | EX.Rs: 00001 394 | EX.Rt: 00100 395 | EX.Wrt_reg_addr: 00101 396 | EX.is_I_type: 0 397 | EX.rd_mem: 0 398 | EX.wrt_mem: 0 399 | EX.alu_op: 1 400 | EX.wrt_enable: 1 401 | EX.nop: 1 402 | MEM.ALUresult: 00000000000000000000000000000110 403 | MEM.Store_data: 00000000000000000000000000000101 404 | MEM.Rs: 00001 405 | MEM.Rt: 00100 406 | MEM.Wrt_reg_addr: 00101 407 | MEM.rd_mem: 0 408 | MEM.wrt_mem: 0 409 | MEM.wrt_enable: 1 410 | MEM.nop: 1 411 | WB.Wrt_data: 00000000000000000000000000000110 412 | WB.Rs: 00001 413 | WB.Rt: 00100 414 | WB.Wrt_reg_addr: 00101 415 | WB.wrt_enable: 1 416 | WB.nop: 1 417 | -------------------------------------------------------------------------------- /testcase/1-5/stateresult_ans.txt: -------------------------------------------------------------------------------- 1 | State after executing cycle: 0 2 | IF.PC: 4 3 | IF.nop: 0 4 | ID.Instr: 10001100000000010000000000000000 5 | ID.nop: 0 6 | EX.Read_data1: 00000000000000000000000000000000 7 | EX.Read_data2: 00000000000000000000000000000000 8 | EX.Imm: 0000000000000000 9 | EX.Rs: 00000 10 | EX.Rt: 00000 11 | EX.Wrt_reg_addr: 00000 12 | EX.is_I_type: 204 13 | EX.rd_mem: 204 14 | EX.wrt_mem: 204 15 | EX.alu_op: 204 16 | EX.wrt_enable: 204 17 | EX.nop: 1 18 | MEM.ALUresult: 00000000000000000000000000000000 19 | MEM.Store_data: 00000000000000000000000000000000 20 | MEM.Rs: 00000 21 | MEM.Rt: 00000 22 | MEM.Wrt_reg_addr: 00000 23 | MEM.rd_mem: 204 24 | MEM.wrt_mem: 204 25 | MEM.wrt_enable: 204 26 | MEM.nop: 1 27 | WB.Wrt_data: 00000000000000000000000000000000 28 | WB.Rs: 00000 29 | WB.Rt: 00000 30 | WB.Wrt_reg_addr: 00000 31 | WB.wrt_enable: 204 32 | WB.nop: 1 33 | State after executing cycle: 1 34 | IF.PC: 8 35 | IF.nop: 0 36 | ID.Instr: 10001100000000100000000000000100 37 | ID.nop: 0 38 | EX.Read_data1: 00000000000000000000000000000000 39 | EX.Read_data2: 00000000000000000000000000000000 40 | EX.Imm: 0000000000000000 41 | EX.Rs: 00000 42 | EX.Rt: 00001 43 | EX.Wrt_reg_addr: 00001 44 | EX.is_I_type: 1 45 | EX.rd_mem: 1 46 | EX.wrt_mem: 0 47 | EX.alu_op: 1 48 | EX.wrt_enable: 1 49 | EX.nop: 0 50 | MEM.ALUresult: 00000000000000000000000000000000 51 | MEM.Store_data: 00000000000000000000000000000000 52 | MEM.Rs: 00000 53 | MEM.Rt: 00000 54 | MEM.Wrt_reg_addr: 00000 55 | MEM.rd_mem: 204 56 | MEM.wrt_mem: 204 57 | MEM.wrt_enable: 204 58 | MEM.nop: 1 59 | WB.Wrt_data: 00000000000000000000000000000000 60 | WB.Rs: 00000 61 | WB.Rt: 00000 62 | WB.Wrt_reg_addr: 00000 63 | WB.wrt_enable: 204 64 | WB.nop: 1 65 | State after executing cycle: 2 66 | IF.PC: 12 67 | IF.nop: 0 68 | ID.Instr: 00000000001000100001100000100001 69 | ID.nop: 0 70 | EX.Read_data1: 00000000000000000000000000000000 71 | EX.Read_data2: 00000000000000000000000000000000 72 | EX.Imm: 0000000000000100 73 | EX.Rs: 00000 74 | EX.Rt: 00010 75 | EX.Wrt_reg_addr: 00010 76 | EX.is_I_type: 1 77 | EX.rd_mem: 1 78 | EX.wrt_mem: 0 79 | EX.alu_op: 1 80 | EX.wrt_enable: 1 81 | EX.nop: 0 82 | MEM.ALUresult: 00000000000000000000000000000000 83 | MEM.Store_data: 00000000000000000000000000000000 84 | MEM.Rs: 00000 85 | MEM.Rt: 00001 86 | MEM.Wrt_reg_addr: 00001 87 | MEM.rd_mem: 1 88 | MEM.wrt_mem: 0 89 | MEM.wrt_enable: 1 90 | MEM.nop: 0 91 | WB.Wrt_data: 00000000000000000000000000000000 92 | WB.Rs: 00000 93 | WB.Rt: 00000 94 | WB.Wrt_reg_addr: 00000 95 | WB.wrt_enable: 204 96 | WB.nop: 1 97 | State after executing cycle: 3 98 | IF.PC: 16 99 | IF.nop: 0 100 | ID.Instr: 00000000011000100010000000100001 101 | ID.nop: 0 102 | EX.Read_data1: 00000000000000000000000000000001 103 | EX.Read_data2: 00000000000000000000000000000100 104 | EX.Imm: 0001100000100001 105 | EX.Rs: 00001 106 | EX.Rt: 00010 107 | EX.Wrt_reg_addr: 00011 108 | EX.is_I_type: 0 109 | EX.rd_mem: 0 110 | EX.wrt_mem: 0 111 | EX.alu_op: 1 112 | EX.wrt_enable: 1 113 | EX.nop: 0 114 | MEM.ALUresult: 00000000000000000000000000000100 115 | MEM.Store_data: 00000000000000000000000000000000 116 | MEM.Rs: 00000 117 | MEM.Rt: 00010 118 | MEM.Wrt_reg_addr: 00010 119 | MEM.rd_mem: 1 120 | MEM.wrt_mem: 0 121 | MEM.wrt_enable: 1 122 | MEM.nop: 0 123 | WB.Wrt_data: 00000000000000000000000000000001 124 | WB.Rs: 00000 125 | WB.Rt: 00001 126 | WB.Wrt_reg_addr: 00001 127 | WB.wrt_enable: 1 128 | WB.nop: 0 129 | State after executing cycle: 4 130 | IF.PC: 16 131 | IF.nop: 0 132 | ID.Instr: 00000000011000100010000000100001 133 | ID.nop: 0 134 | EX.Read_data1: 00000000000000000000000000000001 135 | EX.Read_data2: 00000000000000000000000000000010 136 | EX.Imm: 0001100000100001 137 | EX.Rs: 00001 138 | EX.Rt: 00010 139 | EX.Wrt_reg_addr: 00011 140 | EX.is_I_type: 0 141 | EX.rd_mem: 0 142 | EX.wrt_mem: 0 143 | EX.alu_op: 1 144 | EX.wrt_enable: 1 145 | EX.nop: 0 146 | MEM.ALUresult: 00000000000000000000000000000100 147 | MEM.Store_data: 00000000000000000000000000000000 148 | MEM.Rs: 00000 149 | MEM.Rt: 00010 150 | MEM.Wrt_reg_addr: 00010 151 | MEM.rd_mem: 1 152 | MEM.wrt_mem: 0 153 | MEM.wrt_enable: 1 154 | MEM.nop: 1 155 | WB.Wrt_data: 00000000000000000000000000000010 156 | WB.Rs: 00000 157 | WB.Rt: 00010 158 | WB.Wrt_reg_addr: 00010 159 | WB.wrt_enable: 1 160 | WB.nop: 0 161 | State after executing cycle: 5 162 | IF.PC: 20 163 | IF.nop: 0 164 | ID.Instr: 00000000011001000010100000100001 165 | ID.nop: 0 166 | EX.Read_data1: 00000000000000000000000000000011 167 | EX.Read_data2: 00000000000000000000000000000010 168 | EX.Imm: 0010000000100001 169 | EX.Rs: 00011 170 | EX.Rt: 00010 171 | EX.Wrt_reg_addr: 00100 172 | EX.is_I_type: 0 173 | EX.rd_mem: 0 174 | EX.wrt_mem: 0 175 | EX.alu_op: 1 176 | EX.wrt_enable: 1 177 | EX.nop: 0 178 | MEM.ALUresult: 00000000000000000000000000000011 179 | MEM.Store_data: 00000000000000000000000000000010 180 | MEM.Rs: 00001 181 | MEM.Rt: 00010 182 | MEM.Wrt_reg_addr: 00011 183 | MEM.rd_mem: 0 184 | MEM.wrt_mem: 0 185 | MEM.wrt_enable: 1 186 | MEM.nop: 0 187 | WB.Wrt_data: 00000000000000000000000000000010 188 | WB.Rs: 00000 189 | WB.Rt: 00010 190 | WB.Wrt_reg_addr: 00010 191 | WB.wrt_enable: 1 192 | WB.nop: 1 193 | State after executing cycle: 6 194 | IF.PC: 24 195 | IF.nop: 0 196 | ID.Instr: 10001100000001100000000000001000 197 | ID.nop: 0 198 | EX.Read_data1: 00000000000000000000000000000011 199 | EX.Read_data2: 00000000000000000000000000000101 200 | EX.Imm: 0010100000100001 201 | EX.Rs: 00011 202 | EX.Rt: 00100 203 | EX.Wrt_reg_addr: 00101 204 | EX.is_I_type: 0 205 | EX.rd_mem: 0 206 | EX.wrt_mem: 0 207 | EX.alu_op: 1 208 | EX.wrt_enable: 1 209 | EX.nop: 0 210 | MEM.ALUresult: 00000000000000000000000000000101 211 | MEM.Store_data: 00000000000000000000000000000010 212 | MEM.Rs: 00011 213 | MEM.Rt: 00010 214 | MEM.Wrt_reg_addr: 00100 215 | MEM.rd_mem: 0 216 | MEM.wrt_mem: 0 217 | MEM.wrt_enable: 1 218 | MEM.nop: 0 219 | WB.Wrt_data: 00000000000000000000000000000011 220 | WB.Rs: 00001 221 | WB.Rt: 00010 222 | WB.Wrt_reg_addr: 00011 223 | WB.wrt_enable: 1 224 | WB.nop: 0 225 | State after executing cycle: 7 226 | IF.PC: 28 227 | IF.nop: 0 228 | ID.Instr: 00000000110001010011100000100001 229 | ID.nop: 0 230 | EX.Read_data1: 00000000000000000000000000000000 231 | EX.Read_data2: 00000000000000000000000000000000 232 | EX.Imm: 0000000000001000 233 | EX.Rs: 00000 234 | EX.Rt: 00110 235 | EX.Wrt_reg_addr: 00110 236 | EX.is_I_type: 1 237 | EX.rd_mem: 1 238 | EX.wrt_mem: 0 239 | EX.alu_op: 1 240 | EX.wrt_enable: 1 241 | EX.nop: 0 242 | MEM.ALUresult: 00000000000000000000000000001000 243 | MEM.Store_data: 00000000000000000000000000000101 244 | MEM.Rs: 00011 245 | MEM.Rt: 00100 246 | MEM.Wrt_reg_addr: 00101 247 | MEM.rd_mem: 0 248 | MEM.wrt_mem: 0 249 | MEM.wrt_enable: 1 250 | MEM.nop: 0 251 | WB.Wrt_data: 00000000000000000000000000000101 252 | WB.Rs: 00011 253 | WB.Rt: 00010 254 | WB.Wrt_reg_addr: 00100 255 | WB.wrt_enable: 1 256 | WB.nop: 0 257 | State after executing cycle: 8 258 | IF.PC: 32 259 | IF.nop: 0 260 | ID.Instr: 10101100000001110000000000001100 261 | ID.nop: 0 262 | EX.Read_data1: 00000000000000000000000000001000 263 | EX.Read_data2: 00000000000000000000000000001000 264 | EX.Imm: 0011100000100001 265 | EX.Rs: 00110 266 | EX.Rt: 00101 267 | EX.Wrt_reg_addr: 00111 268 | EX.is_I_type: 0 269 | EX.rd_mem: 0 270 | EX.wrt_mem: 0 271 | EX.alu_op: 1 272 | EX.wrt_enable: 1 273 | EX.nop: 0 274 | MEM.ALUresult: 00000000000000000000000000001000 275 | MEM.Store_data: 00000000000000000000000000000000 276 | MEM.Rs: 00000 277 | MEM.Rt: 00110 278 | MEM.Wrt_reg_addr: 00110 279 | MEM.rd_mem: 1 280 | MEM.wrt_mem: 0 281 | MEM.wrt_enable: 1 282 | MEM.nop: 0 283 | WB.Wrt_data: 00000000000000000000000000001000 284 | WB.Rs: 00011 285 | WB.Rt: 00100 286 | WB.Wrt_reg_addr: 00101 287 | WB.wrt_enable: 1 288 | WB.nop: 0 289 | State after executing cycle: 9 290 | IF.PC: 32 291 | IF.nop: 0 292 | ID.Instr: 10101100000001110000000000001100 293 | ID.nop: 0 294 | EX.Read_data1: 00000000000000000000000000000100 295 | EX.Read_data2: 00000000000000000000000000001000 296 | EX.Imm: 0011100000100001 297 | EX.Rs: 00110 298 | EX.Rt: 00101 299 | EX.Wrt_reg_addr: 00111 300 | EX.is_I_type: 0 301 | EX.rd_mem: 0 302 | EX.wrt_mem: 0 303 | EX.alu_op: 1 304 | EX.wrt_enable: 1 305 | EX.nop: 0 306 | MEM.ALUresult: 00000000000000000000000000001000 307 | MEM.Store_data: 00000000000000000000000000000000 308 | MEM.Rs: 00000 309 | MEM.Rt: 00110 310 | MEM.Wrt_reg_addr: 00110 311 | MEM.rd_mem: 1 312 | MEM.wrt_mem: 0 313 | MEM.wrt_enable: 1 314 | MEM.nop: 1 315 | WB.Wrt_data: 00000000000000000000000000000100 316 | WB.Rs: 00000 317 | WB.Rt: 00110 318 | WB.Wrt_reg_addr: 00110 319 | WB.wrt_enable: 1 320 | WB.nop: 0 321 | State after executing cycle: 10 322 | IF.PC: 36 323 | IF.nop: 0 324 | ID.Instr: 10001100000010000000000000000100 325 | ID.nop: 0 326 | EX.Read_data1: 00000000000000000000000000000000 327 | EX.Read_data2: 00000000000000000000000000001100 328 | EX.Imm: 0000000000001100 329 | EX.Rs: 00000 330 | EX.Rt: 00111 331 | EX.Wrt_reg_addr: 00111 332 | EX.is_I_type: 1 333 | EX.rd_mem: 0 334 | EX.wrt_mem: 1 335 | EX.alu_op: 1 336 | EX.wrt_enable: 0 337 | EX.nop: 0 338 | MEM.ALUresult: 00000000000000000000000000001100 339 | MEM.Store_data: 00000000000000000000000000001000 340 | MEM.Rs: 00110 341 | MEM.Rt: 00101 342 | MEM.Wrt_reg_addr: 00111 343 | MEM.rd_mem: 0 344 | MEM.wrt_mem: 0 345 | MEM.wrt_enable: 1 346 | MEM.nop: 0 347 | WB.Wrt_data: 00000000000000000000000000000100 348 | WB.Rs: 00000 349 | WB.Rt: 00110 350 | WB.Wrt_reg_addr: 00110 351 | WB.wrt_enable: 1 352 | WB.nop: 1 353 | State after executing cycle: 11 354 | IF.PC: 40 355 | IF.nop: 0 356 | ID.Instr: 10101100000010000000000000010000 357 | ID.nop: 0 358 | EX.Read_data1: 00000000000000000000000000000000 359 | EX.Read_data2: 00000000000000000000000000000000 360 | EX.Imm: 0000000000000100 361 | EX.Rs: 00000 362 | EX.Rt: 01000 363 | EX.Wrt_reg_addr: 01000 364 | EX.is_I_type: 1 365 | EX.rd_mem: 1 366 | EX.wrt_mem: 0 367 | EX.alu_op: 1 368 | EX.wrt_enable: 1 369 | EX.nop: 0 370 | MEM.ALUresult: 00000000000000000000000000001100 371 | MEM.Store_data: 00000000000000000000000000001100 372 | MEM.Rs: 00000 373 | MEM.Rt: 00111 374 | MEM.Wrt_reg_addr: 00111 375 | MEM.rd_mem: 0 376 | MEM.wrt_mem: 1 377 | MEM.wrt_enable: 0 378 | MEM.nop: 0 379 | WB.Wrt_data: 00000000000000000000000000001100 380 | WB.Rs: 00110 381 | WB.Rt: 00101 382 | WB.Wrt_reg_addr: 00111 383 | WB.wrt_enable: 1 384 | WB.nop: 0 385 | State after executing cycle: 12 386 | IF.PC: 40 387 | IF.nop: 1 388 | ID.Instr: 11111111111111111111111111111111 389 | ID.nop: 1 390 | EX.Read_data1: 00000000000000000000000000000000 391 | EX.Read_data2: 00000000000000000000000000000100 392 | EX.Imm: 0000000000010000 393 | EX.Rs: 00000 394 | EX.Rt: 01000 395 | EX.Wrt_reg_addr: 01000 396 | EX.is_I_type: 1 397 | EX.rd_mem: 0 398 | EX.wrt_mem: 1 399 | EX.alu_op: 1 400 | EX.wrt_enable: 0 401 | EX.nop: 0 402 | MEM.ALUresult: 00000000000000000000000000000100 403 | MEM.Store_data: 00000000000000000000000000000000 404 | MEM.Rs: 00000 405 | MEM.Rt: 01000 406 | MEM.Wrt_reg_addr: 01000 407 | MEM.rd_mem: 1 408 | MEM.wrt_mem: 0 409 | MEM.wrt_enable: 1 410 | MEM.nop: 0 411 | WB.Wrt_data: 00000000000000000000000000001100 412 | WB.Rs: 00000 413 | WB.Rt: 00111 414 | WB.Wrt_reg_addr: 00111 415 | WB.wrt_enable: 0 416 | WB.nop: 0 417 | State after executing cycle: 13 418 | IF.PC: 40 419 | IF.nop: 1 420 | ID.Instr: 11111111111111111111111111111111 421 | ID.nop: 1 422 | EX.Read_data1: 00000000000000000000000000000000 423 | EX.Read_data2: 00000000000000000000000000000010 424 | EX.Imm: 0000000000010000 425 | EX.Rs: 00000 426 | EX.Rt: 01000 427 | EX.Wrt_reg_addr: 01000 428 | EX.is_I_type: 1 429 | EX.rd_mem: 0 430 | EX.wrt_mem: 1 431 | EX.alu_op: 1 432 | EX.wrt_enable: 0 433 | EX.nop: 1 434 | MEM.ALUresult: 00000000000000000000000000010000 435 | MEM.Store_data: 00000000000000000000000000000010 436 | MEM.Rs: 00000 437 | MEM.Rt: 01000 438 | MEM.Wrt_reg_addr: 01000 439 | MEM.rd_mem: 0 440 | MEM.wrt_mem: 1 441 | MEM.wrt_enable: 0 442 | MEM.nop: 0 443 | WB.Wrt_data: 00000000000000000000000000000010 444 | WB.Rs: 00000 445 | WB.Rt: 01000 446 | WB.Wrt_reg_addr: 01000 447 | WB.wrt_enable: 1 448 | WB.nop: 0 449 | State after executing cycle: 14 450 | IF.PC: 40 451 | IF.nop: 1 452 | ID.Instr: 11111111111111111111111111111111 453 | ID.nop: 1 454 | EX.Read_data1: 00000000000000000000000000000000 455 | EX.Read_data2: 00000000000000000000000000000010 456 | EX.Imm: 0000000000010000 457 | EX.Rs: 00000 458 | EX.Rt: 01000 459 | EX.Wrt_reg_addr: 01000 460 | EX.is_I_type: 1 461 | EX.rd_mem: 0 462 | EX.wrt_mem: 1 463 | EX.alu_op: 1 464 | EX.wrt_enable: 0 465 | EX.nop: 1 466 | MEM.ALUresult: 00000000000000000000000000010000 467 | MEM.Store_data: 00000000000000000000000000000010 468 | MEM.Rs: 00000 469 | MEM.Rt: 01000 470 | MEM.Wrt_reg_addr: 01000 471 | MEM.rd_mem: 0 472 | MEM.wrt_mem: 1 473 | MEM.wrt_enable: 0 474 | MEM.nop: 1 475 | WB.Wrt_data: 00000000000000000000000000010000 476 | WB.Rs: 00000 477 | WB.Rt: 01000 478 | WB.Wrt_reg_addr: 01000 479 | WB.wrt_enable: 0 480 | WB.nop: 0 481 | State after executing cycle: 15 482 | IF.PC: 40 483 | IF.nop: 1 484 | ID.Instr: 11111111111111111111111111111111 485 | ID.nop: 1 486 | EX.Read_data1: 00000000000000000000000000000000 487 | EX.Read_data2: 00000000000000000000000000000010 488 | EX.Imm: 0000000000010000 489 | EX.Rs: 00000 490 | EX.Rt: 01000 491 | EX.Wrt_reg_addr: 01000 492 | EX.is_I_type: 1 493 | EX.rd_mem: 0 494 | EX.wrt_mem: 1 495 | EX.alu_op: 1 496 | EX.wrt_enable: 0 497 | EX.nop: 1 498 | MEM.ALUresult: 00000000000000000000000000010000 499 | MEM.Store_data: 00000000000000000000000000000010 500 | MEM.Rs: 00000 501 | MEM.Rt: 01000 502 | MEM.Wrt_reg_addr: 01000 503 | MEM.rd_mem: 0 504 | MEM.wrt_mem: 1 505 | MEM.wrt_enable: 0 506 | MEM.nop: 1 507 | WB.Wrt_data: 00000000000000000000000000010000 508 | WB.Rs: 00000 509 | WB.Rt: 01000 510 | WB.Wrt_reg_addr: 01000 511 | WB.wrt_enable: 0 512 | WB.nop: 1 513 | -------------------------------------------------------------------------------- /testcase/0-1/dmemresult_ans.txt: -------------------------------------------------------------------------------- 1 | 11111111 2 | 11111111 3 | 11111111 4 | 11111111 5 | 01111111 6 | 11111111 7 | 11111111 8 | 11111110 9 | 01111111 10 | 11111111 11 | 11111111 12 | 11111101 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000000 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000000 29 | 00000000 30 | 00000000 31 | 00000000 32 | 00000000 33 | 00000000 34 | 00000000 35 | 00000000 36 | 00000000 37 | 00000000 38 | 00000000 39 | 00000000 40 | 00000000 41 | 00000000 42 | 00000000 43 | 00000000 44 | 00000000 45 | 00000000 46 | 00000000 47 | 00000000 48 | 00000000 49 | 00000000 50 | 00000000 51 | 00000000 52 | 00000000 53 | 00000000 54 | 00000000 55 | 00000000 56 | 00000000 57 | 00000000 58 | 00000000 59 | 00000000 60 | 00000000 61 | 00000000 62 | 00000000 63 | 00000000 64 | 00000000 65 | 00000000 66 | 00000000 67 | 00000000 68 | 00000000 69 | 00000000 70 | 00000000 71 | 00000000 72 | 00000000 73 | 00000000 74 | 00000000 75 | 00000000 76 | 00000000 77 | 00000000 78 | 00000000 79 | 00000000 80 | 00000000 81 | 00000000 82 | 00000000 83 | 00000000 84 | 00000000 85 | 00000000 86 | 00000000 87 | 00000000 88 | 00000000 89 | 00000000 90 | 00000000 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00000000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00000000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00000000 129 | 00000000 130 | 00000000 131 | 00000000 132 | 00000000 133 | 00000000 134 | 00000000 135 | 00000000 136 | 00000000 137 | 00000000 138 | 00000000 139 | 00000000 140 | 00000000 141 | 00000000 142 | 00000000 143 | 00000000 144 | 00000000 145 | 00000000 146 | 00000000 147 | 00000000 148 | 00000000 149 | 00000000 150 | 00000000 151 | 00000000 152 | 00000000 153 | 00000000 154 | 00000000 155 | 00000000 156 | 00000000 157 | 00000000 158 | 00000000 159 | 00000000 160 | 00000000 161 | 00000000 162 | 00000000 163 | 00000000 164 | 00000000 165 | 00000000 166 | 00000000 167 | 00000000 168 | 00000000 169 | 00000000 170 | 00000000 171 | 00000000 172 | 00000000 173 | 00000000 174 | 00000000 175 | 00000000 176 | 00000000 177 | 00000000 178 | 00000000 179 | 00000000 180 | 00000000 181 | 00000000 182 | 00000000 183 | 00000000 184 | 00000000 185 | 00000000 186 | 00000000 187 | 00000000 188 | 00000000 189 | 00000000 190 | 00000000 191 | 00000000 192 | 00000000 193 | 00000000 194 | 00000000 195 | 00000000 196 | 00000000 197 | 00000000 198 | 00000000 199 | 00000000 200 | 00000000 201 | 00000000 202 | 00000000 203 | 00000000 204 | 00000000 205 | 00000000 206 | 00000000 207 | 00000000 208 | 00000000 209 | 00000000 210 | 00000000 211 | 00000000 212 | 00000000 213 | 00000000 214 | 00000000 215 | 00000000 216 | 00000000 217 | 00000000 218 | 00000000 219 | 00000000 220 | 00000000 221 | 00000000 222 | 00000000 223 | 00000000 224 | 00000000 225 | 00000000 226 | 00000000 227 | 00000000 228 | 00000000 229 | 00000000 230 | 00000000 231 | 00000000 232 | 00000000 233 | 00000000 234 | 00000000 235 | 00000000 236 | 00000000 237 | 00000000 238 | 00000000 239 | 00000000 240 | 00000000 241 | 00000000 242 | 00000000 243 | 00000000 244 | 00000000 245 | 00000000 246 | 00000000 247 | 00000000 248 | 00000000 249 | 00000000 250 | 00000000 251 | 00000000 252 | 00000000 253 | 00000000 254 | 00000000 255 | 00000000 256 | 00000000 257 | 00000000 258 | 00000000 259 | 00000000 260 | 00000000 261 | 00000000 262 | 00000000 263 | 00000000 264 | 00000000 265 | 00000000 266 | 00000000 267 | 00000000 268 | 00000000 269 | 00000000 270 | 00000000 271 | 00000000 272 | 00000000 273 | 00000000 274 | 00000000 275 | 00000000 276 | 00000000 277 | 00000000 278 | 00000000 279 | 00000000 280 | 00000000 281 | 00000000 282 | 00000000 283 | 00000000 284 | 00000000 285 | 00000000 286 | 00000000 287 | 00000000 288 | 00000000 289 | 00000000 290 | 00000000 291 | 00000000 292 | 00000000 293 | 00000000 294 | 00000000 295 | 00000000 296 | 00000000 297 | 00000000 298 | 00000000 299 | 00000000 300 | 00000000 301 | 00000000 302 | 00000000 303 | 00000000 304 | 00000000 305 | 00000000 306 | 00000000 307 | 00000000 308 | 00000000 309 | 00000000 310 | 00000000 311 | 00000000 312 | 00000000 313 | 00000000 314 | 00000000 315 | 00000000 316 | 00000000 317 | 00000000 318 | 00000000 319 | 00000000 320 | 00000000 321 | 00000000 322 | 00000000 323 | 00000000 324 | 00000000 325 | 00000000 326 | 00000000 327 | 00000000 328 | 00000000 329 | 00000000 330 | 00000000 331 | 00000000 332 | 00000000 333 | 00000000 334 | 00000000 335 | 00000000 336 | 00000000 337 | 00000000 338 | 00000000 339 | 00000000 340 | 00000000 341 | 00000000 342 | 00000000 343 | 00000000 344 | 00000000 345 | 00000000 346 | 00000000 347 | 00000000 348 | 00000000 349 | 00000000 350 | 00000000 351 | 00000000 352 | 00000000 353 | 00000000 354 | 00000000 355 | 00000000 356 | 00000000 357 | 00000000 358 | 00000000 359 | 00000000 360 | 00000000 361 | 00000000 362 | 00000000 363 | 00000000 364 | 00000000 365 | 00000000 366 | 00000000 367 | 00000000 368 | 00000000 369 | 00000000 370 | 00000000 371 | 00000000 372 | 00000000 373 | 00000000 374 | 00000000 375 | 00000000 376 | 00000000 377 | 00000000 378 | 00000000 379 | 00000000 380 | 00000000 381 | 00000000 382 | 00000000 383 | 00000000 384 | 00000000 385 | 00000000 386 | 00000000 387 | 00000000 388 | 00000000 389 | 00000000 390 | 00000000 391 | 00000000 392 | 00000000 393 | 00000000 394 | 00000000 395 | 00000000 396 | 00000000 397 | 00000000 398 | 00000000 399 | 00000000 400 | 00000000 401 | 00000000 402 | 00000000 403 | 00000000 404 | 00000000 405 | 00000000 406 | 00000000 407 | 00000000 408 | 00000000 409 | 00000000 410 | 00000000 411 | 00000000 412 | 00000000 413 | 00000000 414 | 00000000 415 | 00000000 416 | 00000000 417 | 00000000 418 | 00000000 419 | 00000000 420 | 00000000 421 | 00000000 422 | 00000000 423 | 00000000 424 | 00000000 425 | 00000000 426 | 00000000 427 | 00000000 428 | 00000000 429 | 00000000 430 | 00000000 431 | 00000000 432 | 00000000 433 | 00000000 434 | 00000000 435 | 00000000 436 | 00000000 437 | 00000000 438 | 00000000 439 | 00000000 440 | 00000000 441 | 00000000 442 | 00000000 443 | 00000000 444 | 00000000 445 | 00000000 446 | 00000000 447 | 00000000 448 | 00000000 449 | 00000000 450 | 00000000 451 | 00000000 452 | 00000000 453 | 00000000 454 | 00000000 455 | 00000000 456 | 00000000 457 | 00000000 458 | 00000000 459 | 00000000 460 | 00000000 461 | 00000000 462 | 00000000 463 | 00000000 464 | 00000000 465 | 00000000 466 | 00000000 467 | 00000000 468 | 00000000 469 | 00000000 470 | 00000000 471 | 00000000 472 | 00000000 473 | 00000000 474 | 00000000 475 | 00000000 476 | 00000000 477 | 00000000 478 | 00000000 479 | 00000000 480 | 00000000 481 | 00000000 482 | 00000000 483 | 00000000 484 | 00000000 485 | 00000000 486 | 00000000 487 | 00000000 488 | 00000000 489 | 00000000 490 | 00000000 491 | 00000000 492 | 00000000 493 | 00000000 494 | 00000000 495 | 00000000 496 | 00000000 497 | 00000000 498 | 00000000 499 | 00000000 500 | 00000000 501 | 00000000 502 | 00000000 503 | 00000000 504 | 00000000 505 | 00000000 506 | 00000000 507 | 00000000 508 | 00000000 509 | 00000000 510 | 00000000 511 | 00000000 512 | 00000000 513 | 00000000 514 | 00000000 515 | 00000000 516 | 00000000 517 | 00000000 518 | 00000000 519 | 00000000 520 | 00000000 521 | 00000000 522 | 00000000 523 | 00000000 524 | 00000000 525 | 00000000 526 | 00000000 527 | 00000000 528 | 00000000 529 | 00000000 530 | 00000000 531 | 00000000 532 | 00000000 533 | 00000000 534 | 00000000 535 | 00000000 536 | 00000000 537 | 00000000 538 | 00000000 539 | 00000000 540 | 00000000 541 | 00000000 542 | 00000000 543 | 00000000 544 | 00000000 545 | 00000000 546 | 00000000 547 | 00000000 548 | 00000000 549 | 00000000 550 | 00000000 551 | 00000000 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