├── Carry_look_ahead_adder_code ├── Block diagram .jpg ├── Carry_look_ahead_adder.v ├── Carry_look_ahead_adder_output.png ├── Carry_look_ahead_adder_tb.v └── Carry_look_ahead_adder_waveform.png ├── Day10[decoder3x8] ├── Block.PNG ├── decoder.v ├── decoder_38_tb.v ├── output.PNG └── waveform.PNG ├── Day11[Encoder8x3] ├── encoder.v ├── encoder_output.png ├── encoder_tb.v └── encoder_waveform.png ├── Day12[8_1 Mux] ├── mux.v ├── mux8_1_output.png ├── mux8_1_waveform.png └── mux_tb.v ├── Day13[Priority_encoder] ├── encoder.v ├── encoder_tb.v ├── priority_encoder_output.png └── priority_encoder_waveform.png ├── Day14[up_counter] ├── syc_up_counter_output.png ├── syc_up_counter_waveform.png ├── up_counter.v └── up_counter_tb.v ├── Day15[Sync_down_counter] ├── down_counter.v ├── down_counter_output.png ├── down_counter_tb.v └── down_counter_waveform.png ├── Day16[up down counter] ├── up_down_counter.v ├── up_down_counter_output.png ├── up_down_counter_tb.v └── up_down_counter_waveform.png ├── Day17[SR Flipflop] ├── sr_ff.v ├── sr_ff_tb.v ├── sr_flipflop_output.png └── sr_flipflop_waveform.png ├── Day18[D Flipflop] ├── blk.PNG ├── dff.v ├── dff_tb.v └── wf.PNG ├── Day20[Clock Divider] ├── clkdivider_tb.v ├── clock_divider_waveform.png └── clockdivider.v ├── Day21[Ring Counter] ├── ring_counter_output.png ├── ring_counter_waveform.png ├── ringcounter.v └── ringcounter_tb.v ├── Day22[Jhonson Counter] ├── jhonson_counter_output.png ├── jhonson_counter_waveform.png ├── jhonson_tb.v └── jhonsoncounter.v ├── Day23[Binary-Gray] ├── Binary-Gray.v ├── Binary-to-Gray_output.png ├── Binary-to-Gray_waveform.png └── Binary_Gray_tb.v ├── Day24[Gray_Binary] ├── G_B.v ├── Gray_to_Binary_Output.png ├── Gray_to_Binary_waveform.png └── g_b_tb.v ├── Day25[N_bit_adder] ├── full_adder.v ├── half_adder.v ├── n_bit_adder.v ├── n_bit_adder_output.png ├── n_bit_adder_tb.v └── n_bit_adder_waveform.png ├── Day26[n_bit_comparator] ├── comparator_n_bit.v ├── comparator_tb.v ├── n_bit_comparator_output.png └── n_bit_comparator_waveform.png ├── Day27[3-bit Comparator structural model] ├── comp3.v ├── comp3_tb.v ├── output.PNG └── waveform.PNG ├── Day28[Digital_Clock] ├── digital_clock.v ├── digital_clock_output.png ├── digital_clock_tb.v ├── digital_clock_waveform.png └── flowchart.jpg ├── Day29[Parity Generator] ├── Wf (1).PNG ├── par_gen.v └── par_gen_tb.v ├── Day5(Carry_select_adder) ├── Block Diagram.jpg ├── Carry_s_adder.v ├── Carry_select_adder_output.png ├── Carry_select_adder_waveform.png ├── carry_s_adder_tb.v ├── fa.v └── mux.v ├── Day6[Half_subtractor] ├── Block diagram .jpg ├── Half_subtractor.v ├── Half_subtractor_output.png ├── Half_subtractor_tb.v └── Half_subtractor_waveform.png ├── Day7[Full_subtractor] ├── Block diagram .jpg ├── Full_subtractor.v ├── Full_subtractor_output.png ├── Full_subtractor_tb.v ├── Full_subtractor_waveform.png └── Truth Table.jpg ├── Day8[ALU4bit] ├── ALU4bit.v ├── ALU4bit_output.png ├── ALU4bit_tb.v └── ALU4bit_waveform.png ├── Day9[and gate using 2-1 mux] ├── and_gate.v ├── and_gate_tb.v ├── and_gate_using_mux_output.png ├── and_gate_using_mux_waveform.png └── mux.v ├── Fulladder_code ├── Fulladdeer_tb.v ├── Fulladder_behavioural.v ├── Fulladder_dataflow.v ├── Fulladder_gateflow.v ├── Fulladder_output.png └── Fulladder_waveform.png ├── Fulladder_u_halfadder[Day4] ├── Block diagram .jpg ├── Fulladder_u_halfadder.v ├── Fulladder_u_halfadder_output.png ├── Fulladder_u_halfadder_tb.v └── Fulladder_u_halfadder_waveform.png ├── Halfadder_code ├── Halfadder_tb.v ├── halfadder.png ├── halfadder.v ├── halfadder1.png └── halfadder_output.png ├── README.md └── Ripple_carry_adder_code ├── Block diagrams.jpg ├── Full_adder.v ├── Ripple_carry_adder.v ├── Ripple_carry_adder_output.png ├── Ripple_carry_adder_tb.v └── Ripple_carry_adder_waveform.png /Carry_look_ahead_adder_code/Block diagram .jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Carry_look_ahead_adder_code/Block diagram .jpg -------------------------------------------------------------------------------- /Carry_look_ahead_adder_code/Carry_look_ahead_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:43:01 11/22/2022 7 | // Design Name: 8 | // Module Name: Carry_look_ahead_adder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Carry_look_ahead_adder(a, b, cin,sum, Cout); 22 | 23 | input [3:0] a, b; 24 | input cin; 25 | output [3:0] sum; 26 | output Cout; 27 | 28 | wire P0,P1,P2,P3,G0,G1,G2,G3; 29 | wire C4, C3, C2, C1; 30 | 31 | /*incase we add one assign then each stmt can be given with ',' and last stmt can be ended with ';' 32 | or else use assign for each stmt and use';' to end each stmt */ 33 | assign 34 | P0 = a[0] ^ b[0], 35 | P1 = a[1] ^ b[1], 36 | P2 = a[2] ^ b[2], 37 | P3 = a[3] ^ b[3]; 38 | 39 | assign 40 | G0 = a[0] & b[0], 41 | G1 = a[1] & b[1], 42 | G2 = a[2] & b[2], 43 | G3 = a[3] & b[3]; 44 | assign 45 | C1 = G0 | (P0 & cin), 46 | C2 = G1 | (P1 & G0) | (P1 & P0 & cin), 47 | C3 = G2 | (P2 & G1) | (P2 & P1 & G0) | (P2 & P1 & P0 & cin), 48 | C4 = G3 | (P3 & G2) | (P3 & P2 & G1) | (P3 & P2 & P1 & G0) | (P3 & P2 & P1 & P0 & cin); 49 | 50 | assign 51 | sum[0] = P0 ^ cin, 52 | sum[1] = P1 ^ C1, 53 | sum[2] = P2 ^ C2, 54 | sum[3] = P3 ^ C3; 55 | 56 | assign Cout = C4; 57 | 58 | endmodule -------------------------------------------------------------------------------- /Carry_look_ahead_adder_code/Carry_look_ahead_adder_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Carry_look_ahead_adder_code/Carry_look_ahead_adder_output.png -------------------------------------------------------------------------------- /Carry_look_ahead_adder_code/Carry_look_ahead_adder_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 22:49:36 11/22/2022 8 | // Design Name: Carry_look_ahead_adder 9 | // Module Name: P:/xilin programs/verilog/Carry_look_ahead_adder/Carry_look_ahead_adder_tb.v 10 | // Project Name: Carry_look_ahead_adder 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: Carry_look_ahead_adder 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module Carry_look_ahead_adder_tb; 26 | 27 | reg [3:0] a; 28 | reg [3:0] b; 29 | reg cin; 30 | 31 | wire [3:0] sum; 32 | wire Cout; 33 | Carry_look_ahead_adder uut ( 34 | .a(a), 35 | .b(b), 36 | .cin(cin), 37 | .sum(sum), 38 | .Cout(Cout) 39 | ); 40 | initial 41 | begin 42 | $monitor($time," a=%d ,b=%d ,cin=%d ,sum=%d ,Cout=%d ",a,b,cin,sum,Cout); 43 | end 44 | initial 45 | begin 46 | a =4'b0000;b =4'b0000;cin = 0; 47 | #100 a=4'b0010;b=4'b0110;cin=1; 48 | #100 a=4'b1111;b=4'b1101;cin=0; // random values 49 | #100 a=4'b1010;b=4'b0101;cin=0; 50 | #100 a=4'b0011;b=4'b1100;cin=1; 51 | end 52 | 53 | endmodule 54 | 55 | -------------------------------------------------------------------------------- /Carry_look_ahead_adder_code/Carry_look_ahead_adder_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Carry_look_ahead_adder_code/Carry_look_ahead_adder_waveform.png -------------------------------------------------------------------------------- /Day10[decoder3x8]/Block.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day10[decoder3x8]/Block.PNG -------------------------------------------------------------------------------- /Day10[decoder3x8]/decoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:35:38 11/29/2022 7 | // Design Name: 8 | // Module Name: decoder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module decoder( in,out, en); 22 | input [2:0] in; 23 | input en; 24 | output [7:0] out; 25 | reg [7:0] out; 26 | 27 | always @( in or en) 28 | begin 29 | 30 | if (en) 31 | begin 32 | out=8'd0; 33 | case (in) 34 | 3'b000: out[0]=1'b1; 35 | 3'b001: out[1]=1'b1; 36 | 3'b010: out[2]=1'b1; 37 | 3'b011: out[3]=1'b1; 38 | 3'b100: out[4]=1'b1; 39 | 3'b101: out[5]=1'b1; 40 | 3'b110: out[6]=1'b1; 41 | 3'b111: out[7]=1'b1; 42 | default: out=8'd0; 43 | endcase 44 | end 45 | else 46 | out=8'd0; 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /Day10[decoder3x8]/decoder_38_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 22:37:28 11/29/2022 8 | // Design Name: decoder 9 | // Module Name: P:/xilin programs/verilog/decored3_8/decoder_38_tb.v 10 | // Project Name: decored3_8 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: decoder 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module decoder_38_tb; 26 | 27 | wire [7:0] out; 28 | reg en; 29 | reg [2:0] in; 30 | integer i; 31 | 32 | decoder uut(in,out,en); 33 | 34 | initial begin 35 | $monitor( "en=%b, in=%d, out=%b ", en, in, out); 36 | for ( i=0; i<16; i=i+1) 37 | begin 38 | {en,in} = i; 39 | #1; 40 | end 41 | end 42 | endmodule -------------------------------------------------------------------------------- /Day10[decoder3x8]/output.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day10[decoder3x8]/output.PNG -------------------------------------------------------------------------------- /Day10[decoder3x8]/waveform.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day10[decoder3x8]/waveform.PNG -------------------------------------------------------------------------------- /Day11[Encoder8x3]/encoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company:Author Prajwal N 4 | // Engineer: 5 | // 6 | // Create Date: 18:47:17 11/30/2022 7 | // Design Name: 8:3 encoder 8 | // Module Name: encoder 9 | // Tool versions: ISE Design Suit 14.7 10 | // 11 | // Revision: 12 | // Revision 0.01 - File Created 13 | // 14 | ////////////////////////////////////////////////////////////////////////////////// 15 | module encoder(en,din,dout); 16 | input en; 17 | input [7:0]din; 18 | output [2:0]dout; 19 | wire[7:0]count; 20 | reg [2:0] dout; 21 | always @(en,din) 22 | begin 23 | if (en==0) 24 | dout=3'b000; 25 | else 26 | begin 27 | dout=3'b000; 28 | case (din) 29 | 8'd1:dout=3'b000; 30 | 8'd2:dout=3'b001; 31 | 8'd4:dout=3'b010; 32 | 8'd8:dout=3'b011; 33 | 8'd16:dout=3'b100; 34 | 8'd32:dout=3'b101; 35 | 8'd64:dout=3'b110; 36 | 8'd128:dout=3'b111; 37 | default:dout=3'b000; 38 | endcase 39 | end 40 | end 41 | endmodule 42 | -------------------------------------------------------------------------------- /Day11[Encoder8x3]/encoder_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day11[Encoder8x3]/encoder_output.png -------------------------------------------------------------------------------- /Day11[Encoder8x3]/encoder_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: Author Prajwal N 5 | // 6 | // Create Date: 19:04:22 11/30/2022 7 | // Design Name: encoder 8 | // Module Name: P:/xilin programs/verilog/encoder8x3/encoder_tb.v 9 | // Project Name: encoder8x3 10 | // Target Device: 11 | // Tool versions: ISE Design Suit 14.7 12 | // 13 | // Verilog Test Fixture created by ISE for module: encoder 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // 20 | //////////////////////////////////////////////////////////////////////////////// 21 | 22 | module encoder_tb; 23 | 24 | // Inputs 25 | reg en; 26 | reg [7:0] din; 27 | 28 | // Outputs 29 | wire [2:0] dout; 30 | integer i; 31 | encoder uut ( 32 | .en(en), 33 | .din(din), 34 | .dout(dout) 35 | ); 36 | 37 | initial begin 38 | $monitor($time," en=%d din=%d dout=%d ",en,din,dout); 39 | end 40 | 41 | initial 42 | begin 43 | en=0; 44 | i=0; 45 | for (i=0;i<8;i=i+1) 46 | begin 47 | din=2**i; 48 | #10; 49 | end 50 | #10 en=1; 51 | for (i=0;i<8;i=i+1) 52 | begin 53 | din=2**i; 54 | #10; 55 | end 56 | end 57 | 58 | 59 | endmodule 60 | 61 | -------------------------------------------------------------------------------- /Day11[Encoder8x3]/encoder_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day11[Encoder8x3]/encoder_waveform.png -------------------------------------------------------------------------------- /Day12[8_1 Mux]/mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: PRajwal N 4 | // Create Date: 18:25:39 12/01/2022 5 | // Design Name: 8:1 Mux 6 | // Module Name: mux 7 | // Project Name: 8:1 Mux 8 | // Target Devices: 9 | // Tool versions: ISE Design Suit 14.7 10 | // Revision 0.01 - File Created 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module mux(in,out,sel); 13 | input[7:0]in; 14 | input[2:0]sel; 15 | output out; 16 | reg out; 17 | always @(in,sel) 18 | begin 19 | case(sel) 20 | 3'b000:out=in[0]; 21 | 3'b001:out=in[1]; 22 | 3'b010:out=in[2]; 23 | 3'b011:out=in[3]; 24 | 3'b100:out=in[4]; 25 | 3'b101:out=in[5]; 26 | 3'b110:out=in[6]; 27 | 3'b111:out=in[7]; 28 | default:out=1'b0; 29 | endcase 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /Day12[8_1 Mux]/mux8_1_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day12[8_1 Mux]/mux8_1_output.png -------------------------------------------------------------------------------- /Day12[8_1 Mux]/mux8_1_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day12[8_1 Mux]/mux8_1_waveform.png -------------------------------------------------------------------------------- /Day12[8_1 Mux]/mux_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Author: Prajwal N 5 | // Create Date: 19:08:49 12/01/2022 6 | // Design Name: mux 7 | // Module Name: P:/xilin programs/verilog/mux81/mux_tb.v 8 | // Project Name: mux81 9 | // Tool versions: ISE Design Suit 14.7 10 | // Revision 0.01 - File Created 11 | //////////////////////////////////////////////////////////////////////////////// 12 | 13 | module mux_tb; 14 | reg [7:0]in; 15 | reg[2:0]sel; 16 | wire out; 17 | mux uut(.in(in),.out(out),.sel(sel)); 18 | initial 19 | begin 20 | $monitor($time," sel=%d in=%b out=%d ",sel,in,out); 21 | end 22 | initial 23 | begin 24 | in=8'b01011010; 25 | sel=3'b000; 26 | repeat(7) 27 | begin 28 | #10 sel=sel+1; 29 | end 30 | #10 $finish; 31 | end 32 | endmodule 33 | 34 | -------------------------------------------------------------------------------- /Day13[Priority_encoder]/encoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company:Author Prajwal N 4 | // Create Date: 18:47:17 11/30/2022 5 | // Design Name: 8:3 encoder 6 | // Module Name: encoder 7 | // Tool versions: ISE Design Suit 14.7 8 | // Revision 0.01 - File Created 9 | // 10 | ////////////////////////////////////////////////////////////////////////////////// 11 | module encoder(en,din,dout); 12 | input en; 13 | input [7:0]din; 14 | output [2:0]dout; 15 | wire[7:0]count; 16 | reg [2:0] dout; 17 | always @(en,din) 18 | begin 19 | if (en==0) 20 | dout=3'b000; 21 | else 22 | begin 23 | dout=3'b000; 24 | casex (din) 25 | 8'b00000001:dout=3'b000; 26 | 8'b0000001x:dout=3'b001; 27 | 8'b000001xx:dout=3'b010; 28 | 8'b00001xxx:dout=3'b011; 29 | 8'b0001xxxx:dout=3'b100; 30 | 8'b001xxxxx:dout=3'b101; 31 | 8'b01xxxxxx:dout=3'b110; 32 | 8'b1xxxxxxx:dout=3'b111; 33 | default:dout=3'b000; 34 | endcase 35 | end 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /Day13[Priority_encoder]/encoder_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: Author Prajwal N 5 | // 6 | // Create Date: 19:04:22 11/30/2022 7 | // Design Name: encoder 8 | // Module Name: P:/xilin programs/verilog/encoder8x3/encoder_tb.v 9 | // Project Name: encoder8x3 10 | // Target Device: 11 | // Tool versions: ISE Design Suit 14.7 12 | // 13 | // Verilog Test Fixture created by ISE for module: encoder 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // 20 | //////////////////////////////////////////////////////////////////////////////// 21 | 22 | module encoder_tb; 23 | 24 | // Inputs 25 | reg en; 26 | reg [7:0] din; 27 | 28 | // Outputs 29 | wire [2:0] dout; 30 | encoder uut ( 31 | .en(en), 32 | .din(din), 33 | .dout(dout) 34 | ); 35 | 36 | initial begin 37 | $monitor($time," en=%d din=%b dout=%b ",en,din,dout); 38 | end 39 | 40 | initial 41 | begin 42 | en=0; 43 | din=8'b00000001; 44 | #10 din=8'b0000001x; 45 | #10 din=8'b000001xx; 46 | #10 din=8'b00001xxx; 47 | #10 din=8'b0001xxxx; 48 | #10 din=8'b001xxxxx; 49 | #10 din=8'b01xxxxxx; 50 | #10 din=8'b1xxxxxxx; 51 | #10 en=1; 52 | din=8'b00000001; 53 | #10 din=8'b0000001x; 54 | #10 din=8'b000001xx; 55 | #10 din=8'b00001xxx; 56 | #10 din=8'b0001xxxx; 57 | #10 din=8'b001xxxxx; 58 | #10 din=8'b01xxxxxx; 59 | #10 din=8'b1xxxxxxx; 60 | #10 $finish; 61 | end 62 | endmodule 63 | 64 | -------------------------------------------------------------------------------- /Day13[Priority_encoder]/priority_encoder_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day13[Priority_encoder]/priority_encoder_output.png -------------------------------------------------------------------------------- /Day13[Priority_encoder]/priority_encoder_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day13[Priority_encoder]/priority_encoder_waveform.png -------------------------------------------------------------------------------- /Day14[up_counter]/syc_up_counter_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day14[up_counter]/syc_up_counter_output.png -------------------------------------------------------------------------------- /Day14[up_counter]/syc_up_counter_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day14[up_counter]/syc_up_counter_waveform.png -------------------------------------------------------------------------------- /Day14[up_counter]/up_counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author : Prajwal N 4 | // Create Date: 20:59:27 12/03/2022 5 | // Design Name: UP COUNTER 6 | // Module Name: up_counter 7 | // Project Name: up_counter 8 | // Tool versions: ISE Design Suit 14.7 9 | // Revision 0.01 - File Created 10 | ////////////////////////////////////////////////////////////////////////////////// 11 | module up_counter(clk,rst,count); 12 | input clk,rst; 13 | output [3:0] count; 14 | reg [3:0]count; 15 | always@(posedge clk) 16 | begin 17 | if(rst==0) 18 | count=4'b0000; 19 | else 20 | count=count+1; 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /Day14[up_counter]/up_counter_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | //Author : Prajwal N 5 | // Create Date: 21:06:22 12/03/2022 6 | // Design Name: up_counter 7 | // Module Name: P:/xilin programs/verilog/up_counter/up_counter_tb.v 8 | // Project Name: up_counter 9 | // Tool versions: ISE Design Suit 14.7 10 | // Verilog Test Fixture created by ISE for module: up_counter 11 | // Revision 0.01 - File Created 12 | //////////////////////////////////////////////////////////////////////////////// 13 | 14 | module up_counter_tb; 15 | 16 | 17 | reg clk; 18 | reg rst; 19 | 20 | wire [3:0] count; 21 | 22 | up_counter uut (.clk(clk),.rst(rst),.count(count)); 23 | 24 | initial 25 | begin 26 | $monitor($time," rst=%b count=%d ",rst,count); 27 | end 28 | 29 | initial 30 | begin 31 | clk = 0; 32 | rst = 0; 33 | #50 rst=1; 34 | end 35 | 36 | always 37 | #20 clk=~clk; 38 | 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /Day15[Sync_down_counter]/down_counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author : Prajwal N 4 | // Create Date: 21:23:29 12/04/2022 5 | // Design Name: Sync_down_counter 6 | // Module Name: down_counter 7 | // Tool versions: ISE Design Suit 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module down_counter(clk,rst,count); 11 | input clk,rst; 12 | output [3:0]count; 13 | reg [3:0] count; 14 | always@(posedge clk) 15 | begin 16 | if(rst==0) 17 | count=4'b1111; 18 | else 19 | count=count-1; 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /Day15[Sync_down_counter]/down_counter_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day15[Sync_down_counter]/down_counter_output.png -------------------------------------------------------------------------------- /Day15[Sync_down_counter]/down_counter_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 21:25:58 12/04/2022 8 | // Design Name: down_counter 9 | // Module Name: P:/xilin programs/verilog/sync_down_counter/down_counter_tb.v 10 | // Project Name: sync_down_counter 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: down_counter 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module down_counter_tb; 26 | 27 | reg clk; 28 | reg rst; 29 | 30 | wire [3:0] count; 31 | 32 | down_counter uut (.clk(clk),.rst(rst),.count(count)); 33 | initial 34 | begin 35 | $monitor($time," rst=%d count=%b ",rst,count); 36 | end 37 | 38 | initial 39 | begin 40 | clk = 0; 41 | rst = 0; 42 | #100 rst=1; 43 | end 44 | 45 | always 46 | #50 clk=~clk; 47 | 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /Day15[Sync_down_counter]/down_counter_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day15[Sync_down_counter]/down_counter_waveform.png -------------------------------------------------------------------------------- /Day16[up down counter]/up_down_counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author : Prajwal N 4 | // Create Date: 22:29:52 12/04/2022 5 | // Design Name: Up Down Counter 6 | // Module Name: up_down_counter 7 | // Tool versions: ISE Design Suit 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module up_down_counter(clk,rst,mode,count); 11 | input clk,rst,mode; 12 | output [3:0]count; 13 | reg [3:0]count; 14 | always@(posedge clk) 15 | if(mode==0) 16 | begin //work as up counter 17 | if(rst==0) 18 | count<=4'b0000; 19 | else 20 | count<=count+1; 21 | end 22 | else 23 | begin //work as down counter 24 | if(rst==0) 25 | count<=4'b1111; 26 | else 27 | count<=count-1; 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /Day16[up down counter]/up_down_counter_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day16[up down counter]/up_down_counter_output.png -------------------------------------------------------------------------------- /Day16[up down counter]/up_down_counter_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Author : Prajwal N 5 | // Create Date: 22:45:09 12/04/2022 6 | // Design Name: up_down_counter 7 | // Module Name: P:/xilin programs/verilog/up_down_counter/up_down_counter_tb.v 8 | // Project Name: up_down_counter 9 | // Tool versions: ISE Design Suit 14.7 10 | // Verilog Test Fixture created by ISE for module: up_down_counter 11 | // Revision 0.01 - File Created 12 | //////////////////////////////////////////////////////////////////////////////// 13 | 14 | module up_down_counter_tb; 15 | 16 | reg clk; 17 | reg rst; 18 | reg mode; 19 | 20 | wire [3:0] count; 21 | 22 | up_down_counter uut (.clk(clk),.rst(rst),.mode(mode),.count(count)); 23 | initial 24 | begin 25 | $monitor($time," mode=%d rst=%d count=%b => %d ",mode,rst,count,count); 26 | end 27 | initial begin 28 | clk = 0; 29 | mode=0; 30 | rst = 0; 31 | #10 rst=1; 32 | #160 mode=1; 33 | rst=0; 34 | #10 rst=1; 35 | end 36 | always 37 | #5 clk=~clk; 38 | 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /Day16[up down counter]/up_down_counter_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day16[up down counter]/up_down_counter_waveform.png -------------------------------------------------------------------------------- /Day17[SR Flipflop]/sr_ff.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: Prajwal N 4 | // Create Date: 23:39:29 12/04/2022 5 | // Design Name: SR FlipFlop 6 | // Module Name: sr_ff 7 | // Tool versions: ISE Design Suit 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module sr_ff(clk,rst,s,r,q,qbar); 11 | input clk,rst,s,r; 12 | output q,qbar; 13 | reg q,qbar; 14 | always@(posedge clk) 15 | begin 16 | if(rst==0) 17 | q=0; 18 | else 19 | case({s,r}) 20 | 2'b00:begin 21 | q=q; 22 | qbar=~q; 23 | end 24 | 2'b01:begin 25 | q=0; 26 | qbar=~q; 27 | end 28 | 2'b10:begin 29 | q=1; 30 | qbar=~q; 31 | end 32 | 2'b11:begin 33 | q=1'bz; 34 | qbar=~q; 35 | end 36 | endcase 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /Day17[SR Flipflop]/sr_ff_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Author: Prajwal N 5 | // Create Date: 23:44:22 12/04/2022 6 | // Design Name: sr_ff 7 | // Module Name: P:/xilin programs/verilog/sr_flipflop/sr_ff_tb.v 8 | // Project Name: sr_flipflop 9 | // Tool versions: ISE Design Suit 14.7 10 | // Verilog Test Fixture created by ISE for module: sr_ff 11 | // Revision 0.01 - File Created 12 | //////////////////////////////////////////////////////////////////////////////// 13 | 14 | module sr_ff_tb; 15 | 16 | reg clk; 17 | reg rst; 18 | reg s; 19 | reg r; 20 | 21 | wire q; 22 | wire qbar; 23 | 24 | sr_ff uut (.clk(clk),.rst(rst),.s(s),.r(r),.q(q),.qbar(qbar)); 25 | 26 | initial 27 | begin 28 | /* we can also use $random function 29 | initial begin 30 | {s,r}=$random; 31 | #10; 32 | end 33 | instead of giving all inputs*/ 34 | clk = 0; 35 | rst = 0; 36 | #10 rst=1; 37 | s=0;r=0; 38 | #10 $display($time," s=%b r=%b q=%b qbar=%d",s,r,q,qbar); 39 | s=0;r=1; 40 | #10 $display($time," s=%b r=%b q=%b qbar=%d",s,r,q,qbar); 41 | s=1;r=0; 42 | #10 $display($time," s=%b r=%b q=%b qbar=%d",s,r,q,qbar); 43 | s=1;r=1; 44 | #10 $display($time," s=%b r=%b q=%b qbar=%d",s,r,q,qbar); 45 | #10 $finish; 46 | end 47 | always 48 | #5 clk=~clk; 49 | 50 | endmodule 51 | 52 | -------------------------------------------------------------------------------- /Day17[SR Flipflop]/sr_flipflop_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day17[SR Flipflop]/sr_flipflop_output.png -------------------------------------------------------------------------------- /Day17[SR Flipflop]/sr_flipflop_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day17[SR Flipflop]/sr_flipflop_waveform.png -------------------------------------------------------------------------------- /Day18[D Flipflop]/blk.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day18[D Flipflop]/blk.PNG -------------------------------------------------------------------------------- /Day18[D Flipflop]/dff.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: Prajwal N 4 | // Create Date: 00:16:09 12/8/2022 5 | // Module Name: dff 6 | // Project Name: D flipflop 7 | // Tool versions: Xilinx ISE Design Suit 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module DFF(Q,Qbar,D,Clk,Reset); 11 | 12 | output reg Q; 13 | 14 | output Qbar; 15 | 16 | input D,Clk,Reset; 17 | 18 | assign Qbar = ~Q; 19 | 20 | always @(posedge Clk) 21 | 22 | begin 23 | 24 | if (Reset == 1'b1) //If not at reset 25 | 26 | Q = 1'b0; 27 | 28 | else 29 | 30 | Q = D; 31 | 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Day18[D Flipflop]/dff_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Author: Prajwal N 5 | // Create Date: 00:24:29 12/8/2022 6 | // Design Name: D flipflop 7 | // Module Name: P:/xilin programs/verilog/dff/dff_tb.v 8 | // Project Name: D Flipflop 9 | // Tool versions: Xilinx ISE Design Suit 14.7 10 | // Verilog Test Fixture created by ISE for module: clockdivider 11 | // Revision 0.01 - File Created 12 | //////////////////////////////////////////////////////////////////////////////// 13 | module DFF_tb; 14 | 15 | // Inputs 16 | 17 | reg D; 18 | 19 | reg Clk; 20 | 21 | reg Reset; 22 | 23 | // Outputs 24 | 25 | wire Q; 26 | 27 | wire Qbar; 28 | 29 | DFF uut (.Q(Q),.Qbar(Qbar),.D(D),.Clk(Clk),.Reset(Reset)); 30 | 31 | initial begin 32 | $monitor( " D=%b Q=%b Qbar=%b",D,Q,Qbar); 33 | end 34 | initial begin 35 | 36 | D = 1'b0; 37 | 38 | Clk = 1'b0; 39 | 40 | Reset = 1'b1; 41 | 42 | #100; 43 | 44 | Reset = 1'b0; 45 | 46 | #20; 47 | 48 | forever #40 D = ~ D; 49 | 50 | end 51 | 52 | always #10 Clk = ~Clk; 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /Day18[D Flipflop]/wf.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day18[D Flipflop]/wf.PNG -------------------------------------------------------------------------------- /Day20[Clock Divider]/clkdivider_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Author: Prajwal N 5 | // Create Date: 00:24:29 12/10/2022 6 | // Design Name: clockdivider 7 | // Module Name: P:/xilin programs/verilog/clockdivider/clkdivider_tb.v 8 | // Project Name: clockdivider 9 | // Tool versions: Xilinx ISE Design Suit 14.7 10 | // Verilog Test Fixture created by ISE for module: clockdivider 11 | // Revision 0.01 - File Created 12 | //////////////////////////////////////////////////////////////////////////////// 13 | 14 | module clkdivider_tb; 15 | 16 | // Inputs 17 | reg clk; 18 | reg rst; 19 | 20 | // Outputs 21 | wire clk2; 22 | wire clk4; 23 | wire clk8; 24 | 25 | // Instantiate the Unit Under Test (UUT) 26 | clockdivider uut ( 27 | .clk(clk), 28 | .clk2(clk2), 29 | .clk4(clk4), 30 | .clk8(clk8), 31 | .rst(rst) 32 | ); 33 | 34 | initial begin 35 | // Initialize Inputs 36 | clk = 0; 37 | rst = 0; 38 | #50 rst=1; 39 | 40 | // Add stimulus here 41 | 42 | end 43 | always 44 | #10 clk=~clk; 45 | 46 | endmodule 47 | 48 | -------------------------------------------------------------------------------- /Day20[Clock Divider]/clock_divider_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day20[Clock Divider]/clock_divider_waveform.png -------------------------------------------------------------------------------- /Day20[Clock Divider]/clockdivider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: Prajwal N 4 | // Create Date: 00:16:09 12/10/2022 5 | // Module Name: clockdivider 6 | // Project Name: Clock Divider 7 | // Tool versions: Xilinx ISE Design Suit 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module clockdivider(clk,clk2,clk4,clk8,rst); 11 | input clk,rst; 12 | reg [3:0]count; 13 | output clk2,clk4,clk8; 14 | reg clk2,clk4,clk8; 15 | always@(posedge clk) 16 | begin 17 | if(rst==0) 18 | count=4'b0000; 19 | else 20 | count=count+1; 21 | clk2=count[1]; 22 | clk4=count[2]; 23 | clk8=count[3]; 24 | end 25 | endmodule 26 | -------------------------------------------------------------------------------- /Day21[Ring Counter]/ring_counter_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day21[Ring Counter]/ring_counter_output.png -------------------------------------------------------------------------------- /Day21[Ring Counter]/ring_counter_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day21[Ring Counter]/ring_counter_waveform.png -------------------------------------------------------------------------------- /Day21[Ring Counter]/ringcounter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: Prajwal N 4 | // Create Date: 23:34:29 12/09/2022 5 | // Module Name: ringcounter 6 | // Project Name: Ring Counter 7 | // Tool versions: Xilinx ISE Desing 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module ringcounter(dout,clk,rst); 11 | input clk,rst; 12 | output [3:0]dout; 13 | reg [3:0] dout; 14 | always @ (posedge clk) 15 | begin 16 | if(rst==0) 17 | dout=4'b0001; 18 | else 19 | dout={dout[0],dout[3:1]}; 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /Day21[Ring Counter]/ringcounter_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Author: Prajwal N 5 | // Create Date: 23:42:32 12/09/2022 6 | // Design Name: ringcounter 7 | // Module Name: P:/xilin programs/verilog/Ringcounter/ringcounter_tb.v 8 | // Project Name: Ringcounter 9 | // Tool versions: Xilinx ISE Design Suit 14.7 10 | // Verilog Test Fixture created by ISE for module: ringcounter 11 | // Revision 0.01 - File Created 12 | //////////////////////////////////////////////////////////////////////////////// 13 | 14 | module ringcounter_tb; 15 | 16 | reg clk; 17 | reg rst; 18 | 19 | wire [3:0] dout; 20 | 21 | ringcounter uut (.dout(dout),.clk(clk),.rst(rst)); 22 | initial 23 | begin 24 | $monitor($time," dout=%b ",dout); 25 | end 26 | 27 | initial 28 | begin 29 | clk=0; 30 | rst=0; 31 | #50 rst=1; 32 | end 33 | always 34 | #10 clk=~clk; 35 | 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /Day22[Jhonson Counter]/jhonson_counter_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day22[Jhonson Counter]/jhonson_counter_output.png -------------------------------------------------------------------------------- /Day22[Jhonson Counter]/jhonson_counter_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day22[Jhonson Counter]/jhonson_counter_waveform.png -------------------------------------------------------------------------------- /Day22[Jhonson Counter]/jhonson_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Author: Prajwal N 5 | // Create Date: 23:18:06 12/11/2022 6 | // Design Name: jhonsoncounter 7 | // Module Name: P:/xilin programs/verilog/JhonsonCounter/jhonson_tb.v 8 | // Project Name: JhonsonCounter 9 | // Tool versions: Xilinx ISE Design 14.7 10 | // Verilog Test Fixture created by ISE for module: jhonsoncounter 11 | // Revision 0.01 - File Created 12 | //////////////////////////////////////////////////////////////////////////////// 13 | 14 | module jhonson_tb; 15 | 16 | // Inputs 17 | reg clk; 18 | reg rst; 19 | 20 | // Outputs 21 | wire [3:0] dout; 22 | 23 | jhonsoncounter uut (.dout(dout),.clk(clk),.rst(rst)); 24 | initial 25 | begin 26 | $monitor($time," dout=%b",dout); 27 | end 28 | initial begin 29 | 30 | clk = 0; 31 | rst = 0; 32 | #50 rst=1; 33 | end 34 | always 35 | #10 clk=~clk; 36 | 37 | endmodule 38 | 39 | -------------------------------------------------------------------------------- /Day22[Jhonson Counter]/jhonsoncounter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: Prajwal N 4 | // Create Date: 23:05:07 12/11/2022 5 | // Module Name: jhonsoncounter 6 | // Project Name: Jhonson Counter 7 | // Tool versions: Xilinx ISE Design 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module jhonsoncounter(dout,clk,rst); 11 | input clk,rst; 12 | output [3:0]dout; 13 | reg [3:0] dout; 14 | always @(posedge clk) 15 | begin 16 | if (rst==0) 17 | dout=4'b0001; 18 | else 19 | dout={~dout[0],dout[3:1]}; 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /Day23[Binary-Gray]/Binary-Gray.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: Prajwal N 4 | // Create Date: 21:53:07 12/12/2022 5 | // Module Name: Binary-Gray 6 | // Project Name: Binary To Gray 7 | // Tool versions: Xilinx ISE Design Suit 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module Binary_Gray(B,G); 11 | input[3:0] B; 12 | output [3:0]G; 13 | assign G[3]=B[3]; 14 | assign G[2]=B[3]^B[2]; 15 | assign G[1]=B[2]^B[1]; 16 | assign G[0]=B[1]^B[0]; 17 | endmodule 18 | -------------------------------------------------------------------------------- /Day23[Binary-Gray]/Binary-to-Gray_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day23[Binary-Gray]/Binary-to-Gray_output.png -------------------------------------------------------------------------------- /Day23[Binary-Gray]/Binary-to-Gray_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day23[Binary-Gray]/Binary-to-Gray_waveform.png -------------------------------------------------------------------------------- /Day23[Binary-Gray]/Binary_Gray_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Author: Prajwal N 5 | // Create Date: 21:57:42 12/12/2022 6 | // Design Name: Binary_Gray 7 | // Module Name: P:/xilin programs/verilog/Binary_Gray/Binary_Gray_tb.v 8 | // Project Name: Binary_Gray 9 | // Tool versions: Xilinx ISE Design Suit 14.7 10 | // Verilog Test Fixture created by ISE for module: Binary_Gray 11 | // Revision 0.01 - File Created 12 | //////////////////////////////////////////////////////////////////////////////// 13 | 14 | module Binary_Gray_tb; 15 | 16 | reg [3:0] B; 17 | 18 | wire [3:0] G; 19 | 20 | integer i; 21 | 22 | Binary_Gray uut (.B(B),.G(G)); 23 | initial 24 | begin 25 | $monitor($time," Binary=%b > %d Gray=%b >%d",B,B,G,G); 26 | end 27 | 28 | initial 29 | begin 30 | for(i=0;i<16;i=i+1) 31 | begin 32 | B=i; 33 | #10; 34 | end 35 | $finish; 36 | end 37 | 38 | endmodule 39 | 40 | -------------------------------------------------------------------------------- /Day24[Gray_Binary]/G_B.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: Prajwal N 4 | // Create Date: 22:29:13 12/13/2022 5 | // Design Name: Gray to Binary 6 | // Module Name: G_B 7 | // Project Name: Gray to Binary code converter 8 | // Tool versions: Xilinx ISE Design Suit 14.7 9 | // Revision 0.01 - File Created 10 | ////////////////////////////////////////////////////////////////////////////////// 11 | module G_B(G,B); 12 | input [3:0]G; 13 | output [3:0]B; 14 | assign B[3]=G[3]; 15 | assign B[2]=G[3]^G[2]; 16 | assign B[1]=G[3]^G[2]^G[1]; 17 | assign B[0]=G[3]^G[2]^G[1]^G[0]; 18 | endmodule 19 | -------------------------------------------------------------------------------- /Day24[Gray_Binary]/Gray_to_Binary_Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day24[Gray_Binary]/Gray_to_Binary_Output.png -------------------------------------------------------------------------------- /Day24[Gray_Binary]/Gray_to_Binary_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Prajwal-ECE/RTL-Coding/7fbce243e2e033bb0ce75c86bae8daec1b96b6dc/Day24[Gray_Binary]/Gray_to_Binary_waveform.png -------------------------------------------------------------------------------- /Day24[Gray_Binary]/g_b_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Author: Prajwal N 5 | // Create Date: 22:33:15 12/13/2022 6 | // Design Name: G_B 7 | // Module Name: P:/xilin programs/verilog/Grat_Binary/g_b_tb.v 8 | // Project Name: Grat_Binary 9 | // Tool versions: Xilinx ISE Design Suit 14.7 10 | // Verilog Test Fixture created by ISE for module: G_B 11 | // Revision 0.01 - File Created 12 | //////////////////////////////////////////////////////////////////////////////// 13 | 14 | module g_b_tb; 15 | 16 | reg [3:0] G; 17 | 18 | wire [3:0] B; 19 | integer i; 20 | 21 | G_B uut (.G(G),.B(B)); 22 | initial 23 | begin 24 | $monitor($time," Gray=%b > %d Binary=%b > %d",G,G,B,B); 25 | end 26 | 27 | initial begin 28 | G = 0; 29 | for(i=0;i<16;i=i+1) 30 | begin 31 | G=i; 32 | #10; 33 | end 34 | $finish; 35 | end 36 | 37 | endmodule 38 | 39 | -------------------------------------------------------------------------------- /Day25[N_bit_adder]/full_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: Prajwal N 4 | // Create Date: 23:13:43 12/14/2022 5 | // Module Name: full_adder 6 | // Project Name: Full Adder 7 | // Tool versions: Xilinx ISE Design Suit 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module full_adder(a,b,cin,s,carry); 11 | input a,b,cin; 12 | output s,carry; 13 | assign s=a^b^cin; 14 | assign carry=(a&b)|(b&cin)|(cin&a); 15 | endmodule 16 | -------------------------------------------------------------------------------- /Day25[N_bit_adder]/half_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:16:39 12/14/2022 7 | // Design Name: 8 | // Module Name: half_adder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module half_adder(a,b,s,carry); 22 | input a,b; 23 | output s,carry; 24 | assign s=a^b; 25 | assign carry=a&b; 26 | endmodule 27 | -------------------------------------------------------------------------------- /Day25[N_bit_adder]/n_bit_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Author: Prajwal N 4 | // Create Date: 23:52:46 12/14/2022 5 | // Module Name: n_bit_adder 6 | // Project Name: N Bit adder 7 | // Tool versions: Xilinx ISE Design Suit 14.7 8 | // Revision 0.01 - File Created 9 | ////////////////////////////////////////////////////////////////////////////////// 10 | module n_bit_adder(a,b,y); 11 | parameter N=32; 12 | input [N-1:0] a,b; 13 | output [N-1:0] y; 14 | wire carry_out; 15 | wire [N-1:0] carry; 16 | genvar i; 17 | generate 18 | for(i=0;ib) 17 | begin 18 | L=0;E=0;G=1; 19 | end 20 | else if (a