├── README.md ├── rtl ├── src │ ├── edgeDetector.v │ ├── fine_counter.v │ ├── UART.sv │ ├── Coarse_Counter_22.v │ ├── TDC.v │ ├── fine_tdc.vhd │ ├── TOP.v │ └── encoder.v └── sim │ ├── toptest.v │ └── wf_cfg │ └── topteset_time_synth.wcfg ├── constraints └── const_051022.xdc ├── rebuild.tcl └── ip └── fifo_ip └── fifo_generator_0.xci /README.md: -------------------------------------------------------------------------------- 1 | # tdcOnFPGA 2 | 3 | Implementation of tappped delay line TDC on FPGA 4 | 5 | A TDC is developed targeting Xilinx-Virtex7 FPGA. 6 | -------------------------------------------------------------------------------- /rtl/src/edgeDetector.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/26/2022 06:24:26 PM 7 | // Design Name: 8 | // Module Name: edgeDetector 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module edgeDetector 24 | ( 25 | input wire clk, reset, 26 | input wire level, 27 | output reg out 28 | ); 29 | 30 | localparam [1:0] // 3 states are required for Moore 31 | zeroMoore = 2'b00, 32 | edgeMoore = 2'b01, 33 | oneMoore = 2'b10, 34 | delay = 2'b11; 35 | 36 | reg[1:0] stateMoore_reg, stateMoore_next; 37 | 38 | always @(posedge clk, posedge reset) 39 | begin 40 | if(reset) // go to state zero if rese 41 | begin 42 | stateMoore_reg <= zeroMoore; 43 | end 44 | else // otherwise update the states 45 | begin 46 | stateMoore_reg <= stateMoore_next; 47 | end 48 | end 49 | 50 | // Moore Design 51 | always @(stateMoore_reg, level) 52 | begin 53 | // store current state as next 54 | stateMoore_next = stateMoore_reg; // required: when no case statement is satisfied 55 | // set tick to zero (so that 'tick = 1' is available for 1 cycle only) 56 | case(stateMoore_reg) 57 | zeroMoore: // if state is zero, 58 | if(level) // and level is 1 59 | stateMoore_next = edgeMoore; // then go to state edge. 60 | edgeMoore: 61 | begin 62 | out = 1'b1; 63 | stateMoore_next = oneMoore; 64 | end 65 | oneMoore: begin 66 | out = 1'b0; 67 | if (~level) 68 | stateMoore_next = zeroMoore; // then go to state zero. 69 | end 70 | endcase 71 | end 72 | endmodule 73 | -------------------------------------------------------------------------------- /constraints/const_051022.xdc: -------------------------------------------------------------------------------- 1 | #SMA 2 | set_property PACKAGE_PIN AN31 [get_ports start] 3 | set_property IOSTANDARD LVCMOS18 [get_ports start] 4 | set_property PACKAGE_PIN AP31 [get_ports stop] 5 | set_property IOSTANDARD LVCMOS18 [get_ports stop] 6 | 7 | #buttons 8 | #set_property PACKAGE_PIN AR40 [get_ports start] #N 9 | #set_property IOSTANDARD LVCMOS18 [get_ports start] 10 | #set_property PACKAGE_PIN AP40 [get_ports stop] #S 11 | #set_property IOSTANDARD LVCMOS18 [get_ports stop] 12 | 13 | #set_property PACKAGE_PIN AW40 [get_ports test] 14 | #set_property IOSTANDARD LVCMOS18 [get_ports test] 15 | 16 | 17 | set_property PACKAGE_PIN AU38 [get_ports enable] 18 | set_property IOSTANDARD LVCMOS18 [get_ports enable] 19 | #E 20 | set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets start_IBUF] 21 | set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets stop_IBUF] 22 | 23 | #set_property PACKAGE_PIN AM39 [get_ports led_1] 24 | #set_property IOSTANDARD LVCMOS18 [get_ports led_1] 25 | #set_property PACKAGE_PIN AN39 [get_ports led_2] 26 | #set_property IOSTANDARD LVCMOS18 [get_ports led_2] 27 | #set_property PACKAGE_PIN AR37 [get_ports led_3] 28 | #set_property IOSTANDARD LVCMOS18 [get_ports led_3] 29 | #set_property PACKAGE_PIN AT37 [get_ports led_4] 30 | #set_property IOSTANDARD LVCMOS18 [get_ports led_4] 31 | #set_property PACKAGE_PIN AR35 [get_ports led_5] 32 | #set_property IOSTANDARD LVCMOS18 [get_ports led_5] 33 | 34 | set_property PACKAGE_PIN AU36 [get_ports tx] 35 | set_property IOSTANDARD LVCMOS18 [get_ports tx] 36 | 37 | set_property IOSTANDARD LVDS [get_ports clk_p] 38 | set_property PACKAGE_PIN E19 [get_ports clk_p] 39 | set_property PACKAGE_PIN E18 [get_ports clk_n] 40 | set_property IOSTANDARD LVDS [get_ports clk_n] 41 | 42 | set_property PACKAGE_PIN AV39 [get_ports reset_button] 43 | set_property IOSTANDARD LVCMOS18 [get_ports reset_button] 44 | #C 45 | 46 | set_max_delay -through [get_ports stop] 40.000 47 | set_max_delay -through [get_ports start] 40.000 48 | 49 | set_max_delay -from [get_ports stop] -to [all_registers] 40.000 50 | set_max_delay -from [get_ports start] -to [all_registers] 40.000 51 | 52 | set_max_delay -from [all_inputs] -to [all_outputs] 60.000 53 | #set_false_path -through [get_ports stop] 54 | #set_false_path -through [get_ports start] 55 | 56 | -------------------------------------------------------------------------------- /rtl/src/fine_counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/10/2022 11:09:01 AM 7 | // Design Name: 8 | // Module Name: fine_counter 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module fine_counter( 24 | input start, 25 | input stop, //clock 26 | input reset, 27 | input clk, 28 | 29 | output [9:0] data 30 | ); 31 | 32 | parameter x = 0 ,y = 0; 33 | 34 | wire [1023:0] out_bus; 35 | reg flag_read; 36 | reg enable; 37 | 38 | fine_tdc #( 39 | .Xoff(x), 40 | .Yoff(y)) 41 | fine 42 | ( 43 | .trigger(start), 44 | .reset(reset), 45 | .clock(stop), 46 | .latched_output(out_bus) 47 | ); 48 | 49 | encoder encode( 50 | .clk(enable), 51 | .op(out_bus), 52 | .en_op(data) 53 | ); 54 | 55 | // STATE MACHINE 56 | 57 | localparam [2:0] 58 | WAIT_FS = 3'b000, 59 | HOLD = 3'b001, 60 | HOLD2 = 3'b010, 61 | HOLD3 = 3'b011 62 | ; 63 | 64 | reg [2:0] state, next; 65 | 66 | initial begin 67 | state = WAIT_FS; 68 | end 69 | 70 | always @(posedge clk) begin 71 | if (reset) begin 72 | state <= WAIT_FS; 73 | end 74 | else begin 75 | state <= next; 76 | end 77 | end 78 | 79 | always @ (posedge clk) begin 80 | case(state) 81 | WAIT_FS : begin 82 | enable = 0; 83 | if(start == 1) begin 84 | next = HOLD; 85 | end 86 | else begin 87 | next = WAIT_FS; 88 | end 89 | end 90 | 91 | HOLD : begin 92 | enable = 1; 93 | next = HOLD3; 94 | end 95 | 96 | HOLD3 : begin 97 | enable = 0; 98 | if(start == 0) begin 99 | next = WAIT_FS; 100 | end 101 | else begin 102 | next = HOLD3; 103 | end 104 | end 105 | endcase 106 | end 107 | endmodule 108 | -------------------------------------------------------------------------------- /rtl/sim/toptest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09/16/2022 03:48:48 PM 7 | // Design Name: 8 | // Module Name: tdctest 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module topteset(); 24 | 25 | reg clk_p; 26 | reg clk_n; 27 | // reg en; 28 | reg start; 29 | reg stop; 30 | reg enable; 31 | reg reset; 32 | // reg t; 33 | 34 | wire [39:0] TDC_out; 35 | wire valid; 36 | wire out; 37 | integer f,j; 38 | real i; 39 | 40 | 41 | TOP test ( 42 | .clk_p(clk_p), 43 | .clk_n(clk_n), 44 | .start (start), 45 | .stop (stop), 46 | .reset_button(reset), 47 | .enable(enable), 48 | .tx(out) 49 | ); 50 | 51 | // fine_tdc test ( 52 | // .trigger (start), 53 | // .clock (clk_p), 54 | // .latched_output (out) 55 | // ); 56 | 57 | initial begin 58 | clk_p = 1'b1; 59 | forever #2.5 clk_p = ~clk_p; 60 | end 61 | 62 | initial begin 63 | clk_n = 1'b0; 64 | start = 1'b0; 65 | stop = 1'b0; 66 | forever #2.5 clk_n = ~clk_n; 67 | end 68 | 69 | // initial begin 70 | // forever #100000 start = ~start; 71 | // end 72 | 73 | // initial begin 74 | // #100 75 | // forever #100000 stop = ~stop; 76 | // end 77 | initial begin 78 | 79 | #10 80 | enable = 0; 81 | start = 0; 82 | stop = 0; 83 | reset = 0; 84 | #500 85 | reset = 1; 86 | #30 87 | reset = 0; 88 | #394.75 89 | for (j = 1; j<500; j = j+1) begin 90 | 91 | #200 92 | start = 1; 93 | #j 94 | stop = 1; 95 | #15 96 | stop = 0; 97 | start = 0; 98 | 99 | end 100 | 101 | 102 | // for (i = 0.01; i<1; i=i+0.05) begin 103 | // #50 104 | 105 | // #i 106 | // start = 1; 107 | // #5 108 | // stop = 1; 109 | // #15 110 | // stop = 0; 111 | // start = 0; 112 | 113 | 114 | // end 115 | 116 | // end 117 | 118 | // always @(posedge valid) begin 119 | // f = $fopen("output.txt","a"); 120 | // $fwrite(f,"%b\n",TDC_out); 121 | // $fclose(f); 122 | end 123 | endmodule -------------------------------------------------------------------------------- /rtl/src/UART.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14.08.2022 16:04:15 7 | // Design Name: 8 | // Module Name: tx_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module UART #( 24 | parameter baudRate = 9600, 25 | parameter clkFreq = 132000000 26 | )( 27 | input logic clk, 28 | input logic reset, 29 | input logic[7:0] data, 30 | input logic send_trigger, 31 | 32 | output logic signal, 33 | output logic done 34 | // output logic rts, 35 | // output logic debug_1, 36 | // output logic debug_2, 37 | // output logic debug_3, 38 | // output logic debug_4 39 | ); 40 | 41 | 42 | //assign rts = 0; 43 | //assign send_trigger = 1; 44 | 45 | //initial debug_1 = 1'b0; 46 | //initial debug_2 = 1'b0; 47 | //initial debug_3 = 1'b0; 48 | //initial debug_4 = 1'b0; 49 | //initial debug_1 = 1'b0; 50 | 51 | //wire clk; 52 | //reg done; 53 | 54 | typedef enum { IDLE, START_BIT, DATA_BITS, STOP_BIT, DONE } State; 55 | State uart_send_state = IDLE; 56 | 57 | int count = 0; 58 | int clkPulsesPerBit = clkFreq / baudRate; 59 | int bits_send = 0; 60 | logic[7:0] dataToSend; 61 | logic startTransmission = 0; 62 | 63 | //always @(send_trigger) begin 64 | // debug_1 <= 1'b1; 65 | //end 66 | 67 | 68 | //always @(posedge send_trigger) begin 69 | // trig <= 1; 70 | //end 71 | 72 | //always @(negedge clk) begin 73 | // trig <= 0; 74 | //end 75 | 76 | 77 | always @(posedge clk) begin 78 | count <= count + 1; 79 | 80 | case (uart_send_state) 81 | IDLE: begin 82 | signal <= 1; 83 | 84 | if (send_trigger == 1) begin 85 | uart_send_state <= START_BIT; 86 | count <= 0; 87 | dataToSend <= data; 88 | 89 | // debug_2 <= 1; 90 | end 91 | end 92 | START_BIT: begin 93 | signal <= 0; 94 | 95 | // debug_1 <= 1; 96 | 97 | if (count == clkPulsesPerBit) begin 98 | uart_send_state <= DATA_BITS; 99 | bits_send <= 0; 100 | count <= 0; 101 | end 102 | end 103 | DATA_BITS: begin 104 | signal <= dataToSend[bits_send]; 105 | 106 | // debug_3 <= signal; 107 | 108 | if (count == clkPulsesPerBit) begin 109 | count <= 0; 110 | bits_send <= bits_send + 1; 111 | 112 | if (bits_send == 7) begin 113 | uart_send_state <= STOP_BIT; 114 | end 115 | end 116 | end 117 | STOP_BIT: begin 118 | signal <= 1; 119 | 120 | if (count == clkPulsesPerBit) begin 121 | count <= 0; 122 | done <= 1; 123 | uart_send_state <= DONE; 124 | end 125 | end 126 | DONE : begin 127 | done <= 0; 128 | uart_send_state <= IDLE; 129 | end 130 | default: uart_send_state <= IDLE; 131 | endcase 132 | end 133 | endmodule 134 | 135 | -------------------------------------------------------------------------------- /rtl/sim/wf_cfg/topteset_time_synth.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | clk_out1 28 | clk_out1 29 | 30 | 31 | start 32 | start 33 | 34 | 35 | stop 36 | stop 37 | 38 | 39 | start_IBUF 40 | start_IBUF 41 | 42 | 43 | stop_IBUF 44 | stop_IBUF 45 | 46 | 47 | trigger 48 | trigger 49 | 50 | 51 | clock 52 | clock 53 | 54 | 55 | Q[8:0] 56 | Q[8:0] 57 | UNSIGNEDDECRADIX 58 | 59 | 60 | enable 61 | enable 62 | 63 | 64 | reset 65 | reset 66 | 67 | 68 | latched_output[511:0] 69 | latched_output[511:0] 70 | 71 | 72 | D[15:0] 73 | D[15:0] 74 | 75 | 76 | -------------------------------------------------------------------------------- /rtl/src/Coarse_Counter_22.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/22/2022 04:40:58 PM 7 | // Design Name: 8 | // Module Name: Coarse_Counter_22 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Coarse_Counter_22( 24 | input clk, 25 | input start, 26 | input stop, 27 | input reset, 28 | output reg[15:0] data 29 | ); 30 | 31 | reg start_hold; 32 | reg [15:0] counter; 33 | reg set; 34 | reg [1:0] start_flag; 35 | reg [15:0] thanos; 36 | 37 | // initial begin 38 | // start_flag = 0; 39 | // state = WAIT_FS; 40 | // counter = 0; 41 | // end 42 | 43 | always @(posedge clk) begin 44 | if(start_hold == 1'b1) begin 45 | if(stop == 1'b1) begin 46 | thanos <= counter + 1; 47 | end 48 | else begin 49 | counter = counter + 1; 50 | end 51 | end 52 | if(set == 1'b1) begin 53 | counter = 0; 54 | end 55 | end 56 | 57 | always @(posedge clk) begin 58 | if(start == 1'b1 && start_flag == 1'b0) begin 59 | set = 0; 60 | start_hold = 1; 61 | start_flag = 1; 62 | end 63 | 64 | if(stop == 1'b1 && start_flag == 1'b1) begin 65 | start_flag = 2; 66 | end 67 | 68 | if(start == 1'b0 && stop == 1'b0 && start_flag == 2) begin 69 | start_hold = 0; 70 | start_flag = 0; 71 | set = 1; 72 | end 73 | end 74 | 75 | //STATE MACHINE 76 | localparam [2:0] 77 | WAIT_FS = 3'b000, 78 | WAIT_FT = 3'b001, 79 | COUNTER = 3'b010, 80 | RESET = 3'b011 81 | ; 82 | 83 | reg [2:0] state, next; 84 | 85 | always @(posedge clk, posedge reset) begin 86 | if (reset) begin 87 | state <= WAIT_FS; 88 | end 89 | else begin 90 | state <= next; 91 | end 92 | end 93 | 94 | 95 | always @(posedge clk) begin 96 | case(state) 97 | WAIT_FS : begin 98 | if(start == 1'b1 && stop == 1'b1) begin 99 | data = 0; 100 | next = RESET; 101 | end 102 | else if (start == 1'b1) begin 103 | next = WAIT_FT; 104 | end 105 | else begin 106 | next = WAIT_FS; 107 | end 108 | end 109 | 110 | WAIT_FT : begin 111 | if(stop == 1'b1) begin 112 | next = COUNTER; 113 | end 114 | else begin 115 | next = WAIT_FT; 116 | end 117 | end 118 | 119 | COUNTER : begin 120 | data <= thanos; 121 | next <= RESET; 122 | end 123 | 124 | RESET : begin 125 | if(start == 1'b0 && stop == 1'b0) begin 126 | next = WAIT_FS; 127 | end 128 | else begin 129 | next = RESET; 130 | end 131 | end 132 | endcase 133 | end 134 | 135 | endmodule 136 | -------------------------------------------------------------------------------- /rtl/src/TDC.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/06/2022 11:00:54 AM 7 | // Design Name: 8 | // Module Name: TDC 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module TDC( 24 | input clk, 25 | input start, 26 | input stop, 27 | input reset, 28 | 29 | output reg [39:0] data, 30 | output reg valid 31 | ); 32 | 33 | wire [9:0] fine1_out; 34 | wire [9:0] fine2_out; 35 | wire [15:0] course_out; 36 | wire coarse_done; 37 | reg set; 38 | wire or_reset; 39 | wire fine1_stop; 40 | wire fine2_stop; 41 | 42 | or(or_reset, set, reset); 43 | 44 | edgeDetector Start ( 45 | .clk(clk), 46 | .reset(or_reset), 47 | .level(start), 48 | .out(fine1_stop) 49 | ); 50 | 51 | edgeDetector Stop ( 52 | .clk(clk), 53 | .reset(or_reset), 54 | .level(stop), 55 | .out(fine2_stop) 56 | ); 57 | 58 | fine_counter #( 59 | .x(46), 60 | .y(4) 61 | ) fine1 ( 62 | .start(start), 63 | .stop(fine1_stop), 64 | .reset(or_reset), 65 | .clk(clk), 66 | .data(fine1_out) 67 | ); 68 | 69 | fine_counter #( 70 | .x(47), 71 | .y(3) 72 | ) fine2 ( 73 | .start(stop), 74 | .stop(fine2_stop), 75 | .reset(or_reset), 76 | .clk(clk), 77 | .data(fine2_out) 78 | ); 79 | 80 | Coarse_Counter_22 coarse ( 81 | .start(start), 82 | .stop(stop), 83 | .clk(clk), 84 | .data(course_out), 85 | .reset(or_reset) 86 | ); 87 | 88 | //STATE MACHINE 89 | 90 | localparam [2:0] 91 | WAIT_FS = 3'b000, 92 | WAIT_FP = 3'b001, 93 | VALID = 3'b010, 94 | WAIT_FR = 3'b011, 95 | WAIT_FSub = 3'b100, 96 | WAIT_FSub2 = 3'b101 97 | ; 98 | 99 | reg [2:0] state, next; 100 | 101 | initial begin 102 | state <= WAIT_FS; 103 | end 104 | 105 | always @(posedge clk, posedge reset) begin 106 | if (reset) begin 107 | state <= WAIT_FS; 108 | end 109 | else begin 110 | state <= next; 111 | end 112 | end 113 | 114 | always @(posedge clk) begin 115 | 116 | case (state) 117 | WAIT_FS : begin 118 | set = 1'b0; 119 | if(start == 1'b1) begin 120 | next <= WAIT_FP; 121 | end 122 | else begin 123 | next <= WAIT_FS; 124 | valid <= 1'b0; 125 | end 126 | end 127 | 128 | WAIT_FP : begin 129 | if(stop == 1'b1) begin 130 | next <= WAIT_FSub; 131 | end 132 | else begin 133 | next <= WAIT_FP; 134 | valid <= 1'b0; 135 | end 136 | end 137 | 138 | WAIT_FSub : begin 139 | next <= WAIT_FSub2; 140 | end 141 | 142 | WAIT_FSub2 : begin 143 | next <= VALID; 144 | end 145 | 146 | VALID : begin 147 | data[23:14] <= fine1_out[9:0]; 148 | data[13:4] <= fine2_out[9:0]; 149 | data[39:24] <= course_out[15:0]; 150 | data[3:0] <= 4'b0101; 151 | valid <= 1'b1; 152 | next <= WAIT_FR; 153 | end 154 | 155 | WAIT_FR : begin 156 | valid <= 1'b0; 157 | set = 1'b1; 158 | if(start == 0 && stop == 0) begin 159 | next <= WAIT_FS; 160 | end 161 | else begin 162 | next <= WAIT_FR; 163 | end 164 | end 165 | endcase 166 | end 167 | 168 | 169 | endmodule 170 | -------------------------------------------------------------------------------- /rtl/src/fine_tdc.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------- 2 | -- Title : FPGA TDC 3 | -- Copyright © 2015 Harald Homulle / Edoardo Charbon 4 | ----------------------------------------------------------------------------- 5 | -- This file is part of FPGA TDC. 6 | 7 | -- FPGA TDC is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | 12 | -- FPGA TDC is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with FPGA TDC. If not, see . 19 | ----------------------------------------------------------------------------- 20 | -- File : fine_tdc.vhd 21 | -- Author : 22 | -- Company : TU Delft 23 | -- Last update: 2015-01-01 24 | -- Platform : FPGA (tested on Spartan 6 and Artix 7) 25 | ----------------------------------------------------------------------------- 26 | -- Description: 27 | -- The main part of the system, i.e. the delayline based TDC. 28 | -- Generating the carrychains and double latching of the output for better stability. 29 | ----------------------------------------------------------------------------- 30 | -- Revisions : 31 | -- Date Version Author Description 32 | -- 2006 1.0 Claudio Created 33 | -- 2014 2.0 Homulle Rewrote core code and added the Therm2bin with counter 34 | ----------------------------------------------------------------------------- 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.ALL; 38 | USE ieee.std_logic_arith.ALL; 39 | USE ieee.math_real.ALL; 40 | 41 | LIBRARY unisim; 42 | USE unisim.vcomponents.ALL; 43 | 44 | ENTITY fine_tdc IS 45 | GENERIC ( 46 | STAGES : INTEGER := 512; 47 | Xoff : INTEGER := 44; 48 | Yoff : INTEGER := 24); 49 | PORT ( 50 | trigger : IN std_logic; -- START signal input (triggers carrychain) 51 | reset : IN std_logic; 52 | clock : IN std_logic; -- STOP signal input (assumed to be clock synchronous) 53 | latched_output : OUT std_logic_vector(STAGES-1 DOWNTO 0)); -- Carrychain output, to be converted to binary 54 | END fine_tdc; 55 | 56 | ARCHITECTURE behaviour OF fine_tdc IS 57 | 58 | -- To place the delayline in a particular spot (best for linearities and resolution), the LOC constraint is used. 59 | ATTRIBUTE LOC : string; 60 | ATTRIBUTE keep_hierarchy : string; 61 | ATTRIBUTE keep_hierarchy OF behaviour : ARCHITECTURE IS "true"; 62 | 63 | SIGNAL unreg : std_logic_vector(STAGES-1 DOWNTO 0); 64 | SIGNAL reg : std_logic_vector(STAGES-1 DOWNTO 0); 65 | 66 | BEGIN 67 | 68 | -- Generation of the carrychain, starting at the specified X, Y coordinate. 69 | carry_delay_line: FOR i IN 0 TO STAGES/4-1 GENERATE 70 | 71 | first_carry4: IF i = 0 GENERATE 72 | 73 | ATTRIBUTE LOC OF delayblock : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff+i); 74 | 75 | BEGIN 76 | 77 | delayblock: CARRY4 78 | PORT MAP( 79 | CO => unreg(3 DOWNTO 0), 80 | CI => '0', 81 | CYINIT => trigger, 82 | DI => "0000", 83 | S => "1111"); 84 | END GENERATE; 85 | 86 | next_carry4: IF i > 0 GENERATE 87 | 88 | ATTRIBUTE LOC OF delayblock : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff+i); 89 | 90 | BEGIN 91 | 92 | delayblock: CARRY4 93 | PORT MAP( 94 | CO => unreg(4*(i+1)-1 DOWNTO 4*i), 95 | CI => unreg(4*i-1), 96 | CYINIT => '0', 97 | DI => "0000", 98 | S => "1111"); 99 | END GENERATE; 100 | END GENERATE; 101 | 102 | -- The output is latched two times for stability reasons. 103 | latch: FOR j IN 0 TO STAGES-1 GENERATE 104 | 105 | --ATTRIBUTE LOC OF FDR_1 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff+integer(floor(real(j/4)))); 106 | --ATTRIBUTE LOC OF FDR_2 : LABEL IS "SLICE_X"&INTEGER'image(Xoff+1)&"Y"&INTEGER'image(Yoff+integer(floor(real(j/4)))); 107 | 108 | BEGIN 109 | 110 | FDR_1: FDR 111 | GENERIC MAP( 112 | INIT => '0') 113 | PORT MAP( 114 | C => clock, 115 | R => reset, 116 | D => unreg(j), 117 | Q => reg(j)); 118 | FDR_2: FDR 119 | GENERIC MAP( 120 | INIT => '0') 121 | PORT MAP( 122 | C => clock, 123 | R => reset, 124 | D => reg(j), 125 | Q => latched_output(j)); 126 | END GENERATE; 127 | 128 | END behaviour; 129 | -------------------------------------------------------------------------------- /rtl/src/TOP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/05/2022 02:39:49 PM 7 | // Design Name: 8 | // Module Name: TOP 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module TOP( 24 | input clk_p, 25 | input clk_n, 26 | input start, 27 | input stop, 28 | input reset_button, 29 | input enable, 30 | 31 | output tx 32 | // output reg [0:7] leds 33 | // output [39:0] TDC_out, 34 | // output val 35 | ); 36 | 37 | wire clk; 38 | wire UART_done; 39 | wire empty; 40 | wire valid; 41 | 42 | reg reset; 43 | reg [7:0] bus_8bit; 44 | wire [39:0] din_40bit; 45 | wire [39:0] dout_40bit; 46 | reg [39:0] buffer; 47 | reg UART_trigger; 48 | reg wr_en; 49 | reg rd_en; 50 | reg FIFO_reset; 51 | 52 | clk_wiz_0 clock ( 53 | .clk_out1 (clk), 54 | .reset (), 55 | .locked (), 56 | .clk_in1_p (clk_p), 57 | .clk_in1_n (clk_n) 58 | ); 59 | 60 | UART transmitter ( 61 | .clk(clk), 62 | .reset(reset), 63 | .data(bus_8bit), 64 | .send_trigger(UART_trigger), 65 | .signal(tx), 66 | .done(UART_done) 67 | ); 68 | 69 | fifo_generator_0 fifo ( 70 | .clk(clk), // input wire clk 71 | .srst(FIFO_reset), // input wire srst 72 | .din(din_40bit), // input wire [39 : 0] din 73 | .wr_en(wr_en), // input wire wr_en 74 | .rd_en(rd_en), // input wire rd_en 75 | .dout(dout_40bit), // output wire [39 : 0] dout 76 | .full(), // output wire full 77 | .empty(empty) // output wire empty 78 | ); 79 | 80 | TDC main ( 81 | .start(start), 82 | .stop(stop), 83 | .clk(clk), 84 | .data(din_40bit), 85 | .valid(valid), 86 | .reset(reset) 87 | ); 88 | 89 | //State Machine 90 | localparam [3:0] 91 | initialize = 4'b0000, 92 | waiting = 4'b0001, 93 | fetch_1 = 4'b0010, 94 | fetch_2 = 4'b0011, 95 | send_1 = 4'b0100, 96 | send_1_w = 4'b0101, 97 | send_2 = 4'b0110, 98 | send_2_w = 4'b0111, 99 | send_3 = 4'b1000, 100 | send_3_w = 4'b1001, 101 | send_4 = 4'b1010, 102 | send_4_w = 4'b1011, 103 | send_5 = 4'b1100, 104 | send_5_w = 4'b1101 105 | ; 106 | 107 | localparam [1:0] 108 | reset_1 = 2'b10, 109 | reset_2 = 2'b11 110 | ; 111 | 112 | localparam [1:0] 113 | state_1 = 2'b00, 114 | state_2 = 2'b01 115 | ; 116 | 117 | localparam [2:0] 118 | LIGHT1 = 3'b000, 119 | LIGHT2 = 3'b001, 120 | LIGHT3 = 3'b010, 121 | LIGHT4 = 3'b011, 122 | LIGHT5 = 3'b100, 123 | LIGHT6 = 3'b101, 124 | LIGHT7 = 3'b110, 125 | LIGHT8 = 3'b111 126 | ; 127 | 128 | localparam TIME = 132000000/3; 129 | 130 | reg [1:0] state_valid, next_valid; 131 | reg [1:0] state_reset, next_reset; 132 | reg [3:0] state, next; 133 | reg [2:0] state_lights, next_lights; 134 | reg [26:0] light_counter; 135 | reg [4:0] timer_f; 136 | 137 | // assign TDC_out = buffer; 138 | // assign val = valid; 139 | 140 | // assign din_40bit = 40'b0000000000111111111100000000001111111111; 141 | 142 | initial begin 143 | state_reset = reset_1; 144 | light_counter = 0; 145 | end 146 | 147 | // // timer 148 | // always @(posedge clk, posedge reset) begin 149 | // if (reset) begin 150 | // light_counter <= 0; 151 | // end 152 | // else begin 153 | // if(state_lights != next_lights) begin // state is changing 154 | // light_counter <= 0; 155 | // end 156 | // else begin 157 | // light_counter <= light_counter + 1; 158 | // end 159 | // end 160 | // end 161 | 162 | // always @(posedge clk) begin 163 | // next_lights = state_lights; 164 | // case(state_lights) 165 | // LIGHT1 : begin 166 | // leds = 8'b10000001; 167 | // if(light_counter >= TIME) begin 168 | // next_lights = LIGHT2; 169 | // end 170 | // end 171 | 172 | // LIGHT2 : begin 173 | // leds = 8'b01000010; 174 | // if(light_counter >= TIME) begin 175 | // next_lights = LIGHT3; 176 | // end 177 | // end 178 | 179 | // LIGHT3 : begin 180 | // leds = 8'b00100100; 181 | // if(light_counter >= TIME) begin 182 | // next_lights = LIGHT4; 183 | // end 184 | // end 185 | 186 | // LIGHT4 : begin 187 | // leds = 8'b00011000; 188 | // if(light_counter >= TIME) begin 189 | // next_lights = LIGHT5; 190 | // end 191 | // end 192 | 193 | // LIGHT5 : begin 194 | // leds = 8'b00100100; 195 | // if(light_counter >= TIME) begin 196 | // next_lights = LIGHT6; 197 | // end 198 | // end 199 | 200 | // LIGHT6 : begin 201 | // leds = 8'b01000010; 202 | // if(light_counter >= TIME) begin 203 | // next_lights = LIGHT1; 204 | // end 205 | // end 206 | 207 | // endcase 208 | // end 209 | 210 | always @(posedge clk) begin 211 | state_reset <= next_reset; 212 | end 213 | 214 | always @(posedge clk) begin 215 | case (state_reset) 216 | reset_1 : begin 217 | if(reset_button == 1'b1) begin 218 | reset <= 1'b1; 219 | next_reset <= reset_2; 220 | end 221 | else begin 222 | next_reset <= reset_1; 223 | end 224 | end 225 | 226 | reset_2 : begin 227 | reset = 1'b0; 228 | if(reset_button == 1'b0) begin 229 | next_reset <= reset_1; 230 | end 231 | else begin 232 | next_reset <= reset_2; 233 | end 234 | end 235 | endcase 236 | end 237 | 238 | always @(posedge clk, posedge reset) begin 239 | if (reset) begin 240 | state <= initialize; 241 | state_valid <= state_1; 242 | state_lights <= LIGHT1; 243 | end 244 | else begin 245 | state <= next; 246 | state_valid <= next_valid; 247 | state_lights <= next_lights; 248 | 249 | end 250 | end 251 | 252 | always @(posedge clk, posedge reset) begin 253 | if (reset) begin 254 | timer_f <= 0; 255 | end 256 | else begin 257 | if (state != next) begin 258 | timer_f <= 0; 259 | end 260 | else begin 261 | timer_f <= timer_f + 1; 262 | end 263 | end 264 | end 265 | 266 | always @(posedge clk) begin 267 | case (state_valid) 268 | state_1 : begin 269 | if((valid == 1'b1) && (enable == 1'b0)) begin 270 | wr_en <= 1'b1; 271 | next_valid <= state_2; 272 | end 273 | else begin 274 | next_valid = state_1; 275 | end 276 | end 277 | 278 | state_2 : begin 279 | wr_en = 1'b0; 280 | next_valid = state_1; 281 | end 282 | endcase 283 | end 284 | 285 | always @(posedge clk) begin 286 | 287 | case (state) 288 | initialize : begin 289 | if(timer_f >= 5) begin 290 | FIFO_reset <= 0; 291 | next <= waiting; 292 | end 293 | else begin 294 | FIFO_reset <= 1; 295 | next <= initialize; 296 | end 297 | end 298 | 299 | waiting : begin 300 | if(empty) begin 301 | next <= waiting; 302 | end 303 | else begin 304 | next <= fetch_1; 305 | end 306 | end 307 | 308 | fetch_1 : begin 309 | rd_en = 1'b1; 310 | next <= fetch_2; 311 | end 312 | 313 | fetch_2 : begin 314 | buffer <= dout_40bit; 315 | rd_en = 1'b0; 316 | next = send_1; 317 | end 318 | 319 | send_1 : begin 320 | bus_8bit <= buffer[39:32]; 321 | UART_trigger = 1'b1; 322 | next = send_1_w; 323 | end 324 | 325 | send_1_w : begin 326 | UART_trigger <= 1'b0; 327 | if(UART_done) begin 328 | next <= send_2; 329 | end 330 | else begin 331 | next <= send_1_w; 332 | end 333 | end 334 | 335 | send_2 : begin 336 | bus_8bit = buffer[31:24]; 337 | UART_trigger = 1'b1; 338 | next <= send_2_w; 339 | end 340 | 341 | send_2_w : begin 342 | UART_trigger <= 1'b0; 343 | if(UART_done) begin 344 | next <= send_3; 345 | end 346 | else begin 347 | next <= send_2_w; 348 | end 349 | end 350 | 351 | send_3 : begin 352 | bus_8bit = buffer[23:16]; 353 | UART_trigger = 1'b1; 354 | next <= send_3_w; 355 | end 356 | 357 | send_3_w : begin 358 | UART_trigger <= 1'b0; 359 | if(UART_done) begin 360 | next <= send_4; 361 | end 362 | else begin 363 | next <= send_3_w; 364 | end 365 | end 366 | 367 | send_4 : begin 368 | bus_8bit = buffer[15:8]; 369 | UART_trigger = 1'b1; 370 | next <= send_4_w; 371 | end 372 | 373 | send_4_w : begin 374 | UART_trigger <= 1'b0; 375 | if(UART_done) begin 376 | next <= send_5; 377 | end 378 | else begin 379 | next <= send_4_w; 380 | end 381 | end 382 | 383 | send_5 : begin 384 | bus_8bit = buffer[7:0]; 385 | UART_trigger = 1'b1; 386 | next <= send_5_w; 387 | end 388 | 389 | send_5_w : begin 390 | UART_trigger <= 1'b0; 391 | if(UART_done) begin 392 | next <= waiting; 393 | end 394 | else begin 395 | next <= send_5_w; 396 | end 397 | end 398 | endcase 399 | end 400 | 401 | endmodule 402 | -------------------------------------------------------------------------------- /rtl/src/encoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/10/2022 11:55:32 AM 7 | // Design Name: 8 | // Module Name: encoder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module encoder( 24 | input clk, 25 | input wire [1023:0] op, 26 | output reg [9:0] en_op 27 | ); 28 | 29 | always @(posedge clk) 30 | begin 31 | if (op[1023]==1) en_op = 10'b1111111111; 32 | else if (op[1021]==1) en_op = 10'b1111111101; 33 | else if (op[1019]==1) en_op = 10'b1111111011; 34 | else if (op[1017]==1) en_op = 10'b1111111001; 35 | else if (op[1015]==1) en_op = 10'b1111110111; 36 | else if (op[1013]==1) en_op = 10'b1111110101; 37 | else if (op[1011]==1) en_op = 10'b1111110011; 38 | else if (op[1009]==1) en_op = 10'b1111110001; 39 | else if (op[1007]==1) en_op = 10'b1111101111; 40 | else if (op[1005]==1) en_op = 10'b1111101101; 41 | else if (op[1003]==1) en_op = 10'b1111101011; 42 | else if (op[1001]==1) en_op = 10'b1111101001; 43 | else if (op[999]==1) en_op = 10'b1111100111; 44 | else if (op[997]==1) en_op = 10'b1111100101; 45 | else if (op[995]==1) en_op = 10'b1111100011; 46 | else if (op[993]==1) en_op = 10'b1111100001; 47 | else if (op[991]==1) en_op = 10'b1111011111; 48 | else if (op[989]==1) en_op = 10'b1111011101; 49 | else if (op[987]==1) en_op = 10'b1111011011; 50 | else if (op[985]==1) en_op = 10'b1111011001; 51 | else if (op[983]==1) en_op = 10'b1111010111; 52 | else if (op[981]==1) en_op = 10'b1111010101; 53 | else if (op[979]==1) en_op = 10'b1111010011; 54 | else if (op[977]==1) en_op = 10'b1111010001; 55 | else if (op[975]==1) en_op = 10'b1111001111; 56 | else if (op[973]==1) en_op = 10'b1111001101; 57 | else if (op[971]==1) en_op = 10'b1111001011; 58 | else if (op[969]==1) en_op = 10'b1111001001; 59 | else if (op[967]==1) en_op = 10'b1111000111; 60 | else if (op[965]==1) en_op = 10'b1111000101; 61 | else if (op[963]==1) en_op = 10'b1111000011; 62 | else if (op[961]==1) en_op = 10'b1111000001; 63 | else if (op[959]==1) en_op = 10'b1110111111; 64 | else if (op[957]==1) en_op = 10'b1110111101; 65 | else if (op[955]==1) en_op = 10'b1110111011; 66 | else if (op[953]==1) en_op = 10'b1110111001; 67 | else if (op[951]==1) en_op = 10'b1110110111; 68 | else if (op[949]==1) en_op = 10'b1110110101; 69 | else if (op[947]==1) en_op = 10'b1110110011; 70 | else if (op[945]==1) en_op = 10'b1110110001; 71 | else if (op[943]==1) en_op = 10'b1110101111; 72 | else if (op[941]==1) en_op = 10'b1110101101; 73 | else if (op[939]==1) en_op = 10'b1110101011; 74 | else if (op[937]==1) en_op = 10'b1110101001; 75 | else if (op[935]==1) en_op = 10'b1110100111; 76 | else if (op[933]==1) en_op = 10'b1110100101; 77 | else if (op[931]==1) en_op = 10'b1110100011; 78 | else if (op[929]==1) en_op = 10'b1110100001; 79 | else if (op[927]==1) en_op = 10'b1110011111; 80 | else if (op[925]==1) en_op = 10'b1110011101; 81 | else if (op[923]==1) en_op = 10'b1110011011; 82 | else if (op[921]==1) en_op = 10'b1110011001; 83 | else if (op[919]==1) en_op = 10'b1110010111; 84 | else if (op[917]==1) en_op = 10'b1110010101; 85 | else if (op[915]==1) en_op = 10'b1110010011; 86 | else if (op[913]==1) en_op = 10'b1110010001; 87 | else if (op[911]==1) en_op = 10'b1110001111; 88 | else if (op[909]==1) en_op = 10'b1110001101; 89 | else if (op[907]==1) en_op = 10'b1110001011; 90 | else if (op[905]==1) en_op = 10'b1110001001; 91 | else if (op[903]==1) en_op = 10'b1110000111; 92 | else if (op[901]==1) en_op = 10'b1110000101; 93 | else if (op[899]==1) en_op = 10'b1110000011; 94 | else if (op[897]==1) en_op = 10'b1110000001; 95 | else if (op[895]==1) en_op = 10'b1101111111; 96 | else if (op[893]==1) en_op = 10'b1101111101; 97 | else if (op[891]==1) en_op = 10'b1101111011; 98 | else if (op[889]==1) en_op = 10'b1101111001; 99 | else if (op[887]==1) en_op = 10'b1101110111; 100 | else if (op[885]==1) en_op = 10'b1101110101; 101 | else if (op[883]==1) en_op = 10'b1101110011; 102 | else if (op[881]==1) en_op = 10'b1101110001; 103 | else if (op[879]==1) en_op = 10'b1101101111; 104 | else if (op[877]==1) en_op = 10'b1101101101; 105 | else if (op[875]==1) en_op = 10'b1101101011; 106 | else if (op[873]==1) en_op = 10'b1101101001; 107 | else if (op[871]==1) en_op = 10'b1101100111; 108 | else if (op[869]==1) en_op = 10'b1101100101; 109 | else if (op[867]==1) en_op = 10'b1101100011; 110 | else if (op[865]==1) en_op = 10'b1101100001; 111 | else if (op[863]==1) en_op = 10'b1101011111; 112 | else if (op[861]==1) en_op = 10'b1101011101; 113 | else if (op[859]==1) en_op = 10'b1101011011; 114 | else if (op[857]==1) en_op = 10'b1101011001; 115 | else if (op[855]==1) en_op = 10'b1101010111; 116 | else if (op[853]==1) en_op = 10'b1101010101; 117 | else if (op[851]==1) en_op = 10'b1101010011; 118 | else if (op[849]==1) en_op = 10'b1101010001; 119 | else if (op[847]==1) en_op = 10'b1101001111; 120 | else if (op[845]==1) en_op = 10'b1101001101; 121 | else if (op[843]==1) en_op = 10'b1101001011; 122 | else if (op[841]==1) en_op = 10'b1101001001; 123 | else if (op[839]==1) en_op = 10'b1101000111; 124 | else if (op[837]==1) en_op = 10'b1101000101; 125 | else if (op[835]==1) en_op = 10'b1101000011; 126 | else if (op[833]==1) en_op = 10'b1101000001; 127 | else if (op[831]==1) en_op = 10'b1100111111; 128 | else if (op[829]==1) en_op = 10'b1100111101; 129 | else if (op[827]==1) en_op = 10'b1100111011; 130 | else if (op[825]==1) en_op = 10'b1100111001; 131 | else if (op[823]==1) en_op = 10'b1100110111; 132 | else if (op[821]==1) en_op = 10'b1100110101; 133 | else if (op[819]==1) en_op = 10'b1100110011; 134 | else if (op[817]==1) en_op = 10'b1100110001; 135 | else if (op[815]==1) en_op = 10'b1100101111; 136 | else if (op[813]==1) en_op = 10'b1100101101; 137 | else if (op[811]==1) en_op = 10'b1100101011; 138 | else if (op[809]==1) en_op = 10'b1100101001; 139 | else if (op[807]==1) en_op = 10'b1100100111; 140 | else if (op[805]==1) en_op = 10'b1100100101; 141 | else if (op[803]==1) en_op = 10'b1100100011; 142 | else if (op[801]==1) en_op = 10'b1100100001; 143 | else if (op[799]==1) en_op = 10'b1100011111; 144 | else if (op[797]==1) en_op = 10'b1100011101; 145 | else if (op[795]==1) en_op = 10'b1100011011; 146 | else if (op[793]==1) en_op = 10'b1100011001; 147 | else if (op[791]==1) en_op = 10'b1100010111; 148 | else if (op[789]==1) en_op = 10'b1100010101; 149 | else if (op[787]==1) en_op = 10'b1100010011; 150 | else if (op[785]==1) en_op = 10'b1100010001; 151 | else if (op[783]==1) en_op = 10'b1100001111; 152 | else if (op[781]==1) en_op = 10'b1100001101; 153 | else if (op[779]==1) en_op = 10'b1100001011; 154 | else if (op[777]==1) en_op = 10'b1100001001; 155 | else if (op[775]==1) en_op = 10'b1100000111; 156 | else if (op[773]==1) en_op = 10'b1100000101; 157 | else if (op[771]==1) en_op = 10'b1100000011; 158 | else if (op[769]==1) en_op = 10'b1100000001; 159 | else if (op[767]==1) en_op = 10'b1011111111; 160 | else if (op[765]==1) en_op = 10'b1011111101; 161 | else if (op[763]==1) en_op = 10'b1011111011; 162 | else if (op[761]==1) en_op = 10'b1011111001; 163 | else if (op[759]==1) en_op = 10'b1011110111; 164 | else if (op[757]==1) en_op = 10'b1011110101; 165 | else if (op[755]==1) en_op = 10'b1011110011; 166 | else if (op[753]==1) en_op = 10'b1011110001; 167 | else if (op[751]==1) en_op = 10'b1011101111; 168 | else if (op[749]==1) en_op = 10'b1011101101; 169 | else if (op[747]==1) en_op = 10'b1011101011; 170 | else if (op[745]==1) en_op = 10'b1011101001; 171 | else if (op[743]==1) en_op = 10'b1011100111; 172 | else if (op[741]==1) en_op = 10'b1011100101; 173 | else if (op[739]==1) en_op = 10'b1011100011; 174 | else if (op[737]==1) en_op = 10'b1011100001; 175 | else if (op[735]==1) en_op = 10'b1011011111; 176 | else if (op[733]==1) en_op = 10'b1011011101; 177 | else if (op[731]==1) en_op = 10'b1011011011; 178 | else if (op[729]==1) en_op = 10'b1011011001; 179 | else if (op[727]==1) en_op = 10'b1011010111; 180 | else if (op[725]==1) en_op = 10'b1011010101; 181 | else if (op[723]==1) en_op = 10'b1011010011; 182 | else if (op[721]==1) en_op = 10'b1011010001; 183 | else if (op[719]==1) en_op = 10'b1011001111; 184 | else if (op[717]==1) en_op = 10'b1011001101; 185 | else if (op[715]==1) en_op = 10'b1011001011; 186 | else if (op[713]==1) en_op = 10'b1011001001; 187 | else if (op[711]==1) en_op = 10'b1011000111; 188 | else if (op[709]==1) en_op = 10'b1011000101; 189 | else if (op[707]==1) en_op = 10'b1011000011; 190 | else if (op[705]==1) en_op = 10'b1011000001; 191 | else if (op[703]==1) en_op = 10'b1010111111; 192 | else if (op[701]==1) en_op = 10'b1010111101; 193 | else if (op[699]==1) en_op = 10'b1010111011; 194 | else if (op[697]==1) en_op = 10'b1010111001; 195 | else if (op[695]==1) en_op = 10'b1010110111; 196 | else if (op[693]==1) en_op = 10'b1010110101; 197 | else if (op[691]==1) en_op = 10'b1010110011; 198 | else if (op[689]==1) en_op = 10'b1010110001; 199 | else if (op[687]==1) en_op = 10'b1010101111; 200 | else if (op[685]==1) en_op = 10'b1010101101; 201 | else if (op[683]==1) en_op = 10'b1010101011; 202 | else if (op[681]==1) en_op = 10'b1010101001; 203 | else if (op[679]==1) en_op = 10'b1010100111; 204 | else if (op[677]==1) en_op = 10'b1010100101; 205 | else if (op[675]==1) en_op = 10'b1010100011; 206 | else if (op[673]==1) en_op = 10'b1010100001; 207 | else if (op[671]==1) en_op = 10'b1010011111; 208 | else if (op[669]==1) en_op = 10'b1010011101; 209 | else if (op[667]==1) en_op = 10'b1010011011; 210 | else if (op[665]==1) en_op = 10'b1010011001; 211 | else if (op[663]==1) en_op = 10'b1010010111; 212 | else if (op[661]==1) en_op = 10'b1010010101; 213 | else if (op[659]==1) en_op = 10'b1010010011; 214 | else if (op[657]==1) en_op = 10'b1010010001; 215 | else if (op[655]==1) en_op = 10'b1010001111; 216 | else if (op[653]==1) en_op = 10'b1010001101; 217 | else if (op[651]==1) en_op = 10'b1010001011; 218 | else if (op[649]==1) en_op = 10'b1010001001; 219 | else if (op[647]==1) en_op = 10'b1010000111; 220 | else if (op[645]==1) en_op = 10'b1010000101; 221 | else if (op[643]==1) en_op = 10'b1010000011; 222 | else if (op[641]==1) en_op = 10'b1010000001; 223 | else if (op[639]==1) en_op = 10'b1001111111; 224 | else if (op[637]==1) en_op = 10'b1001111101; 225 | else if (op[635]==1) en_op = 10'b1001111011; 226 | else if (op[633]==1) en_op = 10'b1001111001; 227 | else if (op[631]==1) en_op = 10'b1001110111; 228 | else if (op[629]==1) en_op = 10'b1001110101; 229 | else if (op[627]==1) en_op = 10'b1001110011; 230 | else if (op[625]==1) en_op = 10'b1001110001; 231 | else if (op[623]==1) en_op = 10'b1001101111; 232 | else if (op[621]==1) en_op = 10'b1001101101; 233 | else if (op[619]==1) en_op = 10'b1001101011; 234 | else if (op[617]==1) en_op = 10'b1001101001; 235 | else if (op[615]==1) en_op = 10'b1001100111; 236 | else if (op[613]==1) en_op = 10'b1001100101; 237 | else if (op[611]==1) en_op = 10'b1001100011; 238 | else if (op[609]==1) en_op = 10'b1001100001; 239 | else if (op[607]==1) en_op = 10'b1001011111; 240 | else if (op[605]==1) en_op = 10'b1001011101; 241 | else if (op[603]==1) en_op = 10'b1001011011; 242 | else if (op[601]==1) en_op = 10'b1001011001; 243 | else if (op[599]==1) en_op = 10'b1001010111; 244 | else if (op[597]==1) en_op = 10'b1001010101; 245 | else if (op[595]==1) en_op = 10'b1001010011; 246 | else if (op[593]==1) en_op = 10'b1001010001; 247 | else if (op[591]==1) en_op = 10'b1001001111; 248 | else if (op[589]==1) en_op = 10'b1001001101; 249 | else if (op[587]==1) en_op = 10'b1001001011; 250 | else if (op[585]==1) en_op = 10'b1001001001; 251 | else if (op[583]==1) en_op = 10'b1001000111; 252 | else if (op[581]==1) en_op = 10'b1001000101; 253 | else if (op[579]==1) en_op = 10'b1001000011; 254 | else if (op[577]==1) en_op = 10'b1001000001; 255 | else if (op[575]==1) en_op = 10'b1000111111; 256 | else if (op[573]==1) en_op = 10'b1000111101; 257 | else if (op[571]==1) en_op = 10'b1000111011; 258 | else if (op[569]==1) en_op = 10'b1000111001; 259 | else if (op[567]==1) en_op = 10'b1000110111; 260 | else if (op[565]==1) en_op = 10'b1000110101; 261 | else if (op[563]==1) en_op = 10'b1000110011; 262 | else if (op[561]==1) en_op = 10'b1000110001; 263 | else if (op[559]==1) en_op = 10'b1000101111; 264 | else if (op[557]==1) en_op = 10'b1000101101; 265 | else if (op[555]==1) en_op = 10'b1000101011; 266 | else if (op[553]==1) en_op = 10'b1000101001; 267 | else if (op[551]==1) en_op = 10'b1000100111; 268 | else if (op[549]==1) en_op = 10'b1000100101; 269 | else if (op[547]==1) en_op = 10'b1000100011; 270 | else if (op[545]==1) en_op = 10'b1000100001; 271 | else if (op[543]==1) en_op = 10'b1000011111; 272 | else if (op[541]==1) en_op = 10'b1000011101; 273 | else if (op[539]==1) en_op = 10'b1000011011; 274 | else if (op[537]==1) en_op = 10'b1000011001; 275 | else if (op[535]==1) en_op = 10'b1000010111; 276 | else if (op[533]==1) en_op = 10'b1000010101; 277 | else if (op[531]==1) en_op = 10'b1000010011; 278 | else if (op[529]==1) en_op = 10'b1000010001; 279 | else if (op[527]==1) en_op = 10'b1000001111; 280 | else if (op[525]==1) en_op = 10'b1000001101; 281 | else if (op[523]==1) en_op = 10'b1000001011; 282 | else if (op[521]==1) en_op = 10'b1000001001; 283 | else if (op[519]==1) en_op = 10'b1000000111; 284 | else if (op[517]==1) en_op = 10'b1000000101; 285 | else if (op[515]==1) en_op = 10'b1000000011; 286 | else if (op[513]==1) en_op = 10'b1000000001; 287 | else if (op[511]==1) en_op = 10'b0111111111; 288 | else if (op[509]==1) en_op = 10'b0111111101; 289 | else if (op[507]==1) en_op = 10'b0111111011; 290 | else if (op[505]==1) en_op = 10'b0111111001; 291 | else if (op[503]==1) en_op = 10'b0111110111; 292 | else if (op[501]==1) en_op = 10'b0111110101; 293 | else if (op[499]==1) en_op = 10'b0111110011; 294 | else if (op[497]==1) en_op = 10'b0111110001; 295 | else if (op[495]==1) en_op = 10'b0111101111; 296 | else if (op[493]==1) en_op = 10'b0111101101; 297 | else if (op[491]==1) en_op = 10'b0111101011; 298 | else if (op[489]==1) en_op = 10'b0111101001; 299 | else if (op[487]==1) en_op = 10'b0111100111; 300 | else if (op[485]==1) en_op = 10'b0111100101; 301 | else if (op[483]==1) en_op = 10'b0111100011; 302 | else if (op[481]==1) en_op = 10'b0111100001; 303 | else if (op[479]==1) en_op = 10'b0111011111; 304 | else if (op[477]==1) en_op = 10'b0111011101; 305 | else if (op[475]==1) en_op = 10'b0111011011; 306 | else if (op[473]==1) en_op = 10'b0111011001; 307 | else if (op[471]==1) en_op = 10'b0111010111; 308 | else if (op[469]==1) en_op = 10'b0111010101; 309 | else if (op[467]==1) en_op = 10'b0111010011; 310 | else if (op[465]==1) en_op = 10'b0111010001; 311 | else if (op[463]==1) en_op = 10'b0111001111; 312 | else if (op[461]==1) en_op = 10'b0111001101; 313 | else if (op[459]==1) en_op = 10'b0111001011; 314 | else if (op[457]==1) en_op = 10'b0111001001; 315 | else if (op[455]==1) en_op = 10'b0111000111; 316 | else if (op[453]==1) en_op = 10'b0111000101; 317 | else if (op[451]==1) en_op = 10'b0111000011; 318 | else if (op[449]==1) en_op = 10'b0111000001; 319 | else if (op[447]==1) en_op = 10'b0110111111; 320 | else if (op[445]==1) en_op = 10'b0110111101; 321 | else if (op[443]==1) en_op = 10'b0110111011; 322 | else if (op[441]==1) en_op = 10'b0110111001; 323 | else if (op[439]==1) en_op = 10'b0110110111; 324 | else if (op[437]==1) en_op = 10'b0110110101; 325 | else if (op[435]==1) en_op = 10'b0110110011; 326 | else if (op[433]==1) en_op = 10'b0110110001; 327 | else if (op[431]==1) en_op = 10'b0110101111; 328 | else if (op[429]==1) en_op = 10'b0110101101; 329 | else if (op[427]==1) en_op = 10'b0110101011; 330 | else if (op[425]==1) en_op = 10'b0110101001; 331 | else if (op[423]==1) en_op = 10'b0110100111; 332 | else if (op[421]==1) en_op = 10'b0110100101; 333 | else if (op[419]==1) en_op = 10'b0110100011; 334 | else if (op[417]==1) en_op = 10'b0110100001; 335 | else if (op[415]==1) en_op = 10'b0110011111; 336 | else if (op[413]==1) en_op = 10'b0110011101; 337 | else if (op[411]==1) en_op = 10'b0110011011; 338 | else if (op[409]==1) en_op = 10'b0110011001; 339 | else if (op[407]==1) en_op = 10'b0110010111; 340 | else if (op[405]==1) en_op = 10'b0110010101; 341 | else if (op[403]==1) en_op = 10'b0110010011; 342 | else if (op[401]==1) en_op = 10'b0110010001; 343 | else if (op[399]==1) en_op = 10'b0110001111; 344 | else if (op[397]==1) en_op = 10'b0110001101; 345 | else if (op[395]==1) en_op = 10'b0110001011; 346 | else if (op[393]==1) en_op = 10'b0110001001; 347 | else if (op[391]==1) en_op = 10'b0110000111; 348 | else if (op[389]==1) en_op = 10'b0110000101; 349 | else if (op[387]==1) en_op = 10'b0110000011; 350 | else if (op[385]==1) en_op = 10'b0110000001; 351 | else if (op[383]==1) en_op = 10'b0101111111; 352 | else if (op[381]==1) en_op = 10'b0101111101; 353 | else if (op[379]==1) en_op = 10'b0101111011; 354 | else if (op[377]==1) en_op = 10'b0101111001; 355 | else if (op[375]==1) en_op = 10'b0101110111; 356 | else if (op[373]==1) en_op = 10'b0101110101; 357 | else if (op[371]==1) en_op = 10'b0101110011; 358 | else if (op[369]==1) en_op = 10'b0101110001; 359 | else if (op[367]==1) en_op = 10'b0101101111; 360 | else if (op[365]==1) en_op = 10'b0101101101; 361 | else if (op[363]==1) en_op = 10'b0101101011; 362 | else if (op[361]==1) en_op = 10'b0101101001; 363 | else if (op[359]==1) en_op = 10'b0101100111; 364 | else if (op[357]==1) en_op = 10'b0101100101; 365 | else if (op[355]==1) en_op = 10'b0101100011; 366 | else if (op[353]==1) en_op = 10'b0101100001; 367 | else if (op[351]==1) en_op = 10'b0101011111; 368 | else if (op[349]==1) en_op = 10'b0101011101; 369 | else if (op[347]==1) en_op = 10'b0101011011; 370 | else if (op[345]==1) en_op = 10'b0101011001; 371 | else if (op[343]==1) en_op = 10'b0101010111; 372 | else if (op[341]==1) en_op = 10'b0101010101; 373 | else if (op[339]==1) en_op = 10'b0101010011; 374 | else if (op[337]==1) en_op = 10'b0101010001; 375 | else if (op[335]==1) en_op = 10'b0101001111; 376 | else if (op[333]==1) en_op = 10'b0101001101; 377 | else if (op[331]==1) en_op = 10'b0101001011; 378 | else if (op[329]==1) en_op = 10'b0101001001; 379 | else if (op[327]==1) en_op = 10'b0101000111; 380 | else if (op[325]==1) en_op = 10'b0101000101; 381 | else if (op[323]==1) en_op = 10'b0101000011; 382 | else if (op[321]==1) en_op = 10'b0101000001; 383 | else if (op[319]==1) en_op = 10'b0100111111; 384 | else if (op[317]==1) en_op = 10'b0100111101; 385 | else if (op[315]==1) en_op = 10'b0100111011; 386 | else if (op[313]==1) en_op = 10'b0100111001; 387 | else if (op[311]==1) en_op = 10'b0100110111; 388 | else if (op[309]==1) en_op = 10'b0100110101; 389 | else if (op[307]==1) en_op = 10'b0100110011; 390 | else if (op[305]==1) en_op = 10'b0100110001; 391 | else if (op[303]==1) en_op = 10'b0100101111; 392 | else if (op[301]==1) en_op = 10'b0100101101; 393 | else if (op[299]==1) en_op = 10'b0100101011; 394 | else if (op[297]==1) en_op = 10'b0100101001; 395 | else if (op[295]==1) en_op = 10'b0100100111; 396 | else if (op[293]==1) en_op = 10'b0100100101; 397 | else if (op[291]==1) en_op = 10'b0100100011; 398 | else if (op[289]==1) en_op = 10'b0100100001; 399 | else if (op[287]==1) en_op = 10'b0100011111; 400 | else if (op[285]==1) en_op = 10'b0100011101; 401 | else if (op[283]==1) en_op = 10'b0100011011; 402 | else if (op[281]==1) en_op = 10'b0100011001; 403 | else if (op[279]==1) en_op = 10'b0100010111; 404 | else if (op[277]==1) en_op = 10'b0100010101; 405 | else if (op[275]==1) en_op = 10'b0100010011; 406 | else if (op[273]==1) en_op = 10'b0100010001; 407 | else if (op[271]==1) en_op = 10'b0100001111; 408 | else if (op[269]==1) en_op = 10'b0100001101; 409 | else if (op[267]==1) en_op = 10'b0100001011; 410 | else if (op[265]==1) en_op = 10'b0100001001; 411 | else if (op[263]==1) en_op = 10'b0100000111; 412 | else if (op[261]==1) en_op = 10'b0100000101; 413 | else if (op[259]==1) en_op = 10'b0100000011; 414 | else if (op[257]==1) en_op = 10'b0100000001; 415 | else if (op[255]==1) en_op = 10'b0011111111; 416 | else if (op[253]==1) en_op = 10'b0011111101; 417 | else if (op[251]==1) en_op = 10'b0011111011; 418 | else if (op[249]==1) en_op = 10'b0011111001; 419 | else if (op[247]==1) en_op = 10'b0011110111; 420 | else if (op[245]==1) en_op = 10'b0011110101; 421 | else if (op[243]==1) en_op = 10'b0011110011; 422 | else if (op[241]==1) en_op = 10'b0011110001; 423 | else if (op[239]==1) en_op = 10'b0011101111; 424 | else if (op[237]==1) en_op = 10'b0011101101; 425 | else if (op[235]==1) en_op = 10'b0011101011; 426 | else if (op[233]==1) en_op = 10'b0011101001; 427 | else if (op[231]==1) en_op = 10'b0011100111; 428 | else if (op[229]==1) en_op = 10'b0011100101; 429 | else if (op[227]==1) en_op = 10'b0011100011; 430 | else if (op[225]==1) en_op = 10'b0011100001; 431 | else if (op[223]==1) en_op = 10'b0011011111; 432 | else if (op[221]==1) en_op = 10'b0011011101; 433 | else if (op[219]==1) en_op = 10'b0011011011; 434 | else if (op[217]==1) en_op = 10'b0011011001; 435 | else if (op[215]==1) en_op = 10'b0011010111; 436 | else if (op[213]==1) en_op = 10'b0011010101; 437 | else if (op[211]==1) en_op = 10'b0011010011; 438 | else if (op[209]==1) en_op = 10'b0011010001; 439 | else if (op[207]==1) en_op = 10'b0011001111; 440 | else if (op[205]==1) en_op = 10'b0011001101; 441 | else if (op[203]==1) en_op = 10'b0011001011; 442 | else if (op[201]==1) en_op = 10'b0011001001; 443 | else if (op[199]==1) en_op = 10'b0011000111; 444 | else if (op[197]==1) en_op = 10'b0011000101; 445 | else if (op[195]==1) en_op = 10'b0011000011; 446 | else if (op[193]==1) en_op = 10'b0011000001; 447 | else if (op[191]==1) en_op = 10'b0010111111; 448 | else if (op[189]==1) en_op = 10'b0010111101; 449 | else if (op[187]==1) en_op = 10'b0010111011; 450 | else if (op[185]==1) en_op = 10'b0010111001; 451 | else if (op[183]==1) en_op = 10'b0010110111; 452 | else if (op[181]==1) en_op = 10'b0010110101; 453 | else if (op[179]==1) en_op = 10'b0010110011; 454 | else if (op[177]==1) en_op = 10'b0010110001; 455 | else if (op[175]==1) en_op = 10'b0010101111; 456 | else if (op[173]==1) en_op = 10'b0010101101; 457 | else if (op[171]==1) en_op = 10'b0010101011; 458 | else if (op[169]==1) en_op = 10'b0010101001; 459 | else if (op[167]==1) en_op = 10'b0010100111; 460 | else if (op[165]==1) en_op = 10'b0010100101; 461 | else if (op[163]==1) en_op = 10'b0010100011; 462 | else if (op[161]==1) en_op = 10'b0010100001; 463 | else if (op[159]==1) en_op = 10'b0010011111; 464 | else if (op[157]==1) en_op = 10'b0010011101; 465 | else if (op[155]==1) en_op = 10'b0010011011; 466 | else if (op[153]==1) en_op = 10'b0010011001; 467 | else if (op[151]==1) en_op = 10'b0010010111; 468 | else if (op[149]==1) en_op = 10'b0010010101; 469 | else if (op[147]==1) en_op = 10'b0010010011; 470 | else if (op[145]==1) en_op = 10'b0010010001; 471 | else if (op[143]==1) en_op = 10'b0010001111; 472 | else if (op[141]==1) en_op = 10'b0010001101; 473 | else if (op[139]==1) en_op = 10'b0010001011; 474 | else if (op[137]==1) en_op = 10'b0010001001; 475 | else if (op[135]==1) en_op = 10'b0010000111; 476 | else if (op[133]==1) en_op = 10'b0010000101; 477 | else if (op[131]==1) en_op = 10'b0010000011; 478 | else if (op[129]==1) en_op = 10'b0010000001; 479 | else if (op[127]==1) en_op = 10'b0001111111; 480 | else if (op[125]==1) en_op = 10'b0001111101; 481 | else if (op[123]==1) en_op = 10'b0001111011; 482 | else if (op[121]==1) en_op = 10'b0001111001; 483 | else if (op[119]==1) en_op = 10'b0001110111; 484 | else if (op[117]==1) en_op = 10'b0001110101; 485 | else if (op[115]==1) en_op = 10'b0001110011; 486 | else if (op[113]==1) en_op = 10'b0001110001; 487 | else if (op[111]==1) en_op = 10'b0001101111; 488 | else if (op[109]==1) en_op = 10'b0001101101; 489 | else if (op[107]==1) en_op = 10'b0001101011; 490 | else if (op[105]==1) en_op = 10'b0001101001; 491 | else if (op[103]==1) en_op = 10'b0001100111; 492 | else if (op[101]==1) en_op = 10'b0001100101; 493 | else if (op[99]==1) en_op = 10'b0001100011; 494 | else if (op[97]==1) en_op = 10'b0001100001; 495 | else if (op[95]==1) en_op = 10'b0001011111; 496 | else if (op[93]==1) en_op = 10'b0001011101; 497 | else if (op[91]==1) en_op = 10'b0001011011; 498 | else if (op[89]==1) en_op = 10'b0001011001; 499 | else if (op[87]==1) en_op = 10'b0001010111; 500 | else if (op[85]==1) en_op = 10'b0001010101; 501 | else if (op[83]==1) en_op = 10'b0001010011; 502 | else if (op[81]==1) en_op = 10'b0001010001; 503 | else if (op[79]==1) en_op = 10'b0001001111; 504 | else if (op[77]==1) en_op = 10'b0001001101; 505 | else if (op[75]==1) en_op = 10'b0001001011; 506 | else if (op[73]==1) en_op = 10'b0001001001; 507 | else if (op[71]==1) en_op = 10'b0001000111; 508 | else if (op[69]==1) en_op = 10'b0001000101; 509 | else if (op[67]==1) en_op = 10'b0001000011; 510 | else if (op[65]==1) en_op = 10'b0001000001; 511 | else if (op[63]==1) en_op = 10'b0000111111; 512 | else if (op[61]==1) en_op = 10'b0000111101; 513 | else if (op[59]==1) en_op = 10'b0000111011; 514 | else if (op[57]==1) en_op = 10'b0000111001; 515 | else if (op[55]==1) en_op = 10'b0000110111; 516 | else if (op[53]==1) en_op = 10'b0000110101; 517 | else if (op[51]==1) en_op = 10'b0000110011; 518 | else if (op[49]==1) en_op = 10'b0000110001; 519 | else if (op[47]==1) en_op = 10'b0000101111; 520 | else if (op[45]==1) en_op = 10'b0000101101; 521 | else if (op[43]==1) en_op = 10'b0000101011; 522 | else if (op[41]==1) en_op = 10'b0000101001; 523 | else if (op[39]==1) en_op = 10'b0000100111; 524 | else if (op[37]==1) en_op = 10'b0000100101; 525 | else if (op[35]==1) en_op = 10'b0000100011; 526 | else if (op[33]==1) en_op = 10'b0000100001; 527 | else if (op[31]==1) en_op = 10'b0000011111; 528 | else if (op[29]==1) en_op = 10'b0000011101; 529 | else if (op[27]==1) en_op = 10'b0000011011; 530 | else if (op[25]==1) en_op = 10'b0000011001; 531 | else if (op[23]==1) en_op = 10'b0000010111; 532 | else if (op[21]==1) en_op = 10'b0000010101; 533 | else if (op[19]==1) en_op = 10'b0000010011; 534 | else if (op[17]==1) en_op = 10'b0000010001; 535 | else if (op[15]==1) en_op = 10'b0000001111; 536 | else if (op[13]==1) en_op = 10'b0000001101; 537 | else if (op[11]==1) en_op = 10'b0000001011; 538 | else if (op[9]==1) en_op = 10'b0000001001; 539 | else if (op[7]==1) en_op = 10'b0000000111; 540 | else if (op[5]==1) en_op = 10'b0000000101; 541 | else if (op[3]==1) en_op = 10'b0000000011; 542 | else if (op[1]==1) en_op = 10'b0000000001; 543 | else 544 | en_op = 10'b0000000000; 545 | end 546 | 547 | endmodule 548 | -------------------------------------------------------------------------------- /rebuild.tcl: -------------------------------------------------------------------------------- 1 | #***************************************************************************************** 2 | # Vivado (TM) v2019.1 (64-bit) 3 | # 4 | # rebuild.tcl: Tcl script for re-creating project 'tdcOnFPGA' 5 | # 6 | # Generated by Vivado on Tue Dec 27 15:05:10 IST 2022 7 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 8 | # 9 | # This file contains the Vivado Tcl commands for re-creating the project to the state* 10 | # when this script was generated. In order to re-create the project, please source this 11 | # file in the Vivado Tcl Shell. 12 | # 13 | # * Note that the runs in the created project will be configured the same way as the 14 | # original project, however they will not be launched automatically. To regenerate the 15 | # run results please launch the synthesis/implementation runs as needed. 16 | # 17 | #***************************************************************************************** 18 | # NOTE: In order to use this script for source control purposes, please make sure that the 19 | # following files are added to the source control system:- 20 | # 21 | # 1. This project restoration tcl script (rebuild.tcl) that was generated. 22 | # 23 | # 2. The following source(s) files that were local or imported into the original project. 24 | # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) 25 | # 26 | # 27 | # 28 | # 3. The following remote source files that were added to the original project:- 29 | # 30 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/src/Coarse_Counter_22.v" 31 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/src/TDC.v" 32 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/src/edgeDetector.v" 33 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/src/encoder.v" 34 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/src/fine_counter.v" 35 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/src/UART.sv" 36 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/src/fine_tdc.vhd" 37 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/src/TOP.v" 38 | # "/home/ehep/aravind/test/tdcOnFPGA/ip/clk_ip/clk_wiz_0.xci" 39 | # "/home/ehep/aravind/test/tdcOnFPGA/ip/fifo_ip/fifo_generator_0.xci" 40 | # "/home/ehep/aravind/test/tdcOnFPGA/constraints/const_051022.xdc" 41 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/sim/toptest.v" 42 | # "/home/ehep/aravind/test/tdcOnFPGA/rtl/sim/wf_cfg/topteset_time_synth.wcfg" 43 | # 44 | #***************************************************************************************** 45 | 46 | # Set the reference directory for source file relative paths (by default the value is script directory path) 47 | set origin_dir "." 48 | 49 | # Use origin directory path location variable, if specified in the tcl shell 50 | if { [info exists ::origin_dir_loc] } { 51 | set origin_dir $::origin_dir_loc 52 | } 53 | 54 | # Set the project name 55 | set _xil_proj_name_ "tdcOnFPGA" 56 | 57 | # Use project name variable, if specified in the tcl shell 58 | if { [info exists ::user_project_name] } { 59 | set _xil_proj_name_ $::user_project_name 60 | } 61 | 62 | variable script_file 63 | set script_file "rebuild.tcl" 64 | 65 | # Help information for this script 66 | proc print_help {} { 67 | variable script_file 68 | puts "\nDescription:" 69 | puts "Recreate a Vivado project from this script. The created project will be" 70 | puts "functionally equivalent to the original project for which this script was" 71 | puts "generated. The script contains commands for creating a project, filesets," 72 | puts "runs, adding/importing sources and setting properties on various objects.\n" 73 | puts "Syntax:" 74 | puts "$script_file" 75 | puts "$script_file -tclargs \[--origin_dir \]" 76 | puts "$script_file -tclargs \[--project_name \]" 77 | puts "$script_file -tclargs \[--help\]\n" 78 | puts "Usage:" 79 | puts "Name Description" 80 | puts "-------------------------------------------------------------------------" 81 | puts "\[--origin_dir \] Determine source file paths wrt this path. Default" 82 | puts " origin_dir path value is \".\", otherwise, the value" 83 | puts " that was set with the \"-paths_relative_to\" switch" 84 | puts " when this script was generated.\n" 85 | puts "\[--project_name \] Create project with the specified name. Default" 86 | puts " name is the name of the project from where this" 87 | puts " script was generated.\n" 88 | puts "\[--help\] Print help information for this script" 89 | puts "-------------------------------------------------------------------------\n" 90 | exit 0 91 | } 92 | 93 | if { $::argc > 0 } { 94 | for {set i 0} {$i < $::argc} {incr i} { 95 | set option [string trim [lindex $::argv $i]] 96 | switch -regexp -- $option { 97 | "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } 98 | "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } 99 | "--help" { print_help } 100 | default { 101 | if { [regexp {^-} $option] } { 102 | puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" 103 | return 1 104 | } 105 | } 106 | } 107 | } 108 | } 109 | 110 | # Set the directory path for the original project from where this script was exported 111 | set orig_proj_dir "[file normalize "$origin_dir/tdcOnFPGA"]" 112 | 113 | # Create project 114 | create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7vx485tffg1761-2 115 | 116 | # Set the directory path for the new project 117 | set proj_dir [get_property directory [current_project]] 118 | 119 | # Set project properties 120 | set obj [current_project] 121 | set_property -name "board_part" -value "xilinx.com:vc707:part0:1.4" -objects $obj 122 | set_property -name "default_lib" -value "xil_defaultlib" -objects $obj 123 | set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj 124 | set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj 125 | set_property -name "dsa.board_id" -value "vc707" -objects $obj 126 | set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj 127 | set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj 128 | set_property -name "dsa.emu_dir" -value "emu" -objects $obj 129 | set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj 130 | set_property -name "dsa.flash_offset_address" -value "0" -objects $obj 131 | set_property -name "dsa.flash_size" -value "1024" -objects $obj 132 | set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj 133 | set_property -name "dsa.host_interface" -value "pcie" -objects $obj 134 | set_property -name "dsa.num_compute_units" -value "60" -objects $obj 135 | set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj 136 | set_property -name "dsa.vendor" -value "xilinx" -objects $obj 137 | set_property -name "dsa.version" -value "0.0" -objects $obj 138 | set_property -name "enable_vhdl_2008" -value "1" -objects $obj 139 | set_property -name "ip_cache_permissions" -value "read write" -objects $obj 140 | set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj 141 | set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj 142 | set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj 143 | set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj 144 | set_property -name "simulator_language" -value "Mixed" -objects $obj 145 | set_property -name "webtalk.activehdl_export_sim" -value "4" -objects $obj 146 | set_property -name "webtalk.ies_export_sim" -value "4" -objects $obj 147 | set_property -name "webtalk.modelsim_export_sim" -value "4" -objects $obj 148 | set_property -name "webtalk.questa_export_sim" -value "4" -objects $obj 149 | set_property -name "webtalk.riviera_export_sim" -value "4" -objects $obj 150 | set_property -name "webtalk.vcs_export_sim" -value "4" -objects $obj 151 | set_property -name "webtalk.xsim_export_sim" -value "4" -objects $obj 152 | set_property -name "webtalk.xsim_launch_sim" -value "5" -objects $obj 153 | set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj 154 | 155 | # Create 'sources_1' fileset (if not found) 156 | if {[string equal [get_filesets -quiet sources_1] ""]} { 157 | create_fileset -srcset sources_1 158 | } 159 | 160 | # Set 'sources_1' fileset object 161 | set obj [get_filesets sources_1] 162 | set files [list \ 163 | [file normalize "${origin_dir}/rtl/src/Coarse_Counter_22.v"] \ 164 | [file normalize "${origin_dir}/rtl/src/TDC.v"] \ 165 | [file normalize "${origin_dir}/rtl/src/edgeDetector.v"] \ 166 | [file normalize "${origin_dir}/rtl/src/encoder.v"] \ 167 | [file normalize "${origin_dir}/rtl/src/fine_counter.v"] \ 168 | [file normalize "${origin_dir}/rtl/src/UART.sv"] \ 169 | [file normalize "${origin_dir}/rtl/src/fine_tdc.vhd"] \ 170 | [file normalize "${origin_dir}/rtl/src/TOP.v"] \ 171 | ] 172 | add_files -norecurse -fileset $obj $files 173 | 174 | # Set 'sources_1' fileset file properties for remote files 175 | set file "$origin_dir/rtl/src/UART.sv" 176 | set file [file normalize $file] 177 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 178 | set_property -name "file_type" -value "SystemVerilog" -objects $file_obj 179 | 180 | set file "$origin_dir/rtl/src/fine_tdc.vhd" 181 | set file [file normalize $file] 182 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 183 | set_property -name "file_type" -value "VHDL" -objects $file_obj 184 | 185 | 186 | # Set 'sources_1' fileset file properties for local files 187 | # None 188 | 189 | # Set 'sources_1' fileset properties 190 | set obj [get_filesets sources_1] 191 | set_property -name "top" -value "TOP" -objects $obj 192 | 193 | # Set 'sources_1' fileset object 194 | set obj [get_filesets sources_1] 195 | set files [list \ 196 | [file normalize "${origin_dir}/ip/clk_ip/clk_wiz_0.xci"] \ 197 | ] 198 | add_files -norecurse -fileset $obj $files 199 | 200 | # Set 'sources_1' fileset file properties for remote files 201 | set file "$origin_dir/ip/clk_ip/clk_wiz_0.xci" 202 | set file [file normalize $file] 203 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 204 | set_property -name "generate_files_for_reference" -value "0" -objects $file_obj 205 | set_property -name "registered_with_manager" -value "1" -objects $file_obj 206 | if { ![get_property "is_locked" $file_obj] } { 207 | set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj 208 | } 209 | 210 | 211 | # Set 'sources_1' fileset file properties for local files 212 | # None 213 | 214 | # Set 'sources_1' fileset object 215 | set obj [get_filesets sources_1] 216 | set files [list \ 217 | [file normalize "${origin_dir}/ip/fifo_ip/fifo_generator_0.xci"] \ 218 | ] 219 | add_files -norecurse -fileset $obj $files 220 | 221 | # Set 'sources_1' fileset file properties for remote files 222 | set file "$origin_dir/ip/fifo_ip/fifo_generator_0.xci" 223 | set file [file normalize $file] 224 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 225 | set_property -name "generate_files_for_reference" -value "0" -objects $file_obj 226 | set_property -name "registered_with_manager" -value "1" -objects $file_obj 227 | if { ![get_property "is_locked" $file_obj] } { 228 | set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj 229 | } 230 | 231 | 232 | # Set 'sources_1' fileset file properties for local files 233 | # None 234 | 235 | # Create 'constrs_1' fileset (if not found) 236 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 237 | create_fileset -constrset constrs_1 238 | } 239 | 240 | # Set 'constrs_1' fileset object 241 | set obj [get_filesets constrs_1] 242 | 243 | # Add/Import constrs file and set constrs file properties 244 | set file "[file normalize "$origin_dir/constraints/const_051022.xdc"]" 245 | set file_added [add_files -norecurse -fileset $obj [list $file]] 246 | set file "$origin_dir/constraints/const_051022.xdc" 247 | set file [file normalize $file] 248 | set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] 249 | set_property -name "file_type" -value "XDC" -objects $file_obj 250 | 251 | # Set 'constrs_1' fileset properties 252 | set obj [get_filesets constrs_1] 253 | 254 | # Create 'sim_1' fileset (if not found) 255 | if {[string equal [get_filesets -quiet sim_1] ""]} { 256 | create_fileset -simset sim_1 257 | } 258 | 259 | # Set 'sim_1' fileset object 260 | set obj [get_filesets sim_1] 261 | set files [list \ 262 | [file normalize "${origin_dir}/rtl/sim/toptest.v"] \ 263 | [file normalize "${origin_dir}/rtl/sim/wf_cfg/topteset_time_synth.wcfg"] \ 264 | ] 265 | add_files -norecurse -fileset $obj $files 266 | 267 | # Set 'sim_1' fileset file properties for remote files 268 | # None 269 | 270 | # Set 'sim_1' fileset file properties for local files 271 | # None 272 | 273 | # Set 'sim_1' fileset properties 274 | set obj [get_filesets sim_1] 275 | set_property -name "sim_mode" -value "post-implementation" -objects $obj 276 | set_property -name "top" -value "topteset" -objects $obj 277 | set_property -name "top_lib" -value "xil_defaultlib" -objects $obj 278 | set_property -name "xsim.simulate.runtime" -value "1ms" -objects $obj 279 | 280 | # Set 'utils_1' fileset object 281 | set obj [get_filesets utils_1] 282 | # Empty (no sources present) 283 | 284 | # Set 'utils_1' fileset properties 285 | set obj [get_filesets utils_1] 286 | 287 | # Create 'synth_1' run (if not found) 288 | if {[string equal [get_runs -quiet synth_1] ""]} { 289 | create_run -name synth_1 -part xc7vx485tffg1761-2 -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 290 | } else { 291 | set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] 292 | set_property flow "Vivado Synthesis 2019" [get_runs synth_1] 293 | } 294 | set obj [get_runs synth_1] 295 | set_property set_report_strategy_name 1 $obj 296 | set_property report_strategy {Vivado Synthesis Default Reports} $obj 297 | set_property set_report_strategy_name 0 $obj 298 | # Create 'synth_1_synth_report_utilization_0' report (if not found) 299 | if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { 300 | create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 301 | } 302 | set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] 303 | if { $obj != "" } { 304 | 305 | } 306 | set obj [get_runs synth_1] 307 | set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj 308 | 309 | # set the current synth run 310 | current_run -synthesis [get_runs synth_1] 311 | 312 | # Create 'impl_1' run (if not found) 313 | if {[string equal [get_runs -quiet impl_1] ""]} { 314 | create_run -name impl_1 -part xc7vx485tffg1761-2 -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 315 | } else { 316 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 317 | set_property flow "Vivado Implementation 2019" [get_runs impl_1] 318 | } 319 | set obj [get_runs impl_1] 320 | set_property set_report_strategy_name 1 $obj 321 | set_property report_strategy {Vivado Implementation Default Reports} $obj 322 | set_property set_report_strategy_name 0 $obj 323 | # Create 'impl_1_init_report_timing_summary_0' report (if not found) 324 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { 325 | create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 326 | } 327 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] 328 | if { $obj != "" } { 329 | set_property -name "is_enabled" -value "0" -objects $obj 330 | set_property -name "options.max_paths" -value "10" -objects $obj 331 | 332 | } 333 | # Create 'impl_1_opt_report_drc_0' report (if not found) 334 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { 335 | create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 336 | } 337 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] 338 | if { $obj != "" } { 339 | 340 | } 341 | # Create 'impl_1_opt_report_timing_summary_0' report (if not found) 342 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { 343 | create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 344 | } 345 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] 346 | if { $obj != "" } { 347 | set_property -name "is_enabled" -value "0" -objects $obj 348 | set_property -name "options.max_paths" -value "10" -objects $obj 349 | 350 | } 351 | # Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) 352 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { 353 | create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 354 | } 355 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] 356 | if { $obj != "" } { 357 | set_property -name "is_enabled" -value "0" -objects $obj 358 | set_property -name "options.max_paths" -value "10" -objects $obj 359 | 360 | } 361 | # Create 'impl_1_place_report_io_0' report (if not found) 362 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { 363 | create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 364 | } 365 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] 366 | if { $obj != "" } { 367 | 368 | } 369 | # Create 'impl_1_place_report_utilization_0' report (if not found) 370 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { 371 | create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 372 | } 373 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] 374 | if { $obj != "" } { 375 | 376 | } 377 | # Create 'impl_1_place_report_control_sets_0' report (if not found) 378 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { 379 | create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 380 | } 381 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] 382 | if { $obj != "" } { 383 | set_property -name "options.verbose" -value "1" -objects $obj 384 | 385 | } 386 | # Create 'impl_1_place_report_incremental_reuse_0' report (if not found) 387 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { 388 | create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 389 | } 390 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] 391 | if { $obj != "" } { 392 | set_property -name "is_enabled" -value "0" -objects $obj 393 | 394 | } 395 | # Create 'impl_1_place_report_incremental_reuse_1' report (if not found) 396 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { 397 | create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 398 | } 399 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] 400 | if { $obj != "" } { 401 | set_property -name "is_enabled" -value "0" -objects $obj 402 | 403 | } 404 | # Create 'impl_1_place_report_timing_summary_0' report (if not found) 405 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { 406 | create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 407 | } 408 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] 409 | if { $obj != "" } { 410 | set_property -name "is_enabled" -value "0" -objects $obj 411 | set_property -name "options.max_paths" -value "10" -objects $obj 412 | 413 | } 414 | # Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) 415 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { 416 | create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 417 | } 418 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] 419 | if { $obj != "" } { 420 | set_property -name "is_enabled" -value "0" -objects $obj 421 | set_property -name "options.max_paths" -value "10" -objects $obj 422 | 423 | } 424 | # Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) 425 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { 426 | create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 427 | } 428 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] 429 | if { $obj != "" } { 430 | set_property -name "is_enabled" -value "0" -objects $obj 431 | set_property -name "options.max_paths" -value "10" -objects $obj 432 | 433 | } 434 | # Create 'impl_1_route_report_drc_0' report (if not found) 435 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { 436 | create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 437 | } 438 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] 439 | if { $obj != "" } { 440 | 441 | } 442 | # Create 'impl_1_route_report_methodology_0' report (if not found) 443 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { 444 | create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 445 | } 446 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] 447 | if { $obj != "" } { 448 | 449 | } 450 | # Create 'impl_1_route_report_power_0' report (if not found) 451 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { 452 | create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 453 | } 454 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] 455 | if { $obj != "" } { 456 | 457 | } 458 | # Create 'impl_1_route_report_route_status_0' report (if not found) 459 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { 460 | create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 461 | } 462 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] 463 | if { $obj != "" } { 464 | 465 | } 466 | # Create 'impl_1_route_report_timing_summary_0' report (if not found) 467 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { 468 | create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 469 | } 470 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] 471 | if { $obj != "" } { 472 | set_property -name "options.max_paths" -value "10" -objects $obj 473 | 474 | } 475 | # Create 'impl_1_route_report_incremental_reuse_0' report (if not found) 476 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { 477 | create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 478 | } 479 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] 480 | if { $obj != "" } { 481 | 482 | } 483 | # Create 'impl_1_route_report_clock_utilization_0' report (if not found) 484 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { 485 | create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 486 | } 487 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] 488 | if { $obj != "" } { 489 | 490 | } 491 | # Create 'impl_1_route_report_bus_skew_0' report (if not found) 492 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { 493 | create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 494 | } 495 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] 496 | if { $obj != "" } { 497 | set_property -name "options.warn_on_violation" -value "1" -objects $obj 498 | 499 | } 500 | # Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) 501 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { 502 | create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 503 | } 504 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] 505 | if { $obj != "" } { 506 | set_property -name "options.max_paths" -value "10" -objects $obj 507 | set_property -name "options.warn_on_violation" -value "1" -objects $obj 508 | 509 | } 510 | # Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) 511 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { 512 | create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 513 | } 514 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] 515 | if { $obj != "" } { 516 | set_property -name "options.warn_on_violation" -value "1" -objects $obj 517 | 518 | } 519 | set obj [get_runs impl_1] 520 | set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj 521 | set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj 522 | set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj 523 | 524 | # set the current impl run 525 | current_run -implementation [get_runs impl_1] 526 | 527 | puts "INFO: Project created:${_xil_proj_name_}" 528 | # Create 'drc_1' gadget (if not found) 529 | if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { 530 | create_dashboard_gadget -name {drc_1} -type drc 531 | } 532 | set obj [get_dashboard_gadgets [ list "drc_1" ] ] 533 | set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj 534 | 535 | # Create 'methodology_1' gadget (if not found) 536 | if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { 537 | create_dashboard_gadget -name {methodology_1} -type methodology 538 | } 539 | set obj [get_dashboard_gadgets [ list "methodology_1" ] ] 540 | set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj 541 | 542 | # Create 'power_1' gadget (if not found) 543 | if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { 544 | create_dashboard_gadget -name {power_1} -type power 545 | } 546 | set obj [get_dashboard_gadgets [ list "power_1" ] ] 547 | set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj 548 | 549 | # Create 'timing_1' gadget (if not found) 550 | if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { 551 | create_dashboard_gadget -name {timing_1} -type timing 552 | } 553 | set obj [get_dashboard_gadgets [ list "timing_1" ] ] 554 | set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj 555 | 556 | # Create 'utilization_1' gadget (if not found) 557 | if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { 558 | create_dashboard_gadget -name {utilization_1} -type utilization 559 | } 560 | set obj [get_dashboard_gadgets [ list "utilization_1" ] ] 561 | set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj 562 | set_property -name "run.step" -value "synth_design" -objects $obj 563 | set_property -name "run.type" -value "synthesis" -objects $obj 564 | 565 | # Create 'utilization_2' gadget (if not found) 566 | if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { 567 | create_dashboard_gadget -name {utilization_2} -type utilization 568 | } 569 | set obj [get_dashboard_gadgets [ list "utilization_2" ] ] 570 | set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj 571 | 572 | move_dashboard_gadget -name {utilization_1} -row 0 -col 0 573 | move_dashboard_gadget -name {power_1} -row 1 -col 0 574 | move_dashboard_gadget -name {drc_1} -row 2 -col 0 575 | move_dashboard_gadget -name {timing_1} -row 0 -col 1 576 | move_dashboard_gadget -name {utilization_2} -row 1 -col 1 577 | move_dashboard_gadget -name {methodology_1} -row 2 -col 1 578 | -------------------------------------------------------------------------------- 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