├── Building Your RayV Light Laser Fault Injection.pdf ├── FPGA └── 200_mhz │ ├── 200_mhz.cache │ ├── ip │ │ └── 2023.2 │ │ │ └── 8 │ │ │ └── 1 │ │ │ └── 81bb5ace1ab1e885 │ │ │ ├── 81bb5ace1ab1e885.xci │ │ │ ├── clk_wiz_0.dcp │ │ │ ├── clk_wiz_0_sim_netlist.v │ │ │ ├── clk_wiz_0_sim_netlist.vhdl │ │ │ ├── clk_wiz_0_stub.v │ │ │ └── clk_wiz_0_stub.vhdl │ ├── sim │ │ └── ssm.db │ └── wt │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf │ ├── 200_mhz.gen │ └── sources_1 │ │ └── ip │ │ └── clk_wiz_0 │ │ ├── clk_wiz_0.dcp │ │ ├── clk_wiz_0.v │ │ ├── clk_wiz_0.veo │ │ ├── clk_wiz_0.xdc │ │ ├── clk_wiz_0.xml │ │ ├── clk_wiz_0_board.xdc │ │ ├── clk_wiz_0_clk_wiz.v │ │ ├── clk_wiz_0_ooc.xdc │ │ ├── clk_wiz_0_sim_netlist.v │ │ ├── clk_wiz_0_sim_netlist.vhdl │ │ ├── clk_wiz_0_stub.v │ │ ├── clk_wiz_0_stub.vhdl │ │ ├── doc │ │ └── clk_wiz_v6_0_changelog.txt │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_pll.vh │ │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ │ └── mmcm_pll_drp_func_us_plus_pll.vh │ ├── 200_mhz.hw │ ├── 200_mhz.lpr │ └── hw_1 │ │ └── hw.xml │ ├── 200_mhz.ip_user_files │ ├── README.txt │ ├── ip │ │ └── clk_wiz_0 │ │ │ ├── clk_wiz_0.veo │ │ │ ├── clk_wiz_0_stub.v │ │ │ └── clk_wiz_0_stub.vhdl │ ├── ipstatic │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_pll.vh │ │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ │ └── mmcm_pll_drp_func_us_plus_pll.vh │ └── sim_scripts │ │ └── clk_wiz_0 │ │ ├── activehdl │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ │ ├── modelsim │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── questa │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── riviera │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ │ ├── vcs │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ │ ├── xcelium │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── hdl.var │ │ └── simulate.do │ │ └── xsim │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── cmd.tcl │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── vlog.prj │ ├── 200_mhz.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_100.xml │ │ ├── vrs_config_101.xml │ │ ├── vrs_config_102.xml │ │ ├── vrs_config_103.xml │ │ ├── vrs_config_104.xml │ │ ├── vrs_config_105.xml │ │ ├── vrs_config_106.xml │ │ ├── vrs_config_107.xml │ │ ├── vrs_config_108.xml │ │ ├── vrs_config_109.xml │ │ ├── vrs_config_11.xml │ │ ├── vrs_config_110.xml │ │ ├── vrs_config_111.xml │ │ ├── vrs_config_112.xml │ │ ├── vrs_config_113.xml │ │ ├── vrs_config_114.xml │ │ ├── vrs_config_115.xml │ │ ├── vrs_config_116.xml │ │ ├── vrs_config_117.xml │ │ ├── vrs_config_118.xml │ │ ├── vrs_config_119.xml │ │ ├── vrs_config_12.xml │ │ ├── vrs_config_120.xml │ │ ├── vrs_config_121.xml │ │ ├── vrs_config_122.xml │ │ ├── vrs_config_123.xml │ │ ├── vrs_config_124.xml │ │ ├── vrs_config_125.xml │ │ ├── vrs_config_126.xml │ │ ├── vrs_config_127.xml │ │ ├── vrs_config_128.xml │ │ ├── vrs_config_129.xml │ │ ├── vrs_config_13.xml │ │ ├── vrs_config_130.xml │ │ ├── vrs_config_131.xml │ │ ├── vrs_config_132.xml │ │ ├── vrs_config_133.xml │ │ ├── vrs_config_134.xml │ │ ├── vrs_config_135.xml │ │ ├── vrs_config_136.xml │ │ ├── vrs_config_137.xml │ │ ├── vrs_config_138.xml │ │ ├── vrs_config_139.xml │ │ ├── vrs_config_14.xml │ │ ├── vrs_config_140.xml │ │ ├── vrs_config_141.xml │ │ ├── vrs_config_142.xml │ │ ├── vrs_config_143.xml │ │ ├── vrs_config_144.xml │ │ ├── vrs_config_145.xml │ │ ├── vrs_config_146.xml │ │ ├── vrs_config_147.xml │ │ ├── vrs_config_148.xml │ │ ├── vrs_config_149.xml │ │ ├── vrs_config_15.xml │ │ ├── vrs_config_150.xml │ │ ├── vrs_config_151.xml │ │ ├── vrs_config_152.xml │ │ ├── vrs_config_153.xml │ │ ├── vrs_config_154.xml │ │ ├── vrs_config_155.xml │ │ ├── vrs_config_156.xml │ │ ├── vrs_config_157.xml │ │ ├── vrs_config_158.xml │ │ ├── vrs_config_159.xml │ │ ├── vrs_config_16.xml │ │ ├── vrs_config_160.xml │ │ ├── vrs_config_161.xml │ │ ├── vrs_config_162.xml │ │ ├── vrs_config_163.xml │ │ ├── vrs_config_164.xml │ │ ├── vrs_config_165.xml │ │ ├── vrs_config_166.xml │ │ ├── vrs_config_167.xml │ │ ├── vrs_config_168.xml │ │ ├── vrs_config_169.xml │ │ ├── vrs_config_17.xml │ │ ├── vrs_config_170.xml │ │ ├── vrs_config_171.xml │ │ ├── vrs_config_172.xml │ │ ├── vrs_config_173.xml │ │ ├── vrs_config_174.xml │ │ ├── vrs_config_175.xml │ │ ├── vrs_config_176.xml │ │ ├── vrs_config_177.xml │ │ ├── vrs_config_178.xml │ │ ├── vrs_config_179.xml │ │ ├── vrs_config_18.xml │ │ ├── vrs_config_180.xml │ │ ├── vrs_config_181.xml │ │ ├── vrs_config_182.xml │ │ ├── vrs_config_183.xml │ │ ├── vrs_config_184.xml │ │ ├── vrs_config_185.xml │ │ ├── vrs_config_186.xml │ │ ├── vrs_config_187.xml │ │ ├── vrs_config_188.xml │ │ ├── vrs_config_189.xml │ │ ├── vrs_config_19.xml │ │ ├── vrs_config_190.xml │ │ ├── vrs_config_191.xml │ │ ├── vrs_config_192.xml │ │ ├── vrs_config_193.xml │ │ ├── vrs_config_194.xml │ │ ├── vrs_config_195.xml │ │ ├── vrs_config_196.xml │ │ ├── vrs_config_197.xml │ │ ├── vrs_config_198.xml │ │ ├── vrs_config_199.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_20.xml │ │ ├── vrs_config_200.xml │ │ ├── vrs_config_201.xml │ │ ├── vrs_config_202.xml │ │ ├── vrs_config_203.xml │ │ ├── vrs_config_204.xml │ │ ├── vrs_config_205.xml │ │ ├── vrs_config_206.xml │ │ ├── vrs_config_207.xml │ │ ├── vrs_config_208.xml │ │ ├── vrs_config_209.xml │ │ ├── vrs_config_21.xml │ │ ├── vrs_config_210.xml │ │ ├── vrs_config_211.xml │ │ ├── vrs_config_212.xml │ │ ├── vrs_config_213.xml │ │ ├── vrs_config_214.xml │ │ ├── vrs_config_215.xml │ │ ├── vrs_config_216.xml │ │ ├── vrs_config_217.xml │ │ ├── vrs_config_218.xml │ │ ├── vrs_config_219.xml │ │ ├── vrs_config_22.xml │ │ ├── vrs_config_220.xml │ │ ├── vrs_config_221.xml │ │ ├── vrs_config_222.xml │ │ ├── vrs_config_223.xml │ │ ├── vrs_config_224.xml │ │ ├── vrs_config_225.xml │ │ ├── vrs_config_226.xml │ │ ├── vrs_config_227.xml │ │ ├── vrs_config_228.xml │ │ ├── vrs_config_229.xml │ │ ├── vrs_config_23.xml │ │ ├── vrs_config_230.xml │ │ ├── vrs_config_231.xml │ │ ├── vrs_config_232.xml │ │ ├── vrs_config_233.xml │ │ ├── vrs_config_234.xml │ │ ├── vrs_config_235.xml │ │ ├── vrs_config_236.xml │ │ ├── vrs_config_237.xml │ │ ├── vrs_config_238.xml │ │ ├── vrs_config_239.xml │ │ ├── vrs_config_24.xml │ │ ├── vrs_config_240.xml │ │ ├── vrs_config_241.xml │ │ ├── vrs_config_242.xml │ │ ├── vrs_config_243.xml │ │ ├── vrs_config_244.xml │ │ ├── vrs_config_245.xml │ │ ├── vrs_config_246.xml │ │ ├── vrs_config_247.xml │ │ ├── vrs_config_248.xml │ │ ├── vrs_config_249.xml │ │ ├── vrs_config_25.xml │ │ ├── vrs_config_250.xml │ │ ├── vrs_config_251.xml │ │ ├── vrs_config_252.xml │ │ ├── vrs_config_253.xml │ │ ├── vrs_config_254.xml │ │ ├── vrs_config_255.xml │ │ ├── vrs_config_256.xml │ │ ├── vrs_config_257.xml │ │ ├── vrs_config_258.xml │ │ ├── vrs_config_259.xml │ │ ├── vrs_config_26.xml │ │ ├── vrs_config_260.xml │ │ ├── vrs_config_261.xml │ │ ├── vrs_config_262.xml │ │ ├── vrs_config_263.xml │ │ ├── vrs_config_264.xml │ │ ├── vrs_config_265.xml │ │ ├── vrs_config_266.xml │ │ ├── vrs_config_267.xml │ │ ├── vrs_config_268.xml │ │ ├── vrs_config_269.xml │ │ ├── vrs_config_27.xml │ │ ├── vrs_config_270.xml │ │ ├── vrs_config_271.xml │ │ ├── vrs_config_272.xml │ │ ├── vrs_config_273.xml │ │ ├── vrs_config_274.xml │ │ ├── vrs_config_275.xml │ │ ├── vrs_config_276.xml │ │ ├── vrs_config_277.xml │ │ ├── vrs_config_278.xml │ │ ├── vrs_config_279.xml │ │ ├── vrs_config_28.xml │ │ ├── vrs_config_280.xml │ │ ├── vrs_config_281.xml │ │ ├── vrs_config_282.xml │ │ ├── vrs_config_283.xml │ │ ├── vrs_config_284.xml │ │ ├── vrs_config_285.xml │ │ ├── vrs_config_286.xml │ │ ├── vrs_config_287.xml │ │ ├── vrs_config_288.xml │ │ ├── vrs_config_289.xml │ │ ├── vrs_config_29.xml │ │ ├── vrs_config_290.xml │ │ ├── vrs_config_291.xml │ │ ├── vrs_config_292.xml │ │ ├── vrs_config_293.xml │ │ ├── vrs_config_294.xml │ │ ├── vrs_config_295.xml │ │ ├── vrs_config_296.xml │ │ ├── vrs_config_297.xml │ │ ├── vrs_config_298.xml │ │ ├── vrs_config_299.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_30.xml │ │ ├── vrs_config_300.xml │ │ ├── vrs_config_301.xml │ │ ├── vrs_config_302.xml │ │ ├── vrs_config_303.xml │ │ ├── vrs_config_304.xml │ │ ├── vrs_config_305.xml │ │ ├── vrs_config_306.xml │ │ ├── vrs_config_307.xml │ │ ├── vrs_config_308.xml │ │ ├── vrs_config_309.xml │ │ ├── vrs_config_31.xml │ │ ├── vrs_config_310.xml │ │ ├── vrs_config_311.xml │ │ ├── vrs_config_312.xml │ │ ├── vrs_config_313.xml │ │ ├── vrs_config_314.xml │ │ ├── vrs_config_315.xml │ │ ├── vrs_config_316.xml │ │ ├── vrs_config_317.xml │ │ ├── vrs_config_318.xml │ │ ├── vrs_config_319.xml │ │ ├── vrs_config_32.xml │ │ ├── vrs_config_320.xml │ │ ├── vrs_config_321.xml │ │ ├── vrs_config_322.xml │ │ ├── vrs_config_323.xml │ │ ├── vrs_config_324.xml │ │ ├── vrs_config_325.xml │ │ ├── vrs_config_326.xml │ │ ├── vrs_config_327.xml │ │ ├── vrs_config_328.xml │ │ ├── vrs_config_329.xml │ │ ├── vrs_config_33.xml │ │ ├── vrs_config_330.xml │ │ ├── vrs_config_331.xml │ │ ├── vrs_config_332.xml │ │ ├── vrs_config_333.xml │ │ ├── vrs_config_334.xml │ │ ├── vrs_config_335.xml │ │ ├── vrs_config_336.xml │ │ ├── vrs_config_337.xml │ │ ├── vrs_config_338.xml │ │ ├── vrs_config_339.xml │ │ ├── vrs_config_34.xml │ │ ├── vrs_config_340.xml │ │ ├── vrs_config_341.xml │ │ ├── vrs_config_342.xml │ │ ├── vrs_config_343.xml │ │ ├── vrs_config_344.xml │ │ ├── vrs_config_345.xml │ │ ├── vrs_config_346.xml │ │ ├── vrs_config_347.xml │ │ ├── vrs_config_348.xml │ │ ├── vrs_config_349.xml │ │ ├── vrs_config_35.xml │ │ ├── vrs_config_350.xml │ │ ├── vrs_config_351.xml │ │ ├── vrs_config_36.xml │ │ ├── vrs_config_37.xml │ │ ├── vrs_config_38.xml │ │ ├── vrs_config_39.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_40.xml │ │ ├── vrs_config_41.xml │ │ ├── vrs_config_42.xml │ │ ├── vrs_config_43.xml │ │ ├── vrs_config_44.xml │ │ ├── vrs_config_45.xml │ │ ├── vrs_config_46.xml │ │ ├── vrs_config_47.xml │ │ ├── vrs_config_48.xml │ │ ├── vrs_config_49.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_50.xml │ │ ├── vrs_config_51.xml │ │ ├── vrs_config_52.xml │ │ ├── vrs_config_53.xml │ │ ├── vrs_config_54.xml │ │ ├── vrs_config_55.xml │ │ ├── vrs_config_56.xml │ │ ├── vrs_config_57.xml │ │ ├── vrs_config_58.xml │ │ ├── vrs_config_59.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_60.xml │ │ ├── vrs_config_61.xml │ │ ├── vrs_config_62.xml │ │ ├── vrs_config_63.xml │ │ ├── vrs_config_64.xml │ │ ├── vrs_config_65.xml │ │ ├── vrs_config_66.xml │ │ ├── vrs_config_67.xml │ │ ├── vrs_config_68.xml │ │ ├── vrs_config_69.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_70.xml │ │ ├── vrs_config_71.xml │ │ ├── vrs_config_72.xml │ │ ├── vrs_config_73.xml │ │ ├── vrs_config_74.xml │ │ ├── vrs_config_75.xml │ │ ├── vrs_config_76.xml │ │ ├── vrs_config_77.xml │ │ ├── vrs_config_78.xml │ │ ├── vrs_config_79.xml │ │ ├── vrs_config_8.xml │ │ ├── vrs_config_80.xml │ │ ├── vrs_config_81.xml │ │ ├── vrs_config_82.xml │ │ ├── vrs_config_83.xml │ │ ├── vrs_config_84.xml │ │ ├── vrs_config_85.xml │ │ ├── vrs_config_86.xml │ │ ├── vrs_config_87.xml │ │ ├── vrs_config_88.xml │ │ ├── vrs_config_89.xml │ │ ├── vrs_config_9.xml │ │ ├── vrs_config_90.xml │ │ ├── vrs_config_91.xml │ │ ├── vrs_config_92.xml │ │ ├── vrs_config_93.xml │ │ ├── vrs_config_94.xml │ │ ├── vrs_config_95.xml │ │ ├── vrs_config_96.xml │ │ ├── vrs_config_97.xml │ │ ├── vrs_config_98.xml │ │ └── vrs_config_99.xml │ ├── clk_wiz_0_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ │ └── clk_wiz_0_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── clk_wiz_0.dcp │ │ ├── clk_wiz_0.tcl │ │ ├── clk_wiz_0.vds │ │ ├── clk_wiz_0_utilization_synth.pb │ │ ├── clk_wiz_0_utilization_synth.rpt │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb │ ├── impl_1 │ │ ├── .Vivado_Implementation.queue.rst │ │ ├── .init_design.begin.rst │ │ ├── .init_design.end.rst │ │ ├── .opt_design.begin.rst │ │ ├── .opt_design.end.rst │ │ ├── .phys_opt_design.begin.rst │ │ ├── .phys_opt_design.end.rst │ │ ├── .place_design.begin.rst │ │ ├── .place_design.end.rst │ │ ├── .route_design.begin.rst │ │ ├── .route_design.end.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── .write_bitstream.begin.rst │ │ ├── .write_bitstream.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── clockInfo.txt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── phys_opt_design.pb │ │ ├── place_design.pb │ │ ├── project.wdf │ │ ├── route_design.pb │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── test_200.bit │ │ ├── test_200.tcl │ │ ├── test_200.vdi │ │ ├── test_200_274287.backup.vdi │ │ ├── test_200_289820.backup.vdi │ │ ├── test_200_307147.backup.vdi │ │ ├── test_200_325192.backup.vdi │ │ ├── test_200_343740.backup.vdi │ │ ├── test_200_bus_skew_routed.pb │ │ ├── test_200_bus_skew_routed.rpt │ │ ├── test_200_bus_skew_routed.rpx │ │ ├── test_200_clock_utilization_routed.rpt │ │ ├── test_200_control_sets_placed.rpt │ │ ├── test_200_drc_opted.pb │ │ ├── test_200_drc_opted.rpt │ │ ├── test_200_drc_opted.rpx │ │ ├── test_200_drc_routed.pb │ │ ├── test_200_drc_routed.rpt │ │ ├── test_200_drc_routed.rpx │ │ ├── test_200_io_placed.rpt │ │ ├── test_200_methodology_drc_routed.pb │ │ ├── test_200_methodology_drc_routed.rpt │ │ ├── test_200_methodology_drc_routed.rpx │ │ ├── test_200_opt.dcp │ │ ├── test_200_physopt.dcp │ │ ├── test_200_placed.dcp │ │ ├── test_200_power_routed.rpt │ │ ├── test_200_power_routed.rpx │ │ ├── test_200_power_summary_routed.pb │ │ ├── test_200_route_status.pb │ │ ├── test_200_route_status.rpt │ │ ├── test_200_routed.dcp │ │ ├── test_200_timing_summary_routed.pb │ │ ├── test_200_timing_summary_routed.rpt │ │ ├── test_200_timing_summary_routed.rpx │ │ ├── test_200_utilization_placed.pb │ │ ├── test_200_utilization_placed.rpt │ │ ├── tight_setup_hold_pins.txt │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ ├── vivado_274287.backup.jou │ │ ├── vivado_289820.backup.jou │ │ ├── vivado_307147.backup.jou │ │ ├── vivado_325192.backup.jou │ │ ├── vivado_343740.backup.jou │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ └── test_200_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── incr_synth_reason.pb │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── test_200.dcp │ │ ├── test_200.tcl │ │ ├── test_200.vds │ │ ├── test_200_utilization_synth.pb │ │ ├── test_200_utilization_synth.rpt │ │ ├── vivado.jou │ │ └── vivado.pb │ ├── 200_mhz.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── compile.log │ │ ├── compile.sh │ │ ├── elaborate.log │ │ ├── elaborate.sh │ │ ├── glbl.v │ │ ├── simulate.log │ │ ├── simulate.sh │ │ ├── test_200.tcl │ │ ├── test_200_behav.wdb │ │ ├── test_200_vlog.prj │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── test_200_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.lnx64.o │ │ │ │ ├── xsim_1.lnx64.o │ │ │ │ ├── xsim_2.c │ │ │ │ └── xsim_2.lnx64.o │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk │ │ │ └── xsimkernel.log │ │ └── xil_defaultlib │ │ │ ├── clk_wiz_0.sdb │ │ │ ├── clk_wiz_0_clk_wiz.sdb │ │ │ ├── glbl.sdb │ │ │ ├── test_200.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xsim.ini.bak │ │ ├── xvlog.log │ │ └── xvlog.pb │ ├── 200_mhz.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── arty_s7-25.xdc │ ├── sources_1 │ │ ├── bd │ │ │ └── design_1 │ │ │ │ └── design_1.bd │ │ ├── ip │ │ │ └── clk_wiz_0 │ │ │ │ └── clk_wiz_0.xci │ │ └── new │ │ │ └── test_200.v │ └── utils_1 │ │ └── imports │ │ └── synth_1 │ │ └── test_200.dcp │ └── 200_mhz.xpr ├── LaserComponentsList.xlsx ├── Model_Training ├── bits_test_cropped.py ├── test_model.py └── validate_training.sh ├── Openflexure_Additions ├── fl_cube.stl ├── laser_holder.stl └── optics_picamera2_rms_f50d13_beamsplitter_delta.stl ├── Pictures ├── Main.png └── cube.png └── README.md /Building Your RayV Light Laser Fault Injection.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/Building Your RayV Light Laser Fault Injection.pdf -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.cache/ip/2023.2/8/1/81bb5ace1ab1e885/clk_wiz_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.cache/ip/2023.2/8/1/81bb5ace1ab1e885/clk_wiz_0.dcp -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.cache/sim/ssm.db: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # DONOT REMOVE THIS FILE 3 | # Unified simulation database file for selected simulation model for IP 4 | # 5 | # File: ssm.db (Tue May 28 22:31:41 2024) 6 | # 7 | # This file is generated by the unified simulation automation and contains the 8 | # selected simulation model information for the IP/BD instances. 9 | # DONOT REMOVE THIS FILE 10 | ################################################################################ 11 | clk_wiz_0,rtl 12 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 57656254616c6b5472616e736d697373696f6e417474656d70746564:90 3 | 6d6f64655f636f756e7465727c4755494d6f6465:9 4 | eof: 5 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.cache/wt/synthesis_details.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 3 | eof:2511430288 4 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:241934075 5 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.hw/200_mhz.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | transcript off 2 | onbreak {quit -force} 3 | onerror {quit -force} 4 | transcript on 5 | 6 | asim +access +r +m+clk_wiz_0 -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O2 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl 7 | 8 | do {clk_wiz_0.udo} 9 | 10 | run 11 | 12 | endsim 13 | 14 | quit -force 15 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl 5 | 6 | set NumericStdNoWarnings 1 7 | set StdArithNoWarnings 1 8 | 9 | do {wave.do} 10 | 11 | view wave 12 | view structure 13 | view signals 14 | 15 | do {clk_wiz_0.udo} 16 | 17 | run 1000ns 18 | 19 | quit -force 20 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 -l elaborate.log +acc=npr -suppress 10016 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_opt 2 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -lib xil_defaultlib clk_wiz_0_opt 5 | 6 | set NumericStdNoWarnings 1 7 | set StdArithNoWarnings 1 8 | 9 | do {wave.do} 10 | 11 | view wave 12 | view structure 13 | view signals 14 | 15 | do {clk_wiz_0.udo} 16 | 17 | run 1000ns 18 | 19 | quit -force 20 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | transcript off 2 | onbreak {quit -force} 3 | onerror {quit -force} 4 | transcript on 5 | 6 | asim +access +r +m+clk_wiz_0 -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl 7 | 8 | do {clk_wiz_0.udo} 9 | 10 | run 1000ns 11 | 12 | endsim 13 | 14 | quit -force 15 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 1000ns 2 | quit 3 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/xcelium/hdl.var: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/xcelium/hdl.var -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do: -------------------------------------------------------------------------------- 1 | set pack_assert_off {numeric_std std_logic_arith} 2 | 3 | database -open waves -into waves.shm -default 4 | catch {probe -create -shm -all -variables -depth 1} msg 5 | 6 | run 1000ns 7 | exit 8 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | quit 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 2 | clk_wiz_0.v,verilog,xil_defaultlib,../../../../200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib --include "../../../ipstatic" \ 2 | "../../../../200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ 3 | "../../../../200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ 4 | 5 | verilog xil_defaultlib "glbl.v" 6 | 7 | # Do not sort compile order 8 | nosort 9 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_10.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_100.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_101.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_103.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_104.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_106.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_107.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_109.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_11.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_110.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_111.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_112.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_113.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_114.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_115.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_116.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_117.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_118.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_119.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_120.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_122.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_123.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_124.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_125.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_126.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_127.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_129.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_13.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_130.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_131.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_133.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_134.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_135.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_137.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_138.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_14.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_140.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_141.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_143.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_144.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_146.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_147.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_149.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_150.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_152.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_153.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_155.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_156.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_157.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_158.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_159.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_16.xml: 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-------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_34.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_340.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_341.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_343.xml: 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-------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_53.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_54.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_55.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_56.xml: 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-------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_60.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_61.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_64.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_67.xml: 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-------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_72.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_73.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_74.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_76.xml: 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-------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_81.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_84.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_87.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_90.xml: 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-------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_94.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/.jobs/vrs_config_97.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc: -------------------------------------------------------------------------------- 1 | set_property SRC_FILE_INFO {cfile:/home/patch/200_mhz/200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc rfile:../../../200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc id:1 order:EARLY scoped_inst:inst} [current_design] 2 | current_instance inst 3 | set_property src_info {type:SCOPED_XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] 4 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100 5 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 7 | # Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 8 | # 9 | 10 | vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl 11 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 6 | rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | 8 | 9 | set HD_SDIR=%~dp0 10 | cd /d "%HD_SDIR%" 11 | set PATH=%SYSTEMROOT%\system32;%PATH% 12 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/clk_wiz_0_synth_1/vivado.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.Vivado_Implementation.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/.Vivado_Implementation.queue.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.init_design.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.init_design.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/.init_design.end.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.opt_design.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.opt_design.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/.opt_design.end.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.phys_opt_design.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.phys_opt_design.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/.phys_opt_design.end.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.place_design.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.place_design.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/.place_design.end.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.route_design.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.route_design.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/.route_design.end.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/.vivado.end.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.write_bitstream.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/.write_bitstream.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/.write_bitstream.end.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/clockInfo.txt: -------------------------------------------------------------------------------- 1 | ------------------------------------- 2 | | Tool Version : Vivado v.2023.2 3 | | Date : Wed Jul 10 19:02:28 2024 4 | | Host : patch-Precision-7760 5 | | Design : design_1 6 | | Device : xc7s25-csga324-1-- 7 | ------------------------------------- 8 | 9 | For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US 10 | 11 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 7 | # Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 8 | # 9 | 10 | vivado -log test_200.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source test_200.tcl -notrace 11 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/init_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/init_design.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/opt_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/opt_design.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/phys_opt_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/phys_opt_design.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/place_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/place_design.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/route_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/route_design.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 6 | rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | 8 | 9 | set HD_SDIR=%~dp0 10 | cd /d "%HD_SDIR%" 11 | set PATH=%SYSTEMROOT%\system32;%PATH% 12 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/test_200.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/test_200.bit -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/test_200_bus_skew_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/test_200_bus_skew_routed.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/test_200_bus_skew_routed.rpx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/test_200_bus_skew_routed.rpx -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/test_200_drc_opted.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/impl_1/test_200_drc_opted.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/impl_1/test_200_drc_opted.rpx: -------------------------------------------------------------------------------- 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/FPGA/200_mhz/200_mhz.runs/synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 7 | # Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 8 | # 9 | 10 | vivado -log test_200.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source test_200.tcl 11 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/synth_1/incr_synth_reason.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/synth_1/incr_synth_reason.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 6 | rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | 8 | 9 | set HD_SDIR=%~dp0 10 | cd /d "%HD_SDIR%" 11 | set PATH=%SYSTEMROOT%\system32;%PATH% 12 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 13 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/synth_1/test_200.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/synth_1/test_200.dcp -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/synth_1/test_200_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/synth_1/test_200_utilization_synth.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.runs/synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.runs/synth_1/vivado.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.sim/sim_1/behav/xsim/simulate.log -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.sim/sim_1/behav/xsim/test_200.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.sim/sim_1/behav/xsim/test_200_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.sim/sim_1/behav/xsim/test_200_behav.wdb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.sim/sim_1/behav/xsim/test_200_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib --include "../../../../200_mhz.ip_user_files/ipstatic" \ 3 | "../../../../200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ 4 | "../../../../200_mhz.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ 5 | "../../../../200_mhz.srcs/sources_1/new/test_200.v" \ 6 | 7 | # compile glbl module 8 | verilog xil_defaultlib "glbl.v" 9 | 10 | # Do not sort compile order 11 | nosort 12 | -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.sim/sim_1/behav/xsim/xsim.dir/test_200_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot 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-------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.srcs/sources_1/bd/design_1/design_1.bd: -------------------------------------------------------------------------------- 1 | { 2 | "design": { 3 | "design_info": { 4 | "boundary_crc": "0x0", 5 | "gen_directory": "../../../../200_mhz.gen/sources_1/bd/design_1", 6 | "name": "design_1", 7 | "rev_ctrl_bd_flag": "RevCtrlBdOff", 8 | "synth_flow_mode": "Hierarchical", 9 | "tool_version": "2023.2" 10 | }, 11 | "design_tree": {} 12 | } 13 | } -------------------------------------------------------------------------------- /FPGA/200_mhz/200_mhz.srcs/utils_1/imports/synth_1/test_200.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ProjectLOREM/RayVLite/b17db390921be2dcdb9bbd19373b2f2ecc5980ba/FPGA/200_mhz/200_mhz.srcs/utils_1/imports/synth_1/test_200.dcp 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