├── LICENSE ├── README.md └── src ├── Avg.v ├── Avg_pool.v ├── Conv2d.v ├── ConvKernel.v ├── FullConnect.v ├── Max.v ├── Max_pool.v ├── Mult.v ├── Relu.v └── Relu_activation.v /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/README.md -------------------------------------------------------------------------------- /src/Avg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/Avg.v -------------------------------------------------------------------------------- /src/Avg_pool.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/Avg_pool.v -------------------------------------------------------------------------------- /src/Conv2d.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/Conv2d.v -------------------------------------------------------------------------------- /src/ConvKernel.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/ConvKernel.v -------------------------------------------------------------------------------- /src/FullConnect.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/FullConnect.v -------------------------------------------------------------------------------- /src/Max.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/Max.v -------------------------------------------------------------------------------- /src/Max_pool.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/Max_pool.v -------------------------------------------------------------------------------- /src/Mult.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/Mult.v -------------------------------------------------------------------------------- /src/Relu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/Relu.v -------------------------------------------------------------------------------- /src/Relu_activation.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QShen3/CNN-FPGA/HEAD/src/Relu_activation.v --------------------------------------------------------------------------------