├── 3rd_party ├── CMSIS │ ├── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_armclang_ltm.h │ │ ├── cmsis_ccs.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv81mml.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm35p.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h │ ├── LICENSE.txt │ └── README.txt ├── README.txt ├── ek-tm4c123gxl │ ├── README.txt │ ├── TM4C123GH6PM.h │ ├── arm │ │ └── startup_TM4C123GH6PM.s │ ├── gnu │ │ └── startup_TM4C123GH6PM.c │ ├── gpio.h │ ├── iar │ │ └── startup_TM4C123GH6PM.s │ ├── rom.h │ ├── sysctl.h │ ├── system_TM4C123GH6PM.c │ └── system_TM4C123GH6PM.h ├── nucleo-c031c6 │ ├── README.txt │ ├── arm │ │ └── startup_stm32c031xx.s │ ├── gnu │ │ ├── nucleo-c031c6.ld │ │ └── startup_stm32c031xx.c │ ├── iar │ │ └── startup_stm32c031xx.s │ ├── qutest │ │ ├── qutest.ld │ │ ├── qutest_cpp.cpp │ │ └── qutest_port.c │ ├── stm32c031xx.h │ ├── stm32c0xx.h │ ├── system_stm32c0xx.c │ └── system_stm32c0xx.h └── nucleo-l152re │ ├── README.txt │ ├── arm │ └── startup_stm32l1xx.s │ ├── gnu │ └── startup_stm32l1xx.c │ ├── iar │ └── startup_stm32l1xx.s │ ├── stm32l1xx.h │ ├── system_stm32l1xx.c │ ├── system_stm32l1xx.c.pll │ └── system_stm32l1xx.h ├── LICENSE ├── README.md ├── examples ├── blinky_ek-tm4c123gxl │ ├── armclang │ │ ├── project.uvoptx │ │ └── project.uvprojx │ ├── bsp.c │ ├── bsp.h │ ├── gnu │ │ ├── Makefile │ │ └── project.ld │ ├── iar │ │ ├── project.ewd │ │ ├── project.ewp │ │ ├── project.eww │ │ └── project.icf │ └── main.c ├── blinky_nucleo-c031c6 │ ├── armclang │ │ ├── project.uvoptx │ │ └── project.uvprojx │ ├── bsp.c │ ├── bsp.h │ ├── gnu │ │ ├── Makefile │ │ └── project.ld │ ├── iar │ │ ├── project.ewd │ │ ├── project.ewp │ │ ├── project.eww │ │ └── project.icf │ └── main.c └── blinky_nucleo-l152re │ ├── armclang │ ├── project.uvoptx │ └── project.uvprojx │ ├── bsp.c │ ├── bsp.h │ ├── gnu │ ├── Makefile │ └── project.ld │ ├── iar │ ├── project.ewd │ ├── project.ewp │ ├── project.eww │ └── project.icf │ └── main.c ├── img ├── MiROS.jpg ├── bd_EK-TM4C123GXL.png ├── bd_NUCLEO-C031C6.jpg ├── bd_NUCLEO-L152RE.png └── github-star.jpg ├── include ├── miros.h └── qassert.h └── src ├── armclang └── miros.c ├── gnu └── miros.c └── iar └── miros.c /3rd_party/CMSIS/Include/cmsis_ccs.h: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // 3 | // Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions 7 | // are met: 8 | // 9 | // Redistributions of source code must retain the above copyright 10 | // notice, this list of conditions and the following disclaimer. 11 | // 12 | // Redistributions in binary form must reproduce the above copyright 13 | // notice, this list of conditions and the following disclaimer in the 14 | // documentation and/or other materials provided with the 15 | // distribution. 16 | // 17 | // Neither the name of Texas Instruments Incorporated nor the names of 18 | // its contributors may be used to endorse or promote products derived 19 | // from this software without specific prior written permission. 20 | // 21 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 | // 33 | // MSP432 Family CMSIS Definitions 34 | // 35 | //**************************************************************************** 36 | 37 | #ifndef CMSIS_CCS_H_ 38 | #define CMSIS_CCS_H_ 39 | 40 | //***************************************************************************** 41 | // CMSIS-compatible instruction calls 42 | //***************************************************************************** 43 | 44 | // 45 | // v5e, v6, Cortex-M3, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics 46 | // 47 | #define __CLZ _norm 48 | #define __SXTB _sxtb 49 | #define __SXTH _sxth 50 | #define __UXTB _uxtb 51 | #define __UXTH _uxth 52 | 53 | // CCS supports intrinsics to take advantage of the shift operand left/right 54 | // before saturation extension of SSAT, but CMSIS does not take advantage 55 | // of those, so tell the compiler to use a sat & shift left with a shift 56 | // value of 0 whenever it encounters an SSAT 57 | #define __SSAT(VAL, BITPOS) \ 58 | _ssatl(VAL , 0, BITPOS) 59 | 60 | // 61 | // Only define M4 based intrinsics if we're not using an M4 62 | // 63 | #if defined (__TI_TMS470_V7M4__) 64 | 65 | // 66 | // Add definitions for enable and disable interrupts 67 | // 68 | #if defined (__TI_COMPILER_VERSION__) 69 | 70 | #if (__TI_COMPILER_VERSION__ >= 5002000) 71 | 72 | #define __enable_irq _enable_IRQ 73 | #define __disable_irq _disable_IRQ 74 | 75 | // No Operation 76 | #define __NOP __nop 77 | // Data Synchronization Barrier 78 | #define __DSB _dsb 79 | 80 | #define __ISB _isb 81 | 82 | #define __WFI() __asm(" wfi") 83 | 84 | #elif (__TI_COMPILER_VERSION__ >= 4009000) 85 | 86 | #define __enable_fault_irq _enable_interrupts 87 | #define __disable_fault_irq _disable_interrupts 88 | 89 | // No Operation 90 | __attribute__( ( always_inline ) ) static inline void __nop(void) 91 | { 92 | __asm(" nop"); 93 | } 94 | 95 | __attribute__( ( always_inline ) ) static inline void __NOP(void) 96 | { 97 | __asm(" nop"); 98 | } 99 | 100 | // Data Synchronization Barrier 101 | __attribute__( ( always_inline ) ) static inline void __DSB(void) 102 | { 103 | __asm(" dsb"); 104 | } 105 | 106 | __attribute__( ( always_inline ) ) static inline void __ISB(void) 107 | { 108 | __asm(" isb"); 109 | } 110 | 111 | __attribute__( ( always_inline ) ) static inline void __WFI(void) 112 | { 113 | __asm(" wfi"); 114 | } 115 | 116 | #endif /*__TI_COMPILER_VERSION__ version*/ 117 | 118 | #endif /*__TI_COMPILER_VERSION__*/ 119 | 120 | // 121 | // V5E, V6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics 122 | // 123 | #define __ROR __ror 124 | #define __SXTB16(src) _sxtb16((src),0) 125 | #define __QADD _sadd 126 | #define __QDADD _sdadd 127 | #define __QDSUB _sdsub 128 | #define __SMLABB _smlabb 129 | #define __SMLABT _smlabt 130 | #define __SMLALBB _smlalbb 131 | #define __SMLALBT _smlalbt 132 | #define __SMLALTB _smlaltb 133 | #define __SMLALTT _smlaltt 134 | #define __SMLATB _smlatb 135 | #define __SMLATT _smlatt 136 | #define __SMLAWB _smlawb 137 | #define __SMLAWT _smlawt 138 | 139 | #define __SMULBB _smulbb 140 | #define __SMULBT _smulbt 141 | #define __SMULTB _smultb 142 | #define __SMULTT _smultt 143 | #define __SMULWB _smulwb 144 | #define __SMULWT _smulwt 145 | #define __QSUB _ssub 146 | #define __SUBC _subc 147 | 148 | // 149 | // v6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics 150 | // 151 | #define __SHASX _shaddsubx 152 | #define __SHSAX _shsubaddx 153 | #define __PKHBT _pkhbt 154 | #define __PKHTB _pkhtb 155 | #define __QADD16 _qadd16 156 | #define __QADD8 _qadd8 157 | #define __QSUB16 _qsub16 158 | #define __QSUB8 _qsub8 159 | #define __QASX _saddsubx 160 | #define __QSAX _qsubaddx 161 | #define __SADD16 _sadd16 162 | #define __SADD8 _sadd8 163 | #define __SASX _saddsubx 164 | #define __SEL _sel 165 | #define __SHADD16 _shadd16 166 | #define __SHADD8 _shadd8 167 | #define __SHSUB16 _shsub16 168 | #define __SHSUB8 _shsub8 169 | #define __SMLAD _smlad 170 | #define __SMLADX _smladx 171 | #define __SMLALD(src1, src2, accumulator) _smlald(accumulator, src1, src2) 172 | #define __SMLALDX _smlaldx 173 | #define __SMLSD _smlsd 174 | #define __SMLSDX _smlsdx 175 | #define __SMLSLD _smlsld 176 | #define __SMLSLDX _smlsldx 177 | #define __SMMLA _smmla 178 | #define __SMMLAR _smmlar 179 | #define __SMMLS _smmls 180 | #define __SMMLSR _smmlsr 181 | #define __SMMUL _smmul 182 | #define __SMMULR _smmulr 183 | #define __SMUAD _smuad 184 | #define __SMUADX _smuadx 185 | #define __SMUSD _smusd 186 | #define __SMUSDX _smusdx 187 | #define __SSAT16 _ssat16 188 | #define __SSUB16 _ssub16 189 | #define __SSUB8 _ssub8 190 | #define __SSAX _ssubaddx 191 | #define __SXTAB _sxtab 192 | #define __SXTAB16 _sxtab16 193 | #define __SXTAH _sxtah 194 | #define __UMAAL _umaal 195 | #define __UADD16 _uadd16 196 | #define __UADD8 _uadd8 197 | #define __UHADD16 _uhadd16 198 | #define __UHADD8 _uhadd8 199 | #define __UASX _uaddsubx 200 | #define __UHSUB16 _uhsub16 201 | #define __UHSUB8 _uhsub8 202 | #define __UQADD16 _uqadd16 203 | #define __UQADD8 _uqadd8 204 | #define __UQASX _uqaddsubx 205 | #define __UQSUB16 _uqsub16 206 | #define __UQSUB8 _uqsub8 207 | #define __UQSAX _uqsubaddx 208 | #define __USAD8 _usad8 209 | #define __USAT16 _usat16 210 | #define __USUB16 _usub16 211 | #define __USUB8 _usub8 212 | #define __USAX _usubaddx 213 | #define __UXTAB _uxtab 214 | #define __UXTAB16 _uxtab16 215 | #define __UXTAH _uxtah 216 | #define __UXTB16 _uxtb16 217 | #endif /*__TI_TMS470_V7M4__*/ 218 | 219 | #endif /*CMSIS_CCS_H_*/ 220 | -------------------------------------------------------------------------------- /3rd_party/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.1.0 5 | * @date 09. October 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6.6 LTM (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) 41 | #include "cmsis_armclang_ltm.h" 42 | 43 | /* 44 | * Arm Compiler above 6.10.1 (armclang) 45 | */ 46 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) 47 | #include "cmsis_armclang.h" 48 | 49 | 50 | /* 51 | * GNU Compiler 52 | */ 53 | #elif defined ( __GNUC__ ) 54 | #include "cmsis_gcc.h" 55 | 56 | 57 | /* 58 | * IAR Compiler 59 | */ 60 | #elif defined ( __ICCARM__ ) 61 | #include 62 | 63 | 64 | /* 65 | * TI Arm Compiler 66 | */ 67 | #elif defined ( __TI_ARM__ ) 68 | #include 69 | 70 | #ifndef __ASM 71 | #define __ASM __asm 72 | #endif 73 | #ifndef __INLINE 74 | #define __INLINE inline 75 | #endif 76 | #ifndef __STATIC_INLINE 77 | #define __STATIC_INLINE static inline 78 | #endif 79 | #ifndef __STATIC_FORCEINLINE 80 | #define __STATIC_FORCEINLINE __STATIC_INLINE 81 | #endif 82 | #ifndef __NO_RETURN 83 | #define __NO_RETURN __attribute__((noreturn)) 84 | #endif 85 | #ifndef __USED 86 | #define __USED __attribute__((used)) 87 | #endif 88 | #ifndef __WEAK 89 | #define __WEAK __attribute__((weak)) 90 | #endif 91 | #ifndef __PACKED 92 | #define __PACKED __attribute__((packed)) 93 | #endif 94 | #ifndef __PACKED_STRUCT 95 | #define __PACKED_STRUCT struct __attribute__((packed)) 96 | #endif 97 | #ifndef __PACKED_UNION 98 | #define __PACKED_UNION union __attribute__((packed)) 99 | #endif 100 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 101 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 102 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 103 | #endif 104 | #ifndef __UNALIGNED_UINT16_WRITE 105 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 106 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 107 | #endif 108 | #ifndef __UNALIGNED_UINT16_READ 109 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 110 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 111 | #endif 112 | #ifndef __UNALIGNED_UINT32_WRITE 113 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 114 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 115 | #endif 116 | #ifndef __UNALIGNED_UINT32_READ 117 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 118 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 119 | #endif 120 | #ifndef __ALIGNED 121 | #define __ALIGNED(x) __attribute__((aligned(x))) 122 | #endif 123 | #ifndef __RESTRICT 124 | #define __RESTRICT __restrict 125 | #endif 126 | #ifndef __COMPILER_BARRIER 127 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 128 | #define __COMPILER_BARRIER() (void)0 129 | #endif 130 | 131 | 132 | /* 133 | * TASKING Compiler 134 | */ 135 | #elif defined ( __TASKING__ ) 136 | /* 137 | * The CMSIS functions have been implemented as intrinsics in the compiler. 138 | * Please use "carm -?i" to get an up to date list of all intrinsics, 139 | * Including the CMSIS ones. 140 | */ 141 | 142 | #ifndef __ASM 143 | #define __ASM __asm 144 | #endif 145 | #ifndef __INLINE 146 | #define __INLINE inline 147 | #endif 148 | #ifndef __STATIC_INLINE 149 | #define __STATIC_INLINE static inline 150 | #endif 151 | #ifndef __STATIC_FORCEINLINE 152 | #define __STATIC_FORCEINLINE __STATIC_INLINE 153 | #endif 154 | #ifndef __NO_RETURN 155 | #define __NO_RETURN __attribute__((noreturn)) 156 | #endif 157 | #ifndef __USED 158 | #define __USED __attribute__((used)) 159 | #endif 160 | #ifndef __WEAK 161 | #define __WEAK __attribute__((weak)) 162 | #endif 163 | #ifndef __PACKED 164 | #define __PACKED __packed__ 165 | #endif 166 | #ifndef __PACKED_STRUCT 167 | #define __PACKED_STRUCT struct __packed__ 168 | #endif 169 | #ifndef __PACKED_UNION 170 | #define __PACKED_UNION union __packed__ 171 | #endif 172 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 173 | struct __packed__ T_UINT32 { uint32_t v; }; 174 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 175 | #endif 176 | #ifndef __UNALIGNED_UINT16_WRITE 177 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 178 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 179 | #endif 180 | #ifndef __UNALIGNED_UINT16_READ 181 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 182 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 183 | #endif 184 | #ifndef __UNALIGNED_UINT32_WRITE 185 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 186 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 187 | #endif 188 | #ifndef __UNALIGNED_UINT32_READ 189 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 190 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 191 | #endif 192 | #ifndef __ALIGNED 193 | #define __ALIGNED(x) __align(x) 194 | #endif 195 | #ifndef __RESTRICT 196 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 197 | #define __RESTRICT 198 | #endif 199 | #ifndef __COMPILER_BARRIER 200 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 201 | #define __COMPILER_BARRIER() (void)0 202 | #endif 203 | 204 | 205 | /* 206 | * COSMIC Compiler 207 | */ 208 | #elif defined ( __CSMC__ ) 209 | #include 210 | 211 | #ifndef __ASM 212 | #define __ASM _asm 213 | #endif 214 | #ifndef __INLINE 215 | #define __INLINE inline 216 | #endif 217 | #ifndef __STATIC_INLINE 218 | #define __STATIC_INLINE static inline 219 | #endif 220 | #ifndef __STATIC_FORCEINLINE 221 | #define __STATIC_FORCEINLINE __STATIC_INLINE 222 | #endif 223 | #ifndef __NO_RETURN 224 | // NO RETURN is automatically detected hence no warning here 225 | #define __NO_RETURN 226 | #endif 227 | #ifndef __USED 228 | #warning No compiler specific solution for __USED. __USED is ignored. 229 | #define __USED 230 | #endif 231 | #ifndef __WEAK 232 | #define __WEAK __weak 233 | #endif 234 | #ifndef __PACKED 235 | #define __PACKED @packed 236 | #endif 237 | #ifndef __PACKED_STRUCT 238 | #define __PACKED_STRUCT @packed struct 239 | #endif 240 | #ifndef __PACKED_UNION 241 | #define __PACKED_UNION @packed union 242 | #endif 243 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 244 | @packed struct T_UINT32 { uint32_t v; }; 245 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 246 | #endif 247 | #ifndef __UNALIGNED_UINT16_WRITE 248 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 249 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 250 | #endif 251 | #ifndef __UNALIGNED_UINT16_READ 252 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 253 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 254 | #endif 255 | #ifndef __UNALIGNED_UINT32_WRITE 256 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 257 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 258 | #endif 259 | #ifndef __UNALIGNED_UINT32_READ 260 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 261 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 262 | #endif 263 | #ifndef __ALIGNED 264 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 265 | #define __ALIGNED(x) 266 | #endif 267 | #ifndef __RESTRICT 268 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 269 | #define __RESTRICT 270 | #endif 271 | #ifndef __COMPILER_BARRIER 272 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 273 | #define __COMPILER_BARRIER() (void)0 274 | #endif 275 | 276 | 277 | #else 278 | #error Unknown compiler. 279 | #endif 280 | 281 | 282 | #endif /* __CMSIS_COMPILER_H */ 283 | 284 | -------------------------------------------------------------------------------- /3rd_party/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.3 5 | * @date 24. June 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /3rd_party/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /3rd_party/CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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The text should be enclosed in the appropriate 184 | comment syntax for the file format. We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright {yyyy} {name of copyright owner} 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /3rd_party/CMSIS/README.txt: -------------------------------------------------------------------------------- 1 | About CMSIS 2 | =========== 3 | This folder contains the Cortex Microcontroller Software Interface Standard 4 | CMSIS 5.6.0 (https://github.com/ARM-software/CMSIS_5/releases/tag/5.6.0). 5 | 6 | CMSIS provides a single standard across all Cortex-M processor series vendors. 7 | It enables code re-use and code sharing across software projects and reduces 8 | time-to-market for new embedded applications. 9 | 10 | 11 | Licensing 12 | ========= 13 | CMSIS-5 is released under the terms of the Apache License Version 2.0 14 | included in the file LICENSE.txt. 15 | 16 | 17 | Complete Downloads 18 | ================== 19 | To reduce the size of the distribution, this CMSIS folder contains only the 20 | Include sub-directory. The complete CMSIS-5 is available at: 21 | 22 | https://github.com/ARM-software/CMSIS_5 23 | 24 | -------------------------------------------------------------------------------- /3rd_party/README.txt: -------------------------------------------------------------------------------- 1 | About 3rd-Party Components 2 | ========================== 3 | This folder contains the Third-Party code used in the QP examples 4 | and is provided in this "3rd_party" folder only to demonstrate 5 | the use of the QP frameworks in conjunction with the Third-Party 6 | software components. 7 | 8 | 9 | Licensing Information 10 | ===================== 11 | Quantum Leaps, LLC expressly makes NO claims of ownership to any of the 12 | code in the "3rd_party" folder, even though some of the code might be 13 | customized or modified by Quantum Leaps. 14 | 15 | The Third-Party software components included in this "3rd_party" 16 | folder are licensed under a variety of different licensing terms that 17 | are defined by the respective owners of this software and are spelled 18 | out in the README.txt or LICENSE.txt files included in the respective 19 | sub-folders. 20 | 21 | 22 | Code Quality 23 | ============ 24 | The code in the "3rd_party" folder comes from various sources, and 25 | contains code of varying quality. Specifically, Quantum Leaps cannot 26 | take responsibility for the quality of the code in the "3rd_party" 27 | folder. 28 | 29 | *** 30 | NOTE: Some of the code in the "3rd_party" folder might cause compiler 31 | warnings. 32 | *** 33 | 34 | 35 | Disclaimer of Warranty 36 | ====================== 37 | QUANTUM LEAPS, LLC DOES NOT MAKE ANY WARRANTIES OF ANY KIND THAT THE 38 | THIRD-PARTY SOFTWARE DOES NOT OR WILL NOT INFRINGE ANY PATENT, TRADE 39 | SECRET, TRADEMARK, MASK WORK, OR OTHER INTELLECTUAL PROPERTY RIGHT 40 | OF ANY THIRD PARTY IN ANY COUNTRY. 41 | 42 | TO THE FULLEST EXTENT PERMITTED BY LAW, QUANTUM LEAPS, LLC DISCLAIMS 43 | ANY EXPRESS OR IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 44 | A PARTICULAR PURPOSE AND ALL OTHER WARRANTIES WITH RESPECT TO THE 45 | THIRD-PARTY SOFTWARE. THE ENTIRE RISK AS TO THE QUALITY OF THE 46 | THIRD-PARTY SOFTWARE IS WITH THE USER. 47 | 48 | 49 | Limitation of Liability 50 | ======================= 51 | UNDER NO CIRCUMSTANCES AND UNDER NO LEGAL THEORY, WHETHER IN TORT 52 | (INCLUDING NEGLIGENCE), CONTRACT, OR OTHERWISE, SHALL QUANTUM LEAPS, 53 | LLC BE LIABLE TO ANY PERSON FOR ANY INDIRECT, SPECIAL, INCIDENTAL, 54 | OR CONSEQUENTIAL DAMAGES OF ANY CHARACTER ARISING AS A RESULT OF 55 | THE USE OF THE THIRD-PART SOFTWARE INCLUDING, WITHOUT LIMITATION, 56 | DAMAGES FOR LOSS OF GOODWILL, LOSS OF PROFITS, WORK STOPPAGE, COMPUTER 57 | FAILURE OR MALFUNCTION, OR ANY AND ALL OTHER COMMERCIAL DAMAGES OR 58 | LOSSES. 59 | 60 | 61 | Contact Information: 62 | ==================== 63 | Quantum Leaps, LLC 64 | https://www.state-machine.com 65 | info@state-machine.com 66 | -------------------------------------------------------------------------------- /3rd_party/ek-tm4c123gxl/README.txt: -------------------------------------------------------------------------------- 1 | This directory contains the support code for the EK-TM4C123GXL board 2 | (TivaC LauchPad). 3 | 4 | The sub-directories contain code that is specific to the particular 5 | ARM toolchains, such as ARM (MDK-ARM), GCC, and IAR. 6 | 7 | 8 | CMSIS-Compliant Device Files 9 | ============================ 10 | The code also includes the CMSIS-compliant interface to the TM4C123GH6PM 11 | MCU files: 12 | 13 | TM4C123GH6PM.h 14 | system_TM4C123GH6PM.h 15 | system_TM4C123GH6PM.c 16 | arm\startup_TM4C123GH6PM.s 17 | gcc\startup_TM4C123GH6PM.c 18 | iar\startup_TM4C123GH6PM.s 19 | 20 | 21 | Adjusting the CPU Clock Speed 22 | ----------------------------- 23 | The current setting is to run at 50MHz from PLL, but the CPU clock speed 24 | can be modified by editing the file system_TM4C123GH6PM.c. 25 | -------------------------------------------------------------------------------- /3rd_party/ek-tm4c123gxl/gpio.h: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // 3 | // gpio.h - Defines and Macros for GPIO API. 4 | // 5 | // Copyright (c) 2005-2015 Texas Instruments Incorporated. All rights reserved. 6 | // Software License Agreement 7 | // 8 | // Redistribution and use in source and binary forms, with or without 9 | // modification, are permitted provided that the following conditions 10 | // are met: 11 | // 12 | // Redistributions of source code must retain the above copyright 13 | // notice, this list of conditions and the following disclaimer. 14 | // 15 | // Redistributions in binary form must reproduce the above copyright 16 | // notice, this list of conditions and the following disclaimer in the 17 | // documentation and/or other materials provided with the 18 | // distribution. 19 | // 20 | // Neither the name of Texas Instruments Incorporated nor the names of 21 | // its contributors may be used to endorse or promote products derived 22 | // from this software without specific prior written permission. 23 | // 24 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 | // 36 | // This is part of revision 2.1.2.111 of the Tiva Peripheral Driver Library. 37 | // 38 | //***************************************************************************** 39 | 40 | #ifndef __DRIVERLIB_GPIO_H__ 41 | #define __DRIVERLIB_GPIO_H__ 42 | 43 | //***************************************************************************** 44 | // 45 | // If building with a C++ compiler, make all of the definitions in this header 46 | // have a C binding. 47 | // 48 | //***************************************************************************** 49 | #ifdef __cplusplus 50 | extern "C" 51 | { 52 | #endif 53 | 54 | //***************************************************************************** 55 | // 56 | // The following values define the bit field for the ui8Pins argument to 57 | // several of the APIs. 58 | // 59 | //***************************************************************************** 60 | #define GPIO_PIN_0 0x00000001 // GPIO pin 0 61 | #define GPIO_PIN_1 0x00000002 // GPIO pin 1 62 | #define GPIO_PIN_2 0x00000004 // GPIO pin 2 63 | #define GPIO_PIN_3 0x00000008 // GPIO pin 3 64 | #define GPIO_PIN_4 0x00000010 // GPIO pin 4 65 | #define GPIO_PIN_5 0x00000020 // GPIO pin 5 66 | #define GPIO_PIN_6 0x00000040 // GPIO pin 6 67 | #define GPIO_PIN_7 0x00000080 // GPIO pin 7 68 | 69 | //***************************************************************************** 70 | // 71 | // Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and 72 | // returned from GPIODirModeGet. 73 | // 74 | //***************************************************************************** 75 | #define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input 76 | #define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output 77 | #define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function 78 | 79 | //***************************************************************************** 80 | // 81 | // Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter, 82 | // and returned from GPIOIntTypeGet. 83 | // 84 | //***************************************************************************** 85 | #define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge 86 | #define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge 87 | #define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges 88 | #define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level 89 | #define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level 90 | #define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins 91 | 92 | //***************************************************************************** 93 | // 94 | // Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter, 95 | // and returned by GPIOPadConfigGet in the *pui32Strength parameter. 96 | // 97 | //***************************************************************************** 98 | #define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength 99 | #define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength 100 | #define GPIO_STRENGTH_6MA 0x00000065 // 6mA drive strength 101 | #define GPIO_STRENGTH_8MA 0x00000066 // 8mA drive strength 102 | #define GPIO_STRENGTH_8MA_SC 0x0000006E // 8mA drive with slew rate control 103 | #define GPIO_STRENGTH_10MA 0x00000075 // 10mA drive strength 104 | #define GPIO_STRENGTH_12MA 0x00000077 // 12mA drive strength 105 | 106 | //***************************************************************************** 107 | // 108 | // Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter, 109 | // and returned by GPIOPadConfigGet in the *pui32PadType parameter. 110 | // 111 | //***************************************************************************** 112 | #define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull 113 | #define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up 114 | #define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down 115 | #define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain 116 | #define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator 117 | #define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208 // Hibernate wake, high 118 | #define GPIO_PIN_TYPE_WAKE_LOW 0x00000108 // Hibernate wake, low 119 | 120 | //***************************************************************************** 121 | // 122 | // Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions 123 | // in the ui32IntFlags parameter. 124 | // 125 | //***************************************************************************** 126 | #define GPIO_INT_PIN_0 0x00000001 127 | #define GPIO_INT_PIN_1 0x00000002 128 | #define GPIO_INT_PIN_2 0x00000004 129 | #define GPIO_INT_PIN_3 0x00000008 130 | #define GPIO_INT_PIN_4 0x00000010 131 | #define GPIO_INT_PIN_5 0x00000020 132 | #define GPIO_INT_PIN_6 0x00000040 133 | #define GPIO_INT_PIN_7 0x00000080 134 | #define GPIO_INT_DMA 0x00000100 135 | 136 | //***************************************************************************** 137 | // 138 | // Prototypes for the APIs. 139 | // 140 | //***************************************************************************** 141 | extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, 142 | uint32_t ui32PinIO); 143 | extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin); 144 | extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, 145 | uint32_t ui32IntType); 146 | extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin); 147 | extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, 148 | uint32_t ui32Strength, uint32_t ui32PadType); 149 | extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, 150 | uint32_t *pui32Strength, uint32_t *pui32PadType); 151 | extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags); 152 | extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags); 153 | extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked); 154 | extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags); 155 | extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)); 156 | extern void GPIOIntUnregister(uint32_t ui32Port); 157 | extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins); 158 | extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val); 159 | extern void GPIOPinConfigure(uint32_t ui32PinConfig); 160 | extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins); 161 | extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins); 162 | extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins); 163 | extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins); 164 | extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins); 165 | extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins); 166 | extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins); 167 | extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins); 168 | extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins); 169 | extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins); 170 | extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins); 171 | extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins); 172 | extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins); 173 | extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins); 174 | extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins); 175 | extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins); 176 | extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins); 177 | extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins); 178 | extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins); 179 | extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins); 180 | extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins); 181 | extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins); 182 | extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins); 183 | extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins); 184 | extern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins); 185 | extern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins); 186 | extern uint32_t GPIOPinWakeStatus(uint32_t ui32Port); 187 | extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); 188 | extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); 189 | extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); 190 | extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); 191 | 192 | //***************************************************************************** 193 | // 194 | // Mark the end of the C bindings section for C++ compilers. 195 | // 196 | //***************************************************************************** 197 | #ifdef __cplusplus 198 | } 199 | #endif 200 | 201 | #endif // __DRIVERLIB_GPIO_H__ 202 | -------------------------------------------------------------------------------- /3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_TM4C123GH6PM.h 3 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for 4 | * TI Tiva TM4C123 Class Devices 5 | * @version V3.1 6 | * @date 15. May 2013 7 | * 8 | * @note 9 | * Copyright (C) 2010-2011 ARM Limited. All rights reserved. 10 | * 11 | * @par 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M 13 | * processor based microcontrollers. This file can be freely distributed 14 | * within development tools that are supporting such ARM based processors. 15 | * 16 | * @par 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 22 | ******************************************************************************/ 23 | 24 | 25 | #ifndef SYSTEM_TM4C123_H 26 | #define SYSTEM_TM4C123_H 27 | 28 | #include 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 35 | 36 | 37 | /** 38 | * Initialize the system 39 | * 40 | * @param none 41 | * @return none 42 | * 43 | * @brief Setup the microcontroller system. 44 | * Initialize the System and update the SystemCoreClock variable. 45 | */ 46 | extern void SystemInit (void); 47 | 48 | /** 49 | * Update SystemCoreClock variable 50 | * 51 | * @param none 52 | * @return none 53 | * 54 | * @brief Updates the SystemCoreClock with current core Clock 55 | * retrieved from cpu registers. 56 | */ 57 | extern void SystemCoreClockUpdate (void); 58 | 59 | #ifdef __cplusplus 60 | } 61 | #endif 62 | 63 | #endif /* SYSTEM_TM4C123_H */ 64 | -------------------------------------------------------------------------------- /3rd_party/nucleo-c031c6/README.txt: -------------------------------------------------------------------------------- 1 | This directory contains embedded code for the STM32 NUCLEO-C031C6 2 | board. This code is then used to build ET tests for this board. 3 | See also the examples/ directory, make_nucleo-l152re makefiles. 4 | -------------------------------------------------------------------------------- /3rd_party/nucleo-c031c6/gnu/nucleo-c031c6.ld: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * Linker script for for STM32C031C6, GNU-ARM linker 3 | * 4 | * Q u a n t u m L e a P s 5 | * ------------------------ 6 | * Modern Embedded Software 7 | * 8 | * Copyright (C) 2005 Quantum Leaps, LLC . 9 | * 10 | * SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial 11 | * 12 | * This software is dual-licensed under the terms of the open source GNU 13 | * General Public License version 3 (or any later version), or alternatively, 14 | * under the terms of one of the closed source Quantum Leaps commercial 15 | * licenses. 16 | * 17 | * The terms of the open source GNU General Public License version 3 18 | * can be found at: 19 | * 20 | * The terms of the closed source Quantum Leaps commercial licenses 21 | * can be found at: 22 | * 23 | * Redistributions in source code must retain this top-level comment block. 24 | * Plagiarizing this software to sidestep the license obligations is illegal. 25 | * 26 | * Contact information: 27 | * 28 | * 29 | *****************************************************************************/ 30 | OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") 31 | OUTPUT_ARCH(arm) 32 | ENTRY(Reset_Handler) /* entry Point */ 33 | 34 | MEMORY { /* memory map of STM32C031C6 */ 35 | ROM (rx) : ORIGIN = 0x08000000, LENGTH = 32K 36 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 12K 37 | } 38 | 39 | /* The size of the stack used by the application. NOTE: you need to adjust */ 40 | STACK_SIZE = 2048; 41 | 42 | /* The size of the heap used by the application. NOTE: you need to adjust */ 43 | HEAP_SIZE = 0; 44 | 45 | SECTIONS { 46 | 47 | .isr_vector : { /* the vector table goes FIRST into ROM */ 48 | KEEP(*(.isr_vector)) /* vector table */ 49 | . = ALIGN(4); 50 | } >ROM 51 | 52 | .text : { /* code and constants */ 53 | . = ALIGN(4); 54 | *(.text) /* .text sections (code) */ 55 | *(.text*) /* .text* sections (code) */ 56 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 57 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 58 | 59 | KEEP (*(.init)) 60 | KEEP (*(.fini)) 61 | 62 | . = ALIGN(4); 63 | } >ROM 64 | 65 | .preinit_array : { 66 | PROVIDE_HIDDEN (__preinit_array_start = .); 67 | KEEP (*(.preinit_array*)) 68 | PROVIDE_HIDDEN (__preinit_array_end = .); 69 | } >ROM 70 | 71 | .init_array : { 72 | PROVIDE_HIDDEN (__init_array_start = .); 73 | KEEP (*(SORT(.init_array.*))) 74 | KEEP (*(.init_array*)) 75 | PROVIDE_HIDDEN (__init_array_end = .); 76 | } >ROM 77 | 78 | .fini_array : { 79 | PROVIDE_HIDDEN (__fini_array_start = .); 80 | KEEP (*(.fini_array*)) 81 | KEEP (*(SORT(.fini_array.*))) 82 | PROVIDE_HIDDEN (__fini_array_end = .); 83 | } >ROM 84 | 85 | _etext = .; /* global symbols at end of code */ 86 | 87 | .stack : { 88 | __stack_start__ = .; 89 | . = . + STACK_SIZE; 90 | . = ALIGN(4); 91 | __stack_end__ = .; 92 | } >RAM 93 | 94 | .data : AT (_etext) { 95 | __data_load = LOADADDR (.data); 96 | __data_start = .; 97 | *(.data) /* .data sections */ 98 | *(.data*) /* .data* sections */ 99 | . = ALIGN(4); 100 | __data_end__ = .; 101 | _edata = __data_end__; 102 | } >RAM 103 | 104 | .bss : { 105 | __bss_start__ = .; 106 | *(.bss) 107 | *(.bss*) 108 | *(COMMON) 109 | . = ALIGN(4); 110 | _ebss = .; /* define a global symbol at bss end */ 111 | __bss_end__ = .; 112 | } >RAM 113 | 114 | __exidx_start = .; 115 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM 116 | __exidx_end = .; 117 | 118 | PROVIDE ( end = _ebss ); 119 | PROVIDE ( _end = _ebss ); 120 | PROVIDE ( __end__ = _ebss ); 121 | 122 | .heap : { 123 | __heap_start__ = .; 124 | . = . + HEAP_SIZE; 125 | . = ALIGN(4); 126 | __heap_end__ = .; 127 | } >RAM 128 | 129 | /* Remove information from the standard libraries */ 130 | /DISCARD/ : { 131 | libc.a ( * ) 132 | libm.a ( * ) 133 | libgcc.a ( * ) 134 | } 135 | } 136 | -------------------------------------------------------------------------------- /3rd_party/nucleo-c031c6/iar/startup_stm32c031xx.s: -------------------------------------------------------------------------------- 1 | ;/***************************************************************************/ 2 | ; @file startup_stm32c031xx.s for IAR ARM assembler 3 | ; @brief CMSIS Cortex-M4F Core Device Startup File for stm32c031xx 4 | ; @version CMSIS 5.9.0 5 | ; @date 1 Feb 2023 6 | ; 7 | ; Modified by Quantum Leaps: 8 | ; - Added relocating of the Vector Table to free up the 256B region at 0x0 9 | ; for NULL-pointer protection by the MPU. 10 | ; - Modified all exception handlers to branch to assert_failed() 11 | ; instead of locking up the CPU inside an endless loop. 12 | ; * 13 | ; * @description 14 | ; * Created from the CMSIS template for the specified device 15 | ; * Quantum Leaps, www.state-machine.com 16 | ; * 17 | 18 | MODULE ?cstartup 19 | 20 | ; Forward declaration of sections. 21 | SECTION CSTACK:DATA:NOROOT(3) 22 | 23 | SECTION .intvec:CODE:NOROOT(8) 24 | 25 | PUBLIC __vector_table 26 | PUBLIC __Vectors 27 | PUBLIC __Vectors_End 28 | PUBLIC __Vectors_Size 29 | 30 | ;****************************************************************************** 31 | ; The vector table 32 | ; 33 | DATA 34 | __vector_table 35 | DCD sfe(CSTACK) 36 | DCD Reset_Handler ; Reset Handler 37 | DCD NMI_Handler ; NMI Handler 38 | DCD HardFault_Handler ; Hard Fault Handler 39 | DCD Default_Handler ; Reserved 40 | DCD Default_Handler ; Reserved 41 | DCD Default_Handler ; Reserved 42 | DCD Default_Handler ; Reserved 43 | DCD Default_Handler ; Reserved 44 | DCD Default_Handler ; Reserved 45 | DCD Default_Handler ; Reserved 46 | DCD SVC_Handler ; SVCall handler 47 | DCD DebugMon_Handler ; Debug Monitor handler 48 | DCD Default_Handler ; Reserved 49 | DCD PendSV_Handler ; PendSV handler 50 | DCD SysTick_Handler ; SysTick handler 51 | 52 | ; IRQ handlers... 53 | DCD WWDG_IRQHandler ; [ 0] Window Watchdog 54 | DCD Reserved1_IRQHandler ; [ 1] Reserved 55 | DCD RTC_IRQHandler ; [ 2] RTC through EXTI Line 56 | DCD FLASH_IRQHandler ; [ 3] FLASH 57 | DCD RCC_IRQHandler ; [ 4] RCC 58 | DCD EXTI0_1_IRQHandler ; [ 5] EXTI Line 0 and 1 59 | DCD EXTI2_3_IRQHandler ; [ 6] EXTI Line 2 and 3 60 | DCD EXTI4_15_IRQHandler ; [ 7] EXTI Line 4 to 15 61 | DCD Reserved8_IRQHandler ; [ 8] Reserved 62 | DCD DMA1_Channel1_IRQHandler ; [ 9] DMA1 Channel 1 63 | DCD DMA1_Channel2_3_IRQHandler ; [10] DMA1 Channel 2 and Channel 3 64 | DCD DMAMUX1_IRQHandler ; [11] DMAMUX 65 | DCD ADC1_IRQHandler ; [12] ADC1 66 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; [13] TIM1 Break, Update, Trigger and Commutation 67 | DCD TIM1_CC_IRQHandler ; [14] TIM1 Capture Compare 68 | DCD Reserved15_IRQHandler ; [15] Reserved 69 | DCD TIM3_IRQHandler ; [16] TIM3 70 | DCD Reserved17_IRQHandler ; [17] Reserved 71 | DCD Reserved18_IRQHandler ; [18] Reserved 72 | DCD TIM14_IRQHandler ; [19] TIM14 73 | DCD Reserved20_IRQHandler ; [20] Reserved 74 | DCD TIM16_IRQHandler ; [21] TIM16 75 | DCD TIM17_IRQHandler ; [22] TIM17 76 | DCD I2C1_IRQHandler ; [23] I2C1 77 | DCD Reserved24_IRQHandler ; [24] Reserved 78 | DCD SPI1_IRQHandler ; [25] SPI1 79 | DCD Reserved26_IRQHandler ; [26] Reserved 80 | DCD USART1_IRQHandler ; [27] USART1 81 | DCD USART2_IRQHandler ; [28] USART2 82 | DCD Reserved29_IRQHandler ; [29] Reserved 83 | DCD Reserved30_IRQHandler ; [30] Reserved 84 | DCD Reserved31_IRQHandler ; [31] Reserved 85 | 86 | __Vectors_End 87 | 88 | __Vectors EQU __vector_table 89 | __Vectors_Size EQU __Vectors_End - __Vectors 90 | 91 | 92 | ;****************************************************************************** 93 | ; This is the code for exception handlers. 94 | ; 95 | SECTION .text:CODE:REORDER:NOROOT(2) 96 | 97 | ;****************************************************************************** 98 | ; This is the code that gets called when the CPU first starts execution 99 | ; following a reset event. 100 | ; 101 | PUBWEAK Reset_Handler 102 | EXTERN SystemInit 103 | EXTERN __iar_program_start 104 | EXTERN assert_failed 105 | 106 | Reset_Handler 107 | LDR r0,=SystemInit ; CMSIS system initialization 108 | BLX r0 109 | 110 | ; pre-fill the CSTACK with 0xDEADBEEF................... 111 | LDR r0,=0xDEADBEEF 112 | MOV r1,r0 113 | LDR r2,=sfb(CSTACK) 114 | LDR r3,=sfe(CSTACK) 115 | Reset_stackInit_fill: 116 | STMIA r2!,{r0,r1} 117 | CMP r2,r3 118 | BLT.N Reset_stackInit_fill 119 | 120 | LDR r0,=__iar_program_start ; IAR startup code 121 | BLX r0 122 | 123 | ; __iar_program_start calls the main() function, which should not return, 124 | ; but just in case jump to assert_failed() if main returns. 125 | CPSID i ; disable all interrupts 126 | LDR r0,=str_EXIT 127 | MOVS r1,#1 128 | LDR r2,=sfe(CSTACK) ; re-set the SP in case of stack overflow 129 | MOV sp,r2 130 | LDR r2,=assert_failed 131 | BX r2 132 | str_EXIT 133 | DCB "EXIT" 134 | ALIGNROM 2 135 | 136 | ;****************************************************************************** 137 | PUBWEAK NMI_Handler 138 | NMI_Handler 139 | CPSID i ; disable all interrupts 140 | LDR r0,=str_NMI 141 | MOVS r1,#1 142 | LDR r2,=sfe(CSTACK) ; re-set the SP in case of stack overflow 143 | MOV sp,r2 144 | LDR r2,=assert_failed 145 | BX r2 146 | str_NMI 147 | DCB "NMI" 148 | ALIGNROM 2 149 | 150 | ;****************************************************************************** 151 | PUBWEAK HardFault_Handler 152 | HardFault_Handler 153 | CPSID i ; disable all interrupts 154 | LDR r0,=str_HardFault 155 | MOVS r1,#1 156 | LDR r2,=sfe(CSTACK) ; re-set the SP in case of stack overflow 157 | MOV sp,r2 158 | LDR r2,=assert_failed 159 | BX r2 160 | str_HardFault 161 | DCB "HardFault" 162 | ALIGNROM 2 163 | 164 | 165 | ;****************************************************************************** 166 | ; 167 | ; Weak non-fault handlers... 168 | ; 169 | 170 | ;****************************************************************************** 171 | PUBWEAK SVC_Handler 172 | SVC_Handler 173 | CPSID i ; disable all interrupts 174 | LDR r0,=str_SVC 175 | MOVS r1,#1 176 | LDR r2,=sfe(CSTACK) ; re-set the SP in case of stack overflow 177 | MOV sp,r2 178 | LDR r2,=assert_failed 179 | BX r2 180 | str_SVC 181 | DCB "SVC" 182 | ALIGNROM 2 183 | 184 | ;****************************************************************************** 185 | PUBWEAK DebugMon_Handler 186 | DebugMon_Handler 187 | CPSID i ; disable all interrupts 188 | LDR r0,=str_DebugMon 189 | MOVS r1,#1 190 | LDR r2,=sfe(CSTACK) ; re-set the SP in case of stack overflow 191 | MOV sp,r2 192 | LDR r2,=assert_failed 193 | BX r2 194 | str_DebugMon 195 | DCB "DebugMon" 196 | ALIGNROM 2 197 | 198 | ;****************************************************************************** 199 | PUBWEAK PendSV_Handler 200 | PendSV_Handler 201 | CPSID i ; disable all interrupts 202 | LDR r0,=str_PendSV 203 | MOVS r1,#1 204 | LDR r2,=sfe(CSTACK) ; re-set the SP in case of stack overflow 205 | MOV sp,r2 206 | LDR r2,=assert_failed 207 | BX r2 208 | str_PendSV 209 | DCB "PendSV" 210 | ALIGNROM 2 211 | 212 | ;****************************************************************************** 213 | PUBWEAK SysTick_Handler 214 | SysTick_Handler 215 | CPSID i ; disable all interrupts 216 | LDR r0,=str_SysTick 217 | MOVS r1,#1 218 | LDR r2,=sfe(CSTACK) ; re-set the SP in case of stack overflow 219 | MOV sp,r2 220 | LDR r2,=assert_failed 221 | BX r2 222 | str_SysTick 223 | DCB "SysTick" 224 | ALIGNROM 2 225 | 226 | ;****************************************************************************** 227 | ; Weak IRQ handlers... 228 | ; 229 | PUBWEAK Default_Handler 230 | PUBWEAK WWDG_IRQHandler 231 | PUBWEAK RTC_IRQHandler 232 | PUBWEAK FLASH_IRQHandler 233 | PUBWEAK RCC_IRQHandler 234 | PUBWEAK EXTI0_1_IRQHandler 235 | PUBWEAK EXTI2_3_IRQHandler 236 | PUBWEAK EXTI4_15_IRQHandler 237 | PUBWEAK DMA1_Channel1_IRQHandler 238 | PUBWEAK DMA1_Channel2_3_IRQHandler 239 | PUBWEAK DMAMUX1_IRQHandler 240 | PUBWEAK ADC1_IRQHandler 241 | PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler 242 | PUBWEAK TIM1_CC_IRQHandler 243 | PUBWEAK TIM3_IRQHandler 244 | PUBWEAK TIM14_IRQHandler 245 | PUBWEAK TIM16_IRQHandler 246 | PUBWEAK TIM17_IRQHandler 247 | PUBWEAK I2C1_IRQHandler 248 | PUBWEAK SPI1_IRQHandler 249 | PUBWEAK USART1_IRQHandler 250 | PUBWEAK USART2_IRQHandler 251 | PUBWEAK Reserved1_IRQHandler 252 | PUBWEAK Reserved8_IRQHandler 253 | PUBWEAK Reserved15_IRQHandler 254 | PUBWEAK Reserved17_IRQHandler 255 | PUBWEAK Reserved18_IRQHandler 256 | PUBWEAK Reserved20_IRQHandler 257 | PUBWEAK Reserved24_IRQHandler 258 | PUBWEAK Reserved26_IRQHandler 259 | PUBWEAK Reserved29_IRQHandler 260 | PUBWEAK Reserved30_IRQHandler 261 | PUBWEAK Reserved31_IRQHandler 262 | 263 | Default_Handler 264 | WWDG_IRQHandler 265 | RTC_IRQHandler 266 | FLASH_IRQHandler 267 | RCC_IRQHandler 268 | EXTI0_1_IRQHandler 269 | EXTI2_3_IRQHandler 270 | EXTI4_15_IRQHandler 271 | DMA1_Channel1_IRQHandler 272 | DMA1_Channel2_3_IRQHandler 273 | DMAMUX1_IRQHandler 274 | ADC1_IRQHandler 275 | TIM1_BRK_UP_TRG_COM_IRQHandler 276 | TIM1_CC_IRQHandler 277 | TIM3_IRQHandler 278 | TIM14_IRQHandler 279 | TIM16_IRQHandler 280 | TIM17_IRQHandler 281 | I2C1_IRQHandler 282 | SPI1_IRQHandler 283 | USART1_IRQHandler 284 | USART2_IRQHandler 285 | Reserved1_IRQHandler 286 | Reserved8_IRQHandler 287 | Reserved15_IRQHandler 288 | Reserved17_IRQHandler 289 | Reserved18_IRQHandler 290 | Reserved20_IRQHandler 291 | Reserved24_IRQHandler 292 | Reserved26_IRQHandler 293 | Reserved29_IRQHandler 294 | Reserved30_IRQHandler 295 | Reserved31_IRQHandler 296 | CPSID i ; disable all interrupts 297 | LDR r0,=str_Undefined 298 | MOVS r1,#1 299 | LDR r2,=sfe(CSTACK) ; re-set the SP in case of stack overflow 300 | MOV sp,r2 301 | LDR r2,=assert_failed 302 | BX r2 303 | str_Undefined 304 | DCB "Undefined" 305 | ALIGNROM 2 306 | 307 | END ; end of module 308 | 309 | -------------------------------------------------------------------------------- /3rd_party/nucleo-c031c6/qutest/qutest.ld: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * Linker script for for STM32C031C6, GNU-ARM linker 3 | * 4 | * Q u a n t u m L e a P s 5 | * ------------------------ 6 | * Modern Embedded Software 7 | * 8 | * Copyright (C) 2005 Quantum Leaps, LLC . 9 | * 10 | * SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial 11 | * 12 | * This software is dual-licensed under the terms of the open source GNU 13 | * General Public License version 3 (or any later version), or alternatively, 14 | * under the terms of one of the closed source Quantum Leaps commercial 15 | * licenses. 16 | * 17 | * The terms of the open source GNU General Public License version 3 18 | * can be found at: 19 | * 20 | * The terms of the closed source Quantum Leaps commercial licenses 21 | * can be found at: 22 | * 23 | * Redistributions in source code must retain this top-level comment block. 24 | * Plagiarizing this software to sidestep the license obligations is illegal. 25 | * 26 | * Contact information: 27 | * 28 | * 29 | *****************************************************************************/ 30 | OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") 31 | OUTPUT_ARCH(arm) 32 | ENTRY(Reset_Handler) /* entry Point */ 33 | 34 | MEMORY { /* memory map of STM32C031C6 */ 35 | ROM (rx) : ORIGIN = 0x08000000, LENGTH = 32K 36 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 12K 37 | } 38 | 39 | /* The size of the stack used by the application. NOTE: you need to adjust */ 40 | STACK_SIZE = 2048; 41 | 42 | /* The size of the heap used by the application. NOTE: you need to adjust */ 43 | HEAP_SIZE = 0; 44 | 45 | SECTIONS { 46 | 47 | .isr_vector : { /* the vector table goes FIRST into ROM */ 48 | KEEP(*(.isr_vector)) /* vector table */ 49 | . = ALIGN(4); 50 | } >ROM 51 | 52 | .text : { /* code and constants */ 53 | . = ALIGN(4); 54 | *(.text) /* .text sections (code) */ 55 | *(.text*) /* .text* sections (code) */ 56 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 57 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 58 | 59 | KEEP (*(.init)) 60 | KEEP (*(.fini)) 61 | 62 | . = ALIGN(4); 63 | } >ROM 64 | 65 | .preinit_array : { 66 | PROVIDE_HIDDEN (__preinit_array_start = .); 67 | KEEP (*(.preinit_array*)) 68 | PROVIDE_HIDDEN (__preinit_array_end = .); 69 | } >ROM 70 | 71 | .init_array : { 72 | PROVIDE_HIDDEN (__init_array_start = .); 73 | KEEP (*(SORT(.init_array.*))) 74 | KEEP (*(.init_array*)) 75 | PROVIDE_HIDDEN (__init_array_end = .); 76 | } >ROM 77 | 78 | .fini_array : { 79 | PROVIDE_HIDDEN (__fini_array_start = .); 80 | KEEP (*(.fini_array*)) 81 | KEEP (*(SORT(.fini_array.*))) 82 | PROVIDE_HIDDEN (__fini_array_end = .); 83 | } >ROM 84 | 85 | _etext = .; /* global symbols at end of code */ 86 | 87 | .stack : { 88 | __stack_start__ = .; 89 | . = . + STACK_SIZE; 90 | . = ALIGN(4); 91 | __stack_end__ = .; 92 | } >RAM 93 | 94 | .data : AT (_etext) { 95 | __data_load = LOADADDR (.data); 96 | __data_start = .; 97 | *(.data) /* .data sections */ 98 | *(.data*) /* .data* sections */ 99 | . = ALIGN(4); 100 | __data_end__ = .; 101 | _edata = __data_end__; 102 | } >RAM 103 | 104 | .bss : { 105 | __bss_start__ = .; 106 | *(.bss) 107 | *(.bss*) 108 | *(COMMON) 109 | . = ALIGN(4); 110 | _ebss = .; /* define a global symbol at bss end */ 111 | __bss_end__ = .; 112 | } >RAM 113 | 114 | __exidx_start = .; 115 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM 116 | __exidx_end = .; 117 | 118 | PROVIDE ( end = _ebss ); 119 | PROVIDE ( _end = _ebss ); 120 | PROVIDE ( __end__ = _ebss ); 121 | 122 | .heap : { 123 | __heap_start__ = .; 124 | . = . + HEAP_SIZE; 125 | . = ALIGN(4); 126 | __heap_end__ = .; 127 | } >RAM 128 | 129 | /* Remove information from the standard libraries */ 130 | /DISCARD/ : { 131 | libc.a ( * ) 132 | libm.a ( * ) 133 | libgcc.a ( * ) 134 | } 135 | } 136 | -------------------------------------------------------------------------------- /3rd_party/nucleo-c031c6/qutest/qutest_cpp.cpp: -------------------------------------------------------------------------------- 1 | //============================================================================ 2 | // Product: QUTEST port for STM32 NUCLEO-C031C6 board 3 | // Last updated for version 7.3.2 4 | // Last updated on 2023-12-13 5 | // 6 | // Q u a n t u m L e a P s 7 | // ------------------------ 8 | // Modern Embedded Software 9 | // 10 | // Copyright (C) 2005 Quantum Leaps, LLC. 11 | // 12 | // SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial 13 | // 14 | // This software is dual-licensed under the terms of the open source GNU 15 | // General Public License version 3 (or any later version), or alternatively, 16 | // under the terms of one of the closed source Quantum Leaps commercial 17 | // licenses. 18 | // 19 | // The terms of the open source GNU General Public License version 3 20 | // can be found at: 21 | // 22 | // The terms of the closed source Quantum Leaps commercial licenses 23 | // can be found at: 24 | // 25 | // Redistributions in source code must retain this top-level comment block. 26 | // Plagiarizing this software to sidestep the license obligations is illegal. 27 | // 28 | // Contact information: 29 | // 30 | // 31 | //============================================================================ 32 | #ifndef Q_SPY 33 | #error "Q_SPY must be defined to compile qutest_cpp.cpp" 34 | #endif // Q_SPY 35 | 36 | #define QP_IMPL // this is QP implementation 37 | #include "qp_port.hpp" // QP port 38 | #include "qs_port.hpp" // QS port 39 | #include "qs_pkg.hpp" // QS package-scope interface 40 | #include "qsafe.h" // QP Functional Safety (FuSa) Subsystem 41 | 42 | #include "stm32c0xx.h" // CMSIS-compliant header file for the MCU used 43 | // add other drivers if necessary... 44 | 45 | //Q_DEFINE_THIS_MODULE("qutest_port") 46 | 47 | using namespace QP; 48 | 49 | // Local-scope defines ------------------------------------------------------- 50 | // LED pins available on the board (just one user LED LD4--Green on PA.5) 51 | #define LD4_PIN 5U 52 | 53 | // Button pins available on the board (just one user Button B1 on PC.13) 54 | #define B1_PIN 13U 55 | 56 | static uint16_t const UARTPrescTable[12] = { 57 | 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U 58 | }; 59 | 60 | #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ 61 | ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) \ 62 | + ((__BAUD__)/2U)) / (__BAUD__)) 63 | 64 | #define UART_PRESCALER_DIV1 0U 65 | 66 | // USART2 pins PA.2 and PA.3 67 | #define USART2_TX_PIN 2U 68 | #define USART2_RX_PIN 3U 69 | 70 | //............................................................................ 71 | extern "C" { 72 | 73 | // ISR for receiving bytes from the QSPY Back-End 74 | // NOTE: This ISR is "QF-unaware" meaning that it does not interact with 75 | // the QF/QK and is not disabled. Such ISRs don't need to call QK_ISR_ENTRY/ 76 | // QK_ISR_EXIT and they cannot post or publish events. 77 | void USART2_IRQHandler(void); // prototype 78 | void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrupt) 79 | // is RX register NOT empty? 80 | while ((USART2->ISR & (1U << 5U)) != 0U) { 81 | std::uint32_t b = USART2->RDR; 82 | QP::QS::rxPut(b); 83 | } 84 | } 85 | 86 | //............................................................................ 87 | void assert_failed(char const * const module, int_t const id); // prototype 88 | void assert_failed(char const * const module, int_t const id) { 89 | Q_onError(module, id); 90 | } 91 | 92 | } // extern "C" 93 | 94 | // QS callbacks ============================================================== 95 | bool QS::onStartup(void const *arg) { 96 | Q_UNUSED_PAR(arg); 97 | 98 | static std::uint8_t qsTxBuf[2*1024]; // buffer for QS-TX channel 99 | initBuf (qsTxBuf, sizeof(qsTxBuf)); 100 | 101 | static std::uint8_t qsRxBuf[256]; // buffer for QS-RX channel 102 | rxInitBuf(qsRxBuf, sizeof(qsRxBuf)); 103 | 104 | // NOTE: SystemInit() already called from the startup code 105 | // but SystemCoreClock needs to be updated 106 | SystemCoreClockUpdate(); 107 | 108 | // enable GPIOA clock port for the LED LD4 109 | RCC->IOPENR |= (1U << 0U); 110 | 111 | // set all used GPIOA pins as push-pull output, no pull-up, pull-down 112 | GPIOA->MODER &= ~(3U << 2U*LD4_PIN); 113 | GPIOA->MODER |= (1U << 2U*LD4_PIN); 114 | GPIOA->OTYPER &= ~(1U << LD4_PIN); 115 | GPIOA->OSPEEDR &= ~(3U << 2U*LD4_PIN); 116 | GPIOA->OSPEEDR |= (1U << 2U*LD4_PIN); 117 | GPIOA->PUPDR &= ~(3U << 2U*LD4_PIN); 118 | 119 | // enable GPIOC clock port for the Button B1 120 | RCC->IOPENR |= (1U << 2U); 121 | 122 | // configure Button B1 pin on GPIOC as input, no pull-up, pull-down 123 | GPIOC->MODER &= ~(3U << 2U*B1_PIN); 124 | GPIOC->PUPDR &= ~(3U << 2U*B1_PIN); 125 | 126 | // enable peripheral clock for USART2 127 | RCC->IOPENR |= ( 1U << 0U); // Enable GPIOA clock for USART pins 128 | RCC->APBENR1 |= ( 1U << 17U); // Enable USART#2 clock 129 | 130 | // Configure PA to USART2_RX, PA to USART2_TX 131 | GPIOA->AFR[0] &= ~((15U << 4U*USART2_RX_PIN) | (15U << 4U*USART2_TX_PIN)); 132 | GPIOA->AFR[0] |= (( 1U << 4U*USART2_RX_PIN) | ( 1U << 4U*USART2_TX_PIN)); 133 | GPIOA->MODER &= ~(( 3U << 2U*USART2_RX_PIN) | ( 3U << 2U*USART2_TX_PIN)); 134 | GPIOA->MODER |= (( 2U << 2U*USART2_RX_PIN) | ( 2U << 2U*USART2_TX_PIN)); 135 | 136 | // baud rate 137 | USART2->BRR = UART_DIV_SAMPLING16( 138 | SystemCoreClock, 115200U, UART_PRESCALER_DIV1); 139 | USART2->CR3 = 0x0000U | // no flow control 140 | (1U << 12U); // disable overrun detection (OVRDIS) 141 | USART2->CR2 = 0x0000U; // 1 stop bit 142 | USART2->CR1 = ((1U << 2U) | // enable RX 143 | (1U << 3U) | // enable TX 144 | (1U << 5U) | // enable RX interrupt 145 | (0U << 12U) | // 8 data bits 146 | (0U << 28U) | // 8 data bits 147 | (1U << 0U)); // enable USART 148 | 149 | // explicitly set NVIC priorities of all Cortex-M interrupts used 150 | NVIC_SetPriorityGrouping(0U); 151 | NVIC_SetPriority(USART2_IRQn, 0U); 152 | 153 | // enable the UART RX interrupt... 154 | NVIC_EnableIRQ(USART2_IRQn); // UART2 interrupt used for QS-RX 155 | 156 | return true; // success 157 | } 158 | //............................................................................ 159 | void QS::onCleanup(void) { 160 | // wait as long as the UART is busy 161 | while ((USART2->ISR & (1U << 7U)) == 0U) { 162 | } 163 | // delay before returning to allow all produced QS bytes to be received 164 | for (std::uint32_t volatile dly_ctr = 10000U; dly_ctr > 0U; --dly_ctr) { 165 | } 166 | } 167 | //............................................................................ 168 | // NOTE: 169 | // No critical section in QS::onFlush() to avoid nesting of critical sections 170 | // in case QS_onFlush() is called from Q_onError(). 171 | void QS::onFlush(void) { 172 | for (;;) { 173 | std::uint16_t b = getByte(); 174 | if (b != QS_EOD) { 175 | while ((USART2->ISR & (1U << 7U)) == 0U) { 176 | } 177 | USART2->TDR = static_cast(b); // put into the DR register 178 | } 179 | else { 180 | break; 181 | } 182 | } 183 | } 184 | //............................................................................ 185 | //! callback function to reset the target (to be implemented in the BSP) 186 | void QS::onReset(void) { 187 | NVIC_SystemReset(); 188 | } 189 | //............................................................................ 190 | void QS::doOutput(void) { 191 | if ((USART2->ISR & (1U << 7U)) != 0U) { // is TXE empty? 192 | QF_INT_DISABLE(); 193 | std::uint16_t b = getByte(); 194 | QF_INT_ENABLE(); 195 | 196 | if (b != QS_EOD) { // not End-Of-Data? 197 | USART2->TDR = static_cast(b); 198 | } 199 | } 200 | } 201 | //............................................................................ 202 | void QS::onTestLoop() { 203 | rxPriv_.inTestLoop = true; 204 | while (rxPriv_.inTestLoop) { 205 | 206 | // toggle an LED LD2 on and then off (not enough LEDs, see NOTE02) 207 | GPIOA->BSRR = (1U << LD4_PIN); // turn LED[n] on 208 | GPIOA->BSRR = (1U << (LD4_PIN + 16U)); // turn LED[n] off 209 | 210 | rxParse(); // parse all the received bytes 211 | 212 | if ((USART2->ISR & (1U << 7U)) != 0U) { // is TXE empty? 213 | QF_INT_DISABLE(); 214 | uint16_t b = getByte(); 215 | QF_INT_ENABLE(); 216 | 217 | if (b != QS_EOD) { // not End-Of-Data? 218 | USART2->TDR = static_cast(b); 219 | } 220 | } 221 | } 222 | // set inTestLoop to true in case calls to QS_onTestLoop() nest, 223 | // which can happen through the calls to QS_TEST_PAUSE(). 224 | rxPriv_.inTestLoop = true; 225 | } 226 | //============================================================================ 227 | // NOTE0: 228 | // ARM Cortex-M0+ does NOT provide "kernel-unaware" interrupts, and 229 | // consequently *all* interrupts are "kernel-aware". This means that 230 | // the UART interrupt used for QS-RX is frequently DISABLED (e.g., to 231 | // perform QS-TX). That can lead to lost some of the received bytes, and 232 | // consequently some QUTest tests might be failing. 233 | // A fix for that would be to use DMA for handling QS-RX, but this is 234 | // currently not implemented. 235 | // 236 | -------------------------------------------------------------------------------- /3rd_party/nucleo-c031c6/qutest/qutest_port.c: -------------------------------------------------------------------------------- 1 | //============================================================================ 2 | // Product: QUTEST port for NUCLEO-C031C6 board 3 | // Last updated for version 7.3.2 4 | // Last updated on 2023-12-13 5 | // 6 | // Q u a n t u m L e a P s 7 | // ------------------------ 8 | // Modern Embedded Software 9 | // 10 | // Copyright (C) 2005 Quantum Leaps, LLC. 11 | // 12 | // SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial 13 | // 14 | // This software is dual-licensed under the terms of the open source GNU 15 | // General Public License version 3 (or any later version), or alternatively, 16 | // under the terms of one of the closed source Quantum Leaps commercial 17 | // licenses. 18 | // 19 | // The terms of the open source GNU General Public License version 3 20 | // can be found at: 21 | // 22 | // The terms of the closed source Quantum Leaps commercial licenses 23 | // can be found at: 24 | // 25 | // Redistributions in source code must retain this top-level comment block. 26 | // Plagiarizing this software to sidestep the license obligations is illegal. 27 | // 28 | // Contact information: 29 | // 30 | // 31 | //============================================================================ 32 | #ifndef Q_SPY 33 | #error "Q_SPY must be defined to compile qutest_port.c" 34 | #endif // Q_SPY 35 | 36 | #define QP_IMPL // this is QP implementation 37 | #include "qp_port.h" // QP port 38 | #include "qsafe.h" // QP Functional Safety (FuSa) Subsystem 39 | #include "qs_port.h" // QS port 40 | #include "qs_pkg.h" // QS package-scope interface 41 | 42 | #include "stm32c0xx.h" // CMSIS-compliant header file for the MCU used 43 | // add other drivers if necessary... 44 | 45 | //Q_DEFINE_THIS_MODULE("qutest_port") 46 | 47 | // Local-scope defines ------------------------------------------------------- 48 | // LED pins available on the board (just one user LED LD4--Green on PA.5) 49 | #define LD4_PIN 5U 50 | 51 | // Button pins available on the board (just one user Button B1 on PC.13) 52 | #define B1_PIN 13U 53 | 54 | static uint16_t const UARTPrescTable[12] = { 55 | 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U 56 | }; 57 | 58 | #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ 59 | ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) \ 60 | + ((__BAUD__)/2U)) / (__BAUD__)) 61 | 62 | #define UART_PRESCALER_DIV1 0U 63 | 64 | // USART2 pins PA.2 and PA.3 65 | #define USART2_TX_PIN 2U 66 | #define USART2_RX_PIN 3U 67 | 68 | //............................................................................ 69 | // ISR for receiving bytes from the QSPY Back-End 70 | // NOTE: This ISR is "QF-unaware" meaning that it does not interact with 71 | // the QF/QK and is not disabled. Such ISRs don't need to call QK_ISR_ENTRY/ 72 | // QK_ISR_EXIT and they cannot post or publish events. 73 | void USART2_IRQHandler(void); // prototype 74 | void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrupt) 75 | // is RX register NOT empty? 76 | while ((USART2->ISR & (1U << 5U)) != 0U) { 77 | uint32_t b = USART2->RDR; 78 | QS_RX_PUT(b); 79 | } 80 | } 81 | 82 | //............................................................................ 83 | void assert_failed(char const * const module, int_t const id); // prototype 84 | void assert_failed(char const * const module, int_t const id) { 85 | Q_onError(module, id); 86 | } 87 | 88 | // QS callbacks ============================================================== 89 | uint8_t QS_onStartup(void const *arg) { 90 | Q_UNUSED_PAR(arg); 91 | 92 | static uint8_t qsTxBuf[2*1024]; // buffer for QS-TX channel 93 | QS_initBuf (qsTxBuf, sizeof(qsTxBuf)); 94 | 95 | static uint8_t qsRxBuf[256]; // buffer for QS-RX channel 96 | QS_rxInitBuf(qsRxBuf, sizeof(qsRxBuf)); 97 | 98 | // NOTE: SystemInit() already called from the startup code 99 | // but SystemCoreClock needs to be updated 100 | SystemCoreClockUpdate(); 101 | 102 | // enable GPIOA clock port for the LED LD4 103 | RCC->IOPENR |= (1U << 0U); 104 | 105 | // set all used GPIOA pins as push-pull output, no pull-up, pull-down 106 | GPIOA->MODER &= ~(3U << 2U*LD4_PIN); 107 | GPIOA->MODER |= (1U << 2U*LD4_PIN); 108 | GPIOA->OTYPER &= ~(1U << LD4_PIN); 109 | GPIOA->OSPEEDR &= ~(3U << 2U*LD4_PIN); 110 | GPIOA->OSPEEDR |= (1U << 2U*LD4_PIN); 111 | GPIOA->PUPDR &= ~(3U << 2U*LD4_PIN); 112 | 113 | // enable GPIOC clock port for the Button B1 114 | RCC->IOPENR |= (1U << 2U); 115 | 116 | // configure Button B1 pin on GPIOC as input, no pull-up, pull-down 117 | GPIOC->MODER &= ~(3U << 2U*B1_PIN); 118 | GPIOC->PUPDR &= ~(3U << 2U*B1_PIN); 119 | 120 | // enable peripheral clock for USART2 121 | RCC->IOPENR |= ( 1U << 0U); // Enable GPIOA clock for USART pins 122 | RCC->APBENR1 |= ( 1U << 17U); // Enable USART#2 clock 123 | 124 | // Configure PA to USART2_RX, PA to USART2_TX 125 | GPIOA->AFR[0] &= ~((15U << 4U*USART2_RX_PIN) | (15U << 4U*USART2_TX_PIN)); 126 | GPIOA->AFR[0] |= (( 1U << 4U*USART2_RX_PIN) | ( 1U << 4U*USART2_TX_PIN)); 127 | GPIOA->MODER &= ~(( 3U << 2U*USART2_RX_PIN) | ( 3U << 2U*USART2_TX_PIN)); 128 | GPIOA->MODER |= (( 2U << 2U*USART2_RX_PIN) | ( 2U << 2U*USART2_TX_PIN)); 129 | 130 | // baud rate 131 | USART2->BRR = UART_DIV_SAMPLING16( 132 | SystemCoreClock, 115200U, UART_PRESCALER_DIV1); 133 | USART2->CR3 = 0x0000U | // no flow control 134 | (1U << 12U); // disable overrun detection (OVRDIS) 135 | USART2->CR2 = 0x0000U; // 1 stop bit 136 | USART2->CR1 = ((1U << 2U) | // enable RX 137 | (1U << 3U) | // enable TX 138 | (1U << 5U) | // enable RX interrupt 139 | (0U << 12U) | // 8 data bits 140 | (0U << 28U) | // 8 data bits 141 | (1U << 0U)); // enable USART 142 | 143 | // explicitly set NVIC priorities of all Cortex-M interrupts used 144 | NVIC_SetPriorityGrouping(0U); 145 | NVIC_SetPriority(USART2_IRQn, 0U); 146 | 147 | // enable the UART RX interrupt... 148 | NVIC_EnableIRQ(USART2_IRQn); // UART2 interrupt used for QS-RX 149 | 150 | return 1U; // return success 151 | } 152 | //............................................................................ 153 | void QS_onCleanup(void) { 154 | // wait as long as the UART is busy 155 | while ((USART2->ISR & (1U << 7U)) == 0U) { 156 | } 157 | // delay before returning to allow all produced QS bytes to be received 158 | for (uint32_t volatile dly_ctr = 10000U; dly_ctr > 0U; --dly_ctr) { 159 | } 160 | } 161 | //............................................................................ 162 | // NOTE: 163 | // No critical section in QS_onFlush() to avoid nesting of critical sections 164 | // in case QS_onFlush() is called from Q_onError(). 165 | void QS_onFlush(void) { 166 | for (;;) { 167 | uint16_t b = QS_getByte(); 168 | if (b != QS_EOD) { 169 | while ((USART2->ISR & (1U << 7U)) == 0U) { 170 | } 171 | USART2->TDR = (uint8_t)b; 172 | } 173 | else { 174 | break; 175 | } 176 | } 177 | } 178 | //............................................................................ 179 | // callback function to reset the target (to be implemented in the BSP) 180 | void QS_onReset(void) { 181 | NVIC_SystemReset(); 182 | } 183 | //............................................................................ 184 | void QS_doOutput(void) { 185 | if ((USART2->ISR & (1U << 7U)) != 0U) { // is TXE empty? 186 | QF_INT_DISABLE(); 187 | uint16_t b = QS_getByte(); 188 | QF_INT_ENABLE(); 189 | 190 | if (b != QS_EOD) { // not End-Of-Data? 191 | USART2->TDR = (uint8_t)b; 192 | } 193 | } 194 | } 195 | //............................................................................ 196 | void QS_onTestLoop() { 197 | QS_rxPriv_.inTestLoop = true; 198 | while (QS_rxPriv_.inTestLoop) { 199 | 200 | // toggle an LED LD2 on and then off (not enough LEDs, see NOTE02) 201 | GPIOA->BSRR = (1U << LD4_PIN); // turn LED[n] on 202 | GPIOA->BSRR = (1U << (LD4_PIN + 16U)); // turn LED[n] off 203 | 204 | QS_rxParse(); // parse all the received bytes 205 | 206 | if ((USART2->ISR & (1U << 7U)) != 0U) { // is TXE empty? 207 | QF_INT_DISABLE(); 208 | uint16_t b = QS_getByte(); 209 | QF_INT_ENABLE(); 210 | 211 | if (b != QS_EOD) { // not End-Of-Data? 212 | USART2->TDR = (uint8_t)b; 213 | } 214 | } 215 | } 216 | // set inTestLoop to true in case calls to QS_onTestLoop() nest, 217 | // which can happen through the calls to QS_TEST_PAUSE(). 218 | QS_rxPriv_.inTestLoop = true; 219 | } 220 | //============================================================================ 221 | // NOTE0: 222 | // ARM Cortex-M0+ does NOT provide "kernel-unaware" interrupts, and 223 | // consequently *all* interrupts are "kernel-aware". This means that 224 | // the UART interrupt used for QS-RX is frequently DISABLED (e.g., to 225 | // perform QS-TX). That can lead to lost some of the received bytes, and 226 | // consequently some QUTest tests might be failing. 227 | // A fix for that would be to use DMA for handling QS-RX, but this is 228 | // currently not implemented. 229 | // 230 | -------------------------------------------------------------------------------- /3rd_party/nucleo-c031c6/stm32c0xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32c0xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS STM32C0xx Device Peripheral Access Layer Header File. 6 | * 7 | * The file is the unique include file that the application programmer 8 | * is using in the C source code, usually in main.c. This file contains: 9 | * - Configuration section that allows to select: 10 | * - The STM32C0xx device used in the target application 11 | * - To use or not the peripherals drivers in application code(i.e. 12 | * code will be based on direct access to peripherals registers 13 | * rather than drivers API), this option is controlled by 14 | * "#define USE_HAL_DRIVER" 15 | * 16 | ****************************************************************************** 17 | * @attention 18 | * 19 | * Copyright (c) 2022 STMicroelectronics. 20 | * All rights reserved. 21 | * 22 | * This software is licensed under terms that can be found in the LICENSE file 23 | * in the root directory of this software component. 24 | * If no LICENSE file comes with this software, it is provided AS-IS. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /** @addtogroup CMSIS 30 | * @{ 31 | */ 32 | 33 | /** @addtogroup stm32c0xx 34 | * @{ 35 | */ 36 | 37 | #ifndef STM32C0xx_H 38 | #define STM32C0xx_H 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif /* __cplusplus */ 43 | 44 | /** @addtogroup Library_configuration_section 45 | * @{ 46 | */ 47 | 48 | /** 49 | * @brief STM32 Family 50 | */ 51 | #if !defined (STM32C0) 52 | #define STM32C0 53 | #endif /* STM32C0 */ 54 | 55 | /* Uncomment the line below according to the target STM32C0 device used in your 56 | application 57 | */ 58 | 59 | #if !defined (STM32C011xx) && !defined (STM32C031xx) 60 | /* #define STM32C011xx */ /*!< STM32C011xx Devices */ 61 | /* #define STM32C031xx */ /*!< STM32C031xx Devices */ 62 | #endif 63 | 64 | /* Tip: To avoid modifying this file each time you need to switch between these 65 | devices, you can define the device in your toolchain compiler preprocessor. 66 | */ 67 | #if !defined (USE_HAL_DRIVER) 68 | /** 69 | * @brief Comment the line below if you will not use the peripherals drivers. 70 | In this case, these drivers will not be included and the application code will 71 | be based on direct access to peripherals registers 72 | */ 73 | /*#define USE_HAL_DRIVER */ 74 | #endif /* USE_HAL_DRIVER */ 75 | 76 | /** 77 | * @brief CMSIS Device version number V1.0.0 78 | */ 79 | #define __STM32C0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ 80 | #define __STM32C0_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ 81 | #define __STM32C0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ 82 | #define __STM32C0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 83 | #define __STM32C0_CMSIS_VERSION ((__STM32C0_CMSIS_VERSION_MAIN << 24)\ 84 | |(__STM32C0_CMSIS_VERSION_SUB1 << 16)\ 85 | |(__STM32C0_CMSIS_VERSION_SUB2 << 8 )\ 86 | |(__STM32C0_CMSIS_VERSION_RC)) 87 | 88 | /** 89 | * @} 90 | */ 91 | 92 | /** @addtogroup Device_Included 93 | * @{ 94 | */ 95 | 96 | #if defined(STM32C011xx) 97 | #include "stm32c011xx.h" 98 | #elif defined(STM32C031xx) 99 | #include "stm32c031xx.h" 100 | #else 101 | #error "Please select first the target STM32C0xx device used in your application (in stm32c0xx.h file)" 102 | #endif 103 | 104 | /** 105 | * @} 106 | */ 107 | 108 | /** @addtogroup Exported_types 109 | * @{ 110 | */ 111 | typedef enum 112 | { 113 | RESET = 0, 114 | SET = !RESET 115 | } FlagStatus, ITStatus; 116 | 117 | typedef enum 118 | { 119 | DISABLE = 0, 120 | ENABLE = !DISABLE 121 | } FunctionalState; 122 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 123 | 124 | typedef enum 125 | { 126 | SUCCESS = 0, 127 | ERROR = !SUCCESS 128 | } ErrorStatus; 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | /** @addtogroup Exported_macros 135 | * @{ 136 | */ 137 | #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 138 | 139 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 140 | 141 | #define READ_BIT(REG, BIT) ((REG) & (BIT)) 142 | 143 | #define CLEAR_REG(REG) ((REG) = (0x0)) 144 | 145 | #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 146 | 147 | #define READ_REG(REG) ((REG)) 148 | 149 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 150 | 151 | /* Use of interrupt control for register exclusive access */ 152 | /* Atomic 32-bit register access macro to set one or several bits */ 153 | #define ATOMIC_SET_BIT(REG, BIT) \ 154 | do { \ 155 | uint32_t primask; \ 156 | primask = __get_PRIMASK(); \ 157 | __set_PRIMASK(1); \ 158 | SET_BIT((REG), (BIT)); \ 159 | __set_PRIMASK(primask); \ 160 | } while(0) 161 | 162 | /* Atomic 32-bit register access macro to clear one or several bits */ 163 | #define ATOMIC_CLEAR_BIT(REG, BIT) \ 164 | do { \ 165 | uint32_t primask; \ 166 | primask = __get_PRIMASK(); \ 167 | __set_PRIMASK(1); \ 168 | CLEAR_BIT((REG), (BIT)); \ 169 | __set_PRIMASK(primask); \ 170 | } while(0) 171 | 172 | /* Atomic 32-bit register access macro to clear and set one or several bits */ 173 | #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 174 | do { \ 175 | uint32_t primask; \ 176 | primask = __get_PRIMASK(); \ 177 | __set_PRIMASK(1); \ 178 | MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ 179 | __set_PRIMASK(primask); \ 180 | } while(0) 181 | 182 | /* Atomic 16-bit register access macro to set one or several bits */ 183 | #define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \ 184 | 185 | /* Atomic 16-bit register access macro to clear one or several bits */ 186 | #define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \ 187 | 188 | /* Atomic 16-bit register access macro to clear and set one or several bits */ 189 | #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 190 | 191 | #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) 192 | /** 193 | * @} 194 | */ 195 | 196 | #if defined (USE_HAL_DRIVER) 197 | #include "stm32c0xx_hal.h" 198 | #endif /* USE_HAL_DRIVER */ 199 | 200 | #ifdef __cplusplus 201 | } 202 | #endif /* __cplusplus */ 203 | 204 | #endif /* STM32C0xx_H */ 205 | /** 206 | * @} 207 | */ 208 | 209 | /** 210 | * @} 211 | */ 212 | 213 | -------------------------------------------------------------------------------- /3rd_party/nucleo-c031c6/system_stm32c0xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32c0xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File 6 | * 7 | * This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32c0xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | ****************************************************************************** 22 | * @attention 23 | * 24 | * Copyright (c) 2022 STMicroelectronics. 25 | * All rights reserved. 26 | * 27 | * This software is licensed under terms that can be found in the LICENSE file 28 | * in the root directory of this software component. 29 | * If no LICENSE file comes with this software, it is provided AS-IS. 30 | * 31 | ****************************************************************************** 32 | */ 33 | 34 | /** @addtogroup CMSIS 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup stm32c0xx_system 39 | * @{ 40 | */ 41 | 42 | /** @addtogroup STM32C0xx_System_Private_Includes 43 | * @{ 44 | */ 45 | 46 | #include "stm32c0xx.h" 47 | 48 | #if !defined (HSE_VALUE) 49 | #define HSE_VALUE (48000000UL) /*!< Value of the External oscillator in Hz */ 50 | #endif /* HSE_VALUE */ 51 | 52 | #if !defined (HSI_VALUE) 53 | #define HSI_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/ 54 | #endif /* HSI_VALUE */ 55 | 56 | #if !defined (LSI_VALUE) 57 | #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ 58 | #endif /* LSI_VALUE */ 59 | 60 | #if !defined (LSE_VALUE) 61 | #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ 62 | #endif /* LSE_VALUE */ 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @addtogroup STM32C0xx_System_Private_TypesDefinitions 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @addtogroup STM32C0xx_System_Private_Defines 77 | * @{ 78 | */ 79 | 80 | /************************* Miscellaneous Configuration ************************/ 81 | /*!< Uncomment the following line if you need to relocate your vector Table in 82 | Internal SRAM. */ 83 | //#define VECT_TAB_SRAM 84 | #define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. 85 | This value must be a multiple of 0x100. */ 86 | /******************************************************************************/ 87 | /** 88 | * @} 89 | */ 90 | 91 | /** @addtogroup STM32C0xx_System_Private_Macros 92 | * @{ 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | 99 | /** @addtogroup STM32C0xx_System_Private_Variables 100 | * @{ 101 | */ 102 | /* The SystemCoreClock variable is updated in three ways: 103 | 1) by calling CMSIS function SystemCoreClockUpdate() 104 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 105 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 106 | Note: If you use this function to configure the system clock; then there 107 | is no need to call the 2 first functions listed above, since SystemCoreClock 108 | variable is updated automatically. 109 | */ 110 | uint32_t SystemCoreClock = 48000000UL; 111 | 112 | const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; 113 | const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; 114 | 115 | /** 116 | * @} 117 | */ 118 | 119 | /** @addtogroup STM32C0xx_System_Private_FunctionPrototypes 120 | * @{ 121 | */ 122 | 123 | /** 124 | * @} 125 | */ 126 | 127 | /** @addtogroup STM32C0xx_System_Private_Functions 128 | * @{ 129 | */ 130 | 131 | /** 132 | * @brief Setup the microcontroller system. 133 | * @param None 134 | * @retval None 135 | */ 136 | void SystemInit(void) 137 | { 138 | 139 | /* Configure the Vector Table location add offset address ------------------*/ 140 | #ifdef VECT_TAB_SRAM 141 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 142 | #else 143 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 144 | #endif 145 | } 146 | 147 | /** 148 | * @brief Update SystemCoreClock variable according to Clock Register Values. 149 | * The SystemCoreClock variable contains the core clock (HCLK), it can 150 | * be used by the user application to setup the SysTick timer or configure 151 | * other parameters. 152 | * 153 | * @note Each time the core clock (HCLK) changes, this function must be called 154 | * to update SystemCoreClock variable value. Otherwise, any configuration 155 | * based on this variable will be incorrect. 156 | * 157 | * @note - The system frequency computed by this function is not the real 158 | * frequency in the chip. It is calculated based on the predefined 159 | * constant and the selected clock source: 160 | * 161 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor 162 | * 163 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) 164 | * 165 | * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE 166 | * 167 | * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE 168 | * 169 | * (**) HSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value 170 | * 48 MHz) but the real value may vary depending on the variations 171 | * in voltage and temperature. 172 | * 173 | * (***) HSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value 174 | * 48 MHz), user has to ensure that HSE_VALUE is same as the real 175 | * frequency of the crystal used. Otherwise, this function may 176 | * have wrong result. 177 | * 178 | * - The result of this function could be not correct when using fractional 179 | * value for HSE crystal. 180 | * 181 | * @param None 182 | * @retval None 183 | */ 184 | void SystemCoreClockUpdate(void) 185 | { 186 | uint32_t tmp; 187 | uint32_t hsidiv; 188 | 189 | /* Get SYSCLK source -------------------------------------------------------*/ 190 | switch (RCC->CFGR & RCC_CFGR_SWS) 191 | { 192 | case RCC_CFGR_SWS_0: /* HSE used as system clock */ 193 | SystemCoreClock = HSE_VALUE; 194 | break; 195 | 196 | case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ 197 | SystemCoreClock = LSI_VALUE; 198 | break; 199 | 200 | case RCC_CFGR_SWS_2: /* LSE used as system clock */ 201 | SystemCoreClock = LSE_VALUE; 202 | break; 203 | 204 | case 0x00000000U: /* HSI used as system clock */ 205 | default: /* HSI used as system clock */ 206 | hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); 207 | SystemCoreClock = (HSI_VALUE/hsidiv); 208 | break; 209 | } 210 | /* Compute HCLK clock frequency --------------------------------------------*/ 211 | /* Get HCLK prescaler */ 212 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; 213 | /* HCLK clock frequency */ 214 | SystemCoreClock >>= tmp; 215 | } 216 | 217 | 218 | /** 219 | * @} 220 | */ 221 | 222 | /** 223 | * @} 224 | */ 225 | 226 | /** 227 | * @} 228 | */ 229 | -------------------------------------------------------------------------------- /3rd_party/nucleo-c031c6/system_stm32c0xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32c0xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M0+ Device System Source File for STM32C0xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /** @addtogroup CMSIS 20 | * @{ 21 | */ 22 | 23 | /** @addtogroup stm32c0xx_system 24 | * @{ 25 | */ 26 | 27 | /** 28 | * @brief Define to prevent recursive inclusion 29 | */ 30 | #ifndef SYSTEM_STM32C0XX_H 31 | #define SYSTEM_STM32C0XX_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /** @addtogroup STM32C0xx_System_Includes 38 | * @{ 39 | */ 40 | 41 | /** 42 | * @} 43 | */ 44 | 45 | 46 | /** @addtogroup STM32C0xx_System_Exported_types 47 | * @{ 48 | */ 49 | /* This variable is updated in three ways: 50 | 1) by calling CMSIS function SystemCoreClockUpdate() 51 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 52 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 53 | Note: If you use this function to configure the system clock; then there 54 | is no need to call the 2 first functions listed above, since SystemCoreClock 55 | variable is updated automatically. 56 | */ 57 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 58 | 59 | extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 60 | extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @addtogroup STM32C0xx_System_Exported_Constants 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @addtogroup STM32C0xx_System_Exported_Macros 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | /** @addtogroup STM32C0xx_System_Exported_Functions 83 | * @{ 84 | */ 85 | 86 | extern void SystemInit(void); 87 | extern void SystemCoreClockUpdate(void); 88 | /** 89 | * @} 90 | */ 91 | 92 | #ifdef __cplusplus 93 | } 94 | #endif 95 | 96 | #endif /*SYSTEM_STM32C0XX_H */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | -------------------------------------------------------------------------------- /3rd_party/nucleo-l152re/README.txt: -------------------------------------------------------------------------------- 1 | This folder contains the support code for the NUCLEO-L152RE board. 2 | 3 | 4 | CMSIS-Compliant Device Files 5 | ============================ 6 | The code also includes the CMSIS-compliant interface to the 7 | STM32L053xx MCU files: 8 | 9 | stm32l1xx.h 10 | system_stm32l1xx.h 11 | system_stm32l1xx.c 12 | arm\startup_stm32l1xx.s 13 | gcc\startup_stm32l1xx.c 14 | iar\startup_stm32l1xx.s 15 | 16 | 17 | Adjusting the CPU Clock Speed 18 | ============================= 19 | The current setting is to run at 2MHz from the MSI (internal oscillator), 20 | but the CPU clock speed can be modified by editing the file 21 | system_stm32l1xx.c. Ther file system_stm32l1xx.c.pll provides an example 22 | of clock setting using the PLL driven from the MSE. 23 | 24 | *** 25 | NOTE: 26 | The NUCLEO boards have a wide range of possible clock selections, depending 27 | on the solder bridge configuration. Please see Chapter 5.7 "OSC clock" in 28 | the STM32 NUCLEO Boards User Manual (ST document UM1724) for more information. 29 | *** 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /3rd_party/nucleo-l152re/stm32l1xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QuantumLeaps/MiROS/21ea718161a4b8f3dc6756e6d254fe32f9fa7ee1/3rd_party/nucleo-l152re/stm32l1xx.h -------------------------------------------------------------------------------- /3rd_party/nucleo-l152re/system_stm32l1xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32l1xx.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 31-January-2014 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2014 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /** @addtogroup CMSIS 29 | * @{ 30 | */ 31 | 32 | /** @addtogroup stm32l1xx_system 33 | * @{ 34 | */ 35 | 36 | /** 37 | * @brief Define to prevent recursive inclusion 38 | */ 39 | #ifndef __SYSTEM_STM32L1XX_H 40 | #define __SYSTEM_STM32L1XX_H 41 | 42 | #ifdef __cplusplus 43 | extern "C" { 44 | #endif 45 | 46 | /** @addtogroup STM32L1xx_System_Includes 47 | * @{ 48 | */ 49 | 50 | /** 51 | * @} 52 | */ 53 | 54 | 55 | /** @addtogroup STM32L1xx_System_Exported_types 56 | * @{ 57 | */ 58 | /* This variable is updated in three ways: 59 | * 1) by calling CMSIS function SystemCoreClockUpdate() 60 | * 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 61 | * 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 62 | * Note: If you use this function to configure the system clock; then there 63 | * is no need to call the 2 first functions listed above, since SystemCoreClock 64 | * variable is updated automatically. 65 | */ 66 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 67 | 68 | /** 69 | * @} 70 | */ 71 | 72 | /** @addtogroup STM32L1xx_System_Exported_Constants 73 | * @{ 74 | */ 75 | 76 | /** 77 | * @} 78 | */ 79 | 80 | /** @addtogroup STM32L1xx_System_Exported_Macros 81 | * @{ 82 | */ 83 | 84 | /** 85 | * @} 86 | */ 87 | 88 | /** @addtogroup STM32L1xx_System_Exported_Functions 89 | * @{ 90 | */ 91 | 92 | extern void SystemInit(void); 93 | extern void SystemCoreClockUpdate(void); 94 | /** 95 | * @} 96 | */ 97 | 98 | #ifdef __cplusplus 99 | } 100 | #endif 101 | 102 | #endif /*__SYSTEM_STM32L1XX_H */ 103 | 104 | /** 105 | * @} 106 | */ 107 | 108 | /** 109 | * @} 110 | */ 111 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 112 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## Brought to you by: 2 | [![Quantum Leaps](https://www.state-machine.com/attachments/logo_ql_400.png)](https://www.state-machine.com) 3 | 4 | # What is it? 5 | [![GitHub release (latest by date)](https://img.shields.io/github/v/release/QuantumLeaps/MiROS)](https://github.com/QuantumLeaps/MiROS/releases/latest) 6 | [![GitHub](https://img.shields.io/github/license/QuantumLeaps/MiROS)](https://github.com/QuantumLeaps/MiROS/blob/master/LICENSE) 7 | 8 | "MiROS" is a Minimal Real-Time Operating System (RTOS) kernel for ARM Cortex-M. 9 | It supports preemptive, priortity-based multithreading, fully compliant with 10 | RMA/RMS (Rate-Monotonic Analysis/Scheduling). 11 | 12 | >NOTE
13 | MiROS is a teaching aid used in the ["Modern Embedded Programming" video course 14 | on YouTube](https://www.youtube.com/playlist?list=PLPW8O6W-1chyrd_Msnn4LD6LBs2slJITs) 15 | 16 | The main goal of the MiROS kernel is to illustrate the concepts underlying 17 | Real-Time Operating Systems (RTOS). The aim here is simplicity and clear 18 | presentation of the concepts, but without dealing with various corner cases, 19 | portability, or error handling. For these reasons, the software is generally 20 | NOT intended or recommended for use in commercial\applications. 21 | 22 | [![MiROS on YouTube: RTOS part-2](img/MiROS.jpg)](https://youtu.be/PKml9ki3178) 23 | 24 | 25 | # Supported Toolchains 26 | MiROS is available for the following embedded toolchains: 27 | - ARM/KEIL MDK (uVision) 28 | - GNU-ARM (Makefile projects) 29 | - IAR EWARM 30 | 31 | # Supported Embedded Boards 32 | Currently, MiROS examples are available for the following embedded boards: 33 | 34 | - EK-TM4C123GXL (TivaC LaunchPad, ARM Cortex-M4F) 35 | 36 |

37 | 38 | - STM32 NUCLEO-L152RE (ARM Cortex-M3) 39 | 40 |

41 | 42 | - STM32 NUCLEO-C031C6 (ARM Cortex-M0+) 43 | 44 |

45 | 46 | 47 | # Directories and Files 48 | ``` 49 | MiROS/ 50 | +---3rd_party/ - third-party software (needed in the examples) 51 | | +---CMSIS/ - ARM CMSIS 52 | | +---ek-tm4c123gxl/ - low-level code to support EK-TM4C123GX board 53 | | +---nucleo-c031c6/ - low-level code to support STM32 NUCLEO LC031C6 board 54 | | +---nucleo-l152re/ - low-level code to support STM32 NUCLEO L152RE board 55 | | 56 | +---examples/ 57 | | +---blinky_ek-tm4c123gxl/ - Blinky exammple for EK-TM4C123GX board 58 | | | +---armclang/ - project for ARM/KEIL uVision with ARMCLANG 59 | | | +---gnu/ - project for GNU-ARM with simple Makefile 60 | | | +---iar/ - project for IAR EWARM 61 | | | 62 | | +---blinky_nucleo-c031c6/ - Blinky exammple for STM32 NUCLEO-C031C6 63 | | +---armclang/ - project for ARM/KEIL uVision with ARMCLANG 64 | | +---gnu/ - project for GNU-ARM with simple Makefile 65 | | +---iar/ - project for IAR EWARM 66 | | | 67 | | +---blinky_nucleo-l152re/ - Blinky exammple for STM32 NUCLEO-L152RE 68 | | +---armclang/ - project for ARM/KEIL uVision with ARMCLANG 69 | | +---gnu/ - project for GNU-ARM with simple Makefile 70 | | +---iar/ - project for IAR EWARM 71 | | 72 | +---include/ - include directory 73 | | miros.h - MiROS API 74 | +---src/ - MiROS source code 75 | | +---armclang/ 76 | | | miros.c - MiROS implementation for ARMCLANG 77 | | +---gnu/ 78 | | | miros.c - MiROS implementation for GNU-ARM 79 | | +---iar/ 80 | | | miros.c - MiROS implementation for IAR EWARM 81 | ``` 82 | 83 | 84 | # Building the Examples 85 | MiROS comes with the "Blinky" examples for the boards listed above. 86 | 87 | To build and run the examples, inside the "examples" directory select 88 | the "Blinky" version for your board and then, inside that sub-directory 89 | select the toolchain (ARMCLANG, GNU-ARM, or IAR). That sub-directory 90 | contains the project that you can open with the IDE (uVision or IAR). 91 | The GNU-ARM project consists of a simple Makefile, which you can run 92 | from the command-line. 93 | 94 | 95 | # Licensing 96 | MiROS is [licensed](LICENSE) under the GPLv3 open source license. 97 | 98 | 99 | # Comments/Discussion 100 | If you'd like to discuss MiROS or related subjects, plese use the ["Issues" tab](https://github.com/QuantumLeaps/MiROS/issues). 101 | 102 | 103 | # How to Help this Project? 104 | If you like this project, please give it a star (in the upper-right corner of your browser window): 105 | 106 |

107 | 108 | 109 | # Contact Information 110 | [state-machine.com](https://www.state-machine.com/video-course) 111 | -------------------------------------------------------------------------------- /examples/blinky_ek-tm4c123gxl/armclang/project.uvoptx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1.0 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | *.c 10 | *.s*; *.src; *.a* 11 | *.obj; *.o 12 | *.lib 13 | *.txt; *.h; *.inc; *.md 14 | *.plm 15 | *.cpp 16 | 0 17 | 18 | 19 | 20 | 0 21 | 0 22 | 23 | 24 | 25 | dbg 26 | 0x4 27 | ARM-ADS 28 | 29 | 16000000 30 | 31 | 1 32 | 1 33 | 0 34 | 1 35 | 0 36 | 37 | 38 | 1 39 | 65535 40 | 0 41 | 0 42 | 0 43 | 44 | 45 | 79 46 | 66 47 | 8 48 | .\dbg\ 49 | 50 | 51 | 1 52 | 1 53 | 1 54 | 0 55 | 1 56 | 1 57 | 0 58 | 1 59 | 0 60 | 0 61 | 0 62 | 0 63 | 64 | 65 | 1 66 | 1 67 | 1 68 | 1 69 | 1 70 | 1 71 | 1 72 | 0 73 | 0 74 | 75 | 76 | 1 77 | 0 78 | 1 79 | 80 | 4 81 | 82 | 0 83 | 1 84 | 1 85 | 1 86 | 1 87 | 1 88 | 1 89 | 1 90 | 1 91 | 1 92 | 1 93 | 1 94 | 1 95 | 1 96 | 0 97 | 1 98 | 1 99 | 1 100 | 1 101 | 0 102 | 0 103 | 1 104 | 0 105 | 0 106 | 19 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | BIN\lmidk-agdi.dll 118 | 119 | 120 | 121 | 0 122 | ARMRTXEVENTFLAGS 123 | -L70 -Z18 -C0 -M0 -T1 124 | 125 | 126 | 0 127 | DLGTARM 128 | (1010=2641,195,3091,752,0)(1007=-1,-1,-1,-1,0)(1008=2104,174,2480,410,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) 129 | 130 | 131 | 0 132 | ARMDBGFLAGS 133 | 134 | 135 | 136 | 0 137 | lmidk-agdi 138 | -U0E2006F4 -O4622 -S3 -FO29 139 | 140 | 141 | 0 142 | UL2CM3 143 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C123_256 -FS00 -FL040000 -FP0($$Device:TM4C123GH6PM$Flash\TM4C123_256.FLM)) 144 | 145 | 146 | 147 | 148 | 149 | 0 150 | 1 151 | OS_curr 152 | 153 | 154 | 1 155 | 1 156 | OS_next 157 | 158 | 159 | 160 | 161 | 1 162 | 2 163 | 0x20000138 164 | 0 165 | 166 | 167 | 168 | 0 169 | 170 | 171 | 0 172 | 0 173 | 1 174 | 0 175 | 0 176 | 0 177 | 0 178 | 1 179 | 0 180 | 0 181 | 0 182 | 0 183 | 0 184 | 0 185 | 0 186 | 0 187 | 0 188 | 0 189 | 0 190 | 0 191 | 1 192 | 0 193 | 0 194 | 0 195 | 196 | 197 | 198 | 0 199 | 0 200 | 0 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | Applicatioin 214 | 1 215 | 0 216 | 0 217 | 0 218 | 219 | 1 220 | 1 221 | 1 222 | 0 223 | 0 224 | 0 225 | ..\bsp.c 226 | bsp.c 227 | 0 228 | 0 229 | 230 | 231 | 1 232 | 2 233 | 5 234 | 0 235 | 0 236 | 0 237 | ..\bsp.h 238 | bsp.h 239 | 0 240 | 0 241 | 242 | 243 | 1 244 | 3 245 | 1 246 | 0 247 | 0 248 | 0 249 | ..\main.c 250 | main.c 251 | 0 252 | 0 253 | 254 | 255 | 256 | 257 | ek-tm4c123gxl 258 | 1 259 | 0 260 | 0 261 | 0 262 | 263 | 2 264 | 4 265 | 1 266 | 0 267 | 0 268 | 0 269 | ..\..\..\3rd_party\ek-tm4c123gxl\system_TM4C123GH6PM.c 270 | system_TM4C123GH6PM.c 271 | 0 272 | 0 273 | 274 | 275 | 2 276 | 5 277 | 5 278 | 0 279 | 0 280 | 0 281 | ..\..\..\3rd_party\ek-tm4c123gxl\TM4C123GH6PM.h 282 | TM4C123GH6PM.h 283 | 0 284 | 0 285 | 286 | 287 | 2 288 | 6 289 | 2 290 | 0 291 | 0 292 | 0 293 | ..\..\..\3rd_party\ek-tm4c123gxl\arm\startup_TM4C123GH6PM.s 294 | startup_TM4C123GH6PM.s 295 | 0 296 | 0 297 | 298 | 299 | 300 | 301 | MiROS 302 | 1 303 | 0 304 | 0 305 | 0 306 | 307 | 3 308 | 7 309 | 1 310 | 0 311 | 0 312 | 0 313 | ..\..\..\src\armclang\miros.c 314 | miros.c 315 | 0 316 | 0 317 | 318 | 319 | 320 | 321 | -------------------------------------------------------------------------------- /examples/blinky_ek-tm4c123gxl/bsp.c: -------------------------------------------------------------------------------- 1 | /* Board Support Package (BSP) for the EK-TM4C123GXL board */ 2 | #include /* Standard integers. WG14/N843 C99 Standard */ 3 | 4 | #include "bsp.h" 5 | #include "miros.h" 6 | #include "TM4C123GH6PM.h" /* the TM4C MCU Peripheral Access Layer (TI) */ 7 | 8 | /* on-board LEDs */ 9 | #define LED_RED (1U << 1) 10 | #define LED_BLUE (1U << 2) 11 | #define LED_GREEN (1U << 3) 12 | #define TEST_PIN (1U << 4) 13 | 14 | void SysTick_Handler(void) { 15 | GPIOF_AHB->DATA_Bits[TEST_PIN] = TEST_PIN; 16 | 17 | OS_tick(); 18 | 19 | __disable_irq(); 20 | OS_sched(); 21 | __enable_irq(); 22 | 23 | GPIOF_AHB->DATA_Bits[TEST_PIN] = 0U; 24 | } 25 | 26 | void BSP_init(void) { 27 | SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */ 28 | SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */ 29 | GPIOF_AHB->DIR |= (LED_RED | LED_BLUE | LED_GREEN | TEST_PIN); 30 | GPIOF_AHB->DEN |= (LED_RED | LED_BLUE | LED_GREEN | TEST_PIN); 31 | } 32 | 33 | void BSP_ledRedOn(void) { 34 | GPIOF_AHB->DATA_Bits[LED_RED] = LED_RED; 35 | } 36 | 37 | void BSP_ledRedOff(void) { 38 | GPIOF_AHB->DATA_Bits[LED_RED] = 0U; 39 | } 40 | 41 | void BSP_ledBlueOn(void) { 42 | GPIOF_AHB->DATA_Bits[LED_BLUE] = LED_BLUE; 43 | } 44 | 45 | void BSP_ledBlueOff(void) { 46 | GPIOF_AHB->DATA_Bits[LED_BLUE] = 0U; 47 | } 48 | 49 | void BSP_ledGreenOn(void) { 50 | GPIOF_AHB->DATA_Bits[LED_GREEN] = LED_GREEN; 51 | } 52 | 53 | void BSP_ledGreenOff(void) { 54 | GPIOF_AHB->DATA_Bits[LED_GREEN] = 0U; 55 | } 56 | 57 | void OS_onStartup(void) { 58 | SystemCoreClockUpdate(); 59 | SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC); 60 | 61 | /* set the SysTick interrupt priority (highest) */ 62 | NVIC_SetPriority(SysTick_IRQn, 0U); 63 | } 64 | 65 | void OS_onIdle(void) { 66 | GPIOF_AHB->DATA_Bits[LED_RED] = LED_RED; 67 | GPIOF_AHB->DATA_Bits[LED_RED] = 0U; 68 | #ifdef NDBEBUG 69 | __WFI(); /* stop the CPU and Wait for Interrupt */ 70 | #endif 71 | } 72 | 73 | void Q_onAssert(char const *module, int loc) { 74 | /* TBD: damage control */ 75 | (void)module; /* avoid the "unused parameter" compiler warning */ 76 | (void)loc; /* avoid the "unused parameter" compiler warning */ 77 | NVIC_SystemReset(); 78 | } 79 | -------------------------------------------------------------------------------- /examples/blinky_ek-tm4c123gxl/bsp.h: -------------------------------------------------------------------------------- 1 | #ifndef __BSP_H__ 2 | #define __BSP_H__ 3 | 4 | /* system clock tick [Hz] */ 5 | #define BSP_TICKS_PER_SEC 100U 6 | 7 | void BSP_init(void); 8 | 9 | void BSP_ledRedOn(void); 10 | void BSP_ledRedOff(void); 11 | 12 | void BSP_ledBlueOn(void); 13 | void BSP_ledBlueOff(void); 14 | 15 | void BSP_ledGreenOn(void); 16 | void BSP_ledGreenOff(void); 17 | 18 | #endif // __BSP_H__ 19 | -------------------------------------------------------------------------------- /examples/blinky_ek-tm4c123gxl/gnu/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # MInimal Real-time Operating System (MiROS), GNU-ARM port. 3 | # version 1.26 (matching lesson 26, see https://youtu.be/kLxxXNCrY60) 4 | # 5 | # This software is a teaching aid to illustrate the concepts underlying 6 | # a Real-Time Operating System (RTOS). The main goal of the software is 7 | # simplicity and clear presentation of the concepts, but without dealing 8 | # with various corner cases, portability, or error handling. For these 9 | # reasons, the software is generally NOT intended or recommended for use 10 | # in commercial applications. 11 | # 12 | # Copyright (C) 2018 Miro Samek. All Rights Reserved. 13 | # 14 | # SPDX-License-Identifier: GPL-3.0-or-later 15 | # 16 | # This program is free software: you can redistribute it and/or modify 17 | # it under the terms of the GNU General Public License as published by 18 | # the Free Software Foundation, either version 3 of the License, or 19 | # (at your option) any later version. 20 | # 21 | # This program is distributed in the hope that it will be useful, 22 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | # GNU General Public License for more details. 25 | # 26 | # You should have received a copy of the GNU General Public License 27 | # along with this program. If not, see . 28 | # 29 | # Git repo: 30 | # https://github.com/QuantumLeaps/MiROS 31 | ############################################################################## 32 | # examples of invoking this Makefile: 33 | # building configurations: Debug (default), Release, and Spy 34 | # make 35 | # make CONF=rel 36 | # 37 | # cleaning configurations: Debug (default), Release, and Spy 38 | # make clean 39 | # make CONF=rel clean 40 | # 41 | # NOTE: 42 | # To use this Makefile on Windows, you will need the GNU make utility, which 43 | # is included in the Qtools collection for Windows, see: 44 | # https://github.com/QuantumLeaps/qtools 45 | # 46 | 47 | #----------------------------------------------------------------------------- 48 | # project name 49 | # 50 | PROJECT := project 51 | 52 | #----------------------------------------------------------------------------- 53 | # project directories 54 | # 55 | 56 | # list of all source directories used by this project 57 | VPATH = \ 58 | .. \ 59 | ../../../src/gnu \ 60 | ../../../3rd_party/ek-tm4c123gxl \ 61 | ../../../3rd_party/ek-tm4c123gxl/gnu 62 | 63 | # list of all include directories needed by this project 64 | INCLUDES = \ 65 | -I.. \ 66 | -I../../../include \ 67 | -I../../../3rd_party/CMSIS/Include \ 68 | -I../../../3rd_party/ek-tm4c123gxl 69 | 70 | #----------------------------------------------------------------------------- 71 | # files 72 | # 73 | 74 | # assembler source files 75 | ASM_SRCS := 76 | 77 | # C source files 78 | C_SRCS := \ 79 | main.c \ 80 | bsp.c \ 81 | miros.c \ 82 | system_TM4C123GH6PM.c \ 83 | startup_TM4C123GH6PM.c 84 | 85 | # C++ source files 86 | CPP_SRCS := 87 | 88 | OUTPUT := $(PROJECT) 89 | LD_SCRIPT := $(PROJECT).ld 90 | 91 | LIB_DIRS := 92 | LIBS := 93 | 94 | # defines 95 | DEFINES := -DTARGET_IS_TM4C123_RB1 96 | 97 | # ARM CPU, ARCH, FPU, and Float-ABI types... 98 | # ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4] 99 | # ARM_ARCH: [6 | 7] (NOTE: must match ARM_CPU!) 100 | # ARM_FPU: [ | vfp] 101 | # FLOAT_ABI: [ | soft | softfp | hard] 102 | # 103 | ARM_CPU := -mcpu=cortex-m4 104 | ARM_ARCH := 7 # NOTE: must match the ARM_CPU! 105 | ARM_FPU := -mfpu=vfp 106 | FLOAT_ABI := -mfloat-abi=softfp 107 | 108 | #----------------------------------------------------------------------------- 109 | # GNU-ARM toolset (NOTE: You need to adjust to your machine) 110 | # see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads 111 | # 112 | ifeq ($(GNU_ARM),) 113 | GNU_ARM := $(QTOOLS)/gnu_arm-none-eabi 114 | endif 115 | 116 | # make sure that the GNU-ARM toolset exists... 117 | ifeq ("$(wildcard $(GNU_ARM))","") 118 | $(error GNU_ARM toolset not found. Please adjust the Makefile) 119 | endif 120 | 121 | CC := $(GNU_ARM)/bin/arm-none-eabi-gcc 122 | CPP := $(GNU_ARM)/bin/arm-none-eabi-g++ 123 | AS := $(GNU_ARM)/bin/arm-none-eabi-as 124 | LINK := $(GNU_ARM)/bin/arm-none-eabi-gcc 125 | BIN := $(GNU_ARM)/bin/arm-none-eabi-objcopy 126 | 127 | 128 | ############################################################################## 129 | # Typically, you should not need to change anything below this line 130 | 131 | # basic utilities (included in Qtools for Windows), see: 132 | # http://sourceforge.net/projects/qpc/files/Qtools 133 | 134 | MKDIR := mkdir 135 | RM := rm 136 | 137 | #----------------------------------------------------------------------------- 138 | # build options for various configurations for ARM Cortex-M4F 139 | # 140 | 141 | # combine all the soruces... 142 | C_SRCS += $(QP_SRCS) 143 | ASM_SRCS += $(QP_ASMS) 144 | 145 | ifeq (rel, $(CONF)) # Release configuration .................................. 146 | 147 | BIN_DIR := rel 148 | 149 | ASFLAGS = $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU) 150 | 151 | CFLAGS = -c $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 152 | -ffunction-sections -fdata-sections \ 153 | -O1 $(INCLUDES) $(DEFINES) -DNDEBUG 154 | 155 | CPPFLAGS = -c $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 156 | -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \ 157 | -O1 $(INCLUDES) $(DEFINES) -DNDEBUG 158 | 159 | else # default Debug configuration .......................................... 160 | 161 | BIN_DIR := dbg 162 | 163 | ASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU) 164 | 165 | CFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 166 | -ffunction-sections -fdata-sections \ 167 | -O $(INCLUDES) $(DEFINES) 168 | 169 | CPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 170 | -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \ 171 | -O $(INCLUDES) $(DEFINES) 172 | 173 | endif # ...................................................................... 174 | 175 | 176 | LINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \ 177 | -specs=nosys.specs -specs=nano.specs \ 178 | -Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS) 179 | 180 | 181 | ASM_OBJS := $(patsubst %.s,%.o, $(notdir $(ASM_SRCS))) 182 | C_OBJS := $(patsubst %.c,%.o, $(notdir $(C_SRCS))) 183 | CPP_OBJS := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS))) 184 | 185 | TARGET_BIN := $(BIN_DIR)/$(OUTPUT).bin 186 | TARGET_ELF := $(BIN_DIR)/$(OUTPUT).elf 187 | ASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS)) 188 | C_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(C_OBJS)) 189 | C_DEPS_EXT := $(patsubst %.o, %.d, $(C_OBJS_EXT)) 190 | CPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS)) 191 | CPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT)) 192 | 193 | # create $(BIN_DIR) if it does not exist 194 | ifeq ("$(wildcard $(BIN_DIR))","") 195 | $(shell $(MKDIR) $(BIN_DIR)) 196 | endif 197 | 198 | #----------------------------------------------------------------------------- 199 | # rules 200 | # 201 | 202 | all: $(TARGET_BIN) 203 | #all: $(TARGET_ELF) 204 | 205 | $(TARGET_BIN): $(TARGET_ELF) 206 | $(BIN) -O binary $< $@ 207 | 208 | $(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT) 209 | $(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS) 210 | 211 | $(BIN_DIR)/%.d : %.c 212 | $(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@ 213 | 214 | $(BIN_DIR)/%.d : %.cpp 215 | $(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@ 216 | 217 | $(BIN_DIR)/%.o : %.s 218 | $(AS) $(ASFLAGS) $< -o $@ 219 | 220 | $(BIN_DIR)/%.o : %.c 221 | $(CC) $(CFLAGS) $< -o $@ 222 | 223 | $(BIN_DIR)/%.o : %.cpp 224 | $(CPP) $(CPPFLAGS) $< -o $@ 225 | 226 | # include dependency files only if our goal depends on their existence 227 | ifneq ($(MAKECMDGOALS),clean) 228 | ifneq ($(MAKECMDGOALS),show) 229 | -include $(C_DEPS_EXT) $(CPP_DEPS_EXT) 230 | endif 231 | endif 232 | 233 | 234 | .PHONY : clean 235 | clean: 236 | -$(RM) $(BIN_DIR)/*.o \ 237 | $(BIN_DIR)/*.d \ 238 | $(BIN_DIR)/*.bin \ 239 | $(BIN_DIR)/*.elf \ 240 | $(BIN_DIR)/*.map 241 | 242 | show: 243 | @echo PROJECT = $(PROJECT) 244 | @echo CONF = $(CONF) 245 | @echo DEFINES = $(DEFINES) 246 | @echo ASM_FPU = $(ASM_FPU) 247 | @echo ASM_SRCS = $(ASM_SRCS) 248 | @echo C_SRCS = $(C_SRCS) 249 | @echo CPP_SRCS = $(CPP_SRCS) 250 | @echo ASM_OBJS_EXT = $(ASM_OBJS_EXT) 251 | @echo C_OBJS_EXT = $(C_OBJS_EXT) 252 | @echo C_DEPS_EXT = $(C_DEPS_EXT) 253 | @echo CPP_DEPS_EXT = $(CPP_DEPS_EXT) 254 | @echo TARGET_ELF = $(TARGET_ELF) 255 | -------------------------------------------------------------------------------- /examples/blinky_ek-tm4c123gxl/gnu/project.ld: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * Product: Linker script for EK-TM4C123GXL, GNU-ARM linker 3 | * Last Updated for Version: 5.9.8 4 | * Date of the Last Update: 2017-09-13 5 | * 6 | * Q u a n t u m L e a P s 7 | * --------------------------- 8 | * innovating embedded systems 9 | * 10 | * Copyright (C) Quantum Leaps, LLC. All rights reserved. 11 | * 12 | * This program is open source software: you can redistribute it and/or 13 | * modify it under the terms of the GNU General Public License as published 14 | * by the Free Software Foundation, either version 3 of the License, or 15 | * (at your option) any later version. 16 | * 17 | * Alternatively, this program may be distributed and modified under the 18 | * terms of Quantum Leaps commercial licenses, which expressly supersede 19 | * the GNU General Public License and are specifically designed for 20 | * licensees interested in retaining the proprietary status of their code. 21 | * 22 | * This program is distributed in the hope that it will be useful, 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | * GNU General Public License for more details. 26 | * 27 | * You should have received a copy of the GNU General Public License 28 | * along with this program. If not, see . 29 | * 30 | * Contact information: 31 | * Web : http://www.state-machine.com 32 | * Email: info@state-machine.com 33 | *****************************************************************************/ 34 | OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") 35 | OUTPUT_ARCH(arm) 36 | ENTRY(Reset_Handler) /* entry Point */ 37 | 38 | MEMORY { /* memory map of Tiva TM4C123GH6PM */ 39 | ROM (rx) : ORIGIN = 0x00000000, LENGTH = 256K 40 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K 41 | } 42 | 43 | /* The size of the stack used by the application. NOTE: you need to adjust */ 44 | STACK_SIZE = 1024; 45 | 46 | /* The size of the heap used by the application. NOTE: you need to adjust */ 47 | HEAP_SIZE = 0; 48 | 49 | SECTIONS { 50 | 51 | .isr_vector : { /* the vector table goes FIRST into ROM */ 52 | KEEP(*(.isr_vector)) /* vector table */ 53 | . = ALIGN(4); 54 | } >ROM 55 | 56 | .text : { /* code and constants */ 57 | . = ALIGN(4); 58 | *(.text) /* .text sections (code) */ 59 | *(.text*) /* .text* sections (code) */ 60 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 61 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 62 | 63 | KEEP (*(.init)) 64 | KEEP (*(.fini)) 65 | 66 | . = ALIGN(4); 67 | } >ROM 68 | 69 | .preinit_array : { 70 | PROVIDE_HIDDEN (__preinit_array_start = .); 71 | KEEP (*(.preinit_array*)) 72 | PROVIDE_HIDDEN (__preinit_array_end = .); 73 | } >ROM 74 | 75 | .init_array : { 76 | PROVIDE_HIDDEN (__init_array_start = .); 77 | KEEP (*(SORT(.init_array.*))) 78 | KEEP (*(.init_array*)) 79 | PROVIDE_HIDDEN (__init_array_end = .); 80 | } >ROM 81 | 82 | .fini_array : { 83 | PROVIDE_HIDDEN (__fini_array_start = .); 84 | KEEP (*(.fini_array*)) 85 | KEEP (*(SORT(.fini_array.*))) 86 | PROVIDE_HIDDEN (__fini_array_end = .); 87 | } >ROM 88 | 89 | _etext = .; /* global symbols at end of code */ 90 | 91 | .stack : { 92 | __stack_start__ = .; 93 | . = . + STACK_SIZE; 94 | . = ALIGN(4); 95 | __stack_end__ = .; 96 | } >RAM 97 | 98 | .data : AT (_etext) { 99 | __data_load = LOADADDR (.data); 100 | __data_start = .; 101 | *(.data) /* .data sections */ 102 | *(.data*) /* .data* sections */ 103 | . = ALIGN(4); 104 | __data_end__ = .; 105 | _edata = __data_end__; 106 | } >RAM 107 | 108 | .bss : { 109 | __bss_start__ = .; 110 | *(.bss) 111 | *(.bss*) 112 | *(COMMON) 113 | . = ALIGN(4); 114 | _ebss = .; /* define a global symbol at bss end */ 115 | __bss_end__ = .; 116 | } >RAM 117 | 118 | __exidx_start = .; 119 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM 120 | __exidx_end = .; 121 | 122 | PROVIDE ( end = _ebss ); 123 | PROVIDE ( _end = _ebss ); 124 | PROVIDE ( __end__ = _ebss ); 125 | 126 | .heap : { 127 | __heap_start__ = .; 128 | . = . + HEAP_SIZE; 129 | . = ALIGN(4); 130 | __heap_end__ = .; 131 | } >RAM 132 | 133 | /* Remove information from the standard libraries */ 134 | /DISCARD/ : { 135 | libc.a ( * ) 136 | libm.a ( * ) 137 | libgcc.a ( * ) 138 | } 139 | } 140 | -------------------------------------------------------------------------------- /examples/blinky_ek-tm4c123gxl/iar/project.eww: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | $WS_DIR$\project.ewp 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /examples/blinky_ek-tm4c123gxl/iar/project.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x00000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 1024; 13 | define symbol __ICFEDIT_size_heap__ = 0; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | place in ROM_region { readonly }; 28 | place in RAM_region { readwrite, 29 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /examples/blinky_ek-tm4c123gxl/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "miros.h" 3 | #include "bsp.h" 4 | 5 | uint32_t stack_blinky1[40]; 6 | OSThread blinky1; 7 | void main_blinky1() { 8 | while (1) { 9 | BSP_ledGreenOn(); 10 | OS_delay(BSP_TICKS_PER_SEC / 4U); 11 | BSP_ledGreenOff(); 12 | OS_delay(BSP_TICKS_PER_SEC * 3U / 4U); 13 | } 14 | } 15 | 16 | uint32_t stack_blinky2[40]; 17 | OSThread blinky2; 18 | void main_blinky2() { 19 | while (1) { 20 | BSP_ledBlueOn(); 21 | OS_delay(BSP_TICKS_PER_SEC / 2U); 22 | BSP_ledBlueOff(); 23 | OS_delay(BSP_TICKS_PER_SEC / 3U); 24 | } 25 | } 26 | 27 | uint32_t stack_blinky3[40]; 28 | OSThread blinky3; 29 | void main_blinky3() { 30 | while (1) { 31 | BSP_ledRedOn(); 32 | OS_delay(BSP_TICKS_PER_SEC / 3U); 33 | BSP_ledRedOff(); 34 | OS_delay(BSP_TICKS_PER_SEC * 3U / 5U); 35 | } 36 | } 37 | 38 | uint32_t stack_idleThread[40]; 39 | 40 | int main() { 41 | OS_init(stack_idleThread, sizeof(stack_idleThread)); 42 | BSP_init(); 43 | 44 | /* start blinky1 thread */ 45 | OSThread_start(&blinky1, 46 | 5U, /* priority */ 47 | &main_blinky1, 48 | stack_blinky1, sizeof(stack_blinky1)); 49 | 50 | /* start blinky2 thread */ 51 | OSThread_start(&blinky2, 52 | 2U, /* priority */ 53 | &main_blinky2, 54 | stack_blinky2, sizeof(stack_blinky2)); 55 | 56 | /* start blinky3 thread */ 57 | OSThread_start(&blinky3, 58 | 1U, /* priority */ 59 | &main_blinky3, 60 | stack_blinky3, sizeof(stack_blinky3)); 61 | 62 | /* transfer control to the RTOS to run the threads */ 63 | OS_run(); 64 | 65 | //return 0; 66 | } 67 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-c031c6/bsp.c: -------------------------------------------------------------------------------- 1 | /* Board Support Package (BSP) for the NUCLEO-C031C6 board */ 2 | #include /* Standard integers. WG14/N843 C99 Standard */ 3 | 4 | #include "bsp.h" 5 | #include "miros.h" 6 | #include "stm32c0xx.h" /* CMSIS-compliant header file for the MCU used */ 7 | /* add other drivers if necessary... */ 8 | 9 | // LED marked "LD4" (PA.5) on the NUCLEO-C031C6 board 10 | #define LD4_PIN 5U 11 | 12 | // external LED to be inserted between GND (short leg) and 13 | // D12 (longer leg) on the CN9 connector 14 | #define LD5_PIN 6U 15 | 16 | // Button B1 (PC.13) on the NUCLEO-C031C6 board 17 | #define B1_PIN 13U 18 | 19 | void SysTick_Handler(void) { 20 | OS_tick(); 21 | 22 | __disable_irq(); 23 | OS_sched(); 24 | __enable_irq(); 25 | } 26 | 27 | void BSP_init(void) { 28 | // enable GPIOA clock port for the LEDs 29 | RCC->IOPENR |= (1U << 0U); 30 | 31 | // NUCLEO-C031C6 board has LED LD4 on GPIOA pin LD4_PIN 32 | // and external LED LD5 on GPIO LD5_PIN 33 | // set the LED pins as push-pull output, no pull-up, pull-down 34 | GPIOA->MODER &= ~((3U << 2U*LD4_PIN) | (3U << 2U*LD5_PIN)); 35 | GPIOA->MODER |= ((1U << 2U*LD4_PIN) | (1U << 2U*LD5_PIN)); 36 | GPIOA->OTYPER &= ~((1U << LD4_PIN) | (1U << LD5_PIN)); 37 | GPIOA->OSPEEDR &= ~((3U << 2U*LD4_PIN) | (3U << 2U*LD5_PIN)); 38 | GPIOA->OSPEEDR |= ((1U << 2U*LD4_PIN) | (1U << 2U*LD5_PIN)); 39 | GPIOA->PUPDR &= ~((3U << 2U*LD4_PIN) | (3U << 2U*LD5_PIN)); 40 | 41 | // configure Button B1 (PC.13) pins as input, no pull-up, pull-down 42 | GPIOC->MODER &= ~(3U << 2*B1_PIN); 43 | GPIOC->OSPEEDR &= ~(3U << 2*B1_PIN); 44 | GPIOC->OSPEEDR |= (1U << 2*B1_PIN); 45 | GPIOC->PUPDR &= ~(3U << 2*B1_PIN); 46 | } 47 | 48 | void BSP_ledRedOn(void) { 49 | /* no red LED on board */ 50 | } 51 | 52 | void BSP_ledRedOff(void) { 53 | /* no red LED on board */ 54 | } 55 | 56 | void BSP_ledBlueOn(void) { 57 | /* no blue LED on board */ 58 | } 59 | 60 | void BSP_ledBlueOff(void) { 61 | /* no blue LED on board */ 62 | } 63 | 64 | void BSP_ledGreenOn(void) { 65 | GPIOA->BSRR = (1U << LD4_PIN); /* turn LED on */ 66 | } 67 | 68 | void BSP_ledGreenOff(void) { 69 | GPIOA->BSRR = (1U << (LD4_PIN + 16U)); /* turn LED off */ 70 | } 71 | 72 | void OS_onStartup(void) { 73 | SystemCoreClockUpdate(); 74 | SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC); 75 | 76 | /* set the SysTick interrupt priority (highest) */ 77 | NVIC_SetPriority(SysTick_IRQn, 0U); 78 | } 79 | 80 | void OS_onIdle(void) { 81 | #ifdef NDBEBUG 82 | __WFI(); /* stop the CPU and Wait for Interrupt */ 83 | #endif 84 | } 85 | 86 | void Q_onAssert(char const *module, int id) { 87 | /* TBD: damage control */ 88 | (void)module; /* avoid the "unused parameter" compiler warning */ 89 | (void)id; /* avoid the "unused parameter" compiler warning */ 90 | NVIC_SystemReset(); 91 | } 92 | 93 | void assert_failed(char const *module, int id) { 94 | Q_onAssert(module, id); 95 | } 96 | 97 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-c031c6/bsp.h: -------------------------------------------------------------------------------- 1 | #ifndef __BSP_H__ 2 | #define __BSP_H__ 3 | 4 | /* system clock tick [Hz] */ 5 | #define BSP_TICKS_PER_SEC 100U 6 | 7 | void BSP_init(void); 8 | 9 | void BSP_ledRedOn(void); 10 | void BSP_ledRedOff(void); 11 | 12 | void BSP_ledBlueOn(void); 13 | void BSP_ledBlueOff(void); 14 | 15 | void BSP_ledGreenOn(void); 16 | void BSP_ledGreenOff(void); 17 | 18 | #endif // __BSP_H__ 19 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-c031c6/gnu/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # MInimal Real-time Operating System (MiROS), GNU-ARM port. 3 | # version 1.26 (matching lesson 26, see https://youtu.be/kLxxXNCrY60) 4 | # 5 | # This software is a teaching aid to illustrate the concepts underlying 6 | # a Real-Time Operating System (RTOS). The main goal of the software is 7 | # simplicity and clear presentation of the concepts, but without dealing 8 | # with various corner cases, portability, or error handling. For these 9 | # reasons, the software is generally NOT intended or recommended for use 10 | # in commercial applications. 11 | # 12 | # Copyright (C) 2018 Miro Samek. All Rights Reserved. 13 | # 14 | # SPDX-License-Identifier: GPL-3.0-or-later 15 | # 16 | # This program is free software: you can redistribute it and/or modify 17 | # it under the terms of the GNU General Public License as published by 18 | # the Free Software Foundation, either version 3 of the License, or 19 | # (at your option) any later version. 20 | # 21 | # This program is distributed in the hope that it will be useful, 22 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | # GNU General Public License for more details. 25 | # 26 | # You should have received a copy of the GNU General Public License 27 | # along with this program. If not, see . 28 | # 29 | # Git repo: 30 | # https://github.com/QuantumLeaps/MiROS 31 | ############################################################################## 32 | # examples of invoking this Makefile: 33 | # building configurations: Debug (default), Release, and Spy 34 | # make 35 | # make CONF=rel 36 | # 37 | # cleaning configurations: Debug (default), Release, and Spy 38 | # make clean 39 | # make CONF=rel clean 40 | # 41 | # NOTE: 42 | # To use this Makefile on Windows, you will need the GNU make utility, which 43 | # is included in the Qtools collection for Windows, see: 44 | # https://github.com/QuantumLeaps/qtools 45 | # 46 | 47 | #----------------------------------------------------------------------------- 48 | # project name 49 | # 50 | PROJECT := project 51 | 52 | #----------------------------------------------------------------------------- 53 | # project directories 54 | # 55 | 56 | # list of all source directories used by this project 57 | VPATH = \ 58 | .. \ 59 | ../../../src/gnu \ 60 | ../../../3rd_party/nucleo-c031c6 \ 61 | ../../../3rd_party/nucleo-c031c6/gnu 62 | 63 | # list of all include directories needed by this project 64 | INCLUDES = \ 65 | -I.. \ 66 | -I../../../include \ 67 | -I../../../3rd_party/CMSIS/Include \ 68 | -I../../../3rd_party/nucleo-c031c6 69 | 70 | #----------------------------------------------------------------------------- 71 | # files 72 | # 73 | 74 | # assembler source files 75 | ASM_SRCS := 76 | 77 | # C source files 78 | C_SRCS := \ 79 | main.c \ 80 | bsp.c \ 81 | miros.c \ 82 | system_stm32c0xx.c \ 83 | startup_stm32c031xx.c 84 | 85 | # C++ source files 86 | CPP_SRCS := 87 | 88 | OUTPUT := $(PROJECT) 89 | LD_SCRIPT := $(PROJECT).ld 90 | 91 | LIB_DIRS := 92 | LIBS := 93 | 94 | # defines 95 | DEFINES := -DSTM32C031xx 96 | 97 | # ARM CPU, ARCH, FPU, and Float-ABI types... 98 | # ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4] 99 | # ARM_FPU: [ | vfp] 100 | # FLOAT_ABI: [ | soft | softfp | hard] 101 | # 102 | ARM_CPU := -mcpu=cortex-m0plus 103 | ARM_FPU := 104 | FLOAT_ABI := 105 | 106 | #----------------------------------------------------------------------------- 107 | # GNU-ARM toolset (NOTE: You need to adjust to your machine) 108 | # see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads 109 | # 110 | ifeq ($(GNU_ARM),) 111 | GNU_ARM := $(QTOOLS)/gnu_arm-none-eabi 112 | endif 113 | 114 | # make sure that the GNU-ARM toolset exists... 115 | ifeq ("$(wildcard $(GNU_ARM))","") 116 | $(error GNU_ARM toolset not found. Please adjust the Makefile) 117 | endif 118 | 119 | CC := $(GNU_ARM)/bin/arm-none-eabi-gcc 120 | CPP := $(GNU_ARM)/bin/arm-none-eabi-g++ 121 | AS := $(GNU_ARM)/bin/arm-none-eabi-as 122 | LINK := $(GNU_ARM)/bin/arm-none-eabi-gcc 123 | BIN := $(GNU_ARM)/bin/arm-none-eabi-objcopy 124 | 125 | 126 | ############################################################################## 127 | # Typically, you should not need to change anything below this line 128 | 129 | # basic utilities (included in Qtools for Windows), see: 130 | # http://sourceforge.net/projects/qpc/files/Qtools 131 | 132 | MKDIR := mkdir 133 | RM := rm 134 | 135 | #----------------------------------------------------------------------------- 136 | # build options for various configurations for ARM Cortex-M4F 137 | # 138 | 139 | # combine all the soruces... 140 | C_SRCS += $(QP_SRCS) 141 | ASM_SRCS += $(QP_ASMS) 142 | 143 | ifeq (rel, $(CONF)) # Release configuration .................................. 144 | 145 | BIN_DIR := rel 146 | 147 | ASFLAGS = $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU) 148 | 149 | CFLAGS = -c $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 150 | -ffunction-sections -fdata-sections \ 151 | -O1 $(INCLUDES) $(DEFINES) -DNDEBUG 152 | 153 | CPPFLAGS = -c $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 154 | -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \ 155 | -O1 $(INCLUDES) $(DEFINES) -DNDEBUG 156 | 157 | else # default Debug configuration .......................................... 158 | 159 | BIN_DIR := dbg 160 | 161 | ASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU) 162 | 163 | CFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 164 | -ffunction-sections -fdata-sections \ 165 | -O $(INCLUDES) $(DEFINES) 166 | 167 | CPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 168 | -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \ 169 | -O $(INCLUDES) $(DEFINES) 170 | 171 | endif # ...................................................................... 172 | 173 | 174 | LINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \ 175 | -specs=nosys.specs -specs=nano.specs \ 176 | -Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS) 177 | 178 | 179 | ASM_OBJS := $(patsubst %.s,%.o, $(notdir $(ASM_SRCS))) 180 | C_OBJS := $(patsubst %.c,%.o, $(notdir $(C_SRCS))) 181 | CPP_OBJS := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS))) 182 | 183 | TARGET_BIN := $(BIN_DIR)/$(OUTPUT).bin 184 | TARGET_ELF := $(BIN_DIR)/$(OUTPUT).elf 185 | ASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS)) 186 | C_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(C_OBJS)) 187 | C_DEPS_EXT := $(patsubst %.o, %.d, $(C_OBJS_EXT)) 188 | CPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS)) 189 | CPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT)) 190 | 191 | # create $(BIN_DIR) if it does not exist 192 | ifeq ("$(wildcard $(BIN_DIR))","") 193 | $(shell $(MKDIR) $(BIN_DIR)) 194 | endif 195 | 196 | #----------------------------------------------------------------------------- 197 | # rules 198 | # 199 | 200 | all: $(TARGET_BIN) 201 | #all: $(TARGET_ELF) 202 | 203 | $(TARGET_BIN): $(TARGET_ELF) 204 | $(BIN) -O binary $< $@ 205 | 206 | $(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT) 207 | $(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS) 208 | 209 | $(BIN_DIR)/%.d : %.c 210 | $(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@ 211 | 212 | $(BIN_DIR)/%.d : %.cpp 213 | $(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@ 214 | 215 | $(BIN_DIR)/%.o : %.s 216 | $(AS) $(ASFLAGS) $< -o $@ 217 | 218 | $(BIN_DIR)/%.o : %.c 219 | $(CC) $(CFLAGS) $< -o $@ 220 | 221 | $(BIN_DIR)/%.o : %.cpp 222 | $(CPP) $(CPPFLAGS) $< -o $@ 223 | 224 | # include dependency files only if our goal depends on their existence 225 | ifneq ($(MAKECMDGOALS),clean) 226 | ifneq ($(MAKECMDGOALS),show) 227 | -include $(C_DEPS_EXT) $(CPP_DEPS_EXT) 228 | endif 229 | endif 230 | 231 | 232 | .PHONY : clean 233 | clean: 234 | -$(RM) $(BIN_DIR)/*.o \ 235 | $(BIN_DIR)/*.d \ 236 | $(BIN_DIR)/*.bin \ 237 | $(BIN_DIR)/*.elf \ 238 | $(BIN_DIR)/*.map 239 | 240 | show: 241 | @echo PROJECT = $(PROJECT) 242 | @echo CONF = $(CONF) 243 | @echo DEFINES = $(DEFINES) 244 | @echo ASM_FPU = $(ASM_FPU) 245 | @echo ASM_SRCS = $(ASM_SRCS) 246 | @echo C_SRCS = $(C_SRCS) 247 | @echo CPP_SRCS = $(CPP_SRCS) 248 | @echo ASM_OBJS_EXT = $(ASM_OBJS_EXT) 249 | @echo C_OBJS_EXT = $(C_OBJS_EXT) 250 | @echo C_DEPS_EXT = $(C_DEPS_EXT) 251 | @echo CPP_DEPS_EXT = $(CPP_DEPS_EXT) 252 | @echo TARGET_ELF = $(TARGET_ELF) 253 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-c031c6/gnu/project.ld: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * Linker script for for STM32C031C6, GNU-ARM linker 3 | * 4 | * Q u a n t u m L e a P s 5 | * ------------------------ 6 | * Modern Embedded Software 7 | * 8 | * Copyright (C) 2005 Quantum Leaps, LLC . 9 | * 10 | * SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial 11 | * 12 | * This software is dual-licensed under the terms of the open source GNU 13 | * General Public License version 3 (or any later version), or alternatively, 14 | * under the terms of one of the closed source Quantum Leaps commercial 15 | * licenses. 16 | * 17 | * The terms of the open source GNU General Public License version 3 18 | * can be found at: 19 | * 20 | * The terms of the closed source Quantum Leaps commercial licenses 21 | * can be found at: 22 | * 23 | * Redistributions in source code must retain this top-level comment block. 24 | * Plagiarizing this software to sidestep the license obligations is illegal. 25 | * 26 | * Contact information: 27 | * 28 | * 29 | *****************************************************************************/ 30 | OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") 31 | OUTPUT_ARCH(arm) 32 | ENTRY(Reset_Handler) /* entry Point */ 33 | 34 | MEMORY { /* memory map of STM32C031C6 */ 35 | ROM (rx) : ORIGIN = 0x08000000, LENGTH = 32K 36 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 12K 37 | } 38 | 39 | /* The size of the stack used by the application. NOTE: you need to adjust */ 40 | STACK_SIZE = 2048; 41 | 42 | /* The size of the heap used by the application. NOTE: you need to adjust */ 43 | HEAP_SIZE = 0; 44 | 45 | SECTIONS { 46 | 47 | .isr_vector : { /* the vector table goes FIRST into ROM */ 48 | KEEP(*(.isr_vector)) /* vector table */ 49 | . = ALIGN(4); 50 | } >ROM 51 | 52 | .text : { /* code and constants */ 53 | . = ALIGN(4); 54 | *(.text) /* .text sections (code) */ 55 | *(.text*) /* .text* sections (code) */ 56 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 57 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 58 | 59 | KEEP (*(.init)) 60 | KEEP (*(.fini)) 61 | 62 | . = ALIGN(4); 63 | } >ROM 64 | 65 | .preinit_array : { 66 | PROVIDE_HIDDEN (__preinit_array_start = .); 67 | KEEP (*(.preinit_array*)) 68 | PROVIDE_HIDDEN (__preinit_array_end = .); 69 | } >ROM 70 | 71 | .init_array : { 72 | PROVIDE_HIDDEN (__init_array_start = .); 73 | KEEP (*(SORT(.init_array.*))) 74 | KEEP (*(.init_array*)) 75 | PROVIDE_HIDDEN (__init_array_end = .); 76 | } >ROM 77 | 78 | .fini_array : { 79 | PROVIDE_HIDDEN (__fini_array_start = .); 80 | KEEP (*(.fini_array*)) 81 | KEEP (*(SORT(.fini_array.*))) 82 | PROVIDE_HIDDEN (__fini_array_end = .); 83 | } >ROM 84 | 85 | _etext = .; /* global symbols at end of code */ 86 | 87 | .stack : { 88 | __stack_start__ = .; 89 | . = . + STACK_SIZE; 90 | . = ALIGN(4); 91 | __stack_end__ = .; 92 | } >RAM 93 | 94 | .data : AT (_etext) { 95 | __data_load = LOADADDR (.data); 96 | __data_start = .; 97 | *(.data) /* .data sections */ 98 | *(.data*) /* .data* sections */ 99 | . = ALIGN(4); 100 | __data_end__ = .; 101 | _edata = __data_end__; 102 | } >RAM 103 | 104 | .bss : { 105 | __bss_start__ = .; 106 | *(.bss) 107 | *(.bss*) 108 | *(COMMON) 109 | . = ALIGN(4); 110 | _ebss = .; /* define a global symbol at bss end */ 111 | __bss_end__ = .; 112 | } >RAM 113 | 114 | __exidx_start = .; 115 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM 116 | __exidx_end = .; 117 | 118 | PROVIDE ( end = _ebss ); 119 | PROVIDE ( _end = _ebss ); 120 | PROVIDE ( __end__ = _ebss ); 121 | 122 | .heap : { 123 | __heap_start__ = .; 124 | . = . + HEAP_SIZE; 125 | . = ALIGN(4); 126 | __heap_end__ = .; 127 | } >RAM 128 | 129 | /* Remove information from the standard libraries */ 130 | /DISCARD/ : { 131 | libc.a ( * ) 132 | libm.a ( * ) 133 | libgcc.a ( * ) 134 | } 135 | } 136 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-c031c6/iar/project.eww: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | $WS_DIR$\project.ewp 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-c031c6/iar/project.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_IROM1_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_IROM1_end__ = 0x08007FFF; 9 | define symbol __ICFEDIT_region_IROM2_start__ = 0x0; 10 | define symbol __ICFEDIT_region_IROM2_end__ = 0x0; 11 | define symbol __ICFEDIT_region_EROM1_start__ = 0x0; 12 | define symbol __ICFEDIT_region_EROM1_end__ = 0x0; 13 | define symbol __ICFEDIT_region_EROM2_start__ = 0x0; 14 | define symbol __ICFEDIT_region_EROM2_end__ = 0x0; 15 | define symbol __ICFEDIT_region_EROM3_start__ = 0x0; 16 | define symbol __ICFEDIT_region_EROM3_end__ = 0x0; 17 | define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000; 18 | define symbol __ICFEDIT_region_IRAM1_end__ = 0x20002FFF; 19 | define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; 20 | define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; 21 | define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; 22 | define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; 23 | define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; 24 | define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; 25 | define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; 26 | define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; 27 | /*-Sizes-*/ 28 | define symbol __ICFEDIT_size_cstack__ = 2048; 29 | define symbol __ICFEDIT_size_proc_stack__ = 0x0; 30 | define symbol __ICFEDIT_size_heap__ = 0; 31 | /**** End of ICF editor section. ###ICF###*/ 32 | 33 | define memory mem with size = 4G; 34 | define symbol use_IROM1 = (__ICFEDIT_region_IROM1_start__ != 0x0 || __ICFEDIT_region_IROM1_end__ != 0x0); 35 | define symbol use_IROM2 = (__ICFEDIT_region_IROM2_start__ != 0x0 || __ICFEDIT_region_IROM2_end__ != 0x0); 36 | define symbol use_EROM1 = (__ICFEDIT_region_EROM1_start__ != 0x0 || __ICFEDIT_region_EROM1_end__ != 0x0); 37 | define symbol use_EROM2 = (__ICFEDIT_region_EROM2_start__ != 0x0 || __ICFEDIT_region_EROM2_end__ != 0x0); 38 | define symbol use_EROM3 = (__ICFEDIT_region_EROM3_start__ != 0x0 || __ICFEDIT_region_EROM3_end__ != 0x0); 39 | define symbol use_IRAM1 = (__ICFEDIT_region_IRAM1_start__ != 0x0 || __ICFEDIT_region_IRAM1_end__ != 0x0); 40 | define symbol use_IRAM2 = (__ICFEDIT_region_IRAM2_start__ != 0x0 || __ICFEDIT_region_IRAM2_end__ != 0x0); 41 | define symbol use_ERAM1 = (__ICFEDIT_region_ERAM1_start__ != 0x0 || __ICFEDIT_region_ERAM1_end__ != 0x0); 42 | define symbol use_ERAM2 = (__ICFEDIT_region_ERAM2_start__ != 0x0 || __ICFEDIT_region_ERAM2_end__ != 0x0); 43 | define symbol use_ERAM3 = (__ICFEDIT_region_ERAM3_start__ != 0x0 || __ICFEDIT_region_ERAM3_end__ != 0x0); 44 | 45 | if (use_IROM1) 46 | { 47 | define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; 48 | } 49 | else 50 | { 51 | define region IROM1_region = []; 52 | } 53 | 54 | if (use_IROM2) 55 | { 56 | define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; 57 | } 58 | else 59 | { 60 | define region IROM2_region = []; 61 | } 62 | define region IROM_region = IROM1_region | IROM2_region; 63 | 64 | if (use_EROM1) 65 | { 66 | define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; 67 | } 68 | else 69 | { 70 | define region EROM1_region = []; 71 | } 72 | if (use_EROM2) 73 | { 74 | define region EROM2_region = mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__]; 75 | } 76 | else 77 | { 78 | define region EROM2_region = []; 79 | } 80 | if (use_EROM3) 81 | { 82 | define region EROM3_region = mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__]; 83 | } 84 | else 85 | { 86 | define region EROM3_region = []; 87 | } 88 | define region EROM_region = EROM1_region | EROM2_region | EROM3_region; 89 | 90 | if (use_IRAM1) 91 | { 92 | define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; 93 | } 94 | else 95 | { 96 | define region IRAM1_region = []; 97 | } 98 | if (use_IRAM2) 99 | { 100 | define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; 101 | } 102 | else 103 | { 104 | define region IRAM2_region = []; 105 | } 106 | define region IRAM_region = IRAM1_region | IRAM2_region; 107 | 108 | if (use_ERAM1) 109 | { 110 | define region ERAM1_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]; 111 | } 112 | else 113 | { 114 | define region ERAM1_region = []; 115 | } 116 | if (use_ERAM2) 117 | { 118 | define region ERAM2_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]; 119 | } 120 | else 121 | { 122 | define region ERAM2_region = []; 123 | } 124 | if (use_ERAM3) 125 | { 126 | define region ERAM3_region = mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; 127 | } 128 | else 129 | { 130 | define region ERAM3_region = []; 131 | } 132 | define region ERAM_region = ERAM1_region | ERAM2_region | ERAM3_region; 133 | 134 | initialize by copy { readwrite }; 135 | if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) 136 | { 137 | // Required in a multi-threaded application 138 | initialize by copy with packing = none { section __DLIB_PERTHREAD }; 139 | } 140 | 141 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 142 | 143 | if (!isempty(IROM_region)) 144 | { 145 | place in IROM_region { readonly }; 146 | } 147 | 148 | if (!isempty(EROM_region)) 149 | { 150 | place in EROM_region { readonly section application_specific_ro }; 151 | } 152 | 153 | if (!isempty(IRAM_region)) 154 | { 155 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 156 | define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; 157 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 158 | place at start of IRAM_region {block CSTACK }; /* <== Quantum Leaps */ 159 | place in IRAM_region { readwrite, block PROC_STACK, block HEAP }; 160 | } 161 | 162 | if (!isempty(ERAM_region)) 163 | { 164 | place in ERAM_region { readwrite section application_specific_rw }; 165 | } -------------------------------------------------------------------------------- /examples/blinky_nucleo-c031c6/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "miros.h" 3 | #include "bsp.h" 4 | 5 | uint32_t stack_blinky1[40]; 6 | OSThread blinky1; 7 | void main_blinky1() { 8 | while (1) { 9 | BSP_ledGreenOn(); 10 | OS_delay(BSP_TICKS_PER_SEC / 4U); 11 | BSP_ledGreenOff(); 12 | OS_delay(BSP_TICKS_PER_SEC * 3U / 4U); 13 | } 14 | } 15 | 16 | uint32_t stack_blinky2[40]; 17 | OSThread blinky2; 18 | void main_blinky2() { 19 | while (1) { 20 | BSP_ledBlueOn(); 21 | OS_delay(BSP_TICKS_PER_SEC / 2U); 22 | BSP_ledBlueOff(); 23 | OS_delay(BSP_TICKS_PER_SEC / 3U); 24 | } 25 | } 26 | 27 | uint32_t stack_blinky3[40]; 28 | OSThread blinky3; 29 | void main_blinky3() { 30 | while (1) { 31 | BSP_ledRedOn(); 32 | OS_delay(BSP_TICKS_PER_SEC / 3U); 33 | BSP_ledRedOff(); 34 | OS_delay(BSP_TICKS_PER_SEC * 3U / 5U); 35 | } 36 | } 37 | 38 | uint32_t stack_idleThread[40]; 39 | 40 | int main() { 41 | OS_init(stack_idleThread, sizeof(stack_idleThread)); 42 | BSP_init(); 43 | 44 | /* start blinky1 thread */ 45 | OSThread_start(&blinky1, 46 | 5U, /* priority */ 47 | &main_blinky1, 48 | stack_blinky1, sizeof(stack_blinky1)); 49 | 50 | /* start blinky2 thread */ 51 | OSThread_start(&blinky2, 52 | 2U, /* priority */ 53 | &main_blinky2, 54 | stack_blinky2, sizeof(stack_blinky2)); 55 | 56 | /* start blinky3 thread */ 57 | OSThread_start(&blinky3, 58 | 1U, /* priority */ 59 | &main_blinky3, 60 | stack_blinky3, sizeof(stack_blinky3)); 61 | 62 | /* transfer control to the RTOS to run the threads */ 63 | OS_run(); 64 | 65 | //return 0; 66 | } 67 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-l152re/bsp.c: -------------------------------------------------------------------------------- 1 | /* Board Support Package (BSP) for the NUCLEO-L152RE board */ 2 | #include /* Standard integers. WG14/N843 C99 Standard */ 3 | 4 | #include "bsp.h" 5 | #include "miros.h" 6 | #include "stm32l1xx.h" /* CMSIS-compliant header file for the MCU used */ 7 | /* add other drivers if necessary... */ 8 | 9 | /* LED pins available on the board (just one user LED LD2--Green on PA.5) */ 10 | #define LED_LD2 (1U << 5) 11 | 12 | /* Button pins available on the board (just one user Button B1 on PC.13) */ 13 | #define BTN_B1 (1U << 13) 14 | 15 | void SysTick_Handler(void) { 16 | OS_tick(); 17 | 18 | __disable_irq(); 19 | OS_sched(); 20 | __enable_irq(); 21 | } 22 | 23 | void BSP_init(void) { 24 | /* enable GPIOA clock port for the LED LD2 */ 25 | RCC->AHBENR |= (1U << 0); 26 | 27 | /* configure LED (PA.5) pin as push-pull output, no pull-up, pull-down */ 28 | GPIOA->MODER &= ~((3U << 2*5)); 29 | GPIOA->MODER |= ((1U << 2*5)); 30 | GPIOA->OTYPER &= ~((1U << 5)); 31 | GPIOA->OSPEEDR &= ~((3U << 2*5)); 32 | GPIOA->OSPEEDR |= ((1U << 2*5)); 33 | GPIOA->PUPDR &= ~((3U << 2*5)); 34 | 35 | /* enable GPIOC clock port for the Button B1 */ 36 | RCC->AHBENR |= (1U << 2); 37 | 38 | /* configure Button (PC.13) pins as input, no pull-up, pull-down */ 39 | GPIOC->MODER &= ~(3U << 2*13); 40 | GPIOC->OSPEEDR &= ~(3U << 2*13); 41 | GPIOC->OSPEEDR |= (1U << 2*13); 42 | GPIOC->PUPDR &= ~(3U << 2*13); 43 | } 44 | 45 | void BSP_ledRedOn(void) { 46 | /* no red LED on board */ 47 | } 48 | 49 | void BSP_ledRedOff(void) { 50 | /* no red LED on board */ 51 | } 52 | 53 | void BSP_ledBlueOn(void) { 54 | /* no blue LED on board */ 55 | } 56 | 57 | void BSP_ledBlueOff(void) { 58 | /* no blue LED on board */ 59 | } 60 | 61 | void BSP_ledGreenOn(void) { 62 | GPIOA->BSRRL |= LED_LD2; /* turn LED on */ 63 | } 64 | 65 | void BSP_ledGreenOff(void) { 66 | GPIOA->BSRRH |= LED_LD2; /* turn LED off */ 67 | } 68 | 69 | void OS_onStartup(void) { 70 | SystemCoreClockUpdate(); 71 | SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC); 72 | 73 | /* set the SysTick interrupt priority (highest) */ 74 | NVIC_SetPriority(SysTick_IRQn, 0U); 75 | } 76 | 77 | void OS_onIdle(void) { 78 | #ifdef NDBEBUG 79 | __WFI(); /* stop the CPU and Wait for Interrupt */ 80 | #endif 81 | } 82 | 83 | void Q_onAssert(char const *module, int loc) { 84 | /* TBD: damage control */ 85 | (void)module; /* avoid the "unused parameter" compiler warning */ 86 | (void)loc; /* avoid the "unused parameter" compiler warning */ 87 | NVIC_SystemReset(); 88 | } 89 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-l152re/bsp.h: -------------------------------------------------------------------------------- 1 | #ifndef __BSP_H__ 2 | #define __BSP_H__ 3 | 4 | /* system clock tick [Hz] */ 5 | #define BSP_TICKS_PER_SEC 100U 6 | 7 | void BSP_init(void); 8 | 9 | void BSP_ledRedOn(void); 10 | void BSP_ledRedOff(void); 11 | 12 | void BSP_ledBlueOn(void); 13 | void BSP_ledBlueOff(void); 14 | 15 | void BSP_ledGreenOn(void); 16 | void BSP_ledGreenOff(void); 17 | 18 | #endif // __BSP_H__ 19 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-l152re/gnu/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # MInimal Real-time Operating System (MiROS), GNU-ARM port. 3 | # version 1.26 (matching lesson 26, see https://youtu.be/kLxxXNCrY60) 4 | # 5 | # This software is a teaching aid to illustrate the concepts underlying 6 | # a Real-Time Operating System (RTOS). The main goal of the software is 7 | # simplicity and clear presentation of the concepts, but without dealing 8 | # with various corner cases, portability, or error handling. For these 9 | # reasons, the software is generally NOT intended or recommended for use 10 | # in commercial applications. 11 | # 12 | # Copyright (C) 2018 Miro Samek. All Rights Reserved. 13 | # 14 | # SPDX-License-Identifier: GPL-3.0-or-later 15 | # 16 | # This program is free software: you can redistribute it and/or modify 17 | # it under the terms of the GNU General Public License as published by 18 | # the Free Software Foundation, either version 3 of the License, or 19 | # (at your option) any later version. 20 | # 21 | # This program is distributed in the hope that it will be useful, 22 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | # GNU General Public License for more details. 25 | # 26 | # You should have received a copy of the GNU General Public License 27 | # along with this program. If not, see . 28 | # 29 | # Git repo: 30 | # https://github.com/QuantumLeaps/MiROS 31 | ############################################################################## 32 | # examples of invoking this Makefile: 33 | # building configurations: Debug (default), Release, and Spy 34 | # make 35 | # make CONF=rel 36 | # 37 | # cleaning configurations: Debug (default), Release, and Spy 38 | # make clean 39 | # make CONF=rel clean 40 | # 41 | # NOTE: 42 | # To use this Makefile on Windows, you will need the GNU make utility, which 43 | # is included in the Qtools collection for Windows, see: 44 | # https://github.com/QuantumLeaps/qtools 45 | # 46 | 47 | #----------------------------------------------------------------------------- 48 | # project name 49 | # 50 | PROJECT := project 51 | 52 | #----------------------------------------------------------------------------- 53 | # project directories 54 | # 55 | 56 | # list of all source directories used by this project 57 | VPATH = \ 58 | .. \ 59 | ../../../src/gnu \ 60 | ../../../3rd_party/nucleo-l152re \ 61 | ../../../3rd_party/nucleo-l152re/gnu 62 | 63 | # list of all include directories needed by this project 64 | INCLUDES = \ 65 | -I.. \ 66 | -I../../../include \ 67 | -I../../../3rd_party/CMSIS/Include \ 68 | -I../../../3rd_party/nucleo-l152re 69 | 70 | #----------------------------------------------------------------------------- 71 | # files 72 | # 73 | 74 | # assembler source files 75 | ASM_SRCS := 76 | 77 | # C source files 78 | C_SRCS := \ 79 | main.c \ 80 | bsp.c \ 81 | miros.c \ 82 | system_stm32l1xx.c \ 83 | startup_stm32l1xx.c 84 | 85 | # C++ source files 86 | CPP_SRCS := 87 | 88 | OUTPUT := $(PROJECT) 89 | LD_SCRIPT := $(PROJECT).ld 90 | 91 | LIB_DIRS := 92 | LIBS := 93 | 94 | # defines 95 | DEFINES := 96 | 97 | # ARM CPU, ARCH, FPU, and Float-ABI types... 98 | # ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4] 99 | # ARM_FPU: [ | vfp] 100 | # FLOAT_ABI: [ | soft | softfp | hard] 101 | # 102 | ARM_CPU := -mcpu=cortex-m3 103 | ARM_FPU := 104 | FLOAT_ABI := 105 | 106 | #----------------------------------------------------------------------------- 107 | # GNU-ARM toolset (NOTE: You need to adjust to your machine) 108 | # see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads 109 | # 110 | ifeq ($(GNU_ARM),) 111 | GNU_ARM := $(QTOOLS)/gnu_arm-none-eabi 112 | endif 113 | 114 | # make sure that the GNU-ARM toolset exists... 115 | ifeq ("$(wildcard $(GNU_ARM))","") 116 | $(error GNU_ARM toolset not found. Please adjust the Makefile) 117 | endif 118 | 119 | CC := $(GNU_ARM)/bin/arm-none-eabi-gcc 120 | CPP := $(GNU_ARM)/bin/arm-none-eabi-g++ 121 | AS := $(GNU_ARM)/bin/arm-none-eabi-as 122 | LINK := $(GNU_ARM)/bin/arm-none-eabi-gcc 123 | BIN := $(GNU_ARM)/bin/arm-none-eabi-objcopy 124 | 125 | 126 | ############################################################################## 127 | # Typically, you should not need to change anything below this line 128 | 129 | # basic utilities (included in Qtools for Windows), see: 130 | # http://sourceforge.net/projects/qpc/files/Qtools 131 | 132 | MKDIR := mkdir 133 | RM := rm 134 | 135 | #----------------------------------------------------------------------------- 136 | # build options for various configurations for ARM Cortex-M4F 137 | # 138 | 139 | # combine all the soruces... 140 | C_SRCS += $(QP_SRCS) 141 | ASM_SRCS += $(QP_ASMS) 142 | 143 | ifeq (rel, $(CONF)) # Release configuration .................................. 144 | 145 | BIN_DIR := rel 146 | 147 | ASFLAGS = $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU) 148 | 149 | CFLAGS = -c $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 150 | -ffunction-sections -fdata-sections \ 151 | -O1 $(INCLUDES) $(DEFINES) -DNDEBUG 152 | 153 | CPPFLAGS = -c $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 154 | -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \ 155 | -O1 $(INCLUDES) $(DEFINES) -DNDEBUG 156 | 157 | else # default Debug configuration .......................................... 158 | 159 | BIN_DIR := dbg 160 | 161 | ASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU) 162 | 163 | CFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 164 | -ffunction-sections -fdata-sections \ 165 | -O $(INCLUDES) $(DEFINES) 166 | 167 | CPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb -Wall \ 168 | -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \ 169 | -O $(INCLUDES) $(DEFINES) 170 | 171 | endif # ...................................................................... 172 | 173 | 174 | LINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \ 175 | -specs=nosys.specs -specs=nano.specs \ 176 | -Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS) 177 | 178 | 179 | ASM_OBJS := $(patsubst %.s,%.o, $(notdir $(ASM_SRCS))) 180 | C_OBJS := $(patsubst %.c,%.o, $(notdir $(C_SRCS))) 181 | CPP_OBJS := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS))) 182 | 183 | TARGET_BIN := $(BIN_DIR)/$(OUTPUT).bin 184 | TARGET_ELF := $(BIN_DIR)/$(OUTPUT).elf 185 | ASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS)) 186 | C_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(C_OBJS)) 187 | C_DEPS_EXT := $(patsubst %.o, %.d, $(C_OBJS_EXT)) 188 | CPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS)) 189 | CPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT)) 190 | 191 | # create $(BIN_DIR) if it does not exist 192 | ifeq ("$(wildcard $(BIN_DIR))","") 193 | $(shell $(MKDIR) $(BIN_DIR)) 194 | endif 195 | 196 | #----------------------------------------------------------------------------- 197 | # rules 198 | # 199 | 200 | all: $(TARGET_BIN) 201 | #all: $(TARGET_ELF) 202 | 203 | $(TARGET_BIN): $(TARGET_ELF) 204 | $(BIN) -O binary $< $@ 205 | 206 | $(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT) 207 | $(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS) 208 | 209 | $(BIN_DIR)/%.d : %.c 210 | $(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@ 211 | 212 | $(BIN_DIR)/%.d : %.cpp 213 | $(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@ 214 | 215 | $(BIN_DIR)/%.o : %.s 216 | $(AS) $(ASFLAGS) $< -o $@ 217 | 218 | $(BIN_DIR)/%.o : %.c 219 | $(CC) $(CFLAGS) $< -o $@ 220 | 221 | $(BIN_DIR)/%.o : %.cpp 222 | $(CPP) $(CPPFLAGS) $< -o $@ 223 | 224 | # include dependency files only if our goal depends on their existence 225 | ifneq ($(MAKECMDGOALS),clean) 226 | ifneq ($(MAKECMDGOALS),show) 227 | -include $(C_DEPS_EXT) $(CPP_DEPS_EXT) 228 | endif 229 | endif 230 | 231 | 232 | .PHONY : clean 233 | clean: 234 | -$(RM) $(BIN_DIR)/*.o \ 235 | $(BIN_DIR)/*.d \ 236 | $(BIN_DIR)/*.bin \ 237 | $(BIN_DIR)/*.elf \ 238 | $(BIN_DIR)/*.map 239 | 240 | show: 241 | @echo PROJECT = $(PROJECT) 242 | @echo CONF = $(CONF) 243 | @echo DEFINES = $(DEFINES) 244 | @echo ASM_FPU = $(ASM_FPU) 245 | @echo ASM_SRCS = $(ASM_SRCS) 246 | @echo C_SRCS = $(C_SRCS) 247 | @echo CPP_SRCS = $(CPP_SRCS) 248 | @echo ASM_OBJS_EXT = $(ASM_OBJS_EXT) 249 | @echo C_OBJS_EXT = $(C_OBJS_EXT) 250 | @echo C_DEPS_EXT = $(C_DEPS_EXT) 251 | @echo CPP_DEPS_EXT = $(CPP_DEPS_EXT) 252 | @echo TARGET_ELF = $(TARGET_ELF) 253 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-l152re/gnu/project.ld: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * Product: Linker script for for STM32L152RET6, GNU-ARM linker 3 | * Last Updated for Version: 5.9.8 4 | * Date of the Last Update: 2017-09-13 5 | * 6 | * Q u a n t u m L e a P s 7 | * --------------------------- 8 | * innovating embedded systems 9 | * 10 | * Copyright (C) Quantum Leaps, LLC. All rights reserved. 11 | * 12 | * This program is open source software: you can redistribute it and/or 13 | * modify it under the terms of the GNU General Public License as published 14 | * by the Free Software Foundation, either version 3 of the License, or 15 | * (at your option) any later version. 16 | * 17 | * Alternatively, this program may be distributed and modified under the 18 | * terms of Quantum Leaps commercial licenses, which expressly supersede 19 | * the GNU General Public License and are specifically designed for 20 | * licensees interested in retaining the proprietary status of their code. 21 | * 22 | * This program is distributed in the hope that it will be useful, 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | * GNU General Public License for more details. 26 | * 27 | * You should have received a copy of the GNU General Public License 28 | * along with this program. If not, see . 29 | * 30 | * Contact information: 31 | * https://state-machine.com 32 | * mailto:info@state-machine.com 33 | *****************************************************************************/ 34 | OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") 35 | OUTPUT_ARCH(arm) 36 | ENTRY(Reset_Handler) /* entry Point */ 37 | 38 | MEMORY { /* memory map of STM32L152RET6 */ 39 | ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512K 40 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K 41 | } 42 | 43 | /* The size of the stack used by the application. NOTE: you need to adjust */ 44 | STACK_SIZE = 1024; 45 | 46 | /* The size of the heap used by the application. NOTE: you need to adjust */ 47 | HEAP_SIZE = 0; 48 | 49 | SECTIONS { 50 | 51 | .isr_vector : { /* the vector table goes FIRST into ROM */ 52 | KEEP(*(.isr_vector)) /* vector table */ 53 | . = ALIGN(4); 54 | } >ROM 55 | 56 | .text : { /* code and constants */ 57 | . = ALIGN(4); 58 | *(.text) /* .text sections (code) */ 59 | *(.text*) /* .text* sections (code) */ 60 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 61 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 62 | 63 | KEEP (*(.init)) 64 | KEEP (*(.fini)) 65 | 66 | . = ALIGN(4); 67 | } >ROM 68 | 69 | .preinit_array : { 70 | PROVIDE_HIDDEN (__preinit_array_start = .); 71 | KEEP (*(.preinit_array*)) 72 | PROVIDE_HIDDEN (__preinit_array_end = .); 73 | } >ROM 74 | 75 | .init_array : { 76 | PROVIDE_HIDDEN (__init_array_start = .); 77 | KEEP (*(SORT(.init_array.*))) 78 | KEEP (*(.init_array*)) 79 | PROVIDE_HIDDEN (__init_array_end = .); 80 | } >ROM 81 | 82 | .fini_array : { 83 | PROVIDE_HIDDEN (__fini_array_start = .); 84 | KEEP (*(.fini_array*)) 85 | KEEP (*(SORT(.fini_array.*))) 86 | PROVIDE_HIDDEN (__fini_array_end = .); 87 | } >ROM 88 | 89 | _etext = .; /* global symbols at end of code */ 90 | 91 | .stack : { 92 | __stack_start__ = .; 93 | . = . + STACK_SIZE; 94 | . = ALIGN(4); 95 | __stack_end__ = .; 96 | } >RAM 97 | 98 | .data : AT (_etext) { 99 | __data_load = LOADADDR (.data); 100 | __data_start = .; 101 | *(.data) /* .data sections */ 102 | *(.data*) /* .data* sections */ 103 | . = ALIGN(4); 104 | __data_end__ = .; 105 | _edata = __data_end__; 106 | } >RAM 107 | 108 | .bss : { 109 | __bss_start__ = .; 110 | *(.bss) 111 | *(.bss*) 112 | *(COMMON) 113 | . = ALIGN(4); 114 | _ebss = .; /* define a global symbol at bss end */ 115 | __bss_end__ = .; 116 | } >RAM 117 | 118 | __exidx_start = .; 119 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM 120 | __exidx_end = .; 121 | 122 | PROVIDE ( end = _ebss ); 123 | PROVIDE ( _end = _ebss ); 124 | PROVIDE ( __end__ = _ebss ); 125 | 126 | .heap : { 127 | __heap_start__ = .; 128 | . = . + HEAP_SIZE; 129 | . = ALIGN(4); 130 | __heap_end__ = .; 131 | } >RAM 132 | 133 | /* Remove information from the standard libraries */ 134 | /DISCARD/ : { 135 | libc.a ( * ) 136 | libm.a ( * ) 137 | libgcc.a ( * ) 138 | } 139 | } 140 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-l152re/iar/project.eww: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | $WS_DIR$\project.ewp 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /examples/blinky_nucleo-l152re/iar/project.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20013FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 1024; 13 | define symbol __ICFEDIT_size_heap__ = 0; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | define symbol __region_EEPROM_start__ = 0x08080000; 33 | define symbol __region_EEPROM_end__ = 0x08083FFF; 34 | define region EEPROM_region = mem:[from __region_EEPROM_start__ to __region_EEPROM_end__]; 35 | 36 | place in EEPROM_region { section .eeprom }; -------------------------------------------------------------------------------- /examples/blinky_nucleo-l152re/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "miros.h" 3 | #include "bsp.h" 4 | 5 | uint32_t stack_blinky1[40]; 6 | OSThread blinky1; 7 | void main_blinky1() { 8 | while (1) { 9 | BSP_ledGreenOn(); 10 | OS_delay(BSP_TICKS_PER_SEC / 4U); 11 | BSP_ledGreenOff(); 12 | OS_delay(BSP_TICKS_PER_SEC * 3U / 4U); 13 | } 14 | } 15 | 16 | uint32_t stack_blinky2[40]; 17 | OSThread blinky2; 18 | void main_blinky2() { 19 | while (1) { 20 | BSP_ledBlueOn(); 21 | OS_delay(BSP_TICKS_PER_SEC / 2U); 22 | BSP_ledBlueOff(); 23 | OS_delay(BSP_TICKS_PER_SEC / 3U); 24 | } 25 | } 26 | 27 | uint32_t stack_blinky3[40]; 28 | OSThread blinky3; 29 | void main_blinky3() { 30 | while (1) { 31 | BSP_ledRedOn(); 32 | OS_delay(BSP_TICKS_PER_SEC / 3U); 33 | BSP_ledRedOff(); 34 | OS_delay(BSP_TICKS_PER_SEC * 3U / 5U); 35 | } 36 | } 37 | 38 | uint32_t stack_idleThread[40]; 39 | 40 | int main() { 41 | OS_init(stack_idleThread, sizeof(stack_idleThread)); 42 | BSP_init(); 43 | 44 | /* start blinky1 thread */ 45 | OSThread_start(&blinky1, 46 | 5U, /* priority */ 47 | &main_blinky1, 48 | stack_blinky1, sizeof(stack_blinky1)); 49 | 50 | /* start blinky2 thread */ 51 | OSThread_start(&blinky2, 52 | 2U, /* priority */ 53 | &main_blinky2, 54 | stack_blinky2, sizeof(stack_blinky2)); 55 | 56 | /* start blinky3 thread */ 57 | OSThread_start(&blinky3, 58 | 1U, /* priority */ 59 | &main_blinky3, 60 | stack_blinky3, sizeof(stack_blinky3)); 61 | 62 | /* transfer control to the RTOS to run the threads */ 63 | OS_run(); 64 | 65 | //return 0; 66 | } 67 | -------------------------------------------------------------------------------- /img/MiROS.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QuantumLeaps/MiROS/21ea718161a4b8f3dc6756e6d254fe32f9fa7ee1/img/MiROS.jpg -------------------------------------------------------------------------------- /img/bd_EK-TM4C123GXL.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QuantumLeaps/MiROS/21ea718161a4b8f3dc6756e6d254fe32f9fa7ee1/img/bd_EK-TM4C123GXL.png -------------------------------------------------------------------------------- /img/bd_NUCLEO-C031C6.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QuantumLeaps/MiROS/21ea718161a4b8f3dc6756e6d254fe32f9fa7ee1/img/bd_NUCLEO-C031C6.jpg -------------------------------------------------------------------------------- /img/bd_NUCLEO-L152RE.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QuantumLeaps/MiROS/21ea718161a4b8f3dc6756e6d254fe32f9fa7ee1/img/bd_NUCLEO-L152RE.png -------------------------------------------------------------------------------- /img/github-star.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/QuantumLeaps/MiROS/21ea718161a4b8f3dc6756e6d254fe32f9fa7ee1/img/github-star.jpg -------------------------------------------------------------------------------- /include/miros.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************** 2 | * MInimal Real-time Operating System (MiROS) 3 | * version 1.26 (matching lesson 26, see https://youtu.be/kLxxXNCrY60) 4 | * 5 | * This software is a teaching aid to illustrate the concepts underlying 6 | * a Real-Time Operating System (RTOS). The main goal of the software is 7 | * simplicity and clear presentation of the concepts, but without dealing 8 | * with various corner cases, portability, or error handling. For these 9 | * reasons, the software is generally NOT intended or recommended for use 10 | * in commercial applications. 11 | * 12 | * Copyright (C) 2018 Miro Samek. All Rights Reserved. 13 | * 14 | * SPDX-License-Identifier: GPL-3.0-or-later 15 | * 16 | * This program is free software: you can redistribute it and/or modify 17 | * it under the terms of the GNU General Public License as published by 18 | * the Free Software Foundation, either version 3 of the License, or 19 | * (at your option) any later version. 20 | * 21 | * This program is distributed in the hope that it will be useful, 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | * GNU General Public License for more details. 25 | * 26 | * You should have received a copy of the GNU General Public License 27 | * along with this program. If not, see . 28 | * 29 | * Git repo: 30 | * https://github.com/QuantumLeaps/MiROS 31 | ****************************************************************************/ 32 | #ifndef MIROS_H 33 | #define MIROS_H 34 | 35 | /* Thread Control Block (TCB) */ 36 | typedef struct { 37 | void *sp; /* stack pointer */ 38 | uint32_t timeout; /* timeout delay down-counter */ 39 | uint8_t prio; /* thread priority */ 40 | /* ... other attributes associated with a thread */ 41 | } OSThread; 42 | 43 | typedef void (*OSThreadHandler)(); 44 | 45 | void OS_init(void *stkSto, uint32_t stkSize); 46 | 47 | /* callback to handle the idle condition */ 48 | void OS_onIdle(void); 49 | 50 | /* this function must be called with interrupts DISABLED */ 51 | void OS_sched(void); 52 | 53 | /* transfer control to the RTOS to run the threads */ 54 | void OS_run(void); 55 | 56 | /* blocking delay */ 57 | void OS_delay(uint32_t ticks); 58 | 59 | /* process all timeouts */ 60 | void OS_tick(void); 61 | 62 | /* callback to configure and start interrupts */ 63 | void OS_onStartup(void); 64 | 65 | void OSThread_start( 66 | OSThread *me, 67 | uint8_t prio, /* thread priority */ 68 | OSThreadHandler threadHandler, 69 | void *stkSto, uint32_t stkSize); 70 | 71 | #endif /* MIROS_H */ 72 | -------------------------------------------------------------------------------- /src/armclang/miros.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************** 2 | * MInimal Real-time Operating System (MiROS), ARM-CLANG port. 3 | * version 1.26 (matching lesson 26, see https://youtu.be/kLxxXNCrY60) 4 | * 5 | * This software is a teaching aid to illustrate the concepts underlying 6 | * a Real-Time Operating System (RTOS). The main goal of the software is 7 | * simplicity and clear presentation of the concepts, but without dealing 8 | * with various corner cases, portability, or error handling. For these 9 | * reasons, the software is generally NOT intended or recommended for use 10 | * in commercial applications. 11 | * 12 | * Copyright (C) 2018 Miro Samek. All Rights Reserved. 13 | * 14 | * SPDX-License-Identifier: GPL-3.0-or-later 15 | * 16 | * This program is free software: you can redistribute it and/or modify 17 | * it under the terms of the GNU General Public License as published by 18 | * the Free Software Foundation, either version 3 of the License, or 19 | * (at your option) any later version. 20 | * 21 | * This program is distributed in the hope that it will be useful, 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | * GNU General Public License for more details. 25 | * 26 | * You should have received a copy of the GNU General Public License 27 | * along with this program. If not, see . 28 | * 29 | * Git repo: 30 | * https://github.com/QuantumLeaps/MiROS 31 | ****************************************************************************/ 32 | #include 33 | #include "miros.h" 34 | #include "qassert.h" 35 | 36 | Q_DEFINE_THIS_FILE 37 | 38 | OSThread * volatile OS_curr; /* pointer to the current thread */ 39 | OSThread * volatile OS_next; /* pointer to the next thread to run */ 40 | 41 | OSThread *OS_thread[32 + 1]; /* array of threads started so far */ 42 | uint32_t OS_readySet; /* bitmask of threads that are ready to run */ 43 | uint32_t OS_delayedSet; /* bitmask of threads that are delayed */ 44 | 45 | #define LOG2(x) (32U - __builtin_clz(x)) 46 | 47 | OSThread idleThread; 48 | void main_idleThread() { 49 | while (1) { 50 | OS_onIdle(); 51 | } 52 | } 53 | 54 | void OS_init(void *stkSto, uint32_t stkSize) { 55 | /* set the PendSV interrupt priority to the lowest level 0xFF */ 56 | *(uint32_t volatile *)0xE000ED20 |= (0xFFU << 16); 57 | 58 | /* start idleThread thread */ 59 | OSThread_start(&idleThread, 60 | 0U, /* idle thread priority */ 61 | &main_idleThread, 62 | stkSto, stkSize); 63 | } 64 | 65 | void OS_sched(void) { 66 | /* choose the next thread to execute... */ 67 | OSThread *next; 68 | if (OS_readySet == 0U) { /* idle condition? */ 69 | next = OS_thread[0]; /* the idle thread */ 70 | } 71 | else { 72 | next = OS_thread[LOG2(OS_readySet)]; 73 | Q_ASSERT(next != (OSThread *)0); 74 | } 75 | 76 | /* trigger PendSV, if needed */ 77 | if (next != OS_curr) { 78 | OS_next = next; 79 | *(uint32_t volatile *)0xE000ED04 = (1U << 28); 80 | } 81 | } 82 | 83 | void OS_run(void) { 84 | /* callback to configure and start interrupts */ 85 | OS_onStartup(); 86 | 87 | __asm volatile ("cpsid i"); 88 | OS_sched(); 89 | __asm volatile ("cpsie i"); 90 | 91 | /* the following code should never execute */ 92 | Q_ERROR(); 93 | } 94 | 95 | void OS_tick(void) { 96 | uint32_t workingSet = OS_delayedSet; 97 | while (workingSet != 0U) { 98 | OSThread *t = OS_thread[LOG2(workingSet)]; 99 | uint32_t bit; 100 | Q_ASSERT((t != (OSThread *)0) && (t->timeout != 0U)); 101 | 102 | bit = (1U << (t->prio - 1U)); 103 | --t->timeout; 104 | if (t->timeout == 0U) { 105 | OS_readySet |= bit; /* insert to set */ 106 | OS_delayedSet &= ~bit; /* remove from set */ 107 | } 108 | workingSet &= ~bit; /* remove from working set */ 109 | } 110 | } 111 | 112 | void OS_delay(uint32_t ticks) { 113 | uint32_t bit; 114 | __asm volatile ("cpsid i"); 115 | 116 | /* never call OS_delay from the idleThread */ 117 | Q_REQUIRE(OS_curr != OS_thread[0]); 118 | 119 | OS_curr->timeout = ticks; 120 | bit = (1U << (OS_curr->prio - 1U)); 121 | OS_readySet &= ~bit; 122 | OS_delayedSet |= bit; 123 | OS_sched(); 124 | __asm volatile ("cpsie i"); 125 | } 126 | 127 | void OSThread_start( 128 | OSThread *me, 129 | uint8_t prio, /* thread priority */ 130 | OSThreadHandler threadHandler, 131 | void *stkSto, uint32_t stkSize) 132 | { 133 | /* round down the stack top to the 8-byte boundary 134 | * NOTE: ARM Cortex-M stack grows down from hi -> low memory 135 | */ 136 | uint32_t *sp = (uint32_t *)((((uint32_t)stkSto + stkSize) / 8) * 8); 137 | uint32_t *stk_limit; 138 | 139 | /* priority must be in ragne 140 | * and the priority level must be unused 141 | */ 142 | Q_REQUIRE((prio < Q_DIM(OS_thread)) 143 | && (OS_thread[prio] == (OSThread *)0)); 144 | 145 | *(--sp) = (1U << 24); /* xPSR */ 146 | *(--sp) = (uint32_t)threadHandler; /* PC */ 147 | *(--sp) = 0x0000000EU; /* LR */ 148 | *(--sp) = 0x0000000CU; /* R12 */ 149 | *(--sp) = 0x00000003U; /* R3 */ 150 | *(--sp) = 0x00000002U; /* R2 */ 151 | *(--sp) = 0x00000001U; /* R1 */ 152 | *(--sp) = 0x00000000U; /* R0 */ 153 | /* additionally, fake registers R4-R11 */ 154 | *(--sp) = 0x0000000BU; /* R11 */ 155 | *(--sp) = 0x0000000AU; /* R10 */ 156 | *(--sp) = 0x00000009U; /* R9 */ 157 | *(--sp) = 0x00000008U; /* R8 */ 158 | *(--sp) = 0x00000007U; /* R7 */ 159 | *(--sp) = 0x00000006U; /* R6 */ 160 | *(--sp) = 0x00000005U; /* R5 */ 161 | *(--sp) = 0x00000004U; /* R4 */ 162 | 163 | /* save the top of the stack in the thread's attibute */ 164 | me->sp = sp; 165 | 166 | /* round up the bottom of the stack to the 8-byte boundary */ 167 | stk_limit = (uint32_t *)(((((uint32_t)stkSto - 1U) / 8) + 1U) * 8); 168 | 169 | /* pre-fill the unused part of the stack with 0xDEADBEEF */ 170 | for (sp = sp - 1U; sp >= stk_limit; --sp) { 171 | *sp = 0xDEADBEEFU; 172 | } 173 | 174 | /* register the thread with the OS */ 175 | OS_thread[prio] = me; 176 | me->prio = prio; 177 | /* make the thread ready to run */ 178 | if (prio > 0U) { 179 | OS_readySet |= (1U << (prio - 1U)); 180 | } 181 | } 182 | 183 | /* inline assembly syntax for Compiler 6 (ARMCLANG) */ 184 | __attribute__ ((naked)) 185 | void PendSV_Handler(void) { 186 | __asm volatile ( 187 | /* __disable_irq(); */ 188 | " CPSID I \n" 189 | 190 | /* if (OS_curr != (OSThread *)0) { */ 191 | " LDR r1,=OS_curr \n" 192 | " LDR r1,[r1,#0x00] \n" 193 | " CMP r1,#0 \n" 194 | " BEQ PendSV_restore \n" 195 | 196 | /* push registers r4-r11 on the stack */ 197 | #if (__ARM_ARCH == 6) // if ARMv6-M... 198 | " SUB sp,sp,#(8*4) \n" // make room for 8 registers r4-r11 199 | " MOV r0,sp \n" // r0 := temporary stack pointer 200 | " STMIA r0!,{r4-r7} \n" // save the low registers 201 | " MOV r4,r8 \n" // move the high registers to low registers... 202 | " MOV r5,r9 \n" 203 | " MOV r6,r10 \n" 204 | " MOV r7,r11 \n" 205 | " STMIA r0!,{r4-r7} \n" // save the high registers 206 | #else // ARMv7-M or higher 207 | " PUSH {r4-r11} \n" 208 | #endif // ARMv7-M or higher 209 | 210 | /* OS_curr->sp = sp; */ 211 | " LDR r1,=OS_curr \n" 212 | " LDR r1,[r1,#0x00] \n" 213 | " MOV r0,sp \n" 214 | " STR r0,[r1,#0x00] \n" 215 | /* } */ 216 | 217 | "PendSV_restore: \n" 218 | /* sp = OS_next->sp; */ 219 | " LDR r1,=OS_next \n" 220 | " LDR r1,[r1,#0x00] \n" 221 | " LDR r0,[r1,#0x00] \n" 222 | " MOV sp,r0 \n" 223 | 224 | /* OS_curr = OS_next; */ 225 | " LDR r1,=OS_next \n" 226 | " LDR r1,[r1,#0x00] \n" 227 | " LDR r2,=OS_curr \n" 228 | " STR r1,[r2,#0x00] \n" 229 | 230 | /* pop registers r4-r11 */ 231 | #if (__ARM_ARCH == 6) // if ARMv6-M... 232 | " MOV r0,sp \n" // r0 := top of stack 233 | " MOV r2,r0 \n" 234 | " ADDS r2,r2,#(4*4) \n" // point r2 to the 4 high registers r7-r11 235 | " LDMIA r2!,{r4-r7} \n" // pop the 4 high registers into low registers 236 | " MOV r8,r4 \n" // move low registers into high registers 237 | " MOV r9,r5 \n" 238 | " MOV r10,r6 \n" 239 | " MOV r11,r7 \n" 240 | " LDMIA r0!,{r4-r7} \n" // pop the low registers 241 | " ADD sp,sp,#(8*4) \n" // remove 8 registers from the stack 242 | #else // ARMv7-M or higher 243 | " POP {r4-r11} \n" 244 | #endif // ARMv7-M or higher 245 | 246 | /* __enable_irq(); */ 247 | " CPSIE I \n" 248 | 249 | /* return to the next thread */ 250 | " BX lr \n" 251 | ); 252 | } 253 | -------------------------------------------------------------------------------- /src/gnu/miros.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************** 2 | * MInimal Real-time Operating System (MiROS), GNU-ARM port. 3 | * version 1.26 (matching lesson 26, see https://youtu.be/kLxxXNCrY60) 4 | * 5 | * This software is a teaching aid to illustrate the concepts underlying 6 | * a Real-Time Operating System (RTOS). The main goal of the software is 7 | * simplicity and clear presentation of the concepts, but without dealing 8 | * with various corner cases, portability, or error handling. For these 9 | * reasons, the software is generally NOT intended or recommended for use 10 | * in commercial applications. 11 | * 12 | * Copyright (C) 2018 Miro Samek. All Rights Reserved. 13 | * 14 | * SPDX-License-Identifier: GPL-3.0-or-later 15 | * 16 | * This program is free software: you can redistribute it and/or modify 17 | * it under the terms of the GNU General Public License as published by 18 | * the Free Software Foundation, either version 3 of the License, or 19 | * (at your option) any later version. 20 | * 21 | * This program is distributed in the hope that it will be useful, 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | * GNU General Public License for more details. 25 | * 26 | * You should have received a copy of the GNU General Public License 27 | * along with this program. If not, see . 28 | * 29 | * Git repo: 30 | * https://github.com/QuantumLeaps/MiROS 31 | ****************************************************************************/ 32 | #include 33 | #include "miros.h" 34 | #include "qassert.h" 35 | 36 | Q_DEFINE_THIS_FILE 37 | 38 | OSThread * volatile OS_curr; /* pointer to the current thread */ 39 | OSThread * volatile OS_next; /* pointer to the next thread to run */ 40 | 41 | OSThread *OS_thread[32 + 1]; /* array of threads started so far */ 42 | uint32_t OS_readySet; /* bitmask of threads that are ready to run */ 43 | uint32_t OS_delayedSet; /* bitmask of threads that are delayed */ 44 | 45 | #define LOG2(x) (32U - __builtin_clz(x)) 46 | 47 | OSThread idleThread; 48 | void main_idleThread() { 49 | while (1) { 50 | OS_onIdle(); 51 | } 52 | } 53 | 54 | void OS_init(void *stkSto, uint32_t stkSize) { 55 | /* set the PendSV interrupt priority to the lowest level 0xFF */ 56 | *(uint32_t volatile *)0xE000ED20 |= (0xFFU << 16); 57 | 58 | /* start idleThread thread */ 59 | OSThread_start(&idleThread, 60 | 0U, /* idle thread priority */ 61 | &main_idleThread, 62 | stkSto, stkSize); 63 | } 64 | 65 | void OS_sched(void) { 66 | /* choose the next thread to execute... */ 67 | OSThread *next; 68 | if (OS_readySet == 0U) { /* idle condition? */ 69 | next = OS_thread[0]; /* the idle thread */ 70 | } 71 | else { 72 | next = OS_thread[LOG2(OS_readySet)]; 73 | Q_ASSERT(next != (OSThread *)0); 74 | } 75 | 76 | /* trigger PendSV, if needed */ 77 | if (next != OS_curr) { 78 | OS_next = next; 79 | *(uint32_t volatile *)0xE000ED04 = (1U << 28); 80 | } 81 | } 82 | 83 | void OS_run(void) { 84 | /* callback to configure and start interrupts */ 85 | OS_onStartup(); 86 | 87 | __asm volatile ("cpsid i"); 88 | OS_sched(); 89 | __asm volatile ("cpsie i"); 90 | 91 | /* the following code should never execute */ 92 | Q_ERROR(); 93 | } 94 | 95 | void OS_tick(void) { 96 | uint32_t workingSet = OS_delayedSet; 97 | while (workingSet != 0U) { 98 | OSThread *t = OS_thread[LOG2(workingSet)]; 99 | uint32_t bit; 100 | Q_ASSERT((t != (OSThread *)0) && (t->timeout != 0U)); 101 | 102 | bit = (1U << (t->prio - 1U)); 103 | --t->timeout; 104 | if (t->timeout == 0U) { 105 | OS_readySet |= bit; /* insert to set */ 106 | OS_delayedSet &= ~bit; /* remove from set */ 107 | } 108 | workingSet &= ~bit; /* remove from working set */ 109 | } 110 | } 111 | 112 | void OS_delay(uint32_t ticks) { 113 | uint32_t bit; 114 | __asm volatile ("cpsid i"); 115 | 116 | /* never call OS_delay from the idleThread */ 117 | Q_REQUIRE(OS_curr != OS_thread[0]); 118 | 119 | OS_curr->timeout = ticks; 120 | bit = (1U << (OS_curr->prio - 1U)); 121 | OS_readySet &= ~bit; 122 | OS_delayedSet |= bit; 123 | OS_sched(); 124 | __asm volatile ("cpsie i"); 125 | } 126 | 127 | void OSThread_start( 128 | OSThread *me, 129 | uint8_t prio, /* thread priority */ 130 | OSThreadHandler threadHandler, 131 | void *stkSto, uint32_t stkSize) 132 | { 133 | /* round down the stack top to the 8-byte boundary 134 | * NOTE: ARM Cortex-M stack grows down from hi -> low memory 135 | */ 136 | uint32_t *sp = (uint32_t *)((((uint32_t)stkSto + stkSize) / 8) * 8); 137 | uint32_t *stk_limit; 138 | 139 | /* priority must be in ragne 140 | * and the priority level must be unused 141 | */ 142 | Q_REQUIRE((prio < Q_DIM(OS_thread)) 143 | && (OS_thread[prio] == (OSThread *)0)); 144 | 145 | *(--sp) = (1U << 24); /* xPSR */ 146 | *(--sp) = (uint32_t)threadHandler; /* PC */ 147 | *(--sp) = 0x0000000EU; /* LR */ 148 | *(--sp) = 0x0000000CU; /* R12 */ 149 | *(--sp) = 0x00000003U; /* R3 */ 150 | *(--sp) = 0x00000002U; /* R2 */ 151 | *(--sp) = 0x00000001U; /* R1 */ 152 | *(--sp) = 0x00000000U; /* R0 */ 153 | /* additionally, fake registers R4-R11 */ 154 | *(--sp) = 0x0000000BU; /* R11 */ 155 | *(--sp) = 0x0000000AU; /* R10 */ 156 | *(--sp) = 0x00000009U; /* R9 */ 157 | *(--sp) = 0x00000008U; /* R8 */ 158 | *(--sp) = 0x00000007U; /* R7 */ 159 | *(--sp) = 0x00000006U; /* R6 */ 160 | *(--sp) = 0x00000005U; /* R5 */ 161 | *(--sp) = 0x00000004U; /* R4 */ 162 | 163 | /* save the top of the stack in the thread's attibute */ 164 | me->sp = sp; 165 | 166 | /* round up the bottom of the stack to the 8-byte boundary */ 167 | stk_limit = (uint32_t *)(((((uint32_t)stkSto - 1U) / 8) + 1U) * 8); 168 | 169 | /* pre-fill the unused part of the stack with 0xDEADBEEF */ 170 | for (sp = sp - 1U; sp >= stk_limit; --sp) { 171 | *sp = 0xDEADBEEFU; 172 | } 173 | 174 | /* register the thread with the OS */ 175 | OS_thread[prio] = me; 176 | me->prio = prio; 177 | /* make the thread ready to run */ 178 | if (prio > 0U) { 179 | OS_readySet |= (1U << (prio - 1U)); 180 | } 181 | } 182 | 183 | /* inline assembly syntax for GNU-ARM */ 184 | __attribute__ ((naked, optimize("-fno-stack-protector"))) 185 | void PendSV_Handler(void) { 186 | __asm volatile ( 187 | /* __disable_irq(); */ 188 | " CPSID I \n" 189 | 190 | /* if (OS_curr != (OSThread *)0) { */ 191 | " LDR r1,=OS_curr \n" 192 | " LDR r1,[r1,#0x00] \n" 193 | " CMP r1,#0 \n" 194 | " BEQ PendSV_restore \n" 195 | 196 | /* push registers r4-r11 on the stack */ 197 | #if (__ARM_ARCH == 6) // if ARMv6-M... 198 | " SUB sp,sp,#(8*4) \n" // make room for 8 registers r4-r11 199 | " MOV r0,sp \n" // r0 := temporary stack pointer 200 | " STMIA r0!,{r4-r7} \n" // save the low registers 201 | " MOV r4,r8 \n" // move the high registers to low registers... 202 | " MOV r5,r9 \n" 203 | " MOV r6,r10 \n" 204 | " MOV r7,r11 \n" 205 | " STMIA r0!,{r4-r7} \n" // save the high registers 206 | #else // ARMv7-M or higher 207 | " PUSH {r4-r11} \n" 208 | #endif // ARMv7-M or higher 209 | 210 | /* OS_curr->sp = sp; */ 211 | " LDR r1,=OS_curr \n" 212 | " LDR r1,[r1,#0x00] \n" 213 | " MOV r0,sp \n" 214 | " STR r0,[r1,#0x00] \n" 215 | /* } */ 216 | 217 | "PendSV_restore: \n" 218 | /* sp = OS_next->sp; */ 219 | " LDR r1,=OS_next \n" 220 | " LDR r1,[r1,#0x00] \n" 221 | " LDR r0,[r1,#0x00] \n" 222 | " MOV sp,r0 \n" 223 | 224 | /* OS_curr = OS_next; */ 225 | " LDR r1,=OS_next \n" 226 | " LDR r1,[r1,#0x00] \n" 227 | " LDR r2,=OS_curr \n" 228 | " STR r1,[r2,#0x00] \n" 229 | 230 | /* pop registers r4-r11 */ 231 | #if (__ARM_ARCH == 6) // if ARMv6-M... 232 | " MOV r0,sp \n" // r0 := top of stack 233 | " MOV r2,r0 \n" 234 | " ADD r2,r2,#(4*4) \n" // point r2 to the 4 high registers r7-r11 235 | " LDMIA r2!,{r4-r7} \n" // pop the 4 high registers into low registers 236 | " MOV r8,r4 \n" // move low registers into high registers 237 | " MOV r9,r5 \n" 238 | " MOV r10,r6 \n" 239 | " MOV r11,r7 \n" 240 | " LDMIA r0!,{r4-r7} \n" // pop the low registers 241 | " ADD sp,sp,#(8*4) \n" // remove 8 registers from the stack 242 | #else // ARMv7-M or higher 243 | " POP {r4-r11} \n" 244 | #endif // ARMv7-M or higher 245 | 246 | /* __enable_irq(); */ 247 | " CPSIE I \n" 248 | 249 | /* return to the next thread */ 250 | " BX lr \n" 251 | ); 252 | } 253 | -------------------------------------------------------------------------------- /src/iar/miros.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************** 2 | * MInimal Real-time Operating System (MiROS), IAR EWARM port. 3 | * version 1.26 (matching lesson 26, see https://youtu.be/kLxxXNCrY60) 4 | * 5 | * This software is a teaching aid to illustrate the concepts underlying 6 | * a Real-Time Operating System (RTOS). The main goal of the software is 7 | * simplicity and clear presentation of the concepts, but without dealing 8 | * with various corner cases, portability, or error handling. For these 9 | * reasons, the software is generally NOT intended or recommended for use 10 | * in commercial applications. 11 | * 12 | * Copyright (C) 2018 Miro Samek. All Rights Reserved. 13 | * 14 | * SPDX-License-Identifier: GPL-3.0-or-later 15 | * 16 | * This program is free software: you can redistribute it and/or modify 17 | * it under the terms of the GNU General Public License as published by 18 | * the Free Software Foundation, either version 3 of the License, or 19 | * (at your option) any later version. 20 | * 21 | * This program is distributed in the hope that it will be useful, 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | * GNU General Public License for more details. 25 | * 26 | * You should have received a copy of the GNU General Public License 27 | * along with this program. If not, see . 28 | * 29 | * Git repo: 30 | * https://github.com/QuantumLeaps/MiROS 31 | ****************************************************************************/ 32 | #include 33 | #include /* IAR intrinsic functions */ 34 | 35 | #include "miros.h" 36 | #include "qassert.h" 37 | 38 | Q_DEFINE_THIS_FILE 39 | 40 | OSThread * volatile OS_curr; /* pointer to the current thread */ 41 | OSThread * volatile OS_next; /* pointer to the next thread to run */ 42 | 43 | OSThread *OS_thread[32 + 1]; /* array of threads started so far */ 44 | uint32_t OS_readySet; /* bitmask of threads that are ready to run */ 45 | uint32_t OS_delayedSet; /* bitmask of threads that are delayed */ 46 | 47 | #define LOG2(x) (32U - __CLZ(x)) 48 | 49 | OSThread idleThread; 50 | void main_idleThread() { 51 | while (1) { 52 | OS_onIdle(); 53 | } 54 | } 55 | 56 | void OS_init(void *stkSto, uint32_t stkSize) { 57 | /* set the PendSV interrupt priority to the lowest level 0xFF */ 58 | *(uint32_t volatile *)0xE000ED20 |= (0xFFU << 16); 59 | 60 | /* start idleThread thread */ 61 | OSThread_start(&idleThread, 62 | 0U, /* idle thread priority */ 63 | &main_idleThread, 64 | stkSto, stkSize); 65 | } 66 | 67 | void OS_sched(void) { 68 | /* choose the next thread to execute... */ 69 | OSThread *next; 70 | if (OS_readySet == 0U) { /* idle condition? */ 71 | next = OS_thread[0]; /* the idle thread */ 72 | } 73 | else { 74 | next = OS_thread[LOG2(OS_readySet)]; 75 | Q_ASSERT(next != (OSThread *)0); 76 | } 77 | 78 | /* trigger PendSV, if needed */ 79 | if (next != OS_curr) { 80 | OS_next = next; 81 | *(uint32_t volatile *)0xE000ED04 = (1U << 28); 82 | } 83 | } 84 | 85 | void OS_run(void) { 86 | /* callback to configure and start interrupts */ 87 | OS_onStartup(); 88 | 89 | __disable_interrupt(); 90 | OS_sched(); 91 | __enable_interrupt(); 92 | 93 | /* the following code should never execute */ 94 | Q_ERROR(); 95 | } 96 | 97 | void OS_tick(void) { 98 | uint32_t workingSet = OS_delayedSet; 99 | while (workingSet != 0U) { 100 | OSThread *t = OS_thread[LOG2(workingSet)]; 101 | uint32_t bit; 102 | Q_ASSERT((t != (OSThread *)0) && (t->timeout != 0U)); 103 | 104 | bit = (1U << (t->prio - 1U)); 105 | --t->timeout; 106 | if (t->timeout == 0U) { 107 | OS_readySet |= bit; /* insert to set */ 108 | OS_delayedSet &= ~bit; /* remove from set */ 109 | } 110 | workingSet &= ~bit; /* remove from working set */ 111 | } 112 | } 113 | 114 | void OS_delay(uint32_t ticks) { 115 | uint32_t bit; 116 | __disable_interrupt(); 117 | 118 | /* never call OS_delay from the idleThread */ 119 | Q_REQUIRE(OS_curr != OS_thread[0]); 120 | 121 | OS_curr->timeout = ticks; 122 | bit = (1U << (OS_curr->prio - 1U)); 123 | OS_readySet &= ~bit; 124 | OS_delayedSet |= bit; 125 | OS_sched(); 126 | __enable_interrupt(); 127 | } 128 | 129 | void OSThread_start( 130 | OSThread *me, 131 | uint8_t prio, /* thread priority */ 132 | OSThreadHandler threadHandler, 133 | void *stkSto, uint32_t stkSize) 134 | { 135 | /* round down the stack top to the 8-byte boundary 136 | * NOTE: ARM Cortex-M stack grows down from hi -> low memory 137 | */ 138 | uint32_t *sp = (uint32_t *)((((uint32_t)stkSto + stkSize) / 8) * 8); 139 | uint32_t *stk_limit; 140 | 141 | /* priority must be in ragne 142 | * and the priority level must be unused 143 | */ 144 | Q_REQUIRE((prio < Q_DIM(OS_thread)) 145 | && (OS_thread[prio] == (OSThread *)0)); 146 | 147 | *(--sp) = (1U << 24); /* xPSR */ 148 | *(--sp) = (uint32_t)threadHandler; /* PC */ 149 | *(--sp) = 0x0000000EU; /* LR */ 150 | *(--sp) = 0x0000000CU; /* R12 */ 151 | *(--sp) = 0x00000003U; /* R3 */ 152 | *(--sp) = 0x00000002U; /* R2 */ 153 | *(--sp) = 0x00000001U; /* R1 */ 154 | *(--sp) = 0x00000000U; /* R0 */ 155 | /* additionally, fake registers R4-R11 */ 156 | *(--sp) = 0x0000000BU; /* R11 */ 157 | *(--sp) = 0x0000000AU; /* R10 */ 158 | *(--sp) = 0x00000009U; /* R9 */ 159 | *(--sp) = 0x00000008U; /* R8 */ 160 | *(--sp) = 0x00000007U; /* R7 */ 161 | *(--sp) = 0x00000006U; /* R6 */ 162 | *(--sp) = 0x00000005U; /* R5 */ 163 | *(--sp) = 0x00000004U; /* R4 */ 164 | 165 | /* save the top of the stack in the thread's attibute */ 166 | me->sp = sp; 167 | 168 | /* round up the bottom of the stack to the 8-byte boundary */ 169 | stk_limit = (uint32_t *)(((((uint32_t)stkSto - 1U) / 8) + 1U) * 8); 170 | 171 | /* pre-fill the unused part of the stack with 0xDEADBEEF */ 172 | for (sp = sp - 1U; sp >= stk_limit; --sp) { 173 | *sp = 0xDEADBEEFU; 174 | } 175 | 176 | /* register the thread with the OS */ 177 | OS_thread[prio] = me; 178 | me->prio = prio; 179 | /* make the thread ready to run */ 180 | if (prio > 0U) { 181 | OS_readySet |= (1U << (prio - 1U)); 182 | } 183 | } 184 | 185 | /* inline assembly syntax for IAR ARM */ 186 | __stackless 187 | void PendSV_Handler(void) { 188 | __asm volatile ( 189 | /* __disable_irq(); */ 190 | " CPSID I \n" 191 | 192 | /* if (OS_curr != (OSThread *)0) { */ 193 | " LDR r1,=OS_curr \n" 194 | " LDR r1,[r1,#0x00] \n" 195 | " CMP r1,#0 \n" 196 | " BEQ PendSV_restore \n" 197 | 198 | /* push registers r4-r11 on the stack */ 199 | #if (__ARM_ARCH == 6) // if ARMv6-M... 200 | " SUB sp,sp,#(8*4) \n" // make room for 8 registers r4-r11 201 | " MOV r0,sp \n" // r0 := temporary stack pointer 202 | " STMIA r0!,{r4-r7} \n" // save the low registers 203 | " MOV r4,r8 \n" // move the high registers to low registers... 204 | " MOV r5,r9 \n" 205 | " MOV r6,r10 \n" 206 | " MOV r7,r11 \n" 207 | " STMIA r0!,{r4-r7} \n" // save the high registers 208 | #else // ARMv7-M or higher 209 | " PUSH {r4-r11} \n" 210 | #endif // ARMv7-M or higher 211 | 212 | /* OS_curr->sp = sp; */ 213 | " LDR r1,=OS_curr \n" 214 | " LDR r1,[r1,#0x00] \n" 215 | " MOV r0,sp \n" 216 | " STR r0,[r1,#0x00] \n" 217 | /* } */ 218 | 219 | "PendSV_restore: \n" 220 | /* sp = OS_next->sp; */ 221 | " LDR r1,=OS_next \n" 222 | " LDR r1,[r1,#0x00] \n" 223 | " LDR r0,[r1,#0x00] \n" 224 | " MOV sp,r0 \n" 225 | 226 | /* OS_curr = OS_next; */ 227 | " LDR r1,=OS_next \n" 228 | " LDR r1,[r1,#0x00] \n" 229 | " LDR r2,=OS_curr \n" 230 | " STR r1,[r2,#0x00] \n" 231 | 232 | /* pop registers r4-r11 */ 233 | #if (__ARM_ARCH == 6) // if ARMv6-M... 234 | " MOV r0,sp \n" // r0 := top of stack 235 | " MOV r2,r0 \n" 236 | " ADDS r2,r2,#(4*4) \n" // point r2 to the 4 high registers r7-r11 237 | " LDMIA r2!,{r4-r7} \n" // pop the 4 high registers into low registers 238 | " MOV r8,r4 \n" // move low registers into high registers 239 | " MOV r9,r5 \n" 240 | " MOV r10,r6 \n" 241 | " MOV r11,r7 \n" 242 | " LDMIA r0!,{r4-r7} \n" // pop the low registers 243 | " ADD sp,sp,#(8*4) \n" // remove 8 registers from the stack 244 | #else // ARMv7-M or higher 245 | " POP {r4-r11} \n" 246 | #endif // ARMv7-M or higher 247 | 248 | /* __enable_irq(); */ 249 | " CPSIE I \n" 250 | 251 | /* return to the next thread */ 252 | " BX lr \n" 253 | ); 254 | } 255 | --------------------------------------------------------------------------------