├── Firmware ├── Sources │ ├── cscc.done │ ├── cscc.pof │ ├── cscc.sof │ ├── cscc.vhd │ ├── cscc.qws │ ├── cscc.dpf │ ├── cscc.map.summary │ ├── cscc.cdf │ ├── cscc.fit.summary │ ├── ram.vhd │ ├── cscc.qpf │ ├── cscc.tan.summary │ ├── lpm_ram.vhd │ ├── maxplusii_to_quartus_name_mapping.txt │ ├── cscc.asm.rpt │ ├── cscc.flow.rpt │ ├── cscc.qsf │ ├── scc_wave.vhd │ ├── scc_save1.vhd │ └── cscc.pin ├── carnivore.pof └── readme_firmware.txt ├── .gitattributes ├── Pics ├── help.jpg ├── menu.jpg ├── carnivore_back.jpg ├── carnivore_front.jpg ├── carnivore_back_fix.jpg └── readme_pics.txt ├── Util ├── cman.asm ├── cman.com ├── cman_40.asm └── cman_40.com ├── Board └── carnivore.pcb ├── Doc ├── disclaimer.txt ├── partslist.txt ├── registers_rus.txt └── readme.txt ├── Presets ├── ALESTE2.RCP ├── GBERET.RCP ├── MANBOW2.RCP ├── MGEAR2.RCP ├── XEVIOUS.RCP ├── 48K_GAME.RCP ├── 64K_GAME.RCP ├── 64K_MAPP.RCP ├── DONKKONG.RCP ├── NEWGOONI.RCP ├── SM_WORLD.RCP ├── SPYVSSPY.RCP └── presets_readme.txt ├── BootBlock ├── bootcscc.bin ├── NoEffects │ └── BOOTCSCC.BIN ├── readme_bblock.txt └── font.inc ├── Gerber ├── readme_gerber.txt ├── CRTPRT01.NCD ├── CRTPRT01.BDR ├── CRTPRT01.BMS └── CRTPRT01.TMS └── .gitignore /Firmware/Sources/cscc.done: -------------------------------------------------------------------------------- 1 | Wed Mar 02 18:58:08 2016 2 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | * linguist-vendored 2 | *.php linguist-vendored=false 3 | 4 | -------------------------------------------------------------------------------- /Pics/help.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Pics/help.jpg -------------------------------------------------------------------------------- /Pics/menu.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Pics/menu.jpg -------------------------------------------------------------------------------- /Util/cman.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Util/cman.asm -------------------------------------------------------------------------------- /Util/cman.com: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Util/cman.com -------------------------------------------------------------------------------- /Util/cman_40.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Util/cman_40.asm -------------------------------------------------------------------------------- /Util/cman_40.com: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Util/cman_40.com -------------------------------------------------------------------------------- /Board/carnivore.pcb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Board/carnivore.pcb -------------------------------------------------------------------------------- /Doc/disclaimer.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Doc/disclaimer.txt -------------------------------------------------------------------------------- /Presets/ALESTE2.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/ALESTE2.RCP -------------------------------------------------------------------------------- /Presets/GBERET.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/GBERET.RCP -------------------------------------------------------------------------------- /Presets/MANBOW2.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/MANBOW2.RCP -------------------------------------------------------------------------------- /Presets/MGEAR2.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/MGEAR2.RCP -------------------------------------------------------------------------------- /Presets/XEVIOUS.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/XEVIOUS.RCP -------------------------------------------------------------------------------- /Presets/48K_GAME.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/48K_GAME.RCP -------------------------------------------------------------------------------- /Presets/64K_GAME.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/64K_GAME.RCP -------------------------------------------------------------------------------- /Presets/64K_MAPP.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/64K_MAPP.RCP -------------------------------------------------------------------------------- /Presets/DONKKONG.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/DONKKONG.RCP -------------------------------------------------------------------------------- /Presets/NEWGOONI.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/NEWGOONI.RCP -------------------------------------------------------------------------------- /Presets/SM_WORLD.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/SM_WORLD.RCP -------------------------------------------------------------------------------- /Presets/SPYVSSPY.RCP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Presets/SPYVSSPY.RCP -------------------------------------------------------------------------------- /BootBlock/bootcscc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/BootBlock/bootcscc.bin -------------------------------------------------------------------------------- /Firmware/carnivore.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Firmware/carnivore.pof -------------------------------------------------------------------------------- /Pics/carnivore_back.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Pics/carnivore_back.jpg -------------------------------------------------------------------------------- /Pics/carnivore_front.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Pics/carnivore_front.jpg -------------------------------------------------------------------------------- /Firmware/Sources/cscc.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Firmware/Sources/cscc.pof -------------------------------------------------------------------------------- /Firmware/Sources/cscc.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Firmware/Sources/cscc.sof -------------------------------------------------------------------------------- /Firmware/Sources/cscc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Firmware/Sources/cscc.vhd -------------------------------------------------------------------------------- /Pics/carnivore_back_fix.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/Pics/carnivore_back_fix.jpg -------------------------------------------------------------------------------- /BootBlock/NoEffects/BOOTCSCC.BIN: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RBSC/Carnivore/HEAD/BootBlock/NoEffects/BOOTCSCC.BIN -------------------------------------------------------------------------------- /BootBlock/readme_bblock.txt: -------------------------------------------------------------------------------- 1 | Carnivore MultiFlash SCC Cartridge version 1.1 2 | Copyright (c) 2016 RBSC 3 | 4 | The Boot Block code and the custom font were created by RBSC. 5 | 6 | See the readme.txt file for more info. -------------------------------------------------------------------------------- /Firmware/Sources/cscc.qws: -------------------------------------------------------------------------------- 1 | [ProjectWorkspace] 2 | ptn_Child1=Frames 3 | [ProjectWorkspace.Frames] 4 | ptn_Child1=ChildFrames 5 | [ProjectWorkspace.Frames.ChildFrames] 6 | ptn_Child1=Document-0 7 | ptn_Child2=Document-1 8 | -------------------------------------------------------------------------------- /Gerber/readme_gerber.txt: -------------------------------------------------------------------------------- 1 | Carnivore MultiFlash SCC Cartridge version 1.1 2 | Copyright (c) 2016 RBSC 3 | 4 | The Gerber files were created by RBSC. Commercial usage is not allowed! 5 | 6 | See the readme.txt file for more info. 7 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.dpf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Wed Mar 02 18:57:45 2016 2 | Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version 3 | Revision Name : cscc 4 | Top-level Entity Name : cscc 5 | Family : FLEX10KA 6 | Total logic elements : 1,724 7 | Total pins : 91 8 | Total memory bits : 2,048 9 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EPC2) Path("K:/msx/ALTERA_S_MSX/aa/cssc/") File("cscc.pof") MfrSpec(OpMask(3)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /Firmware/readme_firmware.txt: -------------------------------------------------------------------------------- 1 | Carnivore MultiFlash SCC Cartridge version 1.1 2 | Copyright (c) 2016 RBSC 3 | Portions (c) Kazuhiro TSUJIKAWA 4 | 5 | The Altera firmware was created by RBSC. Commercial usage is not allowed! 6 | 7 | When the sources are used to create alternative projects, please always 8 | mention the original source and the copyright! 9 | 10 | See the readme.txt file for more info. 11 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Wed Mar 02 18:58:02 2016 2 | Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version 3 | Revision Name : cscc 4 | Top-level Entity Name : cscc 5 | Family : FLEX10KA 6 | Device : EPF10K100ARI240-3 7 | Timing Models : Final 8 | Total logic elements : 1,732 / 4,992 ( 35 % ) 9 | Total pins : 91 / 189 ( 48 % ) 10 | Total memory bits : 2,048 / 24,576 ( 8 % ) 11 | -------------------------------------------------------------------------------- /Pics/readme_pics.txt: -------------------------------------------------------------------------------- 1 | Carnivore MultiFlash SCC Cartridge version 1.1 2 | Copyright (c) 2016 RBSC 3 | 4 | The pictures are copyright by RBSC. Non-commercial usage is allowed. 5 | 6 | NOTE: 7 | ----- 8 | The C2 capacitor's polarity marking is wrong on the board v1.0. See the "carnivore_back_fix.jpg" image for correct 9 | polarity setting! 10 | 11 | The Altera chip on the picture is not MAX, it's FLEX. Looks like the Chinese clone manufacturers made mistake. 12 | 13 | See the readme.txt file for more info. 14 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Windows image file caches 2 | Thumbs.db 3 | ehthumbs.db 4 | 5 | # Folder config file 6 | Desktop.ini 7 | 8 | # Recycle Bin used on file shares 9 | $RECYCLE.BIN/ 10 | 11 | # Windows Installer files 12 | *.cab 13 | *.msi 14 | *.msm 15 | *.msp 16 | 17 | # Windows shortcuts 18 | *.lnk 19 | 20 | # ========================= 21 | # Operating System Files 22 | # ========================= 23 | 24 | # OSX 25 | # ========================= 26 | 27 | .DS_Store 28 | .AppleDouble 29 | .LSOverride 30 | 31 | # Thumbnails 32 | ._* 33 | 34 | # Files that might appear in the root of a volume 35 | .DocumentRevisions-V100 36 | .fseventsd 37 | .Spotlight-V100 38 | .TemporaryItems 39 | .Trashes 40 | .VolumeIcon.icns 41 | 42 | # Directories potentially created on remote AFP share 43 | .AppleDB 44 | .AppleDesktop 45 | Network Trash Folder 46 | Temporary Items 47 | .apdisk 48 | -------------------------------------------------------------------------------- /Doc/partslist.txt: -------------------------------------------------------------------------------- 1 | Carnivore MultiFlash SCC Cartridge version 1.1 2 | Copyright (c) 2016-2017 RBSC 3 | 4 | Partslist 5 | --------- 6 | 7 | ==- Microchips SMD -== 8 | 9 | U1 - Altera Flex EPF10K100ARI240-3 (PQFP208) 10 | U2 - M29W640GB Flash ROM (TSOP48) 11 | U3 - Altera EPC2LC20 12 | 13 | 14 | ==- Capacitors SMD 1210 -== 15 | 16 | C1,C2 - 10uF 10v 17 | 18 | C2 has wrong polarity marker on the board!!! 19 | 20 | 21 | ==- Capacitors SMD 0603 -== 22 | 23 | C3-C11,C16, C12-C14 - 0.1uF 24 | 25 | 26 | ==- Resistors SMD 0603 -== 27 | 28 | R1 -R41 - 100 Ohm 29 | R45-R50 - 1 kOhm 30 | R65 - 1 Ohm 31 | R52,53,54 - 1 kOhm 32 | R55,56,57 - 1 kOhm 33 | R58,59,60 - 6.2 kOhm 34 | 35 | 36 | ==- Voltage regulators -== 37 | 38 | LM1117ADJ 3.3v (SOT223) 39 | 40 | 41 | ==- Sockets -== 42 | AX1 - ST-222 (jack 3.5mm stereo) 43 | 44 | 45 | See the readme.txt file for more info. 46 | -------------------------------------------------------------------------------- /Presets/presets_readme.txt: -------------------------------------------------------------------------------- 1 | Register Configuration Presets 2 | Carnivore and Carnivore2 Cartridges 3 | Copyright (C) 2017 RBSC 4 | 5 | The RCP files should be loaded for certain ROM files or for ROM files of certain size. 6 | Below is the list of currently available RCP files and their descriptions. 7 | 8 | 48K_GAME.RCP - generic RCP file for 49152 byte ROMs without mapper (except for "Spy vs Spy") 9 | 64K_GAME.RCP - generic RCP file for 65535 byte ROMs without mapper 10 | 64K_MAPP.RCP - generic RCP file for 65535 byte ROMs with mapper 11 | MGEAR2.RCP - RCP file for "Metal Gear 2: Solid Snake game" (any version) 12 | NEWGOONI.RCP - RCP file for the "Goonies 'r' good enough" (remake of Goonies) 13 | SM_WORLD.RCP - RCP file for "Super Mario World" game 14 | SPYVBSPY.RCP - RCP file for "Spy vs Spy" game (any version) 15 | DONKKONG.RCP - RCP file for "Donkey Kong" game (both 49 and 64kb versions) 16 | GBERET.RCP - RCP file for "Green Beret" game -------------------------------------------------------------------------------- /Firmware/Sources/ram.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | use IEEE.std_logic_unsigned.all; 4 | 5 | entity ram is 6 | port ( 7 | address : in std_logic_vector(7 downto 0); 8 | inclock : in std_logic; 9 | we : in std_logic; 10 | data : in std_logic_vector(7 downto 0); 11 | q : out std_logic_vector(7 downto 0) 12 | ); 13 | end ram; 14 | 15 | architecture RTL of ram is 16 | type Mem is array (255 downto 0) of std_logic_vector(7 downto 0); 17 | signal WaveMem : Mem; 18 | signal iAddress : std_logic_vector(7 downto 0); 19 | 20 | begin 21 | 22 | process (inclock) 23 | begin 24 | if (inclock'event and inclock ='1') then 25 | if (we = '1') then 26 | WaveMem(conv_integer(address)) <= data; 27 | end if; 28 | iAddress <= address; 29 | end if; 30 | end process; 31 | 32 | q <= WaveMem(conv_integer(iAddress)); 33 | 34 | end RTL; 35 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2009 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 20 | # Version 9.0 Build 132 02/25/2009 SJ Full Version 21 | # Date created = 19:45:57 July 26, 2015 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "9.0" 26 | DATE = "19:45:57 July 26, 2015" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "cscc" 31 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.tan.summary: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------------- 2 | Timing Analyzer Summary 3 | -------------------------------------------------------------------------------------- 4 | 5 | Type : Worst-case tsu 6 | Slack : N/A 7 | Required Time : None 8 | Actual Time : 38.400 ns 9 | From : pSltAdr[7] 10 | To : aB1AdrD[4] 11 | From Clock : -- 12 | To Clock : pSltClk 13 | Failed Paths : 0 14 | 15 | Type : Worst-case tco 16 | Slack : N/A 17 | Required Time : None 18 | Actual Time : 70.400 ns 19 | From : Maddr[21] 20 | To : pFlAdr[22] 21 | From Clock : pSltAdr[14] 22 | To Clock : -- 23 | Failed Paths : 0 24 | 25 | Type : Worst-case tpd 26 | Slack : N/A 27 | Required Time : None 28 | Actual Time : 54.400 ns 29 | From : pSltAdr[14] 30 | To : pFlOE_n 31 | From Clock : -- 32 | To Clock : -- 33 | Failed Paths : 0 34 | 35 | Type : Worst-case th 36 | Slack : N/A 37 | Required Time : None 38 | Actual Time : 34.300 ns 39 | From : pSltAdr[12] 40 | To : Maddr[12] 41 | From Clock : -- 42 | To Clock : pSltAdr[14] 43 | Failed Paths : 0 44 | 45 | Type : Clock Setup: 'pSltClk' 46 | Slack : N/A 47 | Required Time : None 48 | Actual Time : 22.62 MHz ( period = 44.200 ns ) 49 | From : scc_wave:SccCh|ram:WaveMem|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[1]~reg_wa7 50 | To : scc_wave:SccCh|SccAmp[7] 51 | From Clock : pSltClk 52 | To Clock : pSltClk 53 | Failed Paths : 0 54 | 55 | Type : Clock Hold: 'pSltClk' 56 | Slack : Not operational: Clock Skew > Data Delay 57 | Required Time : None 58 | Actual Time : N/A 59 | From : B1MaskR[5] 60 | To : Maddr[21] 61 | From Clock : pSltClk 62 | To Clock : pSltClk 63 | Failed Paths : 705 64 | 65 | Type : Total number of failed paths 66 | Slack : 67 | Required Time : 68 | Actual Time : 69 | From : 70 | To : 71 | From Clock : 72 | To Clock : 73 | Failed Paths : 705 74 | 75 | -------------------------------------------------------------------------------------- 76 | 77 | -------------------------------------------------------------------------------- /Gerber/CRTPRT01.NCD: -------------------------------------------------------------------------------- 1 | M48 2 | ;FILE_FORMAT=2:4 3 | INCH 4 | ;TYPE=PLATED 5 | T01C0.013 6 | T02C0.038 7 | T03C0.047 8 | T04C0.059 9 | ;TYPE=NON_PLATED 10 | T05C0.184 11 | % 12 | T01 13 | X+235250Y+270750 14 | X+235260Y+272570 15 | X+238500Y+266375 16 | Y+267375 17 | X+242000Y+284125 18 | Y+283500 19 | X+245000Y+265260 20 | X+245060Y+271950 21 | Y+270840 22 | X+245070Y+273900 23 | X+245375Y+275000 24 | X+246500Y+266250 25 | X+248500 26 | X+246510 27 | X+247500 28 | X+246980Y+267700 29 | X+250500Y+266250 30 | X+251500 31 | X+250510 32 | X+249500 33 | X+250760Y+270650 34 | X+251470Y+272480 35 | X+249375Y+271625 36 | X+249400Y+275100 37 | Y+277070 38 | Y+277060 39 | Y+280890 40 | X+252500Y+266250 41 | X+254500 42 | X+253500 43 | X+254705Y+270901 44 | X+252340Y+270900 45 | X+254700 46 | Y+270906 47 | X+254350Y+275640 48 | X+253125Y+276875 49 | X+254375Y+278250 50 | X+257500Y+266250 51 | X+256500 52 | X+255500 53 | X+256080Y+270900 54 | X+257125Y+275625 55 | X+255750Y+274375 56 | X+255670Y+276850 57 | X+258500Y+266250 58 | X+259500 59 | X+260500 60 | Y+271420 61 | X+260270Y+272700 62 | X+258750Y+270875 63 | X+260500Y+274310 64 | X+258500Y+274300 65 | X+260500Y+278250 66 | Y+276280 67 | Y+280210 68 | X+261500Y+266250 69 | X+262500 70 | X+263500 71 | X+263380Y+267800 72 | X+262375Y+282750 73 | X+264650Y+270580 74 | X+266250Y+277875 75 | Y+279375 76 | X+265375Y+282750 77 | X+268240Y+270570 78 | X+268130Y+273810 79 | X+242000Y+284750 80 | X+246500Y+267000 81 | X+249400Y+273130 82 | Y+279230 83 | X+250590Y+279190 84 | X+252340Y+281900 85 | X+255340Y+272780 86 | X+256080Y+281900 87 | X+259230 88 | X+262370Y+270190 89 | X+266375Y+266875 90 | X+254950Y+267310 91 | X+260900Y+273320 92 | X+258250Y+278625 93 | X+254780Y+280150 94 | X+260840Y+281400 95 | X+263880Y+284710 96 | X+267250Y+271060 97 | X+269820 98 | X+266750Y+274660 99 | Y+272910 100 | T02 101 | X+262875Y+278750 102 | X+264875 103 | X+270250Y+279750 104 | X+269250 105 | Y+280750 106 | X+270250 107 | X+269250Y+281750 108 | X+270250 109 | X+269250Y+282750 110 | X+270250 111 | Y+283750 112 | X+269250 113 | T03 114 | X+233656Y+284500 115 | X+237594 116 | X+233656Y+285484 117 | X+237594 118 | X+235625Y+282531 119 | T04 120 | X+234641Y+282531 121 | X+237594 122 | X+236609 123 | X+233656 124 | X+235625Y+284500 125 | T05 126 | X+243000Y+269221 127 | X+265000Y+267174 128 | T00 129 | M30 130 | -------------------------------------------------------------------------------- /Firmware/Sources/lpm_ram.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %LPM_RAM_DQ% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: lpm_ram_dq 5 | 6 | -- ============================================================ 7 | -- File Name: ram.vhd 8 | -- Megafunction Name(s): 9 | -- lpm_ram_dq 10 | -- ============================================================ 11 | -- ************************************************************ 12 | -- THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE! 13 | -- ************************************************************ 14 | 15 | 16 | -- Copyright (C) 1988-2000 Altera Corporation 17 | 18 | -- Any megafunction design, and related net list (encrypted or decrypted), 19 | -- support information, device programming or simulation file, and any other 20 | -- associated documentation or information provided by Altera or a partner 21 | -- under Altera's Megafunction Partnership Program may be used only to 22 | -- program PLD devices (but not masked PLD devices) from Altera. Any other 23 | -- use of such megafunction design, net list, support information, device 24 | -- programming or simulation file, or any other related documentation or 25 | -- information is prohibited for any other purpose, including, but not 26 | -- limited to modification, reverse engineering, de-compiling, or use with 27 | -- any other silicon devices, unless such use is explicitly licensed under 28 | -- a separate agreement with Altera or a megafunction partner. Title to 29 | -- the intellectual property, including patents, copyrights, trademarks, 30 | -- trade secrets, or maskworks, embodied in any such megafunction design, 31 | -- net list, support information, device programming or simulation file, or 32 | -- any other related documentation or information provided by Altera or a 33 | -- megafunction partner, remains with Altera, the megafunction partner, or 34 | -- their respective licensors. No other licenses, including any licenses 35 | -- needed under any third party's intellectual property, are provided herein. 36 | 37 | LIBRARY ieee; 38 | USE ieee.std_logic_1164.all; 39 | LIBRARY lpm; 40 | USE lpm.lpm_components.all; 41 | 42 | ENTITY ram IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 46 | inclock : IN STD_LOGIC ; 47 | we : IN STD_LOGIC := '1'; 48 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 50 | ); 51 | END ram; 52 | 53 | 54 | ARCHITECTURE SYN OF ram IS 55 | 56 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 57 | 58 | 59 | 60 | COMPONENT lpm_ram_dq 61 | GENERIC ( 62 | LPM_WIDTH : NATURAL; 63 | LPM_WIDTHAD : NATURAL; 64 | LPM_INDATA : STRING; 65 | LPM_ADDRESS_CONTROL : STRING; 66 | LPM_OUTDATA : STRING; 67 | LPM_HINT : STRING 68 | ); 69 | PORT ( 70 | address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 71 | inclock : IN STD_LOGIC ; 72 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 73 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 74 | we : IN STD_LOGIC 75 | ); 76 | END COMPONENT; 77 | 78 | BEGIN 79 | q <= sub_wire0(7 DOWNTO 0); 80 | 81 | lpm_ram_dq_component : lpm_ram_dq 82 | GENERIC MAP ( 83 | LPM_WIDTH => 8, 84 | LPM_WIDTHAD => 8, 85 | LPM_INDATA => "REGISTERED", 86 | LPM_ADDRESS_CONTROL => "REGISTERED", 87 | LPM_OUTDATA => "UNREGISTERED", 88 | LPM_HINT => "USE_EAB" 89 | ) 90 | PORT MAP ( 91 | address => address, 92 | inclock => inclock, 93 | data => data, 94 | we => we, 95 | q => sub_wire0 96 | ); 97 | 98 | 99 | 100 | END SYN; 101 | 102 | -- ============================================================ 103 | -- CNX file retrieval info 104 | -- ============================================================ 105 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 106 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 107 | -- Retrieval info: PRIVATE: RegData NUMERIC "1" 108 | -- Retrieval info: PRIVATE: RegAdd NUMERIC "1" 109 | -- Retrieval info: PRIVATE: OutputRegistered NUMERIC "0" 110 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 111 | -- Retrieval info: PRIVATE: MIFfilename STRING "" 112 | -- Retrieval info: PRIVATE: UseLCs NUMERIC "0" 113 | -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 114 | -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" 115 | -- Retrieval info: CONSTANT: LPM_WIDTHAD NUMERIC "8" 116 | -- Retrieval info: CONSTANT: LPM_INDATA STRING "REGISTERED" 117 | -- Retrieval info: CONSTANT: LPM_ADDRESS_CONTROL STRING "REGISTERED" 118 | -- Retrieval info: CONSTANT: LPM_OUTDATA STRING "UNREGISTERED" 119 | -- Retrieval info: CONSTANT: LPM_HINT STRING "USE_EAB=ON" 120 | -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0] 121 | -- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock 122 | -- Retrieval info: USED_PORT: we 0 0 0 0 INPUT VCC we 123 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] 124 | -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] 125 | -- Retrieval info: CONNECT: @address 0 0 8 0 address 0 0 8 0 126 | -- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 127 | -- Retrieval info: CONNECT: @we 0 0 0 0 we 0 0 0 0 128 | -- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 129 | -- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 130 | -------------------------------------------------------------------------------- /Doc/registers_rus.txt: -------------------------------------------------------------------------------- 1 | Спецификация картриджа Carnivore MultiFlash SCC. 2 | Copyright (c) 2016 RBSC 3 | 4 | Регистры конфигурации 5 | --------------------- 6 | 7 | Регистры конфигурации и управления начинаются с адреса 0F80h или 4F80h или 8F80h или СF80h или.. 8 | или нигде не начинаются, а тихо прячутся. Всё зависит от того, что записано в «нулевом» управляющем регистре, 9 | после включения питания инициализируются на адрес 4F80h. Все регистры доступны только для записи за исключением 10 | псевдорегистра для доступа к FlashROM с целью её прошивки. 11 | 12 | +00 CardMDR — регистр управления конфигурацией картриджа 13 | 7 bit = 1 — запрет отображения регистров, 0- регистры отображаются 14 | 6,5 bit = 0/1/2/3 — регистры отображаются начиная с адреса 0F80h/4F80h/8F80h/СF80h 15 | 4 bit = 1 — разрешение "чипа" SCC, 0 — запрет 16 | 3 bit = 1 — режим отложенной конфигурации, 0 — конфигурация меняется сразу после изменения управляющих регистров 17 | 2 bit = 0 — при отложенной конфигурации изменения вступают в силу после выполнения процессором команды с адреса 0000h 18 | = 1 — изменения вступают в силу после выполнения чтения с адреса 4000h 19 | отложенная конфигурация регистров действует только для AddrFR и регистров управления банками 20 | 1,0 bit - резерв 21 | начальная конфигурация 20h 22 | 23 | +01 AddrM0 — младший регистр адреса (7..0) для обращения к FlashROM c целью прошивки 24 | +02 AddrM1 — средний регистр адреса (15..8) для обращения к FlashROM c целью прошивки 25 | +03 AddrM2 — старший регистр адреса (22..16) для обращения к FlashROM c целью прошивки 26 | +04 DatM0 — псевдорегистр для передачи данных во FlashRОM или чтения с целью прошивки 27 | 28 | +05 AddrFR - регистр номера блока FlashROM, с которого будут читаться данные для эмуляции ROM (размер блока 64кБ) 29 | начальная конфигурация 00h 30 | 31 | Регистры конфигурации первого банка 32 | ----------------------------------- 33 | 34 | +06 R1Mask — маска для адреса регистра страницы банка (этот регистр, как правило, дублируется на несколько адресов, 35 | например, для картриджа Konami 5 (SCC) эти адреса для первого банка 5000h-57FFh, здесь задаётся 36 | маска только старшего байта — 11111000b или F8h 37 | начальная конфигурация F8h 38 | +07 R1Addr — адрес регистра страницы банка, старший байт для адреса 5000h — это 50h 39 | начальная конфигурация 50h 40 | +08 R1Reg — содержимое регистра страницы банка, сдесь задаётся начальное значение странцы перед запуском 41 | содержимого ROM, как правило = 00h 42 | начальная конфигурация 00h 43 | +09 R1Mult — регистр режима банка и его размера 44 | 7 bit = 1 — разрешение регистра страницы банка, 0 — управление страницой банка выключено 45 | 6 bit = 1 — зеркалирование 46 | 5 bit = 0 — выбор в качестве источника FlashROM, 1 — RAM 47 | 4 bit = 1 — разрешение записи в банк, 0 — запрет записи в банк 48 | 3 bit = 0 — банк включен, 1 банк выключен 49 | 2,1,0 bits — размер банка 111b = 64 Кбайт, 110b = 32 Кбайт, 101b = 16 Кбайт, 100b = 8 Кбайт, 011 = 4 Кбайт 50 | остальные значения — банк выключен 51 | начальная конфигурация 85h 52 | +0A B1MaskR — Маска для адресации банка в блок FlashROM (размер эмулируемой ROM или количество страничек, например 53 | для 128 кБ ROM нужно 16 страничек по 8 кБ, значит выбираем маску = 0Fh или 00001111b) 54 | начальная когфигурация 03h 55 | +0B B1AdrD — Адрес банка, только старший байт.. для 4000h = 40h 56 | начальная конфигуарция 40h 57 | 58 | Регистры конфигурации второго банка 59 | ----------------------------------- 60 | 61 | +0C R2Mask 62 | +0D R2Addr 63 | +0E R2Reg 64 | +0F R2Mult начальное значение 00h, банк выключен 65 | +10 B2MaskR 66 | +11 B2AdrD 67 | 68 | Регистры конфигурации третьего банка 69 | ------------------------------------ 70 | 71 | +12 R3Mask 72 | +13 R3Addr 73 | +14 R3Reg 74 | +15 R3Mult начальное значение 00h, банк выключен 75 | +16 B3MaskR 76 | +17 B3AdrD 77 | 78 | Регистры конфигурации четвёртого банка 79 | -------------------------------------- 80 | 81 | +18 R4Mask 82 | +19 R4Addr 83 | +1A R4Reg 84 | +1B R4Mult начальное значение 00h, банк выключен 85 | +1C B4MaskR 86 | +1D B4AdrD 87 | 88 | +1E Резерв 89 | 90 | +1F дубль регистра управления CardMDR (для использования команды LDIR) 91 | 92 | +20 ConfFl — регистр конфигурации чипа FlashROM 93 | 2b — -BYTE = 0 для 8-разрядной шины данных, = 1 для 16-разрядной шины данных 94 | 1b — -RP — Reset/protect 95 | 0b — +12VPP = 1 подать 12 вольт для режима скоростной записи, =0 запретить +12в 96 | начальная конфигурация 010b 97 | 98 | Формат записи директории 99 | ------------------------ 100 | 101 | [00] ACT — Флаг активности записи (FF — пустая запись) 102 | [01] PSV — Пассивная запись (FF — не пассивная) 103 | [02] STB — Стартовый блок 104 | [03] LNB — Длина в блоках 105 | 106 | Будущий вариант | Текущий вариант 107 | 108 | [04,05,06,07,08,09,0A,0B] Имя файла | [04] — Тип маппера записи 109 | [0C,0D,0E] Расширение | [05–22] Текст (имя записи) 110 | [0F] REZ — Резерв | 111 | [10–22] Текст (19 байт) | 112 | 113 | [23 24 25 26 27 28] R1Mask R1Addr R1Reg R1Mult B1MaskR B1AdrD — 6 byte 1st Bank ROM Mapper 114 | [29 2A 2B 2C 2D 2E] R2Mask R2Addr R2Reg R2Mult B2MaskR B2AdrD — 6 byte 2nd Bank ROM Mapper 115 | [2F 30 31 32 33 34] R3Mask R3Addr R3Reg R3Mult B3MaskR B3AdrD — 6 byte 3st Bank ROM Mapper 116 | [35 36 37 38 39 3A] R4Mask R4Addr R4Reg R4Mult B4MaskR B4AdrD — 6 byte 4st Bank ROM Mapper 117 | 118 | [3B] — Mconf мультикартридж конфигурация, расширенный слот 119 | [3C] — CardMDR 120 | 121 | [3D] — bit 7,6,5,4 позиция в 64кБ блоке, 3-резерв, 2,1,0 bits — размер miniROM 110b = 32 кбайт, 122 | 101b = 16 кбайт, 100b = 8 Кбайт, 011 = 4 кбайт 000= не miniROM 123 | [3E] — опция RESET Bit0 =0 — no reset =1 — reset 124 | Bit1 =0 — RET func =1 — jmp ROMini addr 125 | Bit2 =0 — jmp (4002) =1 — jmp (8002) 126 | [3F] — Резерв 127 | 128 | -------------------------------------------------------------------------------- /Firmware/Sources/maxplusii_to_quartus_name_mapping.txt: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 1991-2004 Altera Corporation 2 | -- Any megafunction design, and related netlist (encrypted or decrypted), 3 | -- support information, device programming or simulation file, and any other 4 | -- associated documentation or information provided by Altera or a partner 5 | -- under Altera's Megafunction Partnership Program may be used only 6 | -- to program PLD devices (but not masked PLD devices) from Altera. Any 7 | -- other use of such megafunction design, netlist, support information, 8 | -- device programming or simulation file, or any other related documentation 9 | -- or information is prohibited for any other purpose, including, but not 10 | -- limited to modification, reverse engineering, de-compiling, or use with 11 | -- any other silicon devices, unless such use is explicitly licensed under 12 | -- a separate agreement with Altera or a megafunction partner. Title to the 13 | -- intellectual property, including patents, copyrights, trademarks, trade 14 | -- secrets, or maskworks, embodied in any such megafunction design, netlist, 15 | -- support information, device programming or simulation file, or any other 16 | -- related documentation or information provided by Altera or a megafunction 17 | -- partner, remains with Altera, the megafunction partner, or their respective 18 | -- licensors. No other licenses, including any licenses needed under any third 19 | -- party's intellectual property, are provided herein. 20 | 21 | -- VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version" 22 | -- DATE "07/26/2015 19:45:58" 23 | 24 | Conversion results for scc 25 | +-----------------------+----------------------+ 26 | | MAX+PLUS II node name | Quartus II node name | 27 | +-----------------------+----------------------+ 28 | | |pRamAdrX0 | pRamAdrX[0] | 29 | | |pRamAdrX1 | pRamAdrX[1] | 30 | | |pRamAdrX2 | pRamAdrX[2] | 31 | | |pRamAdrX3 | pRamAdrX[3] | 32 | | |pRamAdrX4 | pRamAdrX[4] | 33 | | |pRamAdrX5 | pRamAdrX[5] | 34 | | |pRamAdrX6 | pRamAdrX[6] | 35 | | |pRamAdrX7 | pRamAdrX[7] | 36 | | |pRamAdrX8 | pRamAdrX[8] | 37 | | |pRamAdrX9 | pRamAdrX[9] | 38 | | |pRamAdrX10 | pRamAdrX[10] | 39 | | |pRamAdrX11 | pRamAdrX[11] | 40 | | |pRamAdrX12 | pRamAdrX[12] | 41 | | |pRamAdrX13 | pRamAdrX[13] | 42 | | |pRamAdrX14 | pRamAdrX[14] | 43 | | |pRamAdrX15 | pRamAdrX[15] | 44 | | |pRamAdrX16 | pRamAdrX[16] | 45 | | |pRamAdrX17 | pRamAdrX[17] | 46 | | |pRamAdrX18 | pRamAdrX[18] | 47 | | |pRamAdrY0 | pRamAdrY[0] | 48 | | |pRamAdrY1 | pRamAdrY[1] | 49 | | |pRamAdrY2 | pRamAdrY[2] | 50 | | |pRamAdrY3 | pRamAdrY[3] | 51 | | |pRamAdrY4 | pRamAdrY[4] | 52 | | |pRamAdrY5 | pRamAdrY[5] | 53 | | |pRamAdrY6 | pRamAdrY[6] | 54 | | |pRamAdrY7 | pRamAdrY[7] | 55 | | |pRamAdrY8 | pRamAdrY[8] | 56 | | |pRamAdrY9 | pRamAdrY[9] | 57 | | |pRamAdrY10 | pRamAdrY[10] | 58 | | |pRamAdrY11 | pRamAdrY[11] | 59 | | |pRamAdrY12 | pRamAdrY[12] | 60 | | |pRamAdrY13 | pRamAdrY[13] | 61 | | |pRamAdrY14 | pRamAdrY[14] | 62 | | |pRamAdrY15 | pRamAdrY[15] | 63 | | |pRamAdrY16 | pRamAdrY[16] | 64 | | |pRamAdrY17 | pRamAdrY[17] | 65 | | |pRamAdrY18 | pRamAdrY[18] | 66 | | |pRamDatX0 | pRamDatX[0] | 67 | | |pRamDatX1 | pRamDatX[1] | 68 | | |pRamDatX2 | pRamDatX[2] | 69 | | |pRamDatX3 | pRamDatX[3] | 70 | | |pRamDatX4 | pRamDatX[4] | 71 | | |pRamDatX5 | pRamDatX[5] | 72 | | |pRamDatX6 | pRamDatX[6] | 73 | | |pRamDatX7 | pRamDatX[7] | 74 | | |pRamDatY0 | pRamDatY[0] | 75 | | |pRamDatY1 | pRamDatY[1] | 76 | | |pRamDatY2 | pRamDatY[2] | 77 | | |pRamDatY3 | pRamDatY[3] | 78 | | |pRamDatY4 | pRamDatY[4] | 79 | | |pRamDatY5 | pRamDatY[5] | 80 | | |pRamDatY6 | pRamDatY[6] | 81 | | |pRamDatY7 | pRamDatY[7] | 82 | | |pSltAdr0 | pSltAdr[0] | 83 | | |pSltAdr1 | pSltAdr[1] | 84 | | |pSltAdr2 | pSltAdr[2] | 85 | | |pSltAdr3 | pSltAdr[3] | 86 | | |pSltAdr4 | pSltAdr[4] | 87 | | |pSltAdr5 | pSltAdr[5] | 88 | | |pSltAdr6 | pSltAdr[6] | 89 | | |pSltAdr7 | pSltAdr[7] | 90 | | |pSltAdr8 | pSltAdr[8] | 91 | | |pSltAdr9 | pSltAdr[9] | 92 | | |pSltAdr10 | pSltAdr[10] | 93 | | |pSltAdr11 | pSltAdr[11] | 94 | | |pSltAdr12 | pSltAdr[12] | 95 | | |pSltAdr13 | pSltAdr[13] | 96 | | |pSltAdr14 | pSltAdr[14] | 97 | | |pSltAdr15 | pSltAdr[15] | 98 | | |pSltClk2 | pSltClk[2] | 99 | | |pSltCs1 | pSltCs[1] | 100 | | |pSltCs2 | pSltCs[2] | 101 | | |pSltCs12 | pSltCs[12] | 102 | | |pSltDat0 | pSltDat[0] | 103 | | |pSltDat1 | pSltDat[1] | 104 | | |pSltDat2 | pSltDat[2] | 105 | | |pSltDat3 | pSltDat[3] | 106 | | |pSltDat4 | pSltDat[4] | 107 | | |pSltDat5 | pSltDat[5] | 108 | | |pSltDat6 | pSltDat[6] | 109 | | |pSltDat7 | pSltDat[7] | 110 | | |pSltRsv5 | pSltRsv[5] | 111 | | |pSltRsv16 | pSltRsv[16] | 112 | | |pVideoB0 | pVideoB[0] | 113 | | |pVideoB1 | pVideoB[1] | 114 | | |pVideoB2 | pVideoB[2] | 115 | | |pVideoB3 | pVideoB[3] | 116 | | |pVideoB4 | pVideoB[4] | 117 | | |pVideoB5 | pVideoB[5] | 118 | | |pVideoG0 | pVideoG[0] | 119 | | |pVideoG1 | pVideoG[1] | 120 | | |pVideoG2 | pVideoG[2] | 121 | | |pVideoG3 | pVideoG[3] | 122 | | |pVideoG4 | pVideoG[4] | 123 | | |pVideoG5 | pVideoG[5] | 124 | | |pVideoR0 | pVideoR[0] | 125 | | |pVideoR1 | pVideoR[1] | 126 | | |pVideoR2 | pVideoR[2] | 127 | | |pVideoR3 | pVideoR[3] | 128 | | |pVideoR4 | pVideoR[4] | 129 | | |pVideoR5 | pVideoR[5] | 130 | +-----------------------+----------------------+ 131 | 132 | 133 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.asm.rpt: -------------------------------------------------------------------------------- 1 | Assembler report for cscc 2 | Wed Mar 02 18:58:05 2016 3 | Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Assembler Summary 11 | 3. Assembler Settings 12 | 4. Assembler Generated Files 13 | 5. Assembler Device Options: K:/msx/ALTERA_S_MSX/aa/cssc/cscc.sof 14 | 6. Assembler Device Options: K:/msx/ALTERA_S_MSX/aa/cssc/cscc.pof 15 | 7. Assembler Messages 16 | 17 | 18 | 19 | ---------------- 20 | ; Legal Notice ; 21 | ---------------- 22 | Copyright (C) 1991-2009 Altera Corporation 23 | Your use of Altera Corporation's design tools, logic functions 24 | and other software and tools, and its AMPP partner logic 25 | functions, and any output files from any of the foregoing 26 | (including device programming or simulation files), and any 27 | associated documentation or information are expressly subject 28 | to the terms and conditions of the Altera Program License 29 | Subscription Agreement, Altera MegaCore Function License 30 | Agreement, or other applicable license agreement, including, 31 | without limitation, that your use is for the sole purpose of 32 | programming logic devices manufactured by Altera and sold by 33 | Altera or its authorized distributors. Please refer to the 34 | applicable agreement for further details. 35 | 36 | 37 | 38 | +---------------------------------------------------------------+ 39 | ; Assembler Summary ; 40 | +-----------------------+---------------------------------------+ 41 | ; Assembler Status ; Successful - Wed Mar 02 18:58:05 2016 ; 42 | ; Revision Name ; cscc ; 43 | ; Top-level Entity Name ; cscc ; 44 | ; Family ; FLEX10KA ; 45 | ; Device ; EPF10K100ARI240-3 ; 46 | +-----------------------+---------------------------------------+ 47 | 48 | 49 | +--------------------------------------------------------------------------------------------------------+ 50 | ; Assembler Settings ; 51 | +-----------------------------------------------------------------------------+----------+---------------+ 52 | ; Option ; Setting ; Default Value ; 53 | +-----------------------------------------------------------------------------+----------+---------------+ 54 | ; Low-voltage mode ; Off ; On ; 55 | ; Configuration device ; Epc2 ; Auto ; 56 | ; Use smart compilation ; Off ; Off ; 57 | ; Compression mode ; Off ; Off ; 58 | ; Clock source for configuration device ; Internal ; Internal ; 59 | ; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; 60 | ; Divide clock frequency by ; 1 ; 1 ; 61 | ; Use configuration device ; On ; On ; 62 | ; Configuration device auto user code ; Off ; Off ; 63 | ; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; 64 | ; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; 65 | ; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; 66 | ; Hexadecimal Output File start address ; 0 ; 0 ; 67 | ; Hexadecimal Output File count direction ; Up ; Up ; 68 | ; Release clears before tri-states ; Off ; Off ; 69 | ; Auto-restart configuration after error ; On ; On ; 70 | ; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; 71 | ; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; 72 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; 73 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; 74 | +-----------------------------------------------------------------------------+----------+---------------+ 75 | 76 | 77 | +--------------------------------------+ 78 | ; Assembler Generated Files ; 79 | +--------------------------------------+ 80 | ; File Name ; 81 | +--------------------------------------+ 82 | ; K:/msx/ALTERA_S_MSX/aa/cssc/cscc.sof ; 83 | ; K:/msx/ALTERA_S_MSX/aa/cssc/cscc.pof ; 84 | +--------------------------------------+ 85 | 86 | 87 | +----------------------------------------------------------------+ 88 | ; Assembler Device Options: K:/msx/ALTERA_S_MSX/aa/cssc/cscc.sof ; 89 | +----------------+-----------------------------------------------+ 90 | ; Option ; Setting ; 91 | +----------------+-----------------------------------------------+ 92 | ; Device ; EPF10K100ARI240-3 ; 93 | ; JTAG usercode ; 0x0000007F ; 94 | ; Checksum ; 0x00119C24 ; 95 | +----------------+-----------------------------------------------+ 96 | 97 | 98 | +----------------------------------------------------------------+ 99 | ; Assembler Device Options: K:/msx/ALTERA_S_MSX/aa/cssc/cscc.pof ; 100 | +--------------------+-------------------------------------------+ 101 | ; Option ; Setting ; 102 | +--------------------+-------------------------------------------+ 103 | ; Device ; EPC2 ; 104 | ; JTAG usercode ; 0x00000000 ; 105 | ; Checksum ; 0x01109376 ; 106 | ; Compression Ratio ; 1 ; 107 | +--------------------+-------------------------------------------+ 108 | 109 | 110 | +--------------------+ 111 | ; Assembler Messages ; 112 | +--------------------+ 113 | Info: ******************************************************************* 114 | Info: Running Quartus II Assembler 115 | Info: Version 9.0 Build 132 02/25/2009 SJ Full Version 116 | Info: Processing started: Wed Mar 02 18:58:03 2016 117 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off cscc -c cscc 118 | Info: Assembler is generating device programming files 119 | Info: Quartus II Assembler was successful. 0 errors, 0 warnings 120 | Info: Peak virtual memory: 214 megabytes 121 | Info: Processing ended: Wed Mar 02 18:58:05 2016 122 | Info: Elapsed time: 00:00:02 123 | Info: Total CPU time (on all processors): 00:00:02 124 | 125 | 126 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.flow.rpt: -------------------------------------------------------------------------------- 1 | Flow report for cscc 2 | Wed Mar 02 18:58:07 2016 3 | Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Flow Summary 11 | 3. Flow Settings 12 | 4. Flow Non-Default Global Settings 13 | 5. Flow Elapsed Time 14 | 6. Flow OS Summary 15 | 7. Flow Log 16 | 17 | 18 | 19 | ---------------- 20 | ; Legal Notice ; 21 | ---------------- 22 | Copyright (C) 1991-2009 Altera Corporation 23 | Your use of Altera Corporation's design tools, logic functions 24 | and other software and tools, and its AMPP partner logic 25 | functions, and any output files from any of the foregoing 26 | (including device programming or simulation files), and any 27 | associated documentation or information are expressly subject 28 | to the terms and conditions of the Altera Program License 29 | Subscription Agreement, Altera MegaCore Function License 30 | Agreement, or other applicable license agreement, including, 31 | without limitation, that your use is for the sole purpose of 32 | programming logic devices manufactured by Altera and sold by 33 | Altera or its authorized distributors. Please refer to the 34 | applicable agreement for further details. 35 | 36 | 37 | 38 | +--------------------------------------------------------------------+ 39 | ; Flow Summary ; 40 | +-------------------------+------------------------------------------+ 41 | ; Flow Status ; Successful - Wed Mar 02 18:58:07 2016 ; 42 | ; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; 43 | ; Revision Name ; cscc ; 44 | ; Top-level Entity Name ; cscc ; 45 | ; Family ; FLEX10KA ; 46 | ; Device ; EPF10K100ARI240-3 ; 47 | ; Timing Models ; Final ; 48 | ; Met timing requirements ; No ; 49 | ; Total logic elements ; 1,732 / 4,992 ( 35 % ) ; 50 | ; Total pins ; 91 / 189 ( 48 % ) ; 51 | ; Total memory bits ; 2,048 / 24,576 ( 8 % ) ; 52 | +-------------------------+------------------------------------------+ 53 | 54 | 55 | +-----------------------------------------+ 56 | ; Flow Settings ; 57 | +-------------------+---------------------+ 58 | ; Option ; Setting ; 59 | +-------------------+---------------------+ 60 | ; Start date & time ; 03/02/2016 18:57:37 ; 61 | ; Main task ; Compilation ; 62 | ; Revision Name ; cscc ; 63 | +-------------------+---------------------+ 64 | 65 | 66 | +------------------------------------------------------------------------------------------------------------------------------+ 67 | ; Flow Non-Default Global Settings ; 68 | +----------------------------+---------------------------------------+------------------------------+-------------+------------+ 69 | ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; 70 | +----------------------------+---------------------------------------+------------------------------+-------------+------------+ 71 | ; AUTO_FAST_INPUT_REGISTERS ; On ; Off ; -- ; -- ; 72 | ; AUTO_FAST_OUTPUT_REGISTERS ; On ; Off ; -- ; -- ; 73 | ; COMPILER_SIGNATURE_ID ; 18413740489792.145691985709552 ; -- ; -- ; -- ; 74 | ; INCREMENTAL_COMPILATION ; Off ; FULL_INCREMENTAL_COMPILATION ; -- ; -- ; 75 | ; MISC_FILE ; K:/msx/ALTERA_S_MSX/aa/cscc/scc.dpf ; -- ; -- ; -- ; 76 | ; MISC_FILE ; K:/msx/ALTERA_S_MSX/aa/ccssc/cscc.dpf ; -- ; -- ; -- ; 77 | ; MISC_FILE ; K:/msx/ALTERA_S_MSX/aa/cssc/cscc.dpf ; -- ; -- ; -- ; 78 | ; MISC_FILE ; K:/msx/ALTERA_S_MSX/aa/scc/scc.dpf ; -- ; -- ; -- ; 79 | +----------------------------+---------------------------------------+------------------------------+-------------+------------+ 80 | 81 | 82 | +-----------------------------------------------------------------------------------------------------------------------------+ 83 | ; Flow Elapsed Time ; 84 | +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ 85 | ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; 86 | +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ 87 | ; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 248 MB ; 00:00:07 ; 88 | ; Fitter ; 00:00:15 ; 1.0 ; 230 MB ; 00:00:14 ; 89 | ; Assembler ; 00:00:02 ; 1.0 ; 214 MB ; 00:00:01 ; 90 | ; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 185 MB ; 00:00:01 ; 91 | ; Total ; 00:00:26 ; -- ; -- ; 00:00:23 ; 92 | +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ 93 | 94 | 95 | +------------------------------------------------------------------------------------------+ 96 | ; Flow OS Summary ; 97 | +-------------------------+------------------+---------------+------------+----------------+ 98 | ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; 99 | +-------------------------+------------------+---------------+------------+----------------+ 100 | ; Analysis & Synthesis ; magic003 ; Windows Vista ; 6.1 ; x86_64 ; 101 | ; Fitter ; magic003 ; Windows Vista ; 6.1 ; x86_64 ; 102 | ; Assembler ; magic003 ; Windows Vista ; 6.1 ; x86_64 ; 103 | ; Classic Timing Analyzer ; magic003 ; Windows Vista ; 6.1 ; x86_64 ; 104 | +-------------------------+------------------+---------------+------------+----------------+ 105 | 106 | 107 | ------------ 108 | ; Flow Log ; 109 | ------------ 110 | quartus_map --read_settings_files=on --write_settings_files=off cscc -c cscc 111 | quartus_fit --read_settings_files=off --write_settings_files=off cscc -c cscc 112 | quartus_asm --read_settings_files=off --write_settings_files=off cscc -c cscc 113 | quartus_tan --read_settings_files=off --write_settings_files=off cscc -c cscc 114 | 115 | 116 | 117 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2009 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 20 | # Version 9.0 Build 132 02/25/2009 SJ Full Version 21 | # Date created = 19:45:57 July 26, 2015 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # scc_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY FLEX10KA 40 | set_global_assignment -name DEVICE "EPF10K100ARI240-3" 41 | set_global_assignment -name TOP_LEVEL_ENTITY cscc 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:45:57 JULY 26, 2015" 44 | set_global_assignment -name LAST_QUARTUS_VERSION 9.0 45 | set_global_assignment -name MISC_FILE "K:/msx/ALTERA_S_MSX/aa/cscc/scc.dpf" 46 | set_global_assignment -name VHDL_FILE cscc.vhd 47 | set_global_assignment -name MISC_FILE "K:/msx/ALTERA_S_MSX/aa/ccssc/cscc.dpf" 48 | set_global_assignment -name MISC_FILE "K:/msx/ALTERA_S_MSX/aa/cssc/cscc.dpf" 49 | set_location_assignment PIN_91 -to pSltClk 50 | set_location_assignment PIN_211 -to pSltClk2 51 | set_location_assignment PIN_103 -to pSltRst_n 52 | set_location_assignment PIN_118 -to pSltSltsl_n 53 | set_location_assignment PIN_119 -to pSltCs1 54 | set_location_assignment PIN_120 -to pSltCs2 55 | set_location_assignment PIN_117 -to pSltCs12 56 | set_location_assignment PIN_109 -to pSltMerq_n 57 | set_location_assignment PIN_108 -to pSltIorq_n 58 | set_location_assignment PIN_111 -to pSltBdir_n 59 | set_location_assignment PIN_107 -to pSltRd_n 60 | set_location_assignment PIN_106 -to pSltWr_n 61 | set_location_assignment PIN_110 -to pSltM1_n 62 | set_location_assignment PIN_116 -to pSltRfsh_n 63 | set_location_assignment PIN_113 -to pSltWait_n 64 | set_location_assignment PIN_114 -to pSltInt_n 65 | set_location_assignment PIN_115 -to pSltRsv5 66 | set_location_assignment PIN_105 -to pSltRsv16 67 | set_location_assignment PIN_86 -to pSltAdr[0] 68 | set_location_assignment PIN_84 -to pSltAdr[1] 69 | set_location_assignment PIN_83 -to pSltAdr[2] 70 | set_location_assignment PIN_82 -to pSltAdr[3] 71 | set_location_assignment PIN_81 -to pSltAdr[4] 72 | set_location_assignment PIN_80 -to pSltAdr[5] 73 | set_location_assignment PIN_98 -to pSltAdr[6] 74 | set_location_assignment PIN_97 -to pSltAdr[7] 75 | set_location_assignment PIN_95 -to pSltAdr[8] 76 | set_location_assignment PIN_101 -to pSltAdr[9] 77 | set_location_assignment PIN_100 -to pSltAdr[10] 78 | set_location_assignment PIN_99 -to pSltAdr[11] 79 | set_location_assignment PIN_94 -to pSltAdr[12] 80 | set_location_assignment PIN_88 -to pSltAdr[13] 81 | set_location_assignment PIN_87 -to pSltAdr[14] 82 | set_location_assignment PIN_102 -to pSltAdr[15] 83 | set_location_assignment PIN_79 -to pSltDat[0] 84 | set_location_assignment PIN_78 -to pSltDat[1] 85 | set_location_assignment PIN_76 -to pSltDat[2] 86 | set_location_assignment PIN_75 -to pSltDat[3] 87 | set_location_assignment PIN_74 -to pSltDat[4] 88 | set_location_assignment PIN_72 -to pSltDat[5] 89 | set_location_assignment PIN_71 -to pSltDat[6] 90 | set_location_assignment PIN_70 -to pSltDat[7] 91 | set_location_assignment PIN_227 -to pSltSndL 92 | set_location_assignment PIN_226 -to pSltSndR 93 | set_location_assignment PIN_228 -to pSltSound 94 | set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC2LC20 95 | set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2 96 | set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE OFF 97 | set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE OFF 98 | set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE AREA 99 | set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE AREA 100 | set_global_assignment -name STATE_MACHINE_PROCESSING AUTO 101 | set_global_assignment -name AUTO_FAST_INPUT_REGISTERS ON 102 | set_global_assignment -name AUTO_FAST_OUTPUT_REGISTERS ON 103 | set_global_assignment -name AUTO_PACKED_REGISTERS OFF 104 | set_global_assignment -name AUTO_OPEN_DRAIN_PINS ON 105 | set_global_assignment -name AUTO_IMPLEMENT_IN_ROM OFF 106 | set_global_assignment -name AUTO_GLOBAL_CLOCK ON 107 | set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS ON 108 | set_global_assignment -name AUTO_GLOBAL_OE ON 109 | set_global_assignment -name VHDL_FILE lpm_ram.vhd 110 | set_global_assignment -name VHDL_FILE scc_wave.vhd 111 | set_global_assignment -name CDF_FILE scc.cdf 112 | set_global_assignment -name MISC_FILE "K:/msx/ALTERA_S_MSX/aa/scc/scc.dpf" 113 | set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD LVTTL/LVCMOS 114 | set_location_assignment PIN_19 -to pFlAdr[8] 115 | set_location_assignment PIN_233 -to pFlAdr[14] 116 | set_location_assignment PIN_231 -to pFlAdr[15] 117 | set_location_assignment PIN_230 -to pFlAdr[16] 118 | set_location_assignment PIN_234 -to pFlAdr[13] 119 | set_location_assignment PIN_235 -to pFlAdr[12] 120 | set_location_assignment PIN_237 -to pFlAdr[11] 121 | set_location_assignment PIN_6 -to pFlAdr[10] 122 | set_location_assignment PIN_7 -to pFlAdr[9] 123 | set_location_assignment PIN_18 -to pFlAdr[18] 124 | set_location_assignment PIN_17 -to pFlAdr[19] 125 | set_location_assignment PIN_12 -to pFlW_n 126 | set_location_assignment PIN_13 -to pFlRP_n 127 | set_location_assignment PIN_8 -to pFlAdr[20] 128 | set_location_assignment PIN_14 -to pFlAdr[22] 129 | set_location_assignment PIN_9 -to pFlAdr[21] 130 | set_location_assignment PIN_30 -to pFlAdr[17] 131 | set_location_assignment PIN_20 -to pFlAdr[7] 132 | set_location_assignment PIN_21 -to pFlAdr[6] 133 | set_location_assignment PIN_24 -to pFlAdr[5] 134 | set_location_assignment PIN_25 -to pFlAdr[4] 135 | set_location_assignment PIN_28 -to pFlAdr[3] 136 | set_location_assignment PIN_29 -to pFlAdr[2] 137 | set_location_assignment PIN_55 -to pFlAdr[1] 138 | set_location_assignment PIN_33 -to pFlAdr[0] 139 | set_location_assignment PIN_31 -to pFlBYTE_n 140 | set_location_assignment PIN_54 -to pFlCS_n 141 | set_location_assignment PIN_34 -to pFlDat[7] 142 | set_location_assignment PIN_36 -to pFlDat[6] 143 | set_location_assignment PIN_39 -to pFlDat[5] 144 | set_location_assignment PIN_41 -to pFlDat[4] 145 | set_location_assignment PIN_44 -to pFlDat[3] 146 | set_location_assignment PIN_46 -to pFlDat[2] 147 | set_location_assignment PIN_49 -to pFlDat[1] 148 | set_location_assignment PIN_51 -to pFlDat[0] 149 | set_location_assignment PIN_35 -to pFlDatH[6] 150 | set_location_assignment PIN_38 -to pFlDatH[5] 151 | set_location_assignment PIN_40 -to pFlDatH[4] 152 | set_location_assignment PIN_43 -to pFlDatH[3] 153 | set_location_assignment PIN_45 -to pFlDatH[2] 154 | set_location_assignment PIN_48 -to pFlDatH[1] 155 | set_location_assignment PIN_50 -to pFlDatH[0] 156 | set_location_assignment PIN_53 -to pFlOE_n 157 | set_location_assignment PIN_56 -to pFlVpp 158 | set_location_assignment PIN_15 -to pFlRB_b 159 | 160 | set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF 161 | set_global_assignment -name INCREMENTAL_COMPILATION OFF 162 | set_location_assignment PIN_61 -to iFsts 163 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 164 | set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -------------------------------------------------------------------------------- /Doc/readme.txt: -------------------------------------------------------------------------------- 1 | Carnivore MultiFlash SCC Cartridge version 1.1 2 | Copyright (c) 2016-2017 RBSC 3 | 4 | 5 | WARNING! To avoid damage to the Carnivore cartridge and your MSX computer hardware never insert or remove the cartridge 6 | when a computer is powered on! Always power off your computer before inserting or removing of any cartridge! 7 | 8 | 9 | The Setup 10 | --------- 11 | 12 | After assembling, the cartridge needs to be programmed in order to function properly. The following steps are necessary: 13 | 14 | 1. Upload the Altera's firmware 15 | 2. Initialize the directory 16 | 3. Write the Boot Block 17 | 4. Restart MSX 18 | 19 | 20 | How to upload the firmware 21 | -------------------------- 22 | 23 | Before uploading the firmware please make sure that your MSX boots fine with the inserted cartridge! 24 | 25 | 1. Solder jumper pins to the "+5v" and "GND" soldering points (or solder wires to both sides of C1 capacitor) 26 | 2. Prepare the ByteBlaster 2 programmer, open the Quartus II software 27 | 3. In the Quartus user interface select "JTAG" mode for your ByteBlaster 2 28 | 4. Supply 5v power to the cartridge board (mind the correct polarity!) 29 | 5. Connect the ByteBlaster's cable to the JTAG socket of the cartridge (make sure you connect the cable correctly!) 30 | 6. Use "Autodetect" button to detect your Altera chip 31 | 7. Rightclick on the added device's string and select "Change File" 32 | 8. Select the .POF file from the "Firmware" directory 33 | 9. Enable the checkboxes: "Program/Configure", "Verify" and "Blank Check" 34 | 10. Click "Start" and monitor the programming and verification process 35 | 36 | If the programming completed successfully, disconnect the ByteBlaster's cable and 5v power from the board. 37 | 38 | 39 | How to enable the cartridge and install Boot Block 40 | -------------------------------------------------- 41 | 42 | Insert the cartridge into the MSX slot, preferably into the first main slot. Power up MSX and check if it functions 43 | normally. If the machine shows an anomaly, remove and inspect the cartridge. To fully set up the cartridge the 44 | following needs to be done: 45 | 46 | 1. Make sure that the BOOTCSCC.BIN file is in the same folder with the utilities 47 | 2. Run the "cman.com" or "cman_40.com" (for MSX1 only) utility 48 | 3. When asked, enter the slot number where the cartridge is inserted (for example "1" for first slot, "2" for second slot, etc.) 49 | 4. From the main menu select "Open cartridge's Service Menu" using the "9" key 50 | 5. With the "7" key select "Fully erase FlashROM chip" and confirm twice 51 | 6. With the "3" key select "Init/Erase all directory entries" to initialize the directory 52 | 7. With the "4" key select "Write Boot Block (bootcscc.bin)" to write the Boot Block 53 | 8. If there were no errors during the steps 5-7, then power down and start your MSX 54 | 55 | 56 | How to work with Boot Block 57 | --------------------------- 58 | 59 | The Boot Block allows to start the ROMs from the flash chip and to restart the cartridge with the desired configuration. 60 | After MSX shows its boot logo, the cartridge's boot block should start and you should see the menu. Navigating the menu is 61 | very easy. Here are the key assignments: 62 | 63 | [ESC] - boot MSX using the default configuration 64 | [LEFT],[RIGHT] - previous/next directory page 65 | [UP],[DOWN] - select ROM/CFG entry 66 | [SPACE] - start entry normally 67 | [SHIFT]+[G] - start entry directly (using the jump address of the ROM) 68 | [SHIFT]+[R] - reset and start entry 69 | [SHIFT]+[A] - entry's autostart ON 70 | [SHIFT]+[D] - entry's autostart OFF 71 | 72 | Please keep in mind that some ROMs may require alternative starting method, so if pressing SPACE doesn't start the ROM, try 73 | using the direct start or start after system's reset. 74 | 75 | When you enable the autostart for an entry, it will be always activated after MSX's boot logo. The Boot Block menu will not be 76 | shown and the ROM or configuration entry will be started automatically. In order to disable the autostart or to skip the boot 77 | block completely the following keys should be used: 78 | 79 | [TAB] - disable autostart option 80 | [F5] - disable startup menu 81 | 82 | 83 | CMAN and CMAN_40 utilities 84 | -------------------------- 85 | 86 | The CMAN utility allows to initialize the cartridge, add ROMs into the FlashROM, edit the cartridge's directory. The CMAN_40 87 | utility is for MSX1 computers using the 40 character wide display, the CMAN utility is for MSX2 and later computers. 88 | 89 | The utility supports the following command line options: 90 | 91 | cman [filename.rom] [/h] [/v] [/a] [/su] 92 | 93 | /h - help screen 94 | /v - verbose mode (show detailed information) 95 | /a - automatically detect and write ROM image (no user interaction needed) 96 | /su - enable Super User mode (allows editing all registers: this is RISKY!) 97 | 98 | The utility is normally able to find the inserted cartridge by itself. If the utility can't find the cartridge, you will need 99 | to input the slot number manually and press Enter. The slot number is "1" for first slot, "2" for second slot, and so on. 100 | 101 | The main menu allows to: 102 | 103 | - Write new ROM image into FlashROM 104 | - Browse/edit cartridge's directory 105 | 106 | The menu options should be selected with the corresponding numeric buttons. 107 | 108 | 109 | Adding a ROM file into the FlashROM 110 | ----------------------------------- 111 | 112 | To add a new ROM file into the FlashROM chip, select the "Write new ROM image into FlashROM" option. Follow the on-screen instructions 113 | until the ROM is successfully written into the chip and the main menu re-appears. The large ROMs' mapper should be normally 114 | detected automatically by the utility, but on some ROMs autodetecting may fail. In this case the utility will ask you to choose the 115 | mapper. The ROM will not start with incorrect mapper settings, so if your setting didn't work, try to change the mapper type. 116 | 117 | The FlashROM chip contains 128 blocks by 64kb (8mb in total). The first block is occupied by the Boot Block and cartridge's directory. 118 | Other blocks are available for a user to add the ROMs. The ROMs that are smaller than 64kb are grouped into one block. For example two 32kb 119 | ROMs will be written into the same 64kb block, eight 8kb ROMs will be grouped into the same 64kb block and finally four 16kb ROMs will be 120 | grouped written into the same 64kb block. All this is done automatically. 121 | 122 | You can add a ROM into the chip without user interaction. The following command line should be used: 123 | 124 | CMAN file.rom /a 125 | 126 | The utility will try to automatically detect the ROM's mapper, check whether any free space is available and then it will write the 127 | selected ROM into the FlashROM chip. If you add the "/v" option, the utility will show additional information about the chip and the 128 | ROM that is being added as well as the map of the free chip's blocks. 129 | 130 | The map of FlashROM chip blocks can be viewed from the Service Menu. Just select the "Show FlashROM chip's block usage" option. 131 | 132 | 133 | Editing or deleting directory entries 134 | ------------------------------------- 135 | 136 | To edit the cartridge's directory select the "Browse/edit cartridge's directory" option. This will open the screen with the list of 137 | directory entries, 10 per page. The key assignment is similar to the boot block with the exception that you can't start the entry. 138 | An entry can be edited or deleted. Follow the on-screen instructions for editing a directory entry. Please keep in mind that the very 139 | first entry called "DefConfig: SCC cartridge" can't be deleted. 140 | 141 | In the directory editor you can change almost all fields of an entry, select a different mapper, reset options and so on. The editor 142 | has the context based help that is displayed at the bottom of the screen. 143 | 144 | With the Super User mode you can edit any register you want, but be advised, that you may damage the directory beyond repair and you 145 | will need to initialize it to continue using the cartridge. 146 | 147 | When you finish editing, you need to save the entry. The utility will offer you to replace the older entry or to create a copy of the 148 | edited entry. The new entry will be located in the end of the list. The name of the entry will be the same if you didn't rename it while 149 | editing. 150 | 151 | The number of directory entries is limited to 254. If the utility can't find an empty directory entry, it will ask you whether the 152 | directory should be optimized. If you select "Yes", then there's a big chance that unused directory entries will be found and deleted 153 | and you will have the possibility to add new ones. 154 | 155 | 156 | Loading and saving RCP files 157 | ---------------------------- 158 | 159 | When a ROM file doesn't start properly after being detected by the "cman" utility, there may be a need to adjust its configuration. 160 | This can be done either manually - by editing the configuration registers or by loading an RCP (Register Configuration Preset) file. 161 | We are providing a few RCP files for the ROM files that are not working correctly with default configuration. To load the RCP file 162 | you need to run the "cman" utility, enter the directory editor and start editing the selected ROM entry. When editing, select the 163 | "Save/load register preset" option and then use "Load register preset file". When asked, enter the preset's file name and it will 164 | be loaded for the entry you are editing. Just save the entry with the new settings and your ROM will start working correctly. 165 | 166 | When you are making your own configuration settings for a selected ROM file, you can always save them into RCP file. You need to 167 | select the "Save/load register preset" option and then use "Save register preset file". When asked, entry the name of the RCP file 168 | and it will be saved for future use. 169 | 170 | 171 | Notes 172 | ----- 173 | 174 | The audio socket of the Carnivore cartridge may not be suitable for connecting the headphones. It's recommended to connect it to the 175 | speakers or to the amplifier. This socket will only output SCC music and sounds. For the full experience please use the MSX's 176 | startdard sound output - it will have the amplified SCC sound and music as well as the PSG sound and music. 177 | 178 | 179 | IMPORTANT! 180 | ---------- 181 | 182 | The RBSC provides all the files and information for free, without any liability (see the disclaimer.txt file). The provided information, 183 | software or hardware must not be used for commercial purposes unless permitted by the RBSC. Producing a small amount of bare boards for 184 | personal projects and selling the rest of the batch is allowed without the permission of RBSC. 185 | 186 | When the sources of the tools are used to create alternative projects, please always mention the original source and the copyright! 187 | 188 | 189 | Contact information 190 | ------------------- 191 | 192 | The members of RBSC group Wierzbowsky, Ptero and DJS3000 can be contacted via the MSX.ORG or ZX-PK.RU forums. Just send a personal 193 | message and state your business. 194 | 195 | The RBSC repository can be found here: 196 | 197 | https://github.com/rbsc 198 | 199 | 200 | -= ! MSX FOREVER ! =- 201 | -------------------------------------------------------------------------------- /Gerber/CRTPRT01.BDR: -------------------------------------------------------------------------------- 1 | G04* 2 | G04 File: CRTPRT01.BDR, Tue Aug 04 07:36:28 2015* 3 | G04 Source: P-CAD 2006 PCB, Version 19.02.958, (G:\Platform\MSX\Projects\Ptero\Canivore_SCC\CRTPRT01.pcb)* 4 | G04 Format: Gerber Format (RS-274-D), ASCII* 5 | G04* 6 | G04 Format Options: Absolute Positioning* 7 | G04 Leading-Zero Suppression* 8 | G04 Scale Factor 1:1* 9 | G04 NO Circular Interpolation* 10 | G04 Inch Units* 11 | G04 Numeric Format: 4.4 (XXXX.XXXX)* 12 | G04 G54 NOT Used for Aperture Change* 13 | G04 Apertures Embedded* 14 | G04* 15 | G04 File Options: Offset = (0.0mil,0.0mil)* 16 | G04 Drill Symbol Size = 80.0mil* 17 | G04 No Pad/Via Holes* 18 | G04* 19 | G04 File Contents: No Pads* 20 | G04 No Vias* 21 | G04 No Designators* 22 | G04 No Types* 23 | G04 No Values* 24 | G04 No Drill Symbols* 25 | G04 Board* 26 | G04* 27 | %INCRTPRT01.BDR*% 28 | %ICAS*% 29 | %MOIN*% 30 | G04* 31 | G04 Aperture MACROs for general use --- invoked via D-code assignment * 32 | G04* 33 | G04 General MACRO for flashed round with rotation and/or offset hole * 34 | %AMROTOFFROUND* 35 | 1,1,$1,0.0000,0.0000* 36 | 1,0,$2,$3,$4*% 37 | G04* 38 | G04 General MACRO for flashed oval (obround) with rotation and/or offset hole * 39 | %AMROTOFFOVAL* 40 | 21,1,$1,$2,0.0000,0.0000,$3* 41 | 1,1,$4,$5,$6* 42 | 1,1,$4,0-$5,0-$6* 43 | 1,0,$7,$8,$9*% 44 | G04* 45 | G04 General MACRO for flashed oval (obround) with rotation and no hole * 46 | %AMROTOVALNOHOLE* 47 | 21,1,$1,$2,0.0000,0.0000,$3* 48 | 1,1,$4,$5,$6* 49 | 1,1,$4,0-$5,0-$6*% 50 | G04* 51 | G04 General MACRO for flashed rectangle with rotation and/or offset hole * 52 | %AMROTOFFRECT* 53 | 21,1,$1,$2,0.0000,0.0000,$3* 54 | 1,0,$4,$5,$6*% 55 | G04* 56 | G04 General MACRO for flashed rectangle with rotation and no hole * 57 | %AMROTRECTNOHOLE* 58 | 21,1,$1,$2,0.0000,0.0000,$3*% 59 | G04* 60 | G04 General MACRO for flashed rounded-rectangle * 61 | %AMROUNDRECT* 62 | 21,1,$1,$2-$4,0.0000,0.0000,$3* 63 | 21,1,$1-$4,$2,0.0000,0.0000,$3* 64 | 1,1,$4,$5,$6* 65 | 1,1,$4,$7,$8* 66 | 1,1,$4,0-$5,0-$6* 67 | 1,1,$4,0-$7,0-$8* 68 | 1,0,$9,$10,$11*% 69 | G04* 70 | G04 General MACRO for flashed rounded-rectangle with rotation and no hole * 71 | %AMROUNDRECTNOHOLE* 72 | 21,1,$1,$2-$4,0.0000,0.0000,$3* 73 | 21,1,$1-$4,$2,0.0000,0.0000,$3* 74 | 1,1,$4,$5,$6* 75 | 1,1,$4,$7,$8* 76 | 1,1,$4,0-$5,0-$6* 77 | 1,1,$4,0-$7,0-$8*% 78 | G04* 79 | G04 General MACRO for flashed regular polygon * 80 | %AMREGPOLY* 81 | 5,1,$1,0.0000,0.0000,$2,$3+$4* 82 | 1,0,$5,$6,$7*% 83 | G04* 84 | G04 General MACRO for flashed regular polygon with no hole * 85 | %AMREGPOLYNOHOLE* 86 | 5,1,$1,0.0000,0.0000,$2,$3+$4*% 87 | G04* 88 | G04 General MACRO for target * 89 | %AMTARGET* 90 | 6,0,0,$1,$2,$3,4,$4,$5,$6*% 91 | G04* 92 | G04 General MACRO for mounting hole * 93 | %AMMTHOLE* 94 | 1,1,$1,0,0* 95 | 1,0,$2,0,0* 96 | $1=$1-$2* 97 | $1=$1/2* 98 | 21,1,$2+$1,$3,0,0,$4* 99 | 21,1,$3,$2+$1,0,0,$4*% 100 | G04* 101 | G04* 102 | G04 D10 : "Ellipse X10.0mil Y10.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 103 | G04 Disc: OuterDia=0.0100* 104 | %ADD10C, 0.0100*% 105 | G04 D11 : "Ellipse X20.0mil Y20.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 106 | G04 Disc: OuterDia=0.0200* 107 | %ADD11C, 0.0200*% 108 | G04 D12 : "Ellipse X30.0mil Y30.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 109 | G04 Disc: OuterDia=0.0300* 110 | %ADD12C, 0.0300*% 111 | G04 D13 : "Ellipse X40.0mil Y40.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 112 | G04 Disc: OuterDia=0.0400* 113 | %ADD13C, 0.0400*% 114 | G04 D14 : "Ellipse X45.0mil Y45.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 115 | G04 Disc: OuterDia=0.0450* 116 | %ADD14C, 0.0450*% 117 | G04 D15 : "Ellipse X5.0mil Y5.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 118 | G04 Disc: OuterDia=0.0050* 119 | %ADD15C, 0.0050*% 120 | G04 D16 : "Ellipse X5.9mil Y5.9mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 121 | G04 Disc: OuterDia=0.0059* 122 | %ADD16C, 0.0059*% 123 | G04 D17 : "Ellipse X50.0mil Y50.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 124 | G04 Disc: OuterDia=0.0500* 125 | %ADD17C, 0.0500*% 126 | G04 D18 : "Ellipse X6.1mil Y6.1mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 127 | G04 Disc: OuterDia=0.0061* 128 | %ADD18C, 0.0061*% 129 | G04 D19 : "Ellipse X60.0mil Y60.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 130 | G04 Disc: OuterDia=0.0600* 131 | %ADD19C, 0.0600*% 132 | G04 D20 : "Ellipse X7.9mil Y7.9mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 133 | G04 Disc: OuterDia=0.0079* 134 | %ADD20C, 0.0079*% 135 | G04 D21 : "Ellipse X9.8mil Y9.8mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 136 | G04 Disc: OuterDia=0.0098* 137 | %ADD21C, 0.0098*% 138 | G04 D22 : "Ellipse X101.6mil Y101.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 139 | G04 Disc: OuterDia=0.1016* 140 | %ADD22C, 0.1016*% 141 | G04 D23 : "Ellipse X199.0mil Y199.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 142 | G04 Disc: OuterDia=0.1990* 143 | %ADD23C, 0.1990*% 144 | G04 D24 : "Ellipse X60.0mil Y60.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 145 | G04 Disc: OuterDia=0.0600* 146 | %ADD24C, 0.0600*% 147 | G04 D25 : "Ellipse X62.2mil Y62.2mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 148 | G04 Disc: OuterDia=0.0622* 149 | %ADD25C, 0.0622*% 150 | G04 D26 : "Ellipse X75.0mil Y75.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 151 | G04 Disc: OuterDia=0.0750* 152 | %ADD26C, 0.0750*% 153 | G04 D27 : "Ellipse X86.6mil Y86.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 154 | G04 Disc: OuterDia=0.0866* 155 | %ADD27C, 0.0866*% 156 | G04 D28 : "Mounting Hole X184.0mil Y184.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 157 | G04 Mounting Hole: Diameter=0.1840, Rotation=0.0, LineWidth=0.0050 * 158 | %ADD28MTHOLE, 0.1840 X0.1640 X0.0050 X0.0*% 159 | G04 D29 : "Mounting Hole X47.2mil Y47.2mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 160 | G04 Mounting Hole: Diameter=0.0472, Rotation=0.0, LineWidth=0.0050 * 161 | %ADD29MTHOLE, 0.0472 X0.0272 X0.0050 X0.0*% 162 | G04 D30 : "Rounded Rectangle X50.0mil Y350.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 163 | G04 RoundRct: DimX=0.0500, DimY=0.3500, CornerRad=0.0125, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 164 | %ADD30ROUNDRECTNOHOLE, 0.0500 X0.3500 X0.0 X0.0250 X-0.0125 X-0.1625 X-0.0125 X0.1625*% 165 | G04 D31 : "Rounded Rectangle X65.0mil Y365.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 166 | G04 RoundRct: DimX=0.0650, DimY=0.3650, CornerRad=0.0163, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 167 | %ADD31ROUNDRECTNOHOLE, 0.0650 X0.3650 X0.0 X0.0325 X-0.0163 X-0.1663 X-0.0163 X0.1663*% 168 | G04 D32 : "Rectangle X63.0mil Y106.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 169 | G04 Rectangular: DimX=0.0630, DimY=0.1063, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 170 | %ADD32R, 0.0630 X0.1063*% 171 | G04 D33 : "Rectangle X11.8mil Y63.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 172 | G04 Rectangular: DimX=0.0118, DimY=0.0630, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 173 | %ADD33R, 0.0118 X0.0630*% 174 | G04 D34 : "Rectangle X63.0mil Y11.8mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 175 | G04 Rectangular: DimX=0.0630, DimY=0.0118, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 176 | %ADD34R, 0.0630 X0.0118*% 177 | G04 D35 : "Rectangle X59.1mil Y12.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 178 | G04 Rectangular: DimX=0.0591, DimY=0.0120, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 179 | %ADD35R, 0.0591 X0.0120*% 180 | G04 D36 : "Rectangle X78.0mil Y121.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 181 | G04 Rectangular: DimX=0.0780, DimY=0.1213, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 182 | %ADD36R, 0.0780 X0.1213*% 183 | G04 D37 : "Rectangle X157.5mil Y118.1mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 184 | G04 Rectangular: DimX=0.1575, DimY=0.1181, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 185 | %ADD37R, 0.1575 X0.1181*% 186 | G04 D38 : "Rectangle X172.5mil Y133.1mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 187 | G04 Rectangular: DimX=0.1725, DimY=0.1331, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 188 | %ADD38R, 0.1725 X0.1331*% 189 | G04 D39 : "Rectangle X23.6mil Y88.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 190 | G04 Rectangular: DimX=0.0236, DimY=0.0886, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 191 | %ADD39R, 0.0236 X0.0886*% 192 | G04 D40 : "Rectangle X88.6mil Y23.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 193 | G04 Rectangular: DimX=0.0886, DimY=0.0236, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 194 | %ADD40R, 0.0886 X0.0236*% 195 | G04 D41 : "Rectangle X26.8mil Y78.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 196 | G04 Rectangular: DimX=0.0268, DimY=0.0780, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 197 | %ADD41R, 0.0268 X0.0780*% 198 | G04 D42 : "Rectangle X78.0mil Y26.8mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 199 | G04 Rectangular: DimX=0.0780, DimY=0.0268, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 200 | %ADD42R, 0.0780 X0.0268*% 201 | G04 D43 : "Rectangle X74.1mil Y27.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 202 | G04 Rectangular: DimX=0.0741, DimY=0.0270, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 203 | %ADD43R, 0.0741 X0.0270*% 204 | G04 D44 : "Rectangle X32.0mil Y32.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 205 | G04 Square: Side=0.0320, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 206 | %ADD44R, 0.0320 X0.0320*% 207 | G04 D45 : "Rectangle X38.6mil Y103.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 208 | G04 Rectangular: DimX=0.0386, DimY=0.1036, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 209 | %ADD45R, 0.0386 X0.1036*% 210 | G04 D46 : "Rectangle X103.6mil Y38.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 211 | G04 Rectangular: DimX=0.1036, DimY=0.0386, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 212 | %ADD46R, 0.1036 X0.0386*% 213 | G04 D47 : "Rectangle X39.4mil Y43.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 214 | G04 Rectangular: DimX=0.0394, DimY=0.0433, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 215 | %ADD47R, 0.0394 X0.0433*% 216 | G04 D48 : "Rectangle X43.3mil Y39.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 217 | G04 Rectangular: DimX=0.0433, DimY=0.0394, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 218 | %ADD48R, 0.0433 X0.0394*% 219 | G04 D49 : "Rectangle X39.4mil Y98.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 220 | G04 Rectangular: DimX=0.0394, DimY=0.0984, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 221 | %ADD49R, 0.0394 X0.0984*% 222 | G04 D50 : "Rectangle X47.0mil Y47.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 223 | G04 Square: Side=0.0470, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 224 | %ADD50R, 0.0470 X0.0470*% 225 | G04 D51 : "Rectangle X54.4mil Y113.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 226 | G04 Rectangular: DimX=0.0544, DimY=0.1134, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 227 | %ADD51R, 0.0544 X0.1134*% 228 | G04 D52 : "Rectangle X54.4mil Y58.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 229 | G04 Rectangular: DimX=0.0544, DimY=0.0583, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 230 | %ADD52R, 0.0544 X0.0583*% 231 | G04 D53 : "Rectangle X58.3mil Y54.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 232 | G04 Rectangular: DimX=0.0583, DimY=0.0544, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 233 | %ADD53R, 0.0583 X0.0544*% 234 | G04 D54 : "Rectangle X60.0mil Y60.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 235 | G04 Square: Side=0.0600, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 236 | %ADD54R, 0.0600 X0.0600*% 237 | G04 D55 : "Rectangle X75.0mil Y75.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 238 | G04 Square: Side=0.0750, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 239 | %ADD55R, 0.0750 X0.0750*% 240 | G04 D56 : "Rectangle X26.0mil Y80.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 241 | G04 Rectangular: DimX=0.0260, DimY=0.0800, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 242 | %ADD56R, 0.0260 X0.0800*% 243 | G04 D57 : "Rectangle X41.0mil Y95.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 244 | G04 Rectangular: DimX=0.0410, DimY=0.0950, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 245 | %ADD57R, 0.0410 X0.0950*% 246 | G04 D58 : "Ellipse X40.0mil Y40.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 247 | G04 Disc: OuterDia=0.0400* 248 | %ADD58C, 0.0400*% 249 | G04 D59 : "Ellipse X55.0mil Y55.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 250 | G04 Disc: OuterDia=0.0550* 251 | %ADD59C, 0.0550*% 252 | G04* 253 | %FSLAX44Y44*% 254 | %SFA1B1*% 255 | %OFA0.0000B0.0000*% 256 | G04* 257 | G70* 258 | G90* 259 | G01* 260 | D2* 261 | %LNBoard*% 262 | D15* 263 | X266750Y260875* 264 | Y266000D1* 265 | X271500* 266 | Y285875* 267 | X235125* 268 | X232500* 269 | Y283750* 270 | Y269625* 271 | X236500* 272 | Y266000* 273 | X241250* 274 | Y260875* 275 | X241375* 276 | X266750* 277 | D02M02* 278 | -------------------------------------------------------------------------------- /Firmware/Sources/scc_wave.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------- 2 | -- Title : scc_wave.vhd 3 | -- Function : Sound Creation Chip (KONAMI) 4 | -- Date : 28th,August,2000 5 | -- Revision : 1.01 6 | -- Author : Kazuhiro TSUJIKAWA (ESE Artists' factory) 7 | ---------------------------------------------------------------- 8 | library IEEE; 9 | use IEEE.std_logic_1164.all; 10 | use IEEE.std_logic_unsigned.all; 11 | 12 | entity scc_wave is 13 | port( 14 | pSltClk_n : IN std_logic; 15 | pSltRst_n : IN std_logic; 16 | pSltAdr : IN std_logic_vector(7 downto 0); 17 | pSltDat : INOUT std_logic_vector(7 downto 0); 18 | SccAmp : OUT std_logic_vector(7 downto 0); 19 | 20 | SccRegWe : IN std_logic; 21 | SccModWe : IN std_logic; 22 | SccWavCe : IN std_logic; 23 | SccWavOe : IN std_logic; 24 | SccWavWe : IN std_logic; 25 | SccWavWx : IN std_logic; 26 | SccWavAdr : IN std_logic_vector(4 downto 0); 27 | SccWavDat : IN std_logic_vector(7 downto 0); 28 | pFlOE_nt : IN std_logic; 29 | pFlDat : INOUT std_logic_vector(7 downto 0) 30 | ); 31 | end scc_wave; 32 | 33 | architecture RTL of scc_wave is 34 | 35 | -- Wave memory control 36 | signal WaveWe : std_logic; 37 | signal WaveAdr : std_logic_vector(7 downto 0); 38 | signal iWaveDat : std_logic_vector(7 downto 0); 39 | signal oWaveDat : std_logic_vector(7 downto 0); 40 | 41 | -- SCC resisters 42 | signal SccFreqChA : std_logic_vector(11 downto 0); 43 | signal SccFreqChB : std_logic_vector(11 downto 0); 44 | signal SccFreqChC : std_logic_vector(11 downto 0); 45 | signal SccFreqChD : std_logic_vector(11 downto 0); 46 | signal SccFreqChE : std_logic_vector(11 downto 0); 47 | signal SccVolChA : std_logic_vector(3 downto 0); 48 | signal SccVolChB : std_logic_vector(3 downto 0); 49 | signal SccVolChC : std_logic_vector(3 downto 0); 50 | signal SccVolChD : std_logic_vector(3 downto 0); 51 | signal SccVolChE : std_logic_vector(3 downto 0); 52 | signal SccChanSel : std_logic_vector(4 downto 0); 53 | 54 | signal SccModeSel : std_logic_vector(7 downto 0); 55 | 56 | -- SCC temporaries 57 | signal SccRstChA : std_logic; 58 | signal SccRstChB : std_logic; 59 | signal SccRstChC : std_logic; 60 | signal SccRstChD : std_logic; 61 | signal SccRstChE : std_logic; 62 | 63 | signal SccPtrChA : std_logic_vector(4 downto 0); 64 | signal SccPtrChB : std_logic_vector(4 downto 0); 65 | signal SccPtrChC : std_logic_vector(4 downto 0); 66 | signal SccPtrChD : std_logic_vector(4 downto 0); 67 | signal SccPtrChE : std_logic_vector(4 downto 0); 68 | 69 | signal SccClkEna : std_logic_vector(2 downto 0); 70 | signal SccChEna : std_logic; 71 | signal SccChNum : std_logic_vector(2 downto 0); 72 | 73 | component ram 74 | port( 75 | address : IN std_logic_vector(7 downto 0); 76 | inclock : IN std_logic; 77 | we : IN std_logic; 78 | data : IN std_logic_vector(7 downto 0); 79 | q : OUT std_logic_vector(7 downto 0) 80 | ); 81 | end component; 82 | 83 | begin 84 | 85 | ---------------------------------------------------------------- 86 | -- Misceracle control 87 | ---------------------------------------------------------------- 88 | process(pSltClk_n, pSltRst_n) 89 | 90 | begin 91 | 92 | if (pSltRst_n = '0') then 93 | 94 | SccClkEna <= (others => '0'); 95 | SccChNum <= (others => '0'); 96 | 97 | elsif (pSltClk_n'event and pSltClk_n = '1') then 98 | 99 | -- Clock Enable (clock divider) 100 | SccClkEna <= SccClkEna + 1; 101 | 102 | if (SccClkEna = "111") then 103 | SccChNum <= "000"; 104 | elsif (SccChEna = '1') then 105 | SccChNum <= SccChNum + 1; 106 | end if; 107 | 108 | end if; 109 | 110 | end process; 111 | 112 | ---------------------------------------------------------------- 113 | -- Wave memory control 114 | ---------------------------------------------------------------- 115 | WaveAdr <= pSltAdr(7 downto 0) when SccWavCe = '1' else 116 | ("100" & SccWavAdr) when SccWavWx = '1' else 117 | ("000" & SccPtrChA) when SccChNum = "000" else 118 | ("001" & SccPtrChB) when SccChNum = "001" else 119 | ("010" & SccPtrChC) when SccChNum = "010" else 120 | ("011" & SccPtrChD) when SccChNum = "011" else 121 | ("100" & SccPtrChE); 122 | 123 | iWaveDat <= pSltDat when SccWavWx = '0' else SccWavDat; 124 | WaveWe <= '1' when SccWavWe = '1' or SccWavWx = '1' else '0'; 125 | 126 | WaveMem : ram port map(WaveAdr, pSltClk_n, WaveWe, iWaveDat, oWaveDat); 127 | 128 | pSltDat <= oWaveDat when SccWavOe = '1' else 129 | pFlDat when pFlOE_nt = '0' else (others => 'Z'); 130 | 131 | ---------------------------------------------------------------- 132 | -- SCC resister access 133 | ---------------------------------------------------------------- 134 | process(pSltClk_n, pSltRst_n) 135 | 136 | begin 137 | 138 | if (pSltRst_n = '0') then 139 | 140 | SccFreqChA <= (others => '0'); 141 | SccFreqChB <= (others => '0'); 142 | SccFreqChC <= (others => '0'); 143 | SccFreqChD <= (others => '0'); 144 | SccFreqChE <= (others => '0'); 145 | SccVolChA <= (others => '0'); 146 | SccVolChB <= (others => '0'); 147 | SccVolChC <= (others => '0'); 148 | SccVolChD <= (others => '0'); 149 | SccVolChE <= (others => '0'); 150 | SccChanSel <= (others => '0'); 151 | 152 | SccModeSel <= (others => '0'); 153 | 154 | SccRstChA <= '0'; 155 | SccRstChB <= '0'; 156 | SccRstChC <= '0'; 157 | SccRstChD <= '0'; 158 | SccRstChE <= '0'; 159 | 160 | elsif (pSltClk_n'event and pSltClk_n = '1') then 161 | 162 | -- Mapped I/O port access on 9880-988Fh / B8A0-B8AF ... Resister write 163 | if (SccRegWe = '1') then 164 | case pSltAdr(3 downto 0) is 165 | when "0000" => SccFreqChA(7 downto 0) <= pSltDat(7 downto 0); SccRstChA <= SccModeSel(5); 166 | when "0001" => SccFreqChA(11 downto 8) <= pSltDat(3 downto 0); SccRstChA <= SccModeSel(5); 167 | when "0010" => SccFreqChB(7 downto 0) <= pSltDat(7 downto 0); SccRstChB <= SccModeSel(5); 168 | when "0011" => SccFreqChB(11 downto 8) <= pSltDat(3 downto 0); SccRstChB <= SccModeSel(5); 169 | when "0100" => SccFreqChC(7 downto 0) <= pSltDat(7 downto 0); SccRstChC <= SccModeSel(5); 170 | when "0101" => SccFreqChC(11 downto 8) <= pSltDat(3 downto 0); SccRstChC <= SccModeSel(5); 171 | when "0110" => SccFreqChD(7 downto 0) <= pSltDat(7 downto 0); SccRstChD <= SccModeSel(5); 172 | when "0111" => SccFreqChD(11 downto 8) <= pSltDat(3 downto 0); SccRstChD <= SccModeSel(5); 173 | when "1000" => SccFreqChE(7 downto 0) <= pSltDat(7 downto 0); SccRstChE <= SccModeSel(5); 174 | when "1001" => SccFreqChE(11 downto 8) <= pSltDat(3 downto 0); SccRstChE <= SccModeSel(5); 175 | when "1010" => SccVolChA(3 downto 0) <= pSltDat(3 downto 0); 176 | when "1011" => SccVolChB(3 downto 0) <= pSltDat(3 downto 0); 177 | when "1100" => SccVolChC(3 downto 0) <= pSltDat(3 downto 0); 178 | when "1101" => SccVolChD(3 downto 0) <= pSltDat(3 downto 0); 179 | when "1110" => SccVolChE(3 downto 0) <= pSltDat(3 downto 0); 180 | when others => SccChanSel(4 downto 0) <= pSltDat(4 downto 0); 181 | end case; 182 | else 183 | SccRstChA <= '0'; SccRstChB <= '0'; SccRstChC <= '0'; SccRstChD <= '0'; SccRstChE <= '0'; 184 | end if; 185 | 186 | -- Mapped I/O port access on 98C0-98FFh / B8C0-B8DFh ... Resister write 187 | if (SccModWe = '1') then 188 | SccModeSel <= pSltDat; 189 | end if; 190 | 191 | end if; 192 | 193 | end process; 194 | 195 | ---------------------------------------------------------------- 196 | -- Tone generator 197 | ---------------------------------------------------------------- 198 | process(pSltClk_n, pSltRst_n) 199 | 200 | variable SccCntChA : std_logic_vector(11 downto 0); 201 | variable SccCntChB : std_logic_vector(11 downto 0); 202 | variable SccCntChC : std_logic_vector(11 downto 0); 203 | variable SccCntChD : std_logic_vector(11 downto 0); 204 | variable SccCntChE : std_logic_vector(11 downto 0); 205 | 206 | begin 207 | 208 | if (pSltRst_n = '0') then 209 | 210 | SccCntChA := (others => '0'); 211 | SccCntChB := (others => '0'); 212 | SccCntChC := (others => '0'); 213 | SccCntChD := (others => '0'); 214 | SccCntChE := (others => '0'); 215 | 216 | SccPtrChA <= (others => '0'); 217 | SccPtrChB <= (others => '0'); 218 | SccPtrChC <= (others => '0'); 219 | SccPtrChD <= (others => '0'); 220 | SccPtrChE <= (others => '0'); 221 | 222 | elsif (pSltClk_n'event and pSltClk_n = '1') then 223 | 224 | if (SccFreqChA(11 downto 3) = "000000000" or SccRstChA = '1') then 225 | SccPtrChA <= "00000"; 226 | SccCntChA := SccFreqChA; 227 | elsif (SccCntChA = "000000000000") then 228 | SccPtrChA <= SccPtrChA + 1; 229 | SccCntChA := SccFreqChA; 230 | else 231 | SccCntChA := SccCntChA - 1; 232 | end if; 233 | 234 | if (SccFreqChB(11 downto 3) = "000000000" or SccRstChB = '1') then 235 | SccPtrChB <= "00000"; 236 | SccCntChB := SccFreqChB; 237 | elsif (SccCntChB = "000000000000") then 238 | SccPtrChB <= SccPtrChB + 1; 239 | SccCntChB := SccFreqChB; 240 | else 241 | SccCntChB := SccCntChB - 1; 242 | end if; 243 | 244 | if (SccFreqChC(11 downto 3) = "000000000" or SccRstChC = '1') then 245 | SccPtrChC <= "00000"; 246 | SccCntChC := SccFreqChC; 247 | elsif (SccCntChC = "000000000000") then 248 | SccPtrChC <= SccPtrChC + 1; 249 | SccCntChC := SccFreqChC; 250 | else 251 | SccCntChC := SccCntChC - 1; 252 | end if; 253 | 254 | if (SccFreqChD(11 downto 3) = "000000000" or SccRstChD = '1') then 255 | SccPtrChD <= "00000"; 256 | SccCntChD := SccFreqChD; 257 | elsif (SccCntChD = "000000000000") then 258 | SccPtrChD <= SccPtrChD + 1; 259 | SccCntChD := SccFreqChD; 260 | else 261 | SccCntChD := SccCntChD - 1; 262 | end if; 263 | 264 | if (SccFreqChE(11 downto 3) = "000000000" or SccRstChE = '1') then 265 | SccPtrChE <= "00000"; 266 | SccCntChE := SccFreqChE; 267 | elsif (SccCntChE = "000000000000") then 268 | SccPtrChE <= SccPtrChE + 1; 269 | SccCntChE := SccFreqChE; 270 | else 271 | SccCntChE := SccCntChE - 1; 272 | end if; 273 | 274 | end if; 275 | 276 | end process; 277 | 278 | ---------------------------------------------------------------- 279 | -- Mixer control 280 | ---------------------------------------------------------------- 281 | process(pSltClk_n, pSltRst_n) 282 | 283 | variable SccMix : std_logic_vector(14 downto 0); 284 | 285 | begin 286 | 287 | if (pSltRst_n = '0') then 288 | 289 | SccChEna <= '0'; 290 | SccMix := (others => '0'); 291 | SccAmp <= (others => '0'); 292 | 293 | elsif (pSltClk_n'event and pSltClk_n = '1') then 294 | 295 | if (SccWavCe = '1' or SccWavWx = '1') then 296 | SccChEna <= '0'; 297 | else 298 | SccChEna <= '1'; 299 | end if; 300 | 301 | if (SccChEna = '1') then 302 | 303 | case SccChNum is 304 | when "001" => SccMix := "000" & ((SccChanSel(0) & SccChanSel(0) & SccChanSel(0) & SccChanSel(0) & 305 | SccChanSel(0) & SccChanSel(0) & SccChanSel(0) & SccChanSel(0) 306 | and oWaveDat) xor "10000000") * SccVolChA; 307 | when "010" => SccMix := "000" & ((SccChanSel(1) & SccChanSel(1) & SccChanSel(1) & SccChanSel(1) & 308 | SccChanSel(1) & SccChanSel(1) & SccChanSel(1) & SccChanSel(1) 309 | and oWaveDat) xor "10000000") * SccVolChB + SccMix; 310 | when "011" => SccMix := "000" & ((SccChanSel(2) & SccChanSel(2) & SccChanSel(2) & SccChanSel(2) & 311 | SccChanSel(2) & SccChanSel(2) & SccChanSel(2) & SccChanSel(2) 312 | and oWaveDat) xor "10000000") * SccVolChC + SccMix; 313 | when "100" => SccMix := "000" & ((SccChanSel(3) & SccChanSel(3) & SccChanSel(3) & SccChanSel(3) & 314 | SccChanSel(3) & SccChanSel(3) & SccChanSel(3) & SccChanSel(3) 315 | and oWaveDat) xor "10000000") * SccVolChD + SccMix; 316 | when "101" => SccMix := "000" & ((SccChanSel(4) & SccChanSel(4) & SccChanSel(4) & SccChanSel(4) & 317 | SccChanSel(4) & SccChanSel(4) & SccChanSel(4) & SccChanSel(4) 318 | and oWaveDat) xor "10000000") * SccVolChE + SccMix; 319 | when others => null; 320 | 321 | end case; 322 | 323 | end if; 324 | 325 | if (SccClkEna = "111") then 326 | SccAmp <= SccMix(14 downto 7); 327 | end if; 328 | 329 | end if; 330 | 331 | end process; 332 | 333 | end RTL; 334 | -------------------------------------------------------------------------------- /Gerber/CRTPRT01.BMS: -------------------------------------------------------------------------------- 1 | G04* 2 | G04 File: CRTPRT01.BMS, Tue Aug 04 07:36:28 2015* 3 | G04 Source: P-CAD 2006 PCB, Version 19.02.958, (G:\Platform\MSX\Projects\Ptero\Canivore_SCC\CRTPRT01.pcb)* 4 | G04 Format: Gerber Format (RS-274-D), ASCII* 5 | G04* 6 | G04 Format Options: Absolute Positioning* 7 | G04 Leading-Zero Suppression* 8 | G04 Scale Factor 1:1* 9 | G04 NO Circular Interpolation* 10 | G04 Inch Units* 11 | G04 Numeric Format: 4.4 (XXXX.XXXX)* 12 | G04 G54 NOT Used for Aperture Change* 13 | G04 Apertures Embedded* 14 | G04* 15 | G04 File Options: Offset = (0.0mil,0.0mil)* 16 | G04 Drill Symbol Size = 80.0mil* 17 | G04 No Pad/Via Holes* 18 | G04* 19 | G04 File Contents: Pads* 20 | G04 No Vias* 21 | G04 No Designators* 22 | G04 No Types* 23 | G04 No Values* 24 | G04 No Drill Symbols* 25 | G04 Bot Mask* 26 | G04* 27 | %INCRTPRT01.BMS*% 28 | %ICAS*% 29 | %MOIN*% 30 | G04* 31 | G04 Aperture MACROs for general use --- invoked via D-code assignment * 32 | G04* 33 | G04 General MACRO for flashed round with rotation and/or offset hole * 34 | %AMROTOFFROUND* 35 | 1,1,$1,0.0000,0.0000* 36 | 1,0,$2,$3,$4*% 37 | G04* 38 | G04 General MACRO for flashed oval (obround) with rotation and/or offset hole * 39 | %AMROTOFFOVAL* 40 | 21,1,$1,$2,0.0000,0.0000,$3* 41 | 1,1,$4,$5,$6* 42 | 1,1,$4,0-$5,0-$6* 43 | 1,0,$7,$8,$9*% 44 | G04* 45 | G04 General MACRO for flashed oval (obround) with rotation and no hole * 46 | %AMROTOVALNOHOLE* 47 | 21,1,$1,$2,0.0000,0.0000,$3* 48 | 1,1,$4,$5,$6* 49 | 1,1,$4,0-$5,0-$6*% 50 | G04* 51 | G04 General MACRO for flashed rectangle with rotation and/or offset hole * 52 | %AMROTOFFRECT* 53 | 21,1,$1,$2,0.0000,0.0000,$3* 54 | 1,0,$4,$5,$6*% 55 | G04* 56 | G04 General MACRO for flashed rectangle with rotation and no hole * 57 | %AMROTRECTNOHOLE* 58 | 21,1,$1,$2,0.0000,0.0000,$3*% 59 | G04* 60 | G04 General MACRO for flashed rounded-rectangle * 61 | %AMROUNDRECT* 62 | 21,1,$1,$2-$4,0.0000,0.0000,$3* 63 | 21,1,$1-$4,$2,0.0000,0.0000,$3* 64 | 1,1,$4,$5,$6* 65 | 1,1,$4,$7,$8* 66 | 1,1,$4,0-$5,0-$6* 67 | 1,1,$4,0-$7,0-$8* 68 | 1,0,$9,$10,$11*% 69 | G04* 70 | G04 General MACRO for flashed rounded-rectangle with rotation and no hole * 71 | %AMROUNDRECTNOHOLE* 72 | 21,1,$1,$2-$4,0.0000,0.0000,$3* 73 | 21,1,$1-$4,$2,0.0000,0.0000,$3* 74 | 1,1,$4,$5,$6* 75 | 1,1,$4,$7,$8* 76 | 1,1,$4,0-$5,0-$6* 77 | 1,1,$4,0-$7,0-$8*% 78 | G04* 79 | G04 General MACRO for flashed regular polygon * 80 | %AMREGPOLY* 81 | 5,1,$1,0.0000,0.0000,$2,$3+$4* 82 | 1,0,$5,$6,$7*% 83 | G04* 84 | G04 General MACRO for flashed regular polygon with no hole * 85 | %AMREGPOLYNOHOLE* 86 | 5,1,$1,0.0000,0.0000,$2,$3+$4*% 87 | G04* 88 | G04 General MACRO for target * 89 | %AMTARGET* 90 | 6,0,0,$1,$2,$3,4,$4,$5,$6*% 91 | G04* 92 | G04 General MACRO for mounting hole * 93 | %AMMTHOLE* 94 | 1,1,$1,0,0* 95 | 1,0,$2,0,0* 96 | $1=$1-$2* 97 | $1=$1/2* 98 | 21,1,$2+$1,$3,0,0,$4* 99 | 21,1,$3,$2+$1,0,0,$4*% 100 | G04* 101 | G04* 102 | G04 D10 : "Ellipse X10.0mil Y10.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 103 | G04 Disc: OuterDia=0.0100* 104 | %ADD10C, 0.0100*% 105 | G04 D11 : "Ellipse X20.0mil Y20.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 106 | G04 Disc: OuterDia=0.0200* 107 | %ADD11C, 0.0200*% 108 | G04 D12 : "Ellipse X30.0mil Y30.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 109 | G04 Disc: OuterDia=0.0300* 110 | %ADD12C, 0.0300*% 111 | G04 D13 : "Ellipse X40.0mil Y40.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 112 | G04 Disc: OuterDia=0.0400* 113 | %ADD13C, 0.0400*% 114 | G04 D14 : "Ellipse X45.0mil Y45.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 115 | G04 Disc: OuterDia=0.0450* 116 | %ADD14C, 0.0450*% 117 | G04 D15 : "Ellipse X5.0mil Y5.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 118 | G04 Disc: OuterDia=0.0050* 119 | %ADD15C, 0.0050*% 120 | G04 D16 : "Ellipse X5.9mil Y5.9mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 121 | G04 Disc: OuterDia=0.0059* 122 | %ADD16C, 0.0059*% 123 | G04 D17 : "Ellipse X50.0mil Y50.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 124 | G04 Disc: OuterDia=0.0500* 125 | %ADD17C, 0.0500*% 126 | G04 D18 : "Ellipse X6.1mil Y6.1mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 127 | G04 Disc: OuterDia=0.0061* 128 | %ADD18C, 0.0061*% 129 | G04 D19 : "Ellipse X60.0mil Y60.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 130 | G04 Disc: OuterDia=0.0600* 131 | %ADD19C, 0.0600*% 132 | G04 D20 : "Ellipse X7.9mil Y7.9mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 133 | G04 Disc: OuterDia=0.0079* 134 | %ADD20C, 0.0079*% 135 | G04 D21 : "Ellipse X9.8mil Y9.8mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 136 | G04 Disc: OuterDia=0.0098* 137 | %ADD21C, 0.0098*% 138 | G04 D22 : "Ellipse X101.6mil Y101.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 139 | G04 Disc: OuterDia=0.1016* 140 | %ADD22C, 0.1016*% 141 | G04 D23 : "Ellipse X199.0mil Y199.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 142 | G04 Disc: OuterDia=0.1990* 143 | %ADD23C, 0.1990*% 144 | G04 D24 : "Ellipse X60.0mil Y60.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 145 | G04 Disc: OuterDia=0.0600* 146 | %ADD24C, 0.0600*% 147 | G04 D25 : "Ellipse X62.2mil Y62.2mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 148 | G04 Disc: OuterDia=0.0622* 149 | %ADD25C, 0.0622*% 150 | G04 D26 : "Ellipse X75.0mil Y75.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 151 | G04 Disc: OuterDia=0.0750* 152 | %ADD26C, 0.0750*% 153 | G04 D27 : "Ellipse X86.6mil Y86.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 154 | G04 Disc: OuterDia=0.0866* 155 | %ADD27C, 0.0866*% 156 | G04 D28 : "Mounting Hole X184.0mil Y184.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 157 | G04 Mounting Hole: Diameter=0.1840, Rotation=0.0, LineWidth=0.0050 * 158 | %ADD28MTHOLE, 0.1840 X0.1640 X0.0050 X0.0*% 159 | G04 D29 : "Mounting Hole X47.2mil Y47.2mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 160 | G04 Mounting Hole: Diameter=0.0472, Rotation=0.0, LineWidth=0.0050 * 161 | %ADD29MTHOLE, 0.0472 X0.0272 X0.0050 X0.0*% 162 | G04 D30 : "Rounded Rectangle X50.0mil Y350.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 163 | G04 RoundRct: DimX=0.0500, DimY=0.3500, CornerRad=0.0125, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 164 | %ADD30ROUNDRECTNOHOLE, 0.0500 X0.3500 X0.0 X0.0250 X-0.0125 X-0.1625 X-0.0125 X0.1625*% 165 | G04 D31 : "Rounded Rectangle X65.0mil Y365.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 166 | G04 RoundRct: DimX=0.0650, DimY=0.3650, CornerRad=0.0163, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 167 | %ADD31ROUNDRECTNOHOLE, 0.0650 X0.3650 X0.0 X0.0325 X-0.0163 X-0.1663 X-0.0163 X0.1663*% 168 | G04 D32 : "Rectangle X63.0mil Y106.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 169 | G04 Rectangular: DimX=0.0630, DimY=0.1063, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 170 | %ADD32R, 0.0630 X0.1063*% 171 | G04 D33 : "Rectangle X11.8mil Y63.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 172 | G04 Rectangular: DimX=0.0118, DimY=0.0630, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 173 | %ADD33R, 0.0118 X0.0630*% 174 | G04 D34 : "Rectangle X63.0mil Y11.8mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 175 | G04 Rectangular: DimX=0.0630, DimY=0.0118, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 176 | %ADD34R, 0.0630 X0.0118*% 177 | G04 D35 : "Rectangle X59.1mil Y12.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 178 | G04 Rectangular: DimX=0.0591, DimY=0.0120, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 179 | %ADD35R, 0.0591 X0.0120*% 180 | G04 D36 : "Rectangle X78.0mil Y121.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 181 | G04 Rectangular: DimX=0.0780, DimY=0.1213, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 182 | %ADD36R, 0.0780 X0.1213*% 183 | G04 D37 : "Rectangle X157.5mil Y118.1mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 184 | G04 Rectangular: DimX=0.1575, DimY=0.1181, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 185 | %ADD37R, 0.1575 X0.1181*% 186 | G04 D38 : "Rectangle X172.5mil Y133.1mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 187 | G04 Rectangular: DimX=0.1725, DimY=0.1331, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 188 | %ADD38R, 0.1725 X0.1331*% 189 | G04 D39 : "Rectangle X23.6mil Y88.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 190 | G04 Rectangular: DimX=0.0236, DimY=0.0886, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 191 | %ADD39R, 0.0236 X0.0886*% 192 | G04 D40 : "Rectangle X88.6mil Y23.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 193 | G04 Rectangular: DimX=0.0886, DimY=0.0236, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 194 | %ADD40R, 0.0886 X0.0236*% 195 | G04 D41 : "Rectangle X26.8mil Y78.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 196 | G04 Rectangular: DimX=0.0268, DimY=0.0780, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 197 | %ADD41R, 0.0268 X0.0780*% 198 | G04 D42 : "Rectangle X78.0mil Y26.8mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 199 | G04 Rectangular: DimX=0.0780, DimY=0.0268, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 200 | %ADD42R, 0.0780 X0.0268*% 201 | G04 D43 : "Rectangle X74.1mil Y27.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 202 | G04 Rectangular: DimX=0.0741, DimY=0.0270, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 203 | %ADD43R, 0.0741 X0.0270*% 204 | G04 D44 : "Rectangle X32.0mil Y32.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 205 | G04 Square: Side=0.0320, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 206 | %ADD44R, 0.0320 X0.0320*% 207 | G04 D45 : "Rectangle X38.6mil Y103.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 208 | G04 Rectangular: DimX=0.0386, DimY=0.1036, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 209 | %ADD45R, 0.0386 X0.1036*% 210 | G04 D46 : "Rectangle X103.6mil Y38.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 211 | G04 Rectangular: DimX=0.1036, DimY=0.0386, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 212 | %ADD46R, 0.1036 X0.0386*% 213 | G04 D47 : "Rectangle X39.4mil Y43.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 214 | G04 Rectangular: DimX=0.0394, DimY=0.0433, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 215 | %ADD47R, 0.0394 X0.0433*% 216 | G04 D48 : "Rectangle X43.3mil Y39.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 217 | G04 Rectangular: DimX=0.0433, DimY=0.0394, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 218 | %ADD48R, 0.0433 X0.0394*% 219 | G04 D49 : "Rectangle X39.4mil Y98.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 220 | G04 Rectangular: DimX=0.0394, DimY=0.0984, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 221 | %ADD49R, 0.0394 X0.0984*% 222 | G04 D50 : "Rectangle X47.0mil Y47.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 223 | G04 Square: Side=0.0470, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 224 | %ADD50R, 0.0470 X0.0470*% 225 | G04 D51 : "Rectangle X54.4mil Y113.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 226 | G04 Rectangular: DimX=0.0544, DimY=0.1134, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 227 | %ADD51R, 0.0544 X0.1134*% 228 | G04 D52 : "Rectangle X54.4mil Y58.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 229 | G04 Rectangular: DimX=0.0544, DimY=0.0583, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 230 | %ADD52R, 0.0544 X0.0583*% 231 | G04 D53 : "Rectangle X58.3mil Y54.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 232 | G04 Rectangular: DimX=0.0583, DimY=0.0544, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 233 | %ADD53R, 0.0583 X0.0544*% 234 | G04 D54 : "Rectangle X60.0mil Y60.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 235 | G04 Square: Side=0.0600, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 236 | %ADD54R, 0.0600 X0.0600*% 237 | G04 D55 : "Rectangle X75.0mil Y75.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 238 | G04 Square: Side=0.0750, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 239 | %ADD55R, 0.0750 X0.0750*% 240 | G04 D56 : "Rectangle X26.0mil Y80.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 241 | G04 Rectangular: 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437 | X258000D3* 438 | X262000D3* 439 | X261000D3* 440 | X265000D3* 441 | X264000D3* 442 | X242000D3* 443 | X254000D3* 444 | X251000D3* 445 | X248000D3* 446 | X245000D3* 447 | X266000D3* 448 | X263000D3* 449 | X260000D3* 450 | X257000D3* 451 | D02M02* 452 | -------------------------------------------------------------------------------- /BootBlock/font.inc: -------------------------------------------------------------------------------- 1 | <<<<<<< HEAD 2 | db #00,#00,#00,#00,#00,#00,#00,#00,#3C,#42,#A5,#81,#A5,#99,#42,#3C,#3C,#7E,#DB,#FF,#FF,#DB,#66,#3C,#6C,#FE,#FE,#FE,#7C,#38,#10,#00,#00,#00,#00,#FF,#FF,#00,#00,#00,#FF,#FF,#FF,#FF,#FF,#FF,#FF,#FF,#E7,#C3 3 | db #81,#81,#81,#C3,#E7,#00,#00,#00,#00,#F8,#F8,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#1F,#1F,#00,#00,#00,#18,#18,#18,#F8,#F8,#00,#00,#00,#04,#18,#24,#5C,#FC,#9C,#44,#38,#78,#B4,#30,#CC 4 | db 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#A8,#F8,#50,#00,#98,#98,#70,#20,#70,#98,#98,#00,#98,#98,#98,#70,#20,#20,#20,#00,#F8,#98,#18,#30,#60,#C8,#F8,#00,#78,#60,#60,#60,#60,#60,#78,#00,#00,#00,#C0,#60,#30,#18,#0C,#00,#F0,#30,#30,#30,#30,#30 17 | db #F0,#00,#00,#AA,#55,#AA,#55,#AA,#55,#00,#00,#00,#00,#00,#00,#00,#F8,#00,#C0,#60,#30,#00,#00,#00,#00,#00,#00,#00,#70,#18,#78,#98,#78,#00,#C0,#C0,#F0,#C8,#C8,#C8,#F0,#00,#00,#00,#70,#C8,#C0,#C8,#70,#00 18 | db #18,#18,#78,#98,#98,#98,#78,#00,#00,#00,#70,#C8,#F8,#C0,#70,#00,#30,#68,#60,#F8,#60,#60,#60,#00,#00,#00,#78,#98,#98,#78,#18,#70,#C0,#C0,#F0,#C8,#C8,#C8,#C8,#00,#30,#00,#70,#30,#30,#30,#78,#00,#18,#00 19 | db #38,#18,#18,#18,#98,#70,#C0,#C0,#C8,#D0,#E0,#D0,#C8,#00,#70,#30,#30,#30,#30,#30,#78,#00,#00,#00,#50,#F8,#F8,#A8,#88,#00,#00,#00,#F0,#C8,#C8,#C8,#C8,#00,#00,#00,#70,#98,#98,#98,#70,#00,#00,#00,#F0,#C8 20 | db #C8,#F0,#C0,#C0,#00,#00,#78,#98,#98,#78,#18,#18,#00,#00,#B0,#C8,#C0,#C0,#C0,#00,#00,#00,#78,#C0,#F0,#18,#F0,#00,#60,#60,#F0,#60,#60,#68,#30,#00,#00,#00,#98,#98,#98,#98,#6C,#00,#00,#00,#98,#98,#98,#70 21 | db #20,#00,#00,#00,#88,#88,#A8,#F8,#50,#00,#00,#00,#98,#70,#20,#70,#98,#00,#00,#00,#98,#98,#98,#78,#18,#70,#00,#00,#F8,#18,#30,#C0,#F8,#00,#38,#60,#60,#C0,#60,#60,#38,#00,#30,#30,#30,#00,#30,#30,#30,#00 22 | db #E0,#30,#30,#18,#30,#30,#E0,#00,#40,#A8,#10,#00,#00,#00,#00,#00,#00,#00,#20,#50,#F8,#00,#00,#00,#7F,#FF,#FF,#E0,#E0,#E0,#E0,#E0,#F8,#FC,#FC,#1C,#1C,#1C,#1C,#1C,#E0,#E0,#E0,#E0,#E0,#FF,#FF,#7F,#1C,#1C 23 | db #1C,#1C,#1C,#FC,#FC,#F8,#00,#00,#00,#00,#00,#FF,#FF,#FF,#FF,#FF,#FF,#00,#00,#00,#00,#00,#E0,#E0,#E0,#E0,#E0,#E0,#E0,#E0,#1C,#1C,#1C,#1C,#1C,#1C,#1C,#1C,#7F,#FF,#C0,#C0,#C0,#C0,#C0,#C0,#0C,#0C,#0C,#0C 24 | db #0C,#0C,#FC,#F8,#FF,#FF,#00,#00,#00,#00,#00,#00,#00,#00,#00,#00,#00,#00,#FF,#FF,#C0,#C0,#C0,#C0,#C0,#C0,#C0,#C0,#0C,#0C,#0C,#0C,#0C,#0C,#0C,#0C,#C0,#C0,#C0,#C0,#C0,#C0,#FF,#7F,#F8,#FC,#0C,#0C,#0C,#0C 25 | db #0C,#0C,#01,#03,#07,#0F,#07,#03,#01,#00,#FF,#7E,#3C,#18,#18,#3C,#7E,#FF,#81,#C3,#E7,#FF,#FF,#E7,#C3,#81,#F0,#F0,#F0,#F0,#00,#00,#00,#00,#00,#00,#00,#00,#0F,#0F,#0F,#0F,#0F,#0F,#0F,#0F,#00,#00,#00,#00 26 | db #00,#00,#00,#00,#F0,#F0,#F0,#F0,#33,#33,#CC,#CC,#33,#33,#CC,#CC,#00,#20,#20,#50,#50,#88,#F8,#00,#20,#20,#70,#20,#70,#20,#20,#00,#00,#00,#00,#50,#88,#A8,#50,#00,#FF,#FF,#FF,#FF,#FF,#FF,#FF,#FF,#00,#00 27 | db #00,#00,#FF,#FF,#FF,#FF,#F0,#F0,#F0,#F0,#F0,#F0,#F0,#F0,#0F,#0F,#0F,#0F,#0F,#0F,#0F,#0F,#FF,#FF,#FF,#FF,#00,#00,#00,#00,#00,#00,#68,#90,#90,#6C,#00,#00,#30,#48,#48,#70,#48,#48,#70,#C0,#F8,#88,#80,#80 28 | db #80,#80,#80,#00,#F8,#50,#50,#50,#50,#50,#98,#00,#F8,#88,#40,#20,#40,#88,#F8,#00,#00,#00,#78,#90,#90,#90,#60,#00,#00,#50,#50,#50,#50,#68,#80,#80,#00,#50,#A0,#20,#20,#20,#20,#00,#F8,#20,#70,#A8,#A8,#70 29 | db #20,#F8,#20,#50,#88,#F8,#88,#50,#20,#00,#70,#88,#88,#88,#50,#50,#D8,#00,#30,#40,#40,#20,#50,#50,#50,#20,#00,#00,#00,#50,#A8,#A8,#50,#00,#08,#70,#A8,#A8,#A8,#70,#80,#00,#38,#40,#80,#F8,#80,#40,#38,#00 30 | db #70,#88,#88,#88,#88,#88,#88,#00,#00,#F8,#00,#F8,#00,#F8,#00,#00,#20,#20,#F8,#20,#20,#00,#F8,#00,#C0,#30,#08,#30,#C0,#00,#F8,#00,#18,#60,#80,#60,#18,#00,#F8,#00,#10,#28,#20,#20,#20,#20,#20,#20,#20,#20 31 | db #20,#20,#20,#20,#A0,#40,#00,#20,#00,#F8,#00,#20,#00,#00,#00,#50,#A0,#00,#50,#A0,#00,#00,#00,#18,#24,#24,#18,#00,#00,#00,#00,#30,#78,#78,#30,#00,#00,#00,#00,#00,#00,#00,#30,#00,#00,#00,#3E,#20,#20,#20 32 | db #A0,#60,#20,#00,#A0,#50,#50,#50,#00,#00,#00,#00,#40,#A0,#20,#40,#E0,#00,#00,#00,#00,#38,#38,#38,#38,#38,#38,#00,#D8,#70,#98,#98,#70,#D8,#00,#00,#00,#00,#90,#A8,#E8,#A8,#90,#00,#00,#00,#70,#18,#78,#98 33 | db #78,#00,#00,#00,#F0,#C0,#F0,#C8,#F0,#00,#00,#00,#D0,#D0,#D0,#F8,#08,#00,#00,#00,#38,#58,#58,#78,#CC,#00,#00,#00,#70,#C8,#F8,#C0,#70,#00,#00,#20,#70,#A8,#A8,#70,#20,#00,#00,#00,#78,#68,#60,#60,#60,#00 34 | db #00,#00,#98,#70,#20,#70,#98,#00,#00,#00,#98,#98,#B8,#D8,#98,#00,#00,#70,#00,#98,#B8,#D8,#98,#00,#00,#00,#C8,#D0,#E0,#D0,#C8,#00,#00,#00,#78,#98,#98,#98,#98,#00,#00,#00,#50,#F8,#F8,#A8,#88,#00,#00,#00 35 | db #98,#98,#F8,#98,#98,#00,#00,#00,#70,#98,#98,#98,#70,#00,#00,#00,#F8,#98,#98,#98,#98,#00,#00,#00,#78,#98,#78,#58,#98,#00,#00,#00,#F0,#C8,#F0,#C0,#C0,#00,#00,#00,#70,#C8,#C0,#C8,#70,#00,#00,#00,#FC,#30 36 | db #30,#30,#30,#00,#00,#00,#8C,#58,#30,#60,#C0,#00,#00,#00,#A8,#70,#20,#70,#A8,#00,#00,#00,#F0,#C8,#F0,#C8,#F0,#00,#00,#00,#C0,#C0,#F0,#C8,#70,#00,#00,#00,#98,#98,#D8,#B8,#D8,#00,#00,#00,#F0,#18,#70,#18 37 | db #F0,#00,#00,#00,#A8,#A8,#A8,#A8,#F8,#00,#00,#00,#70,#98,#38,#98,#70,#00,#00,#00,#A8,#A8,#A8,#F8,#08,#00,#00,#00,#98,#98,#78,#18,#18,#00,#00,#00,#E0,#60,#70,#68,#70,#00,#90,#A8,#A8,#E8,#A8,#A8,#90,#00 38 | db #70,#98,#98,#98,#F8,#98,#98,#00,#F8,#C8,#C0,#F0,#C8,#C8,#F0,#00,#D0,#D0,#D0,#D0,#D0,#F8,#08,#00,#78,#58,#58,#98,#98,#F8,#D8,#00,#F8,#C8,#C0,#F0,#C0,#C8,#F8,#00,#20,#70,#A8,#A8,#A8,#70,#20,#00,#F8,#C8 39 | db #C8,#C0,#C0,#C0,#C0,#00,#98,#98,#70,#20,#70,#98,#98,#00,#98,#98,#98,#B8,#D8,#98,#98,#00,#70,#00,#98,#98,#B8,#D8,#98,#00,#C8,#C8,#D0,#E0,#D0,#C8,#C8,#00,#18,#38,#58,#58,#58,#58,#98,#00,#50,#F8,#F8,#A8 40 | db #88,#88,#88,#00,#98,#98,#98,#F8,#98,#98,#98,#00,#70,#98,#98,#98,#98,#98,#70,#00,#F8,#98,#98,#98,#98,#98,#98,#00,#78,#98,#98,#98,#78,#98,#98,#00,#F0,#C8,#C8,#F0,#C0,#C0,#C0,#00,#70,#C8,#C0,#C0,#C0,#C8 41 | db #70,#00,#FC,#30,#30,#30,#30,#30,#30,#00,#98,#98,#98,#78,#30,#60,#C0,#00,#A8,#A8,#70,#20,#70,#A8,#A8,#00,#F0,#C8,#C8,#F0,#C8,#C8,#F0,#00,#C0,#C0,#C0,#F0,#C8,#C8,#F0,#00,#98,#98,#98,#D8,#B8,#B8,#D8,#00 42 | ======= 43 | db #00,#00,#00,#00,#00,#00,#00,#00,#3C,#42,#A5,#81,#A5,#99,#42,#3C,#3C,#7E,#DB,#FF,#FF,#DB,#66,#3C,#6C,#FE,#FE,#FE,#7C,#38,#10,#00,#00,#00,#00,#FF,#FF,#00,#00,#00,#FF,#FF,#FF,#FF,#FF,#FF,#FF,#FF,#E7,#C3 44 | db #81,#81,#81,#C3,#E7,#00,#00,#00,#00,#F8,#F8,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#18,#1F,#1F,#00,#00,#00,#18,#18,#18,#F8,#F8,#00,#00,#00,#04,#18,#24,#5C,#FC,#9C,#44,#38,#78,#B4,#30,#CC 45 | db #B4,#B4,#84,#FC,#0C,#0C,#2C,#6C,#FC,#F8,#60,#20,#C0,#F0,#FC,#F0,#98,#0C,#00,#00,#AA,#55,#AA,#55,#AA,#55,#AA,#55,#7F,#80,#80,#80,#80,#80,#80,#80,#FF,#00,#00,#00,#00,#00,#00,#00,#F8,#04,#04,#04,#04,#04 46 | db #04,#04,#04,#04,#04,#04,#04,#04,#04,#04,#04,#04,#04,#04,#04,#04,#04,#F8,#00,#00,#00,#00,#00,#00,#00,#FF,#80,#80,#80,#80,#80,#80,#80,#7F,#80,#80,#80,#80,#80,#80,#80,#80,#7F,#80,#80,#9F,#90,#90,#90,#90 47 | db #FF,#00,#00,#FF,#00,#00,#00,#00,#F8,#04,#04,#E4,#24,#24,#24,#24,#90,#90,#90,#90,#90,#90,#90,#90,#24,#24,#24,#24,#E4,#04,#04,#F8,#00,#00,#00,#00,#FF,#00,#00,#FF,#90,#90,#90,#90,#9F,#80,#80,#7F,#24,#24 48 | db #24,#24,#24,#24,#24,#24,#00,#00,#00,#00,#00,#00,#00,#00,#30,#30,#30,#30,#30,#00,#30,#00,#D8,#D8,#48,#00,#00,#00,#00,#00,#58,#58,#FC,#58,#FC,#58,#58,#00,#30,#7C,#B0,#78,#34,#F8,#30,#00,#C0,#CC,#18,#30 49 | db #60,#D8,#18,#00,#60,#B0,#60,#AC,#98,#9C,#70,#00,#18,#30,#60,#00,#00,#00,#00,#00,#18,#30,#60,#60,#60,#30,#18,#00,#60,#30,#18,#18,#18,#30,#60,#00,#00,#20,#A8,#70,#A8,#20,#00,#00,#00,#30,#30,#FC,#30,#30 50 | db #00,#00,#00,#00,#00,#00,#00,#30,#30,#60,#00,#00,#00,#78,#00,#00,#00,#00,#00,#00,#00,#00,#00,#70,#70,#00,#00,#00,#0C,#18,#30,#60,#C0,#00,#70,#98,#98,#B8,#D8,#98,#70,#00,#30,#70,#B0,#30,#30,#30,#FC,#00 51 | db #70,#98,#18,#18,#70,#C0,#F8,#00,#70,#98,#18,#30,#18,#98,#70,#00,#38,#58,#98,#98,#F8,#18,#18,#00,#F8,#80,#F0,#18,#18,#98,#F0,#00,#70,#C8,#C0,#F0,#C8,#C8,#70,#00,#F8,#98,#18,#30,#30,#30,#30,#00,#70,#98 52 | db #98,#70,#98,#98,#70,#00,#70,#98,#98,#78,#18,#98,#70,#00,#00,#00,#30,#00,#00,#30,#00,#00,#00,#00,#30,#00,#00,#30,#30,#60,#18,#30,#60,#C0,#60,#30,#18,#00,#00,#00,#F8,#00,#F8,#00,#00,#00,#C0,#60,#30,#18 53 | db #30,#60,#C0,#00,#70,#98,#18,#18,#30,#00,#30,#00,#70,#98,#18,#78,#B8,#B8,#70,#00,#70,#98,#98,#98,#F8,#98,#98,#00,#F0,#C8,#C8,#F0,#C8,#C8,#F0,#00,#70,#C8,#C0,#C0,#C0,#C8,#70,#00,#F0,#C8,#C8,#C8,#C8,#C8 54 | db #F0,#00,#F8,#C8,#C0,#F0,#C0,#C8,#F8,#00,#F8,#C8,#C0,#F0,#C0,#C0,#C0,#00,#70,#C8,#C0,#F8,#C8,#C8,#70,#00,#98,#98,#98,#F8,#98,#98,#98,#00,#78,#30,#30,#30,#30,#30,#78,#00,#3C,#18,#18,#18,#98,#98,#70,#00 55 | db #C8,#C8,#D0,#E0,#D0,#C8,#C8,#00,#C0,#C0,#C0,#C0,#C0,#C8,#F8,#00,#50,#F8,#F8,#A8,#88,#88,#88,#00,#98,#D8,#D8,#B8,#98,#98,#98,#00,#70,#98,#98,#98,#98,#98,#70,#00,#F0,#C8,#C8,#F0,#C0,#C0,#C0,#00,#70,#C8 56 | db #C8,#C8,#E8,#D0,#68,#00,#F0,#C8,#C8,#C8,#F0,#C8,#C8,#00,#70,#C8,#C0,#70,#18,#98,#70,#00,#FC,#30,#30,#30,#30,#30,#30,#00,#98,#98,#98,#98,#98,#98,#70,#00,#98,#98,#98,#98,#70,#70,#20,#00,#88,#88,#88,#A8 57 | db #A8,#F8,#50,#00,#98,#98,#70,#20,#70,#98,#98,#00,#98,#98,#98,#70,#20,#20,#20,#00,#F8,#98,#18,#30,#60,#C8,#F8,#00,#78,#60,#60,#60,#60,#60,#78,#00,#00,#00,#C0,#60,#30,#18,#0C,#00,#F0,#30,#30,#30,#30,#30 58 | db #F0,#00,#00,#AA,#55,#AA,#55,#AA,#55,#00,#00,#00,#00,#00,#00,#00,#F8,#00,#C0,#60,#30,#00,#00,#00,#00,#00,#00,#00,#70,#18,#78,#98,#78,#00,#C0,#C0,#F0,#C8,#C8,#C8,#F0,#00,#00,#00,#70,#C8,#C0,#C8,#70,#00 59 | db #18,#18,#78,#98,#98,#98,#78,#00,#00,#00,#70,#C8,#F8,#C0,#70,#00,#30,#68,#60,#F8,#60,#60,#60,#00,#00,#00,#78,#98,#98,#78,#18,#70,#C0,#C0,#F0,#C8,#C8,#C8,#C8,#00,#30,#00,#70,#30,#30,#30,#78,#00,#18,#00 60 | db #38,#18,#18,#18,#98,#70,#C0,#C0,#C8,#D0,#E0,#D0,#C8,#00,#70,#30,#30,#30,#30,#30,#78,#00,#00,#00,#50,#F8,#F8,#A8,#88,#00,#00,#00,#F0,#C8,#C8,#C8,#C8,#00,#00,#00,#70,#98,#98,#98,#70,#00,#00,#00,#F0,#C8 61 | db #C8,#F0,#C0,#C0,#00,#00,#78,#98,#98,#78,#18,#18,#00,#00,#B0,#C8,#C0,#C0,#C0,#00,#00,#00,#78,#C0,#F0,#18,#F0,#00,#60,#60,#F0,#60,#60,#68,#30,#00,#00,#00,#98,#98,#98,#98,#6C,#00,#00,#00,#98,#98,#98,#70 62 | db #20,#00,#00,#00,#88,#88,#A8,#F8,#50,#00,#00,#00,#98,#70,#20,#70,#98,#00,#00,#00,#98,#98,#98,#78,#18,#70,#00,#00,#F8,#18,#30,#C0,#F8,#00,#38,#60,#60,#C0,#60,#60,#38,#00,#30,#30,#30,#00,#30,#30,#30,#00 63 | db #E0,#30,#30,#18,#30,#30,#E0,#00,#40,#A8,#10,#00,#00,#00,#00,#00,#00,#00,#20,#50,#F8,#00,#00,#00,#7F,#FF,#FF,#E0,#E0,#E0,#E0,#E0,#F8,#FC,#FC,#1C,#1C,#1C,#1C,#1C,#E0,#E0,#E0,#E0,#E0,#FF,#FF,#7F,#1C,#1C 64 | db #1C,#1C,#1C,#FC,#FC,#F8,#00,#00,#00,#00,#00,#FF,#FF,#FF,#FF,#FF,#FF,#00,#00,#00,#00,#00,#E0,#E0,#E0,#E0,#E0,#E0,#E0,#E0,#1C,#1C,#1C,#1C,#1C,#1C,#1C,#1C,#7F,#FF,#C0,#C0,#C0,#C0,#C0,#C0,#0C,#0C,#0C,#0C 65 | db #0C,#0C,#FC,#F8,#FF,#FF,#00,#00,#00,#00,#00,#00,#00,#00,#00,#00,#00,#00,#FF,#FF,#C0,#C0,#C0,#C0,#C0,#C0,#C0,#C0,#0C,#0C,#0C,#0C,#0C,#0C,#0C,#0C,#C0,#C0,#C0,#C0,#C0,#C0,#FF,#7F,#F8,#FC,#0C,#0C,#0C,#0C 66 | db #0C,#0C,#01,#03,#07,#0F,#07,#03,#01,#00,#FF,#7E,#3C,#18,#18,#3C,#7E,#FF,#81,#C3,#E7,#FF,#FF,#E7,#C3,#81,#F0,#F0,#F0,#F0,#00,#00,#00,#00,#00,#00,#00,#00,#0F,#0F,#0F,#0F,#0F,#0F,#0F,#0F,#00,#00,#00,#00 67 | db #00,#00,#00,#00,#F0,#F0,#F0,#F0,#33,#33,#CC,#CC,#33,#33,#CC,#CC,#00,#20,#20,#50,#50,#88,#F8,#00,#20,#20,#70,#20,#70,#20,#20,#00,#00,#00,#00,#50,#88,#A8,#50,#00,#FF,#FF,#FF,#FF,#FF,#FF,#FF,#FF,#00,#00 68 | db #00,#00,#FF,#FF,#FF,#FF,#F0,#F0,#F0,#F0,#F0,#F0,#F0,#F0,#0F,#0F,#0F,#0F,#0F,#0F,#0F,#0F,#FF,#FF,#FF,#FF,#00,#00,#00,#00,#00,#00,#68,#90,#90,#6C,#00,#00,#30,#48,#48,#70,#48,#48,#70,#C0,#F8,#88,#80,#80 69 | db #80,#80,#80,#00,#F8,#50,#50,#50,#50,#50,#98,#00,#F8,#88,#40,#20,#40,#88,#F8,#00,#00,#00,#78,#90,#90,#90,#60,#00,#00,#50,#50,#50,#50,#68,#80,#80,#00,#50,#A0,#20,#20,#20,#20,#00,#F8,#20,#70,#A8,#A8,#70 70 | db #20,#F8,#20,#50,#88,#F8,#88,#50,#20,#00,#70,#88,#88,#88,#50,#50,#D8,#00,#30,#40,#40,#20,#50,#50,#50,#20,#00,#00,#00,#50,#A8,#A8,#50,#00,#08,#70,#A8,#A8,#A8,#70,#80,#00,#38,#40,#80,#F8,#80,#40,#38,#00 71 | db #70,#88,#88,#88,#88,#88,#88,#00,#00,#F8,#00,#F8,#00,#F8,#00,#00,#20,#20,#F8,#20,#20,#00,#F8,#00,#C0,#30,#08,#30,#C0,#00,#F8,#00,#18,#60,#80,#60,#18,#00,#F8,#00,#10,#28,#20,#20,#20,#20,#20,#20,#20,#20 72 | db #20,#20,#20,#20,#A0,#40,#00,#20,#00,#F8,#00,#20,#00,#00,#00,#50,#A0,#00,#50,#A0,#00,#00,#00,#18,#24,#24,#18,#00,#00,#00,#00,#30,#78,#78,#30,#00,#00,#00,#00,#00,#00,#00,#30,#00,#00,#00,#3E,#20,#20,#20 73 | db #A0,#60,#20,#00,#A0,#50,#50,#50,#00,#00,#00,#00,#40,#A0,#20,#40,#E0,#00,#00,#00,#00,#38,#38,#38,#38,#38,#38,#00,#D8,#70,#98,#98,#70,#D8,#00,#00,#00,#00,#90,#A8,#E8,#A8,#90,#00,#00,#00,#70,#18,#78,#98 74 | db #78,#00,#00,#00,#F0,#C0,#F0,#C8,#F0,#00,#00,#00,#D0,#D0,#D0,#F8,#08,#00,#00,#00,#38,#58,#58,#78,#CC,#00,#00,#00,#70,#C8,#F8,#C0,#70,#00,#00,#20,#70,#A8,#A8,#70,#20,#00,#00,#00,#78,#68,#60,#60,#60,#00 75 | db #00,#00,#98,#70,#20,#70,#98,#00,#00,#00,#98,#98,#B8,#D8,#98,#00,#00,#70,#00,#98,#B8,#D8,#98,#00,#00,#00,#C8,#D0,#E0,#D0,#C8,#00,#00,#00,#78,#98,#98,#98,#98,#00,#00,#00,#50,#F8,#F8,#A8,#88,#00,#00,#00 76 | db #98,#98,#F8,#98,#98,#00,#00,#00,#70,#98,#98,#98,#70,#00,#00,#00,#F8,#98,#98,#98,#98,#00,#00,#00,#78,#98,#78,#58,#98,#00,#00,#00,#F0,#C8,#F0,#C0,#C0,#00,#00,#00,#70,#C8,#C0,#C8,#70,#00,#00,#00,#FC,#30 77 | db #30,#30,#30,#00,#00,#00,#8C,#58,#30,#60,#C0,#00,#00,#00,#A8,#70,#20,#70,#A8,#00,#00,#00,#F0,#C8,#F0,#C8,#F0,#00,#00,#00,#C0,#C0,#F0,#C8,#70,#00,#00,#00,#98,#98,#D8,#B8,#D8,#00,#00,#00,#F0,#18,#70,#18 78 | db #F0,#00,#00,#00,#A8,#A8,#A8,#A8,#F8,#00,#00,#00,#70,#98,#38,#98,#70,#00,#00,#00,#A8,#A8,#A8,#F8,#08,#00,#00,#00,#98,#98,#78,#18,#18,#00,#00,#00,#E0,#60,#70,#68,#70,#00,#90,#A8,#A8,#E8,#A8,#A8,#90,#00 79 | db #70,#98,#98,#98,#F8,#98,#98,#00,#F8,#C8,#C0,#F0,#C8,#C8,#F0,#00,#D0,#D0,#D0,#D0,#D0,#F8,#08,#00,#78,#58,#58,#98,#98,#F8,#D8,#00,#F8,#C8,#C0,#F0,#C0,#C8,#F8,#00,#20,#70,#A8,#A8,#A8,#70,#20,#00,#F8,#C8 80 | db #C8,#C0,#C0,#C0,#C0,#00,#98,#98,#70,#20,#70,#98,#98,#00,#98,#98,#98,#B8,#D8,#98,#98,#00,#70,#00,#98,#98,#B8,#D8,#98,#00,#C8,#C8,#D0,#E0,#D0,#C8,#C8,#00,#18,#38,#58,#58,#58,#58,#98,#00,#50,#F8,#F8,#A8 81 | db #88,#88,#88,#00,#98,#98,#98,#F8,#98,#98,#98,#00,#70,#98,#98,#98,#98,#98,#70,#00,#F8,#98,#98,#98,#98,#98,#98,#00,#78,#98,#98,#98,#78,#98,#98,#00,#F0,#C8,#C8,#F0,#C0,#C0,#C0,#00,#70,#C8,#C0,#C0,#C0,#C8 82 | db #70,#00,#FC,#30,#30,#30,#30,#30,#30,#00,#98,#98,#98,#78,#30,#60,#C0,#00,#A8,#A8,#70,#20,#70,#A8,#A8,#00,#F0,#C8,#C8,#F0,#C8,#C8,#F0,#00,#C0,#C0,#C0,#F0,#C8,#C8,#F0,#00,#98,#98,#98,#D8,#B8,#B8,#D8,#00 83 | >>>>>>> origin/master 84 | db #F0,#18,#18,#70,#18,#18,#F0,#00,#A8,#A8,#A8,#A8,#A8,#A8,#F8,#00,#70,#98,#18,#78,#18,#98,#70,#00,#A8,#A8,#A8,#A8,#A8,#F8,#08,#00,#98,#98,#98,#98,#78,#18,#18,#00,#FF,#FF,#FF,#FF,#FF,#FF,#FF,#FF -------------------------------------------------------------------------------- /Gerber/CRTPRT01.TMS: -------------------------------------------------------------------------------- 1 | G04* 2 | G04 File: CRTPRT01.TMS, Tue Aug 04 07:36:28 2015* 3 | G04 Source: P-CAD 2006 PCB, Version 19.02.958, (G:\Platform\MSX\Projects\Ptero\Canivore_SCC\CRTPRT01.pcb)* 4 | G04 Format: Gerber Format (RS-274-D), ASCII* 5 | G04* 6 | G04 Format Options: Absolute Positioning* 7 | G04 Leading-Zero Suppression* 8 | G04 Scale Factor 1:1* 9 | G04 NO Circular Interpolation* 10 | G04 Inch Units* 11 | G04 Numeric Format: 4.4 (XXXX.XXXX)* 12 | G04 G54 NOT Used for Aperture Change* 13 | G04 Apertures Embedded* 14 | G04* 15 | G04 File Options: Offset = (0.0mil,0.0mil)* 16 | G04 Drill Symbol Size = 80.0mil* 17 | G04 No Pad/Via Holes* 18 | G04* 19 | G04 File Contents: Pads* 20 | G04 No Vias* 21 | G04 No Designators* 22 | G04 No Types* 23 | G04 No Values* 24 | G04 No Drill Symbols* 25 | G04 Top Mask* 26 | G04* 27 | %INCRTPRT01.TMS*% 28 | %ICAS*% 29 | %MOIN*% 30 | G04* 31 | G04 Aperture MACROs for general use --- invoked via D-code assignment * 32 | G04* 33 | G04 General MACRO for flashed round with rotation and/or offset hole * 34 | %AMROTOFFROUND* 35 | 1,1,$1,0.0000,0.0000* 36 | 1,0,$2,$3,$4*% 37 | G04* 38 | G04 General MACRO for flashed oval (obround) with rotation and/or offset hole * 39 | %AMROTOFFOVAL* 40 | 21,1,$1,$2,0.0000,0.0000,$3* 41 | 1,1,$4,$5,$6* 42 | 1,1,$4,0-$5,0-$6* 43 | 1,0,$7,$8,$9*% 44 | G04* 45 | G04 General MACRO for flashed oval (obround) with rotation and no hole * 46 | %AMROTOVALNOHOLE* 47 | 21,1,$1,$2,0.0000,0.0000,$3* 48 | 1,1,$4,$5,$6* 49 | 1,1,$4,0-$5,0-$6*% 50 | G04* 51 | G04 General MACRO for flashed rectangle with rotation and/or offset hole * 52 | %AMROTOFFRECT* 53 | 21,1,$1,$2,0.0000,0.0000,$3* 54 | 1,0,$4,$5,$6*% 55 | G04* 56 | G04 General MACRO for flashed rectangle with rotation and no hole * 57 | %AMROTRECTNOHOLE* 58 | 21,1,$1,$2,0.0000,0.0000,$3*% 59 | G04* 60 | G04 General MACRO for flashed rounded-rectangle * 61 | %AMROUNDRECT* 62 | 21,1,$1,$2-$4,0.0000,0.0000,$3* 63 | 21,1,$1-$4,$2,0.0000,0.0000,$3* 64 | 1,1,$4,$5,$6* 65 | 1,1,$4,$7,$8* 66 | 1,1,$4,0-$5,0-$6* 67 | 1,1,$4,0-$7,0-$8* 68 | 1,0,$9,$10,$11*% 69 | G04* 70 | G04 General MACRO for flashed rounded-rectangle with rotation and no hole * 71 | %AMROUNDRECTNOHOLE* 72 | 21,1,$1,$2-$4,0.0000,0.0000,$3* 73 | 21,1,$1-$4,$2,0.0000,0.0000,$3* 74 | 1,1,$4,$5,$6* 75 | 1,1,$4,$7,$8* 76 | 1,1,$4,0-$5,0-$6* 77 | 1,1,$4,0-$7,0-$8*% 78 | G04* 79 | G04 General MACRO for flashed regular polygon * 80 | %AMREGPOLY* 81 | 5,1,$1,0.0000,0.0000,$2,$3+$4* 82 | 1,0,$5,$6,$7*% 83 | G04* 84 | G04 General MACRO for flashed regular polygon with no hole * 85 | %AMREGPOLYNOHOLE* 86 | 5,1,$1,0.0000,0.0000,$2,$3+$4*% 87 | G04* 88 | G04 General MACRO for target * 89 | %AMTARGET* 90 | 6,0,0,$1,$2,$3,4,$4,$5,$6*% 91 | G04* 92 | G04 General MACRO for mounting hole * 93 | %AMMTHOLE* 94 | 1,1,$1,0,0* 95 | 1,0,$2,0,0* 96 | $1=$1-$2* 97 | $1=$1/2* 98 | 21,1,$2+$1,$3,0,0,$4* 99 | 21,1,$3,$2+$1,0,0,$4*% 100 | G04* 101 | G04* 102 | G04 D10 : "Ellipse X10.0mil Y10.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 103 | G04 Disc: OuterDia=0.0100* 104 | %ADD10C, 0.0100*% 105 | G04 D11 : "Ellipse X20.0mil Y20.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 106 | G04 Disc: OuterDia=0.0200* 107 | %ADD11C, 0.0200*% 108 | G04 D12 : "Ellipse X30.0mil Y30.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 109 | G04 Disc: OuterDia=0.0300* 110 | %ADD12C, 0.0300*% 111 | G04 D13 : "Ellipse X40.0mil Y40.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 112 | G04 Disc: OuterDia=0.0400* 113 | %ADD13C, 0.0400*% 114 | G04 D14 : "Ellipse X45.0mil Y45.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 115 | G04 Disc: OuterDia=0.0450* 116 | %ADD14C, 0.0450*% 117 | G04 D15 : "Ellipse X5.0mil Y5.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 118 | G04 Disc: OuterDia=0.0050* 119 | %ADD15C, 0.0050*% 120 | G04 D16 : "Ellipse X5.9mil Y5.9mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 121 | G04 Disc: OuterDia=0.0059* 122 | %ADD16C, 0.0059*% 123 | G04 D17 : "Ellipse X50.0mil Y50.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 124 | G04 Disc: OuterDia=0.0500* 125 | %ADD17C, 0.0500*% 126 | G04 D18 : "Ellipse X6.1mil Y6.1mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 127 | G04 Disc: OuterDia=0.0061* 128 | %ADD18C, 0.0061*% 129 | G04 D19 : "Ellipse X60.0mil Y60.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 130 | G04 Disc: OuterDia=0.0600* 131 | %ADD19C, 0.0600*% 132 | G04 D20 : "Ellipse X7.9mil Y7.9mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 133 | G04 Disc: OuterDia=0.0079* 134 | %ADD20C, 0.0079*% 135 | G04 D21 : "Ellipse X9.8mil Y9.8mil H0.0mil 0.0deg (0.0mil,0.0mil) Draw"* 136 | G04 Disc: OuterDia=0.0098* 137 | %ADD21C, 0.0098*% 138 | G04 D22 : "Ellipse X101.6mil Y101.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 139 | G04 Disc: OuterDia=0.1016* 140 | %ADD22C, 0.1016*% 141 | G04 D23 : "Ellipse X199.0mil Y199.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 142 | G04 Disc: OuterDia=0.1990* 143 | %ADD23C, 0.1990*% 144 | G04 D24 : "Ellipse X60.0mil Y60.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 145 | G04 Disc: OuterDia=0.0600* 146 | %ADD24C, 0.0600*% 147 | G04 D25 : "Ellipse X62.2mil Y62.2mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 148 | G04 Disc: OuterDia=0.0622* 149 | %ADD25C, 0.0622*% 150 | G04 D26 : "Ellipse X75.0mil Y75.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 151 | G04 Disc: OuterDia=0.0750* 152 | %ADD26C, 0.0750*% 153 | G04 D27 : "Ellipse X86.6mil Y86.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 154 | G04 Disc: OuterDia=0.0866* 155 | %ADD27C, 0.0866*% 156 | G04 D28 : "Mounting Hole X184.0mil Y184.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 157 | G04 Mounting Hole: Diameter=0.1840, Rotation=0.0, LineWidth=0.0050 * 158 | %ADD28MTHOLE, 0.1840 X0.1640 X0.0050 X0.0*% 159 | G04 D29 : "Mounting Hole X47.2mil Y47.2mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 160 | G04 Mounting Hole: Diameter=0.0472, Rotation=0.0, LineWidth=0.0050 * 161 | %ADD29MTHOLE, 0.0472 X0.0272 X0.0050 X0.0*% 162 | G04 D30 : "Rounded Rectangle X50.0mil Y350.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 163 | G04 RoundRct: DimX=0.0500, DimY=0.3500, CornerRad=0.0125, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 164 | %ADD30ROUNDRECTNOHOLE, 0.0500 X0.3500 X0.0 X0.0250 X-0.0125 X-0.1625 X-0.0125 X0.1625*% 165 | G04 D31 : "Rounded Rectangle X65.0mil Y365.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 166 | G04 RoundRct: DimX=0.0650, DimY=0.3650, CornerRad=0.0163, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 167 | %ADD31ROUNDRECTNOHOLE, 0.0650 X0.3650 X0.0 X0.0325 X-0.0163 X-0.1663 X-0.0163 X0.1663*% 168 | G04 D32 : "Rectangle X63.0mil Y106.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 169 | G04 Rectangular: DimX=0.0630, DimY=0.1063, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 170 | %ADD32R, 0.0630 X0.1063*% 171 | G04 D33 : "Rectangle X11.8mil Y63.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 172 | G04 Rectangular: DimX=0.0118, DimY=0.0630, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 173 | %ADD33R, 0.0118 X0.0630*% 174 | G04 D34 : "Rectangle X63.0mil Y11.8mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 175 | G04 Rectangular: DimX=0.0630, DimY=0.0118, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 176 | %ADD34R, 0.0630 X0.0118*% 177 | G04 D35 : "Rectangle X59.1mil Y12.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 178 | G04 Rectangular: DimX=0.0591, DimY=0.0120, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 179 | %ADD35R, 0.0591 X0.0120*% 180 | G04 D36 : "Rectangle X78.0mil Y121.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 181 | G04 Rectangular: DimX=0.0780, DimY=0.1213, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 182 | %ADD36R, 0.0780 X0.1213*% 183 | G04 D37 : "Rectangle X157.5mil Y118.1mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 184 | G04 Rectangular: DimX=0.1575, DimY=0.1181, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 185 | %ADD37R, 0.1575 X0.1181*% 186 | G04 D38 : "Rectangle X172.5mil Y133.1mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 187 | G04 Rectangular: DimX=0.1725, DimY=0.1331, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 188 | %ADD38R, 0.1725 X0.1331*% 189 | G04 D39 : "Rectangle X23.6mil Y88.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 190 | G04 Rectangular: DimX=0.0236, DimY=0.0886, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 191 | %ADD39R, 0.0236 X0.0886*% 192 | G04 D40 : "Rectangle X88.6mil Y23.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 193 | G04 Rectangular: DimX=0.0886, DimY=0.0236, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 194 | %ADD40R, 0.0886 X0.0236*% 195 | G04 D41 : "Rectangle X26.8mil Y78.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 196 | G04 Rectangular: DimX=0.0268, DimY=0.0780, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 197 | %ADD41R, 0.0268 X0.0780*% 198 | G04 D42 : "Rectangle X78.0mil Y26.8mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 199 | G04 Rectangular: DimX=0.0780, DimY=0.0268, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 200 | %ADD42R, 0.0780 X0.0268*% 201 | G04 D43 : "Rectangle X74.1mil Y27.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 202 | G04 Rectangular: DimX=0.0741, DimY=0.0270, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 203 | %ADD43R, 0.0741 X0.0270*% 204 | G04 D44 : "Rectangle X32.0mil Y32.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 205 | G04 Square: Side=0.0320, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 206 | %ADD44R, 0.0320 X0.0320*% 207 | G04 D45 : "Rectangle X38.6mil Y103.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 208 | G04 Rectangular: DimX=0.0386, DimY=0.1036, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 209 | %ADD45R, 0.0386 X0.1036*% 210 | G04 D46 : "Rectangle X103.6mil Y38.6mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 211 | G04 Rectangular: DimX=0.1036, DimY=0.0386, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 212 | %ADD46R, 0.1036 X0.0386*% 213 | G04 D47 : "Rectangle X39.4mil Y43.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 214 | G04 Rectangular: DimX=0.0394, DimY=0.0433, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 215 | %ADD47R, 0.0394 X0.0433*% 216 | G04 D48 : "Rectangle X43.3mil Y39.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 217 | G04 Rectangular: DimX=0.0433, DimY=0.0394, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 218 | %ADD48R, 0.0433 X0.0394*% 219 | G04 D49 : "Rectangle X39.4mil Y98.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 220 | G04 Rectangular: DimX=0.0394, DimY=0.0984, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 221 | %ADD49R, 0.0394 X0.0984*% 222 | G04 D50 : "Rectangle X47.0mil Y47.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 223 | G04 Square: Side=0.0470, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 224 | %ADD50R, 0.0470 X0.0470*% 225 | G04 D51 : "Rectangle X54.4mil Y113.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 226 | G04 Rectangular: DimX=0.0544, DimY=0.1134, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 227 | %ADD51R, 0.0544 X0.1134*% 228 | G04 D52 : "Rectangle X54.4mil Y58.3mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 229 | G04 Rectangular: DimX=0.0544, DimY=0.0583, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 230 | %ADD52R, 0.0544 X0.0583*% 231 | G04 D53 : "Rectangle X58.3mil Y54.4mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 232 | G04 Rectangular: DimX=0.0583, DimY=0.0544, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 233 | %ADD53R, 0.0583 X0.0544*% 234 | G04 D54 : "Rectangle X60.0mil Y60.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 235 | G04 Square: Side=0.0600, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 236 | %ADD54R, 0.0600 X0.0600*% 237 | G04 D55 : "Rectangle X75.0mil Y75.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 238 | G04 Square: Side=0.0750, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000* 239 | %ADD55R, 0.0750 X0.0750*% 240 | G04 D56 : "Rectangle X26.0mil Y80.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 241 | G04 Rectangular: DimX=0.0260, DimY=0.0800, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 242 | %ADD56R, 0.0260 X0.0800*% 243 | G04 D57 : "Rectangle X41.0mil Y95.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 244 | G04 Rectangular: DimX=0.0410, DimY=0.0950, Rotation=0.0, OffsetX=0.0000, OffsetY=0.0000, HoleDia=0.0000 * 245 | %ADD57R, 0.0410 X0.0950*% 246 | G04 D58 : "Ellipse X40.0mil Y40.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 247 | G04 Disc: OuterDia=0.0400* 248 | %ADD58C, 0.0400*% 249 | G04 D59 : "Ellipse X55.0mil Y55.0mil H0.0mil 0.0deg (0.0mil,0.0mil) Flash"* 250 | G04 Disc: OuterDia=0.0550* 251 | %ADD59C, 0.0550*% 252 | G04* 253 | %FSLAX44Y44*% 254 | %SFA1B1*% 255 | %OFA0.0000B0.0000*% 256 | G04* 257 | G70* 258 | G90* 259 | G01* 260 | D2* 261 | %LNTop Mask*% 262 | D52* 263 | X247000Y265709D3* 264 | Y265040D3* 265 | X248000Y265709D3* 266 | Y265040D3* 267 | X250000Y265709D3* 268 | Y265040D3* 269 | X251000Y265709D3* 270 | Y265040D3* 271 | X253000Y265709D3* 272 | Y265040D3* 273 | X254000Y265709D3* 274 | Y265040D3* 275 | X256000Y265709D3* 276 | Y265040D3* 277 | X257000Y265709D3* 278 | Y265040D3* 279 | X259000Y265709D3* 280 | Y265040D3* 281 | X260000Y265709D3* 282 | Y265040D3* 283 | X262000Y265709D3* 284 | Y265040D3* 285 | X263000Y265709D3* 286 | Y265040D3* 287 | X265000Y265709D3* 288 | Y265040D3* 289 | X266000Y265709D3* 290 | Y265040D3* 291 | D53* 292 | X268934Y269280D3* 293 | X268265D3* 294 | D26* 295 | X262875Y278750D3* 296 | X264875D3* 297 | D53* 298 | X268934Y269910D3* 299 | X268265D3* 300 | D52* 301 | X233625Y271834D3* 302 | Y271165D3* 303 | D53* 304 | X236790Y273500D3* 305 | X237459D3* 306 | X234040Y273875D3* 307 | X234709D3* 308 | X239040Y283500D3* 309 | X239709D3* 310 | X239040Y284125D3* 311 | X239709D3* 312 | D52* 313 | X249000Y265709D3* 314 | Y265040D3* 315 | X252000Y265709D3* 316 | Y265040D3* 317 | X246000Y265709D3* 318 | Y265040D3* 319 | D53* 320 | X242915Y283500D3* 321 | X243584D3* 322 | X242915Y284125D3* 323 | X243584D3* 324 | D52* 325 | X255000Y265709D3* 326 | Y265040D3* 327 | X258000Y265709D3* 328 | Y265040D3* 329 | X261000Y265709D3* 330 | Y265040D3* 331 | X264000Y265709D3* 332 | Y265040D3* 333 | X264100Y274895D3* 334 | Y275564D3* 335 | D53* 336 | X263665Y282750D3* 337 | X264334D3* 338 | D50* 339 | X236120Y273475D3* 340 | X235250Y273075D3* 341 | Y273875D3* 342 | X234025Y273370D3* 343 | X234425Y272500D3* 344 | X233625D3* 345 | D53* 346 | X236790Y272875D3* 347 | X237459D3* 348 | D25* 349 | X233656Y284500D3* 350 | X237593D3* 351 | D22* 352 | X234640Y282531D3* 353 | D25* 354 | X233656Y285484D3* 355 | D22* 356 | X237593Y282531D3* 357 | D25* 358 | Y285484D3* 359 | X235625Y282531D3* 360 | D22* 361 | X236609D3* 362 | X233656D3* 363 | X235625Y284500D3* 364 | D53* 365 | X239040Y284750D3* 366 | X239709D3* 367 | X242915D3* 368 | X243584D3* 369 | D52* 370 | X264110Y273474D3* 371 | Y272805D3* 372 | D26* 373 | X270250Y279750D3* 374 | X269250D3* 375 | Y280750D3* 376 | X270250D3* 377 | X269250Y281750D3* 378 | X270250D3* 379 | X269250Y282750D3* 380 | X270250D3* 381 | Y283750D3* 382 | D55* 383 | X269250D3* 384 | D23* 385 | X243000Y269221D3* 386 | D43* 387 | X238390Y271552D3* 388 | Y271749D3* 389 | Y271946D3* 390 | Y272142D3* 391 | Y272339D3* 392 | Y272536D3* 393 | Y272733D3* 394 | Y272930D3* 395 | Y273127D3* 396 | Y273324D3* 397 | Y273520D3* 398 | Y273717D3* 399 | Y273914D3* 400 | Y274308D3* 401 | Y274505D3* 402 | Y274702D3* 403 | Y274898D3* 404 | Y275095D3* 405 | Y275292D3* 406 | Y275489D3* 407 | Y275686D3* 408 | Y275883D3* 409 | Y276080D3* 410 | X246264Y271552D3* 411 | Y271749D3* 412 | Y271946D3* 413 | Y272142D3* 414 | Y272339D3* 415 | Y272536D3* 416 | Y272733D3* 417 | Y272930D3* 418 | Y273127D3* 419 | Y273324D3* 420 | Y273520D3* 421 | Y273717D3* 422 | Y273914D3* 423 | Y274308D3* 424 | Y274505D3* 425 | Y274702D3* 426 | Y274898D3* 427 | Y275095D3* 428 | Y275292D3* 429 | Y275489D3* 430 | Y275686D3* 431 | Y275883D3* 432 | Y276080D3* 433 | X238390Y274111D3* 434 | X246264D3* 435 | D45* 436 | X267250Y275433D3* 437 | X266750Y272066D3* 438 | X267250D3* 439 | X267750D3* 440 | X268250D3* 441 | D46* 442 | X268933Y272750D3* 443 | Y273250D3* 444 | Y273750D3* 445 | Y274250D3* 446 | Y274750D3* 447 | D45* 448 | X268250Y275433D3* 449 | X266750D3* 450 | X267750D3* 451 | X266250D3* 452 | D46* 453 | X265566Y274750D3* 454 | Y274250D3* 455 | Y273750D3* 456 | Y273250D3* 457 | Y272750D3* 458 | D45* 459 | X266250Y272066D3* 460 | D23* 461 | X265000Y267174D3* 462 | D42* 463 | X248346Y282182D3* 464 | Y280410D3* 465 | D41* 466 | X256870Y269721D3* 467 | X257066D3* 468 | X257263D3* 469 | X257460D3* 470 | X257657D3* 471 | X257854D3* 472 | X258051D3* 473 | X258248D3* 474 | X258444D3* 475 | X258641D3* 476 | D42* 477 | X248346Y280213D3* 478 | D41* 479 | X258838Y269721D3* 480 | X259035D3* 481 | X259232D3* 482 | X259429D3* 483 | X259625D3* 484 | X259822D3* 485 | X260019D3* 486 | X260216D3* 487 | X260413D3* 488 | X260610D3* 489 | D42* 490 | X248346Y280016D3* 491 | D41* 492 | X260807Y269721D3* 493 | D42* 494 | X261653Y270567D3* 495 | Y270764D3* 496 | Y270961D3* 497 | Y271158D3* 498 | Y271355D3* 499 | Y271552D3* 500 | Y271749D3* 501 | Y271945D3* 502 | Y272142D3* 503 | X248346Y279819D3* 504 | X261653Y272339D3* 505 | Y272536D3* 506 | Y272733D3* 507 | Y272930D3* 508 | Y273126D3* 509 | Y273323D3* 510 | Y273520D3* 511 | Y273717D3* 512 | Y273914D3* 513 | Y274111D3* 514 | X248346Y279623D3* 515 | X261653Y274308D3* 516 | Y274504D3* 517 | Y274701D3* 518 | Y274898D3* 519 | Y275095D3* 520 | Y275292D3* 521 | Y275489D3* 522 | Y275686D3* 523 | Y275882D3* 524 | Y276079D3* 525 | X248346Y279426D3* 526 | X261653Y276276D3* 527 | Y276473D3* 528 | Y276670D3* 529 | Y276867D3* 530 | Y277063D3* 531 | Y277260D3* 532 | Y277457D3* 533 | Y277654D3* 534 | Y277851D3* 535 | Y278048D3* 536 | X248346Y279229D3* 537 | X261653Y278245D3* 538 | Y278441D3* 539 | Y278638D3* 540 | Y278835D3* 541 | Y279032D3* 542 | Y279229D3* 543 | Y279426D3* 544 | Y279623D3* 545 | Y279819D3* 546 | Y280016D3* 547 | X248346Y279032D3* 548 | X261653Y280213D3* 549 | Y280410D3* 550 | Y280607D3* 551 | Y280804D3* 552 | Y281000D3* 553 | Y281197D3* 554 | Y281394D3* 555 | Y281591D3* 556 | Y281788D3* 557 | Y281985D3* 558 | X248346Y278835D3* 559 | X261653Y282182D3* 560 | D41* 561 | X260807Y283028D3* 562 | X260610D3* 563 | X260413D3* 564 | X260216D3* 565 | X260019D3* 566 | X259822D3* 567 | X259625D3* 568 | X259429D3* 569 | X259232D3* 570 | D42* 571 | X248346Y278638D3* 572 | D41* 573 | X259035Y283028D3* 574 | X258838D3* 575 | X258641D3* 576 | X258444D3* 577 | X258248D3* 578 | X258051D3* 579 | X257854D3* 580 | X257657D3* 581 | X257460D3* 582 | X257263D3* 583 | D42* 584 | X248346Y281985D3* 585 | Y278441D3* 586 | D41* 587 | X257066Y283028D3* 588 | X256870D3* 589 | X256673D3* 590 | X256476D3* 591 | X256279D3* 592 | X256082D3* 593 | X255885D3* 594 | X255688D3* 595 | X255492D3* 596 | X255295D3* 597 | D42* 598 | X248346Y278245D3* 599 | D41* 600 | X255098Y283028D3* 601 | X254901D3* 602 | X254704D3* 603 | X254507D3* 604 | X254311D3* 605 | X254114D3* 606 | X253917D3* 607 | X253720D3* 608 | X253523D3* 609 | X253326D3* 610 | D42* 611 | X248346Y278048D3* 612 | D41* 613 | X253129Y283028D3* 614 | X252933D3* 615 | X252736D3* 616 | X252539D3* 617 | X252342D3* 618 | X252145D3* 619 | X251948D3* 620 | X251751D3* 621 | X251555D3* 622 | X251358D3* 623 | D42* 624 | X248346Y277851D3* 625 | D41* 626 | X251161Y283028D3* 627 | X250964D3* 628 | X250767D3* 629 | X250570D3* 630 | X250374D3* 631 | X250177D3* 632 | X249980D3* 633 | X249783D3* 634 | X249586D3* 635 | X249389D3* 636 | D42* 637 | X248346Y277654D3* 638 | D41* 639 | X249192Y283028D3* 640 | D42* 641 | X248346Y277457D3* 642 | Y277260D3* 643 | Y277063D3* 644 | Y276867D3* 645 | Y276670D3* 646 | Y281788D3* 647 | Y276473D3* 648 | Y276276D3* 649 | Y276079D3* 650 | Y275882D3* 651 | Y275686D3* 652 | Y275489D3* 653 | Y275292D3* 654 | Y275095D3* 655 | Y274898D3* 656 | Y274701D3* 657 | Y281591D3* 658 | Y274504D3* 659 | Y274308D3* 660 | Y274111D3* 661 | Y273914D3* 662 | Y273717D3* 663 | Y273520D3* 664 | Y273323D3* 665 | Y273126D3* 666 | Y272930D3* 667 | Y272733D3* 668 | Y281394D3* 669 | Y272536D3* 670 | Y272339D3* 671 | Y272142D3* 672 | Y271945D3* 673 | Y271749D3* 674 | Y271552D3* 675 | Y271355D3* 676 | Y271158D3* 677 | Y270961D3* 678 | Y270764D3* 679 | Y281197D3* 680 | Y270567D3* 681 | D41* 682 | X249192Y269721D3* 683 | X249389D3* 684 | X249586D3* 685 | X249783D3* 686 | X249980D3* 687 | X250177D3* 688 | X250374D3* 689 | X250570D3* 690 | X250767D3* 691 | D42* 692 | X248346Y281000D3* 693 | D41* 694 | X250964Y269721D3* 695 | X251161D3* 696 | X251358D3* 697 | X251555D3* 698 | X251751D3* 699 | X251948D3* 700 | X252145D3* 701 | X252342D3* 702 | X252539D3* 703 | X252736D3* 704 | D42* 705 | X248346Y280804D3* 706 | D41* 707 | X252933Y269721D3* 708 | X253129D3* 709 | X253326D3* 710 | X253523D3* 711 | X253720D3* 712 | X253917D3* 713 | X254114D3* 714 | X254311D3* 715 | X254507D3* 716 | X254704D3* 717 | D42* 718 | X248346Y280607D3* 719 | D41* 720 | X254901Y269721D3* 721 | X255098D3* 722 | X255295D3* 723 | X255492D3* 724 | X255688D3* 725 | X255885D3* 726 | X256082D3* 727 | X256279D3* 728 | X256476D3* 729 | X256673D3* 730 | D31* 731 | X244000Y262750D3* 732 | X243000D3* 733 | X247000D3* 734 | X246000D3* 735 | X250000D3* 736 | X249000D3* 737 | X253000D3* 738 | X252000D3* 739 | X256000D3* 740 | X255000D3* 741 | X259000D3* 742 | X258000D3* 743 | X262000D3* 744 | X261000D3* 745 | X265000D3* 746 | X264000D3* 747 | X242000D3* 748 | X254000D3* 749 | X251000D3* 750 | X248000D3* 751 | X245000D3* 752 | X266000D3* 753 | X263000D3* 754 | X260000D3* 755 | X257000D3* 756 | D02M02* 757 | -------------------------------------------------------------------------------- /Firmware/Sources/scc_save1.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------- 2 | -- Title : scc.vhd 3 | -- Function : Sound Creation Chip (KONAMI) 4 | -- Date : 28th,August,2000 5 | -- Revision : 1.01 6 | -- Author : Kazuhiro TSUJIKAWA (ESE Artists' factory) 7 | ---------------------------------------------------------------- 8 | library IEEE; 9 | use IEEE.std_logic_1164.all; 10 | use IEEE.std_logic_unsigned.all; 11 | 12 | entity scc is 13 | port( 14 | pSltClk : IN std_logic; 15 | pSltRst_n : IN std_logic; 16 | pSltSltsl_n : IN std_logic; 17 | pSltIorq_n : IN std_logic; 18 | pSltRd_n : IN std_logic; 19 | pSltWr_n : IN std_logic; 20 | pSltAdr : IN std_logic_vector(15 downto 0); 21 | pSltDat : INOUT std_logic_vector(7 downto 0); 22 | pSltBdir_n : OUT std_logic; 23 | 24 | pSltCs1 : IN std_logic; 25 | pSltCs2 : IN std_logic; 26 | pSltCs12 : IN std_logic; 27 | pSltRfsh_n : IN std_logic; 28 | pSltWait_n : IN std_logic; 29 | pSltInt_n : IN std_logic; 30 | pSltM1_n : IN std_logic; 31 | pSltMerq_n : IN std_logic; 32 | 33 | pSltClk2 : IN std_logic; 34 | pSltRsv5 : OUT std_logic; 35 | pSltRsv16 : OUT std_logic; 36 | 37 | pSltSndL : OUT std_logic; 38 | pSltSndR : OUT std_logic; 39 | pSltSound : OUT std_logic; 40 | 41 | -- FLASH ROM interface 42 | pFlAdr : OUT std_logic_vector(22 downto 0); 43 | pFlDat : INOUT std_logic_vector(7 downto 0); 44 | pFlDatH : IN std_logic_vector(6 downto 0); 45 | pFlCS_n : OUT std_logic; 46 | pFlOE_n : OUT std_logic; 47 | pFlW_n : OUT std_logic; 48 | pFlBYTE_n : OUT std_logic; 49 | pFlRP_n : OUT std_logic; 50 | pFlRB_b : IN std_logic; 51 | pFlVpp : OUT std_logic 52 | 53 | ); 54 | end scc; 55 | 56 | architecture RTL of scc is 57 | 58 | component scc_wave 59 | port( 60 | pSltClk_n : IN std_logic; 61 | pSltRst_n : IN std_logic; 62 | pSltAdr : IN std_logic_vector(7 downto 0); 63 | pSltDat : INOUT std_logic_vector(7 downto 0); 64 | SccAmp : OUT std_logic_vector(7 downto 0); 65 | 66 | SccRegWe : IN std_logic; 67 | SccModWe : IN std_logic; 68 | SccWavCe : IN std_logic; 69 | SccWavOe : IN std_logic; 70 | SccWavWe : IN std_logic; 71 | SccWavWx : IN std_logic; 72 | SccWavAdr : IN std_logic_vector(4 downto 0); 73 | SccWavDat : IN std_logic_vector(7 downto 0) 74 | ); 75 | end component; 76 | 77 | signal pSltClk_n : std_logic; 78 | signal DevHit : std_logic; 79 | signal Dec1FFE : std_logic; 80 | signal DecSccA : std_logic; 81 | signal DecSccB : std_logic; 82 | 83 | signal SccBank0 : std_logic_vector(7 downto 0); 84 | signal SccBank1 : std_logic_vector(7 downto 0); 85 | signal SccBank2 : std_logic_vector(7 downto 0); 86 | signal SccBank3 : std_logic_vector(7 downto 0); 87 | signal SccModeA : std_logic_vector(7 downto 0); 88 | signal SccModeB : std_logic_vector(7 downto 0); 89 | 90 | signal SccRegWe : std_logic; 91 | signal SccModWe : std_logic; 92 | signal SccWavCe : std_logic; 93 | signal SccWavOe : std_logic; 94 | signal SccWavWe : std_logic; 95 | signal SccWavWx : std_logic; 96 | signal SccWavAdr : std_logic_vector(4 downto 0); 97 | signal SccWavDat : std_logic_vector(7 downto 0); 98 | 99 | signal SccAmp : std_logic_vector(7 downto 0); 100 | 101 | -- Multimode card register 102 | 103 | signal CardMDR : std_logic_vector(7 downto 0); 104 | signal AddrM0 : std_logic_vector(7 downto 0); 105 | signal AddrM1 : std_logic_vector(7 downto 0); 106 | signal AddrM2 : std_logic_vector(6 downto 0); 107 | -- signal DatM0 : std_logic_vector(7 downto 0); 108 | signal AddrFR : std_logic_vector(6 downto 0); 109 | 110 | signal R1Mask : std_logic_vector(7 downto 0); 111 | signal R1Addr : std_logic_vector(7 downto 0); 112 | signal R1Reg : std_logic_vector(7 downto 0); 113 | signal R1Mult : std_logic_vector(7 downto 0); 114 | signal B1MaskR : std_logic_vector(7 downto 0); 115 | signal B1AdrD : std_logic_vector(7 downto 0); 116 | -- signal B1MaskD : std_logic_vector(7 downto 0); 117 | 118 | signal R2Mask : std_logic_vector(7 downto 0); 119 | signal R2Addr : std_logic_vector(7 downto 0); 120 | signal R2Reg : std_logic_vector(7 downto 0); 121 | signal R2Mult : std_logic_vector(7 downto 0); 122 | signal B2MaskR : std_logic_vector(7 downto 0); 123 | signal B2AdrD : std_logic_vector(7 downto 0); 124 | -- signal B2MaskD : std_logic_vector(7 downto 0); 125 | 126 | signal R3Mask : std_logic_vector(7 downto 0); 127 | signal R3Addr : std_logic_vector(7 downto 0); 128 | signal R3Reg : std_logic_vector(7 downto 0); 129 | signal R3Mult : std_logic_vector(7 downto 0); 130 | signal B3MaskR : std_logic_vector(7 downto 0); 131 | signal B3AdrD : std_logic_vector(7 downto 0); 132 | -- signal B3MaskD : std_logic_vector(7 downto 0); 133 | 134 | signal R4Mask : std_logic_vector(7 downto 0); 135 | signal R4Addr : std_logic_vector(7 downto 0); 136 | signal R4Reg : std_logic_vector(7 downto 0); 137 | signal R4Mult : std_logic_vector(7 downto 0); 138 | signal B4MaskR : std_logic_vector(7 downto 0); 139 | signal B4AdrD : std_logic_vector(7 downto 0); 140 | -- signal B4MaskD : std_logic_vector(7 downto 0); 141 | 142 | signal ConfFl : std_logic_vector(2 downto 0); 143 | 144 | signal DecMDR : std_logic; 145 | signal DirFlW : std_logic; 146 | signal MAddr : std_logic_vector(22 downto 0); 147 | signal MR1A : std_logic_vector(3 downto 0); 148 | signal MR2A : std_logic_vector(3 downto 0); 149 | signal MR3A : std_logic_vector(3 downto 0); 150 | signal MR4A : std_logic_vector(3 downto 0); 151 | begin 152 | 153 | ---------------------------------------------------------------- 154 | -- Dummy pin 155 | ---------------------------------------------------------------- 156 | pSltRsv5 <= '1'; 157 | pSltRsv16 <= '1'; 158 | 159 | pSltClk_n <= not pSltClk; 160 | 161 | pSltBdir_n <= '0' when pSltSltsl_n = '0' and pSltRd_n = '0' else '1'; 162 | 163 | pFlBYTE_n <= ConfFl(2); 164 | pFlRP_n <= ConfFl(1); 165 | pFlVpp <= ConfFl(0); 166 | 167 | 168 | 169 | ---------------------------------------------------------------- 170 | -- Slot access control 171 | ---------------------------------------------------------------- 172 | process(pSltClk_n, pSltRst_n, pSltIorq_n, pSltSltsl_n, pSltRd_n, pSltWr_n) 173 | 174 | variable DevAcs0 : std_logic; 175 | variable DevAcs1 : std_logic; 176 | 177 | begin 178 | 179 | if ((pSltIorq_n = '0' or pSltSltsl_n = '0') and (pSltRd_n = '0' or pSltWr_n = '0')) then 180 | DevAcs0 := '1'; 181 | else 182 | DevAcs0 := '0'; 183 | end if; 184 | 185 | if (DevAcs0 = '1' and DevAcs1 = '0') then 186 | DevHit <= '1'; 187 | else 188 | DevHit <= '0'; 189 | end if; 190 | 191 | if (pSltRst_n = '0') then 192 | DevAcs1 := '0'; 193 | elsif (pSltClk_n'event and pSltClk_n = '1') then 194 | DevAcs1 := DevAcs0; 195 | end if; 196 | 197 | end process; 198 | 199 | Dec1FFE <= '1' when pSltAdr(12 downto 1) = "111111111111" else '0'; 200 | DecSccA <= '1' when pSltAdr(15 downto 11) = "10011" and SccModeB(5) = '0' and SccBank2(5 downto 0) = "111111" 201 | else '0'; 202 | DecSccB <= '1' when pSltAdr(15 downto 11) = "10111" and SccModeB(5) = '1' and SccBank3(7) = '1' 203 | else '0'; 204 | DecMDR <= '1' when pSltSltsl_n = '0' and pSltAdr(13 downto 6) = "00111110" and 205 | CardMDR(7) = '0' and pSltAdr (15 downto 14) = CardMDR (6 downto 5) 206 | else '0'; 207 | 208 | ---------------------------------------------------------------- 209 | -- Conf register 210 | ---------------------------------------------------------------- 211 | process(pSltClk_n, pSltRst_n) 212 | 213 | begin 214 | 215 | if (pSltRst_n = '0') then 216 | CardMDR <= "01000000"; 217 | ConfFl <= "000"; 218 | AddrFR <= "0000000"; 219 | R1Mult <= "00000000"; 220 | R2Mult <= "00000000"; 221 | R3Mult <= "00000000"; 222 | R4Mult <= "00000000"; 223 | elsif (pSltClk_n'event and pSltClk_n = '1') then 224 | 225 | -- Mapped I/O port access on 8F80 ( 0F80, 4F80, CF80 ) Cart mode resister write 226 | if (DecMDR = '1' and pSltWr_n = '0' ) then 227 | if (pSltAdr(5 downto 0) = "000000") then CardMDR <= pSltDat ; end if; 228 | if (pSltAdr(5 downto 0) = "000001") then AddrM0 <= pSltDat ; end if; 229 | if (pSltAdr(5 downto 0) = "000010") then AddrM1 <= pSltDat ; end if; 230 | if (pSltAdr(5 downto 0) = "000011") then AddrM2 <= pSltDat(6 downto 0) ; end if; 231 | -- if (pSltAdr(5 downto 0) = "000100") then DatM0 <= pSltDat ; end if; -- transit 232 | if (pSltAdr(5 downto 0) = "000101") then AddrFR <= pSltDat(6 downto 0) ; end if; 233 | 234 | if (pSltAdr(5 downto 0) = "000101") then R1Mask <= pSltDat ; end if; 235 | if (pSltAdr(5 downto 0) = "000111") then R1Addr <= pSltDat ; end if; 236 | if (pSltAdr(5 downto 0) = "001000") then R1Reg <= pSltDat ; end if; 237 | if (pSltAdr(5 downto 0) = "001001") then R1Mult <= pSltDat ; end if; 238 | if (pSltAdr(5 downto 0) = "001010") then B1MaskR <= pSltDat ; end if; 239 | if (pSltAdr(5 downto 0) = "001011") then B1AdrD <= pSltDat ; end if; 240 | -- if (pSltAdr(5 downto 0) = "001100") then B1MaskD <= pSltDat ; end if; 241 | 242 | if (pSltAdr(5 downto 0) = "001101") then R2Mask <= pSltDat ; end if; 243 | if (pSltAdr(5 downto 0) = "001110") then R2Addr <= pSltDat ; end if; 244 | if (pSltAdr(5 downto 0) = "001111") then R2Reg <= pSltDat ; end if; 245 | if (pSltAdr(5 downto 0) = "010000") then R2Mult <= pSltDat ; end if; 246 | if (pSltAdr(5 downto 0) = "010001") then B2MaskR <= pSltDat ; end if; 247 | if (pSltAdr(5 downto 0) = "010010") then B2AdrD <= pSltDat ; end if; 248 | -- if (pSltAdr(5 downto 0) = "010011") then B2MaskD <= pSltDat ; end if; 249 | 250 | if (pSltAdr(5 downto 0) = "010100") then R3Mask <= pSltDat ; end if; 251 | if (pSltAdr(5 downto 0) = "010101") then R3Addr <= pSltDat ; end if; 252 | if (pSltAdr(5 downto 0) = "010110") then R3Reg <= pSltDat ; end if; 253 | if (pSltAdr(5 downto 0) = "010111") then R3Mult <= pSltDat ; end if; 254 | if (pSltAdr(5 downto 0) = "011000") then B3MaskR <= pSltDat ; end if; 255 | if (pSltAdr(5 downto 0) = "011001") then B3AdrD <= pSltDat ; end if; 256 | -- if (pSltAdr(5 downto 0) = "011010") then B3MaskD <= pSltDat ; end if; 257 | 258 | if (pSltAdr(5 downto 0) = "011011") then R4Mask <= pSltDat ; end if; 259 | if (pSltAdr(5 downto 0) = "011100") then R4Addr <= pSltDat ; end if; 260 | if (pSltAdr(5 downto 0) = "011101") then R4Reg <= pSltDat ; end if; 261 | if (pSltAdr(5 downto 0) = "011110") then R4Mult <= pSltDat ; end if; 262 | if (pSltAdr(5 downto 0) = "011111") then B4MaskR <= pSltDat ; end if; 263 | if (pSltAdr(5 downto 0) = "100000") then B4AdrD <= pSltDat ; end if; 264 | -- if (pSltAdr(5 downto 0) = "100001") then B4MaskD <= pSltDat ; end if; 265 | 266 | if (pSltAdr(5 downto 0) = "100010") then CardMDR <= pSltDat ; end if; 267 | 268 | if (pSltAdr(5 downto 0) = "100011") then ConfFl <= pSltDat(2 downto 0); end if; 269 | 270 | end if; 271 | 272 | -- Mapped I/O port access on R1 Bank resister write 273 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and R1Mult(7) = '1' 274 | and ( pSltAdr(15) = R1Addr(7) or R1Mask(7) = '0' ) 275 | and ( pSltAdr(14) = R1Addr(6) or R1Mask(6) = '0' ) 276 | and ( pSltAdr(13) = R1Addr(5) or R1Mask(5) = '0' ) 277 | and ( pSltAdr(12) = R1Addr(4) or R1Mask(4) = '0' ) 278 | and ( pSltAdr(11) = R1Addr(3) or R1Mask(3) = '0' ) 279 | and ( pSltAdr(10) = R1Addr(2) or R1Mask(2) = '0' ) 280 | and ( pSltAdr(9) = R1Addr(1) or R1Mask(1) = '0' ) 281 | and ( pSltAdr(8) = R1Addr(0) or R1Mask(0) = '0' ) 282 | ) 283 | then 284 | R1Reg <= pSltDat; 285 | end if; 286 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and R2Mult(7) = '1' 287 | and ( pSltAdr(15) = R2Addr(7) or R2Mask(7) = '0' ) 288 | and ( pSltAdr(14) = R2Addr(6) or R2Mask(6) = '0' ) 289 | and ( pSltAdr(13) = R2Addr(5) or R2Mask(5) = '0' ) 290 | and ( pSltAdr(12) = R2Addr(4) or R2Mask(4) = '0' ) 291 | and ( pSltAdr(11) = R2Addr(3) or R2Mask(3) = '0' ) 292 | and ( pSltAdr(10) = R2Addr(2) or R2Mask(2) = '0' ) 293 | and ( pSltAdr(9) = R2Addr(1) or R2Mask(1) = '0' ) 294 | and ( pSltAdr(8) = R2Addr(0) or R2Mask(0) = '0' ) 295 | ) 296 | then 297 | R2Reg <= pSltDat; 298 | end if; 299 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and R3Mult(7) = '1' 300 | and ( pSltAdr(15) = R3Addr(7) or R3Mask(7) = '0' ) 301 | and ( pSltAdr(14) = R3Addr(6) or R3Mask(6) = '0' ) 302 | and ( pSltAdr(13) = R3Addr(5) or R3Mask(5) = '0' ) 303 | and ( pSltAdr(12) = R3Addr(4) or R3Mask(4) = '0' ) 304 | and ( pSltAdr(11) = R3Addr(3) or R3Mask(3) = '0' ) 305 | and ( pSltAdr(10) = R3Addr(2) or R3Mask(2) = '0' ) 306 | and ( pSltAdr(9) = R3Addr(1) or R3Mask(1) = '0' ) 307 | and ( pSltAdr(8) = R3Addr(0) or R3Mask(0) = '0' ) 308 | ) 309 | then 310 | R3Reg <= pSltDat; 311 | end if; 312 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and R4Mult(7) = '1' 313 | and ( pSltAdr(15) = R4Addr(7) or R4Mask(7) = '0' ) 314 | and ( pSltAdr(14) = R4Addr(6) or R4Mask(6) = '0' ) 315 | and ( pSltAdr(13) = R4Addr(5) or R4Mask(5) = '0' ) 316 | and ( pSltAdr(12) = R4Addr(4) or R4Mask(4) = '0' ) 317 | and ( pSltAdr(11) = R4Addr(3) or R4Mask(3) = '0' ) 318 | and ( pSltAdr(10) = R4Addr(2) or R4Mask(2) = '0' ) 319 | and ( pSltAdr(9) = R4Addr(1) or R4Mask(1) = '0' ) 320 | and ( pSltAdr(8) = R4Addr(0) or R4Mask(0) = '0' ) 321 | ) 322 | then 323 | R4Reg <= pSltDat; 324 | end if; 325 | 326 | end if; 327 | 328 | end process; 329 | ---------------------------------------------------------------- 330 | -- Flash ROM interface 331 | ---------------------------------------------------------------- 332 | -- Flash DataWrite 333 | pFlDat <= pSltDat when pSltSltsl_n = '0' and pSltRd_n = '1' else 334 | (others => 'Z'); 335 | -- Flash -ChipSelect 336 | pFlCS_n <= '0' when DecMDR = '1' or (MR1A(3) = '0' and R1Mult(5) = '0') or (MR2A(3) = '0' and R2Mult(5) = '0') 337 | or (MR3A(3) = '0' and R3Mult(5) = '0') or (MR3A(3) = '0' and R3Mult(5) = '0') else 338 | '1'; 339 | -- Flash -OutputEnable (-Gate) 340 | pFlOE_n <= '0' when pSltRd_n = '0' and ((DecMDR = '1' and pSltAdr(5 downto 0) = "000100") -- DatM0 341 | or MR1A(3) = '0' -- Bank1 342 | or MR2A(3) = '0' -- Bank2 343 | or MR3A(3) = '0' -- Bank3 344 | or MR3A(3) = '0') else -- Bank4 345 | '1'; 346 | -- Flash -Write 347 | pFlW_n <= '0' when pSltWr_n = '0' and ((DecMDR = '1' and pSltAdr(5 downto 0) = "000100") -- DatM0 348 | or (MR1A(3) = '0' and R1Mult(4) = '1') -- Bank1 349 | or (MR2A(3) = '0' and R2Mult(4) = '1') -- Bank2 350 | or (MR3A(3) = '0' and R3Mult(4) = '1') -- Bank3 351 | or (MR3A(3) = '0' and R3Mult(4) = '1')) else -- Bank4 352 | '1'; 353 | 354 | pFlAdr(22 downto 0) <= AddrM2(6 downto 0) & AddrM1(7 downto 0) & AddrM0(7 downto 0) when DecMDR = '1' else 355 | (AddrFR(6 downto 0) + Maddr(22 downto 16)) & Maddr(15 downto 0); 356 | 357 | 358 | Maddr(8 downto 0) <=pSltAdr(8 downto 0); 359 | MR1A <= "0111" when R1Mult(2 downto 0) = "111" and R1Mult(7) = '1' else 360 | "0110" when R1Mult(2 downto 0) = "110" and R1Mult(7) = '1' and B1AdrD(7) = pSltAdr(15) else 361 | "0101" when R1Mult(2 downto 0) = "101" and R1Mult(7) = '1' and B1AdrD(7 downto 6) = pSltAdr(15 downto 14)else 362 | "0100" when R1Mult(2 downto 0) = "100" and R1Mult(7) = '1' and B1AdrD(7 downto 5) = pSltAdr(15 downto 13)else 363 | "0011" when R1Mult(2 downto 0) = "011" and R1Mult(7) = '1' and B1AdrD(7 downto 4) = pSltAdr(15 downto 12)else 364 | "0010" when R1Mult(2 downto 0) = "010" and R1Mult(7) = '1' and B1AdrD(7 downto 3) = pSltAdr(15 downto 11)else 365 | "0001" when R1Mult(2 downto 0) = "001" and R1Mult(7) = '1' and B1AdrD(7 downto 2) = pSltAdr(15 downto 10)else 366 | "0000" when R1Mult(2 downto 0) = "000" and R1Mult(7) = '1' and B1AdrD(7 downto 1) = pSltAdr(15 downto 9)else 367 | "1000" ; 368 | 369 | MR2A <= "0111" when R2Mult(2 downto 0) = "111" and R2Mult(7) = '1' else 370 | "0110" when R2Mult(2 downto 0) = "110" and R2Mult(7) = '1' and B2AdrD(7) = pSltAdr(15) else 371 | "0101" when R2Mult(2 downto 0) = "101" and R2Mult(7) = '1' and B2AdrD(7 downto 6) = pSltAdr(15 downto 14)else 372 | "0100" when R2Mult(2 downto 0) = "100" and R2Mult(7) = '1' and B2AdrD(7 downto 5) = pSltAdr(15 downto 13)else 373 | "0011" when R2Mult(2 downto 0) = "011" and R2Mult(7) = '1' and B2AdrD(7 downto 4) = pSltAdr(15 downto 12)else 374 | "0010" when R2Mult(2 downto 0) = "010" and R2Mult(7) = '1' and B2AdrD(7 downto 3) = pSltAdr(15 downto 11)else 375 | "0001" when R2Mult(2 downto 0) = "001" and R2Mult(7) = '1' and B2AdrD(7 downto 2) = pSltAdr(15 downto 10)else 376 | "0000" when R2Mult(2 downto 0) = "000" and R2Mult(7) = '1' and B2AdrD(7 downto 1) = pSltAdr(15 downto 9)else 377 | "1000" ; 378 | 379 | MR3A <= "0111" when R3Mult(2 downto 0) = "111" and R3Mult(7) = '1' else 380 | "0110" when R3Mult(2 downto 0) = "110" and R3Mult(7) = '1' and B3AdrD(0) = pSltAdr(15) else 381 | "0101" when R3Mult(2 downto 0) = "101" and R3Mult(7) = '1' and B3AdrD(7 downto 6) = pSltAdr(15 downto 14)else 382 | "0100" when R3Mult(2 downto 0) = "100" and R3Mult(7) = '1' and B3AdrD(7 downto 5) = pSltAdr(15 downto 13)else 383 | "0011" when R3Mult(2 downto 0) = "011" and R3Mult(7) = '1' and B3AdrD(7 downto 4) = pSltAdr(15 downto 12)else 384 | "0010" when R3Mult(2 downto 0) = "010" and R3Mult(7) = '1' and B3AdrD(7 downto 3) = pSltAdr(15 downto 11)else 385 | "0001" when R3Mult(2 downto 0) = "001" and R3Mult(7) = '1' and B3AdrD(7 downto 2) = pSltAdr(15 downto 10)else 386 | "0000" when R3Mult(2 downto 0) = "000" and R3Mult(7) = '1' and B3AdrD(7 downto 1) = pSltAdr(15 downto 9)else 387 | "1000" ; 388 | 389 | MR4A <= "0111" when R4Mult(2 downto 0) = "111" and R4Mult(7) = '1' else 390 | "0110" when R4Mult(2 downto 0) = "110" and R4Mult(7) = '1' and B4AdrD(7) = pSltAdr(15) else 391 | "0101" when R4Mult(2 downto 0) = "101" and R4Mult(7) = '1' and B4AdrD(7 downto 6) = pSltAdr(15 downto 14)else 392 | "0100" when R4Mult(2 downto 0) = "100" and R4Mult(7) = '1' and B4AdrD(7 downto 5) = pSltAdr(15 downto 13)else 393 | "0011" when R4Mult(2 downto 0) = "011" and R4Mult(7) = '1' and B4AdrD(7 downto 4) = pSltAdr(15 downto 12)else 394 | "0010" when R4Mult(2 downto 0) = "010" and R4Mult(7) = '1' and B4AdrD(7 downto 3) = pSltAdr(15 downto 11)else 395 | "0001" when R4Mult(2 downto 0) = "001" and R4Mult(7) = '1' and B4AdrD(7 downto 2) = pSltAdr(15 downto 10)else 396 | "0000" when R4Mult(2 downto 0) = "000" and R4Mult(7) = '1' and B4AdrD(7 downto 1) = pSltAdr(15 downto 9)else 397 | "1000" ; 398 | 399 | Maddr(22 downto 9) <= (B1MaskR(6 downto 0) and R1Reg(6 downto 0)) & pSltAdr(15 downto 9) when MR1A = "0111" else 400 | (B1MaskR and R1Reg) & pSltAdr(14 downto 9) when MR1A = "0110" else 401 | "0" & (B1MaskR and R1Reg) & pSltAdr(13 downto 9) when MR1A = "0101" else 402 | "00" & (B1MaskR and R1Reg) & pSltAdr(12 downto 9) when MR1A = "0100" else 403 | "000" & (B1MaskR and R1Reg) & pSltAdr(11 downto 9) when MR1A = "0011" else 404 | "0000" & (B1MaskR and R1Reg) & pSltAdr(10 downto 9) when MR1A = "0010" else 405 | "00000" & (B1MaskR and R1Reg) & pSltAdr(9) when MR1A = "0001" else 406 | "000000" & (B1MaskR and R1Reg) when MR1A = "0000" else 407 | 408 | (B2MaskR(6 downto 0) and R2Reg(6 downto 0)) & pSltAdr(15 downto 9) when MR2A = "0111" else 409 | (B2MaskR and R2Reg) & pSltAdr(14 downto 9) when MR2A = "0110" else 410 | "0" & (B2MaskR and R2Reg) & pSltAdr(13 downto 9) when MR2A = "0101" else 411 | "00" & (B2MaskR and R2Reg) & pSltAdr(12 downto 9) when MR2A = "0100" else 412 | "000" & (B2MaskR and R2Reg) & pSltAdr(11 downto 9) when MR2A = "0011" else 413 | "0000" & (B2MaskR and R2Reg) & pSltAdr(10 downto 9) when MR2A = "0010" else 414 | "00000" & (B2MaskR and R2Reg) & pSltAdr(9) when MR2A = "0001" else 415 | "000000" & (B2MaskR and R2Reg) when MR2A = "0000" else 416 | 417 | (B3MaskR(6 downto 0) and R3Reg(6 downto 0)) & pSltAdr(15 downto 9) when MR1A = "0111" else 418 | (B3MaskR and R3Reg) & pSltAdr(14 downto 9) when MR3A = "0110" else 419 | "0" & (B3MaskR and R3Reg) & pSltAdr(13 downto 9) when MR3A = "0101" else 420 | "00" & (B3MaskR and R3Reg) & pSltAdr(12 downto 9) when MR3A = "0100" else 421 | "000" & (B3MaskR and R3Reg) & pSltAdr(11 downto 9) when MR3A = "0011" else 422 | "0000" & (B3MaskR and R3Reg) & pSltAdr(10 downto 9) when MR3A = "0010" else 423 | "00000" & (B3MaskR and R3Reg) & pSltAdr(9) when MR3A = "0001" else 424 | "000000" & (B3MaskR and R3Reg) when MR3A = "0000" else 425 | 426 | (B4MaskR(6 downto 0) and R4Reg(6 downto 0)) & pSltAdr(15 downto 9) when MR4A = "0111" else 427 | (B4MaskR and R4Reg) & pSltAdr(14 downto 9) when MR4A = "0110" else 428 | "0" & (B4MaskR and R4Reg) & pSltAdr(13 downto 9) when MR4A = "0101" else 429 | "00" & (B4MaskR and R4Reg) & pSltAdr(12 downto 9) when MR4A = "0100" else 430 | "000" & (B4MaskR and R4Reg) & pSltAdr(11 downto 9) when MR4A = "0011" else 431 | "0000" & (B4MaskR and R4Reg) & pSltAdr(10 downto 9) when MR4A = "0010" else 432 | "00000" & (B4MaskR and R4Reg) & pSltAdr(9) when MR4A = "0001" else 433 | "000000" & (B4MaskR and R4Reg) when MR4A = "0000" ; 434 | 435 | 436 | 437 | -- if(R1Mult(2 downto 0) = "111") then Maddr(22 downto 8) <= (B1MaskR(6 downto 0) and R1Reg(6 downto 0)) & pSltAdr(15 downto 8); 438 | -- elsif (R1Mult(2 downto 0) = "110" and B1AdrD(0) = pSltAdr(15)) then Maddr(22 downto 8) <= (B1MaskR and R1Reg) & pSltAdr(14 downto 8); 439 | -- elsif (R1Mult(2 downto 0) = "101" and B1AdrD(1 downto 0) = pSltAdr(15 downto 14)) then Maddr(22 downto 8) <= "0" & (B1MaskR and R1Reg) & pSltAdr(13 downto 8); 440 | -- end if; 441 | 442 | ---------------------------------------------------------------- 443 | -- SCC register / wave memory access 444 | ---------------------------------------------------------------- 445 | process(pSltClk_n, pSltRst_n) 446 | 447 | begin 448 | 449 | if (pSltRst_n = '0') then 450 | 451 | SccBank0 <= "00000000"; 452 | SccBank1 <= "00000001"; 453 | SccBank2 <= "00000010"; 454 | SccBank3 <= "00000011"; 455 | SccModeA <= (others => '0'); 456 | SccModeB <= (others => '0'); 457 | 458 | SccWavWx <= '0'; 459 | SccWavAdr <= (others => '0'); 460 | SccWavDat <= (others => '0'); 461 | 462 | elsif (pSltClk_n'event and pSltClk_n = '1') then 463 | 464 | -- Mapped I/O port access on 5000-57FFh ... Bank resister write 465 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and pSltAdr(15 downto 11) = "01010" and 466 | SccModeA(6) = '0' and SccModeA(4) = '0' and SccModeB(4) = '0') then 467 | SccBank0 <= pSltDat; 468 | end if; 469 | -- Mapped I/O port access on 7000-77FFh ... Bank resister write 470 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and pSltAdr(15 downto 11) = "01110" and 471 | SccModeA(6) = '0' and SccModeA(4) = '0' and SccModeB(4) = '0') then 472 | SccBank1 <= pSltDat; 473 | end if; 474 | -- Mapped I/O port access on 9000-97FFh ... Bank resister write 475 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and pSltAdr(15 downto 11) = "10010" and 476 | SccModeB(4) = '0') then 477 | SccBank2 <= pSltDat; 478 | end if; 479 | -- Mapped I/O port access on B000-B7FFh ... Bank resister write 480 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and pSltAdr(15 downto 11) = "10110" and 481 | SccModeA(6) = '0' and SccModeA(4) = '0' and SccModeB(4) = '0') then 482 | SccBank3 <= pSltDat; 483 | end if; 484 | 485 | -- Mapped I/O port access on 7FFE-7FFFh ... Resister write 486 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and pSltAdr(15 downto 13) = "011" and Dec1FFE = '1' and 487 | SccModeB(5 downto 4) = "00") then 488 | SccModeA <= pSltDat; 489 | end if; 490 | 491 | -- Mapped I/O port access on BFFE-BFFFh ... Resister write 492 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and pSltAdr(15 downto 13) = "101" and Dec1FFE = '1' and 493 | SccModeA(6) = '0' and SccModeA(4) = '0') then 494 | SccModeB <= pSltDat; 495 | end if; 496 | 497 | -- Mapped I/O port access on 9860-987Fh ... Wave memory copy 498 | if (pSltSltsl_n = '0' and pSltWr_n = '0' and pSltAdr(7 downto 5) = "011" and 499 | DevHit = '1' and SccModeB(4) = '0' and DecSccA = '1') then 500 | SccWavAdr <= pSltAdr(4 downto 0); 501 | SccWavDat <= pSltDat; 502 | SccWavWx <= '1'; 503 | else 504 | SccWavWx <= '0'; 505 | end if; 506 | 507 | end if; 508 | 509 | end process; 510 | 511 | -- Mapped I/O port access on 9800-987Fh / B800-B89Fh ... Wave memory 512 | SccWavCe <= '1' when pSltSltsl_n = '0' and DevHit = '1' and SccModeB(4) = '0' and 513 | (DecSccA = '1' or DecSccB = '1') 514 | else '0'; 515 | 516 | -- Mapped I/O port access on 9800-987Fh / B800-B89Fh ... Wave memory 517 | SccWavOe <= '1' when pSltSltsl_n = '0' and pSltRd_n = '0' and SccModeB(4) = '0' and 518 | ((DecSccA = '1' and pSltAdr(7) = '0') or 519 | (DecSccB = '1' and (pSltAdr(7) = '0' or pSltAdr(6 downto 5) = "00"))) 520 | else '0'; 521 | 522 | -- Mapped I/O port access on 9800-987Fh / B800-B89Fh ... Wave memory 523 | SccWavWe <= '1' when pSltSltsl_n = '0' and pSltWr_n = '0' and DevHit = '1' and SccModeB(4) = '0' and 524 | ((DecSccA = '1' and pSltAdr(7) = '0') or DecSccB = '1') 525 | else '0'; 526 | 527 | -- Mapped I/O port access on 9880-988Fh / B8A0-B8AF ... Resister write 528 | SccRegWe <= '1' when pSltSltsl_n = '0' and pSltWr_n = '0' and 529 | ((DecSccA = '1' and pSltAdr(7 downto 5) = "100") or 530 | (DecSccB = '1' and pSltAdr(7 downto 5) = "101")) and 531 | DevHit = '1' and SccModeB(4) = '0' 532 | else '0'; 533 | 534 | -- Mapped I/O port access on 98C0-98FFh / B8C0-B8DFh ... Resister write 535 | SccModWe <= '1' when pSltSltsl_n = '0' and pSltWr_n = '0' and pSltAdr(7 downto 6) = "11" and 536 | (DecSccA = '1' or (pSltAdr(5) = '0' and DecSccB = '1')) and 537 | DevHit = '1' and SccModeB(4) = '0' 538 | else '0'; 539 | 540 | ---------------------------------------------------------------- 541 | -- Connect components 542 | ---------------------------------------------------------------- 543 | 544 | SccCh : scc_wave 545 | port map( 546 | pSltClk_n, pSltRst_n, pSltAdr(7 downto 0), pSltDat, SccAmp, 547 | SccRegWe, SccModWe, SccWavCe, SccWavOe, SccWavWe, SccWavWx, SccWavAdr, SccWavDat 548 | ); 549 | 550 | ---------------------------------------------------------------- 551 | -- 1 bit D/A control 552 | ---------------------------------------------------------------- 553 | process(pSltClk_n, pSltRst_n) 554 | 555 | variable Amp : std_logic_vector(7 downto 0); 556 | variable Acu : std_logic_vector(8 downto 0); 557 | 558 | begin 559 | 560 | if (pSltRst_n = '0') then 561 | 562 | Amp := (others => '0'); 563 | Acu := (others => '0'); 564 | pSltSndL <= '0'; 565 | pSltSndR <= '0'; 566 | pSltSound <= '0'; 567 | 568 | elsif (pSltClk_n'event and pSltClk_n = '1') then 569 | 570 | Amp := SccAmp and "11111110"; 571 | Acu := ('0' & Acu(7 downto 0)) + ('0' & Amp); 572 | pSltSndL <= Acu(8); 573 | pSltSndR <= Acu(8); 574 | pSltSound <= Acu(8); 575 | 576 | end if; 577 | end process; 578 | 579 | 580 | end RTL; 581 | -------------------------------------------------------------------------------- /Firmware/Sources/cscc.pin: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 1991-2009 Altera Corporation 2 | -- Your use of Altera Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Altera Program License 8 | -- Subscription Agreement, Altera MegaCore Function License 9 | -- Agreement, or other applicable license agreement, including, 10 | -- without limitation, that your use is for the sole purpose of 11 | -- programming logic devices manufactured by Altera and sold by 12 | -- Altera or its authorized distributors. Please refer to the 13 | -- applicable agreement for further details. 14 | -- 15 | -- This is a Quartus II output file. It is for reporting purposes only, and is 16 | -- not intended for use as a Quartus II input file. This file cannot be used 17 | -- to make Quartus II pin assignments - for instructions on how to make pin 18 | -- assignments, please see Quartus II help. 19 | ------------------------------------------------------------------------------ 20 | 21 | 22 | 23 | ------------------------------------------------------------------------------ 24 | -- NC : No Connect. This pin has no internal connection to the device. 25 | -- VCC_INT : Dedicated power pin, which MUST be connected to VCC (3.3V). 26 | -- VCC_IO : Dedicated power pin, which MUST be connected to VCC (Refer to 27 | -- the table below for voltage). 28 | -- GND : Dedicated ground pin, which MUST be connected to GND. 29 | -- GND+ : Unused input. This pin should be connected to GND. It may also 30 | -- be connected to a valid signal on the board (low, high, or 31 | -- toggling) if that signal is required for a different revision 32 | -- of the design. 33 | -- GND* : Unused I/O pin. This pin can either be left unconnected or 34 | -- connected to GND. Connecting this pin to GND will improve the 35 | -- device's immunity to noise. 36 | ------------------------------------------------------------------------------ 37 | 38 | 39 | File Generation Date & Time: Wed Mar 02 18:58:02 2016 40 | Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version 41 | CHIP "cscc" ASSIGNED TO AN: EPF10K100ARI240-3 42 | 43 | Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment 44 | ------------------------------------------------------------------------------------------------------------- 45 | TCK : 1 : input : : : : 46 | CONF_DONE : 2 : bidir : : : : 47 | nCEO : 3 : output : : : : 48 | TDO : 4 : output : : : : 49 | VCC_INT : 5 : power : : 3.3V : : 50 | pFlAdr[10] : 6 : output : LVTTL/LVCMOS : : : Y 51 | pFlAdr[9] : 7 : output : LVTTL/LVCMOS : : : Y 52 | pFlAdr[20] : 8 : output : LVTTL/LVCMOS : : : Y 53 | pFlAdr[21] : 9 : output : LVTTL/LVCMOS : : : Y 54 | GND_INT : 10 : gnd : : : : 55 | GND* : 11 : : : : : 56 | pFlW_n : 12 : output : LVTTL/LVCMOS : : : Y 57 | pFlRP_n : 13 : output : LVTTL/LVCMOS : : : Y 58 | pFlAdr[22] : 14 : output : LVTTL/LVCMOS : : : Y 59 | pFlRB_b : 15 : input : LVTTL/LVCMOS : : : Y 60 | VCC_INT : 16 : power : : 3.3V : : 61 | pFlAdr[19] : 17 : output : LVTTL/LVCMOS : : : Y 62 | pFlAdr[18] : 18 : output : LVTTL/LVCMOS : : : Y 63 | pFlAdr[8] : 19 : output : LVTTL/LVCMOS : : : Y 64 | pFlAdr[7] : 20 : output : LVTTL/LVCMOS : : : Y 65 | pFlAdr[6] : 21 : output : LVTTL/LVCMOS : : : Y 66 | GND_INT : 22 : gnd : : : : 67 | GND* : 23 : : : : : 68 | pFlAdr[5] : 24 : output : LVTTL/LVCMOS : : : Y 69 | pFlAdr[4] : 25 : output : LVTTL/LVCMOS : : : Y 70 | GND* : 26 : : : : : 71 | VCC_INT : 27 : power : : 3.3V : : 72 | pFlAdr[3] : 28 : output : LVTTL/LVCMOS : : : Y 73 | pFlAdr[2] : 29 : output : LVTTL/LVCMOS : : : Y 74 | pFlAdr[17] : 30 : output : LVTTL/LVCMOS : : : Y 75 | pFlBYTE_n : 31 : output : LVTTL/LVCMOS : : : Y 76 | GND_INT : 32 : gnd : : : : 77 | pFlAdr[0] : 33 : output : LVTTL/LVCMOS : : : Y 78 | pFlDat[7] : 34 : bidir : LVTTL/LVCMOS : : : Y 79 | pFlDatH[6] : 35 : input : LVTTL/LVCMOS : : : Y 80 | pFlDat[6] : 36 : bidir : LVTTL/LVCMOS : : : Y 81 | VCC_INT : 37 : power : : 3.3V : : 82 | pFlDatH[5] : 38 : input : LVTTL/LVCMOS : : : Y 83 | pFlDat[5] : 39 : bidir : LVTTL/LVCMOS : : : Y 84 | pFlDatH[4] : 40 : input : LVTTL/LVCMOS : : : Y 85 | pFlDat[4] : 41 : bidir : LVTTL/LVCMOS : : : Y 86 | GND_INT : 42 : gnd : : : : 87 | pFlDatH[3] : 43 : input : LVTTL/LVCMOS : : : Y 88 | pFlDat[3] : 44 : bidir : LVTTL/LVCMOS : : : Y 89 | pFlDatH[2] : 45 : input : LVTTL/LVCMOS : : : Y 90 | pFlDat[2] : 46 : bidir : LVTTL/LVCMOS : : : Y 91 | VCC_INT : 47 : power : : 3.3V : : 92 | pFlDatH[1] : 48 : input : LVTTL/LVCMOS : : : Y 93 | pFlDat[1] : 49 : bidir : LVTTL/LVCMOS : : : Y 94 | pFlDatH[0] : 50 : input : LVTTL/LVCMOS : : : Y 95 | pFlDat[0] : 51 : bidir : LVTTL/LVCMOS : : : Y 96 | GND_INT : 52 : gnd : : : : 97 | pFlOE_n : 53 : output : LVTTL/LVCMOS : : : Y 98 | pFlCS_n : 54 : output : LVTTL/LVCMOS : : : Y 99 | pFlAdr[1] : 55 : output : LVTTL/LVCMOS : : : Y 100 | pFlVpp : 56 : output : LVTTL/LVCMOS : : : Y 101 | VCC_INT : 57 : power : : 3.3V : : 102 | TMS : 58 : input : : : : 103 | TRST : 59 : input : : : : 104 | nSTATUS : 60 : bidir : : : : 105 | iFsts : 61 : bidir : LVTTL/LVCMOS : : : Y 106 | GND* : 62 : : : : : 107 | GND* : 63 : : : : : 108 | GND* : 64 : : : : : 109 | GND* : 65 : : : : : 110 | GND* : 66 : : : : : 111 | GND* : 67 : : : : : 112 | GND* : 68 : : : : : 113 | GND_INT : 69 : gnd : : : : 114 | pSltDat[7] : 70 : bidir : LVTTL/LVCMOS : : : Y 115 | pSltDat[6] : 71 : bidir : LVTTL/LVCMOS : : : Y 116 | pSltDat[5] : 72 : bidir : LVTTL/LVCMOS : : : Y 117 | GND* : 73 : : : : : 118 | pSltDat[4] : 74 : bidir : LVTTL/LVCMOS : : : Y 119 | pSltDat[3] : 75 : bidir : LVTTL/LVCMOS : : : Y 120 | pSltDat[2] : 76 : bidir : LVTTL/LVCMOS : : : Y 121 | VCC_INT : 77 : power : : 3.3V : : 122 | pSltDat[1] : 78 : bidir : LVTTL/LVCMOS : : : Y 123 | pSltDat[0] : 79 : bidir : LVTTL/LVCMOS : : : Y 124 | pSltAdr[5] : 80 : input : LVTTL/LVCMOS : : : Y 125 | pSltAdr[4] : 81 : input : LVTTL/LVCMOS : : : Y 126 | pSltAdr[3] : 82 : input : LVTTL/LVCMOS : : : Y 127 | pSltAdr[2] : 83 : input : LVTTL/LVCMOS : : : Y 128 | pSltAdr[1] : 84 : input : LVTTL/LVCMOS : : : Y 129 | GND_INT : 85 : gnd : : : : 130 | pSltAdr[0] : 86 : input : LVTTL/LVCMOS : : : Y 131 | pSltAdr[14] : 87 : input : LVTTL/LVCMOS : : : Y 132 | pSltAdr[13] : 88 : input : LVTTL/LVCMOS : : : Y 133 | VCC_INT : 89 : power : : 3.3V : : 134 | GND+ : 90 : : : : : 135 | pSltClk : 91 : input : LVTTL/LVCMOS : : : Y 136 | GND+ : 92 : : : : : 137 | GND_INT : 93 : gnd : : : : 138 | pSltAdr[12] : 94 : input : LVTTL/LVCMOS : : : Y 139 | pSltAdr[8] : 95 : input : LVTTL/LVCMOS : : : Y 140 | VCC_INT : 96 : power : : 3.3V : : 141 | pSltAdr[7] : 97 : input : LVTTL/LVCMOS : : : Y 142 | pSltAdr[6] : 98 : input : LVTTL/LVCMOS : : : Y 143 | pSltAdr[11] : 99 : input : LVTTL/LVCMOS : : : Y 144 | pSltAdr[10] : 100 : input : LVTTL/LVCMOS : : : Y 145 | pSltAdr[9] : 101 : input : LVTTL/LVCMOS : : : Y 146 | pSltAdr[15] : 102 : input : LVTTL/LVCMOS : : : Y 147 | pSltRst_n : 103 : input : LVTTL/LVCMOS : : : Y 148 | GND_INT : 104 : gnd : : : : 149 | pSltRsv16 : 105 : output : LVTTL/LVCMOS : : : Y 150 | pSltWr_n : 106 : input : LVTTL/LVCMOS : : : Y 151 | pSltRd_n : 107 : input : LVTTL/LVCMOS : : : Y 152 | pSltIorq_n : 108 : input : LVTTL/LVCMOS : : : Y 153 | pSltMerq_n : 109 : input : LVTTL/LVCMOS : : : Y 154 | pSltM1_n : 110 : input : LVTTL/LVCMOS : : : Y 155 | pSltBdir_n : 111 : output : LVTTL/LVCMOS : : : Y 156 | VCC_INT : 112 : power : : 3.3V : : 157 | pSltWait_n : 113 : input : LVTTL/LVCMOS : : : Y 158 | pSltInt_n : 114 : input : LVTTL/LVCMOS : : : Y 159 | pSltRsv5 : 115 : output : LVTTL/LVCMOS : : : Y 160 | pSltRfsh_n : 116 : input : LVTTL/LVCMOS : : : Y 161 | pSltCs12 : 117 : input : LVTTL/LVCMOS : : : Y 162 | pSltSltsl_n : 118 : input : LVTTL/LVCMOS : : : Y 163 | pSltCs1 : 119 : input : LVTTL/LVCMOS : : : Y 164 | pSltCs2 : 120 : input : LVTTL/LVCMOS : : : Y 165 | nCONFIG : 121 : input : : : : 166 | VCC_INT : 122 : power : : 3.3V : : 167 | MSEL1 : 123 : input : : : : 168 | MSEL0 : 124 : input : : : : 169 | GND_INT : 125 : gnd : : : : 170 | GND* : 126 : : : : : 171 | GND* : 127 : : : : : 172 | GND* : 128 : : : : : 173 | GND* : 129 : : : : : 174 | VCC_INT : 130 : power : : 3.3V : : 175 | GND* : 131 : : : : : 176 | GND* : 132 : : : : : 177 | GND* : 133 : : : : : 178 | GND* : 134 : : : : : 179 | GND_INT : 135 : gnd : : : : 180 | GND* : 136 : : : : : 181 | GND* : 137 : : : : : 182 | GND* : 138 : : : : : 183 | GND* : 139 : : : : : 184 | VCC_INT : 140 : power : : 3.3V : : 185 | GND* : 141 : : : : : 186 | GND* : 142 : : : : : 187 | GND* : 143 : : : : : 188 | GND* : 144 : : : : : 189 | GND_INT : 145 : gnd : : : : 190 | GND* : 146 : : : : : 191 | GND* : 147 : : : : : 192 | GND* : 148 : : : : : 193 | GND* : 149 : : : : : 194 | VCC_INT : 150 : power : : 3.3V : : 195 | GND* : 151 : : : : : 196 | GND* : 152 : : : : : 197 | GND* : 153 : : : : : 198 | GND* : 154 : : : : : 199 | GND_INT : 155 : gnd : : : : 200 | GND* : 156 : : : : : 201 | GND* : 157 : : : : : 202 | GND* : 158 : : : : : 203 | GND* : 159 : : : : : 204 | VCC_INT : 160 : power : : 3.3V : : 205 | GND* : 161 : : : : : 206 | GND* : 162 : : : : : 207 | GND* : 163 : : : : : 208 | GND* : 164 : : : : : 209 | GND_INT : 165 : gnd : : : : 210 | GND* : 166 : : : : : 211 | GND* : 167 : : : : : 212 | GND* : 168 : : : : : 213 | GND* : 169 : : : : : 214 | VCC_INT : 170 : power : : 3.3V : : 215 | GND* : 171 : : : : : 216 | GND* : 172 : : : : : 217 | GND* : 173 : : : : : 218 | GND* : 174 : : : : : 219 | GND* : 175 : : : : : 220 | GND_INT : 176 : gnd : : : : 221 | TDI : 177 : input : : : : 222 | nCE : 178 : input : : : : 223 | DCLK : 179 : bidir : : : : 224 | DATA0 : 180 : input : : : : 225 | GND* : 181 : : : : : 226 | GND* : 182 : : : : : 227 | GND* : 183 : : : : : 228 | GND* : 184 : : : : : 229 | GND* : 185 : : : : : 230 | GND* : 186 : : : : : 231 | GND* : 187 : : : : : 232 | GND* : 188 : : : : : 233 | VCC_INT : 189 : power : : 3.3V : : 234 | GND* : 190 : : : : : 235 | GND* : 191 : : : : : 236 | GND* : 192 : : : : : 237 | GND* : 193 : : : : : 238 | GND* : 194 : : : : : 239 | GND* : 195 : : : : : 240 | GND* : 196 : : : : : 241 | GND_INT : 197 : gnd : : : : 242 | GND* : 198 : : : : : 243 | GND* : 199 : : : : : 244 | GND* : 200 : : : : : 245 | GND* : 201 : : : : : 246 | GND* : 202 : : : : : 247 | GND* : 203 : : : : : 248 | GND* : 204 : : : : : 249 | VCC_INT : 205 : power : : 3.3V : : 250 | GND* : 206 : : : : : 251 | GND* : 207 : : : : : 252 | GND* : 208 : : : : : 253 | GND* : 209 : : : : : 254 | GND+ : 210 : : : : : 255 | pSltClk2 : 211 : input : LVTTL/LVCMOS : : : Y 256 | GND+ : 212 : : : : : 257 | GND* : 213 : : : : : 258 | GND* : 214 : : : : : 259 | GND* : 215 : : : : : 260 | GND_INT : 216 : gnd : : : : 261 | GND* : 217 : : : : : 262 | GND* : 218 : : : : : 263 | GND* : 219 : : : : : 264 | GND* : 220 : : : : : 265 | GND* : 221 : : : : : 266 | GND* : 222 : : : : : 267 | GND* : 223 : : : : : 268 | VCC_INT : 224 : power : : 3.3V : : 269 | GND* : 225 : : : : : 270 | pSltSndR : 226 : output : LVTTL/LVCMOS : : : Y 271 | pSltSndL : 227 : output : LVTTL/LVCMOS : : : Y 272 | pSltSound : 228 : output : LVTTL/LVCMOS : : : Y 273 | GND* : 229 : : : : : 274 | pFlAdr[16] : 230 : output : LVTTL/LVCMOS : : : Y 275 | pFlAdr[15] : 231 : output : LVTTL/LVCMOS : : : Y 276 | GND_INT : 232 : gnd : : : : 277 | pFlAdr[14] : 233 : output : LVTTL/LVCMOS : : : Y 278 | pFlAdr[13] : 234 : output : LVTTL/LVCMOS : : : Y 279 | pFlAdr[12] : 235 : output : LVTTL/LVCMOS : : : Y 280 | GND* : 236 : : : : : 281 | pFlAdr[11] : 237 : output : LVTTL/LVCMOS : : : Y 282 | GND* : 238 : : : : : 283 | GND* : 239 : : : : : 284 | GND* : 240 : : : : : 285 | --------------------------------------------------------------------------------