├── IP ├── BTB_mem.xcix ├── PHT_mem.xcix ├── README.md ├── XADC_INST.xcix ├── blk_mem_gen_v7_3.xcix ├── blk_mem_gen_v7_3_2.xcix ├── clk_wiz_0.xcix ├── dcache.xcix ├── mainMem.xcix ├── tag_ram.xcix ├── xbip_dsp48_macro_0.xcix ├── xbip_dsp48_macro_1.xcix └── xbip_dsp48_macro_2.xcix ├── LICENSE ├── README.md ├── benchmarks ├── README.md └── matmultiplication │ ├── Makefile │ ├── Makefile.inc │ ├── Outputfiles │ └── xmem.coe │ ├── Scripts │ ├── __pycache__ │ │ └── config.cpython-38.pyc │ ├── base.hex │ ├── config.py │ ├── config.pyc │ ├── hex.py │ ├── run.sh │ ├── temp.hex │ ├── temphex │ └── xmem.coe │ ├── app │ └── c │ │ ├── a_mat.c │ │ ├── b_mat.c │ │ └── expected_output.c │ ├── arch │ ├── boot.S │ ├── configstring.h │ ├── interrupt.S │ └── riscv.ld │ ├── drivers │ ├── uart_lib.c │ └── uart_lib.h │ ├── include │ └── header.h │ ├── main.c │ ├── riscv-spike.asm │ ├── riscv-spike.dump │ ├── riscv-spike.elf │ ├── temp.hex │ └── temphex ├── constraints └── constraints.xdc ├── rtl ├── BPU │ ├── BTB_PLRU.v │ ├── Branch_Prediction_Unit.v │ ├── Branch_Target_Buff.v │ ├── Direction_Predictor.v │ └── Return_Addr_Stack.v ├── CPU │ ├── DECODE.v │ ├── EXECUTE.v │ ├── IF_ID_EX.v │ ├── INST_FETCH.v │ └── REG_FILE.v ├── EVA │ ├── EVA_ArgSort.v │ ├── EVA_update.v │ ├── access_ctr.v │ ├── addr_cal.v │ ├── age_set_ctr.v │ ├── block.v │ ├── class_bit.v │ ├── ctr_update.v │ ├── div_18.v │ ├── div_4_14.v │ ├── div_5_15.v │ ├── eviction_ctr.v │ ├── hit_ctr.v │ ├── replacement_algo.v │ └── seq.v ├── FPGA_WRAPPER.v ├── FPU │ ├── FP_DECODE.v │ ├── FP_EXECUTE.v │ ├── FP_REG_FILE.v │ └── fpu │ │ ├── ADD.v │ │ ├── COMPARE_1.v │ │ ├── CONVERT.v │ │ ├── Compare.v │ │ ├── DIV.v │ │ ├── FPU.v │ │ ├── FP_to_FP.v │ │ ├── FP_to_int.v │ │ ├── IEEE_to_flopoco_DP.vhdl │ │ ├── IEEE_to_flopoco_SP.vhdl │ │ ├── LZC.v │ │ ├── MULT.v │ │ ├── Rounding_Mode.v │ │ ├── SIGN_INJECTION.v │ │ ├── SQRT.v │ │ ├── TRANSFER.v │ │ ├── add_DP.vhdl │ │ ├── add_SP.vhd │ │ ├── div_DP.vhdl │ │ ├── div_SP.vhdl │ │ ├── flopoco_to_IEEE_DP.vhdl │ │ ├── flopoco_to_IEEE_SP.vhdl │ │ ├── int_to_FP.v │ │ ├── mul_DP.vhdl │ │ ├── mul_SP.vhdl │ │ ├── sqrt_DP.vhdl │ │ └── sqrt_SP.vhdl ├── ITLB │ ├── icam.v │ ├── ilru.v │ └── itlb.v ├── PWM.v ├── README.md ├── SW_LED.v ├── Sys_counter.v ├── cachefsm.v ├── cpu.v ├── csr.v ├── dcache_biu.v ├── dcache_dpram.v ├── dcache_ram_fsm.v ├── dcache_top.v ├── debouce.v ├── defines.v ├── ext_emulator.v ├── fet_dec_ex_mem.v ├── icache.v ├── icache_itlb │ ├── cachefsm.v │ ├── icache.v │ ├── mem_hier.v │ └── wishbone.v ├── intercon.v ├── interrupt_main.v ├── irq_interface.v ├── lcd.v ├── mem_hier.v ├── or1200_amultp2_32x32.v ├── or1200_fpu_div.v ├── or1200_wb_biu.v ├── raminfr.v ├── timescale.v ├── tlb │ ├── cam.v │ ├── lru.v │ └── tlb.v ├── uart_debug_if.v ├── uart_defines.v ├── uart_receiver.v ├── uart_regs.v ├── uart_rfifo.v ├── uart_sync_flops.v ├── uart_tfifo.v ├── uart_top.v └── uart_transmitter.v └── testbench ├── FPGA_WRAPPER_TEST.v └── README.md /IP/BTB_mem.xcix: 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