├── AUTHORS.md ├── LICENSE ├── README.md ├── bin └── README.md ├── dev └── custom_pdk_builds.md ├── dfm └── README.md ├── docs ├── masks.md └── userguide │ ├── 1-schematic capture.md │ ├── 2-pre-layout simulation.md │ ├── 3-layout creation.md │ ├── 4-physical verification.md │ ├── 5-post-layout simulation.md │ ├── 6-dfm-verification.md │ └── README.md ├── dtco └── README.md ├── libraries ├── README.md ├── cmp │ └── README.md ├── drc │ ├── README.md │ └── magic │ │ └── README.md ├── lfd │ └── README.md ├── lvs │ ├── README.md │ └── netgen │ │ └── README.md ├── models │ ├── commonspice │ │ └── README.md │ └── ngspice │ │ ├── design.ngspice │ │ └── typical.ngspice ├── symbols │ ├── README.md │ └── xschem │ │ ├── nfet.sym │ │ └── pfet.sym └── tech │ ├── klayout │ ├── openrpdk28,map │ ├── openrpdk28.lyp │ └── openrpdk28.lyt │ └── magic │ └── README.md ├── multiphysics └── README.md ├── openlane └── README.md ├── ref └── README.md ├── scripts └── README.md └── tcaddata └── README.md /AUTHORS.md: -------------------------------------------------------------------------------- 1 | This is the list of OpenRPDK28's significant contributors. 2 | # Anouncement 3 | This does not necessarily list everyone who has contributed code, especially since many employees of one corporation may be contributing. 4 | 5 | To see the full list of contributors, see the revision history insource control. 6 | 7 | # Affiliations 8 | RISC-V International Open Source Library 9 | 10 | TensorChip Technolgy Co.,Ltd 11 | 12 | # Individuals 13 | Chen Wei 14 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 RISC-V International Open Source Laboratory (RIOS Lab) 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ![rios-ip](https://github.com/riosmpw/OpenXPDK28/assets/100336131/9f3d5cb0-e9f8-48c8-b4e6-38c896d54da8) 2 | 3 | # OpenRPDK28 4 | **Process Design Kit** (**PDK**) is a set of files or models used within the semiconductor industry to model a fabrication process characteristic for the design tools and its users used to design an integrated circuit. An accurate PDK will increase the chances of first-pass successful silicon and provide good yield for chip. 5 | 6 | The **OpenRPDK28** is Open RIOS PDK, created by the [RIOS Lab](https://www.rioslab.org/). This PDK is open-source and could be used for a preliminary template for the industrial level PDK. 7 | The **OpenRPDK28** is an open-source PDK developed by the [RIOS Lab](https://www.rioslab.org/) and serves as a preliminary template for industrial-level PDKs. The PDK is designed to be flexible and customizable, allowing users to modify it to their specific needs. Additionally, the OpenRPDK28 offers a wide range of features, such as the ability to integrate with open-source EDA tools. The PDK is also accompanied by comprehensive documentation, making it easy for users to get started and begin designing their own chips. Overall, the OpenRPDK28 will be an excellent choice for anyone looking to develop their own custom chips and is sure to meet the needs of a wide range of users. 8 | 9 | As part of its commitment to the open-source community, RIOS Lab will make the OpenRPDK28 project completely open-source. This means that anyone can access the code, contribute to the project, and even use this pDK in their own products. RIOS Lab believes that by making the project open-source, it will encourage innovation and collaboration in the process-design bridge, leading to even more exciting and groundbreaking developments in the future. 10 | 11 | ![image](https://github.com/riosmpw/OpenRPDK28/assets/100336131/0f9578f7-6952-4f26-ba7d-d6dfec5fbe3b) 12 | 13 | 28nm OpenRPDK Content 14 | 15 | **OpenRPDK28 is under constrcuction now** 16 | 17 | 18 | OpenRPDK28 defines a certain technology variation and characteristic for the 28nm open-source academic processes. Designers may enhance this PDK, tailoring it to their specific design styles and markets. 19 | 20 | OpenRPDK28 offers a library of blocks for re-use, each one the result of years of research and development. It will plays a pivotal role in open source EDA and process breakthrough: 21 | 22 | 1) Access to a OpenRPDK28 means IC designers don’t have to start from scratch. Designer could choose from open-source building blocks which have already proven their efficacy and functionality, resulting in a shorter time to research or market and at lower development costs. 23 | 24 | 2) An OpenRPDK28 is crucial in the design phase. 28nm PDK-based designs follow a series of design rules which makes them compliant with 28nm open-source process. 25 | 26 | Designers could use the OpenRPDK28 to design, simulate, draw and verify the integrated circuit design before puting the design back to the foundry to manufacture chips. 27 | 28 | ![image](https://github.com/riosmpw/OpenRPDK28/assets/100336131/75a95b38-7a87-44c3-8521-2af649e463a9) 29 | 30 | 31 | Open EDA Ecosystem 32 | 33 | 34 | 35 | ## 1 Description 36 | 37 | Different tools in the design flow have different input formats for the PDK data. 38 | 39 | ![image](https://github.com/riosmpw/OpenRPDK28/assets/100336131/61d08cb4-57c1-4a23-8941-614b1bfddb0e) 40 | 41 | 42 | **OpenRPDK28** PDK contains: 43 | 44 | - Technology data 45 | 46 | - Layers, layer names, layer/purpose pairs 47 | 48 | - Colors, fills and display attributes 49 | 50 | - Process constraints 51 | 52 | - Electrical rules 53 | 54 | - A primitive device library 55 | 56 | - Symbols 57 | 58 | - SPICE or Varilog-A model and device parameters 59 | 60 | - Parameterized cells 61 | 62 | - Rule check files 63 | 64 | - Design rule checking 65 | 66 | - Layout versus schematic 67 | 68 | - Antenna and electrical rule check 69 | 70 | - Physical parameters extraction 71 | 72 | - Litho friendly check 73 | 74 | - Other DFM check 75 | 76 | - Design Rule Manual 77 | 78 | - A user friendly documents of the process 79 | 80 | ![image](https://github.com/riosmpw/OpenXPDK28/assets/100336131/89d5dcd0-6f8f-43c8-8960-570019a38714) 81 | 82 | Standard Cell Designed with OpenRPDK 83 | 84 | ## 2 DTCO (Design-Technology Co-Optimization) 85 | 86 | Design Technology Co-Optimization (DTCO) is a methodology that helps semiconductor foundries reduce cost and time-to-market in process development. 87 | 88 | In DTCO flow, design and process technology optimized together to improve performance, power efficiency, transistor density, and cost. DTCO for a new technology node usually involves substantial architectural innovation instead of just delivering the similar structure as the previous process node. 89 | 90 | ![image](https://github.com/riosmpw/OpenRPDK28/assets/100336131/58bf54e3-be74-4ffb-9f95-a8528c1161de) 91 | 92 | 93 | DTCO Flow (Source: Synopsys) 94 | 95 | ## 3 DFM (Design for Manufacturing) 96 | 97 | As the IC manufacturing enter sub 40nm tech nodes, DFM become more and more important to make sure more stable yield and lower cost. Manufacturing is facing big challenges in terms of manufacturability, yield ramp-up, and variability. 98 | 99 | To addresses these challenges, physical verification and implementation technolgies have been augmented with in-design and signoff DFM checks and automated DFM enhancement, then designers can reduce the impact of variability and improve the manufacturability of IC designs. And foundries also need highly accurate modeling and efficient design analysis, yield enhancements, and mask data preparation in their workflow. 100 | 101 | ![image](https://github.com/riosmpw/OpenRPDK28/assets/100336131/46f7294c-e84c-42cd-9baa-9ad8eb4723f1) 102 | 103 | 104 | Typical DFM flow: 105 | 106 | 1) LFD (Litho Fridenly Design) 107 | 108 | LFD is the methodology to address the urgent issue of how to accurate manage lithographic process variability in the early stages of design creation. Accurately LFD could maintain the lithographic processes on “as-drawn” layout data to determine the actual “as-built” dimensions of fabricated gates and metal interconnects. 109 | 110 | 2) CMP(Chemical-mechanical polishing) 111 | 112 | Chemical mechanical polishing (CMP) or planarization is a process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of chemical etching and free abrasive polishing 113 | 114 | 115 | ## 4 Multi-Physics and IR-Drop Analysis 116 | 117 | Multi-physics and IR-Drop analysis are important steps in designing electronic chips. Multi-physics analysis allows you to simulate how your chip behaves under different conditions, giving you insight into its performance. This helps you identify potential problems and make improvements before manufacturing. Similarly, IR-Drop analysis ensures that your chip is optimized for power delivery and voltage drops. By analyzing voltage drop across the chip, you can identify areas where voltage may be too low and take steps to fix it. Combining both analyses improves the manufacturability, performance, and reliability of your chip. It's worth noting that while these analyses may add complexity to the design process, their long-term benefits outweigh any drawbacks. 118 | 119 | Furthermore, when considering the manufacturing cost and time of a product, it is important to take into account changes in multi-physics and IR-drop. Multi-physics refers to the interaction of different physical phenomena in a manufacturing process, such as thermo-mechanical or electro-thermal interactions. Changes in multi-physics can have a significant impact on the manufacturability of a product and need to be considered during the design phase. Similarly, IR-drop refers to the voltage drop across a circuit due to the resistance of the materials used. This can lead to a significant reduction in power and performance of the device being manufactured. By taking into account changes in multi-physics and IR-drop, engineers and designers can make more informed decisions that will ultimately result in a more robust and efficient manufacturing process. 120 | 121 | 122 | ## 5 28nm Process Node 123 | 124 | Under the guidance of Moore's Law, the feature length of integrated circuits is constantly reducing. 125 | 126 | The 28nm process is between 32nm and 22nm. 2013 was the year of 28nm process popularization. Between 2015 and 2016, the 28nm process began to be used in cell phone application processors and basebands chip at scale. 127 | 128 | The planar process can be most cost-effective at 28nm, and 28nm maybe the best planar process in foundry both in performance and cost-efficiency . For the subsequent 16/14nm FinFET process, the cost of IC manufacturing increases by at least 50%. Only applications with huge amount such as cell phones or processors can support the cost and market size. In many applications, 28nm planar process offers good value for performance, and cost balance. 129 | 130 | ![81d00d417c3e3dc179ee0d73a42d95d9_figure-4-amd215821](https://github.com/riosmpw/OpenXPDK28/assets/100336131/20b596a1-bc7d-44ca-b5dd-f306b69e4cb3) 131 | 132 | 28nm HP 6T-SRAM Example – Plan View SEM (Source: chipworks) 133 | 134 | 135 | 136 | ## Main Reference 137 | 138 | 139 | | Item | Type | Link | Comment | 140 | |------------------------|---------|------------------|---------| 141 | | google/skywater-pdk | PDK | [https://github.com/google/skywater-pdk](https://github.com/google/skywater-pdk) | | 142 | | SkyWater SKY130 PDK | DOC | [https://skywater-pdk.readthedocs.io](https://skywater-pdk.readthedocs.io) | | 143 | | GlobalFoundries 0.18UM 3.3V/(5V)6V MCU PDK | DOC |[https://gf180mcu-pdk.readthedocs.io/](https://gf180mcu-pdk.readthedocs.io/) | | 144 | | globalfoundries-pdk-libs-gf180mcu_fd_pr | PDK |[https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr](https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr) | | 145 | | The OpenLane Documentation | DOC |[https://openlane.readthedocs.io/](https://openlane.readthedocs.io） | | 146 | | Gate level static timing analyzer | | [https://github.com/The-OpenROAD-Project/OpenSTA ](https://github.com/The-OpenROAD-Project/OpenSTA ) | | 147 | | Neural Networks for Automated Power Delivery Network (PDN) Synthesis | | [https://github.com/The-OpenROAD-Project/OpeNPDN ]( https://github.com/The-OpenROAD-Project/OpeNPDN) | | 148 | | IR Solver | | [https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm ](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm ) | | 149 | | P-Cell | | https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr/tree/main/cells/klayout/pymacros/cells] | | 150 | | STD Cell | | https://github.com/thesourcerer8/StdCellLib | | 151 | | STD Cell | | https://ceat.okstate.edu/ece/faculty/james-stine.html | | 152 | | DRC&LVS | | https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pv | | 153 | 154 | 155 | ## About RIOS Lab 156 | 157 | ![image](https://github.com/riosmpw/OpenRPDK28/assets/109063674/6aae13c6-50a5-40c3-9a4e-ed4c79d41c20) 158 | 159 | 160 | **Ecosystem Wants to be Free** 161 | 162 | By David A. Patterson · Director of RIOS Lab 163 | 164 | **RISC-V International Open Source Laboratory** (RIOS Lab) is a Shenzhen-based research facility focused on computer system architecture, supported by the Tsinghua-Berkeley Shenzhen Research Institute. As an Open Source and Nobel Prize Laboratory, RIOS Lab promotes open-source innovation and collaboration. Our philosophy is that the computer architecture ecosystem should be free for all to access and build upon. 165 | 166 | In November 2019, RIOS Lab was officially unveiled. Under the leadership of 2017 A.M. Turing Award winner Prof. David A. Patterson and operational support from TBSI, RIOS Lab will conduct cutting-edge research in RISC-V hardware and software technology. Patterson first proposed the Reduced Instruction Set Computer (RISC), an open and free instruction set architecture enabling a new era of processor innovation through open standard collaboration. Released in 2010, the latest Fifth Generation RISC has gained worldwide attention. 167 | 168 | The name for the lab RIOS is also inspired by the Spanish word for “rivers.” It symbolizes the flow of information from many sources, coming together to create a whole that is greater than the sum of its parts. 169 | 170 | 171 | -------------------------------------------------------------------------------- /bin/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /dev/custom_pdk_builds.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | If you need custom libraries, you will have to resort to manual builds using Volare as shown below. You will need Git 2.35+ and Docker. 4 | 5 | Note that this will take a while, from 20 minutes to an hour depending on your internet speed and compute power. 6 | 7 | Start a venv shell using make start-build-env. You should see a prompt looking kind of like this: 8 | 9 | (venv) [user@host openlane]$ 10 | First of all, install volare: 11 | 12 | pip3 install --upgrade --no-cache-dir volare 13 | Then, build the PDK as follows: The -l options are the libraries you want to include. For example, to also include sky130_fd_sc_hs, you can add -l sky130_fd_sc_hs to the default set of libraries using the following command: 14 | 15 | volare build -j$(nproc) --pdk sky130 --clear-build-artifacts --sram -l sky130_fd_io -l sky130_fd_pr -l sky130_fd_sc_hvl -l sky130_fd_sc_hd -l sky130_fd_sc_hs 16 | You can also add -l all to just include all of them: 17 | 18 | volare build -j$(nproc) --pdk sky130 --clear-build-artifacts --sram -l all 19 | Either way, go grab a smoothie. This will take a while. 20 | 21 | After it is done, you can then enable the resulting PDK as such: 22 | 23 | volare enable 24 | Et voila, your custom-built PDK is ready. 25 | -------------------------------------------------------------------------------- /dfm/README.md: -------------------------------------------------------------------------------- 1 | # Design for Manufacture 2 | 3 | Design for Manufacture (DFM) is a set of guidelines that aim to optimize the design of a chip for efficient and cost-effective manufacturing. The goal of DFM is to ensure that the chip can be produced at scale, with minimal production costs, and without compromising on quality. 4 | 5 | DFM tool involves collaboration between the design team and the manufacturing team from the early stages of product development. This collaboration ensures that the design takes into account the manufacturing process and tooling, among other factors. 6 | ![0b1d1430a1bbd24c2e0532469c81715e_Manufacturing-design-pattern-library-from-Full-chip-mask-data-simulation-Systematic](https://github.com/RIOSMPW/OpenRPDK28/assets/100336131/a4c702ac-a5f8-4d7e-9568-b43ca1f178bb) 7 | 8 | Manufacturing design pattern library from Full chip mask data simulation & Systematic defect detection on Silicon. (Source:Jean-Christophe Le Denmat ) 9 | 10 | 11 | Chip design establishes a chip’s vulnerability to defect-induced yield loss. The design optimization guidelines described in this section were generated following the development and use of critical area analysis tools on a wide variety of designs. Following these guidelines helps ensure: 12 | 13 | 1) Faster technology and product development because manufacturing sites typically target CA and V1 images at upper specification limits and metal spacing near lower specification limits to prevent open circuits. 14 | 15 | 2) Improved yields because the resulting designs will be less sensitive to the random manufacturing defects that impact yield. 16 | 17 | 3) More chips that fulfill the specifications sooner. 18 | 19 | 4) Fewer process variations, especially for contacts. 20 | 21 | 5) Fewer parasitics and improved circuit performance 22 | 23 | Design for manufacturability does not always require drastic changes. Every change, including a change of only one grid point, can help. The following general recommendations will help improve the manufacturability of a design: 24 | 25 | 1) Do not compromise on area; use existing empty space. 26 | 27 | 3) Use the recommended rules wherever possible. 28 | 29 | 4) Increase space and width equally wherever possible. 30 | 31 | 5) For long, parallel metal or polysilicon lines, use wider spacing. (A long line is approximately 50 times the minimum design length. 32 | 33 | 34 | ![image](https://github.com/RIOSMPW/OpenRPDK28/assets/100336131/1986b1b2-7826-459a-970a-5ac6969c0ffb) 35 | 36 | Optical simulation of Litho( Source: Yorick Trouiller) 37 | 38 | ## 4.1 Yield Enhancement Design Techniques 39 | 40 | 1) Space out elements as much as possible. 41 | Unless this approach grows the design beyond the available space, move elements as far apart as possible. If the design is wiring-limited, spread out the devices, and vice versa. If white space exists, use it. 42 | 43 | ![image](https://github.com/RIOSMPW/OpenRPDK28/assets/100336131/685eb9b2-53ca-4514-928d-4701a505ccec) 44 | 45 | 46 | -------------------------------------------------------------------------------- /docs/masks.md: -------------------------------------------------------------------------------- 1 | This file provide the mask layer information of current OpenRPDK 28nm process. 2 | 3 | The following layers are drawn directly on the layout system. 4 | 5 | | Layer Type | Layer Name(GF) | Purpose | GDS \#(GF) | Data type | 6 | |------------|----------------------|-----------------------------------------------------------------|--------|-----------| 7 | | Drawn | COMP (1) | Diffusion for device and interconnect | 22 | 0 | 8 | | Drawn | DNWELL | Deep Nwell | 12 | 0 | 9 | | Drawn | Nwell | Nwell implant | 21 | 0 | 10 | | Drawn | LVPWELL | Pwell implant | 204 | 0 | 11 | | Drawn | Dualgate | 6V Gate Oxide | 55 | 0 | 12 | | Drawn | Poly2 | POLY2 gate & interconnect | 30 | 0 | 13 | | Drawn | Nplus | Nplus Implant | 32 | 0 | 14 | | Drawn | Pplus | Pplus Implant | 31 | 0 | 15 | | Drawn | SAB | Unsalicided poly & active regions | 49 | 0 | 16 | | Drawn | ESD (2) | ESD Implant (Optional) | 24 | 0 | 17 | | Drawn | Contact | Metal1 to Active or Poly2 contact | 33 | 0 | 18 | | Drawn | Metal1 | Metal1 interconnect | 34 | 0 | 19 | | Drawn | Via1 | Metal2 to Metal1 contact | 35 | 0 | 20 | | Drawn | Metal2 | Metal2 interconnect | 36 | 0 | 21 | | Drawn | Via2 | Metal3 to Metal2 contact | 38 | 0 | 22 | | Drawn | Metal3 | Metal3 interconnect | 42 | 0 | 23 | | Drawn | Via3 | Metal4 to Metal3 contact | 40 | 0 | 24 | | Drawn | Metal4 | Metal4 interconnect | 46 | 0 | 25 | | Drawn | Via4 | Metal5 to Metal4 contact | 41 | 0 | 26 | | Drawn | Metal5 | Metal5 interconnect | 81 | 0 | 27 | | Drawn | Via5 | Metal 6 to Metal5 contact | 82 | 0 | 28 | | Drawn | MetalTop | MetalTop interconnect | 53 | 0 | 29 | | Drawn | Pad (1) | Bond pad opening | 37 | 0 | 30 | | Drawn | Resistor (3) | High sheet rho P-poly resistor (Optional) | 62 | 0 | 31 | | Drawn | FHRES (3) | Free high sheet rho P-POLY2 resistor | 227 | 0 | 32 | | Drawn | FuseTop (3) | Top plate of MIM capacitors (Optional) | 75 | 0 | 33 | | Drawn | FuseWindow\_D | Metal Fuse window (Optional) | 96 | 1 | 34 | | Drawn | POLYFUSE | POLY FUSE window (Optional) | 220 | 0 | 35 | | Drawn | MVSD | Define LDNMOS Drain | 210 | 0 | 36 | | Drawn | MVPSD | Define LDPMOS Drain | 11 | 39 | 37 | | Drawn | NAT | N-channel native VT mark layer | 5 | 0 | 38 | | Drawn | COMP\_Dummy | COMP Dummy fill | 22 | 4 | 39 | | Drawn | Poly2\_Dummy | Poly2 Dummy Fill | 30 | 4 | 40 | | Drawn | Metal1\_Dummy (4) | Metal1 Dummy Fill | 34 | 4 | 41 | | Drawn | Metal2\_Dummy (4) | Metal2 Dummy Fill | 36 | 4 | 42 | | Drawn | Metal3\_Dummy (5) | Metal3 Dummy Fill | 42 | 4 | 43 | | Drawn | Metal4\_Dummy (5) | Metal4 Dummy Fill | 46 | 4 | 44 | | Drawn | Metal5\_Dummy (5) | Metal5 Dummy Fill | 81 | 4 | 45 | | Drawn | MetalTop\_Dummy (5) | MetalTop Dummy Fill | 53 | 4 | 46 | | Drawn | COMP\_Label (6) | LABEL drawn at active layer | 22 | 10 | 47 | | Drawn | Poly2\_Label (6) | LABEL drawn at poly2 layer | 30 | 10 | 48 | | Drawn | Metal1\_Label (6) | LABEL drawn at Metal1 layer | 34 | 10 | 49 | | Drawn | Metal2\_Label (6) | LABEL drawn at Metal2 layer | 36 | 10 | 50 | | Drawn | Metal3\_Label(6) | LABEL drawn at Metal3 layer | 42 | 10 | 51 | | Drawn | Metal4\_Label (6) | LABEL drawn at Metal4 layer | 46 | 10 | 52 | | Drawn | Metal5\_Label (6) | LABEL drawn at Metal5 layer | 81 | 10 | 53 | | Drawn | MetalTop\_Label (6) | LABEL drawn at MetalTop layer | 53 | 10 | 54 | | Drawn | Metal1\_Slot | Metal1 Slot (used to create slots in metal1) | 34 | 3 | 55 | | Drawn | Metal2\_Slot | Metal2 Slot (used to create slots in metal2) | 36 | 3 | 56 | | Drawn | Metal3\_Slot | Metal3 Slot (used to create slots in metal3) | 42 | 3 | 57 | | Drawn | Metal4\_Slot | Metal4 Slot (used to create slots in metal4) | 46 | 3 | 58 | | Drawn | Metal5\_Slot | Metal5 Slot (used to create slots in metal5) | 81 | 3 | 59 | | Drawn | MetalTop\_Slot | MetalTop Slot (used to create slots in metal top) | 53 | 3 | 60 | | Drawn | UBMPPeri | Direct Bumping option using peripheral printing | 183 | 0 | 61 | | Drawn | UBMPArray | Direct Bumping option using Array printing | 184 | 0 | 62 | | Drawn | UBMEPlate | Direct Bumping option using Electroplating | 185 | 0 | 63 | | Drawn | Schottky\_diode | Define Schottky diode area | 241 | 0 | 64 | | Drawn | ZENER | ZENER diode implant | 178 | 0 | 65 | | Marking | RES\_MK (1) | Resistor Mark | 110 | 5 | 66 | | Marking | OPC\_drc | Marking layer for OPC design rule check. | 124 | 5 | 67 | | Marking | NDMY (1) | Dummy Active Exclude Mark layer | 111 | 5 | 68 | | Marking | PMNDMY (1) | Dummy Poly & Metal Exclude Mark | 152 | 5 | 69 | | Marking | V5\_XTOR (7) | Define 5V Transistor Marking Layer | 112 | 1 | 70 | | Marking | CAP\_MK (8) | MIM Capacitor Marking layer | 117 | 5 | 71 | | Marking | MOS\_CAP\_MK | MOS capacitor LVS marking | 166 | 5 | 72 | | Marking | IND\_MK | Inductor Mark | 151 | 5 | 73 | | Marking | DIODE\_MK | Diode Mark | 115 | 5 | 74 | | Marking | DRC\_BJT (9) | BJT marking for DRC | 127 | 5 | 75 | | Marking | LVS\_BJT | BJT Mark | 118 | 5 | 76 | | Marking | MIM\_L\_MK | Min length marking layer for MIM Capacitor | 117 | 10 | 77 | | Marking | Latchup\_MK | Marking layer for I/O latch-up rule check | 137 | 5 | 78 | | Marking | GUARD\_RING\_MK | Marking Layer for Scribe Line Guard Ring | 167 | 5 | 79 | | Marking | OTP\_MK | To define OTP area with Marking layer | 173 | 5 | 80 | | Marking | MTPMARK | Multi Time Program Memory cell marking | 122 | 5 | 81 | | Marking | NEO\_EE\_MK | NeoEE OTP area with Marking layer | 88 | 17 | 82 | | Marking | SramCore (10) | SRAM Mark | 108 | 5 | 83 | | Marking | LVS\_RF | RF LVS Mark | 100 | 5 | 84 | | Marking | LVS\_Drain | RF Drain LVS Mark | 100 | 7 | 85 | | Marking | IND\_MK1 | Inductor Mark | 151 | 5 | 86 | | Marking | HVPOLYRS | High Voltage Poly2 Resistor in HV area Marking layer | 123 | 5 | 87 | | Marking | LVS\_IO | IO LVS Mark | 119 | 5 | 88 | | Marking | PROBE\_MK | Marking layer for probe pad | 13 | 17 | 89 | | Marking | ESD\_MK | Marking layer on ESD protection device | 24 | 5 | 90 | | Marking | LVS\_Source | Source LVS/DRC marking Layer | 100 | 8 | 91 | | Marking | WELL\_DIODE\_MK | Marking layer for Nwell/Psub, LVPwell/Dnwell, DNwell/Psub diode | 153 | 51 | 92 | | Marking | LDMOS\_XTOR | LDMOS device mark layer | 226 | 0 | 93 | | Marking | PLFUSE | Marking layer for eFUSE Link | 125 | 5 | 94 | | Marking | EFUSE\_MK | Marking layer for whole eFUSE Element | 80 | 5 | 95 | | Marking | MCELL\_FEOL\_MK (13) | Marking layer to define YMTP Mcell Implant region | 11 | 17 | 96 | | Marking | YMTP\_MK (13) | Marking layer to define YMTP Cell and exclude NLDD region | 86 | 17 | 97 | | Marking | DEV\_WF\_MK | LVS marking layer for Fab special purposes layout | 128 | 17 | 98 | | EDAMark | Metal1\_BLK | Place & Route Metal1 Blockage | 34 | 5 | 99 | | EDAMark | Metal2\_BLK | Place & Route Metal2 Blockage | 36 | 5 | 100 | | EDAMark | Metal3\_BLK | Place & Route Metal3 Blockage | 42 | 5 | 101 | | EDAMark | Metal4\_BLK | Place & Route Metal4 Blockage | 46 | 5 | 102 | | EDAMark | Metal5\_BLK | Place & Route Metal5 Blockage | 81 | 5 | 103 | | EDAMark | MetalT\_BLK | Place & Route MetalTop Blockage | 53 | 5 | 104 | | EDAMark | PR\_bndry | PR Boundary for cell, block or chip | 0 | 0 | 105 | | EDAMark | MDIODE | MDiode Mark | 116 | 5 | 106 | | EDAMark | Metal1\_Res (11) | Metal 1 Resistor | 110 | 11 | 107 | | EDAMark | Metal2\_Res (11) | Metal 2 Resistor | 110 | 12 | 108 | | EDAMark | Metal3\_Res (11) | Metal 3 Resistor | 110 | 13 | 109 | | EDAMark | Metal4\_Res (11) | Metal 4 Resistor | 110 | 14 | 110 | | EDAMark | Metal5\_Res (11) | Metal 5 Resistor | 110 | 15 | 111 | | EDAMark | Metal6\_Res (11) | Metal6 Resistor | 110 | 16 | 112 | | DevMark | Border | Border | 63 | 0 | 113 | 114 | 115 | 116 | | Term | Definition | 117 | |---------------------|-----------------------------| 118 | | NCOMP | COMP AND Nplus | 119 | | PCOMP | COMP AND Pplus | 120 | | Field | NOT COMP | 121 | | Transistor gate | Poly2 AND COMP | 122 | | N-channel gate | Nplus AND Poly2 AND COMP | 123 | | P-channel gate | Pplus AND Poly2 AND COMP | 124 | -------------------------------------------------------------------------------- /docs/userguide/1-schematic capture.md: -------------------------------------------------------------------------------- 1 | # XSCHEM ELEMENTS 2 | 3 | ## SYMBOLS 4 | Symbols are graphical elements that represent electrical components. A symbol represents an electronic device, like for example a resistor, a bipolar transistor, an amplifier etc. As you can see graphically symbols are built with lines, rectangles, polygons and texts, the graphical primitives shown before. In the picture below some components are placed in a schematic window. Components are instances of symbols. For example you see three placements of the 'npn' bipolar transistor symbol. Like in C++, where objects are instances of classes, here components are instances of symbols. 5 | 6 | ![492ce4fae41d7153a3cad57ae1df84df_xschem_symbols](https://github.com/riosmpw/OpenRPDK28/assets/100336131/ff877469-51b1-4ee6-b859-2b42515ea8c1) 7 | 8 | 9 | ## WIRES 10 | 11 | Wires in XSCHEM are the equivalent of copper traces in printed circuit boards or electrical conductors. Wires are drawn as lines but the electrical connectivity graph is built by XSCHEM. To draw a wire segment point the mouse somewhere in the drawing window and press the 'w' key. A rubber wire is shown with one end following the mouse. Clicking the left mouse button finishes the placement. The following picture shows a set of connected wires. There are many wire segments but only 3 electrical nodes. XSCHEM recognizes connection of wires and uses this information to build up the circuit connectivity. All wires are drawn on the 'wire' layer. One electrical node in the picture below has been highlighted in red (this is a XSCHEM function we will cover later on). 12 | 13 | ![7984efe9c3daa6e90b3735dd7e6253b1_xschem_wires](https://github.com/riosmpw/OpenRPDK28/assets/100336131/31228215-8381-4da5-8a92-cd942ded4198) 14 | 15 | ## LINES 16 | 17 | Lines are just segments that are used for drawing. Lines do not have any electrical meaning, in fact when building the circuit netlist, lines are completely ignored. XSCHEM uses different layers to draw lines. Each layer has its own color, allowing to draw with different colors. Lines are placed like wires, but using the 'l' key. The 'Layers' menu allows to select various different layers (colors) for the line. 18 | 19 | ![3783d4b934e54dc1841895a81f77d01b_xschem_lines](https://github.com/riosmpw/OpenRPDK28/assets/100336131/3170a6b8-5bbd-441a-8ff6-baf8fff30dcd) 20 | 21 | ## TEXT 22 | 23 | Text can be placed with the 't' bindkey. A dialog box appears where the user inputs the text and text size. 24 | 25 | ![d73159a32450e6fc9dcf0c1bbe1a1c11_xschem_texts](https://github.com/riosmpw/OpenRPDK28/assets/100336131/dd5c31c9-5305-4def-8182-527b9f0289fa) 26 | 27 | The layer property can be used to draw text on a different layer, for example, setting layer=6 will draw on cyan color. A font property is defined to change the default font. A hcenter=true attribute may be set to center text in the reading direction, while vcenter=true centers text in the perpendicular (to reading) direction. the 2 attributes may be set both to get full centered text box. 28 | A weight=bold attribute may be given for bold text, while a slant=italic or slant=oblique may specify italic or slanted text. 29 | A hide=true will make the specified text invisible when the symbol is displayed as a component in a schematic. 30 | 31 | ![a02e8d97dfea608036fd0cd0959e42ac_xschem_elements_02](https://github.com/riosmpw/OpenRPDK28/assets/100336131/95b57255-8216-42be-a097-0290e0511efd) 32 | 33 | # CREATING A CIRCUIT SCHEMATIC 34 | 35 | To create a new circuit start from an empty window, run xschem and select New Schematic in the File menu. Suppose we want co create a NAND gate, with two inputs, A and B and one output, Z. Lets start placing the input and output schematic pins; use the Insert key and locate the devices/ipin.sym symbol. After placing it change its lab attribute to 'A' 36 | 37 | ![76e5141b3ea5d6e32d15b88a061d9fb2_creating_schematic1](https://github.com/riosmpw/OpenRPDK28/assets/100336131/b7061b45-db47-4bde-95f2-2df2c04709aa) 38 | 39 | Copy another instance of it and set its lab attribute to B. Next place an output pin devices/opin.sym and set its lab to Z. The result will be as follows: 40 | 41 | ![e0979d37986e50390489378468dea062_creating_schematic2](https://github.com/riosmpw/OpenRPDK28/assets/100336131/45a15821-f89b-451b-874b-d378be25e143) 42 | 43 | Now we need to build the actual circuit. Since we plan to do it in CMOS technology we need nmos and pmos transistors. Place one nmos from devices/nmos4.sym and one pmos from devices/pmos4.sym By selecting them with the mouse, moving (m bindkey), copying ('c' bindkey) place 4 transistors in the following way (the upper ones are pmos4, the lower ones nmos4): 44 | 45 | ![c625c6dbdd08a4a298bb2c9ac0bda127_creating_schematic3](https://github.com/riosmpw/OpenRPDK28/assets/100336131/e5273dc2-da7d-49e7-a63a-368baaf12c39) 46 | 47 | 48 | now draw wires to connect together the transistor to form a NAND gate; in the picture i have highlighted 2 electrical nodes by selecting one wire segment of each and pressing the 'k' bindkey. 49 | 50 | 51 | ![848ee184998a2c30eb46ed783737d2fb_creating_schematic4](https://github.com/riosmpw/OpenRPDK28/assets/100336131/fc05c276-4ebf-49f8-a9d7-b9f902f61f8e) 52 | 53 | Next we need to place the supply nodes , VCC and VSS. we decide to use global nodes. Global nodes in SPICE semantics are like global variables in C programs, they are available everywhere, we do not need to propagate global nodes with pins. We could equally well use regular pins , as used for the A and B inputs, I am just showing different design styles. Use the Insert key and place both devices/vdd.sym and devices/gnd.sym Since the default names are respectively VDD and GND use the edit property bindkey 'q' to change these to VCC and VSS. 54 | 55 | ![266b3c38b645bbe58c4e5eb4b2e22111_creating_schematic5](https://github.com/riosmpw/OpenRPDK28/assets/100336131/0b78f783-658b-431e-bc6c-aa6e6f294e7a) 56 | 57 | we still need to connect the body terminals of the mos transistors. One possibility is to hookup the two upper pmos transistor terminals to VCC with wires, and the two bottom nmos terminals to VSS with wires, but just to show different design styles i am planning to use ''by name'' connection with labels. So place a wire label devices/lab_pin.sym and use 4 instances of it to name the 4 body terminals. Remember, while moving (select and press the 'm' key) you can flip/rotate using the R/F keys. 58 | 59 | 60 | ![415ef4e2b0f7324178b701704f89e772_creating_schematic6](https://github.com/riosmpw/OpenRPDK28/assets/100336131/eb625905-8b89-410c-8d5a-548f093b2408) 61 | 62 | 63 | Finally we must connect the input and output port connectors, and to complete the gate schematic we decide to use W=8u for the pmos transistors. Select both the pmos devices and press the edit proprty 'q' key; modify from 5u (default) to 8u. 64 | 65 | ![f9f385fb909b695ba5f6eda08bc7ac6a_creating_schematic7](https://github.com/riosmpw/OpenRPDK28/assets/100336131/b0c832f7-831e-44b9-857d-c60b968e90d2) 66 | 67 | Now do a Save as operation, save it for example in mylib/nand2.sch. 68 | To make the schematic nicer we also add the title component. This component is not netlisted but is useful, it reports the modification date and the author. Place the devices/title.sym component. The NAND gate is completed! (below picture also with grid, normally disabled in pictures to make image sizes smaller). 69 | 70 | 71 | 72 | 73 | # Reference 74 | 75 | https://xschem.sourceforge.io/stefan/xschem_man/xschem_elements.html 76 | 77 | https://xschem.sourceforge.io/stefan/xschem_man/creating_schematic.html 78 | 79 | -------------------------------------------------------------------------------- /docs/userguide/2-pre-layout simulation.md: -------------------------------------------------------------------------------- 1 | # ngspice 2 | 3 | ngspice is a circuit simulator that numerically solves equations describing (electronic) circuits: These are made of passive and active devices. Time varying currents and voltages are simulated as well as noise and small signal behavior. ngspice is the Open Source successor of the venerable spice3f5 from UC at Berkeley. 4 | 5 | ![9b71e463bd51a9206bc8178207623268_intro1](https://github.com/riosmpw/OpenRPDK28/assets/100336131/70f7b48a-7f3b-4d5e-bcd7-552957776eb4) 6 | 7 | 8 | Fig. 1 9 | 10 | As shown in Fig. 1, you start with a circuit (here: an inverter). You have to create a netlist describing this circuit. The netlist is the input to ngspice, telling it about the circuit to be simulated. Together with some simulation commands this input cares for reading and parsing the netlist, starting the simulation and plotting the output. The output voltage (plotted in red) is the inverse of the (green) input. Both voltages are plotted versus time. 11 | 12 | The input to ngspice is read from a file, and it may be enhanced by commands given on the command line. The simulated output may be written to a file, or be plotted as a y-x graph or a smith chart. There is no graphical user interface with schematic capture of circuit diagrams and automatic netlist generation, however there are third party tools available to draw the circuit and generate a ngspice netlist. 13 | 14 | 15 | # Reference 16 | 17 | https://ngspice.sourceforge.io/ngspice-tutorial.html 18 | -------------------------------------------------------------------------------- /docs/userguide/3-layout creation.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /docs/userguide/4-physical verification.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /docs/userguide/5-post-layout simulation.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /docs/userguide/6-dfm-verification.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /docs/userguide/README.md: -------------------------------------------------------------------------------- 1 | 2 | # Purpose 3 | The main purpose of this document is to introduce the basic usage of OpenRPDK flow for those users who are new to OpenRPDK. 4 | A simple design flow is used as an example to show the whole design philosophy starting, which goes from the schematic capture and ending at post-layout simulatiom and DFM verification. 5 | 6 | # Design Phases 7 | The whole flow is divided into several phases to match general logic or mix-signal design flows. Which are： 8 | 9 | 1）Schematic capture 10 | 11 | 2）Pre-layout simulation 12 | 13 | 3）Layout creation 14 | 15 | 4）Physical verification 16 | 17 | 5）Post-layoutsimulation 18 | 19 | 6）DFM verification 20 | -------------------------------------------------------------------------------- /dtco/README.md: -------------------------------------------------------------------------------- 1 | # Design Technology Co-Optimization 2 | 3 | Design Technology Co-Optimization (DTCO) analysis was pursued for library cell or chip PPA estimates for devices and new metallurgy options. The cell design and process recommendations are a bit surprising. 4 | 5 | Physical and electrical models for scaled devices and interconnects were derived and IP design progressed while the process was being qualified. Several factors led to the need for a much closer collaboration between process technology and std cell library development, a partnership which has been described as Design Technology Co-Optimization” (DTCO), 6 | 7 | ![70e57dde41d374f038aea1fec2e2642c_DTCO_cell_designs](https://github.com/RIOSMPW/OpenRPDK28/assets/100336131/41bc0510-2e50-4d26-80d0-1fc9a649da16) 8 | 9 | Cell design alternatives(Source：Tom Dillinger ) 10 | -------------------------------------------------------------------------------- /libraries/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /libraries/cmp/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /libraries/drc/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /libraries/drc/magic/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /libraries/lfd/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /libraries/lvs/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /libraries/lvs/netgen/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /libraries/models/commonspice/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /libraries/models/ngspice/design.ngspice: -------------------------------------------------------------------------------- 1 | * OpenRPDK Authors 2 | * 3 | ************************************************************************* 4 | ** Global Parameter Settings 5 | ************************************************************************* 6 | ** NGSPICE include file for global switches, corner parameters 7 | ** and other user-defined settings 8 | ** ********************************************************************** 9 | ** ------------------------------------------- 10 | ** MonteCarlo and matching simulation setting: 11 | ** ------------------------------------------- 12 | ** sw_stat_global 13 | ** sw_stat_mismatch 14 | ** 15 | ** -------------------------------------------------------------------------- 16 | ** | setting | sw_stat_global=0 | sw_stat_global=1 | 17 | ** -------------------------------------------------------------------------- 18 | ** | sw_stat_mismatch=0 | No statistical | Global variation is on, | 19 | ** | | modeling | but mismatch is off. | 20 | ** -------------------------------------------------------------------------- 21 | ** | sw_stat_mismatch=1 | mismacth is on, | Most realistic | 22 | ** | | global variation off | distribution. | 23 | ** -------------------------------------------------------------------------- 24 | ** 25 | ** 26 | ** (default) - sw_stat_global=1 and sw_stat_mismatch=1 27 | ** This setting provides the most complete representation of the 28 | ** statistical variations during chip manufacturing. 29 | ** Global process variations are determined by random distributions. 30 | ** Mismatch is differentiated from global variation in that mismatch only 31 | ** includes intra-die variation, and it is especially critical for analog matching applications. 32 | ** 33 | ** mc_skew is the monte-carlo simulation variation control. 34 | ** 35 | ** 36 | ** ------------------------------------------- 37 | ** Flicker noise corner setting: 38 | ** ------------------------------------------- 39 | ** 40 | ** "fnoicor" switch is added for user to select between the best- or worst-case 41 | ** flicker noise simulation options 42 | ** fnoicor = 0 : (default) as-extracted simulation 43 | ** fnoicor = 1 : worst case simulation 44 | ** 45 | ** ***************************************************************************** 46 | ** 47 | ** Switches 48 | ** 49 | *********** Default mc switches ********** 50 | ** 51 | .param 52 | + sw_stat_global = 0 53 | + sw_stat_mismatch = 0 54 | ** 55 | ********* Default mc skew value ********* 56 | ** 57 | + mc_skew = 3 58 | + res_mc_skew = 3 59 | + cap_mc_skew = 3 60 | ** 61 | ****** Default flicker noise corner switch ***** 62 | ** 63 | + fnoicor = 0 64 | ******************************************************************************** 65 | -------------------------------------------------------------------------------- /libraries/symbols/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /libraries/symbols/xschem/nfet.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.1.0 file_version=1.2 2 | 3 | } 4 | G {} 5 | K {type=nmos 6 | format="@spiceprefix@name @pinlist @model L=@L W=@W 7 | + nf=@nf ad=@ad as=@as pd=@pd ps=@ps 8 | + nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd 9 | + m=@m" 10 | lvs_format="@name @pinlist @model L=@L W=@W nf=@nf m=@m" 11 | template="name=M1 12 | L=0.030u 13 | W=0.0.036u 14 | nf=1 15 | m=1 16 | ad=\\"'int((nf+1)/2) * W/nf * 0.028u'\\" 17 | pd=\\"'2*int((nf+1)/2) * (W/nf + 0.028u)'\\" 18 | as=\\"'int((nf+2)/2) * W/nf * 0.028u'\\" 19 | ps=\\"'2*int((nf+2)/2) * (W/nf + 0.028u)'\\" 20 | nrd=\\"'0.18u / W'\\" nrs=\\"'0.028u / W'\\" 21 | sa=0 sb=0 sd=0 22 | model=nfet_03v3 23 | spiceprefix=X 24 | " 25 | } 26 | V {} 27 | S {} 28 | E {} 29 | L 4 7.5 -22.5 7.5 22.5 {} 30 | L 4 -20 0 2.5 0 {} 31 | L 4 20 -30 20 -17.5 {} 32 | L 4 20 17.5 20 30 {} 33 | L 4 2.5 -15 2.5 15 {} 34 | L 4 7.5 -17.5 20 -17.5 {} 35 | L 4 7.5 17.5 15 17.5 {} 36 | B 5 17.5 -32.5 22.5 -27.5 {name=D dir=inout} 37 | B 5 -22.5 -2.5 -17.5 2.5 {name=G dir=in} 38 | B 5 17.5 27.5 22.5 32.5 {name=S dir=inout} 39 | B 5 19.921875 -0.078125 20.078125 0.078125 {name=B dir=in} 40 | P 4 4 15 15 20 17.5 15 20 15 15 {fill=true} 41 | P 5 4 20 -2.5 15 0 20 2.5 20 -2.5 {fill=true} 42 | T {@spiceprefix@name} 5 -30 0 1 0.2 0.2 {} 43 | T {S} 22.5 17.5 0 0 0.15 0.15 {layer=7} 44 | T {D} 22.5 -17.5 2 1 0.15 0.15 {layer=7} 45 | T {B} 20 -10 0 0 0.15 0.15 {layer=7} 46 | T {G} -10 -10 0 1 0.15 0.15 {layer=7} 47 | T {@model} 30 -8.75 2 1 0.2 0.2 {} 48 | T {@m x @W / @L} 31.25 13.75 0 0 0.2 0.2 { layer=13} 49 | T {nf=@nf} 31.25 1.25 0 0 0.2 0.2 { layer=13} 50 | T {tcleval(gm=[ngspice::get_node [subst -nocommand \{\\@m.$\{path\}@spiceprefix@name\\.msky130_fd_pr__@model\\[gm]\}]] )} 32.5 -7.5 0 0 0.15 0.15 {layer=15 51 | hide=true} 52 | T {tcleval(id=[ngspice::get_node [subst -nocommand \{i(\\@m.$\{path\}@spiceprefix@name\\.msky130_fd_pr__@model\\[id])\}]] )} 32.5 -30 0 0 0.15 0.15 {layer=15 53 | hide=true} 54 | -------------------------------------------------------------------------------- /libraries/symbols/xschem/pfet.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.1.0 file_version=1.2 2 | 3 | } 4 | G {} 5 | K {type=pmos 6 | format="@spiceprefix@name @pinlist @model L=@L W=@W 7 | + nf=@nf ad=@ad as=@as pd=@pd ps=@ps 8 | + nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd 9 | + m=@m" 10 | lvs_format="@name @pinlist @model L=@L W=@W nf=@nf m=@m" 11 | template="name=M1 12 | L=0.030u 13 | W=0.036u 14 | nf=1 15 | m=1 16 | ad=\\"'int((nf+1)/2) * W/nf * 0.028u'\\" 17 | pd=\\"'2*int((nf+1)/2) * (W/nf + 0.028u)'\\" 18 | as=\\"'int((nf+2)/2) * W/nf * 0.028u'\\" 19 | ps=\\"'2*int((nf+2)/2) * (W/nf + 0.028u)'\\" 20 | nrd=\\"'0.18u / W'\\" nrs=\\"'0.028u / W'\\" 21 | sa=0 sb=0 sd=0 22 | model=pfet_03v3 23 | spiceprefix=X 24 | " 25 | } 26 | V {} 27 | S {} 28 | E {} 29 | L 4 7.5 -22.5 7.5 22.5 {} 30 | L 4 20 -30 20 -17.5 {} 31 | L 4 20 17.5 20 30 {} 32 | L 4 2.5 -15 2.5 15 {} 33 | L 4 7.5 17.5 20 17.5 {} 34 | L 4 12.5 -17.5 20 -17.5 {} 35 | L 4 -20 0 -7.5 0 {} 36 | B 5 17.5 27.5 22.5 32.5 {name=D dir=inout} 37 | B 5 -22.5 -2.5 -17.5 2.5 {name=G dir=in} 38 | B 5 17.5 -32.5 22.5 -27.5 {name=S dir=inout} 39 | B 5 19.921875 -0.078125 20.078125 0.078125 {name=B dir=in} 40 | A 4 -2.5 0 5 180 360 {} 41 | P 4 4 12.5 -20 7.5 -17.5 12.5 -15 12.5 -20 {fill=true} 42 | P 5 4 15 -2.5 20 0 15 2.5 15 -2.5 {fill=true} 43 | T {D} 22.5 17.5 0 0 0.15 0.15 {layer=7} 44 | T {S} 22.5 -17.5 2 1 0.15 0.15 {layer=7} 45 | T {B} 20 -10 0 0 0.15 0.15 {layer=7} 46 | T {G} -10 -10 0 1 0.15 0.15 {layer=7} 47 | T {@model} 30 -8.75 2 1 0.2 0.2 {} 48 | T {@m x @W / @L} 31.25 13.75 0 0 0.2 0.2 { layer=13} 49 | T {nf=@nf} 31.25 1.25 0 0 0.2 0.2 { layer=13} 50 | T {tcleval(gm=[ngspice::get_node [subst -nocommand \{\\@m.$\{path\}@spiceprefix@name\\.msky130_fd_pr__@model\\[gm]\}]] )} 32.5 -7.5 0 0 0.15 0.15 {layer=15 51 | hide=true} 52 | T {tcleval(id=[ngspice::get_node [subst -nocommand \{i(\\@m.$\{path\}@spiceprefix@name\\.msky130_fd_pr__@model\\[id])\}]] )} 32.5 -30 0 0 0.15 0.15 {layer=15 53 | hide=true} 54 | T {@spiceprefix@name} 5 -30 0 1 0.2 0.2 {} 55 | -------------------------------------------------------------------------------- /libraries/tech/klayout/openrpdk28,map: -------------------------------------------------------------------------------- 1 | Via1 VIA 35 0 2 | Via2 VIA 38 0 3 | Via3 VIA 40 0 4 | Via4 VIA 41 0 5 | Via5 VIA 82 0 6 | 7 | Metal1 NET,SPNET,PIN,VIA 34 0 8 | NAME Metal1/LABEL 34 10 9 | Metal1 PIN 34 10 10 | 11 | Metal2 NET,SPNET,PIN,VIA 36 0 12 | NAME Metal2/LABEL 36 10 13 | Metal2 PIN 36 10 14 | 15 | Metal3 NET,SPNET,PIN,VIA 42 0 16 | NAME Metal3/LABEL 42 10 17 | Metal3 PIN 42 10 18 | 19 | Metal4 NET,SPNET,PIN,VIA 46 0 20 | NAME Metal4/LABEL 46 10 21 | Metal4 PIN 46 10 22 | 23 | Metal5 NET,SPNET,PIN,VIA 81 0 24 | NAME Metal5/LABEL 81 10 25 | Metal5 PIN 81 10 26 | 27 | DIEAREA ALL 0 0 28 | -------------------------------------------------------------------------------- /libraries/tech/klayout/openrpdk28.lyp: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | 7 | #55ce57 8 | #55ce57 9 | 0 10 | 0 11 | I3 12 | 13 | true 14 | false 15 | false 16 | 1 17 | false 18 | false 19 | 0 20 | 21 | 1/222@1 22 | 23 | 24 | #661a48 25 | #661a48 26 | 0 27 | 0 28 | I3 29 | 30 | true 31 | false 32 | false 33 | 1 34 | false 35 | false 36 | 0 37 | 38 | pass_mk 2/222@1 39 | 40 | 41 | #7c6078 42 | #7c6078 43 | 0 44 | 0 45 | I3 46 | 47 | true 48 | false 49 | false 50 | 1 51 | false 52 | false 53 | 0 54 | 55 | fail_mk 3/222@1 56 | 57 | 58 | #f26f6c 59 | #f26f6c 60 | 0 61 | 0 62 | I3 63 | 64 | true 65 | false 66 | false 67 | 1 68 | false 69 | false 70 | 0 71 | 72 | polygon_mk 4/222@1 73 | 74 | 75 | #324416 76 | #324416 77 | 0 78 | 0 79 | I3 80 | 81 | true 82 | false 83 | false 84 | 1 85 | false 86 | false 87 | 0 88 | 89 | 5/222@1 90 | 91 | 92 | #3acb88 93 | #3acb88 94 | 0 95 | 0 96 | I3 97 | 98 | true 99 | false 100 | false 101 | 1 102 | false 103 | false 104 | 0 105 | 106 | violation_mk 6/222@1 107 | 108 | 109 | #5a68c2 110 | #5a68c2 111 | 0 112 | 0 113 | I3 114 | 115 | true 116 | false 117 | false 118 | 1 119 | false 120 | false 121 | 0 122 | 123 | rule_txt_mk 11/222@1 124 | 125 | 126 | #718e2d 127 | #718e2d 128 | 0 129 | 0 130 | I3 131 | 132 | true 133 | false 134 | false 135 | 1 136 | false 137 | false 138 | 0 139 | 140 | 12/222@1 141 | 142 | 143 | #3f3f3c 144 | #3f3f3c 145 | 0 146 | 0 147 | I3 148 | 149 | true 150 | false 151 | false 152 | 1 153 | false 154 | false 155 | 0 156 | 157 | case_txt_mk 13/222@1 158 | 159 | 160 | #3f12e4 161 | #3f12e4 162 | 0 163 | 0 164 | I3 165 | 166 | true 167 | false 168 | false 169 | 1 170 | false 171 | false 172 | 0 173 | 174 | 14/222@1 175 | 176 | 177 | #f9bd46 178 | #f9bd46 179 | 0 180 | 0 181 | I3 182 | 183 | true 184 | false 185 | false 186 | 1 187 | false 188 | false 189 | 0 190 | 191 | 15/222@1 192 | 193 | 194 | #bd74bd 195 | #bd74bd 196 | 0 197 | 0 198 | I5 199 | 200 | true 201 | true 202 | false 203 | 1 204 | false 205 | false 206 | 0 207 | 208 | COMP 22/0@1 209 | 210 | 211 | #88cb1d 212 | #88cb1d 213 | 0 214 | 0 215 | I9 216 | 217 | true 218 | true 219 | false 220 | 1 221 | false 222 | false 223 | 0 224 | 225 | DNWELL 12/0@1 226 | 227 | 228 | #f9946b 229 | #f9946b 230 | 0 231 | 0 232 | I5 233 | 234 | true 235 | true 236 | false 237 | 1 238 | false 239 | false 240 | 0 241 | 242 | Nwell 21/0@1 243 | 244 | 245 | #3a2888 246 | #3a2888 247 | 0 248 | 0 249 | I9 250 | 251 | true 252 | true 253 | false 254 | 1 255 | false 256 | false 257 | 0 258 | 259 | LVPWELL 204/0@1 260 | 261 | 262 | #c16f5c 263 | #c16f5c 264 | 0 265 | 0 266 | I5 267 | 268 | true 269 | true 270 | false 271 | 1 272 | false 273 | false 274 | 0 275 | 276 | Dualgate 55/0@1 277 | 278 | 279 | #2e9521 280 | #2e9521 281 | 0 282 | 0 283 | I9 284 | 285 | true 286 | true 287 | false 288 | 1 289 | false 290 | false 291 | 0 292 | 293 | Poly2 30/0@1 294 | 295 | 296 | #bf3efb 297 | #bf3efb 298 | 0 299 | 0 300 | I5 301 | 302 | true 303 | true 304 | false 305 | 1 306 | false 307 | false 308 | 0 309 | 310 | Nplus 32/0@1 311 | 312 | 313 | #34c590 314 | #34c590 315 | 0 316 | 0 317 | I9 318 | 319 | true 320 | true 321 | false 322 | 1 323 | false 324 | false 325 | 0 326 | 327 | Pplus 31/0@1 328 | 329 | 330 | #67392f 331 | #67392f 332 | 0 333 | 0 334 | I5 335 | 336 | true 337 | true 338 | false 339 | 1 340 | false 341 | false 342 | 0 343 | 344 | SAB 49/0@1 345 | 346 | 347 | #d9ef03 348 | #d9ef03 349 | 0 350 | 0 351 | I9 352 | 353 | true 354 | true 355 | false 356 | 1 357 | false 358 | false 359 | 0 360 | 361 | ESD 24/0@1 362 | 363 | 364 | #c86634 365 | #c86634 366 | 0 367 | 0 368 | I5 369 | 370 | true 371 | true 372 | false 373 | 1 374 | false 375 | false 376 | 0 377 | 378 | Contact 33/0@1 379 | 380 | 381 | #eddd07 382 | #eddd07 383 | 0 384 | 0 385 | I9 386 | 387 | true 388 | true 389 | false 390 | 1 391 | false 392 | false 393 | 0 394 | 395 | Metal1 34/0@1 396 | 397 | 398 | #f5e7f1 399 | #f5e7f1 400 | 0 401 | 0 402 | I5 403 | 404 | true 405 | true 406 | false 407 | 1 408 | false 409 | false 410 | 0 411 | 412 | Via1 35/0@1 413 | 414 | 415 | #ccf338 416 | #ccf338 417 | 0 418 | 0 419 | I9 420 | 421 | true 422 | true 423 | false 424 | 1 425 | false 426 | false 427 | 0 428 | 429 | Metal2 36/0@1 430 | 431 | 432 | #e1d8ca 433 | #e1d8ca 434 | 0 435 | 0 436 | I5 437 | 438 | true 439 | true 440 | false 441 | 1 442 | false 443 | false 444 | 0 445 | 446 | Via2 38/0@1 447 | 448 | 449 | #97b91b 450 | #97b91b 451 | 0 452 | 0 453 | I9 454 | 455 | true 456 | true 457 | false 458 | 1 459 | false 460 | false 461 | 0 462 | 463 | Metal3 42/0@1 464 | 465 | 466 | #53e2e8 467 | #53e2e8 468 | 0 469 | 0 470 | I5 471 | 472 | true 473 | true 474 | false 475 | 1 476 | false 477 | false 478 | 0 479 | 480 | Via3 40/0@1 481 | 482 | 483 | #80317c 484 | #80317c 485 | 0 486 | 0 487 | I9 488 | 489 | true 490 | true 491 | false 492 | 1 493 | false 494 | false 495 | 0 496 | 497 | Metal4 46/0@1 498 | 499 | 500 | #a7b1d1 501 | #a7b1d1 502 | 0 503 | 0 504 | I5 505 | 506 | true 507 | true 508 | false 509 | 1 510 | false 511 | false 512 | 0 513 | 514 | Via4 41/0@1 515 | 516 | 517 | #cdc16b 518 | #cdc16b 519 | 0 520 | 0 521 | I9 522 | 523 | true 524 | true 525 | false 526 | 1 527 | false 528 | false 529 | 0 530 | 531 | Metal5 81/0@1 532 | 533 | 534 | #827e5b 535 | #827e5b 536 | 0 537 | 0 538 | I5 539 | 540 | true 541 | true 542 | false 543 | 1 544 | false 545 | false 546 | 0 547 | 548 | Via5 82/0@1 549 | 550 | 551 | #b1dd9c 552 | #b1dd9c 553 | 0 554 | 0 555 | I9 556 | 557 | true 558 | true 559 | false 560 | 1 561 | false 562 | false 563 | 0 564 | 565 | MetalTop 53/0@1 566 | 567 | 568 | #72342b 569 | #72342b 570 | 0 571 | 0 572 | I5 573 | 574 | true 575 | true 576 | false 577 | 1 578 | false 579 | false 580 | 0 581 | 582 | Pad 37/0@1 583 | 584 | 585 | #1437ff 586 | #1437ff 587 | 0 588 | 0 589 | I9 590 | 591 | true 592 | true 593 | false 594 | 1 595 | false 596 | false 597 | 0 598 | 599 | Resistor 62/0@1 600 | 601 | 602 | #82b18c 603 | #82b18c 604 | 0 605 | 0 606 | I5 607 | 608 | true 609 | true 610 | false 611 | 1 612 | false 613 | false 614 | 0 615 | 616 | FHRES 227/0@1 617 | 618 | 619 | #b9a4fd 620 | #b9a4fd 621 | 0 622 | 0 623 | I9 624 | 625 | true 626 | true 627 | false 628 | 1 629 | false 630 | false 631 | 0 632 | 633 | FuseTop 75/0@1 634 | 635 | 636 | #87ad41 637 | #87ad41 638 | 0 639 | 0 640 | I5 641 | 642 | true 643 | true 644 | false 645 | 1 646 | false 647 | false 648 | 0 649 | 650 | FuseWindow_D 96/1@1 651 | 652 | 653 | #ec7ceb 654 | #ec7ceb 655 | 0 656 | 0 657 | I9 658 | 659 | true 660 | true 661 | false 662 | 1 663 | false 664 | false 665 | 0 666 | 667 | POLYFUSE 220/0@1 668 | 669 | 670 | #e29901 671 | #e29901 672 | 0 673 | 0 674 | I5 675 | 676 | true 677 | true 678 | false 679 | 1 680 | false 681 | false 682 | 0 683 | 684 | MVSD 210/0@1 685 | 686 | 687 | #63a2db 688 | #63a2db 689 | 0 690 | 0 691 | I9 692 | 693 | true 694 | true 695 | false 696 | 1 697 | false 698 | false 699 | 0 700 | 701 | MVPSD 11/39@1 702 | 703 | 704 | #91d339 705 | #91d339 706 | 0 707 | 0 708 | I5 709 | 710 | true 711 | true 712 | false 713 | 1 714 | false 715 | false 716 | 0 717 | 718 | NAT 5/0@1 719 | 720 | 721 | #f84e38 722 | #f84e38 723 | 0 724 | 0 725 | I9 726 | 727 | true 728 | true 729 | false 730 | 1 731 | false 732 | false 733 | 0 734 | 735 | COMP_Dummy 22/4@1 736 | 737 | 738 | #2d4da8 739 | #2d4da8 740 | 0 741 | 0 742 | I5 743 | 744 | true 745 | true 746 | false 747 | 1 748 | false 749 | false 750 | 0 751 | 752 | Poly2_Dummy 30/4@1 753 | 754 | 755 | #c01202 756 | #c01202 757 | 0 758 | 0 759 | I9 760 | 761 | true 762 | true 763 | false 764 | 1 765 | false 766 | false 767 | 0 768 | 769 | Metal1_Dummy 34/4@1 770 | 771 | 772 | #2f93c0 773 | #2f93c0 774 | 0 775 | 0 776 | I5 777 | 778 | true 779 | true 780 | false 781 | 1 782 | false 783 | false 784 | 0 785 | 786 | Metal2_Dummy 36/4@1 787 | 788 | 789 | #867300 790 | #867300 791 | 0 792 | 0 793 | I9 794 | 795 | true 796 | true 797 | false 798 | 1 799 | false 800 | false 801 | 0 802 | 803 | Metal3_Dummy 42/4@1 804 | 805 | 806 | #e86c70 807 | #e86c70 808 | 0 809 | 0 810 | I5 811 | 812 | true 813 | true 814 | false 815 | 1 816 | false 817 | false 818 | 0 819 | 820 | Metal4_Dummy 46/4@1 821 | 822 | 823 | #26676b 824 | #26676b 825 | 0 826 | 0 827 | I9 828 | 829 | true 830 | true 831 | false 832 | 1 833 | false 834 | false 835 | 0 836 | 837 | Metal5_Dummy 81/4@1 838 | 839 | 840 | #60fe08 841 | #60fe08 842 | 0 843 | 0 844 | I5 845 | 846 | true 847 | true 848 | false 849 | 1 850 | false 851 | false 852 | 0 853 | 854 | MetalTop_Dummy 53/4@1 855 | 856 | 857 | #4665c7 858 | #4665c7 859 | 0 860 | 0 861 | I9 862 | 863 | true 864 | true 865 | false 866 | 1 867 | false 868 | false 869 | 0 870 | 871 | COMP_Label 22/10@1 872 | 873 | 874 | #fb1879 875 | #fb1879 876 | 0 877 | 0 878 | I5 879 | 880 | true 881 | true 882 | false 883 | 1 884 | false 885 | false 886 | 0 887 | 888 | Poly2_Label 30/10@1 889 | 890 | 891 | #880f5b 892 | #880f5b 893 | 0 894 | 0 895 | I9 896 | 897 | true 898 | false 899 | false 900 | 1 901 | false 902 | false 903 | 0 904 | 905 | Metal1_Label 34/10@1 906 | 907 | 908 | #ff80b7 909 | #ff80b7 910 | 0 911 | 0 912 | I5 913 | 914 | true 915 | false 916 | false 917 | 1 918 | false 919 | false 920 | 0 921 | 922 | Metal2_Label 36/10@1 923 | 924 | 925 | #ad9348 926 | #ad9348 927 | 0 928 | 0 929 | I9 930 | 931 | true 932 | false 933 | false 934 | 1 935 | false 936 | false 937 | 0 938 | 939 | Metal3_Label 42/10@1 940 | 941 | 942 | #876bbe 943 | #876bbe 944 | 0 945 | 0 946 | I5 947 | 948 | true 949 | false 950 | false 951 | 1 952 | false 953 | false 954 | 0 955 | 956 | Metal4_Label 46/10@1 957 | 958 | 959 | #43e12f 960 | #43e12f 961 | 0 962 | 0 963 | I9 964 | 965 | true 966 | false 967 | false 968 | 1 969 | false 970 | false 971 | 0 972 | 973 | Metal5_Label 81/10@1 974 | 975 | 976 | #a6ec0e 977 | #a6ec0e 978 | 0 979 | 0 980 | I5 981 | 982 | true 983 | true 984 | false 985 | 1 986 | false 987 | false 988 | 0 989 | 990 | MetalTop_Label 53/10@1 991 | 992 | 993 | #271fe3 994 | #271fe3 995 | 0 996 | 0 997 | I9 998 | 999 | true 1000 | true 1001 | false 1002 | 1 1003 | false 1004 | false 1005 | 0 1006 | 1007 | Metal1_Slot 34/3@1 1008 | 1009 | 1010 | #d56ff8 1011 | #d56ff8 1012 | 0 1013 | 0 1014 | I5 1015 | 1016 | true 1017 | true 1018 | false 1019 | 1 1020 | false 1021 | false 1022 | 0 1023 | 1024 | Metal2_Slot 36/3@1 1025 | 1026 | 1027 | #d8c178 1028 | #d8c178 1029 | 0 1030 | 0 1031 | I9 1032 | 1033 | true 1034 | true 1035 | false 1036 | 1 1037 | false 1038 | false 1039 | 0 1040 | 1041 | Metal3_Slot 42/3@1 1042 | 1043 | 1044 | #6c36fb 1045 | #6c36fb 1046 | 0 1047 | 0 1048 | I5 1049 | 1050 | true 1051 | true 1052 | false 1053 | 1 1054 | false 1055 | false 1056 | 0 1057 | 1058 | Metal4_Slot 46/3@1 1059 | 1060 | 1061 | #225c09 1062 | #225c09 1063 | 0 1064 | 0 1065 | I9 1066 | 1067 | true 1068 | true 1069 | false 1070 | 1 1071 | false 1072 | false 1073 | 0 1074 | 1075 | Metal5_Slot 81/3@1 1076 | 1077 | 1078 | #03f979 1079 | #03f979 1080 | 0 1081 | 0 1082 | I5 1083 | 1084 | true 1085 | true 1086 | false 1087 | 1 1088 | false 1089 | false 1090 | 0 1091 | 1092 | MetalTop_Slot 53/3@1 1093 | 1094 | 1095 | #6c9be2 1096 | #6c9be2 1097 | 0 1098 | 0 1099 | I9 1100 | 1101 | true 1102 | true 1103 | false 1104 | 1 1105 | false 1106 | false 1107 | 0 1108 | 1109 | UBMPPeri 183/0@1 1110 | 1111 | 1112 | #0174b8 1113 | #0174b8 1114 | 0 1115 | 0 1116 | I5 1117 | 1118 | true 1119 | true 1120 | false 1121 | 1 1122 | false 1123 | false 1124 | 0 1125 | 1126 | UBMPArray 184/0@1 1127 | 1128 | 1129 | #5bdc70 1130 | #5bdc70 1131 | 0 1132 | 0 1133 | I9 1134 | 1135 | true 1136 | true 1137 | false 1138 | 1 1139 | false 1140 | false 1141 | 0 1142 | 1143 | UBMEPlate 185/0@1 1144 | 1145 | 1146 | #94d628 1147 | #94d628 1148 | 0 1149 | 0 1150 | I5 1151 | 1152 | true 1153 | true 1154 | false 1155 | 1 1156 | false 1157 | false 1158 | 0 1159 | 1160 | Schottky_diode 241/0@1 1161 | 1162 | 1163 | #5660ce 1164 | #5660ce 1165 | 0 1166 | 0 1167 | I9 1168 | 1169 | true 1170 | true 1171 | false 1172 | 1 1173 | false 1174 | false 1175 | 0 1176 | 1177 | ZENER 178/0@1 1178 | 1179 | 1180 | #4a0c51 1181 | #4a0c51 1182 | 0 1183 | 0 1184 | I5 1185 | 1186 | true 1187 | true 1188 | false 1189 | 1 1190 | false 1191 | false 1192 | 0 1193 | 1194 | RES_MK 110/5@1 1195 | 1196 | 1197 | #84fd79 1198 | #84fd79 1199 | 0 1200 | 0 1201 | I9 1202 | 1203 | true 1204 | true 1205 | false 1206 | 1 1207 | false 1208 | false 1209 | 0 1210 | 1211 | OPC_drc 124/5@1 1212 | 1213 | 1214 | #49ee98 1215 | #49ee98 1216 | 0 1217 | 0 1218 | I5 1219 | 1220 | true 1221 | true 1222 | false 1223 | 1 1224 | false 1225 | false 1226 | 0 1227 | 1228 | NDMY 111/5@1 1229 | 1230 | 1231 | #0c7e5b 1232 | #0c7e5b 1233 | 0 1234 | 0 1235 | I9 1236 | 1237 | true 1238 | true 1239 | false 1240 | 1 1241 | false 1242 | false 1243 | 0 1244 | 1245 | PMNDMY 152/5@1 1246 | 1247 | 1248 | #49b403 1249 | #49b403 1250 | 0 1251 | 0 1252 | I5 1253 | 1254 | true 1255 | true 1256 | false 1257 | 1 1258 | false 1259 | false 1260 | 0 1261 | 1262 | V5_XTOR 112/1@1 1263 | 1264 | 1265 | #2522b7 1266 | #2522b7 1267 | 0 1268 | 0 1269 | I9 1270 | 1271 | true 1272 | true 1273 | false 1274 | 1 1275 | false 1276 | false 1277 | 0 1278 | 1279 | CAP_MK 117/5@1 1280 | 1281 | 1282 | #0c5e62 1283 | #0c5e62 1284 | 0 1285 | 0 1286 | I5 1287 | 1288 | true 1289 | true 1290 | false 1291 | 1 1292 | false 1293 | false 1294 | 0 1295 | 1296 | MOS_CAP_MK 166/5@1 1297 | 1298 | 1299 | #99ac7e 1300 | #99ac7e 1301 | 0 1302 | 0 1303 | I9 1304 | 1305 | true 1306 | true 1307 | false 1308 | 1 1309 | false 1310 | false 1311 | 0 1312 | 1313 | IND_MK 151/5@1 1314 | 1315 | 1316 | #9f0f89 1317 | #9f0f89 1318 | 0 1319 | 0 1320 | I5 1321 | 1322 | true 1323 | true 1324 | false 1325 | 1 1326 | false 1327 | false 1328 | 0 1329 | 1330 | DIODE_MK 115/5@1 1331 | 1332 | 1333 | #04507b 1334 | #04507b 1335 | 0 1336 | 0 1337 | I9 1338 | 1339 | true 1340 | true 1341 | false 1342 | 1 1343 | false 1344 | false 1345 | 0 1346 | 1347 | DRC_BJT 127/5@1 1348 | 1349 | 1350 | #0e7575 1351 | #0e7575 1352 | 0 1353 | 0 1354 | I5 1355 | 1356 | true 1357 | true 1358 | false 1359 | 1 1360 | false 1361 | false 1362 | 0 1363 | 1364 | LVS_BJT 118/5@1 1365 | 1366 | 1367 | #f6b1ef 1368 | #f6b1ef 1369 | 0 1370 | 0 1371 | I9 1372 | 1373 | true 1374 | true 1375 | false 1376 | 1 1377 | false 1378 | false 1379 | 0 1380 | 1381 | MIM_L_MK 117/10@1 1382 | 1383 | 1384 | #10c9d8 1385 | #10c9d8 1386 | 0 1387 | 0 1388 | I5 1389 | 1390 | true 1391 | true 1392 | false 1393 | 1 1394 | false 1395 | false 1396 | 0 1397 | 1398 | Latchup_MK 137/5@1 1399 | 1400 | 1401 | #79d94d 1402 | #79d94d 1403 | 0 1404 | 0 1405 | I9 1406 | 1407 | true 1408 | true 1409 | false 1410 | 1 1411 | false 1412 | false 1413 | 0 1414 | 1415 | GUARD_RING_MK 167/5@1 1416 | 1417 | 1418 | #2aa0fb 1419 | #2aa0fb 1420 | 0 1421 | 0 1422 | I5 1423 | 1424 | true 1425 | true 1426 | false 1427 | 1 1428 | false 1429 | false 1430 | 0 1431 | 1432 | OTP_MK 173/5@1 1433 | 1434 | 1435 | #7b407b 1436 | #7b407b 1437 | 0 1438 | 0 1439 | I9 1440 | 1441 | true 1442 | true 1443 | false 1444 | 1 1445 | false 1446 | false 1447 | 0 1448 | 1449 | MTPMARK 122/5@1 1450 | 1451 | 1452 | #f894c4 1453 | #f894c4 1454 | 0 1455 | 0 1456 | I5 1457 | 1458 | true 1459 | true 1460 | false 1461 | 1 1462 | false 1463 | false 1464 | 0 1465 | 1466 | NEO_EE_MK 88/17@1 1467 | 1468 | 1469 | #d69c01 1470 | #d69c01 1471 | 0 1472 | 0 1473 | I9 1474 | 1475 | true 1476 | true 1477 | false 1478 | 1 1479 | false 1480 | false 1481 | 0 1482 | 1483 | SramCore 108/5@1 1484 | 1485 | 1486 | #c80a86 1487 | #c80a86 1488 | 0 1489 | 0 1490 | I5 1491 | 1492 | true 1493 | true 1494 | false 1495 | 1 1496 | false 1497 | false 1498 | 0 1499 | 1500 | LVS_RF 100/5@1 1501 | 1502 | 1503 | #fa898a 1504 | #fa898a 1505 | 0 1506 | 0 1507 | I9 1508 | 1509 | true 1510 | true 1511 | false 1512 | 1 1513 | false 1514 | false 1515 | 0 1516 | 1517 | LVS_Drain 100/7@1 1518 | 1519 | 1520 | #5a305a 1521 | #5a305a 1522 | 0 1523 | 0 1524 | I5 1525 | 1526 | true 1527 | true 1528 | false 1529 | 1 1530 | false 1531 | false 1532 | 0 1533 | 1534 | IND_MK 151/5@1 1535 | 1536 | 1537 | #c2bf6d 1538 | #c2bf6d 1539 | 0 1540 | 0 1541 | I9 1542 | 1543 | true 1544 | true 1545 | false 1546 | 1 1547 | false 1548 | false 1549 | 0 1550 | 1551 | HVPOLYRS 123/5@1 1552 | 1553 | 1554 | #9f3b8a 1555 | #9f3b8a 1556 | 0 1557 | 0 1558 | I5 1559 | 1560 | true 1561 | true 1562 | false 1563 | 1 1564 | false 1565 | false 1566 | 0 1567 | 1568 | LVS_IO 119/5@1 1569 | 1570 | 1571 | #5aac8a 1572 | #5aac8a 1573 | 0 1574 | 0 1575 | I9 1576 | 1577 | true 1578 | true 1579 | false 1580 | 1 1581 | false 1582 | false 1583 | 0 1584 | 1585 | PROBE_MK 13/17@1 1586 | 1587 | 1588 | #5de533 1589 | #5de533 1590 | 0 1591 | 0 1592 | I5 1593 | 1594 | true 1595 | true 1596 | false 1597 | 1 1598 | false 1599 | false 1600 | 0 1601 | 1602 | ESD_MK 24/5@1 1603 | 1604 | 1605 | #b654a3 1606 | #b654a3 1607 | 0 1608 | 0 1609 | I9 1610 | 1611 | true 1612 | true 1613 | false 1614 | 1 1615 | false 1616 | false 1617 | 0 1618 | 1619 | LVS_Source 100/8@1 1620 | 1621 | 1622 | #9beaaf 1623 | #9beaaf 1624 | 0 1625 | 0 1626 | I5 1627 | 1628 | true 1629 | true 1630 | false 1631 | 1 1632 | false 1633 | false 1634 | 0 1635 | 1636 | WELL_DIODE_MK 153/51@1 1637 | 1638 | 1639 | #b0eb32 1640 | #b0eb32 1641 | 0 1642 | 0 1643 | I9 1644 | 1645 | true 1646 | true 1647 | false 1648 | 1 1649 | false 1650 | false 1651 | 0 1652 | 1653 | LDMOS_XTOR 226/0@1 1654 | 1655 | 1656 | #2507df 1657 | #2507df 1658 | 0 1659 | 0 1660 | I5 1661 | 1662 | true 1663 | true 1664 | false 1665 | 1 1666 | false 1667 | false 1668 | 0 1669 | 1670 | PLFUSE 125/5@1 1671 | 1672 | 1673 | #7791b3 1674 | #7791b3 1675 | 0 1676 | 0 1677 | I9 1678 | 1679 | true 1680 | true 1681 | false 1682 | 1 1683 | false 1684 | false 1685 | 0 1686 | 1687 | EFUSE_MK 80/5@1 1688 | 1689 | 1690 | #ac9801 1691 | #ac9801 1692 | 0 1693 | 0 1694 | I5 1695 | 1696 | true 1697 | true 1698 | false 1699 | 1 1700 | false 1701 | false 1702 | 0 1703 | 1704 | MCELL_FEOL_MK 11/17@1 1705 | 1706 | 1707 | #ae438e 1708 | #ae438e 1709 | 0 1710 | 0 1711 | I9 1712 | 1713 | true 1714 | true 1715 | false 1716 | 1 1717 | false 1718 | false 1719 | 0 1720 | 1721 | YMTP_MK 86/17@1 1722 | 1723 | 1724 | #5779b7 1725 | #5779b7 1726 | 0 1727 | 0 1728 | I5 1729 | 1730 | true 1731 | true 1732 | false 1733 | 1 1734 | false 1735 | false 1736 | 0 1737 | 1738 | DEV_WF_MK 128/17@1 1739 | 1740 | 1741 | #8e3415 1742 | #8e3415 1743 | 0 1744 | 0 1745 | I9 1746 | 1747 | true 1748 | true 1749 | false 1750 | 1 1751 | false 1752 | false 1753 | 0 1754 | 1755 | Metal1_BLK 34/5@1 1756 | 1757 | 1758 | #47649f 1759 | #47649f 1760 | 0 1761 | 0 1762 | I5 1763 | 1764 | true 1765 | true 1766 | false 1767 | 1 1768 | false 1769 | false 1770 | 0 1771 | 1772 | Metal2_BLK 36/5@1 1773 | 1774 | 1775 | #3bf37a 1776 | #3bf37a 1777 | 0 1778 | 0 1779 | I9 1780 | 1781 | true 1782 | true 1783 | false 1784 | 1 1785 | false 1786 | false 1787 | 0 1788 | 1789 | Metal3_BLK 42/5@1 1790 | 1791 | 1792 | #678619 1793 | #678619 1794 | 0 1795 | 0 1796 | I5 1797 | 1798 | true 1799 | true 1800 | false 1801 | 1 1802 | false 1803 | false 1804 | 0 1805 | 1806 | Metal4_BLK 46/5@1 1807 | 1808 | 1809 | #44fa82 1810 | #44fa82 1811 | 0 1812 | 0 1813 | I9 1814 | 1815 | true 1816 | true 1817 | false 1818 | 1 1819 | false 1820 | false 1821 | 0 1822 | 1823 | Metal5_BLK 81/5@1 1824 | 1825 | 1826 | #614b6a 1827 | #614b6a 1828 | 0 1829 | 0 1830 | I5 1831 | 1832 | true 1833 | true 1834 | false 1835 | 1 1836 | false 1837 | false 1838 | 0 1839 | 1840 | MetalT_BLK 53/5@1 1841 | 1842 | 1843 | #d9f817 1844 | #d9f817 1845 | 0 1846 | 0 1847 | I9 1848 | 1849 | true 1850 | true 1851 | false 1852 | 1 1853 | false 1854 | false 1855 | 0 1856 | 1857 | PR_bndry 0/0@1 1858 | 1859 | 1860 | #0bdfb7 1861 | #0bdfb7 1862 | 0 1863 | 0 1864 | I5 1865 | 1866 | true 1867 | true 1868 | false 1869 | 1 1870 | false 1871 | false 1872 | 0 1873 | 1874 | MDIODE 116/5@1 1875 | 1876 | 1877 | #658af3 1878 | #658af3 1879 | 0 1880 | 0 1881 | I9 1882 | 1883 | true 1884 | true 1885 | false 1886 | 1 1887 | false 1888 | false 1889 | 0 1890 | 1891 | Metal1_Res 110/11@1 1892 | 1893 | 1894 | #e9465c 1895 | #e9465c 1896 | 0 1897 | 0 1898 | I5 1899 | 1900 | true 1901 | true 1902 | false 1903 | 1 1904 | false 1905 | false 1906 | 0 1907 | 1908 | Metal2_Res 110/12@1 1909 | 1910 | 1911 | #ba3263 1912 | #ba3263 1913 | 0 1914 | 0 1915 | I9 1916 | 1917 | true 1918 | true 1919 | false 1920 | 1 1921 | false 1922 | false 1923 | 0 1924 | 1925 | Metal3_Res 110/13@1 1926 | 1927 | 1928 | #ddeef3 1929 | #ddeef3 1930 | 0 1931 | 0 1932 | I5 1933 | 1934 | true 1935 | true 1936 | false 1937 | 1 1938 | false 1939 | false 1940 | 0 1941 | 1942 | Metal4_Res 110/14@1 1943 | 1944 | 1945 | #004676 1946 | #004676 1947 | 0 1948 | 0 1949 | I9 1950 | 1951 | true 1952 | true 1953 | false 1954 | 1 1955 | false 1956 | false 1957 | 0 1958 | 1959 | Metal5_Res 110/15@1 1960 | 1961 | 1962 | #e4b00d 1963 | #e4b00d 1964 | 0 1965 | 0 1966 | I5 1967 | 1968 | true 1969 | true 1970 | false 1971 | 1 1972 | false 1973 | false 1974 | 0 1975 | 1976 | Metal6_Res 110/16@1 1977 | 1978 | 1979 | #edeb06 1980 | #edeb06 1981 | 0 1982 | 0 1983 | I9 1984 | 1985 | true 1986 | true 1987 | false 1988 | 1 1989 | false 1990 | false 1991 | 0 1992 | 1993 | Border 63/0@1 1994 | 1995 | 1996 | 1997 | -------------------------------------------------------------------------------- /libraries/tech/klayout/openrpdk28.lyt: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | 28nm OpenRPDK 7 | 28nm OpenRPDK TECHNOLOGY 8 | 9 | 0.001 10 | 11 | $PDK_ROOT/$PDK/libs.tech/klayout 12 | openrpdk28.lyp 13 | true 14 | 15 | 16 | 1 17 | true 18 | true 19 | 20 | 21 | true 22 | layer_map() 23 | true 24 | true 25 | 26 | 27 | true 28 | layer_map() 29 | 0.001 30 | true 31 | #1 32 | true 33 | #1 34 | false 35 | #1 36 | true 37 | OUTLINE 38 | true 39 | PLACEMENT_BLK 40 | true 41 | REGIONS 42 | true 43 | 44 | 0 45 | true 46 | .PIN 47 | 2 48 | true 49 | .PIN 50 | 2 51 | true 52 | .FILL 53 | 5 54 | true 55 | .OBS 56 | 3 57 | true 58 | .BLK 59 | 4 60 | true 61 | .LABEL 62 | 1 63 | true 64 | .LABEL 65 | 1 66 | true 67 | 68 | 0 69 | true 70 | 71 | 0 72 | VIA_ 73 | true 74 | default 75 | false 76 | 77 | 78 | 79 | false 80 | true 81 | true 82 | 64 83 | 0 84 | 1 85 | 0 86 | DATA 87 | 0 88 | 0 89 | BORDER 90 | layer_map() 91 | true 92 | 93 | 94 | 0.001 95 | 1 96 | 100 97 | 100 98 | 0 99 | 0 100 | 0 101 | false 102 | false 103 | false 104 | true 105 | layer_map() 106 | 107 | 108 | 0 109 | 0.001 110 | layer_map() 111 | true 112 | false 113 | 114 | 115 | 1 116 | 0.001 117 | layer_map() 118 | true 119 | false 120 | true 121 | 122 | 123 | 124 | 125 | 126 | 127 | true 128 | false 129 | false 130 | false 131 | false 132 | false 133 | 8000 134 | 32000 135 | LIB 136 | 137 | 138 | 2 139 | false 140 | false 141 | 1 142 | * 143 | false 144 | 145 | 146 | 0 147 | 148 | 149 | false 150 | false 151 | 152 | 153 | 0 154 | 155 | true 156 | 157 | 158 | 159 | # Provide z stack information here 160 | # 161 | # Each line is one layer. The specification consists of a layer specification, a colon and arguments. 162 | # The arguments are named (like "x=...") or in serial. Parameters are separated by comma or blanks. 163 | # Named arguments are: 164 | # 165 | # zstart The lower z position of the extruded layer in µm 166 | # zstop The upper z position of the extruded layer in µm 167 | # height The height of the extruded layer in µm 168 | # 169 | # 'height', 'zstart' and 'zstop' can be used in any combination. If no value is given for 'zstart', 170 | # the upper level of the previous layer will be used. 171 | # 172 | # If a single unnamed parameter is given, it corresponds to 'height'. Two parameters correspond to 173 | # 'zstart' and 'zstop'. 174 | # 175 | # Examples: 176 | # 1: 0.5 1.5 # extrude layer 1/0 from 0.5 to 1.5 vertically 177 | # 1/0: 0.5 1.5 # same with explicit datatype 178 | # 1: zstop=1.5, zstart=0.5 # same with named parameters 179 | # 1: height=1.0, zstop=1.5 # same with z stop minus height 180 | # 1: 1.0 zstop=1.5 # same with height as unnamed parameter 181 | # 182 | # VARIABLES 183 | # 184 | # You can declare variables with: 185 | # var name = value 186 | # 187 | # You can use variables inside numeric expressions. 188 | # Example: 189 | # var hmetal = 0.48 190 | # 7/0: 0.5 0.5+hmetal*2 # 2x thick metal 191 | # 192 | # You cannot use variables inside layer specifications currently. 193 | # 194 | # CONDITIONALS 195 | # 196 | # You can enable or disable branches of the table using 'if', 'else', 'elseif' and 'end': 197 | # Example: 198 | # var thick_m1 = true 199 | # if thickm1 200 | # 1: 0.5 1.5 201 | # else 202 | # 1: 0.5 1.2 203 | # end 204 | 205 | 206 | 207 | 208 | 30/0,33/0,Metal1 209 | Metal1,35/0,Metal2 210 | Metal2,38/0,Metal3 211 | Metal3,40/0,Metal4 212 | Metal4,41/0,Metal5 213 | Metal5,82/0,53/0 214 | 215 | Metal1='34/0+34/10' 216 | Metal2='36/0+36/10' 217 | Metal3='42/0+42/10' 218 | Metal4='46/0+46/10' 219 | Metal5='81/0+81/10' 220 | 221 | 222 | -------------------------------------------------------------------------------- /libraries/tech/magic/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /multiphysics/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /openlane/README.md: -------------------------------------------------------------------------------- 1 | # OpenLane 2 | 3 | OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, KLayout and a number of custom scripts for design exploration and optimization. The flow performs all ASIC implementation steps from RTL all the way down to GDSII. 4 | 5 | ![image](https://github.com/riosmpw/OpenRPDK28/assets/100336131/9a7f564a-c631-4058-ac13-5710f032cdd2) 6 | 7 | -------------------------------------------------------------------------------- /ref/README.md: -------------------------------------------------------------------------------- 1 | # Reference 2 | 3 | 4 | | Item | Type | Link | Comment | 5 | |------------------------|---------|------------------|---------| 6 | | google/skywater-pdk | PDK | [https://github.com/google/skywater-pdk](https://github.com/google/skywater-pdk) | | 7 | | SkyWater SKY130 PDK | DOC | [https://skywater-pdk.readthedocs.io](https://skywater-pdk.readthedocs.io) | | 8 | | GlobalFoundries 0.18UM 3.3V/(5V)6V MCU PDK | DOC |[https://gf180mcu-pdk.readthedocs.io/](https://gf180mcu-pdk.readthedocs.io/) | | 9 | | globalfoundries-pdk-libs-gf180mcu_fd_pr | PDK |[https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr](https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr) | | 10 | | The OpenLane Documentation | DOC |[https://openlane.readthedocs.io/](https://openlane.readthedocs.io） | | 11 | | Gate level static timing analyzer | | [https://github.com/The-OpenROAD-Project/OpenSTA ](https://github.com/The-OpenROAD-Project/OpenSTA ) | | 12 | | Neural Networks for Automated Power Delivery Network (PDN) Synthesis | | [https://github.com/The-OpenROAD-Project/OpeNPDN ]( https://github.com/The-OpenROAD-Project/OpeNPDN) | | 13 | | IR Solver | | [https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm ](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm ) | | 14 | 15 | 16 | -------------------------------------------------------------------------------- /scripts/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /tcaddata/README.md: -------------------------------------------------------------------------------- 1 | 2 | --------------------------------------------------------------------------------