├── miv-rv32im-systick-blinky ├── .gitignore ├── .project ├── hal │ ├── hal_irq.c │ ├── cpu_types.h │ ├── hal_assert.h │ └── hw_macros.h ├── drivers │ ├── CoreGPIO │ │ └── coregpio_regs.h │ └── CoreUARTapb │ │ └── coreuartapb_regs.h ├── riscv_hal │ ├── riscv_hal.h │ ├── init.c │ ├── microsemi-riscv-igloo2.ld │ ├── microsemi-riscv-ram.ld │ ├── entry.S │ └── sample_hw_platform.h ├── main.c ├── README.txt ├── hw_platform.h └── miv-rv32im-systick-blinky Debug.launch ├── miv-rv32im-interrupt-blinky ├── .gitignore ├── drivers │ ├── CoreTimer │ │ ├── core_timer.h │ │ ├── coretimer_regs.h │ │ └── core_timer.c │ ├── CoreGPIO │ │ └── coregpio_regs.h │ └── CoreUARTapb │ │ └── coreuartapb_regs.h ├── .project ├── hal │ ├── hal_irq.c │ ├── cpu_types.h │ ├── hal_assert.h │ └── hw_macros.h ├── riscv_hal │ ├── riscv_hal.h │ ├── init.c │ ├── microsemi-riscv-igloo2.ld │ ├── microsemi-riscv-ram.ld │ ├── entry.S │ └── sample_hw_platform.h ├── README.txt ├── main.c └── hw_platform.h ├── riscv-simple-baremetal-bootloader ├── .gitignore ├── drivers │ ├── CoreSPI │ │ └── core_spi.h │ ├── CoreTimer │ │ ├── core_timer.h │ │ ├── coretimer_regs.h │ │ └── core_timer.c │ ├── CoreGPIO │ │ └── coregpio_regs.h │ └── CoreUARTapb │ │ └── coreuartapb_regs.h ├── .project ├── hal │ ├── hal_irq.c │ ├── cpu_types.h │ ├── hal_assert.h │ └── hw_macros.h ├── riscv_hal │ ├── riscv_hal.h │ ├── init.c │ ├── microsemi-riscv-igloo2.ld │ ├── microsemi-riscv-ram.ld │ ├── entry.S │ └── sample_hw_platform.h ├── ymodem │ └── ymodem.h ├── README.txt └── riscv-simple-baremetal-bootloader Debug.launch ├── Dhrystone ├── .gitignore ├── drivers │ ├── CoreGPIO │ │ ├── core_gpio.o │ │ └── coregpio_regs.h │ ├── CoreTimer │ │ ├── core_timer.h │ │ ├── core_timer.o │ │ ├── coretimer_regs.h │ │ └── core_timer.c │ └── CoreUARTapb │ │ ├── core_uart_apb.o │ │ └── coreuartapb_regs.h ├── riscv_hal │ ├── all-ram.lds │ ├── all-ram-2.lds │ ├── link.lds │ ├── riscv_hal.h │ ├── init.c │ ├── shared.h │ ├── microsemi-riscv-igloo2.ld │ ├── microsemi-riscv-ram.ld │ ├── entry.S │ └── sample_hw_platform.h ├── dhry_stubs.c ├── .project ├── hal │ ├── hal_irq.c │ ├── cpu_types.h │ ├── hal_assert.h │ └── hw_macros.h ├── .settings │ └── language.settings.xml ├── Readme.md └── Makefile └── .travis.yml /miv-rv32im-systick-blinky/.gitignore: -------------------------------------------------------------------------------- 1 | /Debug/ 2 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/.gitignore: -------------------------------------------------------------------------------- 1 | /Debug/ 2 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/.gitignore: -------------------------------------------------------------------------------- 1 | /Debug/ 2 | -------------------------------------------------------------------------------- /Dhrystone/.gitignore: -------------------------------------------------------------------------------- 1 | /dhrystone.elf 2 | /dhrystone.lst 3 | 4 | -------------------------------------------------------------------------------- /Dhrystone/drivers/CoreGPIO/core_gpio.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RISCV-on-Microsemi-FPGA/SoftConsole/HEAD/Dhrystone/drivers/CoreGPIO/core_gpio.o -------------------------------------------------------------------------------- /Dhrystone/drivers/CoreTimer/core_timer.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RISCV-on-Microsemi-FPGA/SoftConsole/HEAD/Dhrystone/drivers/CoreTimer/core_timer.h -------------------------------------------------------------------------------- /Dhrystone/drivers/CoreTimer/core_timer.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RISCV-on-Microsemi-FPGA/SoftConsole/HEAD/Dhrystone/drivers/CoreTimer/core_timer.o -------------------------------------------------------------------------------- /Dhrystone/drivers/CoreUARTapb/core_uart_apb.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RISCV-on-Microsemi-FPGA/SoftConsole/HEAD/Dhrystone/drivers/CoreUARTapb/core_uart_apb.o -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | sudo: required 2 | language: generic 3 | script: 4 | - docker run -v ${TRAVIS_BUILD_DIR}:/projects microsemiproess/softconsole-headless-slim:5.3 bash -c "sch -i=/projects" 5 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/drivers/CoreTimer/core_timer.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RISCV-on-Microsemi-FPGA/SoftConsole/HEAD/miv-rv32im-interrupt-blinky/drivers/CoreTimer/core_timer.h -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/drivers/CoreSPI/core_spi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RISCV-on-Microsemi-FPGA/SoftConsole/HEAD/riscv-simple-baremetal-bootloader/drivers/CoreSPI/core_spi.h -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/drivers/CoreTimer/core_timer.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RISCV-on-Microsemi-FPGA/SoftConsole/HEAD/riscv-simple-baremetal-bootloader/drivers/CoreTimer/core_timer.h -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/all-ram.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | SECTIONS 4 | { 5 | . = 0x80000000; 6 | .text : 7 | { 8 | entry.o(.text) 9 | *(.text) 10 | } 11 | 12 | /* data segment */ 13 | _data = .; 14 | .data : { *(.data) } 15 | 16 | .sdata : { 17 | _gp = . + 0x800; 18 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 19 | *(.srodata*) 20 | *(.sdata .sdata.* .gnu.linkonce.s.*) 21 | } 22 | 23 | /* bss segment */ 24 | .sbss : { 25 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 26 | *(.scommon) 27 | } 28 | .bss : { *(.bss) } 29 | 30 | /* End of uninitalized data segement */ 31 | _data_end = .; 32 | _end = .; 33 | _heap_end = .; 34 | } 35 | 36 | -------------------------------------------------------------------------------- /Dhrystone/dhry_stubs.c: -------------------------------------------------------------------------------- 1 | /* The functions in this file are only meant to support Dhrystone on an 2 | * embedded RV32 system and are obviously incorrect in general. */ 3 | // return the cycle counter as though it were the current time 4 | long time(void) 5 | { 6 | unsigned long t; 7 | asm volatile ("csrr %0, mcycle" : "=r" (t)); 8 | // Assumes processor is at 100MHz and that you want time in ms. 9 | return t / 83000000; 10 | } 11 | 12 | // set the number of dhrystone iterations 13 | void scanf(const char* fmt, int* n) 14 | { 15 | *n = 100000; 16 | } 17 | 18 | // simple memory allocator 19 | void* malloc(unsigned long sz) 20 | { 21 | extern void* _sbrk(long); 22 | void* res = sbrk(sz); 23 | if ((long)res == -1) 24 | return 0; 25 | return res; 26 | } 27 | 28 | // simple memory deallocator 29 | void free(void* ptr) {} 30 | -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/all-ram-2.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | SECTIONS 4 | { 5 | . = 0x80000000; 6 | .text : 7 | { 8 | entry.o(.text) 9 | dhry_stubs.o(.text) 10 | syscall.o(.text) 11 | *(.text.startup) 12 | *(.text) 13 | } 14 | 15 | .eh_frame : { *(.eh_frame) } 16 | 17 | .rodata : { 18 | *(.rodata*) 19 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 20 | *(.srodata*) 21 | } 22 | 23 | . = 0x80040000; 24 | _data = .; 25 | 26 | /* data segment */ 27 | .data : { *(.data) } 28 | 29 | .sdata : { 30 | _gp = . + 0x800; 31 | *(.sdata .sdata.* .gnu.linkonce.s.*) 32 | } 33 | 34 | /* bss segment */ 35 | .sbss : { 36 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 37 | *(.scommon) 38 | } 39 | .bss : { *(.bss) } 40 | 41 | _data_end = .; 42 | _end = .; 43 | } 44 | -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/link.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | SECTIONS 4 | { 5 | . = 0x60000000; 6 | .text : 7 | { 8 | entry.o(.text) 9 | dhry_stubs.o(.text) 10 | syscall.o(.text) 11 | *(.text.startup) 12 | *(.text) 13 | } 14 | 15 | .eh_frame : { *(.eh_frame) } 16 | 17 | .rodata : { 18 | *(.rodata*) 19 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 20 | *(.srodata*) 21 | } 22 | 23 | . = 0x80000000; 24 | _data = .; 25 | 26 | /* data segment */ 27 | .data : { *(.data) } 28 | 29 | .sdata : { 30 | _gp = . + 0x800; 31 | *(.sdata .sdata.* .gnu.linkonce.s.*) 32 | } 33 | 34 | /* bss segment */ 35 | .sbss : { 36 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 37 | *(.scommon) 38 | } 39 | .bss : { *(.bss) } 40 | 41 | _data_end = .; 42 | _end = .; 43 | } 44 | 45 | -------------------------------------------------------------------------------- /Dhrystone/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | Dhrystone_RISCV 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | miv-rv32im-systick-blinky 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | miv-rv32im-interrupt-blinky 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | riscv-simple-baremetal-bootloader 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /Dhrystone/hal/hal_irq.c: -------------------------------------------------------------------------------- 1 | /***************************************************************************//** 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * Legacy interrupt control functions for the Microsemi driver library hardware 5 | * abstraction layer. 6 | * 7 | * SVN $Revision: 9661 $ 8 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 9 | */ 10 | #include "hal.h" 11 | #include "riscv_hal.h" 12 | 13 | /*------------------------------------------------------------------------------ 14 | * 15 | */ 16 | void HAL_enable_interrupts(void) { 17 | __enable_irq(); 18 | } 19 | 20 | /*------------------------------------------------------------------------------ 21 | * 22 | */ 23 | psr_t HAL_disable_interrupts(void) { 24 | psr_t psr; 25 | psr = read_csr(mstatus); 26 | __disable_irq(); 27 | return(psr); 28 | } 29 | 30 | /*------------------------------------------------------------------------------ 31 | * 32 | */ 33 | void HAL_restore_interrupts(psr_t saved_psr) { 34 | write_csr(mstatus, saved_psr); 35 | } 36 | 37 | -------------------------------------------------------------------------------- /Dhrystone/hal/cpu_types.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9661 $ 5 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 6 | */ 7 | #ifndef __CPU_TYPES_H 8 | #define __CPU_TYPES_H 1 9 | 10 | #include 11 | 12 | /*------------------------------------------------------------------------------ 13 | */ 14 | typedef unsigned int size_t; 15 | 16 | /*------------------------------------------------------------------------------ 17 | * addr_t: address type. 18 | * Used to specify the address of peripherals present in the processor's memory 19 | * map. 20 | */ 21 | typedef unsigned int addr_t; 22 | 23 | /*------------------------------------------------------------------------------ 24 | * psr_t: processor state register. 25 | * Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the 26 | * processor's state between disabling and restoring interrupts. 27 | */ 28 | typedef unsigned int psr_t; 29 | 30 | #endif /* __CPU_TYPES_H */ 31 | 32 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/hal/hal_irq.c: -------------------------------------------------------------------------------- 1 | /***************************************************************************//** 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * Legacy interrupt control functions for the Microsemi driver library hardware 5 | * abstraction layer. 6 | * 7 | * SVN $Revision: 9085 $ 8 | * SVN $Date: 2017-04-28 14:29:14 +0530 (Fri, 28 Apr 2017) $ 9 | */ 10 | #include "hal.h" 11 | #include "riscv_hal.h" 12 | 13 | /*------------------------------------------------------------------------------ 14 | * 15 | */ 16 | void HAL_enable_interrupts(void) { 17 | __enable_irq(); 18 | } 19 | 20 | /*------------------------------------------------------------------------------ 21 | * 22 | */ 23 | psr_t HAL_disable_interrupts(void) { 24 | psr_t psr; 25 | psr = read_csr(mstatus); 26 | __disable_irq(); 27 | return(psr); 28 | } 29 | 30 | /*------------------------------------------------------------------------------ 31 | * 32 | */ 33 | void HAL_restore_interrupts(psr_t saved_psr) { 34 | write_csr(mstatus, saved_psr); 35 | } 36 | 37 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/hal/hal_irq.c: -------------------------------------------------------------------------------- 1 | /***************************************************************************//** 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * Legacy interrupt control functions for the Microsemi driver library hardware 5 | * abstraction layer. 6 | * 7 | * SVN $Revision: 9661 $ 8 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 9 | */ 10 | #include "hal.h" 11 | #include "riscv_hal.h" 12 | 13 | /*------------------------------------------------------------------------------ 14 | * 15 | */ 16 | void HAL_enable_interrupts(void) { 17 | __enable_irq(); 18 | } 19 | 20 | /*------------------------------------------------------------------------------ 21 | * 22 | */ 23 | psr_t HAL_disable_interrupts(void) { 24 | psr_t psr; 25 | psr = read_csr(mstatus); 26 | __disable_irq(); 27 | return(psr); 28 | } 29 | 30 | /*------------------------------------------------------------------------------ 31 | * 32 | */ 33 | void HAL_restore_interrupts(psr_t saved_psr) { 34 | write_csr(mstatus, saved_psr); 35 | } 36 | 37 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/hal/hal_irq.c: -------------------------------------------------------------------------------- 1 | /***************************************************************************//** 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * Legacy interrupt control functions for the Microsemi driver library hardware 5 | * abstraction layer. 6 | * 7 | * SVN $Revision: 9661 $ 8 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 9 | */ 10 | #include "hal.h" 11 | #include "riscv_hal.h" 12 | 13 | /*------------------------------------------------------------------------------ 14 | * 15 | */ 16 | void HAL_enable_interrupts(void) { 17 | __enable_irq(); 18 | } 19 | 20 | /*------------------------------------------------------------------------------ 21 | * 22 | */ 23 | psr_t HAL_disable_interrupts(void) { 24 | psr_t psr; 25 | psr = read_csr(mstatus); 26 | __disable_irq(); 27 | return(psr); 28 | } 29 | 30 | /*------------------------------------------------------------------------------ 31 | * 32 | */ 33 | void HAL_restore_interrupts(psr_t saved_psr) { 34 | write_csr(mstatus, saved_psr); 35 | } 36 | 37 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/hal/cpu_types.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9661 $ 5 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 6 | */ 7 | #ifndef __CPU_TYPES_H 8 | #define __CPU_TYPES_H 1 9 | 10 | #include 11 | 12 | /*------------------------------------------------------------------------------ 13 | */ 14 | typedef unsigned int size_t; 15 | 16 | /*------------------------------------------------------------------------------ 17 | * addr_t: address type. 18 | * Used to specify the address of peripherals present in the processor's memory 19 | * map. 20 | */ 21 | typedef unsigned int addr_t; 22 | 23 | /*------------------------------------------------------------------------------ 24 | * psr_t: processor state register. 25 | * Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the 26 | * processor's state between disabling and restoring interrupts. 27 | */ 28 | typedef unsigned int psr_t; 29 | 30 | #endif /* __CPU_TYPES_H */ 31 | 32 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/hal/cpu_types.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9085 $ 5 | * SVN $Date: 2017-04-28 14:29:14 +0530 (Fri, 28 Apr 2017) $ 6 | */ 7 | #ifndef __CPU_TYPES_H 8 | #define __CPU_TYPES_H 1 9 | 10 | #include 11 | 12 | /*------------------------------------------------------------------------------ 13 | */ 14 | typedef unsigned int size_t; 15 | 16 | /*------------------------------------------------------------------------------ 17 | * addr_t: address type. 18 | * Used to specify the address of peripherals present in the processor's memory 19 | * map. 20 | */ 21 | typedef unsigned int addr_t; 22 | 23 | /*------------------------------------------------------------------------------ 24 | * psr_t: processor state register. 25 | * Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the 26 | * processor's state between disabling and restoring interrupts. 27 | */ 28 | typedef unsigned int psr_t; 29 | 30 | #endif /* __CPU_TYPES_H */ 31 | 32 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/hal/cpu_types.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9661 $ 5 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 6 | */ 7 | #ifndef __CPU_TYPES_H 8 | #define __CPU_TYPES_H 1 9 | 10 | #include 11 | 12 | /*------------------------------------------------------------------------------ 13 | */ 14 | typedef unsigned int size_t; 15 | 16 | /*------------------------------------------------------------------------------ 17 | * addr_t: address type. 18 | * Used to specify the address of peripherals present in the processor's memory 19 | * map. 20 | */ 21 | typedef unsigned int addr_t; 22 | 23 | /*------------------------------------------------------------------------------ 24 | * psr_t: processor state register. 25 | * Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the 26 | * processor's state between disabling and restoring interrupts. 27 | */ 28 | typedef unsigned int psr_t; 29 | 30 | #endif /* __CPU_TYPES_H */ 31 | 32 | -------------------------------------------------------------------------------- /Dhrystone/hal/hal_assert.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2008-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9661 $ 5 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 6 | */ 7 | #ifndef HAL_ASSERT_HEADER 8 | #define HAL_ASSERT_HEADER 9 | 10 | #define NDEBUG 1 11 | 12 | #if defined(NDEBUG) 13 | /***************************************************************************//** 14 | * HAL_ASSERT() is defined out when the NDEBUG symbol is used. 15 | ******************************************************************************/ 16 | #define HAL_ASSERT(CHECK) 17 | 18 | #else 19 | /***************************************************************************//** 20 | * Default behaviour for HAL_ASSERT() macro: 21 | *------------------------------------------------------------------------------ 22 | The behaviour is toolchain specific and project setting specific. 23 | ******************************************************************************/ 24 | #define HAL_ASSERT(CHECK) ASSERT(CHECK); 25 | 26 | #endif /* NDEBUG */ 27 | 28 | #endif /* HAL_ASSERT_HEADER */ 29 | 30 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/hal/hal_assert.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2008-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9661 $ 5 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 6 | */ 7 | #ifndef HAL_ASSERT_HEADER 8 | #define HAL_ASSERT_HEADER 9 | 10 | #define NDEBUG 1 11 | 12 | #if defined(NDEBUG) 13 | /***************************************************************************//** 14 | * HAL_ASSERT() is defined out when the NDEBUG symbol is used. 15 | ******************************************************************************/ 16 | #define HAL_ASSERT(CHECK) 17 | 18 | #else 19 | /***************************************************************************//** 20 | * Default behaviour for HAL_ASSERT() macro: 21 | *------------------------------------------------------------------------------ 22 | The behaviour is toolchain specific and project setting specific. 23 | ******************************************************************************/ 24 | #define HAL_ASSERT(CHECK) ASSERT(CHECK); 25 | 26 | #endif /* NDEBUG */ 27 | 28 | #endif /* HAL_ASSERT_HEADER */ 29 | 30 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/hal/hal_assert.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2008-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9587 $ 5 | * SVN $Date: 2017-11-16 12:53:31 +0530 (Thu, 16 Nov 2017) $ 6 | */ 7 | #ifndef HAL_ASSERT_HEADER 8 | #define HAL_ASSERT_HEADER 9 | 10 | #define NDEBUG 1 11 | 12 | #if defined(NDEBUG) 13 | /***************************************************************************//** 14 | * HAL_ASSERT() is defined out when the NDEBUG symbol is used. 15 | ******************************************************************************/ 16 | #define HAL_ASSERT(CHECK) 17 | 18 | #else 19 | /***************************************************************************//** 20 | * Default behaviour for HAL_ASSERT() macro: 21 | *------------------------------------------------------------------------------ 22 | The behaviour is toolchain specific and project setting specific. 23 | ******************************************************************************/ 24 | #define HAL_ASSERT(CHECK) ASSERT(CHECK); 25 | 26 | #endif /* NDEBUG */ 27 | 28 | #endif /* HAL_ASSERT_HEADER */ 29 | 30 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/hal/hal_assert.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2008-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9661 $ 5 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 6 | */ 7 | #ifndef HAL_ASSERT_HEADER 8 | #define HAL_ASSERT_HEADER 9 | 10 | #define NDEBUG 1 11 | 12 | #if defined(NDEBUG) 13 | /***************************************************************************//** 14 | * HAL_ASSERT() is defined out when the NDEBUG symbol is used. 15 | ******************************************************************************/ 16 | #define HAL_ASSERT(CHECK) 17 | 18 | #else 19 | /***************************************************************************//** 20 | * Default behaviour for HAL_ASSERT() macro: 21 | *------------------------------------------------------------------------------ 22 | The behaviour is toolchain specific and project setting specific. 23 | ******************************************************************************/ 24 | #define HAL_ASSERT(CHECK) ASSERT(CHECK); 25 | 26 | #endif /* NDEBUG */ 27 | 28 | #endif /* HAL_ASSERT_HEADER */ 29 | 30 | -------------------------------------------------------------------------------- /Dhrystone/drivers/CoreGPIO/coregpio_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2009-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9743 $ 5 | * SVN $Date: 2018-02-12 15:45:09 +0530 (Mon, 12 Feb 2018) $ 6 | */ 7 | #ifndef __CORE_GPIO_REGISTERS_H 8 | #define __CORE_GPIO_REGISTERS_H 1 9 | 10 | /*------------------------------------------------------------------------------ 11 | * 12 | */ 13 | #define IRQ_REG_OFFSET 0x80 14 | 15 | #define IRQ0_REG_OFFSET 0x80 16 | #define IRQ1_REG_OFFSET 0x84 17 | #define IRQ2_REG_OFFSET 0x88 18 | #define IRQ3_REG_OFFSET 0x8C 19 | 20 | /*------------------------------------------------------------------------------ 21 | * 22 | */ 23 | #define GPIO_IN_REG_OFFSET 0x90 24 | 25 | #define GPIO_IN0_REG_OFFSET 0x90 26 | #define GPIO_IN1_REG_OFFSET 0x94 27 | #define GPIO_IN2_REG_OFFSET 0x98 28 | #define GPIO_IN3_REG_OFFSET 0x9C 29 | 30 | /*------------------------------------------------------------------------------ 31 | * 32 | */ 33 | #define GPIO_OUT_REG_OFFSET 0xA0 34 | 35 | #define GPIO_OUT0_REG_OFFSET 0xA0 36 | #define GPIO_OUT1_REG_OFFSET 0xA4 37 | #define GPIO_OUT2_REG_OFFSET 0xA8 38 | #define GPIO_OUT3_REG_OFFSET 0xAC 39 | 40 | #endif /* __CORE_GPIO_REGISTERS_H */ 41 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/drivers/CoreGPIO/coregpio_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2009-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9743 $ 5 | * SVN $Date: 2018-02-12 15:45:09 +0530 (Mon, 12 Feb 2018) $ 6 | */ 7 | #ifndef __CORE_GPIO_REGISTERS_H 8 | #define __CORE_GPIO_REGISTERS_H 1 9 | 10 | /*------------------------------------------------------------------------------ 11 | * 12 | */ 13 | #define IRQ_REG_OFFSET 0x80 14 | 15 | #define IRQ0_REG_OFFSET 0x80 16 | #define IRQ1_REG_OFFSET 0x84 17 | #define IRQ2_REG_OFFSET 0x88 18 | #define IRQ3_REG_OFFSET 0x8C 19 | 20 | /*------------------------------------------------------------------------------ 21 | * 22 | */ 23 | #define GPIO_IN_REG_OFFSET 0x90 24 | 25 | #define GPIO_IN0_REG_OFFSET 0x90 26 | #define GPIO_IN1_REG_OFFSET 0x94 27 | #define GPIO_IN2_REG_OFFSET 0x98 28 | #define GPIO_IN3_REG_OFFSET 0x9C 29 | 30 | /*------------------------------------------------------------------------------ 31 | * 32 | */ 33 | #define GPIO_OUT_REG_OFFSET 0xA0 34 | 35 | #define GPIO_OUT0_REG_OFFSET 0xA0 36 | #define GPIO_OUT1_REG_OFFSET 0xA4 37 | #define GPIO_OUT2_REG_OFFSET 0xA8 38 | #define GPIO_OUT3_REG_OFFSET 0xAC 39 | 40 | #endif /* __CORE_GPIO_REGISTERS_H */ 41 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/drivers/CoreGPIO/coregpio_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2009-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9743 $ 5 | * SVN $Date: 2018-02-12 15:45:09 +0530 (Mon, 12 Feb 2018) $ 6 | */ 7 | #ifndef __CORE_GPIO_REGISTERS_H 8 | #define __CORE_GPIO_REGISTERS_H 1 9 | 10 | /*------------------------------------------------------------------------------ 11 | * 12 | */ 13 | #define IRQ_REG_OFFSET 0x80 14 | 15 | #define IRQ0_REG_OFFSET 0x80 16 | #define IRQ1_REG_OFFSET 0x84 17 | #define IRQ2_REG_OFFSET 0x88 18 | #define IRQ3_REG_OFFSET 0x8C 19 | 20 | /*------------------------------------------------------------------------------ 21 | * 22 | */ 23 | #define GPIO_IN_REG_OFFSET 0x90 24 | 25 | #define GPIO_IN0_REG_OFFSET 0x90 26 | #define GPIO_IN1_REG_OFFSET 0x94 27 | #define GPIO_IN2_REG_OFFSET 0x98 28 | #define GPIO_IN3_REG_OFFSET 0x9C 29 | 30 | /*------------------------------------------------------------------------------ 31 | * 32 | */ 33 | #define GPIO_OUT_REG_OFFSET 0xA0 34 | 35 | #define GPIO_OUT0_REG_OFFSET 0xA0 36 | #define GPIO_OUT1_REG_OFFSET 0xA4 37 | #define GPIO_OUT2_REG_OFFSET 0xA8 38 | #define GPIO_OUT3_REG_OFFSET 0xAC 39 | 40 | #endif /* __CORE_GPIO_REGISTERS_H */ 41 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/drivers/CoreGPIO/coregpio_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2009-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9743 $ 5 | * SVN $Date: 2018-02-12 15:45:09 +0530 (Mon, 12 Feb 2018) $ 6 | */ 7 | #ifndef __CORE_GPIO_REGISTERS_H 8 | #define __CORE_GPIO_REGISTERS_H 1 9 | 10 | /*------------------------------------------------------------------------------ 11 | * 12 | */ 13 | #define IRQ_REG_OFFSET 0x80 14 | 15 | #define IRQ0_REG_OFFSET 0x80 16 | #define IRQ1_REG_OFFSET 0x84 17 | #define IRQ2_REG_OFFSET 0x88 18 | #define IRQ3_REG_OFFSET 0x8C 19 | 20 | /*------------------------------------------------------------------------------ 21 | * 22 | */ 23 | #define GPIO_IN_REG_OFFSET 0x90 24 | 25 | #define GPIO_IN0_REG_OFFSET 0x90 26 | #define GPIO_IN1_REG_OFFSET 0x94 27 | #define GPIO_IN2_REG_OFFSET 0x98 28 | #define GPIO_IN3_REG_OFFSET 0x9C 29 | 30 | /*------------------------------------------------------------------------------ 31 | * 32 | */ 33 | #define GPIO_OUT_REG_OFFSET 0xA0 34 | 35 | #define GPIO_OUT0_REG_OFFSET 0xA0 36 | #define GPIO_OUT1_REG_OFFSET 0xA4 37 | #define GPIO_OUT2_REG_OFFSET 0xA8 38 | #define GPIO_OUT3_REG_OFFSET 0xAC 39 | 40 | #endif /* __CORE_GPIO_REGISTERS_H */ 41 | -------------------------------------------------------------------------------- /Dhrystone/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/riscv_hal.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file riscv_hal.h 5 | * @author Microsemi SoC Products Group 6 | * @brief Hardware Abstraction Layer functions for Mi-V soft processors 7 | * 8 | * SVN $Revision: 9835 $ 9 | * SVN $Date: 2018-03-19 19:11:35 +0530 (Mon, 19 Mar 2018) $ 10 | */ 11 | 12 | #ifndef RISCV_HAL_H 13 | #define RISCV_HAL_H 14 | 15 | #include "riscv_plic.h" 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | /* 22 | *Return value from External IRQ handler. This will be used to disable the External 23 | *interrupt. 24 | */ 25 | #define EXT_IRQ_KEEP_ENABLED 0U 26 | #define EXT_IRQ_DISABLE 1U 27 | 28 | /*------------------------------------------------------------------------------ 29 | * Interrupt enable/disable. 30 | */ 31 | void __disable_irq(void); 32 | void __enable_irq(void); 33 | 34 | /*------------------------------------------------------------------------------ 35 | * System tick handler. This is generated from the RISC-V machine timer. 36 | */ 37 | void SysTick_Handler(void); 38 | 39 | /*------------------------------------------------------------------------------ 40 | * System tick configuration. 41 | * Configures the machine timer to generate a system tick interrupt at regular 42 | * intervals. 43 | * Takes the number of system clock ticks between interrupts. 44 | * 45 | * Returns 0 if successful. 46 | * Returns 1 if the interrupt interval cannot be achieved. 47 | */ 48 | uint32_t SysTick_Config(uint32_t ticks); 49 | 50 | #ifdef __cplusplus 51 | } 52 | #endif 53 | 54 | #endif /* RISCV_HAL_H */ 55 | 56 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/riscv_hal/riscv_hal.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file riscv_hal.h 5 | * @author Microsemi SoC Products Group 6 | * @brief Hardware Abstraction Layer functions for Mi-V soft processors 7 | * 8 | * SVN $Revision: 9835 $ 9 | * SVN $Date: 2018-03-19 19:11:35 +0530 (Mon, 19 Mar 2018) $ 10 | */ 11 | 12 | #ifndef RISCV_HAL_H 13 | #define RISCV_HAL_H 14 | 15 | #include "riscv_plic.h" 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | /* 22 | *Return value from External IRQ handler. This will be used to disable the External 23 | *interrupt. 24 | */ 25 | #define EXT_IRQ_KEEP_ENABLED 0U 26 | #define EXT_IRQ_DISABLE 1U 27 | 28 | /*------------------------------------------------------------------------------ 29 | * Interrupt enable/disable. 30 | */ 31 | void __disable_irq(void); 32 | void __enable_irq(void); 33 | 34 | /*------------------------------------------------------------------------------ 35 | * System tick handler. This is generated from the RISC-V machine timer. 36 | */ 37 | void SysTick_Handler(void); 38 | 39 | /*------------------------------------------------------------------------------ 40 | * System tick configuration. 41 | * Configures the machine timer to generate a system tick interrupt at regular 42 | * intervals. 43 | * Takes the number of system clock ticks between interrupts. 44 | * 45 | * Returns 0 if successful. 46 | * Returns 1 if the interrupt interval cannot be achieved. 47 | */ 48 | uint32_t SysTick_Config(uint32_t ticks); 49 | 50 | #ifdef __cplusplus 51 | } 52 | #endif 53 | 54 | #endif /* RISCV_HAL_H */ 55 | 56 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/riscv_hal/riscv_hal.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file riscv_hal.h 5 | * @author Microsemi SoC Products Group 6 | * @brief Hardware Abstraction Layer functions for Mi-V soft processors 7 | * 8 | * SVN $Revision: 9835 $ 9 | * SVN $Date: 2018-03-19 19:11:35 +0530 (Mon, 19 Mar 2018) $ 10 | */ 11 | 12 | #ifndef RISCV_HAL_H 13 | #define RISCV_HAL_H 14 | 15 | #include "riscv_plic.h" 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | /* 22 | *Return value from External IRQ handler. This will be used to disable the External 23 | *interrupt. 24 | */ 25 | #define EXT_IRQ_KEEP_ENABLED 0U 26 | #define EXT_IRQ_DISABLE 1U 27 | 28 | /*------------------------------------------------------------------------------ 29 | * Interrupt enable/disable. 30 | */ 31 | void __disable_irq(void); 32 | void __enable_irq(void); 33 | 34 | /*------------------------------------------------------------------------------ 35 | * System tick handler. This is generated from the RISC-V machine timer. 36 | */ 37 | void SysTick_Handler(void); 38 | 39 | /*------------------------------------------------------------------------------ 40 | * System tick configuration. 41 | * Configures the machine timer to generate a system tick interrupt at regular 42 | * intervals. 43 | * Takes the number of system clock ticks between interrupts. 44 | * 45 | * Returns 0 if successful. 46 | * Returns 1 if the interrupt interval cannot be achieved. 47 | */ 48 | uint32_t SysTick_Config(uint32_t ticks); 49 | 50 | #ifdef __cplusplus 51 | } 52 | #endif 53 | 54 | #endif /* RISCV_HAL_H */ 55 | 56 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/riscv_hal/riscv_hal.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file riscv_hal.h 5 | * @author Microsemi SoC Products Group 6 | * @brief Hardware Abstraction Layer functions for Mi-V soft processors 7 | * 8 | * SVN $Revision: 9835 $ 9 | * SVN $Date: 2018-03-19 19:11:35 +0530 (Mon, 19 Mar 2018) $ 10 | */ 11 | 12 | #ifndef RISCV_HAL_H 13 | #define RISCV_HAL_H 14 | 15 | #include "riscv_plic.h" 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | /* 22 | *Return value from External IRQ handler. This will be used to disable the External 23 | *interrupt. 24 | */ 25 | #define EXT_IRQ_KEEP_ENABLED 0U 26 | #define EXT_IRQ_DISABLE 1U 27 | 28 | /*------------------------------------------------------------------------------ 29 | * Interrupt enable/disable. 30 | */ 31 | void __disable_irq(void); 32 | void __enable_irq(void); 33 | 34 | /*------------------------------------------------------------------------------ 35 | * System tick handler. This is generated from the RISC-V machine timer. 36 | */ 37 | void SysTick_Handler(void); 38 | 39 | /*------------------------------------------------------------------------------ 40 | * System tick configuration. 41 | * Configures the machine timer to generate a system tick interrupt at regular 42 | * intervals. 43 | * Takes the number of system clock ticks between interrupts. 44 | * 45 | * Returns 0 if successful. 46 | * Returns 1 if the interrupt interval cannot be achieved. 47 | */ 48 | uint32_t SysTick_Config(uint32_t ticks); 49 | 50 | #ifdef __cplusplus 51 | } 52 | #endif 53 | 54 | #endif /* RISCV_HAL_H */ 55 | 56 | -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/init.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file init.c 5 | * @author Microsemi SoC Products Group 6 | * @brief Mi-V soft processor memory section initializations and start-up code. 7 | * 8 | * SVN $Revision: 9661 $ 9 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 10 | */ 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | #include "encoding.h" 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | extern uint32_t __sdata_load; 23 | extern uint32_t __sdata_start; 24 | extern uint32_t __sdata_end; 25 | 26 | extern uint32_t __data_load; 27 | extern uint32_t __data_start; 28 | extern uint32_t __data_end; 29 | 30 | extern uint32_t __sbss_start; 31 | extern uint32_t __sbss_end; 32 | extern uint32_t __bss_start; 33 | extern uint32_t __bss_end; 34 | 35 | 36 | static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end) 37 | { 38 | while(p_vma <= p_vma_end) 39 | { 40 | *p_vma = *p_load; 41 | ++p_load; 42 | ++p_vma; 43 | } 44 | } 45 | 46 | static void zero_section(uint32_t * start, uint32_t * end) 47 | { 48 | uint32_t * p_zero = start; 49 | 50 | while(p_zero <= end) 51 | { 52 | *p_zero = 0; 53 | ++p_zero; 54 | } 55 | } 56 | 57 | void _init(void) 58 | { 59 | extern int main(int, char**); 60 | const char *argv0 = "hello"; 61 | char *argv[] = {(char *)argv0, NULL, NULL}; 62 | 63 | copy_section(&__sdata_load, &__sdata_start, &__sdata_end); 64 | copy_section(&__data_load, &__data_start, &__data_end); 65 | zero_section(&__sbss_start, &__sbss_end); 66 | zero_section(&__bss_start, &__bss_end); 67 | 68 | main(1, argv); 69 | } 70 | 71 | /* Function called after main() finishes */ 72 | void 73 | _fini() 74 | { 75 | } 76 | 77 | #ifdef __cplusplus 78 | } 79 | #endif 80 | 81 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/riscv_hal/init.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file init.c 5 | * @author Microsemi SoC Products Group 6 | * @brief Mi-V soft processor memory section initializations and start-up code. 7 | * 8 | * SVN $Revision: 9661 $ 9 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 10 | */ 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | #include "encoding.h" 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | extern uint32_t __sdata_load; 23 | extern uint32_t __sdata_start; 24 | extern uint32_t __sdata_end; 25 | 26 | extern uint32_t __data_load; 27 | extern uint32_t __data_start; 28 | extern uint32_t __data_end; 29 | 30 | extern uint32_t __sbss_start; 31 | extern uint32_t __sbss_end; 32 | extern uint32_t __bss_start; 33 | extern uint32_t __bss_end; 34 | 35 | 36 | static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end) 37 | { 38 | while(p_vma <= p_vma_end) 39 | { 40 | *p_vma = *p_load; 41 | ++p_load; 42 | ++p_vma; 43 | } 44 | } 45 | 46 | static void zero_section(uint32_t * start, uint32_t * end) 47 | { 48 | uint32_t * p_zero = start; 49 | 50 | while(p_zero <= end) 51 | { 52 | *p_zero = 0; 53 | ++p_zero; 54 | } 55 | } 56 | 57 | void _init(void) 58 | { 59 | extern int main(int, char**); 60 | const char *argv0 = "hello"; 61 | char *argv[] = {(char *)argv0, NULL, NULL}; 62 | 63 | copy_section(&__sdata_load, &__sdata_start, &__sdata_end); 64 | copy_section(&__data_load, &__data_start, &__data_end); 65 | zero_section(&__sbss_start, &__sbss_end); 66 | zero_section(&__bss_start, &__bss_end); 67 | 68 | main(1, argv); 69 | } 70 | 71 | /* Function called after main() finishes */ 72 | void 73 | _fini() 74 | { 75 | } 76 | 77 | #ifdef __cplusplus 78 | } 79 | #endif 80 | 81 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/riscv_hal/init.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file init.c 5 | * @author Microsemi SoC Products Group 6 | * @brief Mi-V soft processor memory section initializations and start-up code. 7 | * 8 | * SVN $Revision: 9661 $ 9 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 10 | */ 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | #include "encoding.h" 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | extern uint32_t __sdata_load; 23 | extern uint32_t __sdata_start; 24 | extern uint32_t __sdata_end; 25 | 26 | extern uint32_t __data_load; 27 | extern uint32_t __data_start; 28 | extern uint32_t __data_end; 29 | 30 | extern uint32_t __sbss_start; 31 | extern uint32_t __sbss_end; 32 | extern uint32_t __bss_start; 33 | extern uint32_t __bss_end; 34 | 35 | 36 | static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end) 37 | { 38 | while(p_vma <= p_vma_end) 39 | { 40 | *p_vma = *p_load; 41 | ++p_load; 42 | ++p_vma; 43 | } 44 | } 45 | 46 | static void zero_section(uint32_t * start, uint32_t * end) 47 | { 48 | uint32_t * p_zero = start; 49 | 50 | while(p_zero <= end) 51 | { 52 | *p_zero = 0; 53 | ++p_zero; 54 | } 55 | } 56 | 57 | void _init(void) 58 | { 59 | extern int main(int, char**); 60 | const char *argv0 = "hello"; 61 | char *argv[] = {(char *)argv0, NULL, NULL}; 62 | 63 | copy_section(&__sdata_load, &__sdata_start, &__sdata_end); 64 | copy_section(&__data_load, &__data_start, &__data_end); 65 | zero_section(&__sbss_start, &__sbss_end); 66 | zero_section(&__bss_start, &__bss_end); 67 | 68 | main(1, argv); 69 | } 70 | 71 | /* Function called after main() finishes */ 72 | void 73 | _fini() 74 | { 75 | } 76 | 77 | #ifdef __cplusplus 78 | } 79 | #endif 80 | 81 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/riscv_hal/init.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file init.c 5 | * @author Microsemi SoC Products Group 6 | * @brief Mi-V soft processor memory section initializations and start-up code. 7 | * 8 | * SVN $Revision: 9661 $ 9 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 10 | */ 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | #include "encoding.h" 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | extern uint32_t __sdata_load; 23 | extern uint32_t __sdata_start; 24 | extern uint32_t __sdata_end; 25 | 26 | extern uint32_t __data_load; 27 | extern uint32_t __data_start; 28 | extern uint32_t __data_end; 29 | 30 | extern uint32_t __sbss_start; 31 | extern uint32_t __sbss_end; 32 | extern uint32_t __bss_start; 33 | extern uint32_t __bss_end; 34 | 35 | 36 | static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end) 37 | { 38 | while(p_vma <= p_vma_end) 39 | { 40 | *p_vma = *p_load; 41 | ++p_load; 42 | ++p_vma; 43 | } 44 | } 45 | 46 | static void zero_section(uint32_t * start, uint32_t * end) 47 | { 48 | uint32_t * p_zero = start; 49 | 50 | while(p_zero <= end) 51 | { 52 | *p_zero = 0; 53 | ++p_zero; 54 | } 55 | } 56 | 57 | void _init(void) 58 | { 59 | extern int main(int, char**); 60 | const char *argv0 = "hello"; 61 | char *argv[] = {(char *)argv0, NULL, NULL}; 62 | 63 | copy_section(&__sdata_load, &__sdata_start, &__sdata_end); 64 | copy_section(&__data_load, &__data_start, &__data_end); 65 | zero_section(&__sbss_start, &__sbss_end); 66 | zero_section(&__bss_start, &__bss_end); 67 | 68 | main(1, argv); 69 | } 70 | 71 | /* Function called after main() finishes */ 72 | void 73 | _fini() 74 | { 75 | } 76 | 77 | #ifdef __cplusplus 78 | } 79 | #endif 80 | 81 | -------------------------------------------------------------------------------- /Dhrystone/Readme.md: -------------------------------------------------------------------------------- 1 | # Dhrystone 2 | 3 | This Softconsole Makefile project is used for benchmarking purpose. Using dhrystone you can know the integer performance of th Mi-V processor based system. 4 | ## Mi-V Soft processor 5 | This example uses a Mi-V Soft processor MiV_RV32IMA_L1_AHB. The design is 6 | built for debugging MiV_RV32IMA_L1_AHB through the SmartFusion2 FPGA programming 7 | JTAG port using a FlashPro5. To achieve this the CoreJTAGDebug IP is used to 8 | connect to the JTAG port of the MiV_RV32IMA_L1_AHB. 9 | 10 | Optionally, The design can be build to use Olimex ARM-USB-TINY-H JTAG probe. 11 | For this,The JTAG pins must be routed through Fabric to the top level pins. 12 | 13 | All the platform/design specific definitions such as peripheral base addresses, 14 | system clock frequency etc. are included in hw_platform.h. The hw_platform.h is 15 | located at the root folder of this project. 16 | 17 | The MiV_RV32IMA_L1_AHB firmware projects needs the riscv_hal and the hal firmware 18 | (RISC-V HAL). 19 | 20 | The RISC-V HAL is available through Firmware catalog as well as the link below: 21 | https://github.com/RISCV-on-Microsemi-FPGA/Solutions/tree/master/Mi-V-Firmware 22 | 23 | 24 | ## How to use this example 25 | This example project requires USB-UART interface to be connected to a host PC. 26 | The host PC must connect to the serial port using a terminal emulator such as 27 | HyperTerminal or PuTTY configured as follows: 28 | 29 | * 115200 baud 30 | * 8 data bits 31 | * 1 stop bit 32 | * no parity 33 | * no flow control 34 | 35 | This example displays the Dhrystone results on the terminal. 36 | 37 | ## Target hardware 38 | 39 | This example project is targeted at a SmartFusion2 M2S150 advanced development kit. 40 | The example project is built using a clock frequency of 83MHz. Trying to execute 41 | this example project on a different design will result in incorrect baud rate 42 | being used by CoreUART and timer load value. 43 | 44 | This example project can be used with another design using a different clock 45 | configuration. This can be achieved by overwriting the content of this example 46 | project's "hw_platform.h" file with the correct data from your Libero design. 47 | 48 | An example design for SmartFusion2 150 Ad. Dev Kit is available at 49 | https://github.com/RISCV-on-Microsemi-FPGA/SmartFusion2-Advanced-Dev-Kit 50 | -------------------------------------------------------------------------------- /Dhrystone/Makefile: -------------------------------------------------------------------------------- 1 | LINKER_SCRIPT := ./riscv_hal/microsemi-riscv-ram.ld 2 | #LINKER_SCRIPT := all-ram.lds 3 | #LINKER_SCRIPT := ./riscv_hal/all-ram-2.lds 4 | #LINKER_SCRIPT := ./riscv_hal/link.lds 5 | 6 | C_DEFINES = -DMSCC_STDIO_THRU_CORE_UART_APB 7 | 8 | TARGET = dhrystone 9 | 10 | ASM_SRCS := 11 | C_SRCS := ./riscv_hal/init.c dhry_1.c dhry_2.c dhry_stubs.c dhry_printf.c 12 | RISCV_HAL_ASM_SRCS := ./riscv_hal/entry.S 13 | RISCV_HAL_C_SRCS := ./riscv_hal/syscall.c ./riscv_hal/riscv_hal.c ./riscv_hal/riscv_hal_stubs.c 14 | HEADERS := ./riscv_hal/encoding.h ./riscv_hal/riscv_plic.h dhry.h 15 | 16 | 17 | DHRYSTONE_CFLAGS := -DTIME -fno-inline -Wno-implicit 18 | 19 | C_SRCS += ./hal/hw_reg_access.c 20 | C_SRCS += ./drivers/CoreGPIO/core_gpio.c 21 | C_SRCS += ./drivers/CoreUARTapb/core_uart_apb.c 22 | C_SRCS += ./drivers/CoreTimer/core_timer.c 23 | 24 | INCLUDES += -I. 25 | INCLUDES += -I./riscv_hal 26 | INCLUDES += -I./drivers/CoreGPIO 27 | INCLUDES += -I./drivers/CoreUARTapb 28 | INCLUDES += -I./drivers/CoreTimer 29 | INCLUDES += -I./hal 30 | 31 | 32 | CC := riscv64-unknown-elf-gcc 33 | CFLAGS := $(DHRYSTONE_CFLAGS) -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder $(INCLUDES) $(C_DEFINES) 34 | LDFLAGS := -T $(LINKER_SCRIPT) -nostdlib -nostartfiles -lc -lgcc #--specs=nano.specs 35 | LDFLAGS += -L./riscv_hal 36 | 37 | ASM_OBJS := $(patsubst %.S,%.o,$(ASM_SRCS)) 38 | RISCV_HAL_ASM_OBJS := $(patsubst %.S,%.o,$(RISCV_HAL_ASM_SRCS)) 39 | C_OBJS := $(patsubst %.c,%.o,$(C_SRCS)) 40 | RISCV_HAL_C_OBJS := $(patsubst %.c,%.o,$(RISCV_HAL_C_SRCS)) 41 | 42 | $(TARGET).elf: $(ASM_OBJS) $(RISCV_HAL_ASM_OBJS) $(C_OBJS) $(RISCV_HAL_C_OBJS) $(LINKER_SCRIPT) 43 | $(CC) $(CFLAGS) $(ASM_OBJS) $(C_OBJS) $(RISCV_HAL_ASM_OBJS) $(RISCV_HAL_C_OBJS) -o $@ $(LDFLAGS) 44 | 45 | $(ASM_OBJS): %.o: %.S $(HEADERS) 46 | $(CC) $(CFLAGS) -c -o $@ $< 47 | 48 | $(RISCV_HAL_ASM_OBJS): %.o: %.S $(HEADERS) 49 | $(CC) $(CFLAGS) -c -o $@ $< 50 | 51 | $(C_OBJS): %.o: %.c $(HEADERS) 52 | $(CC) $(CFLAGS) -c -o $@ $< 53 | 54 | $(RISCV_HAL_C_OBJS): %.o: %.c $(HEADERS) 55 | $(CC) $(CFLAGS) -c -o $@ $< 56 | 57 | ELF_TO_IHEX = riscv64-unknown-elf-objcopy -O ihex --set-start 0 58 | ELF_TO_LST = -riscv64-unknown-elf-objdump --source --all-headers --demangle --line-numbers --wide "dhrystone.elf" > "dhrystone.lst" 59 | 60 | 61 | dhrystone.lst: dhrystone.elf 62 | $(ELF_TO_LST) 63 | 64 | default: $(TARGET).elf 65 | 66 | all: default $(TARGET).lst 67 | 68 | clean: 69 | rm -f dhrystone *.o ./riscv_hal/*.o dhrystone.lst dhrystone.elf 70 | 71 | .PHONY: clean all default 72 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/ymodem/ymodem.h: -------------------------------------------------------------------------------- 1 | /* ymodem for SmartFusion2 Bootloader 2 | * 3 | * copyright (c) 2015 Microsemi Inc 4 | * 5 | * based on ymodem for RTD Serial Recovery (rtdsr) 6 | * copyright (c) 2011 Pete B. 7 | * 8 | * based on ymodem.h for bootldr, copyright (c) 2001 John G Dorsey 9 | * 10 | * This program is free software; you can redistribute it and/or 11 | * modify it under the terms of the GNU General Public License as 12 | * published by the Free Software Foundation, either version 3 of 13 | * the License, or (at your option) any later version. 14 | * 15 | * This program is distributed in the hope that it will be useful, 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | * GNU General Public License for more details. 19 | * 20 | * You should have received a copy of the GNU General Public License 21 | * along with this program; if not, see . 22 | * 23 | * SVN $Revision: 8241 $ 24 | * SVN $Date: 2016-02-15 11:21:27 +0000 (Mon, 15 Feb 2016) $ 25 | * 26 | */ 27 | 28 | #if !defined(_YMODEM_H) 29 | #define _YMODEM_H 30 | 31 | #define PACKET_SEQNO_INDEX (1) 32 | #define PACKET_SEQNO_COMP_INDEX (2) 33 | 34 | #define PACKET_HEADER (3) /* start, block, block-complement */ 35 | #define PACKET_TRAILER (2) /* CRC bytes */ 36 | #define PACKET_OVERHEAD (PACKET_HEADER + PACKET_TRAILER) 37 | #define PACKET_SIZE (128) 38 | #define PACKET_1K_SIZE (1024) 39 | #define PACKET_TIMEOUT (1) 40 | 41 | #define FILE_NAME_LENGTH (64) 42 | #define FILE_SIZE_LENGTH (16) 43 | 44 | /* ASCII control codes: */ 45 | #define SOH (0x01) /* start of 128-byte data packet */ 46 | #define STX (0x02) /* start of 1024-byte data packet */ 47 | #define EOT (0x04) /* end of transmission */ 48 | #define ACK (0x06) /* receive OK */ 49 | #define NAK (0x15) /* receiver error; retry */ 50 | #define CAN (0x18) /* two of these in succession aborts transfer */ 51 | #define CRC (0x43) /* use in place of first NAK for CRC mode */ 52 | 53 | /* Number of consecutive receive errors before giving up: */ 54 | #define MAX_ERRORS (5) 55 | 56 | void sf2bl_ymodem_init(void); 57 | void sf2bl_ymodem_deinit(void); 58 | uint32_t ymodem_receive(uint8_t *buf, uint32_t length); 59 | uint16_t sf2bl_crc16(const uint8_t *buf, uint32_t count); 60 | void _putchar(int32_t data); 61 | void _putstring(uint8_t *string); 62 | 63 | #endif /* !define(_YMODEM_H) */ 64 | -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/shared.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef SIFIVE_SHARED_H 4 | #define SIFIVE_SHARED_H 5 | 6 | #include "riscv_hal.h" 7 | #include "../drivers/CoreUARTapb/core_uart_apb.h" 8 | #include "../drivers/CoreGPIO/core_gpio.h" 9 | #include "../drivers/CoreTIMER/core_timer.h" 10 | #include "riscv_plic.h" 11 | 12 | #define PLIC_BASE_ADDR 0x40000000UL 13 | #define COREUARTAPB0_BASE_ADDR 0x70001000UL 14 | #define COREGPIO_IN_BASE_ADDR 0x70002000UL 15 | #define COREGPIO_OUT_BASE_ADDR 0x70005000UL 16 | 17 | #define CORETIMER0_BASE_ADDR 0x70003000UL 18 | 19 | 20 | #define CORETIMER1_BASE_ADDR 0x70004000UL 21 | 22 | /**************************************************************************** 23 | * External Interrupts. Note that these are off-by-one from their pin of 24 | * InterruptVector[30:0], because PLIC's DEVICE_0 is unused. 25 | *****************************************************************************/ 26 | // Buttons & Switches 27 | #define INT_DEVICE_BUTTON_0 1 28 | #define INT_DEVICE_BUTTON_1 2 29 | #define INT_DEVICE_BUTTON_2 3 30 | #define INT_DEVICE_BUTTON_3 4 31 | #define INT_DEVICE_SWITCHES_0 5 32 | #define INT_DEVICE_SWITCHES_1 6 33 | #define INT_DEVICE_SWITCHES_2 7 34 | #define INT_DEVICE_SWITCHES_3 8 35 | //UART 36 | #define INT_DEVICE_UTXRDY 25 37 | #define INT_DEVICE_URXRDY 26 38 | #define INT_DEVICE_UPARITY 27 39 | #define INT_DEVICE_UOVERFLOW 28 40 | #define INT_DEVICE_UFRAMING 29 41 | //CoreTimer 42 | #define INT_DEVICE_TIMER0 30 43 | #define INT_DEVICE_TIMER1 31 44 | 45 | // Setting these correctly makes the initialization scripts 46 | // run faster. 47 | #define PLIC_NUM_SOURCES 31 48 | #define PLIC_NUM_PRIORITIES 0 49 | 50 | extern UART_instance_t g_uart; 51 | 52 | void write_hex(int fd, uint32_t hex); 53 | 54 | /**************************************************************************** 55 | * Baud value to achieve a 115200 baud rate with a 100MHz system clock. 56 | * This value is calculated using the following equation: 57 | * BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1 58 | *****************************************************************************/ 59 | //#define BAUD_VALUE_115200 53 60 | 61 | /**************************************************************************** 62 | * Baud value to achieve a 115200 baud rate with a 83MHz system clock. 63 | * This value is calculated using the following equation: 64 | * BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1 65 | *****************************************************************************/ 66 | #define BAUD_VALUE_115200 44 67 | 68 | #endif 69 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/main.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * This SoftConsole example project demonstrates how to configure and use the 5 | * MiV_RV32IM_L1_AHB system timer. 6 | * 7 | * Please refer README.TXT in the root folder of this project for more details. 8 | */ 9 | #include "riscv_hal.h" 10 | #include "hw_platform.h" 11 | #include "core_uart_apb.h" 12 | #include "core_gpio.h" 13 | 14 | const char * g_hello_msg = 15 | "\r\n System timer Blinky Example \n\r\n\r\ 16 | Observe the LEDs blinking on the board. The LED pattern changes \ 17 | every time a system timer interrupt occurs\r\n"; 18 | 19 | /*----------------------------------------------------------------------------- 20 | * UART instance data. 21 | */ 22 | UART_instance_t g_uart; 23 | 24 | /*----------------------------------------------------------------------------- 25 | * GPIO instance data. 26 | */ 27 | 28 | gpio_instance_t g_gpio_in; 29 | gpio_instance_t g_gpio_out; 30 | 31 | /*----------------------------------------------------------------------------- 32 | * Global state counter. 33 | */ 34 | uint32_t g_state = 1; 35 | 36 | /*----------------------------------------------------------------------------- 37 | * System Tick interrupt handler 38 | */ 39 | void SysTick_Handler(void) { 40 | uint32_t stable; 41 | uint32_t gpout; 42 | 43 | stable = GPIO_get_inputs(&g_gpio_in); 44 | gpout = ~stable & 0x000000F0; 45 | 46 | g_state = g_state << 1; 47 | if (g_state > 4) { 48 | g_state = 0x01; 49 | } 50 | gpout = gpout | g_state; 51 | 52 | GPIO_set_outputs(&g_gpio_out, gpout); 53 | UART_polled_tx_string(&g_uart, (const uint8_t *)"tick\r\n"); 54 | } 55 | 56 | /*----------------------------------------------------------------------------- 57 | * main 58 | */ 59 | int main(int argc, char **argv) { 60 | uint8_t rx_char; 61 | uint8_t rx_count; 62 | 63 | PLIC_init(); 64 | 65 | GPIO_init(&g_gpio_in, COREGPIO_IN_BASE_ADDR, GPIO_APB_32_BITS_BUS); 66 | GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS); 67 | 68 | UART_init(&g_uart, 69 | COREUARTAPB0_BASE_ADDR, 70 | BAUD_VALUE_115200, 71 | (DATA_8_BITS | NO_PARITY)); 72 | 73 | UART_polled_tx_string(&g_uart, (const uint8_t *)g_hello_msg); 74 | 75 | SysTick_Config(SYS_CLK_FREQ); 76 | 77 | /* 78 | * Loop. Echo back characters received on UART. 79 | */ 80 | do { 81 | rx_count = UART_get_rx(&g_uart, &rx_char, 1); 82 | if (rx_count > 0) { 83 | UART_send(&g_uart, &rx_char, 1); 84 | } 85 | } while (1); 86 | 87 | 88 | return 0; 89 | } 90 | 91 | -------------------------------------------------------------------------------- /Dhrystone/drivers/CoreTimer/coretimer_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9665 $ 5 | * SVN $Date: 2018-01-16 16:41:53 +0530 (Tue, 16 Jan 2018) $ 6 | */ 7 | 8 | #ifndef __CORE_TIMER_REGISTERS 9 | #define __CORE_TIMER_REGISTERS 1 10 | 11 | /*------------------------------------------------------------------------------ 12 | * TimerLoad register details 13 | */ 14 | #define TimerLoad_REG_OFFSET 0x00 15 | 16 | /* 17 | * LoadValue bits. 18 | */ 19 | #define LoadValue_OFFSET 0x00 20 | #define LoadValue_MASK 0xFFFFFFFF 21 | #define LoadValue_SHIFT 0 22 | 23 | /*------------------------------------------------------------------------------ 24 | * TimerValue register details 25 | */ 26 | #define TimerValue_REG_OFFSET 0x04 27 | 28 | /* 29 | * CurrentValue bits. 30 | */ 31 | #define CurrentValue_OFFSET 0x04 32 | #define CurrentValue_MASK 0xFFFFFFFF 33 | #define CurrentValue_SHIFT 0 34 | 35 | /*------------------------------------------------------------------------------ 36 | * TimerControl register details 37 | */ 38 | #define TimerControl_REG_OFFSET 0x08 39 | 40 | /* 41 | * TimerEnable bits. 42 | */ 43 | #define TimerEnable_OFFSET 0x08 44 | #define TimerEnable_MASK 0x00000001 45 | #define TimerEnable_SHIFT 0 46 | 47 | /* 48 | * InterruptEnable bits. 49 | */ 50 | #define InterruptEnable_OFFSET 0x08 51 | #define InterruptEnable_MASK 0x00000002 52 | #define InterruptEnable_SHIFT 1 53 | 54 | /* 55 | * TimerMode bits. 56 | */ 57 | #define TimerMode_OFFSET 0x08 58 | #define TimerMode_MASK 0x00000004 59 | #define TimerMode_SHIFT 2 60 | 61 | /*------------------------------------------------------------------------------ 62 | * TimerPrescale register details 63 | */ 64 | #define TimerPrescale_REG_OFFSET 0x0C 65 | 66 | /* 67 | * Prescale bits. 68 | */ 69 | #define Prescale_OFFSET 0x0C 70 | #define Prescale_MASK 0x0000000F 71 | #define Prescale_SHIFT 0 72 | 73 | /*------------------------------------------------------------------------------ 74 | * TimerIntClr register details 75 | */ 76 | #define TimerIntClr_REG_OFFSET 0x10 77 | 78 | /* 79 | * TimerIntClr bits. 80 | */ 81 | #define TimerIntClr_OFFSET 0x10 82 | #define TimerIntClr_MASK 0xFFFFFFFF 83 | #define TimerIntClr_SHIFT 0 84 | 85 | /*------------------------------------------------------------------------------ 86 | * TimerRIS register details 87 | */ 88 | #define TimerRIS_REG_OFFSET 0x14 89 | 90 | /* 91 | * RawTimerInterrupt bits. 92 | */ 93 | #define RawTimerInterrupt_OFFSET 0x14 94 | #define RawTimerInterrupt_MASK 0x00000001 95 | #define RawTimerInterrupt_SHIFT 0 96 | 97 | /*------------------------------------------------------------------------------ 98 | * TimerMIS register details 99 | */ 100 | #define TimerMIS_REG_OFFSET 0x18 101 | 102 | /* 103 | * TimerInterrupt bits. 104 | */ 105 | #define TimerInterrupt_OFFSET 0x18 106 | #define TimerInterrupt_MASK 0x00000001 107 | #define TimerInterrupt_SHIFT 0 108 | 109 | #endif /* __CORE_TIMER_REGISTERS */ 110 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/drivers/CoreTimer/coretimer_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 8933 $ 5 | * SVN $Date: 2017-03-31 13:54:33 +0530 (Fri, 31 Mar 2017) $ 6 | */ 7 | 8 | #ifndef __CORE_TIMER_REGISTERS 9 | #define __CORE_TIMER_REGISTERS 1 10 | 11 | /*------------------------------------------------------------------------------ 12 | * TimerLoad register details 13 | */ 14 | #define TimerLoad_REG_OFFSET 0x00 15 | 16 | /* 17 | * LoadValue bits. 18 | */ 19 | #define LoadValue_OFFSET 0x00 20 | #define LoadValue_MASK 0xFFFFFFFF 21 | #define LoadValue_SHIFT 0 22 | 23 | /*------------------------------------------------------------------------------ 24 | * TimerValue register details 25 | */ 26 | #define TimerValue_REG_OFFSET 0x04 27 | 28 | /* 29 | * CurrentValue bits. 30 | */ 31 | #define CurrentValue_OFFSET 0x04 32 | #define CurrentValue_MASK 0xFFFFFFFF 33 | #define CurrentValue_SHIFT 0 34 | 35 | /*------------------------------------------------------------------------------ 36 | * TimerControl register details 37 | */ 38 | #define TimerControl_REG_OFFSET 0x08 39 | 40 | /* 41 | * TimerEnable bits. 42 | */ 43 | #define TimerEnable_OFFSET 0x08 44 | #define TimerEnable_MASK 0x00000001 45 | #define TimerEnable_SHIFT 0 46 | 47 | /* 48 | * InterruptEnable bits. 49 | */ 50 | #define InterruptEnable_OFFSET 0x08 51 | #define InterruptEnable_MASK 0x00000002 52 | #define InterruptEnable_SHIFT 1 53 | 54 | /* 55 | * TimerMode bits. 56 | */ 57 | #define TimerMode_OFFSET 0x08 58 | #define TimerMode_MASK 0x00000004 59 | #define TimerMode_SHIFT 2 60 | 61 | /*------------------------------------------------------------------------------ 62 | * TimerPrescale register details 63 | */ 64 | #define TimerPrescale_REG_OFFSET 0x0C 65 | 66 | /* 67 | * Prescale bits. 68 | */ 69 | #define Prescale_OFFSET 0x0C 70 | #define Prescale_MASK 0x0000000F 71 | #define Prescale_SHIFT 0 72 | 73 | /*------------------------------------------------------------------------------ 74 | * TimerIntClr register details 75 | */ 76 | #define TimerIntClr_REG_OFFSET 0x10 77 | 78 | /* 79 | * TimerIntClr bits. 80 | */ 81 | #define TimerIntClr_OFFSET 0x10 82 | #define TimerIntClr_MASK 0xFFFFFFFF 83 | #define TimerIntClr_SHIFT 0 84 | 85 | /*------------------------------------------------------------------------------ 86 | * TimerRIS register details 87 | */ 88 | #define TimerRIS_REG_OFFSET 0x14 89 | 90 | /* 91 | * RawTimerInterrupt bits. 92 | */ 93 | #define RawTimerInterrupt_OFFSET 0x14 94 | #define RawTimerInterrupt_MASK 0x00000001 95 | #define RawTimerInterrupt_SHIFT 0 96 | 97 | /*------------------------------------------------------------------------------ 98 | * TimerMIS register details 99 | */ 100 | #define TimerMIS_REG_OFFSET 0x18 101 | 102 | /* 103 | * TimerInterrupt bits. 104 | */ 105 | #define TimerInterrupt_OFFSET 0x18 106 | #define TimerInterrupt_MASK 0x00000001 107 | #define TimerInterrupt_SHIFT 0 108 | 109 | #endif /* __CORE_TIMER_REGISTERS */ 110 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/drivers/CoreTimer/coretimer_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 8933 $ 5 | * SVN $Date: 2017-03-31 13:54:33 +0530 (Fri, 31 Mar 2017) $ 6 | */ 7 | 8 | #ifndef __CORE_TIMER_REGISTERS 9 | #define __CORE_TIMER_REGISTERS 1 10 | 11 | /*------------------------------------------------------------------------------ 12 | * TimerLoad register details 13 | */ 14 | #define TimerLoad_REG_OFFSET 0x00 15 | 16 | /* 17 | * LoadValue bits. 18 | */ 19 | #define LoadValue_OFFSET 0x00 20 | #define LoadValue_MASK 0xFFFFFFFF 21 | #define LoadValue_SHIFT 0 22 | 23 | /*------------------------------------------------------------------------------ 24 | * TimerValue register details 25 | */ 26 | #define TimerValue_REG_OFFSET 0x04 27 | 28 | /* 29 | * CurrentValue bits. 30 | */ 31 | #define CurrentValue_OFFSET 0x04 32 | #define CurrentValue_MASK 0xFFFFFFFF 33 | #define CurrentValue_SHIFT 0 34 | 35 | /*------------------------------------------------------------------------------ 36 | * TimerControl register details 37 | */ 38 | #define TimerControl_REG_OFFSET 0x08 39 | 40 | /* 41 | * TimerEnable bits. 42 | */ 43 | #define TimerEnable_OFFSET 0x08 44 | #define TimerEnable_MASK 0x00000001 45 | #define TimerEnable_SHIFT 0 46 | 47 | /* 48 | * InterruptEnable bits. 49 | */ 50 | #define InterruptEnable_OFFSET 0x08 51 | #define InterruptEnable_MASK 0x00000002 52 | #define InterruptEnable_SHIFT 1 53 | 54 | /* 55 | * TimerMode bits. 56 | */ 57 | #define TimerMode_OFFSET 0x08 58 | #define TimerMode_MASK 0x00000004 59 | #define TimerMode_SHIFT 2 60 | 61 | /*------------------------------------------------------------------------------ 62 | * TimerPrescale register details 63 | */ 64 | #define TimerPrescale_REG_OFFSET 0x0C 65 | 66 | /* 67 | * Prescale bits. 68 | */ 69 | #define Prescale_OFFSET 0x0C 70 | #define Prescale_MASK 0x0000000F 71 | #define Prescale_SHIFT 0 72 | 73 | /*------------------------------------------------------------------------------ 74 | * TimerIntClr register details 75 | */ 76 | #define TimerIntClr_REG_OFFSET 0x10 77 | 78 | /* 79 | * TimerIntClr bits. 80 | */ 81 | #define TimerIntClr_OFFSET 0x10 82 | #define TimerIntClr_MASK 0xFFFFFFFF 83 | #define TimerIntClr_SHIFT 0 84 | 85 | /*------------------------------------------------------------------------------ 86 | * TimerRIS register details 87 | */ 88 | #define TimerRIS_REG_OFFSET 0x14 89 | 90 | /* 91 | * RawTimerInterrupt bits. 92 | */ 93 | #define RawTimerInterrupt_OFFSET 0x14 94 | #define RawTimerInterrupt_MASK 0x00000001 95 | #define RawTimerInterrupt_SHIFT 0 96 | 97 | /*------------------------------------------------------------------------------ 98 | * TimerMIS register details 99 | */ 100 | #define TimerMIS_REG_OFFSET 0x18 101 | 102 | /* 103 | * TimerInterrupt bits. 104 | */ 105 | #define TimerInterrupt_OFFSET 0x18 106 | #define TimerInterrupt_MASK 0x00000001 107 | #define TimerInterrupt_SHIFT 0 108 | 109 | #endif /* __CORE_TIMER_REGISTERS */ 110 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/README.txt: -------------------------------------------------------------------------------- 1 | ================================================================================ 2 | RISC-V simple bare metal bootloader example project 3 | ================================================================================ 4 | 5 | Simple boot-loader example program. 6 | * This sample project is targeted at a RISC-V design running on the M2S150 development board. 7 | * You can program the on board SPI Flash from a command line program and have the 8 | boot-loader load a program from SPI Flash and jump to it. 9 | * These actions are driven from a serial command line interface. 10 | 11 | -------------------------------------------------------------------------------- 12 | Mi-V Soft processor 13 | -------------------------------------------------------------------------------- 14 | This example uses a Mi-V Soft processor MiV_RV32IM_L1_AHB. The design is 15 | built for debugging MiV_RV32IM_L1_AHB through the SmartFusion2 FPGA programming 16 | JTAG port using a FlashPro5. To achieve this the CoreJTAGDebug IP is used to 17 | connect to the JTAG port of the MiV_RV32IM_L1_AHB. 18 | 19 | Optionally, The design can be build to use Olimex ARM-USB-TINY-H JTAG probe. 20 | For this,The JTAG pins must be routed through Fabric to the top level pins. 21 | 22 | All the platform/design specific definitions such as peripheral base addresses, 23 | system clock frequency etc. are included in hw_platform.h. The hw_platform.h is 24 | located at the root folder of this project. 25 | 26 | The MiV_RV32IM_L1_AHB firmware projects needs the riscv_hal and the hal firmware 27 | (RISC-V HAL). 28 | 29 | The RISC-V HAL is available through Firmware catalog as well as the link below: 30 | 31 | https://github.com/RISCV-on-Microsemi-FPGA/Solutions/tree/master/Mi-V-Firmware 32 | -------------------------------------------------------------------------------- 33 | How to use this example 34 | -------------------------------------------------------------------------------- 35 | This example project requires USB-UART interface to be connected to a host PC. 36 | The host PC must connect to the serial port using a terminal emulator such as 37 | HyperTerminal or PuTTY configured as follows: 38 | - 115200 baud 39 | - 8 data bits 40 | - 1 stop bit 41 | - no parity 42 | - no flow control 43 | 44 | This example displays a message on HyperTerminal. Use the interactive user interface 45 | to give commands from HyperTerminal. 46 | 47 | -------------------------------------------------------------------------------- 48 | Target hardware 49 | -------------------------------------------------------------------------------- 50 | This example project is targeted at a SmartFusion2 M2S150 advanced development kit 51 | design which has CoreTimer enabled. 52 | The example project is built using a clock frequency of 83MHz. Trying to execute 53 | this example project on a different design will result in incorrect baud rate 54 | being used by CoreUART and timer load value. 55 | 56 | This example project can be used with another design using a different clock 57 | configuration. This can be achieved by overwriting the content of this example 58 | project's "hw_platform.h" file with the correct data from your Libero design. 59 | 60 | An example design for SmartFusion2 150 Ad. Dev Kit is available at 61 | https://github.com/RISCV-on-Microsemi-FPGA/SmartFusion2-Advanced-Dev-Kit 62 | -------------------------------------------------------------------------------- /Dhrystone/drivers/CoreUARTapb/coreuartapb_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9746 $ 5 | * SVN $Date: 2018-02-12 17:59:59 +0530 (Mon, 12 Feb 2018) $ 6 | */ 7 | 8 | #ifndef __CORE_UART_APB_REGISTERS 9 | #define __CORE_UART_APB_REGISTERS 1 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | /*------------------------------------------------------------------------------ 16 | * TxData register details 17 | */ 18 | #define TXDATA_REG_OFFSET 0x0u 19 | 20 | /* 21 | * TxData bits. 22 | */ 23 | #define TXDATA_OFFSET 0x0u 24 | #define TXDATA_MASK 0xFFu 25 | #define TXDATA_SHIFT 0u 26 | 27 | /*------------------------------------------------------------------------------ 28 | * RxData register details 29 | */ 30 | #define RXDATA_REG_OFFSET 0x4u 31 | 32 | /* 33 | * RxData bits. 34 | */ 35 | #define RXDATA_OFFSET 0x4u 36 | #define RXDATA_MASK 0xFFu 37 | #define RXDATA_SHIFT 0u 38 | 39 | /*------------------------------------------------------------------------------ 40 | * ControReg1 register details 41 | */ 42 | #define CTRL1_REG_OFFSET 0x8u 43 | 44 | /* 45 | * Baud value (Lower 8-bits) 46 | */ 47 | #define CTRL1_BAUDVALUE_OFFSET 0x8u 48 | #define CTRL1_BAUDVALUE_MASK 0xFFu 49 | #define CTRL1_BAUDVALUE_SHIFT 0u 50 | 51 | /*------------------------------------------------------------------------------ 52 | * ControReg2 register details 53 | */ 54 | #define CTRL2_REG_OFFSET 0xCu 55 | 56 | /* 57 | * Bit length 58 | */ 59 | #define CTRL2_BIT_LENGTH_OFFSET 0xCu 60 | #define CTRL2_BIT_LENGTH_MASK 0x01u 61 | #define CTRL2_BIT_LENGTH_SHIFT 0u 62 | 63 | /* 64 | * Parity enable. 65 | */ 66 | #define CTRL2_PARITY_EN_OFFSET 0xCu 67 | #define CTRL2_PARITY_EN_MASK 0x02u 68 | #define CTRL2_PARITY_EN_SHIFT 1u 69 | 70 | /* 71 | * Odd/even parity selection. 72 | */ 73 | #define CTRL2_ODD_EVEN_OFFSET 0xCu 74 | #define CTRL2_ODD_EVEN_MASK 0x04u 75 | #define CTRL2_ODD_EVEN_SHIFT 2u 76 | 77 | /* 78 | * Baud value (Higher 5-bits) 79 | */ 80 | #define CTRL2_BAUDVALUE_OFFSET 0xCu 81 | #define CTRL2_BAUDVALUE_MASK 0xF8u 82 | #define CTRL2_BAUDVALUE_SHIFT 3u 83 | 84 | /*------------------------------------------------------------------------------ 85 | * StatusReg register details 86 | */ 87 | #define StatusReg_REG_OFFSET 0x10u 88 | 89 | #define STATUS_REG_OFFSET 0x10u 90 | 91 | /* 92 | * Transmit ready. 93 | */ 94 | #define STATUS_TXRDY_OFFSET 0x10u 95 | #define STATUS_TXRDY_MASK 0x01u 96 | #define STATUS_TXRDY_SHIFT 0u 97 | 98 | /* 99 | * Receive full. 100 | */ 101 | #define STATUS_RXFULL_OFFSET 0x10u 102 | #define STATUS_RXFULL_MASK 0x02u 103 | #define STATUS_RXFULL_SHIFT 1u 104 | 105 | /* 106 | * Parity error. 107 | */ 108 | #define STATUS_PARITYERR_OFFSET 0x10u 109 | #define STATUS_PARITYERR_MASK 0x04u 110 | #define STATUS_PARITYERR_SHIFT 2u 111 | 112 | /* 113 | * Overflow. 114 | */ 115 | #define STATUS_OVERFLOW_OFFSET 0x10u 116 | #define STATUS_OVERFLOW_MASK 0x08u 117 | #define STATUS_OVERFLOW_SHIFT 3u 118 | 119 | /* 120 | * Frame Error. 121 | */ 122 | #define STATUS_FRAMERR_OFFSET 0x10u 123 | #define STATUS_FRAMERR_MASK 0x10u 124 | #define STATUS_FRAMERR_SHIFT 4u 125 | 126 | #ifdef __cplusplus 127 | } 128 | #endif 129 | 130 | #endif /* __CORE_UART_APB_REGISTERS */ 131 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/drivers/CoreUARTapb/coreuartapb_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9082 $ 5 | * SVN $Date: 2017-04-28 11:51:36 +0530 (Fri, 28 Apr 2017) $ 6 | */ 7 | 8 | #ifndef __CORE_UART_APB_REGISTERS 9 | #define __CORE_UART_APB_REGISTERS 1 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | /*------------------------------------------------------------------------------ 16 | * TxData register details 17 | */ 18 | #define TXDATA_REG_OFFSET 0x0u 19 | 20 | /* 21 | * TxData bits. 22 | */ 23 | #define TXDATA_OFFSET 0x0u 24 | #define TXDATA_MASK 0xFFu 25 | #define TXDATA_SHIFT 0u 26 | 27 | /*------------------------------------------------------------------------------ 28 | * RxData register details 29 | */ 30 | #define RXDATA_REG_OFFSET 0x4u 31 | 32 | /* 33 | * RxData bits. 34 | */ 35 | #define RXDATA_OFFSET 0x4u 36 | #define RXDATA_MASK 0xFFu 37 | #define RXDATA_SHIFT 0u 38 | 39 | /*------------------------------------------------------------------------------ 40 | * ControReg1 register details 41 | */ 42 | #define CTRL1_REG_OFFSET 0x8u 43 | 44 | /* 45 | * Baud value (Lower 8-bits) 46 | */ 47 | #define CTRL1_BAUDVALUE_OFFSET 0x8u 48 | #define CTRL1_BAUDVALUE_MASK 0xFFu 49 | #define CTRL1_BAUDVALUE_SHIFT 0u 50 | 51 | /*------------------------------------------------------------------------------ 52 | * ControReg2 register details 53 | */ 54 | #define CTRL2_REG_OFFSET 0xCu 55 | 56 | /* 57 | * Bit length 58 | */ 59 | #define CTRL2_BIT_LENGTH_OFFSET 0xCu 60 | #define CTRL2_BIT_LENGTH_MASK 0x01u 61 | #define CTRL2_BIT_LENGTH_SHIFT 0u 62 | 63 | /* 64 | * Parity enable. 65 | */ 66 | #define CTRL2_PARITY_EN_OFFSET 0xCu 67 | #define CTRL2_PARITY_EN_MASK 0x02u 68 | #define CTRL2_PARITY_EN_SHIFT 1u 69 | 70 | /* 71 | * Odd/even parity selection. 72 | */ 73 | #define CTRL2_ODD_EVEN_OFFSET 0xCu 74 | #define CTRL2_ODD_EVEN_MASK 0x04u 75 | #define CTRL2_ODD_EVEN_SHIFT 2u 76 | 77 | /* 78 | * Baud value (Higher 5-bits) 79 | */ 80 | #define CTRL2_BAUDVALUE_OFFSET 0xCu 81 | #define CTRL2_BAUDVALUE_MASK 0xF8u 82 | #define CTRL2_BAUDVALUE_SHIFT 3u 83 | 84 | /*------------------------------------------------------------------------------ 85 | * StatusReg register details 86 | */ 87 | #define StatusReg_REG_OFFSET 0x10u 88 | 89 | #define STATUS_REG_OFFSET 0x10u 90 | 91 | /* 92 | * Transmit ready. 93 | */ 94 | #define STATUS_TXRDY_OFFSET 0x10u 95 | #define STATUS_TXRDY_MASK 0x01u 96 | #define STATUS_TXRDY_SHIFT 0u 97 | 98 | /* 99 | * Receive full. 100 | */ 101 | #define STATUS_RXFULL_OFFSET 0x10u 102 | #define STATUS_RXFULL_MASK 0x02u 103 | #define STATUS_RXFULL_SHIFT 1u 104 | 105 | /* 106 | * Parity error. 107 | */ 108 | #define STATUS_PARITYERR_OFFSET 0x10u 109 | #define STATUS_PARITYERR_MASK 0x04u 110 | #define STATUS_PARITYERR_SHIFT 2u 111 | 112 | /* 113 | * Overflow. 114 | */ 115 | #define STATUS_OVERFLOW_OFFSET 0x10u 116 | #define STATUS_OVERFLOW_MASK 0x08u 117 | #define STATUS_OVERFLOW_SHIFT 3u 118 | 119 | /* 120 | * Frame Error. 121 | */ 122 | #define STATUS_FRAMERR_OFFSET 0x10u 123 | #define STATUS_FRAMERR_MASK 0x10u 124 | #define STATUS_FRAMERR_SHIFT 4u 125 | 126 | #ifdef __cplusplus 127 | } 128 | #endif 129 | 130 | #endif /* __CORE_UART_APB_REGISTERS */ 131 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/drivers/CoreUARTapb/coreuartapb_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9082 $ 5 | * SVN $Date: 2017-04-28 11:51:36 +0530 (Fri, 28 Apr 2017) $ 6 | */ 7 | 8 | #ifndef __CORE_UART_APB_REGISTERS 9 | #define __CORE_UART_APB_REGISTERS 1 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | /*------------------------------------------------------------------------------ 16 | * TxData register details 17 | */ 18 | #define TXDATA_REG_OFFSET 0x0u 19 | 20 | /* 21 | * TxData bits. 22 | */ 23 | #define TXDATA_OFFSET 0x0u 24 | #define TXDATA_MASK 0xFFu 25 | #define TXDATA_SHIFT 0u 26 | 27 | /*------------------------------------------------------------------------------ 28 | * RxData register details 29 | */ 30 | #define RXDATA_REG_OFFSET 0x4u 31 | 32 | /* 33 | * RxData bits. 34 | */ 35 | #define RXDATA_OFFSET 0x4u 36 | #define RXDATA_MASK 0xFFu 37 | #define RXDATA_SHIFT 0u 38 | 39 | /*------------------------------------------------------------------------------ 40 | * ControReg1 register details 41 | */ 42 | #define CTRL1_REG_OFFSET 0x8u 43 | 44 | /* 45 | * Baud value (Lower 8-bits) 46 | */ 47 | #define CTRL1_BAUDVALUE_OFFSET 0x8u 48 | #define CTRL1_BAUDVALUE_MASK 0xFFu 49 | #define CTRL1_BAUDVALUE_SHIFT 0u 50 | 51 | /*------------------------------------------------------------------------------ 52 | * ControReg2 register details 53 | */ 54 | #define CTRL2_REG_OFFSET 0xCu 55 | 56 | /* 57 | * Bit length 58 | */ 59 | #define CTRL2_BIT_LENGTH_OFFSET 0xCu 60 | #define CTRL2_BIT_LENGTH_MASK 0x01u 61 | #define CTRL2_BIT_LENGTH_SHIFT 0u 62 | 63 | /* 64 | * Parity enable. 65 | */ 66 | #define CTRL2_PARITY_EN_OFFSET 0xCu 67 | #define CTRL2_PARITY_EN_MASK 0x02u 68 | #define CTRL2_PARITY_EN_SHIFT 1u 69 | 70 | /* 71 | * Odd/even parity selection. 72 | */ 73 | #define CTRL2_ODD_EVEN_OFFSET 0xCu 74 | #define CTRL2_ODD_EVEN_MASK 0x04u 75 | #define CTRL2_ODD_EVEN_SHIFT 2u 76 | 77 | /* 78 | * Baud value (Higher 5-bits) 79 | */ 80 | #define CTRL2_BAUDVALUE_OFFSET 0xCu 81 | #define CTRL2_BAUDVALUE_MASK 0xF8u 82 | #define CTRL2_BAUDVALUE_SHIFT 3u 83 | 84 | /*------------------------------------------------------------------------------ 85 | * StatusReg register details 86 | */ 87 | #define StatusReg_REG_OFFSET 0x10u 88 | 89 | #define STATUS_REG_OFFSET 0x10u 90 | 91 | /* 92 | * Transmit ready. 93 | */ 94 | #define STATUS_TXRDY_OFFSET 0x10u 95 | #define STATUS_TXRDY_MASK 0x01u 96 | #define STATUS_TXRDY_SHIFT 0u 97 | 98 | /* 99 | * Receive full. 100 | */ 101 | #define STATUS_RXFULL_OFFSET 0x10u 102 | #define STATUS_RXFULL_MASK 0x02u 103 | #define STATUS_RXFULL_SHIFT 1u 104 | 105 | /* 106 | * Parity error. 107 | */ 108 | #define STATUS_PARITYERR_OFFSET 0x10u 109 | #define STATUS_PARITYERR_MASK 0x04u 110 | #define STATUS_PARITYERR_SHIFT 2u 111 | 112 | /* 113 | * Overflow. 114 | */ 115 | #define STATUS_OVERFLOW_OFFSET 0x10u 116 | #define STATUS_OVERFLOW_MASK 0x08u 117 | #define STATUS_OVERFLOW_SHIFT 3u 118 | 119 | /* 120 | * Frame Error. 121 | */ 122 | #define STATUS_FRAMERR_OFFSET 0x10u 123 | #define STATUS_FRAMERR_MASK 0x10u 124 | #define STATUS_FRAMERR_SHIFT 4u 125 | 126 | #ifdef __cplusplus 127 | } 128 | #endif 129 | 130 | #endif /* __CORE_UART_APB_REGISTERS */ 131 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/drivers/CoreUARTapb/coreuartapb_regs.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * SVN $Revision: 9082 $ 5 | * SVN $Date: 2017-04-28 11:51:36 +0530 (Fri, 28 Apr 2017) $ 6 | */ 7 | 8 | #ifndef __CORE_UART_APB_REGISTERS 9 | #define __CORE_UART_APB_REGISTERS 1 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | /*------------------------------------------------------------------------------ 16 | * TxData register details 17 | */ 18 | #define TXDATA_REG_OFFSET 0x0u 19 | 20 | /* 21 | * TxData bits. 22 | */ 23 | #define TXDATA_OFFSET 0x0u 24 | #define TXDATA_MASK 0xFFu 25 | #define TXDATA_SHIFT 0u 26 | 27 | /*------------------------------------------------------------------------------ 28 | * RxData register details 29 | */ 30 | #define RXDATA_REG_OFFSET 0x4u 31 | 32 | /* 33 | * RxData bits. 34 | */ 35 | #define RXDATA_OFFSET 0x4u 36 | #define RXDATA_MASK 0xFFu 37 | #define RXDATA_SHIFT 0u 38 | 39 | /*------------------------------------------------------------------------------ 40 | * ControReg1 register details 41 | */ 42 | #define CTRL1_REG_OFFSET 0x8u 43 | 44 | /* 45 | * Baud value (Lower 8-bits) 46 | */ 47 | #define CTRL1_BAUDVALUE_OFFSET 0x8u 48 | #define CTRL1_BAUDVALUE_MASK 0xFFu 49 | #define CTRL1_BAUDVALUE_SHIFT 0u 50 | 51 | /*------------------------------------------------------------------------------ 52 | * ControReg2 register details 53 | */ 54 | #define CTRL2_REG_OFFSET 0xCu 55 | 56 | /* 57 | * Bit length 58 | */ 59 | #define CTRL2_BIT_LENGTH_OFFSET 0xCu 60 | #define CTRL2_BIT_LENGTH_MASK 0x01u 61 | #define CTRL2_BIT_LENGTH_SHIFT 0u 62 | 63 | /* 64 | * Parity enable. 65 | */ 66 | #define CTRL2_PARITY_EN_OFFSET 0xCu 67 | #define CTRL2_PARITY_EN_MASK 0x02u 68 | #define CTRL2_PARITY_EN_SHIFT 1u 69 | 70 | /* 71 | * Odd/even parity selection. 72 | */ 73 | #define CTRL2_ODD_EVEN_OFFSET 0xCu 74 | #define CTRL2_ODD_EVEN_MASK 0x04u 75 | #define CTRL2_ODD_EVEN_SHIFT 2u 76 | 77 | /* 78 | * Baud value (Higher 5-bits) 79 | */ 80 | #define CTRL2_BAUDVALUE_OFFSET 0xCu 81 | #define CTRL2_BAUDVALUE_MASK 0xF8u 82 | #define CTRL2_BAUDVALUE_SHIFT 3u 83 | 84 | /*------------------------------------------------------------------------------ 85 | * StatusReg register details 86 | */ 87 | #define StatusReg_REG_OFFSET 0x10u 88 | 89 | #define STATUS_REG_OFFSET 0x10u 90 | 91 | /* 92 | * Transmit ready. 93 | */ 94 | #define STATUS_TXRDY_OFFSET 0x10u 95 | #define STATUS_TXRDY_MASK 0x01u 96 | #define STATUS_TXRDY_SHIFT 0u 97 | 98 | /* 99 | * Receive full. 100 | */ 101 | #define STATUS_RXFULL_OFFSET 0x10u 102 | #define STATUS_RXFULL_MASK 0x02u 103 | #define STATUS_RXFULL_SHIFT 1u 104 | 105 | /* 106 | * Parity error. 107 | */ 108 | #define STATUS_PARITYERR_OFFSET 0x10u 109 | #define STATUS_PARITYERR_MASK 0x04u 110 | #define STATUS_PARITYERR_SHIFT 2u 111 | 112 | /* 113 | * Overflow. 114 | */ 115 | #define STATUS_OVERFLOW_OFFSET 0x10u 116 | #define STATUS_OVERFLOW_MASK 0x08u 117 | #define STATUS_OVERFLOW_SHIFT 3u 118 | 119 | /* 120 | * Frame Error. 121 | */ 122 | #define STATUS_FRAMERR_OFFSET 0x10u 123 | #define STATUS_FRAMERR_MASK 0x10u 124 | #define STATUS_FRAMERR_SHIFT 4u 125 | 126 | #ifdef __cplusplus 127 | } 128 | #endif 129 | 130 | #endif /* __CORE_UART_APB_REGISTERS */ 131 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/README.txt: -------------------------------------------------------------------------------- 1 | ================================================================================ 2 | System Internal Timer example project 3 | ================================================================================ 4 | 5 | This SoftConsole example project demonstrates how to configure and use the 6 | Mi-V Soft processor system timer. 7 | 8 | 9 | -------------------------------------------------------------------------------- 10 | Mi-V Soft processor 11 | -------------------------------------------------------------------------------- 12 | This example uses a Mi-V Soft processor MiV_RV32IMA_L1_AHB. The design is 13 | built for debugging MiV_RV32IMA_L1_AHB through the SmartFusion2 FPGA programming 14 | JTAG port using a FlashPro5. To achieve this the CoreJTAGDebug IP is used to 15 | connect to the JTAG port of the MiV_RV32IMA_L1_AHB. 16 | 17 | Optionally, The design can be build to use Olimex ARM-USB-TINY-H JTAG probe. 18 | For this,The JTAG pins must be routed through Fabric to the top level pins. 19 | 20 | All the platform/design specific definitions such as peripheral base addresses, 21 | system clock frequency etc. are included in hw_platform.h. The hw_platform.h is 22 | located at the root folder of this project. 23 | 24 | The MiV_RV32IMA_L1_AHB firmware projects needs the riscv_hal and the hal firmware 25 | (RISC-V HAL). 26 | 27 | The RISC-V HAL is available through Firmware catalog as well as the link below: 28 | 29 | https://github.com/RISCV-on-Microsemi-FPGA/Solutions/tree/master/Mi-V-Firmware 30 | 31 | 32 | -------------------------------------------------------------------------------- 33 | How to use this example 34 | -------------------------------------------------------------------------------- 35 | The System timer is configured using SysTick_Config() function. This function 36 | also enables the internal system timer interrupt. This example implements the 37 | SysTick_Handler() function which will be called by the RISCV-HAL.The application 38 | specific interrupt handling is implemented in SysTick_Handler() function. 39 | As demonstration, the LEDs blink pattern can be observed to see the System internal 40 | timer interrupt functionality. 41 | 42 | This example project requires USB-UART interface to be connected to a host PC. 43 | The host PC must connect to the serial port using a terminal emulator such as 44 | HyperTerminal or PuTTY configured as follows: 45 | - 115200 baud 46 | - 8 data bits 47 | - 1 stop bit 48 | - no parity 49 | - no flow control 50 | 51 | This example displays a message on HyperTerminal then echoes back characters 52 | typed in HyperTerminal. 53 | The LEDs will toggle every time the Systick interrupt is asserted. 54 | 55 | 56 | -------------------------------------------------------------------------------- 57 | Target hardware 58 | -------------------------------------------------------------------------------- 59 | This example project is targeted at a SmartFusion2 M2S150 advanced development kit 60 | design which has CoreTimer enabled. 61 | The example project is built using a clock frequency of 83MHz. Trying to execute 62 | this example project on a different design will result in incorrect baud rate 63 | being used by CoreUART and timer load value. 64 | 65 | This example project can be used with another design using a different clock 66 | configuration. This can be achieved by overwriting the content of this example 67 | project's "hw_platform.h" file with the correct data from your Libero design. 68 | 69 | An example design for SmartFusion2 150 Ad. Dev Kit is available at 70 | https://github.com/RISCV-on-Microsemi-FPGA/SmartFusion2-Advanced-Dev-Kit 71 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/README.txt: -------------------------------------------------------------------------------- 1 | ================================================================================ 2 | CoreTIMER and external interrupt example project 3 | ================================================================================ 4 | 5 | This SoftConsole example project demonstrates how to use the CoreTimer driver. 6 | This example project also demonstrates how to configure PLIC of Mi-V Soft processor 7 | to handle the external interrupts. 8 | 9 | -------------------------------------------------------------------------------- 10 | Mi-V Soft processor 11 | -------------------------------------------------------------------------------- 12 | This example uses a Mi-V Soft processor MiV_RV32IM_L1_AHB. The design is 13 | built for debugging MiV_RV32IM_L1_AHB through the SmartFusion2 FPGA programming 14 | JTAG port using a FlashPro5. To achieve this the CoreJTAGDebug IP is used to 15 | connect to the JTAG port of the MiV_RV32IM_L1_AHB. 16 | 17 | Optionally, The design can be build to use Olimex ARM-USB-TINY-H JTAG probe. 18 | For this,The JTAG pins must be routed through Fabric to the top level pins. 19 | 20 | All the platform/design specific definitions such as peripheral base addresses, 21 | system clock frequency etc. are included in hw_platform.h. The hw_platform.h is 22 | located at the root folder of this project. 23 | 24 | The MiV_RV32IM_L1_AHB firmware projects needs the riscv_hal and the hal firmware 25 | (RISC-V HAL). 26 | 27 | The RISC-V HAL is available through Firmware catalog as well as the link below: 28 | 29 | https://github.com/RISCV-on-Microsemi-FPGA/Solutions/tree/master/Mi-V-Firmware 30 | -------------------------------------------------------------------------------- 31 | How to use this example 32 | -------------------------------------------------------------------------------- 33 | The timer0 and timer1 are enabled and are setup up in continuous mode. The 34 | LEDs blinking on the board indicate the timer interrupt operation. 35 | 36 | The PLIC enables the external interrupt handling on Mi-V Soft processor. Up to 31 37 | external interrupts can be connected to Mi-V Soft processor. These external interrupts 38 | are configured and handled via PLIC. 39 | 40 | This example project demonstrates how to use PLIC functions to configure PLIC. 41 | It also demonstrates how to configure and use an external interrupt handler. 42 | 43 | This example project requires USB-UART interface to be connected to a host PC. 44 | The host PC must connect to the serial port using a terminal emulator such as 45 | HyperTerminal or PuTTY configured as follows: 46 | - 115200 baud 47 | - 8 data bits 48 | - 1 stop bit 49 | - no parity 50 | - no flow control 51 | 52 | This example displays a message on HyperTerminal then echoes back characters 53 | typed in HyperTerminal. 54 | 55 | The LEDs will toggle every time the Timer timer interrupt asserts. 56 | -------------------------------------------------------------------------------- 57 | Target hardware 58 | -------------------------------------------------------------------------------- 59 | This example project is targeted at a SmartFusion2 M2S150 advanced development kit 60 | design which has CoreTimer enabled. 61 | The example project is built using a clock frequency of 83MHz. Trying to execute 62 | this example project on a different design will result in incorrect baud rate 63 | being used by CoreUART and timer load value. 64 | 65 | This example project can be used with another design using a different clock 66 | configuration. This can be achieved by overwriting the content of this example 67 | project's "hw_platform.h" file with the correct data from your Libero design. 68 | 69 | An example design for SmartFusion2 150 Ad. Dev Kit is available at 70 | https://github.com/RISCV-on-Microsemi-FPGA/SmartFusion2-Advanced-Dev-Kit 71 | -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/microsemi-riscv-igloo2.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * file name : microsemi-riscv-igloo2.ld 5 | * Mi-V soft processor linker script for creating a SoftConsole downloadable 6 | * image executing in eNVM. 7 | * 8 | * This linker script assumes that the eNVM is connected at on the Mi-V soft 9 | * processor memory space. 10 | * 11 | * SVN $Revision: 9661 $ 12 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 13 | */ 14 | 15 | OUTPUT_ARCH( "riscv" ) 16 | ENTRY(_start) 17 | 18 | 19 | MEMORY 20 | { 21 | envm (rx) : ORIGIN = 0x60000000, LENGTH = 240k 22 | ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64k 23 | } 24 | 25 | RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */ 26 | RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */ 27 | STACK_SIZE = 2k; /* needs to be calculated for your application */ 28 | HEAP_SIZE = 2k; /* needs to be calculated for your application */ 29 | 30 | SECTIONS 31 | { 32 | .text : ALIGN(0x10) 33 | { 34 | KEEP (*(SORT_NONE(.text.entry))) 35 | . = ALIGN(0x10); 36 | *(.text .text.* .gnu.linkonce.t.*) 37 | *(.plt) 38 | . = ALIGN(0x10); 39 | 40 | KEEP (*crtbegin.o(.ctors)) 41 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 42 | KEEP (*(SORT(.ctors.*))) 43 | KEEP (*crtend.o(.ctors)) 44 | KEEP (*crtbegin.o(.dtors)) 45 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 46 | KEEP (*(SORT(.dtors.*))) 47 | KEEP (*crtend.o(.dtors)) 48 | 49 | *(.rodata .rodata.* .gnu.linkonce.r.*) 50 | *(.gcc_except_table) 51 | *(.eh_frame_hdr) 52 | *(.eh_frame) 53 | 54 | KEEP (*(.init)) 55 | KEEP (*(.fini)) 56 | 57 | PROVIDE_HIDDEN (__preinit_array_start = .); 58 | KEEP (*(.preinit_array)) 59 | PROVIDE_HIDDEN (__preinit_array_end = .); 60 | PROVIDE_HIDDEN (__init_array_start = .); 61 | KEEP (*(SORT(.init_array.*))) 62 | KEEP (*(.init_array)) 63 | PROVIDE_HIDDEN (__init_array_end = .); 64 | PROVIDE_HIDDEN (__fini_array_start = .); 65 | KEEP (*(.fini_array)) 66 | KEEP (*(SORT(.fini_array.*))) 67 | PROVIDE_HIDDEN (__fini_array_end = .); 68 | . = ALIGN(0x10); 69 | 70 | } >envm 71 | 72 | /* short/global data section */ 73 | .sdata : ALIGN(0x10) 74 | { 75 | __sdata_load = LOADADDR(.sdata); 76 | __sdata_start = .; 77 | PROVIDE( __global_pointer$ = . + 0x800); 78 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 79 | *(.srodata*) 80 | *(.sdata .sdata.* .gnu.linkonce.s.*) 81 | . = ALIGN(0x10); 82 | __sdata_end = .; 83 | } >ram AT>envm 84 | 85 | /* data section */ 86 | .data : ALIGN(0x10) 87 | { 88 | __data_load = LOADADDR(.data); 89 | __data_start = .; 90 | *(.got.plt) *(.got) 91 | *(.shdata) 92 | *(.data .data.* .gnu.linkonce.d.*) 93 | . = ALIGN(0x10); 94 | __data_end = .; 95 | } >ram AT>envm 96 | 97 | /* sbss section */ 98 | .sbss : ALIGN(0x10) 99 | { 100 | __sbss_start = .; 101 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 102 | *(.scommon) 103 | . = ALIGN(0x10); 104 | __sbss_end = .; 105 | } > ram 106 | 107 | /* sbss section */ 108 | .bss : ALIGN(0x10) 109 | { 110 | __bss_start = .; 111 | *(.shbss) 112 | *(.bss .bss.* .gnu.linkonce.b.*) 113 | *(COMMON) 114 | . = ALIGN(0x10); 115 | __bss_end = .; 116 | } > ram 117 | 118 | /* End of uninitialized data segment */ 119 | _end = .; 120 | 121 | .heap : ALIGN(0x10) 122 | { 123 | __heap_start = .; 124 | . += HEAP_SIZE; 125 | __heap_end = .; 126 | . = ALIGN(0x10); 127 | _heap_end = __heap_end; 128 | } > ram 129 | 130 | .stack : ALIGN(0x10) 131 | { 132 | __stack_bottom = .; 133 | . += STACK_SIZE; 134 | __stack_top = .; 135 | } > ram 136 | } 137 | 138 | -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/microsemi-riscv-ram.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * file name : microsemi-riscv-ram.ld 5 | * Mi-V soft processor linker script for creating a SoftConsole downloadable 6 | * debug image executing in SRAM. 7 | * 8 | * This linker script assumes that the SRAM is connected at on the Mi-V soft 9 | * processor memory space. The start address and size of the memory space must 10 | * be correct as per the Libero design. 11 | * 12 | * SVN $Revision: 9661 $ 13 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 14 | */ 15 | 16 | OUTPUT_ARCH( "riscv" ) 17 | ENTRY(_start) 18 | 19 | 20 | MEMORY 21 | { 22 | ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64k 23 | } 24 | 25 | RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */ 26 | RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */ 27 | STACK_SIZE = 2k; /* needs to be calculated for your application */ 28 | HEAP_SIZE = 2k; /* needs to be calculated for your application */ 29 | 30 | SECTIONS 31 | { 32 | .text : ALIGN(0x10) 33 | { 34 | KEEP (*(SORT_NONE(.text.entry))) 35 | . = ALIGN(0x10); 36 | *(.text .text.* .gnu.linkonce.t.*) 37 | *(.plt) 38 | . = ALIGN(0x10); 39 | 40 | KEEP (*crtbegin.o(.ctors)) 41 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 42 | KEEP (*(SORT(.ctors.*))) 43 | KEEP (*crtend.o(.ctors)) 44 | KEEP (*crtbegin.o(.dtors)) 45 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 46 | KEEP (*(SORT(.dtors.*))) 47 | KEEP (*crtend.o(.dtors)) 48 | 49 | *(.rodata .rodata.* .gnu.linkonce.r.*) 50 | *(.gcc_except_table) 51 | *(.eh_frame_hdr) 52 | *(.eh_frame) 53 | 54 | KEEP (*(.init)) 55 | KEEP (*(.fini)) 56 | 57 | PROVIDE_HIDDEN (__preinit_array_start = .); 58 | KEEP (*(.preinit_array)) 59 | PROVIDE_HIDDEN (__preinit_array_end = .); 60 | PROVIDE_HIDDEN (__init_array_start = .); 61 | KEEP (*(SORT(.init_array.*))) 62 | KEEP (*(.init_array)) 63 | PROVIDE_HIDDEN (__init_array_end = .); 64 | PROVIDE_HIDDEN (__fini_array_start = .); 65 | KEEP (*(.fini_array)) 66 | KEEP (*(SORT(.fini_array.*))) 67 | PROVIDE_HIDDEN (__fini_array_end = .); 68 | . = ALIGN(0x10); 69 | 70 | } > ram 71 | 72 | /* short/global data section */ 73 | .sdata : ALIGN(0x10) 74 | { 75 | __sdata_load = LOADADDR(.sdata); 76 | __sdata_start = .; 77 | PROVIDE( __global_pointer$ = . + 0x800); 78 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 79 | *(.srodata*) 80 | *(.sdata .sdata.* .gnu.linkonce.s.*) 81 | . = ALIGN(0x10); 82 | __sdata_end = .; 83 | } > ram 84 | 85 | /* data section */ 86 | .data : ALIGN(0x10) 87 | { 88 | __data_load = LOADADDR(.data); 89 | __data_start = .; 90 | *(.got.plt) *(.got) 91 | *(.shdata) 92 | *(.data .data.* .gnu.linkonce.d.*) 93 | . = ALIGN(0x10); 94 | __data_end = .; 95 | } > ram 96 | 97 | /* sbss section */ 98 | .sbss : ALIGN(0x10) 99 | { 100 | __sbss_start = .; 101 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 102 | *(.scommon) 103 | . = ALIGN(0x10); 104 | __sbss_end = .; 105 | } > ram 106 | 107 | /* sbss section */ 108 | .bss : ALIGN(0x10) 109 | { 110 | __bss_start = .; 111 | *(.shbss) 112 | *(.bss .bss.* .gnu.linkonce.b.*) 113 | *(COMMON) 114 | . = ALIGN(0x10); 115 | __bss_end = .; 116 | } > ram 117 | 118 | /* End of uninitialized data segment */ 119 | _end = .; 120 | 121 | .heap : ALIGN(0x10) 122 | { 123 | __heap_start = .; 124 | . += HEAP_SIZE; 125 | __heap_end = .; 126 | . = ALIGN(0x10); 127 | _heap_end = __heap_end; 128 | } > ram 129 | 130 | .stack : ALIGN(0x10) 131 | { 132 | __stack_bottom = .; 133 | . += STACK_SIZE; 134 | __stack_top = .; 135 | } > ram 136 | } 137 | 138 | -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/entry.S: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file entry.S 5 | * @author Microsemi SoC Products Group 6 | * @brief Mi-V soft processor vectors, trap handling and startup code. 7 | * 8 | * SVN $Revision: 9661 $ 9 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 10 | */ 11 | #ifndef ENTRY_S 12 | #define ENTRY_S 13 | 14 | #include "encoding.h" 15 | 16 | #if __riscv_xlen == 64 17 | # define LREG ld 18 | # define SREG sd 19 | # define REGBYTES 8 20 | #else 21 | # define LREG lw 22 | # define SREG sw 23 | # define REGBYTES 4 24 | #endif 25 | 26 | .section .text.entry 27 | .globl _start 28 | 29 | _start: 30 | j handle_reset 31 | 32 | nmi_vector: 33 | j nmi_vector 34 | 35 | trap_vector: 36 | j trap_entry 37 | 38 | handle_reset: 39 | la t0, trap_entry 40 | csrw mtvec, t0 41 | csrwi mstatus, 0 42 | csrwi mie, 0 43 | 44 | /*Flaoting point support configuration*/ 45 | 46 | #ifdef __riscv_flen 47 | csrr t0, mstatus 48 | lui t1, 0xffffa 49 | addi t1, t1, -1 50 | and t0, t0, t1 51 | lui t1, 0x4 52 | or t1, t0, t1 53 | csrw mstatus, t1 54 | 55 | lui t0, 0x0 56 | fscsr t0 57 | #endif 58 | .option push 59 | 60 | # Ensure the instruction is not optimized, since gp is not yet set 61 | 62 | .option norelax 63 | # initialize global pointer 64 | la gp, __global_pointer$ 65 | 66 | .option pop 67 | 68 | # initialize stack pointer 69 | la sp, __stack_top 70 | 71 | # perform the rest of initialization in C 72 | j _init 73 | 74 | 75 | trap_entry: 76 | addi sp, sp, -32*REGBYTES 77 | 78 | SREG x1, 0 * REGBYTES(sp) 79 | SREG x2, 1 * REGBYTES(sp) 80 | SREG x3, 2 * REGBYTES(sp) 81 | SREG x4, 3 * REGBYTES(sp) 82 | SREG x5, 4 * REGBYTES(sp) 83 | SREG x6, 5 * REGBYTES(sp) 84 | SREG x7, 6 * REGBYTES(sp) 85 | SREG x8, 7 * REGBYTES(sp) 86 | SREG x9, 8 * REGBYTES(sp) 87 | SREG x10, 9 * REGBYTES(sp) 88 | SREG x11, 10 * REGBYTES(sp) 89 | SREG x12, 11 * REGBYTES(sp) 90 | SREG x13, 12 * REGBYTES(sp) 91 | SREG x14, 13 * REGBYTES(sp) 92 | SREG x15, 14 * REGBYTES(sp) 93 | SREG x16, 15 * REGBYTES(sp) 94 | SREG x17, 16 * REGBYTES(sp) 95 | SREG x18, 17 * REGBYTES(sp) 96 | SREG x19, 18 * REGBYTES(sp) 97 | SREG x20, 19 * REGBYTES(sp) 98 | SREG x21, 20 * REGBYTES(sp) 99 | SREG x22, 21 * REGBYTES(sp) 100 | SREG x23, 22 * REGBYTES(sp) 101 | SREG x24, 23 * REGBYTES(sp) 102 | SREG x25, 24 * REGBYTES(sp) 103 | SREG x26, 25 * REGBYTES(sp) 104 | SREG x27, 26 * REGBYTES(sp) 105 | SREG x28, 27 * REGBYTES(sp) 106 | SREG x29, 28 * REGBYTES(sp) 107 | SREG x30, 29 * REGBYTES(sp) 108 | SREG x31, 30 * REGBYTES(sp) 109 | 110 | 111 | csrr t0, mepc 112 | SREG t0, 31 * REGBYTES(sp) 113 | 114 | csrr a0, mcause 115 | csrr a1, mepc 116 | mv a2, sp 117 | jal handle_trap 118 | csrw mepc, a0 119 | 120 | # Remain in M-mode after mret 121 | li t0, MSTATUS_MPP 122 | csrs mstatus, t0 123 | 124 | LREG x1, 0 * REGBYTES(sp) 125 | LREG x2, 1 * REGBYTES(sp) 126 | LREG x3, 2 * REGBYTES(sp) 127 | LREG x4, 3 * REGBYTES(sp) 128 | LREG x5, 4 * REGBYTES(sp) 129 | LREG x6, 5 * REGBYTES(sp) 130 | LREG x7, 6 * REGBYTES(sp) 131 | LREG x8, 7 * REGBYTES(sp) 132 | LREG x9, 8 * REGBYTES(sp) 133 | LREG x10, 9 * REGBYTES(sp) 134 | LREG x11, 10 * REGBYTES(sp) 135 | LREG x12, 11 * REGBYTES(sp) 136 | LREG x13, 12 * REGBYTES(sp) 137 | LREG x14, 13 * REGBYTES(sp) 138 | LREG x15, 14 * REGBYTES(sp) 139 | LREG x16, 15 * REGBYTES(sp) 140 | LREG x17, 16 * REGBYTES(sp) 141 | LREG x18, 17 * REGBYTES(sp) 142 | LREG x19, 18 * REGBYTES(sp) 143 | LREG x20, 19 * REGBYTES(sp) 144 | LREG x21, 20 * REGBYTES(sp) 145 | LREG x22, 21 * REGBYTES(sp) 146 | LREG x23, 22 * REGBYTES(sp) 147 | LREG x24, 23 * REGBYTES(sp) 148 | LREG x25, 24 * REGBYTES(sp) 149 | LREG x26, 25 * REGBYTES(sp) 150 | LREG x27, 26 * REGBYTES(sp) 151 | LREG x28, 27 * REGBYTES(sp) 152 | LREG x29, 28 * REGBYTES(sp) 153 | LREG x30, 29 * REGBYTES(sp) 154 | LREG x31, 30 * REGBYTES(sp) 155 | 156 | addi sp, sp, 32*REGBYTES 157 | mret 158 | 159 | #endif 160 | 161 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/riscv_hal/microsemi-riscv-igloo2.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * file name : microsemi-riscv-igloo2.ld 5 | * Mi-V soft processor linker script for creating a SoftConsole downloadable 6 | * image executing in eNVM. 7 | * 8 | * This linker script assumes that the eNVM is connected at on the Mi-V soft 9 | * processor memory space. 10 | * 11 | * SVN $Revision: 9661 $ 12 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 13 | */ 14 | 15 | OUTPUT_ARCH( "riscv" ) 16 | ENTRY(_start) 17 | 18 | 19 | MEMORY 20 | { 21 | envm (rx) : ORIGIN = 0x60000000, LENGTH = 240k 22 | ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64k 23 | } 24 | 25 | RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */ 26 | RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */ 27 | STACK_SIZE = 2k; /* needs to be calculated for your application */ 28 | HEAP_SIZE = 2k; /* needs to be calculated for your application */ 29 | 30 | SECTIONS 31 | { 32 | .text : ALIGN(0x10) 33 | { 34 | KEEP (*(SORT_NONE(.text.entry))) 35 | . = ALIGN(0x10); 36 | *(.text .text.* .gnu.linkonce.t.*) 37 | *(.plt) 38 | . = ALIGN(0x10); 39 | 40 | KEEP (*crtbegin.o(.ctors)) 41 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 42 | KEEP (*(SORT(.ctors.*))) 43 | KEEP (*crtend.o(.ctors)) 44 | KEEP (*crtbegin.o(.dtors)) 45 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 46 | KEEP (*(SORT(.dtors.*))) 47 | KEEP (*crtend.o(.dtors)) 48 | 49 | *(.rodata .rodata.* .gnu.linkonce.r.*) 50 | *(.gcc_except_table) 51 | *(.eh_frame_hdr) 52 | *(.eh_frame) 53 | 54 | KEEP (*(.init)) 55 | KEEP (*(.fini)) 56 | 57 | PROVIDE_HIDDEN (__preinit_array_start = .); 58 | KEEP (*(.preinit_array)) 59 | PROVIDE_HIDDEN (__preinit_array_end = .); 60 | PROVIDE_HIDDEN (__init_array_start = .); 61 | KEEP (*(SORT(.init_array.*))) 62 | KEEP (*(.init_array)) 63 | PROVIDE_HIDDEN (__init_array_end = .); 64 | PROVIDE_HIDDEN (__fini_array_start = .); 65 | KEEP (*(.fini_array)) 66 | KEEP (*(SORT(.fini_array.*))) 67 | PROVIDE_HIDDEN (__fini_array_end = .); 68 | . = ALIGN(0x10); 69 | 70 | } >envm 71 | 72 | /* short/global data section */ 73 | .sdata : ALIGN(0x10) 74 | { 75 | __sdata_load = LOADADDR(.sdata); 76 | __sdata_start = .; 77 | PROVIDE( __global_pointer$ = . + 0x800); 78 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 79 | *(.srodata*) 80 | *(.sdata .sdata.* .gnu.linkonce.s.*) 81 | . = ALIGN(0x10); 82 | __sdata_end = .; 83 | } >ram AT>envm 84 | 85 | /* data section */ 86 | .data : ALIGN(0x10) 87 | { 88 | __data_load = LOADADDR(.data); 89 | __data_start = .; 90 | *(.got.plt) *(.got) 91 | *(.shdata) 92 | *(.data .data.* .gnu.linkonce.d.*) 93 | . = ALIGN(0x10); 94 | __data_end = .; 95 | } >ram AT>envm 96 | 97 | /* sbss section */ 98 | .sbss : ALIGN(0x10) 99 | { 100 | __sbss_start = .; 101 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 102 | *(.scommon) 103 | . = ALIGN(0x10); 104 | __sbss_end = .; 105 | } > ram 106 | 107 | /* sbss section */ 108 | .bss : ALIGN(0x10) 109 | { 110 | __bss_start = .; 111 | *(.shbss) 112 | *(.bss .bss.* .gnu.linkonce.b.*) 113 | *(COMMON) 114 | . = ALIGN(0x10); 115 | __bss_end = .; 116 | } > ram 117 | 118 | /* End of uninitialized data segment */ 119 | _end = .; 120 | 121 | .heap : ALIGN(0x10) 122 | { 123 | __heap_start = .; 124 | . += HEAP_SIZE; 125 | __heap_end = .; 126 | . = ALIGN(0x10); 127 | _heap_end = __heap_end; 128 | } > ram 129 | 130 | .stack : ALIGN(0x10) 131 | { 132 | __stack_bottom = .; 133 | . += STACK_SIZE; 134 | __stack_top = .; 135 | } > ram 136 | } 137 | 138 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/riscv_hal/microsemi-riscv-igloo2.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * file name : microsemi-riscv-igloo2.ld 5 | * Mi-V soft processor linker script for creating a SoftConsole downloadable 6 | * image executing in eNVM. 7 | * 8 | * This linker script assumes that the eNVM is connected at on the Mi-V soft 9 | * processor memory space. 10 | * 11 | * SVN $Revision: 9661 $ 12 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 13 | */ 14 | 15 | OUTPUT_ARCH( "riscv" ) 16 | ENTRY(_start) 17 | 18 | 19 | MEMORY 20 | { 21 | envm (rx) : ORIGIN = 0x60000000, LENGTH = 240k 22 | ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64k 23 | } 24 | 25 | RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */ 26 | RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */ 27 | STACK_SIZE = 2k; /* needs to be calculated for your application */ 28 | HEAP_SIZE = 2k; /* needs to be calculated for your application */ 29 | 30 | SECTIONS 31 | { 32 | .text : ALIGN(0x10) 33 | { 34 | KEEP (*(SORT_NONE(.text.entry))) 35 | . = ALIGN(0x10); 36 | *(.text .text.* .gnu.linkonce.t.*) 37 | *(.plt) 38 | . = ALIGN(0x10); 39 | 40 | KEEP (*crtbegin.o(.ctors)) 41 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 42 | KEEP (*(SORT(.ctors.*))) 43 | KEEP (*crtend.o(.ctors)) 44 | KEEP (*crtbegin.o(.dtors)) 45 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 46 | KEEP (*(SORT(.dtors.*))) 47 | KEEP (*crtend.o(.dtors)) 48 | 49 | *(.rodata .rodata.* .gnu.linkonce.r.*) 50 | *(.gcc_except_table) 51 | *(.eh_frame_hdr) 52 | *(.eh_frame) 53 | 54 | KEEP (*(.init)) 55 | KEEP (*(.fini)) 56 | 57 | PROVIDE_HIDDEN (__preinit_array_start = .); 58 | KEEP (*(.preinit_array)) 59 | PROVIDE_HIDDEN (__preinit_array_end = .); 60 | PROVIDE_HIDDEN (__init_array_start = .); 61 | KEEP (*(SORT(.init_array.*))) 62 | KEEP (*(.init_array)) 63 | PROVIDE_HIDDEN (__init_array_end = .); 64 | PROVIDE_HIDDEN (__fini_array_start = .); 65 | KEEP (*(.fini_array)) 66 | KEEP (*(SORT(.fini_array.*))) 67 | PROVIDE_HIDDEN (__fini_array_end = .); 68 | . = ALIGN(0x10); 69 | 70 | } >envm 71 | 72 | /* short/global data section */ 73 | .sdata : ALIGN(0x10) 74 | { 75 | __sdata_load = LOADADDR(.sdata); 76 | __sdata_start = .; 77 | PROVIDE( __global_pointer$ = . + 0x800); 78 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 79 | *(.srodata*) 80 | *(.sdata .sdata.* .gnu.linkonce.s.*) 81 | . = ALIGN(0x10); 82 | __sdata_end = .; 83 | } >ram AT>envm 84 | 85 | /* data section */ 86 | .data : ALIGN(0x10) 87 | { 88 | __data_load = LOADADDR(.data); 89 | __data_start = .; 90 | *(.got.plt) *(.got) 91 | *(.shdata) 92 | *(.data .data.* .gnu.linkonce.d.*) 93 | . = ALIGN(0x10); 94 | __data_end = .; 95 | } >ram AT>envm 96 | 97 | /* sbss section */ 98 | .sbss : ALIGN(0x10) 99 | { 100 | __sbss_start = .; 101 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 102 | *(.scommon) 103 | . = ALIGN(0x10); 104 | __sbss_end = .; 105 | } > ram 106 | 107 | /* sbss section */ 108 | .bss : ALIGN(0x10) 109 | { 110 | __bss_start = .; 111 | *(.shbss) 112 | *(.bss .bss.* .gnu.linkonce.b.*) 113 | *(COMMON) 114 | . = ALIGN(0x10); 115 | __bss_end = .; 116 | } > ram 117 | 118 | /* End of uninitialized data segment */ 119 | _end = .; 120 | 121 | .heap : ALIGN(0x10) 122 | { 123 | __heap_start = .; 124 | . += HEAP_SIZE; 125 | __heap_end = .; 126 | . = ALIGN(0x10); 127 | _heap_end = __heap_end; 128 | } > ram 129 | 130 | .stack : ALIGN(0x10) 131 | { 132 | __stack_bottom = .; 133 | . += STACK_SIZE; 134 | __stack_top = .; 135 | } > ram 136 | } 137 | 138 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/riscv_hal/microsemi-riscv-igloo2.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * file name : microsemi-riscv-igloo2.ld 5 | * Mi-V soft processor linker script for creating a SoftConsole downloadable 6 | * image executing in eNVM. 7 | * 8 | * This linker script assumes that the eNVM is connected at on the Mi-V soft 9 | * processor memory space. 10 | * 11 | * SVN $Revision: 9661 $ 12 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 13 | */ 14 | 15 | OUTPUT_ARCH( "riscv" ) 16 | ENTRY(_start) 17 | 18 | 19 | MEMORY 20 | { 21 | envm (rx) : ORIGIN = 0x60000000, LENGTH = 240k 22 | ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64k 23 | } 24 | 25 | RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */ 26 | RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */ 27 | STACK_SIZE = 2k; /* needs to be calculated for your application */ 28 | HEAP_SIZE = 2k; /* needs to be calculated for your application */ 29 | 30 | SECTIONS 31 | { 32 | .text : ALIGN(0x10) 33 | { 34 | KEEP (*(SORT_NONE(.text.entry))) 35 | . = ALIGN(0x10); 36 | *(.text .text.* .gnu.linkonce.t.*) 37 | *(.plt) 38 | . = ALIGN(0x10); 39 | 40 | KEEP (*crtbegin.o(.ctors)) 41 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 42 | KEEP (*(SORT(.ctors.*))) 43 | KEEP (*crtend.o(.ctors)) 44 | KEEP (*crtbegin.o(.dtors)) 45 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 46 | KEEP (*(SORT(.dtors.*))) 47 | KEEP (*crtend.o(.dtors)) 48 | 49 | *(.rodata .rodata.* .gnu.linkonce.r.*) 50 | *(.gcc_except_table) 51 | *(.eh_frame_hdr) 52 | *(.eh_frame) 53 | 54 | KEEP (*(.init)) 55 | KEEP (*(.fini)) 56 | 57 | PROVIDE_HIDDEN (__preinit_array_start = .); 58 | KEEP (*(.preinit_array)) 59 | PROVIDE_HIDDEN (__preinit_array_end = .); 60 | PROVIDE_HIDDEN (__init_array_start = .); 61 | KEEP (*(SORT(.init_array.*))) 62 | KEEP (*(.init_array)) 63 | PROVIDE_HIDDEN (__init_array_end = .); 64 | PROVIDE_HIDDEN (__fini_array_start = .); 65 | KEEP (*(.fini_array)) 66 | KEEP (*(SORT(.fini_array.*))) 67 | PROVIDE_HIDDEN (__fini_array_end = .); 68 | . = ALIGN(0x10); 69 | 70 | } >envm 71 | 72 | /* short/global data section */ 73 | .sdata : ALIGN(0x10) 74 | { 75 | __sdata_load = LOADADDR(.sdata); 76 | __sdata_start = .; 77 | PROVIDE( __global_pointer$ = . + 0x800); 78 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 79 | *(.srodata*) 80 | *(.sdata .sdata.* .gnu.linkonce.s.*) 81 | . = ALIGN(0x10); 82 | __sdata_end = .; 83 | } >ram AT>envm 84 | 85 | /* data section */ 86 | .data : ALIGN(0x10) 87 | { 88 | __data_load = LOADADDR(.data); 89 | __data_start = .; 90 | *(.got.plt) *(.got) 91 | *(.shdata) 92 | *(.data .data.* .gnu.linkonce.d.*) 93 | . = ALIGN(0x10); 94 | __data_end = .; 95 | } >ram AT>envm 96 | 97 | /* sbss section */ 98 | .sbss : ALIGN(0x10) 99 | { 100 | __sbss_start = .; 101 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 102 | *(.scommon) 103 | . = ALIGN(0x10); 104 | __sbss_end = .; 105 | } > ram 106 | 107 | /* sbss section */ 108 | .bss : ALIGN(0x10) 109 | { 110 | __bss_start = .; 111 | *(.shbss) 112 | *(.bss .bss.* .gnu.linkonce.b.*) 113 | *(COMMON) 114 | . = ALIGN(0x10); 115 | __bss_end = .; 116 | } > ram 117 | 118 | /* End of uninitialized data segment */ 119 | _end = .; 120 | 121 | .heap : ALIGN(0x10) 122 | { 123 | __heap_start = .; 124 | . += HEAP_SIZE; 125 | __heap_end = .; 126 | . = ALIGN(0x10); 127 | _heap_end = __heap_end; 128 | } > ram 129 | 130 | .stack : ALIGN(0x10) 131 | { 132 | __stack_bottom = .; 133 | . += STACK_SIZE; 134 | __stack_top = .; 135 | } > ram 136 | } 137 | 138 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/riscv_hal/microsemi-riscv-ram.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * file name : microsemi-riscv-ram.ld 5 | * Mi-V soft processor linker script for creating a SoftConsole downloadable 6 | * debug image executing in SRAM. 7 | * 8 | * This linker script assumes that the SRAM is connected at on the Mi-V soft 9 | * processor memory space. The start address and size of the memory space must 10 | * be correct as per the Libero design. 11 | * 12 | * SVN $Revision: 9661 $ 13 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 14 | */ 15 | 16 | OUTPUT_ARCH( "riscv" ) 17 | ENTRY(_start) 18 | 19 | 20 | MEMORY 21 | { 22 | ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64k 23 | } 24 | 25 | RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */ 26 | RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */ 27 | STACK_SIZE = 2k; /* needs to be calculated for your application */ 28 | HEAP_SIZE = 2k; /* needs to be calculated for your application */ 29 | 30 | SECTIONS 31 | { 32 | .text : ALIGN(0x10) 33 | { 34 | KEEP (*(SORT_NONE(.text.entry))) 35 | . = ALIGN(0x10); 36 | *(.text .text.* .gnu.linkonce.t.*) 37 | *(.plt) 38 | . = ALIGN(0x10); 39 | 40 | KEEP (*crtbegin.o(.ctors)) 41 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 42 | KEEP (*(SORT(.ctors.*))) 43 | KEEP (*crtend.o(.ctors)) 44 | KEEP (*crtbegin.o(.dtors)) 45 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 46 | KEEP (*(SORT(.dtors.*))) 47 | KEEP (*crtend.o(.dtors)) 48 | 49 | *(.rodata .rodata.* .gnu.linkonce.r.*) 50 | *(.gcc_except_table) 51 | *(.eh_frame_hdr) 52 | *(.eh_frame) 53 | 54 | KEEP (*(.init)) 55 | KEEP (*(.fini)) 56 | 57 | PROVIDE_HIDDEN (__preinit_array_start = .); 58 | KEEP (*(.preinit_array)) 59 | PROVIDE_HIDDEN (__preinit_array_end = .); 60 | PROVIDE_HIDDEN (__init_array_start = .); 61 | KEEP (*(SORT(.init_array.*))) 62 | KEEP (*(.init_array)) 63 | PROVIDE_HIDDEN (__init_array_end = .); 64 | PROVIDE_HIDDEN (__fini_array_start = .); 65 | KEEP (*(.fini_array)) 66 | KEEP (*(SORT(.fini_array.*))) 67 | PROVIDE_HIDDEN (__fini_array_end = .); 68 | . = ALIGN(0x10); 69 | 70 | } > ram 71 | 72 | /* short/global data section */ 73 | .sdata : ALIGN(0x10) 74 | { 75 | __sdata_load = LOADADDR(.sdata); 76 | __sdata_start = .; 77 | PROVIDE( __global_pointer$ = . + 0x800); 78 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 79 | *(.srodata*) 80 | *(.sdata .sdata.* .gnu.linkonce.s.*) 81 | . = ALIGN(0x10); 82 | __sdata_end = .; 83 | } > ram 84 | 85 | /* data section */ 86 | .data : ALIGN(0x10) 87 | { 88 | __data_load = LOADADDR(.data); 89 | __data_start = .; 90 | *(.got.plt) *(.got) 91 | *(.shdata) 92 | *(.data .data.* .gnu.linkonce.d.*) 93 | . = ALIGN(0x10); 94 | __data_end = .; 95 | } > ram 96 | 97 | /* sbss section */ 98 | .sbss : ALIGN(0x10) 99 | { 100 | __sbss_start = .; 101 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 102 | *(.scommon) 103 | . = ALIGN(0x10); 104 | __sbss_end = .; 105 | } > ram 106 | 107 | /* sbss section */ 108 | .bss : ALIGN(0x10) 109 | { 110 | __bss_start = .; 111 | *(.shbss) 112 | *(.bss .bss.* .gnu.linkonce.b.*) 113 | *(COMMON) 114 | . = ALIGN(0x10); 115 | __bss_end = .; 116 | } > ram 117 | 118 | /* End of uninitialized data segment */ 119 | _end = .; 120 | 121 | .heap : ALIGN(0x10) 122 | { 123 | __heap_start = .; 124 | . += HEAP_SIZE; 125 | __heap_end = .; 126 | . = ALIGN(0x10); 127 | _heap_end = __heap_end; 128 | } > ram 129 | 130 | .stack : ALIGN(0x10) 131 | { 132 | __stack_bottom = .; 133 | . += STACK_SIZE; 134 | __stack_top = .; 135 | } > ram 136 | } 137 | 138 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/riscv_hal/microsemi-riscv-ram.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * file name : microsemi-riscv-ram.ld 5 | * Mi-V soft processor linker script for creating a SoftConsole downloadable 6 | * debug image executing in SRAM. 7 | * 8 | * This linker script assumes that the SRAM is connected at on the Mi-V soft 9 | * processor memory space. The start address and size of the memory space must 10 | * be correct as per the Libero design. 11 | * 12 | * SVN $Revision: 9661 $ 13 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 14 | */ 15 | 16 | OUTPUT_ARCH( "riscv" ) 17 | ENTRY(_start) 18 | 19 | 20 | MEMORY 21 | { 22 | ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64k 23 | } 24 | 25 | RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */ 26 | RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */ 27 | STACK_SIZE = 2k; /* needs to be calculated for your application */ 28 | HEAP_SIZE = 2k; /* needs to be calculated for your application */ 29 | 30 | SECTIONS 31 | { 32 | .text : ALIGN(0x10) 33 | { 34 | KEEP (*(SORT_NONE(.text.entry))) 35 | . = ALIGN(0x10); 36 | *(.text .text.* .gnu.linkonce.t.*) 37 | *(.plt) 38 | . = ALIGN(0x10); 39 | 40 | KEEP (*crtbegin.o(.ctors)) 41 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 42 | KEEP (*(SORT(.ctors.*))) 43 | KEEP (*crtend.o(.ctors)) 44 | KEEP (*crtbegin.o(.dtors)) 45 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 46 | KEEP (*(SORT(.dtors.*))) 47 | KEEP (*crtend.o(.dtors)) 48 | 49 | *(.rodata .rodata.* .gnu.linkonce.r.*) 50 | *(.gcc_except_table) 51 | *(.eh_frame_hdr) 52 | *(.eh_frame) 53 | 54 | KEEP (*(.init)) 55 | KEEP (*(.fini)) 56 | 57 | PROVIDE_HIDDEN (__preinit_array_start = .); 58 | KEEP (*(.preinit_array)) 59 | PROVIDE_HIDDEN (__preinit_array_end = .); 60 | PROVIDE_HIDDEN (__init_array_start = .); 61 | KEEP (*(SORT(.init_array.*))) 62 | KEEP (*(.init_array)) 63 | PROVIDE_HIDDEN (__init_array_end = .); 64 | PROVIDE_HIDDEN (__fini_array_start = .); 65 | KEEP (*(.fini_array)) 66 | KEEP (*(SORT(.fini_array.*))) 67 | PROVIDE_HIDDEN (__fini_array_end = .); 68 | . = ALIGN(0x10); 69 | 70 | } > ram 71 | 72 | /* short/global data section */ 73 | .sdata : ALIGN(0x10) 74 | { 75 | __sdata_load = LOADADDR(.sdata); 76 | __sdata_start = .; 77 | PROVIDE( __global_pointer$ = . + 0x800); 78 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 79 | *(.srodata*) 80 | *(.sdata .sdata.* .gnu.linkonce.s.*) 81 | . = ALIGN(0x10); 82 | __sdata_end = .; 83 | } > ram 84 | 85 | /* data section */ 86 | .data : ALIGN(0x10) 87 | { 88 | __data_load = LOADADDR(.data); 89 | __data_start = .; 90 | *(.got.plt) *(.got) 91 | *(.shdata) 92 | *(.data .data.* .gnu.linkonce.d.*) 93 | . = ALIGN(0x10); 94 | __data_end = .; 95 | } > ram 96 | 97 | /* sbss section */ 98 | .sbss : ALIGN(0x10) 99 | { 100 | __sbss_start = .; 101 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 102 | *(.scommon) 103 | . = ALIGN(0x10); 104 | __sbss_end = .; 105 | } > ram 106 | 107 | /* sbss section */ 108 | .bss : ALIGN(0x10) 109 | { 110 | __bss_start = .; 111 | *(.shbss) 112 | *(.bss .bss.* .gnu.linkonce.b.*) 113 | *(COMMON) 114 | . = ALIGN(0x10); 115 | __bss_end = .; 116 | } > ram 117 | 118 | /* End of uninitialized data segment */ 119 | _end = .; 120 | 121 | .heap : ALIGN(0x10) 122 | { 123 | __heap_start = .; 124 | . += HEAP_SIZE; 125 | __heap_end = .; 126 | . = ALIGN(0x10); 127 | _heap_end = __heap_end; 128 | } > ram 129 | 130 | .stack : ALIGN(0x10) 131 | { 132 | __stack_bottom = .; 133 | . += STACK_SIZE; 134 | __stack_top = .; 135 | } > ram 136 | } 137 | 138 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/riscv_hal/microsemi-riscv-ram.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * file name : microsemi-riscv-ram.ld 5 | * Mi-V soft processor linker script for creating a SoftConsole downloadable 6 | * debug image executing in SRAM. 7 | * 8 | * This linker script assumes that the SRAM is connected at on the Mi-V soft 9 | * processor memory space. The start address and size of the memory space must 10 | * be correct as per the Libero design. 11 | * 12 | * SVN $Revision: 9661 $ 13 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 14 | */ 15 | 16 | OUTPUT_ARCH( "riscv" ) 17 | ENTRY(_start) 18 | 19 | 20 | MEMORY 21 | { 22 | ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64k 23 | } 24 | 25 | RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */ 26 | RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */ 27 | STACK_SIZE = 2k; /* needs to be calculated for your application */ 28 | HEAP_SIZE = 2k; /* needs to be calculated for your application */ 29 | 30 | SECTIONS 31 | { 32 | .text : ALIGN(0x10) 33 | { 34 | KEEP (*(SORT_NONE(.text.entry))) 35 | . = ALIGN(0x10); 36 | *(.text .text.* .gnu.linkonce.t.*) 37 | *(.plt) 38 | . = ALIGN(0x10); 39 | 40 | KEEP (*crtbegin.o(.ctors)) 41 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 42 | KEEP (*(SORT(.ctors.*))) 43 | KEEP (*crtend.o(.ctors)) 44 | KEEP (*crtbegin.o(.dtors)) 45 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 46 | KEEP (*(SORT(.dtors.*))) 47 | KEEP (*crtend.o(.dtors)) 48 | 49 | *(.rodata .rodata.* .gnu.linkonce.r.*) 50 | *(.gcc_except_table) 51 | *(.eh_frame_hdr) 52 | *(.eh_frame) 53 | 54 | KEEP (*(.init)) 55 | KEEP (*(.fini)) 56 | 57 | PROVIDE_HIDDEN (__preinit_array_start = .); 58 | KEEP (*(.preinit_array)) 59 | PROVIDE_HIDDEN (__preinit_array_end = .); 60 | PROVIDE_HIDDEN (__init_array_start = .); 61 | KEEP (*(SORT(.init_array.*))) 62 | KEEP (*(.init_array)) 63 | PROVIDE_HIDDEN (__init_array_end = .); 64 | PROVIDE_HIDDEN (__fini_array_start = .); 65 | KEEP (*(.fini_array)) 66 | KEEP (*(SORT(.fini_array.*))) 67 | PROVIDE_HIDDEN (__fini_array_end = .); 68 | . = ALIGN(0x10); 69 | 70 | } > ram 71 | 72 | /* short/global data section */ 73 | .sdata : ALIGN(0x10) 74 | { 75 | __sdata_load = LOADADDR(.sdata); 76 | __sdata_start = .; 77 | PROVIDE( __global_pointer$ = . + 0x800); 78 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 79 | *(.srodata*) 80 | *(.sdata .sdata.* .gnu.linkonce.s.*) 81 | . = ALIGN(0x10); 82 | __sdata_end = .; 83 | } > ram 84 | 85 | /* data section */ 86 | .data : ALIGN(0x10) 87 | { 88 | __data_load = LOADADDR(.data); 89 | __data_start = .; 90 | *(.got.plt) *(.got) 91 | *(.shdata) 92 | *(.data .data.* .gnu.linkonce.d.*) 93 | . = ALIGN(0x10); 94 | __data_end = .; 95 | } > ram 96 | 97 | /* sbss section */ 98 | .sbss : ALIGN(0x10) 99 | { 100 | __sbss_start = .; 101 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 102 | *(.scommon) 103 | . = ALIGN(0x10); 104 | __sbss_end = .; 105 | } > ram 106 | 107 | /* sbss section */ 108 | .bss : ALIGN(0x10) 109 | { 110 | __bss_start = .; 111 | *(.shbss) 112 | *(.bss .bss.* .gnu.linkonce.b.*) 113 | *(COMMON) 114 | . = ALIGN(0x10); 115 | __bss_end = .; 116 | } > ram 117 | 118 | /* End of uninitialized data segment */ 119 | _end = .; 120 | 121 | .heap : ALIGN(0x10) 122 | { 123 | __heap_start = .; 124 | . += HEAP_SIZE; 125 | __heap_end = .; 126 | . = ALIGN(0x10); 127 | _heap_end = __heap_end; 128 | } > ram 129 | 130 | .stack : ALIGN(0x10) 131 | { 132 | __stack_bottom = .; 133 | . += STACK_SIZE; 134 | __stack_top = .; 135 | } > ram 136 | } 137 | 138 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/riscv_hal/entry.S: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file entry.S 5 | * @author Microsemi SoC Products Group 6 | * @brief Mi-V soft processor vectors, trap handling and startup code. 7 | * 8 | * SVN $Revision: 9947 $ 9 | * SVN $Date: 2018-04-30 20:28:49 +0530 (Mon, 30 Apr 2018) $ 10 | */ 11 | #ifndef ENTRY_S 12 | #define ENTRY_S 13 | 14 | #include "encoding.h" 15 | 16 | #if __riscv_xlen == 64 17 | # define LREG ld 18 | # define SREG sd 19 | # define REGBYTES 8 20 | #else 21 | # define LREG lw 22 | # define SREG sw 23 | # define REGBYTES 4 24 | #endif 25 | 26 | .section .text.entry 27 | .globl _start 28 | 29 | _start: 30 | j handle_reset 31 | 32 | nmi_vector: 33 | j nmi_vector 34 | 35 | trap_vector: 36 | j trap_entry 37 | 38 | handle_reset: 39 | la t0, trap_entry 40 | csrw mtvec, t0 41 | csrwi mstatus, 0 42 | csrwi mie, 0 43 | 44 | /*Floating point support configuration*/ 45 | 46 | #ifdef __riscv_flen 47 | csrr t0, mstatus 48 | lui t1, 0xffffa 49 | addi t1, t1, -1 50 | and t0, t0, t1 51 | lui t1, 0x4 52 | or t1, t0, t1 53 | csrw mstatus, t1 54 | 55 | lui t0, 0x0 56 | fscsr t0 57 | #endif 58 | .option push 59 | 60 | # Ensure the instruction is not optimized, since gp is not yet set 61 | 62 | .option norelax 63 | # initialize global pointer 64 | la gp, __global_pointer$ 65 | 66 | .option pop 67 | 68 | # initialize stack pointer 69 | la sp, __stack_top 70 | 71 | # perform the rest of initialization in C 72 | j _init 73 | 74 | 75 | trap_entry: 76 | addi sp, sp, -32*REGBYTES 77 | 78 | SREG x1, 0 * REGBYTES(sp) 79 | SREG x2, 1 * REGBYTES(sp) 80 | SREG x3, 2 * REGBYTES(sp) 81 | SREG x4, 3 * REGBYTES(sp) 82 | SREG x5, 4 * REGBYTES(sp) 83 | SREG x6, 5 * REGBYTES(sp) 84 | SREG x7, 6 * REGBYTES(sp) 85 | SREG x8, 7 * REGBYTES(sp) 86 | SREG x9, 8 * REGBYTES(sp) 87 | SREG x10, 9 * REGBYTES(sp) 88 | SREG x11, 10 * REGBYTES(sp) 89 | SREG x12, 11 * REGBYTES(sp) 90 | SREG x13, 12 * REGBYTES(sp) 91 | SREG x14, 13 * REGBYTES(sp) 92 | SREG x15, 14 * REGBYTES(sp) 93 | SREG x16, 15 * REGBYTES(sp) 94 | SREG x17, 16 * REGBYTES(sp) 95 | SREG x18, 17 * REGBYTES(sp) 96 | SREG x19, 18 * REGBYTES(sp) 97 | SREG x20, 19 * REGBYTES(sp) 98 | SREG x21, 20 * REGBYTES(sp) 99 | SREG x22, 21 * REGBYTES(sp) 100 | SREG x23, 22 * REGBYTES(sp) 101 | SREG x24, 23 * REGBYTES(sp) 102 | SREG x25, 24 * REGBYTES(sp) 103 | SREG x26, 25 * REGBYTES(sp) 104 | SREG x27, 26 * REGBYTES(sp) 105 | SREG x28, 27 * REGBYTES(sp) 106 | SREG x29, 28 * REGBYTES(sp) 107 | SREG x30, 29 * REGBYTES(sp) 108 | SREG x31, 30 * REGBYTES(sp) 109 | 110 | 111 | csrr t0, mepc 112 | SREG t0, 31 * REGBYTES(sp) 113 | 114 | csrr a0, mcause 115 | csrr a1, mepc 116 | mv a2, sp 117 | jal handle_trap 118 | csrw mepc, a0 119 | 120 | # Remain in M-mode after mret 121 | li t0, MSTATUS_MPP 122 | csrs mstatus, t0 123 | 124 | LREG x1, 0 * REGBYTES(sp) 125 | LREG x2, 1 * REGBYTES(sp) 126 | LREG x3, 2 * REGBYTES(sp) 127 | LREG x4, 3 * REGBYTES(sp) 128 | LREG x5, 4 * REGBYTES(sp) 129 | LREG x6, 5 * REGBYTES(sp) 130 | LREG x7, 6 * REGBYTES(sp) 131 | LREG x8, 7 * REGBYTES(sp) 132 | LREG x9, 8 * REGBYTES(sp) 133 | LREG x10, 9 * REGBYTES(sp) 134 | LREG x11, 10 * REGBYTES(sp) 135 | LREG x12, 11 * REGBYTES(sp) 136 | LREG x13, 12 * REGBYTES(sp) 137 | LREG x14, 13 * REGBYTES(sp) 138 | LREG x15, 14 * REGBYTES(sp) 139 | LREG x16, 15 * REGBYTES(sp) 140 | LREG x17, 16 * REGBYTES(sp) 141 | LREG x18, 17 * REGBYTES(sp) 142 | LREG x19, 18 * REGBYTES(sp) 143 | LREG x20, 19 * REGBYTES(sp) 144 | LREG x21, 20 * REGBYTES(sp) 145 | LREG x22, 21 * REGBYTES(sp) 146 | LREG x23, 22 * REGBYTES(sp) 147 | LREG x24, 23 * REGBYTES(sp) 148 | LREG x25, 24 * REGBYTES(sp) 149 | LREG x26, 25 * REGBYTES(sp) 150 | LREG x27, 26 * REGBYTES(sp) 151 | LREG x28, 27 * REGBYTES(sp) 152 | LREG x29, 28 * REGBYTES(sp) 153 | LREG x30, 29 * REGBYTES(sp) 154 | LREG x31, 30 * REGBYTES(sp) 155 | 156 | addi sp, sp, 32*REGBYTES 157 | mret 158 | 159 | #endif 160 | 161 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/riscv_hal/entry.S: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file entry.S 5 | * @author Microsemi SoC Products Group 6 | * @brief Mi-V soft processor vectors, trap handling and startup code. 7 | * 8 | * SVN $Revision: 9947 $ 9 | * SVN $Date: 2018-04-30 20:28:49 +0530 (Mon, 30 Apr 2018) $ 10 | */ 11 | #ifndef ENTRY_S 12 | #define ENTRY_S 13 | 14 | #include "encoding.h" 15 | 16 | #if __riscv_xlen == 64 17 | # define LREG ld 18 | # define SREG sd 19 | # define REGBYTES 8 20 | #else 21 | # define LREG lw 22 | # define SREG sw 23 | # define REGBYTES 4 24 | #endif 25 | 26 | .section .text.entry 27 | .globl _start 28 | 29 | _start: 30 | j handle_reset 31 | 32 | nmi_vector: 33 | j nmi_vector 34 | 35 | trap_vector: 36 | j trap_entry 37 | 38 | handle_reset: 39 | la t0, trap_entry 40 | csrw mtvec, t0 41 | csrwi mstatus, 0 42 | csrwi mie, 0 43 | 44 | /*Floating point support configuration*/ 45 | 46 | #ifdef __riscv_flen 47 | csrr t0, mstatus 48 | lui t1, 0xffffa 49 | addi t1, t1, -1 50 | and t0, t0, t1 51 | lui t1, 0x4 52 | or t1, t0, t1 53 | csrw mstatus, t1 54 | 55 | lui t0, 0x0 56 | fscsr t0 57 | #endif 58 | .option push 59 | 60 | # Ensure the instruction is not optimized, since gp is not yet set 61 | 62 | .option norelax 63 | # initialize global pointer 64 | la gp, __global_pointer$ 65 | 66 | .option pop 67 | 68 | # initialize stack pointer 69 | la sp, __stack_top 70 | 71 | # perform the rest of initialization in C 72 | j _init 73 | 74 | 75 | trap_entry: 76 | addi sp, sp, -32*REGBYTES 77 | 78 | SREG x1, 0 * REGBYTES(sp) 79 | SREG x2, 1 * REGBYTES(sp) 80 | SREG x3, 2 * REGBYTES(sp) 81 | SREG x4, 3 * REGBYTES(sp) 82 | SREG x5, 4 * REGBYTES(sp) 83 | SREG x6, 5 * REGBYTES(sp) 84 | SREG x7, 6 * REGBYTES(sp) 85 | SREG x8, 7 * REGBYTES(sp) 86 | SREG x9, 8 * REGBYTES(sp) 87 | SREG x10, 9 * REGBYTES(sp) 88 | SREG x11, 10 * REGBYTES(sp) 89 | SREG x12, 11 * REGBYTES(sp) 90 | SREG x13, 12 * REGBYTES(sp) 91 | SREG x14, 13 * REGBYTES(sp) 92 | SREG x15, 14 * REGBYTES(sp) 93 | SREG x16, 15 * REGBYTES(sp) 94 | SREG x17, 16 * REGBYTES(sp) 95 | SREG x18, 17 * REGBYTES(sp) 96 | SREG x19, 18 * REGBYTES(sp) 97 | SREG x20, 19 * REGBYTES(sp) 98 | SREG x21, 20 * REGBYTES(sp) 99 | SREG x22, 21 * REGBYTES(sp) 100 | SREG x23, 22 * REGBYTES(sp) 101 | SREG x24, 23 * REGBYTES(sp) 102 | SREG x25, 24 * REGBYTES(sp) 103 | SREG x26, 25 * REGBYTES(sp) 104 | SREG x27, 26 * REGBYTES(sp) 105 | SREG x28, 27 * REGBYTES(sp) 106 | SREG x29, 28 * REGBYTES(sp) 107 | SREG x30, 29 * REGBYTES(sp) 108 | SREG x31, 30 * REGBYTES(sp) 109 | 110 | 111 | csrr t0, mepc 112 | SREG t0, 31 * REGBYTES(sp) 113 | 114 | csrr a0, mcause 115 | csrr a1, mepc 116 | mv a2, sp 117 | jal handle_trap 118 | csrw mepc, a0 119 | 120 | # Remain in M-mode after mret 121 | li t0, MSTATUS_MPP 122 | csrs mstatus, t0 123 | 124 | LREG x1, 0 * REGBYTES(sp) 125 | LREG x2, 1 * REGBYTES(sp) 126 | LREG x3, 2 * REGBYTES(sp) 127 | LREG x4, 3 * REGBYTES(sp) 128 | LREG x5, 4 * REGBYTES(sp) 129 | LREG x6, 5 * REGBYTES(sp) 130 | LREG x7, 6 * REGBYTES(sp) 131 | LREG x8, 7 * REGBYTES(sp) 132 | LREG x9, 8 * REGBYTES(sp) 133 | LREG x10, 9 * REGBYTES(sp) 134 | LREG x11, 10 * REGBYTES(sp) 135 | LREG x12, 11 * REGBYTES(sp) 136 | LREG x13, 12 * REGBYTES(sp) 137 | LREG x14, 13 * REGBYTES(sp) 138 | LREG x15, 14 * REGBYTES(sp) 139 | LREG x16, 15 * REGBYTES(sp) 140 | LREG x17, 16 * REGBYTES(sp) 141 | LREG x18, 17 * REGBYTES(sp) 142 | LREG x19, 18 * REGBYTES(sp) 143 | LREG x20, 19 * REGBYTES(sp) 144 | LREG x21, 20 * REGBYTES(sp) 145 | LREG x22, 21 * REGBYTES(sp) 146 | LREG x23, 22 * REGBYTES(sp) 147 | LREG x24, 23 * REGBYTES(sp) 148 | LREG x25, 24 * REGBYTES(sp) 149 | LREG x26, 25 * REGBYTES(sp) 150 | LREG x27, 26 * REGBYTES(sp) 151 | LREG x28, 27 * REGBYTES(sp) 152 | LREG x29, 28 * REGBYTES(sp) 153 | LREG x30, 29 * REGBYTES(sp) 154 | LREG x31, 30 * REGBYTES(sp) 155 | 156 | addi sp, sp, 32*REGBYTES 157 | mret 158 | 159 | #endif 160 | 161 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/riscv_hal/entry.S: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * @file entry.S 5 | * @author Microsemi SoC Products Group 6 | * @brief Mi-V soft processor vectors, trap handling and startup code. 7 | * 8 | * SVN $Revision: 9947 $ 9 | * SVN $Date: 2018-04-30 20:28:49 +0530 (Mon, 30 Apr 2018) $ 10 | */ 11 | #ifndef ENTRY_S 12 | #define ENTRY_S 13 | 14 | #include "encoding.h" 15 | 16 | #if __riscv_xlen == 64 17 | # define LREG ld 18 | # define SREG sd 19 | # define REGBYTES 8 20 | #else 21 | # define LREG lw 22 | # define SREG sw 23 | # define REGBYTES 4 24 | #endif 25 | 26 | .section .text.entry 27 | .globl _start 28 | 29 | _start: 30 | j handle_reset 31 | 32 | nmi_vector: 33 | j nmi_vector 34 | 35 | trap_vector: 36 | j trap_entry 37 | 38 | handle_reset: 39 | la t0, trap_entry 40 | csrw mtvec, t0 41 | csrwi mstatus, 0 42 | csrwi mie, 0 43 | 44 | /*Floating point support configuration*/ 45 | 46 | #ifdef __riscv_flen 47 | csrr t0, mstatus 48 | lui t1, 0xffffa 49 | addi t1, t1, -1 50 | and t0, t0, t1 51 | lui t1, 0x4 52 | or t1, t0, t1 53 | csrw mstatus, t1 54 | 55 | lui t0, 0x0 56 | fscsr t0 57 | #endif 58 | .option push 59 | 60 | # Ensure the instruction is not optimized, since gp is not yet set 61 | 62 | .option norelax 63 | # initialize global pointer 64 | la gp, __global_pointer$ 65 | 66 | .option pop 67 | 68 | # initialize stack pointer 69 | la sp, __stack_top 70 | 71 | # perform the rest of initialization in C 72 | j _init 73 | 74 | 75 | trap_entry: 76 | addi sp, sp, -32*REGBYTES 77 | 78 | SREG x1, 0 * REGBYTES(sp) 79 | SREG x2, 1 * REGBYTES(sp) 80 | SREG x3, 2 * REGBYTES(sp) 81 | SREG x4, 3 * REGBYTES(sp) 82 | SREG x5, 4 * REGBYTES(sp) 83 | SREG x6, 5 * REGBYTES(sp) 84 | SREG x7, 6 * REGBYTES(sp) 85 | SREG x8, 7 * REGBYTES(sp) 86 | SREG x9, 8 * REGBYTES(sp) 87 | SREG x10, 9 * REGBYTES(sp) 88 | SREG x11, 10 * REGBYTES(sp) 89 | SREG x12, 11 * REGBYTES(sp) 90 | SREG x13, 12 * REGBYTES(sp) 91 | SREG x14, 13 * REGBYTES(sp) 92 | SREG x15, 14 * REGBYTES(sp) 93 | SREG x16, 15 * REGBYTES(sp) 94 | SREG x17, 16 * REGBYTES(sp) 95 | SREG x18, 17 * REGBYTES(sp) 96 | SREG x19, 18 * REGBYTES(sp) 97 | SREG x20, 19 * REGBYTES(sp) 98 | SREG x21, 20 * REGBYTES(sp) 99 | SREG x22, 21 * REGBYTES(sp) 100 | SREG x23, 22 * REGBYTES(sp) 101 | SREG x24, 23 * REGBYTES(sp) 102 | SREG x25, 24 * REGBYTES(sp) 103 | SREG x26, 25 * REGBYTES(sp) 104 | SREG x27, 26 * REGBYTES(sp) 105 | SREG x28, 27 * REGBYTES(sp) 106 | SREG x29, 28 * REGBYTES(sp) 107 | SREG x30, 29 * REGBYTES(sp) 108 | SREG x31, 30 * REGBYTES(sp) 109 | 110 | 111 | csrr t0, mepc 112 | SREG t0, 31 * REGBYTES(sp) 113 | 114 | csrr a0, mcause 115 | csrr a1, mepc 116 | mv a2, sp 117 | jal handle_trap 118 | csrw mepc, a0 119 | 120 | # Remain in M-mode after mret 121 | li t0, MSTATUS_MPP 122 | csrs mstatus, t0 123 | 124 | LREG x1, 0 * REGBYTES(sp) 125 | LREG x2, 1 * REGBYTES(sp) 126 | LREG x3, 2 * REGBYTES(sp) 127 | LREG x4, 3 * REGBYTES(sp) 128 | LREG x5, 4 * REGBYTES(sp) 129 | LREG x6, 5 * REGBYTES(sp) 130 | LREG x7, 6 * REGBYTES(sp) 131 | LREG x8, 7 * REGBYTES(sp) 132 | LREG x9, 8 * REGBYTES(sp) 133 | LREG x10, 9 * REGBYTES(sp) 134 | LREG x11, 10 * REGBYTES(sp) 135 | LREG x12, 11 * REGBYTES(sp) 136 | LREG x13, 12 * REGBYTES(sp) 137 | LREG x14, 13 * REGBYTES(sp) 138 | LREG x15, 14 * REGBYTES(sp) 139 | LREG x16, 15 * REGBYTES(sp) 140 | LREG x17, 16 * REGBYTES(sp) 141 | LREG x18, 17 * REGBYTES(sp) 142 | LREG x19, 18 * REGBYTES(sp) 143 | LREG x20, 19 * REGBYTES(sp) 144 | LREG x21, 20 * REGBYTES(sp) 145 | LREG x22, 21 * REGBYTES(sp) 146 | LREG x23, 22 * REGBYTES(sp) 147 | LREG x24, 23 * REGBYTES(sp) 148 | LREG x25, 24 * REGBYTES(sp) 149 | LREG x26, 25 * REGBYTES(sp) 150 | LREG x27, 26 * REGBYTES(sp) 151 | LREG x28, 27 * REGBYTES(sp) 152 | LREG x29, 28 * REGBYTES(sp) 153 | LREG x30, 29 * REGBYTES(sp) 154 | LREG x31, 30 * REGBYTES(sp) 155 | 156 | addi sp, sp, 32*REGBYTES 157 | mret 158 | 159 | #endif 160 | 161 | -------------------------------------------------------------------------------- /Dhrystone/hal/hw_macros.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * Hardware registers access macros. 5 | * 6 | * THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW 7 | * DEVELOPMENT. 8 | * 9 | * These macros are used to access peripheral's registers. They allow access to 10 | * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should 11 | * be done through these macros in order to ease porting across different 12 | * processors/bus architectures. 13 | * 14 | * Some of these macros also allow to access a specific register field. 15 | * 16 | * SVN $Revision: 9661 $ 17 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 18 | */ 19 | #ifndef __HW_REGISTER_MACROS_H 20 | #define __HW_REGISTER_MACROS_H 1 21 | 22 | /*------------------------------------------------------------------------------ 23 | * 32 bits registers access: 24 | */ 25 | #define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 26 | 27 | #define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 28 | 29 | #define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \ 30 | (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 31 | ( \ 32 | (uint32_t) \ 33 | ( \ 34 | (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 35 | (uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 36 | ) \ 37 | ) 38 | 39 | #define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \ 40 | (( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 41 | 42 | /*------------------------------------------------------------------------------ 43 | * 32 bits memory access: 44 | */ 45 | #define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR))) 46 | 47 | #define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE)) 48 | 49 | /*------------------------------------------------------------------------------ 50 | * 16 bits registers access: 51 | */ 52 | #define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 53 | 54 | #define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 55 | 56 | #define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \ 57 | (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 58 | ( \ 59 | (uint16_t) \ 60 | ( \ 61 | (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 62 | (uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 63 | ) \ 64 | ) 65 | 66 | #define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \ 67 | (( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 68 | 69 | /*------------------------------------------------------------------------------ 70 | * 8 bits registers access: 71 | */ 72 | #define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 73 | 74 | #define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 75 | 76 | #define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \ 77 | (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 78 | ( \ 79 | (uint8_t) \ 80 | ( \ 81 | (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 82 | (uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 83 | ) \ 84 | ) 85 | 86 | #define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \ 87 | (( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 88 | 89 | /*------------------------------------------------------------------------------ 90 | * 8 bits memory access: 91 | */ 92 | #define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR))) 93 | 94 | #define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE)) 95 | 96 | #endif /* __HW_REGISTER_MACROS_H */ 97 | 98 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/hal/hw_macros.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * Hardware registers access macros. 5 | * 6 | * THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW 7 | * DEVELOPMENT. 8 | * 9 | * These macros are used to access peripheral's registers. They allow access to 10 | * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should 11 | * be done through these macros in order to ease porting across different 12 | * processors/bus architectures. 13 | * 14 | * Some of these macros also allow to access a specific register field. 15 | * 16 | * SVN $Revision: 9085 $ 17 | * SVN $Date: 2017-04-28 14:29:14 +0530 (Fri, 28 Apr 2017) $ 18 | */ 19 | #ifndef __HW_REGISTER_MACROS_H 20 | #define __HW_REGISTER_MACROS_H 1 21 | 22 | /*------------------------------------------------------------------------------ 23 | * 32 bits registers access: 24 | */ 25 | #define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 26 | 27 | #define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 28 | 29 | #define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \ 30 | (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 31 | ( \ 32 | (uint32_t) \ 33 | ( \ 34 | (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 35 | (uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 36 | ) \ 37 | ) 38 | 39 | #define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \ 40 | (( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 41 | 42 | /*------------------------------------------------------------------------------ 43 | * 32 bits memory access: 44 | */ 45 | #define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR))) 46 | 47 | #define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE)) 48 | 49 | /*------------------------------------------------------------------------------ 50 | * 16 bits registers access: 51 | */ 52 | #define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 53 | 54 | #define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 55 | 56 | #define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \ 57 | (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 58 | ( \ 59 | (uint16_t) \ 60 | ( \ 61 | (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 62 | (uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 63 | ) \ 64 | ) 65 | 66 | #define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \ 67 | (( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 68 | 69 | /*------------------------------------------------------------------------------ 70 | * 8 bits registers access: 71 | */ 72 | #define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 73 | 74 | #define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 75 | 76 | #define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \ 77 | (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 78 | ( \ 79 | (uint8_t) \ 80 | ( \ 81 | (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 82 | (uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 83 | ) \ 84 | ) 85 | 86 | #define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \ 87 | (( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 88 | 89 | /*------------------------------------------------------------------------------ 90 | * 8 bits memory access: 91 | */ 92 | #define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR))) 93 | 94 | #define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE)) 95 | 96 | #endif /* __HW_REGISTER_MACROS_H */ 97 | 98 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/hal/hw_macros.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * Hardware registers access macros. 5 | * 6 | * THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW 7 | * DEVELOPMENT. 8 | * 9 | * These macros are used to access peripheral's registers. They allow access to 10 | * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should 11 | * be done through these macros in order to ease porting across different 12 | * processors/bus architectures. 13 | * 14 | * Some of these macros also allow to access a specific register field. 15 | * 16 | * SVN $Revision: 9661 $ 17 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 18 | */ 19 | #ifndef __HW_REGISTER_MACROS_H 20 | #define __HW_REGISTER_MACROS_H 1 21 | 22 | /*------------------------------------------------------------------------------ 23 | * 32 bits registers access: 24 | */ 25 | #define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 26 | 27 | #define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 28 | 29 | #define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \ 30 | (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 31 | ( \ 32 | (uint32_t) \ 33 | ( \ 34 | (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 35 | (uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 36 | ) \ 37 | ) 38 | 39 | #define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \ 40 | (( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 41 | 42 | /*------------------------------------------------------------------------------ 43 | * 32 bits memory access: 44 | */ 45 | #define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR))) 46 | 47 | #define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE)) 48 | 49 | /*------------------------------------------------------------------------------ 50 | * 16 bits registers access: 51 | */ 52 | #define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 53 | 54 | #define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 55 | 56 | #define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \ 57 | (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 58 | ( \ 59 | (uint16_t) \ 60 | ( \ 61 | (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 62 | (uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 63 | ) \ 64 | ) 65 | 66 | #define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \ 67 | (( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 68 | 69 | /*------------------------------------------------------------------------------ 70 | * 8 bits registers access: 71 | */ 72 | #define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 73 | 74 | #define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 75 | 76 | #define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \ 77 | (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 78 | ( \ 79 | (uint8_t) \ 80 | ( \ 81 | (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 82 | (uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 83 | ) \ 84 | ) 85 | 86 | #define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \ 87 | (( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 88 | 89 | /*------------------------------------------------------------------------------ 90 | * 8 bits memory access: 91 | */ 92 | #define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR))) 93 | 94 | #define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE)) 95 | 96 | #endif /* __HW_REGISTER_MACROS_H */ 97 | 98 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/hal/hw_macros.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * Hardware registers access macros. 5 | * 6 | * THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW 7 | * DEVELOPMENT. 8 | * 9 | * These macros are used to access peripheral's registers. They allow access to 10 | * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should 11 | * be done through these macros in order to ease porting across different 12 | * processors/bus architectures. 13 | * 14 | * Some of these macros also allow to access a specific register field. 15 | * 16 | * SVN $Revision: 9661 $ 17 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 18 | */ 19 | #ifndef __HW_REGISTER_MACROS_H 20 | #define __HW_REGISTER_MACROS_H 1 21 | 22 | /*------------------------------------------------------------------------------ 23 | * 32 bits registers access: 24 | */ 25 | #define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 26 | 27 | #define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 28 | 29 | #define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \ 30 | (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 31 | ( \ 32 | (uint32_t) \ 33 | ( \ 34 | (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 35 | (uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 36 | ) \ 37 | ) 38 | 39 | #define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \ 40 | (( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 41 | 42 | /*------------------------------------------------------------------------------ 43 | * 32 bits memory access: 44 | */ 45 | #define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR))) 46 | 47 | #define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE)) 48 | 49 | /*------------------------------------------------------------------------------ 50 | * 16 bits registers access: 51 | */ 52 | #define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 53 | 54 | #define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 55 | 56 | #define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \ 57 | (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 58 | ( \ 59 | (uint16_t) \ 60 | ( \ 61 | (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 62 | (uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 63 | ) \ 64 | ) 65 | 66 | #define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \ 67 | (( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 68 | 69 | /*------------------------------------------------------------------------------ 70 | * 8 bits registers access: 71 | */ 72 | #define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) 73 | 74 | #define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) 75 | 76 | #define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \ 77 | (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ 78 | ( \ 79 | (uint8_t) \ 80 | ( \ 81 | (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ 82 | (uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ 83 | ) \ 84 | ) 85 | 86 | #define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \ 87 | (( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) 88 | 89 | /*------------------------------------------------------------------------------ 90 | * 8 bits memory access: 91 | */ 92 | #define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR))) 93 | 94 | #define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE)) 95 | 96 | #endif /* __HW_REGISTER_MACROS_H */ 97 | 98 | -------------------------------------------------------------------------------- /Dhrystone/drivers/CoreTimer/core_timer.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * CoreTimer driver implementation. 5 | * 6 | * SVN $Revision: 9665 $ 7 | * SVN $Date: 2018-01-16 16:41:53 +0530 (Tue, 16 Jan 2018) $ 8 | */ 9 | 10 | #include "core_timer.h" 11 | #include "coretimer_regs.h" 12 | #include "hal.h" 13 | #include "hal_assert.h" 14 | 15 | #ifndef NDEBUG 16 | static timer_instance_t* NULL_timer_instance; 17 | #endif 18 | 19 | /***************************************************************************//** 20 | * TMR_init() 21 | * See "core_timer.h" for details of how to use this function. 22 | */ 23 | void 24 | TMR_init 25 | ( 26 | timer_instance_t * this_timer, 27 | addr_t address, 28 | uint8_t mode, 29 | uint32_t prescale, 30 | uint32_t load_value 31 | ) 32 | { 33 | HAL_ASSERT( this_timer != NULL_timer_instance ) 34 | HAL_ASSERT( prescale <= PRESCALER_DIV_1024 ) 35 | HAL_ASSERT( load_value != 0 ) 36 | 37 | this_timer->base_address = address; 38 | 39 | /* Disable interrupts. */ 40 | HAL_set_32bit_reg_field( address, InterruptEnable,0 ); 41 | 42 | /* Disable timer. */ 43 | HAL_set_32bit_reg_field( address, TimerEnable, 0 ); 44 | 45 | /* Clear pending interrupt. */ 46 | HAL_set_32bit_reg( address, TimerIntClr, 1 ); 47 | 48 | /* Configure prescaler and load value. */ 49 | HAL_set_32bit_reg( address, TimerPrescale, prescale ); 50 | HAL_set_32bit_reg( address, TimerLoad, load_value ); 51 | 52 | /* Set the interrupt mode. */ 53 | if ( mode == TMR_CONTINUOUS_MODE ) 54 | { 55 | HAL_set_32bit_reg_field( address, TimerMode, 0 ); 56 | } 57 | else 58 | { 59 | /* TMR_ONE_SHOT_MODE */ 60 | HAL_set_32bit_reg_field( address, TimerMode, 1 ); 61 | } 62 | } 63 | 64 | /***************************************************************************//** 65 | * TMR_start() 66 | * See "core_timer.h" for details of how to use this function. 67 | */ 68 | void 69 | TMR_start 70 | ( 71 | timer_instance_t * this_timer 72 | ) 73 | { 74 | HAL_ASSERT( this_timer != NULL_timer_instance ) 75 | 76 | HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 1 ); 77 | } 78 | 79 | /***************************************************************************//** 80 | * TMR_stop() 81 | * See "core_timer.h" for details of how to use this function. 82 | */ 83 | void 84 | TMR_stop 85 | ( 86 | timer_instance_t * this_timer 87 | ) 88 | { 89 | HAL_ASSERT( this_timer != NULL_timer_instance ) 90 | 91 | HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 0 ); 92 | } 93 | 94 | 95 | /***************************************************************************//** 96 | * TMR_enable_int() 97 | * See "core_timer.h" for details of how to use this function. 98 | */ 99 | void 100 | TMR_enable_int 101 | ( 102 | timer_instance_t * this_timer 103 | ) 104 | { 105 | HAL_ASSERT( this_timer != NULL_timer_instance ) 106 | 107 | HAL_set_32bit_reg_field( this_timer->base_address, InterruptEnable, 1 ); 108 | } 109 | 110 | /***************************************************************************//** 111 | * TMR_clear_int() 112 | * See "core_timer.h" for details of how to use this function. 113 | */ 114 | void 115 | TMR_clear_int 116 | ( 117 | timer_instance_t * this_timer 118 | ) 119 | { 120 | HAL_ASSERT( this_timer != NULL_timer_instance ) 121 | 122 | HAL_set_32bit_reg( this_timer->base_address, TimerIntClr, 0x01 ); 123 | } 124 | 125 | /***************************************************************************//** 126 | * TMR_current_value() 127 | * See "core_timer.h" for details of how to use this function. 128 | */ 129 | uint32_t 130 | TMR_current_value 131 | ( 132 | timer_instance_t * this_timer 133 | ) 134 | { 135 | uint32_t value = 0; 136 | HAL_ASSERT( this_timer != NULL_timer_instance ) 137 | 138 | value = HAL_get_32bit_reg( this_timer->base_address, TimerValue ); 139 | 140 | return value; 141 | } 142 | 143 | /***************************************************************************//** 144 | * TMR_reload() 145 | * See "core_timer.h" for details of how to use this function. 146 | */ 147 | void TMR_reload 148 | ( 149 | timer_instance_t * this_timer, 150 | uint32_t load_value 151 | ) 152 | { 153 | HAL_ASSERT( this_timer != NULL_timer_instance ) 154 | HAL_ASSERT( load_value != 0 ) 155 | 156 | HAL_set_32bit_reg(this_timer->base_address, TimerLoad, load_value ); 157 | } 158 | 159 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/drivers/CoreTimer/core_timer.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * CoreTimer driver implementation. 5 | * 6 | * SVN $Revision: 8933 $ 7 | * SVN $Date: 2017-03-31 13:54:33 +0530 (Fri, 31 Mar 2017) $ 8 | */ 9 | 10 | #include "core_timer.h" 11 | #include "coretimer_regs.h" 12 | #include "hal.h" 13 | #include "hal_assert.h" 14 | 15 | #ifndef NDEBUG 16 | static timer_instance_t* NULL_timer_instance; 17 | #endif 18 | 19 | /***************************************************************************//** 20 | * TMR_init() 21 | * See "core_timer.h" for details of how to use this function. 22 | */ 23 | void 24 | TMR_init 25 | ( 26 | timer_instance_t * this_timer, 27 | addr_t address, 28 | uint8_t mode, 29 | uint32_t prescale, 30 | uint32_t load_value 31 | ) 32 | { 33 | HAL_ASSERT( this_timer != NULL_timer_instance ) 34 | HAL_ASSERT( prescale <= PRESCALER_DIV_1024 ) 35 | HAL_ASSERT( load_value != 0 ) 36 | 37 | this_timer->base_address = address; 38 | 39 | /* Disable interrupts. */ 40 | HAL_set_32bit_reg_field( address, InterruptEnable,0 ); 41 | 42 | /* Disable timer. */ 43 | HAL_set_32bit_reg_field( address, TimerEnable, 0 ); 44 | 45 | /* Clear pending interrupt. */ 46 | HAL_set_32bit_reg( address, TimerIntClr, 1 ); 47 | 48 | /* Configure prescaler and load value. */ 49 | HAL_set_32bit_reg( address, TimerPrescale, prescale ); 50 | HAL_set_32bit_reg( address, TimerLoad, load_value ); 51 | 52 | /* Set the interrupt mode. */ 53 | if ( mode == TMR_CONTINUOUS_MODE ) 54 | { 55 | HAL_set_32bit_reg_field( address, TimerMode, 0 ); 56 | } 57 | else 58 | { 59 | /* TMR_ONE_SHOT_MODE */ 60 | HAL_set_32bit_reg_field( address, TimerMode, 1 ); 61 | } 62 | } 63 | 64 | /***************************************************************************//** 65 | * TMR_start() 66 | * See "core_timer.h" for details of how to use this function. 67 | */ 68 | void 69 | TMR_start 70 | ( 71 | timer_instance_t * this_timer 72 | ) 73 | { 74 | HAL_ASSERT( this_timer != NULL_timer_instance ) 75 | 76 | HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 1 ); 77 | } 78 | 79 | /***************************************************************************//** 80 | * TMR_stop() 81 | * See "core_timer.h" for details of how to use this function. 82 | */ 83 | void 84 | TMR_stop 85 | ( 86 | timer_instance_t * this_timer 87 | ) 88 | { 89 | HAL_ASSERT( this_timer != NULL_timer_instance ) 90 | 91 | HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 0 ); 92 | } 93 | 94 | 95 | /***************************************************************************//** 96 | * TMR_enable_int() 97 | * See "core_timer.h" for details of how to use this function. 98 | */ 99 | void 100 | TMR_enable_int 101 | ( 102 | timer_instance_t * this_timer 103 | ) 104 | { 105 | HAL_ASSERT( this_timer != NULL_timer_instance ) 106 | 107 | HAL_set_32bit_reg_field( this_timer->base_address, InterruptEnable, 1 ); 108 | } 109 | 110 | /***************************************************************************//** 111 | * TMR_clear_int() 112 | * See "core_timer.h" for details of how to use this function. 113 | */ 114 | void 115 | TMR_clear_int 116 | ( 117 | timer_instance_t * this_timer 118 | ) 119 | { 120 | HAL_ASSERT( this_timer != NULL_timer_instance ) 121 | 122 | HAL_set_32bit_reg( this_timer->base_address, TimerIntClr, 0x01 ); 123 | } 124 | 125 | /***************************************************************************//** 126 | * TMR_current_value() 127 | * See "core_timer.h" for details of how to use this function. 128 | */ 129 | uint32_t 130 | TMR_current_value 131 | ( 132 | timer_instance_t * this_timer 133 | ) 134 | { 135 | uint32_t value = 0; 136 | HAL_ASSERT( this_timer != NULL_timer_instance ) 137 | 138 | value = HAL_get_32bit_reg( this_timer->base_address, TimerValue ); 139 | 140 | return value; 141 | } 142 | 143 | /***************************************************************************//** 144 | * TMR_reload() 145 | * See "core_timer.h" for details of how to use this function. 146 | */ 147 | void TMR_reload 148 | ( 149 | timer_instance_t * this_timer, 150 | uint32_t load_value 151 | ) 152 | { 153 | HAL_ASSERT( this_timer != NULL_timer_instance ) 154 | HAL_ASSERT( load_value != 0 ) 155 | 156 | HAL_set_32bit_reg(this_timer->base_address, TimerLoad, load_value ); 157 | } 158 | 159 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/drivers/CoreTimer/core_timer.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved. 3 | * 4 | * CoreTimer driver implementation. 5 | * 6 | * SVN $Revision: 8933 $ 7 | * SVN $Date: 2017-03-31 13:54:33 +0530 (Fri, 31 Mar 2017) $ 8 | */ 9 | 10 | #include "core_timer.h" 11 | #include "coretimer_regs.h" 12 | #include "hal.h" 13 | #include "hal_assert.h" 14 | 15 | #ifndef NDEBUG 16 | static timer_instance_t* NULL_timer_instance; 17 | #endif 18 | 19 | /***************************************************************************//** 20 | * TMR_init() 21 | * See "core_timer.h" for details of how to use this function. 22 | */ 23 | void 24 | TMR_init 25 | ( 26 | timer_instance_t * this_timer, 27 | addr_t address, 28 | uint8_t mode, 29 | uint32_t prescale, 30 | uint32_t load_value 31 | ) 32 | { 33 | HAL_ASSERT( this_timer != NULL_timer_instance ) 34 | HAL_ASSERT( prescale <= PRESCALER_DIV_1024 ) 35 | HAL_ASSERT( load_value != 0 ) 36 | 37 | this_timer->base_address = address; 38 | 39 | /* Disable interrupts. */ 40 | HAL_set_32bit_reg_field( address, InterruptEnable,0 ); 41 | 42 | /* Disable timer. */ 43 | HAL_set_32bit_reg_field( address, TimerEnable, 0 ); 44 | 45 | /* Clear pending interrupt. */ 46 | HAL_set_32bit_reg( address, TimerIntClr, 1 ); 47 | 48 | /* Configure prescaler and load value. */ 49 | HAL_set_32bit_reg( address, TimerPrescale, prescale ); 50 | HAL_set_32bit_reg( address, TimerLoad, load_value ); 51 | 52 | /* Set the interrupt mode. */ 53 | if ( mode == TMR_CONTINUOUS_MODE ) 54 | { 55 | HAL_set_32bit_reg_field( address, TimerMode, 0 ); 56 | } 57 | else 58 | { 59 | /* TMR_ONE_SHOT_MODE */ 60 | HAL_set_32bit_reg_field( address, TimerMode, 1 ); 61 | } 62 | } 63 | 64 | /***************************************************************************//** 65 | * TMR_start() 66 | * See "core_timer.h" for details of how to use this function. 67 | */ 68 | void 69 | TMR_start 70 | ( 71 | timer_instance_t * this_timer 72 | ) 73 | { 74 | HAL_ASSERT( this_timer != NULL_timer_instance ) 75 | 76 | HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 1 ); 77 | } 78 | 79 | /***************************************************************************//** 80 | * TMR_stop() 81 | * See "core_timer.h" for details of how to use this function. 82 | */ 83 | void 84 | TMR_stop 85 | ( 86 | timer_instance_t * this_timer 87 | ) 88 | { 89 | HAL_ASSERT( this_timer != NULL_timer_instance ) 90 | 91 | HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 0 ); 92 | } 93 | 94 | 95 | /***************************************************************************//** 96 | * TMR_enable_int() 97 | * See "core_timer.h" for details of how to use this function. 98 | */ 99 | void 100 | TMR_enable_int 101 | ( 102 | timer_instance_t * this_timer 103 | ) 104 | { 105 | HAL_ASSERT( this_timer != NULL_timer_instance ) 106 | 107 | HAL_set_32bit_reg_field( this_timer->base_address, InterruptEnable, 1 ); 108 | } 109 | 110 | /***************************************************************************//** 111 | * TMR_clear_int() 112 | * See "core_timer.h" for details of how to use this function. 113 | */ 114 | void 115 | TMR_clear_int 116 | ( 117 | timer_instance_t * this_timer 118 | ) 119 | { 120 | HAL_ASSERT( this_timer != NULL_timer_instance ) 121 | 122 | HAL_set_32bit_reg( this_timer->base_address, TimerIntClr, 0x01 ); 123 | } 124 | 125 | /***************************************************************************//** 126 | * TMR_current_value() 127 | * See "core_timer.h" for details of how to use this function. 128 | */ 129 | uint32_t 130 | TMR_current_value 131 | ( 132 | timer_instance_t * this_timer 133 | ) 134 | { 135 | uint32_t value = 0; 136 | HAL_ASSERT( this_timer != NULL_timer_instance ) 137 | 138 | value = HAL_get_32bit_reg( this_timer->base_address, TimerValue ); 139 | 140 | return value; 141 | } 142 | 143 | /***************************************************************************//** 144 | * TMR_reload() 145 | * See "core_timer.h" for details of how to use this function. 146 | */ 147 | void TMR_reload 148 | ( 149 | timer_instance_t * this_timer, 150 | uint32_t load_value 151 | ) 152 | { 153 | HAL_ASSERT( this_timer != NULL_timer_instance ) 154 | HAL_ASSERT( load_value != 0 ) 155 | 156 | HAL_set_32bit_reg(this_timer->base_address, TimerLoad, load_value ); 157 | } 158 | 159 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/main.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2017 Microsemi SoC Products Group. All rights reserved. 3 | * This SoftConsole example project demonstrates how to use the CoreTimer driver. 4 | * This example project also demonstrates how to configure PLIC to handle the 5 | * external interrupts. 6 | * 7 | * Please refer README.TXT in the root folder of this project for more details. 8 | */ 9 | #include "hw_platform.h" 10 | #include "riscv_hal.h" 11 | #include "hal.h" 12 | #include "core_gpio.h" 13 | #include "core_timer.h" 14 | #include "core_uart_apb.h" 15 | 16 | UART_instance_t g_uart; 17 | 18 | const char * g_hello_msg = 19 | "\r\n CoreTIMER and external Interrupt Example \r\n\r\n\ 20 | Observe the LEDs blinking on the board. The LED pattern changes \ 21 | every time a timer interrupt occurs\r\n"; 22 | 23 | /****************************************************************************** 24 | * GPIO instance data. 25 | *****************************************************************************/ 26 | 27 | gpio_instance_t g_gpio0; 28 | gpio_instance_t g_gpio1; 29 | 30 | /****************************************************************************** 31 | * CoreTimer instance data. 32 | *****************************************************************************/ 33 | 34 | timer_instance_t g_timer0; 35 | timer_instance_t g_timer1; 36 | 37 | /****************************************************************************** 38 | * Global state counter. 39 | *****************************************************************************/ 40 | 41 | uint32_t g_state; 42 | 43 | /*Core Timer 0 Interrupt Handler*/ 44 | uint8_t External_30_IRQHandler() 45 | { 46 | uint32_t stable; 47 | uint32_t gpout; 48 | 49 | stable = GPIO_get_inputs(&g_gpio0); 50 | gpout = ~stable & 0x000000F0; 51 | 52 | g_state = g_state << 1; 53 | if (g_state > 4) 54 | { 55 | g_state = 0x01; 56 | } 57 | 58 | gpout = gpout | g_state; 59 | GPIO_set_outputs(&g_gpio1, gpout); 60 | TMR_clear_int(&g_timer0); 61 | 62 | return(EXT_IRQ_KEEP_ENABLED); 63 | } 64 | 65 | /*Core Timer 1 Interrupt Handler*/ 66 | uint8_t External_31_IRQHandler() 67 | { 68 | g_state = g_state + 1; 69 | GPIO_set_outputs(&g_gpio1, g_state << 8); 70 | TMR_clear_int(&g_timer1); 71 | 72 | return(EXT_IRQ_KEEP_ENABLED); 73 | } 74 | 75 | int main(int argc, char **argv) 76 | { 77 | uint8_t rx_char; 78 | uint8_t rx_count; 79 | uint32_t switches; 80 | 81 | PLIC_init(); 82 | 83 | GPIO_init(&g_gpio0, COREGPIO_IN_BASE_ADDR, GPIO_APB_32_BITS_BUS); 84 | GPIO_init(&g_gpio1, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS); 85 | 86 | UART_init(&g_uart, 87 | COREUARTAPB0_BASE_ADDR, 88 | BAUD_VALUE_115200, 89 | (DATA_8_BITS | NO_PARITY)); 90 | 91 | UART_polled_tx_string(&g_uart, (const uint8_t *)g_hello_msg); 92 | 93 | /************************************************************************** 94 | * Set up CoreTimer 95 | *************************************************************************/ 96 | TMR_init(&g_timer0, 97 | CORETIMER0_BASE_ADDR, 98 | TMR_CONTINUOUS_MODE, 99 | PRESCALER_DIV_1024, 100 | 83000); 101 | 102 | TMR_init(&g_timer1, 103 | CORETIMER1_BASE_ADDR, 104 | TMR_CONTINUOUS_MODE, 105 | PRESCALER_DIV_512, 106 | 42000); 107 | 108 | /* In this version of the PLIC, the priorities are fixed at 1. 109 | Lower numbered devices have higher priorities. But this code is given as 110 | an example. 111 | */ 112 | PLIC_SetPriority(External_30_IRQn, 1); 113 | PLIC_SetPriority(External_31_IRQn, 1); 114 | 115 | /*Enable Timer 1 & 0 Interrupt*/ 116 | PLIC_EnableIRQ(External_30_IRQn); 117 | PLIC_EnableIRQ(External_31_IRQn); 118 | 119 | /* Enable the timers */ 120 | TMR_enable_int(&g_timer0); 121 | TMR_enable_int(&g_timer1); 122 | 123 | HAL_enable_interrupts(); 124 | 125 | g_state = 0x01; 126 | 127 | /*Start the timer*/ 128 | TMR_start(&g_timer0); 129 | TMR_start(&g_timer1); 130 | 131 | /************************************************************************** 132 | * Loop 133 | *************************************************************************/ 134 | do { 135 | switches = GPIO_get_inputs(&g_gpio0); 136 | rx_count = UART_get_rx(&g_uart, &rx_char, 1); 137 | 138 | if (rx_count > 0) 139 | { 140 | UART_send(&g_uart, &rx_char, 1); 141 | } 142 | GPIO_set_outputs(&g_gpio1, (~switches & 0x000000F0) | g_state); 143 | 144 | } while (1); 145 | 146 | return 0; 147 | } 148 | 149 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/riscv-simple-baremetal-bootloader Debug.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | -------------------------------------------------------------------------------- /Dhrystone/riscv_hal/sample_hw_platform.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi Corporation. All rights reserved. 3 | * 4 | * Platform definitions 5 | * Version based on requirements of RISCV-HAL 6 | * 7 | * SVN $Revision: 9661 $ 8 | * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $ 9 | */ 10 | /*=========================================================================*//** 11 | @mainpage Sample file detailing how hw_platform.h should be constructed for 12 | the Mi-V processors. 13 | 14 | @section intro_sec Introduction 15 | The hw_platform.h is to be located in the project root directory. 16 | Currently this file must be hand crafted when using the Mi-V Soft Processor. 17 | 18 | You can use this file as sample. 19 | Rename this file from sample_hw_platform.h to hw_platform.h and store it in 20 | the root folder of your project. Then customize it per your HW design. 21 | 22 | @section driver_configuration Project configuration Instructions 23 | 1. Change SYS_CLK_FREQ define to frequency of Mi-V Soft processor clock 24 | 2 Add all other core BASE addresses 25 | 3. Add peripheral Core Interrupt to Mi-V Soft processor interrupt mappings 26 | 4. Define MSCC_STDIO_UART_BASE_ADDR if you want a CoreUARTapb mapped to STDIO 27 | *//*=========================================================================*/ 28 | 29 | #ifndef HW_PLATFORM_H 30 | #define HW_PLATFORM_H 31 | 32 | /***************************************************************************//** 33 | * Soft-processor clock definition 34 | * This is the only clock brought over from the Mi-V Soft processor Libero design. 35 | */ 36 | #define SYS_CLK_FREQ 83000000UL 37 | 38 | /***************************************************************************//** 39 | * Non-memory Peripheral base addresses 40 | * Format of define is: 41 | * __BASE_ADDR 42 | */ 43 | #define COREUARTAPB0_BASE_ADDR 0x70001000UL 44 | #define COREGPIO_IN_BASE_ADDR 0x70002000UL 45 | #define CORETIMER0_BASE_ADDR 0x70003000UL 46 | #define CORETIMER1_BASE_ADDR 0x70004000UL 47 | #define COREGPIO_OUT_BASE_ADDR 0x70005000UL 48 | #define FLASH_CORE_SPI_BASE 0x70006000UL 49 | #define CORE16550_BASE_ADDR 0x70007000UL 50 | 51 | /***************************************************************************//** 52 | * Peripheral Interrupts are mapped to the corresponding Mi-V Soft processor 53 | * interrupt from the Libero design. 54 | * There can be up to 31 external interrupts (IRQ[30:0] pins) on the Mi-V Soft 55 | * processor.The Mi-V Soft processor external interrupts are defined in the 56 | * riscv_plic.h 57 | * These are of the form 58 | * typedef enum 59 | { 60 | NoInterrupt_IRQn = 0, 61 | External_1_IRQn = 1, 62 | External_2_IRQn = 2, 63 | . 64 | . 65 | . 66 | External_31_IRQn = 31 67 | } IRQn_Type; 68 | 69 | The interrupt 0 on RISC-V processor is not used. The pin IRQ[0] should map to 70 | External_1_IRQn likewise IRQ[30] should map to External_31_IRQn 71 | * Format of define is: 72 | * __ 73 | */ 74 | 75 | #define TIMER0_IRQn External_30_IRQn 76 | #define TIMER1_IRQn External_31_IRQn 77 | 78 | /**************************************************************************** 79 | * Baud value to achieve a 115200 baud rate with a 83MHz system clock. 80 | * This value is calculated using the following equation: 81 | * BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1 82 | *****************************************************************************/ 83 | #define BAUD_VALUE_115200 (SYS_CLK_FREQ / (16 * 115200)) - 1 84 | 85 | /***************************************************************************//** 86 | * User edit section- Edit sections below if required 87 | */ 88 | #ifdef MSCC_STDIO_THRU_CORE_UART_APB 89 | /* 90 | * A base address mapping for the STDIO printf/scanf mapping to CortUARTapb 91 | * must be provided if it is being used 92 | * 93 | * e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 94 | */ 95 | #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB0_BASE_ADDR 96 | 97 | #ifndef MSCC_STDIO_UART_BASE_ADDR 98 | #error MSCC_STDIO_UART_BASE_ADDR not defined- e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 99 | #endif 100 | 101 | #ifndef MSCC_STDIO_BAUD_VALUE 102 | /* 103 | * The MSCC_STDIO_BAUD_VALUE define should be set in your project's settings to 104 | * specify the baud value used by the standard output CoreUARTapb instance for 105 | * generating the UART's baud rate if you want a different baud rate from the 106 | * default of 115200 baud 107 | */ 108 | #define MSCC_STDIO_BAUD_VALUE 115200 109 | #endif /*MSCC_STDIO_BAUD_VALUE*/ 110 | 111 | #endif /* end of MSCC_STDIO_THRU_CORE_UART_APB */ 112 | /******************************************************************************* 113 | * End of user edit section 114 | */ 115 | #endif /* HW_PLATFORM_H */ 116 | 117 | 118 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/hw_platform.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2017 Microsemi Corporation. All rights reserved. 3 | * 4 | * Platform definitions 5 | * Version based on requirements of RISCV-HAL 6 | * 7 | * SVN $Revision: 9546 $ 8 | * SVN $Date: 2017-10-24 10:27:17 +0530 (Tue, 24 Oct 2017) $ 9 | */ 10 | /*=========================================================================*//** 11 | @mainpage Sample file detailing how hw_platform.h should be constructed for 12 | the Mi-V processors. 13 | 14 | @section intro_sec Introduction 15 | The hw_platform.h is to be located in the project root directory. 16 | Currently this file must be hand crafted when using the Mi-V Soft Processor. 17 | 18 | You can use this file as sample. 19 | Rename this file from sample_hw_platform.h to hw_platform.h and store it in 20 | the root folder of your project. Then customize it per your HW design. 21 | 22 | @section driver_configuration Project configuration Instructions 23 | 1. Change SYS_CLK_FREQ define to frequency of Mi-V Soft processor clock 24 | 2 Add all other core BASE addresses 25 | 3. Add peripheral Core Interrupt to Mi-V Soft processor interrupt mappings 26 | 4. Define MSCC_STDIO_UART_BASE_ADDR if you want a CoreUARTapb mapped to STDIO 27 | *//*=========================================================================*/ 28 | 29 | #ifndef HW_PLATFORM_H 30 | #define HW_PLATFORM_H 31 | 32 | /***************************************************************************//** 33 | * Soft-processor clock definition 34 | * This is the only clock brought over from the Mi-V Soft processor Libero design. 35 | */ 36 | #ifndef SYS_CLK_FREQ 37 | #define SYS_CLK_FREQ 66000000UL 38 | #endif 39 | /***************************************************************************//** 40 | * Non-memory Peripheral base addresses 41 | * Format of define is: 42 | * __BASE_ADDR 43 | */ 44 | #define COREUARTAPB0_BASE_ADDR 0x70001000UL 45 | #define COREGPIO_IN_BASE_ADDR 0x70002000UL 46 | #define CORETIMER0_BASE_ADDR 0x70003000UL 47 | #define CORETIMER1_BASE_ADDR 0x70004000UL 48 | #define COREGPIO_OUT_BASE_ADDR 0x70005000UL 49 | #define FLASH_CORE_SPI_BASE 0x70006000UL 50 | #define CORE16550_BASE_ADDR 0x70007000UL 51 | 52 | /***************************************************************************//** 53 | * Peripheral Interrupts are mapped to the corresponding Mi-V Soft processor 54 | * interrupt from the Libero design. 55 | * There can be up to 31 external interrupts (IRQ[30:0] pins) on the Mi-V Soft 56 | * processor.The Mi-V Soft processor external interrupts are defined in the 57 | * riscv_plic.h 58 | * These are of the form 59 | * typedef enum 60 | { 61 | NoInterrupt_IRQn = 0, 62 | External_1_IRQn = 1, 63 | External_2_IRQn = 2, 64 | . 65 | . 66 | . 67 | External_31_IRQn = 31 68 | } IRQn_Type; 69 | 70 | The interrupt 0 on RISC-V processor is not used. The pin IRQ[0] should map to 71 | External_1_IRQn likewise IRQ[30] should map to External_31_IRQn 72 | * Format of define is: 73 | * __ 74 | */ 75 | 76 | #define TIMER0_IRQn External_30_IRQn 77 | #define TIMER1_IRQn External_31_IRQn 78 | 79 | /**************************************************************************** 80 | * Baud value to achieve a 115200 baud rate with a 83MHz system clock. 81 | * This value is calculated using the following equation: 82 | * BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1 83 | *****************************************************************************/ 84 | #define BAUD_VALUE_115200 (SYS_CLK_FREQ / (16 * 115200)) - 1 85 | 86 | /***************************************************************************//** 87 | * User edit section- Edit sections below if required 88 | */ 89 | #ifdef MSCC_STDIO_THRU_CORE_UART_APB 90 | /* 91 | * A base address mapping for the STDIO printf/scanf mapping to CortUARTapb 92 | * must be provided if it is being used 93 | * 94 | * e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 95 | */ 96 | #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB0_BASE_ADDR 97 | 98 | #ifndef MSCC_STDIO_UART_BASE_ADDR 99 | #error MSCC_STDIO_UART_BASE_ADDR not defined- e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 100 | #endif 101 | 102 | #ifndef MSCC_STDIO_BAUD_VALUE 103 | /* 104 | * The MSCC_STDIO_BAUD_VALUE define should be set in your project's settings to 105 | * specify the baud value used by the standard output CoreUARTapb instance for 106 | * generating the UART's baud rate if you want a different baud rate from the 107 | * default of 115200 baud 108 | */ 109 | #define MSCC_STDIO_BAUD_VALUE 115200 110 | #endif /*MSCC_STDIO_BAUD_VALUE*/ 111 | 112 | #endif /* end of MSCC_STDIO_THRU_CORE_UART_APB */ 113 | /******************************************************************************* 114 | * End of user edit section 115 | */ 116 | #endif /* HW_PLATFORM_H */ 117 | 118 | 119 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/hw_platform.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2017 Microsemi Corporation. All rights reserved. 3 | * 4 | * Platform definitions 5 | * Version based on requirements of RISCV-HAL 6 | * 7 | * SVN $Revision: 9546 $ 8 | * SVN $Date: 2017-10-24 10:27:17 +0530 (Tue, 24 Oct 2017) $ 9 | */ 10 | /*=========================================================================*//** 11 | @mainpage Sample file detailing how hw_platform.h should be constructed for 12 | the Mi-V processors. 13 | 14 | @section intro_sec Introduction 15 | The hw_platform.h is to be located in the project root directory. 16 | Currently this file must be hand crafted when using the Mi-V Soft Processor. 17 | 18 | You can use this file as sample. 19 | Rename this file from sample_hw_platform.h to hw_platform.h and store it in 20 | the root folder of your project. Then customize it per your HW design. 21 | 22 | @section driver_configuration Project configuration Instructions 23 | 1. Change SYS_CLK_FREQ define to frequency of Mi-V Soft processor clock 24 | 2 Add all other core BASE addresses 25 | 3. Add peripheral Core Interrupt to Mi-V Soft processor interrupt mappings 26 | 4. Define MSCC_STDIO_UART_BASE_ADDR if you want a CoreUARTapb mapped to STDIO 27 | *//*=========================================================================*/ 28 | 29 | #ifndef HW_PLATFORM_H 30 | #define HW_PLATFORM_H 31 | 32 | /***************************************************************************//** 33 | * Soft-processor clock definition 34 | * This is the only clock brought over from the Mi-V Soft processor Libero design. 35 | */ 36 | #ifndef SYS_CLK_FREQ 37 | #define SYS_CLK_FREQ 50000000UL 38 | #endif 39 | /***************************************************************************//** 40 | * Non-memory Peripheral base addresses 41 | * Format of define is: 42 | * __BASE_ADDR 43 | */ 44 | #define COREUARTAPB0_BASE_ADDR 0x70001000UL 45 | #define COREGPIO_IN_BASE_ADDR 0x70002000UL 46 | #define CORETIMER0_BASE_ADDR 0x70003000UL 47 | #define CORETIMER1_BASE_ADDR 0x70004000UL 48 | #define COREGPIO_OUT_BASE_ADDR 0x70005000UL 49 | #define FLASH_CORE_SPI_BASE 0x70006000UL 50 | #define CORE16550_BASE_ADDR 0x70007000UL 51 | 52 | /***************************************************************************//** 53 | * Peripheral Interrupts are mapped to the corresponding Mi-V Soft processor 54 | * interrupt from the Libero design. 55 | * There can be up to 31 external interrupts (IRQ[30:0] pins) on the Mi-V Soft 56 | * processor.The Mi-V Soft processor external interrupts are defined in the 57 | * riscv_plic.h 58 | * These are of the form 59 | * typedef enum 60 | { 61 | NoInterrupt_IRQn = 0, 62 | External_1_IRQn = 1, 63 | External_2_IRQn = 2, 64 | . 65 | . 66 | . 67 | External_31_IRQn = 31 68 | } IRQn_Type; 69 | 70 | The interrupt 0 on RISC-V processor is not used. The pin IRQ[0] should map to 71 | External_1_IRQn likewise IRQ[30] should map to External_31_IRQn 72 | * Format of define is: 73 | * __ 74 | */ 75 | 76 | #define TIMER0_IRQn External_30_IRQn 77 | #define TIMER1_IRQn External_31_IRQn 78 | 79 | /**************************************************************************** 80 | * Baud value to achieve a 115200 baud rate with a 83MHz system clock. 81 | * This value is calculated using the following equation: 82 | * BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1 83 | *****************************************************************************/ 84 | #define BAUD_VALUE_115200 (SYS_CLK_FREQ / (16 * 115200)) - 1 85 | 86 | /***************************************************************************//** 87 | * User edit section- Edit sections below if required 88 | */ 89 | #ifdef MSCC_STDIO_THRU_CORE_UART_APB 90 | /* 91 | * A base address mapping for the STDIO printf/scanf mapping to CortUARTapb 92 | * must be provided if it is being used 93 | * 94 | * e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 95 | */ 96 | #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB0_BASE_ADDR 97 | 98 | #ifndef MSCC_STDIO_UART_BASE_ADDR 99 | #error MSCC_STDIO_UART_BASE_ADDR not defined- e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 100 | #endif 101 | 102 | #ifndef MSCC_STDIO_BAUD_VALUE 103 | /* 104 | * The MSCC_STDIO_BAUD_VALUE define should be set in your project's settings to 105 | * specify the baud value used by the standard output CoreUARTapb instance for 106 | * generating the UART's baud rate if you want a different baud rate from the 107 | * default of 115200 baud 108 | */ 109 | #define MSCC_STDIO_BAUD_VALUE 115200 110 | #endif /*MSCC_STDIO_BAUD_VALUE*/ 111 | 112 | #endif /* end of MSCC_STDIO_THRU_CORE_UART_APB */ 113 | /******************************************************************************* 114 | * End of user edit section 115 | */ 116 | #endif /* HW_PLATFORM_H */ 117 | 118 | 119 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/riscv_hal/sample_hw_platform.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi Corporation. All rights reserved. 3 | * 4 | * Platform definitions 5 | * Version based on requirements of RISCV-HAL 6 | * 7 | * SVN $Revision: 9946 $ 8 | * SVN $Date: 2018-04-30 20:26:55 +0530 (Mon, 30 Apr 2018) $ 9 | */ 10 | /*=========================================================================*//** 11 | @mainpage Sample file detailing how hw_platform.h should be constructed for 12 | the Mi-V processors. 13 | 14 | @section intro_sec Introduction 15 | The hw_platform.h is to be located in the project root directory. 16 | Currently this file must be hand crafted when using the Mi-V Soft Processor. 17 | 18 | You can use this file as sample. 19 | Rename this file from sample_hw_platform.h to hw_platform.h and store it in 20 | the root folder of your project. Then customize it per your HW design. 21 | 22 | @section driver_configuration Project configuration Instructions 23 | 1. Change SYS_CLK_FREQ define to frequency of Mi-V Soft processor clock 24 | 2 Add all other core BASE addresses 25 | 3. Add peripheral Core Interrupt to Mi-V Soft processor interrupt mappings 26 | 4. Define MSCC_STDIO_UART_BASE_ADDR if you want a CoreUARTapb mapped to STDIO 27 | *//*=========================================================================*/ 28 | 29 | #ifndef HW_PLATFORM_H 30 | #define HW_PLATFORM_H 31 | 32 | /***************************************************************************//** 33 | * Soft-processor clock definition 34 | * This is the only clock brought over from the Mi-V Soft processor Libero design. 35 | */ 36 | #ifndef SYS_CLK_FREQ 37 | #define SYS_CLK_FREQ 83000000UL 38 | #endif 39 | 40 | 41 | /***************************************************************************//** 42 | * Non-memory Peripheral base addresses 43 | * Format of define is: 44 | * __BASE_ADDR 45 | */ 46 | #define COREUARTAPB0_BASE_ADDR 0x70001000UL 47 | #define COREGPIO_IN_BASE_ADDR 0x70002000UL 48 | #define CORETIMER0_BASE_ADDR 0x70003000UL 49 | #define CORETIMER1_BASE_ADDR 0x70004000UL 50 | #define COREGPIO_OUT_BASE_ADDR 0x70005000UL 51 | #define FLASH_CORE_SPI_BASE 0x70006000UL 52 | #define CORE16550_BASE_ADDR 0x70007000UL 53 | 54 | /***************************************************************************//** 55 | * Peripheral Interrupts are mapped to the corresponding Mi-V Soft processor 56 | * interrupt from the Libero design. 57 | * There can be up to 31 external interrupts (IRQ[30:0] pins) on the Mi-V Soft 58 | * processor.The Mi-V Soft processor external interrupts are defined in the 59 | * riscv_plic.h 60 | * These are of the form 61 | * typedef enum 62 | { 63 | NoInterrupt_IRQn = 0, 64 | External_1_IRQn = 1, 65 | External_2_IRQn = 2, 66 | . 67 | . 68 | . 69 | External_31_IRQn = 31 70 | } IRQn_Type; 71 | 72 | The interrupt 0 on RISC-V processor is not used. The pin IRQ[0] should map to 73 | External_1_IRQn likewise IRQ[30] should map to External_31_IRQn 74 | * Format of define is: 75 | * __ 76 | */ 77 | 78 | #define TIMER0_IRQn External_30_IRQn 79 | #define TIMER1_IRQn External_31_IRQn 80 | 81 | /**************************************************************************** 82 | * Baud value to achieve a 115200 baud rate with a 83MHz system clock. 83 | * This value is calculated using the following equation: 84 | * BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1 85 | *****************************************************************************/ 86 | #define BAUD_VALUE_115200 (SYS_CLK_FREQ / (16 * 115200)) - 1 87 | 88 | /***************************************************************************//** 89 | * User edit section- Edit sections below if required 90 | */ 91 | #ifdef MSCC_STDIO_THRU_CORE_UART_APB 92 | /* 93 | * A base address mapping for the STDIO printf/scanf mapping to CortUARTapb 94 | * must be provided if it is being used 95 | * 96 | * e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 97 | */ 98 | #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB0_BASE_ADDR 99 | 100 | #ifndef MSCC_STDIO_UART_BASE_ADDR 101 | #error MSCC_STDIO_UART_BASE_ADDR not defined- e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 102 | #endif 103 | 104 | #ifndef MSCC_STDIO_BAUD_VALUE 105 | /* 106 | * The MSCC_STDIO_BAUD_VALUE define should be set in your project's settings to 107 | * specify the baud value used by the standard output CoreUARTapb instance for 108 | * generating the UART's baud rate if you want a different baud rate from the 109 | * default of 115200 baud 110 | */ 111 | #define MSCC_STDIO_BAUD_VALUE 115200 112 | #endif /*MSCC_STDIO_BAUD_VALUE*/ 113 | 114 | #endif /* end of MSCC_STDIO_THRU_CORE_UART_APB */ 115 | /******************************************************************************* 116 | * End of user edit section 117 | */ 118 | #endif /* HW_PLATFORM_H */ 119 | 120 | 121 | -------------------------------------------------------------------------------- /miv-rv32im-interrupt-blinky/riscv_hal/sample_hw_platform.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi Corporation. All rights reserved. 3 | * 4 | * Platform definitions 5 | * Version based on requirements of RISCV-HAL 6 | * 7 | * SVN $Revision: 9946 $ 8 | * SVN $Date: 2018-04-30 20:26:55 +0530 (Mon, 30 Apr 2018) $ 9 | */ 10 | /*=========================================================================*//** 11 | @mainpage Sample file detailing how hw_platform.h should be constructed for 12 | the Mi-V processors. 13 | 14 | @section intro_sec Introduction 15 | The hw_platform.h is to be located in the project root directory. 16 | Currently this file must be hand crafted when using the Mi-V Soft Processor. 17 | 18 | You can use this file as sample. 19 | Rename this file from sample_hw_platform.h to hw_platform.h and store it in 20 | the root folder of your project. Then customize it per your HW design. 21 | 22 | @section driver_configuration Project configuration Instructions 23 | 1. Change SYS_CLK_FREQ define to frequency of Mi-V Soft processor clock 24 | 2 Add all other core BASE addresses 25 | 3. Add peripheral Core Interrupt to Mi-V Soft processor interrupt mappings 26 | 4. Define MSCC_STDIO_UART_BASE_ADDR if you want a CoreUARTapb mapped to STDIO 27 | *//*=========================================================================*/ 28 | 29 | #ifndef HW_PLATFORM_H 30 | #define HW_PLATFORM_H 31 | 32 | /***************************************************************************//** 33 | * Soft-processor clock definition 34 | * This is the only clock brought over from the Mi-V Soft processor Libero design. 35 | */ 36 | #ifndef SYS_CLK_FREQ 37 | #define SYS_CLK_FREQ 83000000UL 38 | #endif 39 | 40 | 41 | /***************************************************************************//** 42 | * Non-memory Peripheral base addresses 43 | * Format of define is: 44 | * __BASE_ADDR 45 | */ 46 | #define COREUARTAPB0_BASE_ADDR 0x70001000UL 47 | #define COREGPIO_IN_BASE_ADDR 0x70002000UL 48 | #define CORETIMER0_BASE_ADDR 0x70003000UL 49 | #define CORETIMER1_BASE_ADDR 0x70004000UL 50 | #define COREGPIO_OUT_BASE_ADDR 0x70005000UL 51 | #define FLASH_CORE_SPI_BASE 0x70006000UL 52 | #define CORE16550_BASE_ADDR 0x70007000UL 53 | 54 | /***************************************************************************//** 55 | * Peripheral Interrupts are mapped to the corresponding Mi-V Soft processor 56 | * interrupt from the Libero design. 57 | * There can be up to 31 external interrupts (IRQ[30:0] pins) on the Mi-V Soft 58 | * processor.The Mi-V Soft processor external interrupts are defined in the 59 | * riscv_plic.h 60 | * These are of the form 61 | * typedef enum 62 | { 63 | NoInterrupt_IRQn = 0, 64 | External_1_IRQn = 1, 65 | External_2_IRQn = 2, 66 | . 67 | . 68 | . 69 | External_31_IRQn = 31 70 | } IRQn_Type; 71 | 72 | The interrupt 0 on RISC-V processor is not used. The pin IRQ[0] should map to 73 | External_1_IRQn likewise IRQ[30] should map to External_31_IRQn 74 | * Format of define is: 75 | * __ 76 | */ 77 | 78 | #define TIMER0_IRQn External_30_IRQn 79 | #define TIMER1_IRQn External_31_IRQn 80 | 81 | /**************************************************************************** 82 | * Baud value to achieve a 115200 baud rate with a 83MHz system clock. 83 | * This value is calculated using the following equation: 84 | * BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1 85 | *****************************************************************************/ 86 | #define BAUD_VALUE_115200 (SYS_CLK_FREQ / (16 * 115200)) - 1 87 | 88 | /***************************************************************************//** 89 | * User edit section- Edit sections below if required 90 | */ 91 | #ifdef MSCC_STDIO_THRU_CORE_UART_APB 92 | /* 93 | * A base address mapping for the STDIO printf/scanf mapping to CortUARTapb 94 | * must be provided if it is being used 95 | * 96 | * e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 97 | */ 98 | #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB0_BASE_ADDR 99 | 100 | #ifndef MSCC_STDIO_UART_BASE_ADDR 101 | #error MSCC_STDIO_UART_BASE_ADDR not defined- e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 102 | #endif 103 | 104 | #ifndef MSCC_STDIO_BAUD_VALUE 105 | /* 106 | * The MSCC_STDIO_BAUD_VALUE define should be set in your project's settings to 107 | * specify the baud value used by the standard output CoreUARTapb instance for 108 | * generating the UART's baud rate if you want a different baud rate from the 109 | * default of 115200 baud 110 | */ 111 | #define MSCC_STDIO_BAUD_VALUE 115200 112 | #endif /*MSCC_STDIO_BAUD_VALUE*/ 113 | 114 | #endif /* end of MSCC_STDIO_THRU_CORE_UART_APB */ 115 | /******************************************************************************* 116 | * End of user edit section 117 | */ 118 | #endif /* HW_PLATFORM_H */ 119 | 120 | 121 | -------------------------------------------------------------------------------- /riscv-simple-baremetal-bootloader/riscv_hal/sample_hw_platform.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 2016-2018 Microsemi Corporation. All rights reserved. 3 | * 4 | * Platform definitions 5 | * Version based on requirements of RISCV-HAL 6 | * 7 | * SVN $Revision: 9946 $ 8 | * SVN $Date: 2018-04-30 20:26:55 +0530 (Mon, 30 Apr 2018) $ 9 | */ 10 | /*=========================================================================*//** 11 | @mainpage Sample file detailing how hw_platform.h should be constructed for 12 | the Mi-V processors. 13 | 14 | @section intro_sec Introduction 15 | The hw_platform.h is to be located in the project root directory. 16 | Currently this file must be hand crafted when using the Mi-V Soft Processor. 17 | 18 | You can use this file as sample. 19 | Rename this file from sample_hw_platform.h to hw_platform.h and store it in 20 | the root folder of your project. Then customize it per your HW design. 21 | 22 | @section driver_configuration Project configuration Instructions 23 | 1. Change SYS_CLK_FREQ define to frequency of Mi-V Soft processor clock 24 | 2 Add all other core BASE addresses 25 | 3. Add peripheral Core Interrupt to Mi-V Soft processor interrupt mappings 26 | 4. Define MSCC_STDIO_UART_BASE_ADDR if you want a CoreUARTapb mapped to STDIO 27 | *//*=========================================================================*/ 28 | 29 | #ifndef HW_PLATFORM_H 30 | #define HW_PLATFORM_H 31 | 32 | /***************************************************************************//** 33 | * Soft-processor clock definition 34 | * This is the only clock brought over from the Mi-V Soft processor Libero design. 35 | */ 36 | #ifndef SYS_CLK_FREQ 37 | #define SYS_CLK_FREQ 83000000UL 38 | #endif 39 | 40 | 41 | /***************************************************************************//** 42 | * Non-memory Peripheral base addresses 43 | * Format of define is: 44 | * __BASE_ADDR 45 | */ 46 | #define COREUARTAPB0_BASE_ADDR 0x70001000UL 47 | #define COREGPIO_IN_BASE_ADDR 0x70002000UL 48 | #define CORETIMER0_BASE_ADDR 0x70003000UL 49 | #define CORETIMER1_BASE_ADDR 0x70004000UL 50 | #define COREGPIO_OUT_BASE_ADDR 0x70005000UL 51 | #define FLASH_CORE_SPI_BASE 0x70006000UL 52 | #define CORE16550_BASE_ADDR 0x70007000UL 53 | 54 | /***************************************************************************//** 55 | * Peripheral Interrupts are mapped to the corresponding Mi-V Soft processor 56 | * interrupt from the Libero design. 57 | * There can be up to 31 external interrupts (IRQ[30:0] pins) on the Mi-V Soft 58 | * processor.The Mi-V Soft processor external interrupts are defined in the 59 | * riscv_plic.h 60 | * These are of the form 61 | * typedef enum 62 | { 63 | NoInterrupt_IRQn = 0, 64 | External_1_IRQn = 1, 65 | External_2_IRQn = 2, 66 | . 67 | . 68 | . 69 | External_31_IRQn = 31 70 | } IRQn_Type; 71 | 72 | The interrupt 0 on RISC-V processor is not used. The pin IRQ[0] should map to 73 | External_1_IRQn likewise IRQ[30] should map to External_31_IRQn 74 | * Format of define is: 75 | * __ 76 | */ 77 | 78 | #define TIMER0_IRQn External_30_IRQn 79 | #define TIMER1_IRQn External_31_IRQn 80 | 81 | /**************************************************************************** 82 | * Baud value to achieve a 115200 baud rate with a 83MHz system clock. 83 | * This value is calculated using the following equation: 84 | * BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1 85 | *****************************************************************************/ 86 | #define BAUD_VALUE_115200 (SYS_CLK_FREQ / (16 * 115200)) - 1 87 | 88 | /***************************************************************************//** 89 | * User edit section- Edit sections below if required 90 | */ 91 | #ifdef MSCC_STDIO_THRU_CORE_UART_APB 92 | /* 93 | * A base address mapping for the STDIO printf/scanf mapping to CortUARTapb 94 | * must be provided if it is being used 95 | * 96 | * e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 97 | */ 98 | #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB0_BASE_ADDR 99 | 100 | #ifndef MSCC_STDIO_UART_BASE_ADDR 101 | #error MSCC_STDIO_UART_BASE_ADDR not defined- e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR 102 | #endif 103 | 104 | #ifndef MSCC_STDIO_BAUD_VALUE 105 | /* 106 | * The MSCC_STDIO_BAUD_VALUE define should be set in your project's settings to 107 | * specify the baud value used by the standard output CoreUARTapb instance for 108 | * generating the UART's baud rate if you want a different baud rate from the 109 | * default of 115200 baud 110 | */ 111 | #define MSCC_STDIO_BAUD_VALUE 115200 112 | #endif /*MSCC_STDIO_BAUD_VALUE*/ 113 | 114 | #endif /* end of MSCC_STDIO_THRU_CORE_UART_APB */ 115 | /******************************************************************************* 116 | * End of user edit section 117 | */ 118 | #endif /* HW_PLATFORM_H */ 119 | 120 | 121 | -------------------------------------------------------------------------------- /miv-rv32im-systick-blinky/miv-rv32im-systick-blinky Debug.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | --------------------------------------------------------------------------------