├── LICENSE ├── README.md ├── doc ├── Red-Hat-blogs-on-Virtio.md ├── bm-hive.png ├── custom-protocol-vhost.png ├── fpga-bridging.png ├── qemu-hdl-cosim.png ├── soc-option.png ├── virio-fpga-bridge.odp └── virtio-without-the-virt-2019-final.pdf ├── hw ├── prj │ └── qemu_hdl_cosim │ │ ├── Makefile │ │ ├── README.md │ │ ├── add_cosim_ip_path.tcl │ │ ├── cleanup.sh │ │ ├── cosim_dpi.sh │ │ ├── cosim_proj.tcl │ │ ├── create_proj.tcl │ │ ├── edt_proj.tcl │ │ └── gen_dpi_2nd.sh └── src │ ├── hdl │ └── virtio_csr.v │ ├── ipi │ ├── cosim_default.bd.tcl │ └── cosim_setup_flow.tcl │ └── qemu_hdl_cosim │ ├── axi_vip │ ├── axi_vip_0_passthrough_mst_stimulus.sv │ ├── axi_vip_1_passthrough_mst_stimulus.sv │ ├── csrinit_trace.txt │ ├── dma_transaction.vh │ └── dma_transaction_for_queue_notify.v │ ├── sim_ip │ └── QEMUPCIeBridge │ │ ├── Makefile │ │ ├── component.xml │ │ ├── hdl │ │ ├── acc.h │ │ ├── axi4_ip_mod.sv │ │ ├── axi4_m_r.sv │ │ ├── axi4_m_w.sv │ │ ├── axi4_s_i.sv │ │ ├── axi4_s_r.sv │ │ ├── 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