├── .github ├── dependabot.yml └── workflows │ └── ci.yml ├── .gitignore ├── CHANGELOG.md ├── Cargo.toml ├── LICENSE-APACHE ├── LICENSE-MIT ├── README.md ├── build.rs ├── examples └── atmega328p │ ├── .cargo │ └── config.toml │ ├── .gitignore │ ├── Cargo.toml │ ├── README.md │ ├── rust-toolchain.toml │ └── src │ └── main.rs ├── macros ├── Cargo.toml └── src │ └── lib.rs ├── patch ├── at90can128.yaml ├── at90can32.yaml ├── at90can64.yaml ├── at90usb1286.yaml ├── atmega1280.yaml ├── atmega1284p.yaml ├── atmega128a.yaml ├── atmega128rfa1.yaml ├── atmega16.yaml ├── atmega164pa.yaml ├── atmega168.yaml ├── atmega16u2.yaml ├── atmega2560.yaml ├── atmega3208.yaml ├── atmega3209.yaml ├── atmega324pa.yaml ├── atmega328p.yaml ├── atmega328pb.yaml ├── atmega32a.yaml ├── atmega32u2.yaml ├── atmega32u4.yaml ├── atmega4808.yaml ├── atmega4809.yaml ├── atmega48p.yaml ├── atmega64.yaml ├── atmega644.yaml ├── atmega8.yaml ├── atmega88p.yaml ├── atmega8u2.yaml ├── attiny13a.yaml ├── attiny1604.yaml ├── attiny1626.yaml ├── attiny167.yaml ├── attiny202.yaml ├── attiny204.yaml ├── attiny212.yaml ├── attiny214.yaml ├── attiny2313-common.yaml ├── attiny2313.yaml ├── attiny2313a.yaml ├── attiny26.yaml ├── attiny261a.yaml ├── attiny402.yaml ├── attiny404.yaml ├── attiny412.yaml ├── attiny414.yaml ├── attiny416.yaml ├── attiny461a.yaml ├── attiny804.yaml ├── attiny816.yaml ├── attiny828.yaml ├── attiny84.yaml ├── attiny841.yaml ├── attiny84a.yaml ├── attiny85.yaml ├── attiny861.yaml ├── attiny861a.yaml ├── attiny88.yaml ├── common │ ├── ac.yaml │ ├── adc.yaml │ ├── at90 │ │ ├── adc.yaml │ │ ├── spi.yaml │ │ └── usart.yaml │ ├── attiny-1-series.yaml │ ├── attiny-xmega │ │ ├── 0-series.yaml │ │ ├── 1-series.yaml │ │ ├── 2-series.yaml │ │ └── common.yaml │ ├── eeprom.yaml │ ├── mega0 │ │ └── port.yaml │ ├── pll.yaml │ ├── spi.yaml │ ├── tiny │ │ ├── attinyx61a-adc.yaml │ │ ├── attinyx61a-ports.yaml │ │ ├── attinyx61a-timers.yaml │ │ ├── exint.yaml │ │ └── usi.yaml │ ├── twi.yaml │ ├── usart-single-attiny2313.yaml │ ├── usart-single-attiny2313a.yaml │ ├── usart.yaml │ └── wdt.yaml └── timer │ ├── atmega1280-2560.yaml │ ├── atmega1284p.yaml │ ├── atmega128a.yaml │ ├── atmega128rfa1.yaml │ ├── atmega16.yaml │ ├── atmega2560.yaml │ ├── atmega324pa.yaml │ ├── atmega328p.yaml │ ├── atmega328pb.yaml │ ├── atmega32u4.yaml │ ├── atmega8.yaml │ ├── atmega8u2.yaml │ ├── attiny13a.yaml │ ├── attiny167.yaml │ ├── attiny2313-common.yaml │ ├── attiny828.yaml │ ├── attiny84.yaml │ ├── attiny841.yaml │ ├── attiny85.yaml │ ├── attiny861.yaml │ ├── attiny88.yaml │ └── dev │ ├── 10bit.yaml │ ├── 16bit-mega8.yaml │ ├── 16bit-tiny861-tc0.yaml │ ├── 16bit.yaml │ ├── 8bit-async-mega8.yaml │ ├── 8bit-async.yaml │ ├── 8bit-mega8.yaml │ ├── 8bit-tiny167.yaml │ ├── 8bit-tiny85-tc1.yaml │ ├── 8bit-tiny88.yaml │ ├── 8bit-tiny8n-tc0.yaml │ └── 8bit.yaml ├── src ├── asm.rs ├── devices.rs ├── interrupt.rs └── lib.rs └── vendor ├── LICENSE ├── README.md ├── at90can128.atdf ├── at90can32.atdf ├── at90can64.atdf ├── at90usb1286.atdf ├── atmega1280.atdf ├── atmega1284p.atdf ├── atmega128a.atdf ├── atmega128rfa1.atdf ├── atmega16.atdf ├── atmega164pa.atdf ├── atmega168.atdf ├── atmega16u2.atdf ├── atmega2560.atdf ├── atmega3208.atdf ├── atmega3209.atdf ├── atmega324pa.atdf ├── atmega328p.atdf ├── atmega328pb.atdf ├── atmega32a.atdf ├── atmega32u2.atdf ├── atmega32u4.atdf ├── atmega4808.atdf ├── atmega4809.atdf ├── atmega48p.atdf ├── atmega64.atdf ├── atmega644.atdf ├── atmega8.atdf ├── atmega88p.atdf ├── atmega8u2.atdf ├── attiny13a.atdf ├── attiny1604.atdf ├── attiny1606.atdf ├── attiny1614.atdf ├── attiny1626.atdf ├── attiny167.atdf ├── attiny202.atdf ├── attiny204.atdf ├── attiny212.atdf ├── attiny214.atdf ├── attiny2313.atdf ├── attiny2313a.atdf ├── attiny26.atdf ├── attiny261a.atdf ├── attiny402.atdf ├── attiny404.atdf ├── attiny412.atdf ├── attiny414.atdf ├── attiny416.atdf ├── attiny44a.atdf ├── attiny461a.atdf ├── attiny804.atdf ├── attiny816.atdf ├── attiny828.atdf ├── attiny84.atdf ├── attiny841.atdf ├── attiny84a.atdf ├── attiny85.atdf ├── attiny861.atdf ├── attiny861a.atdf ├── attiny88.atdf ├── avr128db28.atdf ├── avr64du28.atdf └── avr64du32.atdf /.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | updates: 3 | - package-ecosystem: "github-actions" 4 | directory: "/" 5 | schedule: 6 | interval: "weekly" 7 | - package-ecosystem: "cargo" 8 | directory: "/" 9 | schedule: 10 | interval: "weekly" 11 | -------------------------------------------------------------------------------- /.github/workflows/ci.yml: -------------------------------------------------------------------------------- 1 | name: Continuous Integration 2 | 3 | on: 4 | push: 5 | branches: 6 | - main 7 | - wip 8 | pull_request: 9 | 10 | jobs: 11 | ci: 12 | name: "Test-build avr-device with all targets and runtime enabled" 13 | runs-on: ubuntu-latest 14 | steps: 15 | - name: Checkout code 16 | uses: actions/checkout@v4 17 | 18 | # Rust Dependencies 19 | - name: Install Stable Rust 20 | uses: actions-rust-lang/setup-rust-toolchain@v1 21 | with: 22 | toolchain: stable 23 | - name: Install Nightly Rust 24 | uses: actions-rust-lang/setup-rust-toolchain@v1 25 | with: 26 | toolchain: nightly-2025-04-27 27 | components: rustfmt,rust-src 28 | 29 | # Actual test run 30 | - name: Test-compile the crate 31 | run: cargo check --target avr-none --all-features -Zbuild-std=core 32 | env: 33 | RUSTFLAGS: "-C target-cpu=atmega328p" 34 | 35 | # Package artifacts 36 | - name: Generate a cargo package for the macros 37 | run: cd macros/; cargo package --target avr-none --no-verify --allow-dirty 38 | env: 39 | RUSTFLAGS: "-C target-cpu=atmega328p" 40 | - name: Generate a cargo package for avr-device 41 | run: cargo package --target avr-none --no-verify --allow-dirty 42 | env: 43 | RUSTFLAGS: "-C target-cpu=atmega328p" 44 | 45 | # Upload artifacts 46 | - uses: actions/upload-artifact@v4 47 | with: 48 | name: avr-device 49 | path: | 50 | target/avr-none/debug/build/avr-device-*/out/svd/ 51 | target/package/avr-device-*.crate 52 | macros/target/package/avr-device-macros-*.crate 53 | 54 | ci-example: 55 | name: "Test-build ATmega328P example" 56 | runs-on: ubuntu-latest 57 | steps: 58 | - name: Checkout code 59 | uses: actions/checkout@v4 60 | - name: Install Rust 61 | uses: actions-rust-lang/setup-rust-toolchain@v1 62 | with: 63 | toolchain: nightly-2025-04-27 64 | rustflags: "" 65 | components: rust-src,rustfmt 66 | - name: Install AVR gcc, binutils, and libc 67 | run: sudo apt-get install -y avr-libc binutils-avr gcc-avr 68 | - name: Build ATmega328P example 69 | run: cd examples/atmega328p && cargo build 70 | - name: Check ATmega328P formatting 71 | run: cd examples/atmega328p && cargo fmt --check 72 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /target/ 2 | /macros/target/ 3 | **/*.rs.bk 4 | Cargo.lock 5 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "avr-device" 3 | version = "0.7.0" 4 | 5 | authors = ["Rahix "] 6 | edition = "2021" 7 | description = "Register access crate for AVR microcontrollers" 8 | license = "MIT OR Apache-2.0" 9 | repository = "https://github.com/Rahix/avr-device" 10 | readme = "README.md" 11 | keywords = ["avr", "arduino"] 12 | categories = ["no-std", "embedded", "hardware-support"] 13 | 14 | include = [ 15 | "/src/**/*.rs", 16 | "/LICENSE-*", 17 | "/README.md", 18 | "/build.rs", 19 | "/patch/**/*.yaml", 20 | "/vendor/*.atdf", 21 | "/vendor/LICENSE", 22 | "/examples/**/src/*.rs" 23 | ] 24 | 25 | [package.metadata.docs.rs] 26 | features = ["docsrs"] 27 | 28 | [features] 29 | device-selected = [] 30 | at90can128 = ["device-selected"] 31 | at90can64 = ["device-selected"] 32 | at90can32 = ["device-selected"] 33 | at90usb1286 = ["device-selected"] 34 | atmega1280 = ["device-selected"] 35 | atmega1284p = ["device-selected"] 36 | atmega128a = ["device-selected"] 37 | atmega128rfa1 = ["device-selected"] 38 | atmega16 = ["device-selected"] 39 | atmega16u2 = ["device-selected"] 40 | atmega164pa = ["device-selected"] 41 | atmega168 = ["device-selected"] 42 | atmega2560 = ["device-selected"] 43 | atmega8 = ["device-selected"] 44 | atmega8u2 = ["device-selected"] 45 | atmega324pa = ["device-selected"] 46 | atmega328p = ["device-selected"] 47 | atmega328pb = ["device-selected"] 48 | atmega3208 = ["device-selected"] 49 | atmega3209 = ["device-selected"] 50 | atmega4808 = ["device-selected"] 51 | atmega4809 = ["device-selected"] 52 | atmega48p = ["device-selected"] 53 | atmega32a = ["device-selected"] 54 | atmega32u2 = ["device-selected"] 55 | atmega32u4 = ["device-selected"] 56 | atmega64 = ["device-selected"] 57 | atmega644 = ["device-selected"] 58 | atmega88p = ["device-selected"] 59 | attiny13a = ["device-selected"] 60 | attiny167 = ["device-selected"] 61 | attiny202 = ["device-selected"] 62 | attiny212 = ["device-selected"] 63 | attiny204 = ["device-selected"] 64 | attiny214 = ["device-selected"] 65 | attiny2313 = ["device-selected"] 66 | attiny2313a = ["device-selected"] 67 | attiny26 = ["device-selected"] 68 | attiny261a = ["device-selected"] 69 | attiny402 = ["device-selected"] 70 | attiny404 = ["device-selected"] 71 | attiny412 = ["device-selected"] 72 | attiny414 = ["device-selected"] 73 | attiny416 = ["device-selected"] 74 | attiny44a = ["device-selected"] 75 | attiny461a = ["device-selected"] 76 | attiny804 = ["device-selected"] 77 | attiny816 = ["device-selected"] 78 | attiny828 = ["device-selected"] 79 | attiny84 = ["device-selected"] 80 | attiny841 = ["device-selected"] 81 | attiny84a = ["device-selected"] 82 | attiny85 = ["device-selected"] 83 | attiny861 = ["device-selected"] 84 | attiny861a = ["device-selected"] 85 | attiny88 = ["device-selected"] 86 | attiny1604 = ["device-selected"] 87 | attiny1606 = ["device-selected"] 88 | attiny1614 = ["device-selected"] 89 | attiny1626 = ["device-selected"] 90 | avr64du32 = ["device-selected"] 91 | avr64du28 = ["device-selected"] 92 | avr128db28 = ["device-selected"] 93 | rt = ["avr-device-macros"] 94 | 95 | critical-section = ["critical-section/restore-state-u8"] 96 | 97 | default = ["critical-section"] 98 | 99 | # Unfortunately, we can only build documentation for a subset of the supported 100 | # MCUs on docs.rs. If you think a very popular chip is missing from the list, 101 | # feel free to add it here. 102 | docsrs = ["rt", "ufmt", "atmega328p", "atmega32u4", "atmega2560", "attiny85", "atmega4809"] 103 | 104 | [dependencies] 105 | bare-metal = "1.0.0" 106 | vcell = "0.1.3" 107 | cfg-if = "1.0.0" 108 | ufmt = { version = "0.2.0", optional = true } 109 | critical-section = { version = "1.2.0", optional = true } 110 | 111 | [dependencies.avr-device-macros] 112 | path = "macros/" 113 | version = "=0.7.0" 114 | optional = true 115 | 116 | [build-dependencies] 117 | svd2rust = { version = "=0.36.1", default-features = false } 118 | svdtools = { version = "=0.5.0", default-features = false } 119 | atdf2svd = { version = "=0.5.1", default-features = false } 120 | prettyplease = "=0.2.33" 121 | svd-rs = { version = "=0.14.12", default-features = false } 122 | yaml-rust2 = { version = "=0.10.2", default-features = false } 123 | syn = { version = "=2.0.101", default-features = false, features = ["full", "parsing"] } 124 | anyhow = "1.0" 125 | -------------------------------------------------------------------------------- /LICENSE-APACHE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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IN NO EVENT 19 | SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 20 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 21 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR 22 | IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 | DEALINGS IN THE SOFTWARE. 24 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | avr-device [![crates.io page](https://img.shields.io/crates/v/avr-device.svg)](https://crates.io/crates/avr-device) [![docs.rs](https://docs.rs/avr-device/badge.svg)](https://docs.rs/avr-device) ![Continuous Integration](https://github.com/Rahix/avr-device/workflows/Continuous%20Integration/badge.svg) 2 | ========== 3 | Auto-generated wrappers around registers for AVR microcontrollers. 4 | 5 | ## Usage 6 | Add the following to `Cargo.toml`: 7 | ```toml 8 | [dependencies.avr-device] 9 | version = "0.7.0" 10 | features = ["atmega32u4"] 11 | ``` 12 | 13 | With the feature you can select which chip you want the register definitions 14 | for. For a full list of supported AVR chips, please check 15 | [`Cargo.toml`](https://github.com/rahix/avr-device/blob/main/Cargo.toml#L30). 16 | 17 | ## Build Instructions 18 | The PACs (Peripheral Access Crates, or really modules, in our case) **are not** 19 | checked into git. Rather, we generate them at build time, via an automated 20 | process implemented in [`build.rs`](./build.rs). It takes the ATDF files 21 | Microchip (former Atmel) provides plus some patches of our own making as inputs, 22 | and outputs a module generated from those device descriptions. These inputs 23 | **are** checked-in. The process is similar to what the `*bindgen` crates 24 | provide, just has more steps. So, in short, building should be a matter of 25 | selecting the features and running cargo. 26 | 27 | ### Adding a new Chip 28 | To add a new chip: 29 | 30 | 1. Download the ATDF from and place it in 31 | `vendor/`. Be sure to name it like the Rust module that should be generated. 32 | 2. Add a feature of the same name to `Cargo.toml` (it should enable 33 | `device-selected`); 34 | 3. Add any needed patches to a yaml file with the same name under the `patch` 35 | directory, ideally by including some of the snippets present in 36 | `patch/common` and `patch/timer`; The format is decribed 37 | [here](https://github.com/rust-embedded/svdtools#device-and-peripheral-yaml-format), 38 | but it should not include the top-level `_svd` key, as that's handled by the 39 | build system; If patching is unneeded (it's almost always needed!), the file 40 | can be omitted. 41 | 4. Include the module into the tree, in [`devices.rs`](./src/devices.rs), 42 | following the format used by other modules in that file; 43 | 5. Update [`lib.rs`](./src/lib.rs) to conditionally `use` the new MCU module, 44 | and add it to the lists of selected and available MCUs in the doc comment. 45 | 6. Finally, try building the crate for your MCU with 46 | `cargo build --features ,rt`. 47 | 7. Also check the built documentation for inconsistencies, via 48 | `cargo doc --features ,rt --open` (it will pop up in your browser). 49 | 8. Update this README.md, adding the MCU to the table. 50 | 51 | ## Internals 52 | Since the vendor does not provide SVDs we can pass to [`svd2rust`][], we 53 | generate one via [`atdf2svd`][]. The sequence is as follows: 54 | 55 | 1. Check which MCUs are known to the crate 56 | ([build.rs:get_available_mcus](./build.rs)); 57 | 2. Select which to build for by checking enabled features 58 | ([build.rs:select_mcu](./build.rs)); 59 | 3. Generate the Rust module ([build.rs:build_mcu_module](./build.rs)); 60 | 61 | Substeps are: 62 | 1. Register inputs with cargo; 63 | 2. Get a temporary directory; 64 | 3. Apply `atdf2svd`; 65 | 4. If a yaml patch exists, use it via [`svdtools`][] and read the new content 66 | / else, read the content of the unpatched file to continue; 67 | 5. Get the output directory; 68 | 6. Apply `svd2rust`; 69 | 7. Run [`prettyplease`][] on the module to make it readable in [`docs.rs`][]; 70 | 4. It will be included from `$OUT_DIR/pac/.rs` into the path 71 | `avr_device::devices::` (private), and re-exported as 72 | `avr_device::` (public). 73 | 74 | [`atdf2svd`]: https://github.com/Rahix/atdf2svd 75 | [`svd2rust`]: https://github.com/rust-embedded/svd2rust 76 | [`svdtools`]: https://github.com/rust-embedded/svdtools 77 | [`prettyplease`]: https://github.com/dtolnay/prettyplease 78 | [`docs.rs`]: https://docs.rs/avr-device/latest/avr_device 79 | 80 | ## License 81 | *avr-device* is licensed under either of 82 | 83 | * Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0) 84 | * MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT) 85 | 86 | at your option. 87 | 88 | The vendored *atdf* files are licensed under the Apache License, Version 2.0 ([LICENSE-VENDOR](vendor/LICENSE)). 89 | -------------------------------------------------------------------------------- /examples/atmega328p/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [build] 2 | target = "avr-none" 3 | rustflags = ["-C", "target-cpu=atmega328p"] 4 | 5 | [target.'cfg(target_arch = "avr")'] 6 | runner = "ravedude uno -cb 57600" 7 | 8 | [unstable] 9 | build-std = ["core"] 10 | -------------------------------------------------------------------------------- /examples/atmega328p/.gitignore: -------------------------------------------------------------------------------- 1 | target/ 2 | -------------------------------------------------------------------------------- /examples/atmega328p/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mega328-test" 3 | version = "0.1.0" 4 | authors = ["Frank Villaro-Dixon "] 5 | edition = "2024" 6 | license = "MIT OR Apache-2.0" 7 | 8 | [[bin]] 9 | name = "mega328-test" 10 | test = false 11 | bench = false 12 | 13 | 14 | [dependencies] 15 | ufmt = "0.2.0" 16 | nb = "0.1.2" 17 | embedded-hal = "0.2.3" 18 | 19 | 20 | [dependencies.avr-device] 21 | version = "0.7" 22 | path = "../.." 23 | features = ["atmega328p", "rt"] 24 | 25 | # Configure the build for minimal size - AVRs have very little program memory 26 | [profile.dev] 27 | panic = "abort" 28 | lto = true 29 | opt-level = "s" 30 | 31 | [profile.release] 32 | panic = "abort" 33 | codegen-units = 1 34 | debug = true 35 | lto = true 36 | opt-level = "s" 37 | -------------------------------------------------------------------------------- /examples/atmega328p/README.md: -------------------------------------------------------------------------------- 1 | # ATmega328P Example 2 | ## Overview 3 | This example showcases a minimal Rust program that solely utilizes bare 4 | register writes without relying on a Hardware Abstraction Layer. If you want 5 | to use a HAL, you can use [`avr-hal`], which uses `avr-device` under the hood. 6 | 7 | [`avr-hal`]: https://github.com/Rahix/avr-hal 8 | 9 | ## Demonstrated Features 10 | The primary purpose of this example is to illustrate how to interact directly 11 | with AVR microcontroller registers without using a higher-level HAL. 12 | 13 | This is of course more painful, but can be interesting in order to gain 14 | insights into the low-level details of AVR programming and understand the 15 | intricacies of register manipulation. 16 | 17 | ## Example Setup 18 | This example uses an ATmega328P with two LEDs attached (through an adequately 19 | sized resistor) to ground. The LED pins are: 20 | 21 | - `PD2` for the green led 22 | - `PD3` for the red led 23 | 24 | This example demonstrates three things: 25 | 26 | ### Panic Handler 27 | A custom panic handler which blinks the red LED connected to `PD3` 28 | indefinitely. 29 | 30 | This panic handler is called on the main loop by the `panic!()` macro once the 31 | counter reaches 10. 32 | 33 | ### Global Variables 34 | A global variable named `LED_STATE` is shared between the timer interrupt 35 | function and the main loop. The variable is a `Mutex>`. Being a 36 | mutex, the variable can only being accessed through a critical section. A 37 | critical section is created using the `interrupt::free` function which ensures 38 | that the closure is run in an interrupt free context. 39 | 40 | ### Timer Interrupt 41 | The `TIMER0_OVF` function is called as an interrupt handler when the `timer0` 42 | timer overflows. Every 16 overflows (as stored into the `OVF_COUNTER` static 43 | variable), it toggles the state of the `LED_STATE` variable. 44 | 45 | ### Main Loop 46 | The main loop just watches the state of the `LED_STATE` variable and sets the 47 | green led (`PD3`) according to the state of the boolean. 48 | 49 | Every time this variable changes, a counter is incremented. When it reaches 10, 50 | a panic is raised and our custom panic handler is called. 51 | 52 | ## Trying it out 53 | 1. First of all, check the README of the [`avr-hal`][avr-hal-readme] crate for 54 | an overview of required build dependencies. 55 | 2. Change into the example directory: 56 | ```bash 57 | cd examples/atmega328p/ 58 | ``` 59 | 3. Build the program: 60 | ```bash 61 | cargo build 62 | ``` 63 | 4. If you want to run the example on an Arduino Uno board, you can use 64 | [`ravedude`] to flash the microcontroller. The project is preconfigured for 65 | this, so all you need to do is: 66 | ```bash 67 | cargo run 68 | ``` 69 | You can configure a different ATmega328P board by editing the 70 | `.cargo/config.toml` file. 71 | 72 | [avr-hal-readme]: https://github.com/Rahix/avr-hal#quickstart 73 | [`ravedude`]: https://github.com/Rahix/avr-hal/tree/main/ravedude 74 | -------------------------------------------------------------------------------- /examples/atmega328p/rust-toolchain.toml: -------------------------------------------------------------------------------- 1 | [toolchain] 2 | channel = "nightly-2025-04-27" 3 | components = ["rust-src"] 4 | profile = "minimal" 5 | -------------------------------------------------------------------------------- /examples/atmega328p/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | #![feature(abi_avr_interrupt)] 4 | 5 | use core::cell::Cell; 6 | 7 | use avr_device::interrupt::{self, Mutex}; 8 | 9 | static LED_STATE: Mutex> = Mutex::new(Cell::new(true)); 10 | 11 | // Our panic handler. It hangs forever while making the PD3 pin blink. 12 | // In a real world use-case, this can be used to put the device into a 13 | // fail-state mode (shutting off motors, power, ...) 14 | #[cfg(not(doc))] 15 | #[panic_handler] 16 | fn panic(_info: &core::panic::PanicInfo) -> ! { 17 | // disable interrupts - firmware has panicked so no ISRs should continue running 18 | avr_device::interrupt::disable(); 19 | 20 | // get the peripherals so we can access serial and the LED. 21 | // 22 | // SAFETY: Because main() already has references to the peripherals this is an unsafe 23 | // operation - but because no other code can run after the panic handler was called, 24 | // we know it is okay. 25 | let dp = unsafe { avr_device::atmega328p::Peripherals::steal() }; 26 | 27 | loop { 28 | avr_device::asm::delay_cycles(1_000_000); 29 | dp.PORTD.portd().write(|w| w.pd3().set_bit()); 30 | avr_device::asm::delay_cycles(1_000_000); 31 | dp.PORTD.portd().write(|w| w.pd3().clear_bit()); 32 | } 33 | } 34 | 35 | #[avr_device::interrupt(atmega328p)] 36 | fn TIMER0_OVF() { 37 | // This interrupt should raise every (1024*255)/16MHz s ≈ 0.01s 38 | // We then count 61 times to approximate 1s. 39 | // XXX: this is a really bad way to count time 40 | 41 | use core::sync::atomic::{AtomicU8, Ordering::Relaxed}; 42 | 43 | static OVF_COUNTER: AtomicU8 = AtomicU8::new(0); 44 | const ROLLOVER: u8 = 61; 45 | 46 | let ovf = OVF_COUNTER.load(Relaxed); 47 | if ovf < ROLLOVER { 48 | OVF_COUNTER.store(ovf + 1, Relaxed); 49 | } else { 50 | OVF_COUNTER.store(0, Relaxed); 51 | interrupt::free(|cs| { 52 | LED_STATE.borrow(cs).set(!LED_STATE.borrow(cs).get()); 53 | }); 54 | } 55 | } 56 | 57 | #[avr_device::entry] 58 | fn main() -> ! { 59 | let dp = avr_device::atmega328p::Peripherals::take().unwrap(); 60 | 61 | // As you can see, we use .write() instead of .modify(), so the register 62 | // will be written value + the modified bits 63 | 64 | // Divide by 1024 -> 16MHz/1024 = 15.6kHz 65 | dp.TC0.tccr0b().write(|w| w.cs0().prescale_1024()); 66 | // Enable overflow interrupts 67 | dp.TC0.timsk0().write(|w| w.toie0().set_bit()); 68 | 69 | // Make pd2 and pd3 outputs 70 | // We use .modify() in order not to change the other bits 71 | dp.PORTD.ddrd().modify(|_, w| w.pd2().set_bit()); 72 | dp.PORTD.ddrd().modify(|_, w| w.pd3().set_bit()); 73 | 74 | // SAFETY: We can enable the interrupts here as we are not inside 75 | // a critical section. 76 | unsafe { 77 | avr_device::interrupt::enable(); 78 | } 79 | 80 | let mut counter = 0; 81 | let mut previous_state: bool = true; 82 | loop { 83 | let mut led_state: bool = true; 84 | interrupt::free(|cs| { 85 | led_state = LED_STATE.borrow(cs).get(); 86 | }); 87 | 88 | dp.PORTD.portd().modify(|_, w| w.pd2().bit(led_state)); 89 | 90 | // We want to make the program crash after 9 blinks 91 | if previous_state != led_state { 92 | counter += 1; 93 | } 94 | if counter > 9 { 95 | // The following panics, but it could also be 96 | // a more "general" bug like dividing by zero, out of bounds, 97 | // etc.. 98 | panic!(); 99 | } 100 | previous_state = led_state; 101 | } 102 | } 103 | -------------------------------------------------------------------------------- /macros/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "avr-device-macros" 3 | version = "0.7.0" 4 | 5 | authors = ["Rahix "] 6 | edition = "2021" 7 | description = "Attribute macros for re-export in `avr-device`" 8 | license = "MIT OR Apache-2.0" 9 | repository = "https://github.com/Rahix/avr-device" 10 | 11 | include = [ 12 | "src/*.rs" 13 | ] 14 | 15 | [lib] 16 | proc-macro = true 17 | 18 | [dependencies] 19 | quote = "1.0.7" 20 | proc-macro2 = "1.0.19" 21 | 22 | [dependencies.syn] 23 | version = "1.0.35" 24 | features = ["extra-traits", "full"] 25 | -------------------------------------------------------------------------------- /macros/src/lib.rs: -------------------------------------------------------------------------------- 1 | //! Adapted from 2 | //! 3 | //! Do not use this crate directly. 4 | 5 | extern crate proc_macro; 6 | 7 | use syn::spanned::Spanned; 8 | 9 | #[proc_macro_attribute] 10 | pub fn entry( 11 | args: proc_macro::TokenStream, 12 | input: proc_macro::TokenStream, 13 | ) -> proc_macro::TokenStream { 14 | let mut f = syn::parse_macro_input!(input as syn::ItemFn); 15 | 16 | // check the function signature 17 | let valid_signature = f.sig.constness.is_none() 18 | && f.vis == syn::Visibility::Inherited 19 | && f.sig.abi.is_none() 20 | && f.sig.inputs.is_empty() 21 | && f.sig.generics.params.is_empty() 22 | && f.sig.generics.where_clause.is_none() 23 | && f.sig.variadic.is_none() 24 | && match f.sig.output { 25 | syn::ReturnType::Default => false, 26 | syn::ReturnType::Type(_, ref ty) => matches!(**ty, syn::Type::Never(_)), 27 | }; 28 | 29 | if !valid_signature { 30 | return syn::parse::Error::new( 31 | f.span(), 32 | "`#[entry]` function must have signature `[unsafe] fn() -> !`", 33 | ) 34 | .to_compile_error() 35 | .into(); 36 | } 37 | 38 | if !args.is_empty() { 39 | return syn::parse::Error::new( 40 | proc_macro2::Span::call_site(), 41 | "This attribute accepts no arguments", 42 | ) 43 | .to_compile_error() 44 | .into(); 45 | } 46 | 47 | let (statics, stmts) = match extract_static_muts(f.block.stmts) { 48 | Err(e) => return e.to_compile_error().into(), 49 | Ok(x) => x, 50 | }; 51 | 52 | // Rename the function so it is not callable 53 | f.sig.ident = syn::Ident::new( 54 | &format!("__avr_device_rt_{}", f.sig.ident), 55 | proc_macro2::Span::call_site(), 56 | ); 57 | f.sig.inputs.extend(statics.iter().map(|statik| { 58 | let ident = &statik.ident; 59 | let ty = &statik.ty; 60 | let attrs = &statik.attrs; 61 | 62 | // Note that we use an explicit `'static` lifetime for the entry point arguments. This makes 63 | // it more flexible, and is sound here, since the entry will not be called again, ever. 64 | syn::parse::( 65 | quote::quote!(#[allow(non_snake_case)] #(#attrs)* #ident: &'static mut #ty).into(), 66 | ) 67 | .unwrap() 68 | })); 69 | f.block.stmts = stmts; 70 | 71 | let tramp_ident = syn::Ident::new( 72 | &format!("{}_trampoline", f.sig.ident), 73 | proc_macro2::Span::call_site(), 74 | ); 75 | let ident = &f.sig.ident; 76 | 77 | let resource_args = statics 78 | .iter() 79 | .map(|statik| { 80 | let (ref cfgs, ref attrs) = extract_cfgs(statik.attrs.clone()); 81 | let ident = &statik.ident; 82 | let ty = &statik.ty; 83 | let expr = &statik.expr; 84 | quote::quote! { 85 | #(#cfgs)* 86 | unsafe { 87 | #(#attrs)* 88 | static mut #ident: #ty = #expr; 89 | &mut #ident 90 | } 91 | } 92 | }) 93 | .collect::>(); 94 | 95 | if let Err(error) = check_attr_whitelist(&f.attrs, WhiteListCaller::Entry) { 96 | return error; 97 | } 98 | 99 | let (ref cfgs, ref attrs) = extract_cfgs(f.attrs.clone()); 100 | 101 | quote::quote! ( 102 | #[cfg(not(any(doc, target_arch = "avr")))] 103 | compile_error!( 104 | "Ensure that you are using an AVR target! You may need to change \ 105 | directories or pass a --target flag to cargo. See 106 | https://github.com/Rahix/avr-device/pull/41 for more details." 107 | ); 108 | 109 | #(#cfgs)* 110 | #(#attrs)* 111 | #[doc(hidden)] 112 | #[export_name = "main"] 113 | pub unsafe extern "C" fn #tramp_ident() { 114 | #ident( 115 | #(#resource_args),* 116 | ) 117 | } 118 | 119 | #[doc(hidden)] 120 | #f 121 | ) 122 | .into() 123 | } 124 | 125 | #[proc_macro_attribute] 126 | pub fn interrupt( 127 | args: proc_macro::TokenStream, 128 | input: proc_macro::TokenStream, 129 | ) -> proc_macro::TokenStream { 130 | let mut f: syn::ItemFn = 131 | syn::parse(input).expect("`#[interrupt]` must be applied to a function"); 132 | let args: Vec<_> = args.into_iter().collect(); 133 | 134 | let fspan = f.span(); 135 | let ident = f.sig.ident.clone(); 136 | 137 | let chip = if let Some(tree) = args.get(0) { 138 | if let proc_macro::TokenTree::Ident(ident) = tree { 139 | syn::Ident::new(&ident.to_string(), fspan) 140 | } else { 141 | return syn::parse::Error::new( 142 | proc_macro2::Span::call_site(), 143 | "#[interrupt(chip)]: chip must be an ident", 144 | ) 145 | .to_compile_error() 146 | .into(); 147 | } 148 | } else { 149 | return syn::parse::Error::new( 150 | proc_macro2::Span::call_site(), 151 | "#[interrupt(chip)] needs a chip argument", 152 | ) 153 | .to_compile_error() 154 | .into(); 155 | }; 156 | 157 | let valid_signature = f.sig.constness.is_none() 158 | && f.vis == syn::Visibility::Inherited 159 | && f.sig.abi.is_none() 160 | && f.sig.inputs.is_empty() 161 | && f.sig.generics.params.is_empty() 162 | && f.sig.generics.where_clause.is_none() 163 | && f.sig.variadic.is_none() 164 | && match f.sig.output { 165 | syn::ReturnType::Default => true, 166 | syn::ReturnType::Type(_, ref ty) => match **ty { 167 | syn::Type::Tuple(ref tuple) => tuple.elems.is_empty(), 168 | syn::Type::Never(..) => true, 169 | _ => false, 170 | }, 171 | }; 172 | 173 | if !valid_signature { 174 | return syn::parse::Error::new( 175 | fspan, 176 | "`#[interrupt]` handlers must have signature `[unsafe] fn() [-> !]`", 177 | ) 178 | .to_compile_error() 179 | .into(); 180 | } 181 | 182 | let (statics, stmts) = match extract_static_muts(f.block.stmts.iter().cloned()) { 183 | Err(e) => return e.to_compile_error().into(), 184 | Ok(x) => x, 185 | }; 186 | 187 | f.sig.ident = syn::Ident::new( 188 | &format!("__avr_device_rt_{}", f.sig.ident), 189 | proc_macro2::Span::call_site(), 190 | ); 191 | f.sig.inputs.extend(statics.iter().map(|statik| { 192 | let ident = &statik.ident; 193 | let ty = &statik.ty; 194 | let attrs = &statik.attrs; 195 | syn::parse::( 196 | quote::quote!(#[allow(non_snake_case)] #(#attrs)* #ident: &mut #ty).into(), 197 | ) 198 | .unwrap() 199 | })); 200 | f.block.stmts = stmts; 201 | 202 | let resource_args = statics 203 | .iter() 204 | .map(|statik| { 205 | let (ref cfgs, ref attrs) = extract_cfgs(statik.attrs.clone()); 206 | let ident = &statik.ident; 207 | let ty = &statik.ty; 208 | let expr = &statik.expr; 209 | quote::quote! { 210 | #(#cfgs)* 211 | unsafe { 212 | #(#attrs)* 213 | static mut #ident: #ty = #expr; 214 | &mut #ident 215 | } 216 | } 217 | }) 218 | .collect::>(); 219 | 220 | if let Err(error) = check_attr_whitelist(&f.attrs, WhiteListCaller::Interrupt) { 221 | return error; 222 | } 223 | 224 | let (ref cfgs, ref attrs) = extract_cfgs(f.attrs.clone()); 225 | 226 | let tramp_ident = syn::Ident::new( 227 | &format!("{}_trampoline", f.sig.ident), 228 | proc_macro2::Span::call_site(), 229 | ); 230 | let interrupt_ident = &f.sig.ident; 231 | 232 | quote::quote! { 233 | #(#cfgs)* 234 | #(#attrs)* 235 | ::avr_device::__avr_device_trampoline!(@#chip, #ident, pub extern "avr-interrupt" fn #tramp_ident() { 236 | #[allow(static_mut_refs)] 237 | #interrupt_ident( 238 | #(#resource_args),* 239 | ) 240 | }); 241 | 242 | #f 243 | } 244 | .into() 245 | } 246 | 247 | /// Extracts `static mut` vars from the beginning of the given statements 248 | fn extract_static_muts( 249 | stmts: impl IntoIterator, 250 | ) -> Result<(Vec, Vec), syn::parse::Error> { 251 | let mut istmts = stmts.into_iter(); 252 | 253 | let mut seen = std::collections::HashSet::new(); 254 | let mut statics = vec![]; 255 | let mut stmts = vec![]; 256 | while let Some(stmt) = istmts.next() { 257 | match stmt { 258 | syn::Stmt::Item(syn::Item::Static(var)) => { 259 | if var.mutability.is_some() { 260 | if seen.contains(&var.ident) { 261 | return Err(syn::parse::Error::new( 262 | var.ident.span(), 263 | format!("the name `{}` is defined multiple times", var.ident), 264 | )); 265 | } 266 | 267 | seen.insert(var.ident.clone()); 268 | statics.push(var); 269 | } else { 270 | stmts.push(syn::Stmt::Item(syn::Item::Static(var))); 271 | } 272 | } 273 | _ => { 274 | stmts.push(stmt); 275 | break; 276 | } 277 | } 278 | } 279 | 280 | stmts.extend(istmts); 281 | 282 | Ok((statics, stmts)) 283 | } 284 | 285 | fn extract_cfgs(attrs: Vec) -> (Vec, Vec) { 286 | let mut cfgs = vec![]; 287 | let mut not_cfgs = vec![]; 288 | 289 | for attr in attrs { 290 | if eq(&attr, "cfg") { 291 | cfgs.push(attr); 292 | } else { 293 | not_cfgs.push(attr); 294 | } 295 | } 296 | 297 | (cfgs, not_cfgs) 298 | } 299 | 300 | enum WhiteListCaller { 301 | Entry, 302 | Interrupt, 303 | } 304 | 305 | fn check_attr_whitelist(attrs: &[syn::Attribute], caller: WhiteListCaller) -> Result<(), proc_macro::TokenStream> { 306 | let whitelist = &[ 307 | "doc", 308 | "link_section", 309 | "cfg", 310 | "allow", 311 | "warn", 312 | "deny", 313 | "forbid", 314 | "cold", 315 | "naked", 316 | ]; 317 | 318 | 'o: for attr in attrs { 319 | for val in whitelist { 320 | if eq(attr, val) { 321 | continue 'o; 322 | } 323 | } 324 | 325 | let err_str = match caller { 326 | WhiteListCaller::Entry => "this attribute is not allowed on an avr-device entry point", 327 | WhiteListCaller::Interrupt => { 328 | "this attribute is not allowed on an interrupt handler controlled by avr-device" 329 | } 330 | }; 331 | 332 | return Err(syn::parse::Error::new(attr.span(), err_str) 333 | .to_compile_error() 334 | .into()); 335 | } 336 | 337 | Ok(()) 338 | } 339 | 340 | /// Returns `true` if `attr.path` matches `name` 341 | fn eq(attr: &syn::Attribute, name: &str) -> bool { 342 | attr.style == syn::AttrStyle::Outer && attr.path.is_ident(name) 343 | } 344 | -------------------------------------------------------------------------------- /patch/at90can128.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/at90/adc.yaml" 4 | - "common/at90/spi.yaml" 5 | - "common/at90/usart.yaml" 6 | -------------------------------------------------------------------------------- /patch/at90can32.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/at90/adc.yaml" 4 | - "common/at90/spi.yaml" 5 | - "common/at90/usart.yaml" 6 | -------------------------------------------------------------------------------- /patch/at90can64.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/at90/adc.yaml" 4 | - "common/at90/spi.yaml" 5 | - "common/at90/usart.yaml" 6 | -------------------------------------------------------------------------------- /patch/at90usb1286.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/usart.yaml" 6 | - "common/twi.yaml" 7 | -------------------------------------------------------------------------------- /patch/atmega1280.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/twi.yaml" 6 | - "common/usart.yaml" 7 | - "common/wdt.yaml" 8 | 9 | - "timer/atmega1280-2560.yaml" 10 | -------------------------------------------------------------------------------- /patch/atmega1284p.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/twi.yaml" 6 | - "common/usart.yaml" 7 | - "common/wdt.yaml" 8 | 9 | - "timer/atmega1284p.yaml" 10 | 11 | EXINT: 12 | EIMSK: 13 | _split: 14 | INT: 15 | name: INT%s 16 | description: External Interrupt %s Request Enable 17 | EIFR: 18 | _split: 19 | INTF: 20 | name: INTF%s 21 | description: External Interrupt Flags %s 22 | PCICR: 23 | _split: 24 | PCIE: 25 | name: PCIE%s 26 | description: Pin Change Interrupt Enable %s 27 | PCIFR: 28 | _split: 29 | PCIF: 30 | name: PCIF%s 31 | description: Pin Change Interrupt Flag %s 32 | -------------------------------------------------------------------------------- /patch/atmega128a.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/usart.yaml" 6 | - "timer/atmega128a.yaml" 7 | 8 | USART?: 9 | UCSR?C: 10 | _modify: 11 | UMSEL?: 12 | bitRange: "[7:6]" 13 | 14 | # Patches for the Two-Wire-Interface peripheral (i2c) 15 | # 16 | # - Make the Control Register read-write with only the 17 | # "Write Collision Flag" being read-only 18 | # - Fix the Prescaler enumerated values 19 | TWI*: 20 | TWCR: 21 | _modify: 22 | TWWC: 23 | access: read-only 24 | TWSR: 25 | _modify: 26 | TWS: 27 | access: read-only 28 | TWPS: 29 | _replace_enum: 30 | PRESCALER_1: [0, "Prescaler Value 1"] 31 | PRESCALER_4: [1, "Prescaler Value 4"] 32 | PRESCALER_16: [2, "Prescaler Value 16"] 33 | PRESCALER_64: [3, "Prescaler Value 64"] 34 | 35 | WDT: 36 | WDTCR: 37 | _delete: 38 | - WDP 39 | _add: 40 | WDPL: 41 | description: "Watchdog Timer Prescaler - Low Bits" 42 | bitRange: "[2:0]" 43 | WDPL: 44 | CYCLES_16K: [0, "- 16K (16,384) cycles, ~14ms"] 45 | CYCLES_32K: [1, "- 32K (32,768) cycles, ~28ms"] 46 | CYCLES_64K: [2, "- 64K (65,536) cycles, ~56ms"] 47 | CYCLES_128K: [3, "- 128K (131,072) cycles, ~0.11s"] 48 | CYCLES_256K: [4, "- 256K (262,144) cycles, ~0.22s"] 49 | CYCLES_512K: [5, "- 512K (524,288) cycles, ~0.45s"] 50 | CYCLES_1024K: [6, "- 1024K (1,048,576) cycles, ~0.9s"] 51 | CYCLES_2048K: [7, "- 2048K (2,097,152) cycles, ~1.8s"] 52 | 53 | ADC: 54 | ADMUX: 55 | MUX: 56 | _replace_enum: 57 | ADC0: [0, "ADC Single Ended Input pin 0"] 58 | ADC1: [1, "ADC Single Ended Input pin 1"] 59 | ADC2: [2, "ADC Single Ended Input pin 2"] 60 | ADC3: [3, "ADC Single Ended Input pin 3"] 61 | ADC4: [4, "ADC Single Ended Input pin 4"] 62 | ADC5: [5, "ADC Single Ended Input pin 5"] 63 | ADC6: [6, "ADC Single Ended Input pin 6"] 64 | ADC7: [7, "ADC Single Ended Input pin 7"] 65 | ADC_VBG: [29, "Internal Reference (VBG)"] 66 | ADC_GND: [31, "0V (GND)"] 67 | -------------------------------------------------------------------------------- /patch/atmega16.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | 6 | - "timer/atmega16.yaml" 7 | 8 | ADC: 9 | ADMUX: 10 | MUX: 11 | ADC0: [0, "Single-ended Input ADC0"] 12 | ADC1: [1, "Single-ended Input ADC1"] 13 | ADC2: [2, "Single-ended Input ADC2"] 14 | ADC3: [3, "Single-ended Input ADC3"] 15 | ADC4: [4, "Single-ended Input ADC4"] 16 | ADC5: [5, "Single-ended Input ADC5"] 17 | ADC6: [6, "Single-ended Input ADC6"] 18 | ADC7: [7, "Single-ended Input ADC7"] 19 | 20 | ADC0_ADC0_10X: [8, "Differential Input: Positive - ADC0, Negative - ADC0, Gain - 10x"] 21 | ADC1_ADC0_10X: [9, "Differential Input: Positive - ADC1, Negative - ADC0, Gain - 10x"] 22 | ADC0_ADC0_200X: [10, "Differential Input: Positive - ADC0, Negative - ADC0, Gain - 200x"] 23 | ADC1_ADC0_200X: [11, "Differential Input: Positive - ADC1, Negative - ADC0, Gain - 200x"] 24 | ADC2_ADC2_10X: [12, "Differential Input: Positive - ADC2, Negative - ADC2, Gain - 10x"] 25 | ADC3_ADC2_10X: [13, "Differential Input: Positive - ADC3, Negative - ADC2, Gain - 10x"] 26 | ADC2_ADC2_200X: [14, "Differential Input: Positive - ADC2, Negative - ADC2, Gain - 200x"] 27 | ADC3_ADC2_200X: [15, "Differential Input: Positive - ADC3, Negative - ADC2, Gain - 200x"] 28 | ADC0_ADC1_1X: [16, "Differential Input: Positive - ADC0, Negative - ADC1, Gain - 1x"] 29 | ADC1_ADC1_1X: [17, "Differential Input: Positive - ADC1, Negative - ADC1, Gain - 1x"] 30 | ADC2_ADC1_1X: [18, "Differential Input: Positive - ADC2, Negative - ADC1, Gain - 1x"] 31 | ADC3_ADC1_1X: [19, "Differential Input: Positive - ADC3, Negative - ADC1, Gain - 1x"] 32 | ADC4_ADC1_1X: [20, "Differential Input: Positive - ADC4, Negative - ADC1, Gain - 1x"] 33 | ADC5_ADC1_1X: [21, "Differential Input: Positive - ADC5, Negative - ADC1, Gain - 1x"] 34 | ADC6_ADC1_1X: [22, "Differential Input: Positive - ADC6, Negative - ADC1, Gain - 1x"] 35 | ADC7_ADC1_1X: [23, "Differential Input: Positive - ADC7, Negative - ADC1, Gain - 1x"] 36 | ADC0_ADC2_1X: [24, "Differential Input: Positive - ADC0, Negative - ADC2, Gain - 1x"] 37 | ADC1_ADC2_1X: [25, "Differential Input: Positive - ADC1, Negative - ADC2, Gain - 1x"] 38 | ADC2_ADC2_1X: [26, "Differential Input: Positive - ADC2, Negative - ADC2, Gain - 1x"] 39 | ADC3_ADC2_1X: [27, "Differential Input: Positive - ADC3, Negative - ADC2, Gain - 1x"] 40 | ADC4_ADC2_1X: [28, "Differential Input: Positive - ADC4, Negative - ADC2, Gain - 1x"] 41 | ADC5_ADC2_1X: [29, "Differential Input: Positive - ADC5, Negative - ADC2, Gain - 1x"] 42 | 43 | ADC_VBG: [30, "Internal Reference (VBG)"] 44 | ADC_GND: [31, "0V (GND)"] 45 | 46 | TWI: 47 | TWCR: 48 | _modify: 49 | TWWC: 50 | access: read-only 51 | TWSR: 52 | _modify: 53 | TWS: 54 | access: read-only 55 | TWPS: 56 | _replace_enum: 57 | PRESCALER_1: [0, "Prescaler Value 1"] 58 | PRESCALER_4: [1, "Prescaler Value 4"] 59 | PRESCALER_16: [2, "Prescaler Value 16"] 60 | PRESCALER_64: [3, "Prescaler Value 64"] 61 | 62 | WDT: 63 | WDTCR: 64 | _delete: 65 | - WDP 66 | _add: 67 | WDPL: 68 | description: "Watchdog Timer Prescaler - Low Bits" 69 | bitRange: "[2:0]" 70 | WDPL: 71 | CYCLES_16K: [0, "- 16K (16384) cycles, ~16ms"] 72 | CYCLES_32K: [1, "- 32K (32768) cycles, ~32ms"] 73 | CYCLES_64K: [2, "- 64K (65536) cycles, ~65ms"] 74 | CYCLES_128K: [3, "- 128K (131072) cycles, ~0.13s"] 75 | CYCLES_256K: [4, "- 256K (262144) cycles, ~0.26s"] 76 | CYCLES_512K: [5, "- 512K (524288) cycles, ~0.52s"] 77 | CYCLES_1024K: [6, "- 1024K (1048576) cycles, ~1.0s"] 78 | CYCLES_2048K: [7, "- 2048K (2097152) cycles, ~2.1s"] 79 | 80 | USART: 81 | UCSRA: 82 | _modify: 83 | UPE: 84 | access: read-only 85 | name: PE 86 | DOR: 87 | access: read-only 88 | FE: 89 | access: read-only 90 | UDRE: 91 | access: read-only 92 | TXC: 93 | description: "USART Transmit Complete" 94 | RXC: 95 | access: read-only 96 | UCSRB: 97 | _modify: 98 | RXB8: 99 | access: read-only 100 | UCSRC: 101 | UMSEL: 102 | _replace_enum: 103 | USART_ASYNC: [0, "Asynchronous USART"] 104 | USART_SYNC: [1, "Synchronous USART"] 105 | UPM: 106 | _replace_enum: 107 | DISABLED: [0, "Disabled"] 108 | PARITY_EVEN: [2, "Enabled, Even Parity"] 109 | PARITY_ODD: [3, "Enabled, Odd Parity"] 110 | USBS: 111 | _replace_enum: 112 | STOP1: [0, "1-bit"] 113 | STOP2: [1, "2-bit"] 114 | UCSZ: 115 | _replace_enum: 116 | CHR5: [0, "Character Size: 5 bit"] 117 | CHR6: [1, "Character Size: 6 bit"] 118 | CHR7: [2, "Character Size: 7 bit"] 119 | CHR8: [3, "Character Size: 8 bit"] 120 | UCPOL: 121 | _replace_enum: 122 | RISING_EDGE: [0, "Transmit on Rising XCK Edge, Receive on Falling XCK Edge"] 123 | FALLING_EDGE: [1, "Transmit on Falling XCK Edge, Receive on Rising XCK Edge"] 124 | -------------------------------------------------------------------------------- /patch/atmega164pa.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/adc.yaml" 3 | - "common/twi.yaml" 4 | - "common/usart.yaml" 5 | - "common/wdt.yaml" 6 | 7 | EEPROM: 8 | EECR: 9 | EEPM: 10 | _replace_enum: 11 | VAL_0x00: [0, "Atomic (erase and write in one operation)"] 12 | VAL_0x01: [1, "Erase only"] 13 | VAL_0x02: [2, "Write only"] 14 | -------------------------------------------------------------------------------- /patch/atmega168.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/twi.yaml" 6 | - "common/usart.yaml" 7 | - "common/wdt.yaml" 8 | 9 | - "timer/atmega328p.yaml" 10 | -------------------------------------------------------------------------------- /patch/atmega16u2.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/spi.yaml" 5 | - "common/usart.yaml" 6 | - "common/wdt.yaml" 7 | 8 | - "timer/atmega8u2.yaml" 9 | 10 | PLL: 11 | PLLCSR: 12 | _modify: 13 | PLOCK: 14 | access: read-only -------------------------------------------------------------------------------- /patch/atmega2560.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/twi.yaml" 6 | - "common/usart.yaml" 7 | - "common/wdt.yaml" 8 | 9 | - "timer/atmega1280-2560.yaml" 10 | -------------------------------------------------------------------------------- /patch/atmega3208.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/mega0/port.yaml" -------------------------------------------------------------------------------- /patch/atmega3209.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/mega0/port.yaml" -------------------------------------------------------------------------------- /patch/atmega324pa.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/twi.yaml" 5 | - "common/usart.yaml" 6 | - "common/wdt.yaml" 7 | 8 | - "timer/atmega324pa.yaml" 9 | 10 | EXINT: 11 | EIMSK: 12 | _split: 13 | INT: 14 | name: INT%s 15 | description: External Interrupt %s Request Enable 16 | EIFR: 17 | _split: 18 | INTF: 19 | name: INTF%s 20 | description: External Interrupt Flags %s 21 | PCICR: 22 | _split: 23 | PCIE: 24 | name: PCIE%s 25 | description: Pin Change Interrupt Enable %s 26 | PCIFR: 27 | _split: 28 | PCIF: 29 | name: PCIF%s 30 | description: Pin Change Interrupt Flag %s 31 | -------------------------------------------------------------------------------- /patch/atmega328p.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/twi.yaml" 6 | - "common/usart.yaml" 7 | - "common/wdt.yaml" 8 | 9 | - "timer/atmega328p.yaml" 10 | 11 | EXINT: 12 | EIMSK: 13 | _modify: 14 | INT: 15 | description: External Interrupt Request Enable 16 | _split: [INT] 17 | -------------------------------------------------------------------------------- /patch/atmega328pb.yaml: -------------------------------------------------------------------------------- 1 | # Remove index suffix from all registers and fields 2 | SPI0: 3 | _strip_end: 4 | - "0" 5 | SPI1: 6 | _strip_end: 7 | - "1" 8 | SPSR: 9 | _strip_end: 10 | - "1" 11 | SPCR: 12 | _strip_end: 13 | - "1" 14 | 15 | # Remove index suffix from all registers and fields 16 | TWI0: 17 | _strip_end: 18 | - "0" 19 | TWI1: 20 | _strip_end: 21 | - "1" 22 | TWCR: 23 | _strip_end: 24 | - "1" 25 | TWSR: 26 | _strip_end: 27 | - "1" 28 | 29 | # the svd has a register called ACSRA with no fields that 30 | # messes up the patch when using `common/ac.yaml`, so the 31 | # ac has to be patched here instead. 32 | AC: 33 | ACSR: 34 | _modify: 35 | ACIS: 36 | description: "Analog Comparator Interrupt Mode Select" 37 | ACO: 38 | access: read-only 39 | ACIS: 40 | _replace_enum: 41 | ON_TOGGLE: [0, "Interrupt on Toggle"] 42 | # Leaving [1, 'Reserved'] out 43 | ON_FALLING_EDGE: [2, "Interrupt on Falling Edge"] 44 | ON_RISING_EDGE: [3, "Interrupt on Rising Edge"] 45 | 46 | _include: 47 | - "common/adc.yaml" 48 | - "common/usart.yaml" 49 | - "common/spi.yaml" 50 | - "common/twi.yaml" 51 | - "common/wdt.yaml" 52 | 53 | - "timer/atmega328pb.yaml" 54 | 55 | EXINT: 56 | EIMSK: 57 | _modify: 58 | INT: 59 | description: External Interrupt Request Enable 60 | _split: [INT] 61 | 62 | 63 | -------------------------------------------------------------------------------- /patch/atmega32a.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | 6 | ADC: 7 | ADMUX: 8 | MUX: 9 | ADC0: [0, "Single-ended Input ADC0"] 10 | ADC1: [1, "Single-ended Input ADC1"] 11 | ADC2: [2, "Single-ended Input ADC2"] 12 | ADC3: [3, "Single-ended Input ADC3"] 13 | ADC4: [4, "Single-ended Input ADC4"] 14 | ADC5: [5, "Single-ended Input ADC5"] 15 | ADC6: [6, "Single-ended Input ADC6"] 16 | ADC7: [7, "Single-ended Input ADC7"] 17 | 18 | ADC0_ADC0_10X: [8, "Differential Input: Positive - ADC0, Negative - ADC0, Gain - 10x"] 19 | ADC1_ADC0_10X: [9, "Differential Input: Positive - ADC1, Negative - ADC0, Gain - 10x"] 20 | ADC0_ADC0_200X: [10, "Differential Input: Positive - ADC0, Negative - ADC0, Gain - 200x"] 21 | ADC1_ADC0_200X: [11, "Differential Input: Positive - ADC1, Negative - ADC0, Gain - 200x"] 22 | ADC2_ADC2_10X: [12, "Differential Input: Positive - ADC2, Negative - ADC2, Gain - 10x"] 23 | ADC3_ADC2_10X: [13, "Differential Input: Positive - ADC3, Negative - ADC2, Gain - 10x"] 24 | ADC2_ADC2_200X: [14, "Differential Input: Positive - ADC2, Negative - ADC2, Gain - 200x"] 25 | ADC3_ADC2_200X: [15, "Differential Input: Positive - ADC3, Negative - ADC2, Gain - 200x"] 26 | ADC0_ADC1_1X: [16, "Differential Input: Positive - ADC0, Negative - ADC1, Gain - 1x"] 27 | ADC1_ADC1_1X: [17, "Differential Input: Positive - ADC1, Negative - ADC1, Gain - 1x"] 28 | ADC2_ADC1_1X: [18, "Differential Input: Positive - ADC2, Negative - ADC1, Gain - 1x"] 29 | ADC3_ADC1_1X: [19, "Differential Input: Positive - ADC3, Negative - ADC1, Gain - 1x"] 30 | ADC4_ADC1_1X: [20, "Differential Input: Positive - ADC4, Negative - ADC1, Gain - 1x"] 31 | ADC5_ADC1_1X: [21, "Differential Input: Positive - ADC5, Negative - ADC1, Gain - 1x"] 32 | ADC6_ADC1_1X: [22, "Differential Input: Positive - ADC6, Negative - ADC1, Gain - 1x"] 33 | ADC7_ADC1_1X: [23, "Differential Input: Positive - ADC7, Negative - ADC1, Gain - 1x"] 34 | ADC0_ADC2_1X: [24, "Differential Input: Positive - ADC0, Negative - ADC2, Gain - 1x"] 35 | ADC1_ADC2_1X: [25, "Differential Input: Positive - ADC1, Negative - ADC2, Gain - 1x"] 36 | ADC2_ADC2_1X: [26, "Differential Input: Positive - ADC2, Negative - ADC2, Gain - 1x"] 37 | ADC3_ADC2_1X: [27, "Differential Input: Positive - ADC3, Negative - ADC2, Gain - 1x"] 38 | ADC4_ADC2_1X: [28, "Differential Input: Positive - ADC4, Negative - ADC2, Gain - 1x"] 39 | ADC5_ADC2_1X: [29, "Differential Input: Positive - ADC5, Negative - ADC2, Gain - 1x"] 40 | 41 | ADC_VBG: [30, "Internal Reference (VBG)"] 42 | ADC_GND: [31, "0V (GND)"] 43 | 44 | TWI: 45 | TWCR: 46 | _modify: 47 | TWWC: 48 | access: read-only 49 | TWSR: 50 | _modify: 51 | TWS: 52 | access: read-only 53 | TWPS: 54 | _replace_enum: 55 | PRESCALER_1: [0, "Prescaler Value 1"] 56 | PRESCALER_4: [1, "Prescaler Value 4"] 57 | PRESCALER_16: [2, "Prescaler Value 16"] 58 | PRESCALER_64: [3, "Prescaler Value 64"] 59 | 60 | WDT: 61 | WDTCR: 62 | _modify: 63 | WDTOE: 64 | name: WDCE 65 | _delete: 66 | - WDP 67 | _add: 68 | WDPL: 69 | description: "Watchdog Timer Prescaler - Low Bits" 70 | bitRange: "[2:0]" 71 | WDPL: 72 | CYCLES_16K: [0, "- 16K (16384) cycles, ~16ms"] 73 | CYCLES_32K: [1, "- 32K (32768) cycles, ~32ms"] 74 | CYCLES_64K: [2, "- 64K (65536) cycles, ~65ms"] 75 | CYCLES_128K: [3, "- 128K (131072) cycles, ~0.13s"] 76 | CYCLES_256K: [4, "- 256K (262144) cycles, ~0.26s"] 77 | CYCLES_512K: [5, "- 512K (524288) cycles, ~0.52s"] 78 | CYCLES_1024K: [6, "- 1024K (1048576) cycles, ~1.0s"] 79 | CYCLES_2048K: [7, "- 2048K (2097152) cycles, ~2.1s"] 80 | 81 | 82 | USART: 83 | UCSRA: 84 | _modify: 85 | UPE: 86 | access: read-only 87 | name: PE 88 | DOR: 89 | access: read-only 90 | FE: 91 | access: read-only 92 | UDRE: 93 | access: read-only 94 | TXC: 95 | description: "USART Transmit Complete" 96 | RXC: 97 | access: read-only 98 | UCSRB: 99 | _modify: 100 | RXB8: 101 | access: read-only 102 | UCSRC: 103 | UMSEL: 104 | _replace_enum: 105 | USART_ASYNC: [0, "Asynchronous USART"] 106 | USART_SYNC: [1, "Synchronous USART"] 107 | UPM: 108 | _replace_enum: 109 | DISABLED: [0, "Disabled"] 110 | PARITY_EVEN: [2, "Enabled, Even Parity"] 111 | PARITY_ODD: [3, "Enabled, Odd Parity"] 112 | USBS: 113 | _replace_enum: 114 | STOP1: [0, "1-bit"] 115 | STOP2: [1, "2-bit"] 116 | UCSZ: 117 | _replace_enum: 118 | CHR5: [0, "Character Size: 5 bit"] 119 | CHR6: [1, "Character Size: 6 bit"] 120 | CHR7: [2, "Character Size: 7 bit"] 121 | CHR8: [3, "Character Size: 8 bit"] 122 | UCPOL: 123 | _replace_enum: 124 | RISING_EDGE: [0, "Transmit on Rising XCK Edge, Receive on Falling XCK Edge"] 125 | FALLING_EDGE: [1, "Transmit on Falling XCK Edge, Receive on Rising XCK Edge"] -------------------------------------------------------------------------------- /patch/atmega32u2.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/spi.yaml" 5 | - "common/usart.yaml" 6 | - "common/wdt.yaml" 7 | 8 | - "timer/atmega8u2.yaml" 9 | 10 | PLL: 11 | PLLCSR: 12 | _modify: 13 | PLOCK: 14 | access: read-only -------------------------------------------------------------------------------- /patch/atmega32u4.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/pll.yaml" 5 | - "common/spi.yaml" 6 | - "common/twi.yaml" 7 | - "common/usart.yaml" 8 | - "common/wdt.yaml" 9 | 10 | - "timer/atmega32u4.yaml" 11 | 12 | # Pin F7 is not present in the ATDF file for some reason. 13 | PORTF: 14 | DDRF: 15 | _add: 16 | PF7: 17 | description: "Pin F7" 18 | bitRange: "[7:7]" 19 | access: read-write 20 | PINF: 21 | _add: 22 | PF7: 23 | description: "Pin F7" 24 | bitRange: "[7:7]" 25 | access: read-write 26 | PORTF: 27 | _add: 28 | PF7: 29 | description: "Pin F7" 30 | bitRange: "[7:7]" 31 | access: read-write 32 | -------------------------------------------------------------------------------- /patch/atmega4808.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/mega0/port.yaml" -------------------------------------------------------------------------------- /patch/atmega4809.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/mega0/port.yaml" 3 | -------------------------------------------------------------------------------- /patch/atmega48p.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/twi.yaml" 6 | - "common/usart.yaml" 7 | - "common/wdt.yaml" 8 | 9 | - "timer/atmega328p.yaml" 10 | -------------------------------------------------------------------------------- /patch/atmega64.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/usart.yaml" 6 | 7 | USART?: 8 | UCSR?C: 9 | _modify: 10 | UMSEL?: 11 | bitRange: "[7:6]" 12 | -------------------------------------------------------------------------------- /patch/atmega644.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/twi.yaml" 6 | - "common/usart.yaml" 7 | - "common/wdt.yaml" 8 | 9 | - "timer/atmega328p.yaml" 10 | -------------------------------------------------------------------------------- /patch/atmega8.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | 6 | - "timer/atmega8.yaml" 7 | 8 | TWI: 9 | TWCR: 10 | _modify: 11 | TWWC: 12 | access: read-only 13 | TWSR: 14 | _modify: 15 | TWS: 16 | access: read-only 17 | TWPS: 18 | _replace_enum: 19 | PRESCALER_1: [0, "Prescaler Value 1"] 20 | PRESCALER_4: [1, "Prescaler Value 4"] 21 | PRESCALER_16: [2, "Prescaler Value 16"] 22 | PRESCALER_64: [3, "Prescaler Value 64"] 23 | 24 | ADC: 25 | ADMUX: 26 | MUX: 27 | _replace_enum: 28 | ADC0: [0, "ADC Single Ended Input pin 0"] 29 | ADC1: [1, "ADC Single Ended Input pin 1"] 30 | ADC2: [2, "ADC Single Ended Input pin 2"] 31 | ADC3: [3, "ADC Single Ended Input pin 3"] 32 | ADC4: [4, "ADC Single Ended Input pin 4"] 33 | ADC5: [5, "ADC Single Ended Input pin 5"] 34 | ADC6: [6, "ADC Single Ended Input pin 6"] 35 | ADC7: [7, "ADC Single Ended Input pin 7"] 36 | ADC_VBG: [14, "Internal Reference (VBG)"] 37 | ADC_GND: [15, "0V (GND)"] 38 | 39 | USART: 40 | UCSRA: 41 | _modify: 42 | UPE: 43 | name: PE 44 | access: read-only 45 | DOR: 46 | access: read-only 47 | FE: 48 | access: read-only 49 | UDRE: 50 | access: read-only 51 | TXC: 52 | description: "USART Transmit Complete" 53 | RXC: 54 | access: read-only 55 | UCSRB: 56 | _modify: 57 | RXB8: 58 | access: read-only 59 | UCSRC: 60 | UMSEL: 61 | _replace_enum: 62 | USART_ASYNC: [0, "Asynchronous USART"] 63 | USART_SYNC: [1, "Synchronous USART"] 64 | UPM: 65 | _replace_enum: 66 | DISABLED: [0, "Disabled"] 67 | PARITY_EVEN: [2, "Enabled, Even Parity"] 68 | PARITY_ODD: [3, "Enabled, Odd Parity"] 69 | USBS: 70 | _replace_enum: 71 | STOP1: [0, "1-bit"] 72 | STOP2: [1, "2-bit"] 73 | UCSZ: 74 | _replace_enum: 75 | CHR5: [0, "Character Size: 5 bit"] 76 | CHR6: [1, "Character Size: 6 bit"] 77 | CHR7: [2, "Character Size: 7 bit"] 78 | CHR8: [3, "Character Size: 8 bit"] 79 | UCPOL: 80 | _replace_enum: 81 | RISING_EDGE: [0, "Transmit on Rising XCK Edge, Receive on Falling XCK Edge"] 82 | FALLING_EDGE: [1, "Transmit on Falling XCK Edge, Receive on Rising XCK Edge"] 83 | 84 | WDT: 85 | WDTCR: 86 | _delete: 87 | - WDP 88 | _add: 89 | WDPL: 90 | description: "Watchdog Timer Prescaler - Low Bits" 91 | bitRange: "[2:0]" 92 | WDPL: 93 | CYCLES_16K: [0, "- 16K (16384) cycles, ~16ms"] 94 | CYCLES_32K: [1, "- 32K (32768) cycles, ~32ms"] 95 | CYCLES_64K: [2, "- 64K (65536) cycles, ~65ms"] 96 | CYCLES_128K: [3, "- 128K (131072) cycles, ~0.13s"] 97 | CYCLES_256K: [4, "- 256K (262144) cycles, ~0.26s"] 98 | CYCLES_512K: [5, "- 512K (524288) cycles, ~0.52s"] 99 | CYCLES_1024K: [6, "- 1024K (1048576) cycles, ~1.0s"] 100 | CYCLES_2048K: [7, "- 2048K (2097152) cycles, ~2.1s"] 101 | -------------------------------------------------------------------------------- /patch/atmega88p.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/spi.yaml" 5 | - "common/twi.yaml" 6 | - "common/usart.yaml" 7 | - "common/wdt.yaml" 8 | 9 | - "timer/atmega328p.yaml" 10 | -------------------------------------------------------------------------------- /patch/atmega8u2.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/spi.yaml" 5 | - "common/usart.yaml" 6 | - "common/wdt.yaml" 7 | - "timer/atmega8u2.yaml" 8 | 9 | PLL: 10 | PLLCSR: 11 | _modify: 12 | PLOCK: 13 | access: read-only 14 | -------------------------------------------------------------------------------- /patch/attiny13a.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/wdt.yaml" 5 | 6 | - "common/tiny/exint.yaml" 7 | 8 | - "timer/attiny13a.yaml" 9 | 10 | AC: 11 | _modify: 12 | DIDR0: 13 | description: "Digital Input Disable Register 0" 14 | ADC: 15 | _modify: 16 | ADCSRA: 17 | description: "ADC Control and Status Register A" 18 | ADCSRA: 19 | ADPS: 20 | _replace_enum: 21 | PRESCALER_2: [1, "Prescaler Value 2"] 22 | PRESCALER_4: [2, "Prescaler Value 4"] 23 | PRESCALER_8: [3, "Prescaler Value 8"] 24 | PRESCALER_16: [4, "Prescaler Value 16"] 25 | PRESCALER_32: [5, "Prescaler Value 32"] 26 | PRESCALER_64: [6, "Prescaler Value 64"] 27 | PRESCALER_128: [7, "Prescaler Value 128"] 28 | ADCSRB: 29 | ADTS: 30 | _replace_enum: 31 | FREE: [0, "Free Running mode"] 32 | AC: [1, "Analog Comparator"] 33 | INT0: [2, "External Interrupt Request 0"] 34 | TC0_CMA: [3, "Timer/Counter0 Compare Match A"] 35 | TC0_OVF: [4, "Timer/Counter0 Overflow"] 36 | TC0_CMB: [5, "Timer/Counter0 Compare Match B"] 37 | PCIR: [6, "Pin Change Interrupt Request"] 38 | ADMUX: 39 | _modify: 40 | MUX: 41 | _write_constraint: enum 42 | MUX: 43 | _replace_enum: 44 | ADC0: [0, "Single-ended Input ADC0"] 45 | ADC1: [1, "Single-ended Input ADC1"] 46 | ADC2: [2, "Single-ended Input ADC2"] 47 | ADC3: [3, "Single-ended Input ADC3"] 48 | REFS0: 49 | _replace_enum: 50 | VCC: [0, "Vcc used as Voltage Reference"] 51 | INTERNAL: [1, "Internal Voltage Reference of 1.1V "] 52 | CPU: 53 | CLKPR: 54 | CLKPS: 55 | _replace_enum: 56 | PRESCALER_1: [0, "Prescaler Value 1"] 57 | PRESCALER_2: [1, "Prescaler Value 2"] 58 | PRESCALER_4: [2, "Prescaler Value 4"] 59 | PRESCALER_8: [3, "Prescaler Value 8"] 60 | PRESCALER_16: [4, "Prescaler Value 16"] 61 | PRESCALER_32: [5, "Prescaler Value 32"] 62 | PRESCALER_64: [6, "Prescaler Value 64"] 63 | PRESCALER_128: [7, "Prescaler Value 128"] 64 | PRESCALER_256: [8, "Prescaler Value 256"] 65 | MCUCR: 66 | _delete: 67 | - ISC? 68 | _add: 69 | BODS: 70 | description: "BOD Sleep (available on some devices)" 71 | bitOffset: 7 72 | bitWidth: 1 73 | access: read-write 74 | BODSE: 75 | description: "BOD Sleep Enable (available on some devices)" 76 | bitOffset: 2 77 | bitWidth: 1 78 | access: read-write 79 | -------------------------------------------------------------------------------- /patch/attiny1604.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/attiny1604.svd 2 | 3 | _include: 4 | - common/attiny-xmega/common.yaml 5 | - common/attiny-xmega/0-series.yaml 6 | -------------------------------------------------------------------------------- /patch/attiny1626.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - common/attiny-xmega/common.yaml 3 | - common/attiny-xmega/2-series.yaml 4 | -------------------------------------------------------------------------------- /patch/attiny167.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/spi.yaml" 5 | # - "common/twi.yaml" 6 | - "common/wdt.yaml" 7 | - "common/tiny/usi.yaml" 8 | - "timer/attiny167.yaml" 9 | 10 | ADC: 11 | ADMUX: 12 | _modify: 13 | MUX: 14 | description: "Analog Channel Selection Bits" 15 | MUX: 16 | _replace_enum: 17 | ADC0: [0, "ADC Single Ended Input pin 0"] 18 | ADC1: [1, "ADC Single Ended Input pin 1"] 19 | ADC2: [2, "ADC Single Ended Input pin 2"] 20 | ADC3: [3, "ADC Single Ended Input pin 3"] 21 | ADC4: [4, "ADC Single Ended Input pin 4"] 22 | ADC5: [5, "ADC Single Ended Input pin 5"] 23 | ADC6: [6, "ADC Single Ended Input pin 6"] 24 | ADC7: [7, "ADC Single Ended Input pin 7"] 25 | ADC8: [8, "ADC Single Ended Input pin 8"] 26 | ADC9: [9, "ADC Single Ended Input pin 9"] 27 | ADC10: [10, "ADC Single Ended Input pin 10"] 28 | TEMPSENS: [11, "Temperature sensor"] 29 | ADC_VBG: [12, "Internal Reference (VBG)"] 30 | ADC_AVCC_4: [13, "AVcc/4"] 31 | ADC_GND: [14, "0V (GND)"] 32 | REFS: 33 | _replace_enum: 34 | AVCC: [0, "AVcc or External Reference"] 35 | INTERNAL_11: [1, "Internal 1.1V Voltage Reference"] 36 | INTERNAL_256: [3, "Internal 2.56V Voltage Reference"] 37 | ADCSRA: 38 | ADPS: 39 | _replace_enum: 40 | PRESCALER_2: [1, "Prescaler Value 2"] 41 | PRESCALER_4: [2, "Prescaler Value 4"] 42 | PRESCALER_8: [3, "Prescaler Value 8"] 43 | PRESCALER_16: [4, "Prescaler Value 16"] 44 | PRESCALER_32: [5, "Prescaler Value 32"] 45 | PRESCALER_64: [6, "Prescaler Value 64"] 46 | PRESCALER_128: [7, "Prescaler Value 128"] 47 | ADCSRB: 48 | ADTS: 49 | _replace_enum: 50 | FREE: [0, "Free Running mode"] 51 | AC: [1, "Analog Comparator"] 52 | INT0: [2, "External Interrupt Request 0"] 53 | TC0_CMA: [3, "Timer/Counter0 Compare Match A"] 54 | TC0_OVF: [4, "Timer/Counter0 Overflow"] 55 | TC1_CMB: [5, "Timer/Counter1 Compare Match B"] 56 | TC1_CE: [6, "Timer/Counter1 Capture Event"] 57 | WDT: [7, "Watchdog Interrupt Request"] 58 | CPU: 59 | CLKPR: 60 | CLKPS: 61 | _replace_enum: 62 | PRESCALER_1: [0, "Prescaler Value 1"] 63 | PRESCALER_2: [1, "Prescaler Value 2"] 64 | PRESCALER_4: [2, "Prescaler Value 4"] 65 | PRESCALER_8: [3, "Prescaler Value 8"] 66 | PRESCALER_16: [4, "Prescaler Value 16"] 67 | PRESCALER_32: [5, "Prescaler Value 32"] 68 | PRESCALER_64: [6, "Prescaler Value 64"] 69 | PRESCALER_128: [7, "Prescaler Value 128"] 70 | PRESCALER_256: [8, "Prescaler Value 256"] 71 | EXINT: 72 | EICRA: 73 | ISC?: 74 | _replace_enum: 75 | LOW: [0, "The low level of INTx generates an interrupt request"] 76 | TOGGLE: [1, "Any logical change on INTx generates an interrupt request"] 77 | FALLING: [2, "The falling edge of INTx generates an interrupt request"] 78 | RISING: [3, "The rising edge of INTx generates an interrupt request"] 79 | _modify: 80 | PCICR: 81 | description: "Pin Change Interrupt Control Register" 82 | 83 | PORTA: 84 | DDRA: 85 | _add: 86 | PA0: 87 | description: "Pin A0" 88 | bitRange: "[0:0]" 89 | access: read-write 90 | PA1: 91 | description: "Pin A1" 92 | bitRange: "[1:1]" 93 | access: read-write 94 | PA2: 95 | description: "Pin A2" 96 | bitRange: "[2:2]" 97 | access: read-write 98 | PA3: 99 | description: "Pin A3" 100 | bitRange: "[3:3]" 101 | access: read-write 102 | PA4: 103 | description: "Pin A4" 104 | bitRange: "[4:4]" 105 | access: read-write 106 | PA5: 107 | description: "Pin A5" 108 | bitRange: "[5:5]" 109 | access: read-write 110 | PA6: 111 | description: "Pin A6" 112 | bitRange: "[6:6]" 113 | access: read-write 114 | PA7: 115 | description: "Pin A7" 116 | bitRange: "[7:7]" 117 | access: read-write 118 | PINA: 119 | _add: 120 | PA0: 121 | description: "Pin A0" 122 | bitRange: "[0:0]" 123 | access: read-write 124 | PA1: 125 | description: "Pin A1" 126 | bitRange: "[1:1]" 127 | access: read-write 128 | PA2: 129 | description: "Pin A2" 130 | bitRange: "[2:2]" 131 | access: read-write 132 | PA3: 133 | description: "Pin A3" 134 | bitRange: "[3:3]" 135 | access: read-write 136 | PA4: 137 | description: "Pin A4" 138 | bitRange: "[4:4]" 139 | access: read-write 140 | PA5: 141 | description: "Pin A5" 142 | bitRange: "[5:5]" 143 | access: read-write 144 | PA6: 145 | description: "Pin A6" 146 | bitRange: "[6:6]" 147 | access: read-write 148 | PA7: 149 | description: "Pin A7" 150 | bitRange: "[7:7]" 151 | access: read-write 152 | PORTA: 153 | _add: 154 | PA0: 155 | description: "Pin A0" 156 | bitRange: "[0:0]" 157 | access: read-write 158 | PA1: 159 | description: "Pin A1" 160 | bitRange: "[1:1]" 161 | access: read-write 162 | PA2: 163 | description: "Pin A2" 164 | bitRange: "[2:2]" 165 | access: read-write 166 | PA3: 167 | description: "Pin A3" 168 | bitRange: "[3:3]" 169 | access: read-write 170 | PA4: 171 | description: "Pin A4" 172 | bitRange: "[4:4]" 173 | access: read-write 174 | PA5: 175 | description: "Pin A5" 176 | bitRange: "[5:5]" 177 | access: read-write 178 | PA6: 179 | description: "Pin A6" 180 | bitRange: "[6:6]" 181 | access: read-write 182 | PA7: 183 | description: "Pin A7" 184 | bitRange: "[7:7]" 185 | access: read-write 186 | 187 | PORTB: 188 | DDRB: 189 | _add: 190 | PB0: 191 | description: "Pin B0" 192 | bitRange: "[0:0]" 193 | access: read-write 194 | PB1: 195 | description: "Pin B1" 196 | bitRange: "[1:1]" 197 | access: read-write 198 | PB2: 199 | description: "Pin B2" 200 | bitRange: "[2:2]" 201 | access: read-write 202 | PB3: 203 | description: "Pin B3" 204 | bitRange: "[3:3]" 205 | access: read-write 206 | PB4: 207 | description: "Pin B4" 208 | bitRange: "[4:4]" 209 | access: read-write 210 | PB5: 211 | description: "Pin B5" 212 | bitRange: "[5:5]" 213 | access: read-write 214 | PB6: 215 | description: "Pin B6" 216 | bitRange: "[6:6]" 217 | access: read-write 218 | PB7: 219 | description: "Pin B7" 220 | bitRange: "[7:7]" 221 | access: read-write 222 | PINB: 223 | _add: 224 | PB0: 225 | description: "Pin B0" 226 | bitRange: "[0:0]" 227 | access: read-write 228 | PB1: 229 | description: "Pin B1" 230 | bitRange: "[1:1]" 231 | access: read-write 232 | PB2: 233 | description: "Pin B2" 234 | bitRange: "[2:2]" 235 | access: read-write 236 | PB3: 237 | description: "Pin B3" 238 | bitRange: "[3:3]" 239 | access: read-write 240 | PB4: 241 | description: "Pin B4" 242 | bitRange: "[4:4]" 243 | access: read-write 244 | PB5: 245 | description: "Pin B5" 246 | bitRange: "[5:5]" 247 | access: read-write 248 | PB6: 249 | description: "Pin B6" 250 | bitRange: "[6:6]" 251 | access: read-write 252 | PB7: 253 | description: "Pin B7" 254 | bitRange: "[7:7]" 255 | access: read-write 256 | PORTB: 257 | _add: 258 | PB0: 259 | description: "Pin B0" 260 | bitRange: "[0:0]" 261 | access: read-write 262 | PB1: 263 | description: "Pin B1" 264 | bitRange: "[1:1]" 265 | access: read-write 266 | PB2: 267 | description: "Pin B2" 268 | bitRange: "[2:2]" 269 | access: read-write 270 | PB3: 271 | description: "Pin B3" 272 | bitRange: "[3:3]" 273 | access: read-write 274 | PB4: 275 | description: "Pin B4" 276 | bitRange: "[4:4]" 277 | access: read-write 278 | PB5: 279 | description: "Pin B5" 280 | bitRange: "[5:5]" 281 | access: read-write 282 | PB6: 283 | description: "Pin B6" 284 | bitRange: "[6:6]" 285 | access: read-write 286 | PB7: 287 | description: "Pin B7" 288 | bitRange: "[7:7]" 289 | access: read-write 290 | -------------------------------------------------------------------------------- /patch/attiny202.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - common/attiny-xmega/common.yaml 3 | - common/attiny-xmega/0-series.yaml 4 | -------------------------------------------------------------------------------- /patch/attiny204.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/attiny204.svd 2 | 3 | _include: 4 | - common/attiny-xmega/common.yaml 5 | - common/attiny-xmega/0-series.yaml 6 | -------------------------------------------------------------------------------- /patch/attiny212.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - common/attiny-xmega/common.yaml 3 | - common/attiny-xmega/1-series.yaml 4 | -------------------------------------------------------------------------------- /patch/attiny214.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - common/attiny-xmega/common.yaml 3 | - common/attiny-xmega/1-series.yaml 4 | -------------------------------------------------------------------------------- /patch/attiny2313-common.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/wdt.yaml" 5 | - "common/tiny/usi.yaml" 6 | 7 | - "timer/attiny2313-common.yaml" 8 | 9 | CPU: 10 | MCUCR: 11 | ISC?: 12 | _replace_enum: 13 | LOW: [0, "The low level of INTx generates an interrupt request"] 14 | TOGGLE: [1, "Any logical change on INTx generates an interrupt request"] 15 | FALLING: [2, "The falling edge of INTx generates an interrupt request"] 16 | RISING: [3, "The rising edge of INTx generates an interrupt request"] 17 | CLKPR: 18 | CLKPS: 19 | _replace_enum: 20 | PRESCALER_1: [0, "Prescaler Value 1"] 21 | PRESCALER_2: [1, "Prescaler Value 2"] 22 | PRESCALER_4: [2, "Prescaler Value 4"] 23 | PRESCALER_8: [3, "Prescaler Value 8"] 24 | PRESCALER_16: [4, "Prescaler Value 16"] 25 | PRESCALER_32: [5, "Prescaler Value 32"] 26 | PRESCALER_64: [6, "Prescaler Value 64"] 27 | PRESCALER_128: [7, "Prescaler Value 128"] 28 | PRESCALER_256: [8, "Prescaler Value 256"] 29 | 30 | PORTA: 31 | DDRA: 32 | _add: 33 | PA0: 34 | description: "Pin A0" 35 | bitRange: "[0:0]" 36 | access: read-write 37 | PA1: 38 | description: "Pin A1" 39 | bitRange: "[1:1]" 40 | access: read-write 41 | PA2: 42 | description: "Pin A2" 43 | bitRange: "[2:2]" 44 | access: read-write 45 | PINA: 46 | _add: 47 | PA0: 48 | description: "Pin A0" 49 | bitRange: "[0:0]" 50 | access: read-write 51 | PA1: 52 | description: "Pin A1" 53 | bitRange: "[1:1]" 54 | access: read-write 55 | PA2: 56 | description: "Pin A2" 57 | bitRange: "[2:2]" 58 | access: read-write 59 | PORTA: 60 | _add: 61 | PA0: 62 | description: "Pin A0" 63 | bitRange: "[0:0]" 64 | access: read-write 65 | PA1: 66 | description: "Pin A1" 67 | bitRange: "[1:1]" 68 | access: read-write 69 | PA2: 70 | description: "Pin A2" 71 | bitRange: "[2:2]" 72 | access: read-write 73 | 74 | PORTB: 75 | DDRB: 76 | _add: 77 | PB0: 78 | description: "Pin B0" 79 | bitRange: "[0:0]" 80 | access: read-write 81 | PB1: 82 | description: "Pin B1" 83 | bitRange: "[1:1]" 84 | access: read-write 85 | PB2: 86 | description: "Pin B2" 87 | bitRange: "[2:2]" 88 | access: read-write 89 | PB3: 90 | description: "Pin B3" 91 | bitRange: "[3:3]" 92 | access: read-write 93 | PB4: 94 | description: "Pin B4" 95 | bitRange: "[4:4]" 96 | access: read-write 97 | PB5: 98 | description: "Pin B5" 99 | bitRange: "[5:5]" 100 | access: read-write 101 | PB6: 102 | description: "Pin B6" 103 | bitRange: "[6:6]" 104 | access: read-write 105 | PB7: 106 | description: "Pin B7" 107 | bitRange: "[7:7]" 108 | access: read-write 109 | PINB: 110 | _add: 111 | PB0: 112 | description: "Pin B0" 113 | bitRange: "[0:0]" 114 | access: read-write 115 | PB1: 116 | description: "Pin B1" 117 | bitRange: "[1:1]" 118 | access: read-write 119 | PB2: 120 | description: "Pin B2" 121 | bitRange: "[2:2]" 122 | access: read-write 123 | PB3: 124 | description: "Pin B3" 125 | bitRange: "[3:3]" 126 | access: read-write 127 | PB4: 128 | description: "Pin B4" 129 | bitRange: "[4:4]" 130 | access: read-write 131 | PB5: 132 | description: "Pin B5" 133 | bitRange: "[5:5]" 134 | access: read-write 135 | PB6: 136 | description: "Pin B6" 137 | bitRange: "[6:6]" 138 | access: read-write 139 | PB7: 140 | description: "Pin B7" 141 | bitRange: "[7:7]" 142 | access: read-write 143 | PORTB: 144 | _add: 145 | PB0: 146 | description: "Pin B0" 147 | bitRange: "[0:0]" 148 | access: read-write 149 | PB1: 150 | description: "Pin B1" 151 | bitRange: "[1:1]" 152 | access: read-write 153 | PB2: 154 | description: "Pin B2" 155 | bitRange: "[2:2]" 156 | access: read-write 157 | PB3: 158 | description: "Pin B3" 159 | bitRange: "[3:3]" 160 | access: read-write 161 | PB4: 162 | description: "Pin B4" 163 | bitRange: "[4:4]" 164 | access: read-write 165 | PB5: 166 | description: "Pin B5" 167 | bitRange: "[5:5]" 168 | access: read-write 169 | PB6: 170 | description: "Pin B6" 171 | bitRange: "[6:6]" 172 | access: read-write 173 | PB7: 174 | description: "Pin B7" 175 | bitRange: "[7:7]" 176 | access: read-write 177 | 178 | PORTD: 179 | DDRD: 180 | _add: 181 | PD0: 182 | description: "Pin D0" 183 | bitRange: "[0:0]" 184 | access: read-write 185 | PD1: 186 | description: "Pin D1" 187 | bitRange: "[1:1]" 188 | access: read-write 189 | PD2: 190 | description: "Pin D2" 191 | bitRange: "[2:2]" 192 | access: read-write 193 | PD3: 194 | description: "Pin D3" 195 | bitRange: "[3:3]" 196 | access: read-write 197 | PD4: 198 | description: "Pin D4" 199 | bitRange: "[4:4]" 200 | access: read-write 201 | PD5: 202 | description: "Pin D5" 203 | bitRange: "[5:5]" 204 | access: read-write 205 | PD6: 206 | description: "Pin D6" 207 | bitRange: "[6:6]" 208 | access: read-write 209 | PIND: 210 | _add: 211 | PD0: 212 | description: "Pin D0" 213 | bitRange: "[0:0]" 214 | access: read-write 215 | PD1: 216 | description: "Pin D1" 217 | bitRange: "[1:1]" 218 | access: read-write 219 | PD2: 220 | description: "Pin D2" 221 | bitRange: "[2:2]" 222 | access: read-write 223 | PD3: 224 | description: "Pin D3" 225 | bitRange: "[3:3]" 226 | access: read-write 227 | PD4: 228 | description: "Pin D4" 229 | bitRange: "[4:4]" 230 | access: read-write 231 | PD5: 232 | description: "Pin D5" 233 | bitRange: "[5:5]" 234 | access: read-write 235 | PD6: 236 | description: "Pin D6" 237 | bitRange: "[6:6]" 238 | access: read-write 239 | PORTD: 240 | _add: 241 | PD0: 242 | description: "Pin D0" 243 | bitRange: "[0:0]" 244 | access: read-write 245 | PD1: 246 | description: "Pin D1" 247 | bitRange: "[1:1]" 248 | access: read-write 249 | PD2: 250 | description: "Pin D2" 251 | bitRange: "[2:2]" 252 | access: read-write 253 | PD3: 254 | description: "Pin D3" 255 | bitRange: "[3:3]" 256 | access: read-write 257 | PD4: 258 | description: "Pin D4" 259 | bitRange: "[4:4]" 260 | access: read-write 261 | PD5: 262 | description: "Pin D5" 263 | bitRange: "[5:5]" 264 | access: read-write 265 | PD6: 266 | description: "Pin D6" 267 | bitRange: "[6:6]" 268 | access: read-write 269 | -------------------------------------------------------------------------------- /patch/attiny2313.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "attiny2313-common.yaml" 3 | - "common/usart-single-attiny2313.yaml" 4 | -------------------------------------------------------------------------------- /patch/attiny2313a.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "attiny2313-common.yaml" 3 | - "common/usart-single-attiny2313a.yaml" 4 | -------------------------------------------------------------------------------- /patch/attiny26.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/wdt.yaml" 4 | - "common/tiny/usi.yaml" 5 | - "common/tiny/attinyx61a-ports.yaml" 6 | 7 | # All FUSEs are read-only from the CPU. 8 | FUSE: 9 | _modify: 10 | "*": 11 | access: read-only 12 | 13 | ADC: 14 | _modify: 15 | ADCSR: 16 | description: "ADC Control and Status Register" 17 | ADCSR: 18 | ADPS: 19 | _replace_enum: 20 | PRESCALER_2: [1, "Prescaler Value 2"] 21 | PRESCALER_4: [2, "Prescaler Value 4"] 22 | PRESCALER_8: [3, "Prescaler Value 8"] 23 | PRESCALER_16: [4, "Prescaler Value 16"] 24 | PRESCALER_32: [5, "Prescaler Value 32"] 25 | PRESCALER_64: [6, "Prescaler Value 64"] 26 | PRESCALER_128: [7, "Prescaler Value 128"] 27 | ADMUX: 28 | _modify: 29 | MUX: 30 | _write_constraint: enum 31 | REFS: 32 | _write_constraint: enum 33 | MUX: 34 | _replace_enum: 35 | ADC0: [0, "Single-ended Input ADC0"] 36 | ADC1: [1, "Single-ended Input ADC1"] 37 | ADC2: [2, "Single-ended Input ADC2"] 38 | ADC3: [3, "Single-ended Input ADC3"] 39 | ADC4: [4, "Single-ended Input ADC4"] 40 | ADC5: [5, "Single-ended Input ADC5"] 41 | ADC6: [6, "Single-ended Input ADC6"] 42 | ADC7: [7, "Single-ended Input ADC7"] 43 | ADC8: [8, "Single-ended Input ADC8"] 44 | ADC9: [9, "Single-ended Input ADC9"] 45 | ADC10: [10, "Single-ended Input ADC10"] 46 | 47 | ADC0_ADC1_20X: [11, "Differential Inputs Positive ADC0 Negative ADC1 20x Gain"] 48 | ADC0_ADC1_1X: [12, "Differential Inputs Positive ADC0 Negative ADC1 1x Gain"] 49 | ADC1_ADC1_20X: [13, "Differential Inputs Positive ADC1 Negative ADC1 20x Gain (for offset compensation)"] 50 | ADC2_ADC1_20X: [14, "Differential Inputs Positive ADC2 Negative ADC1 20x Gain"] 51 | ADC2_ADC1_1X: [15, "Differential Inputs Positive ADC2 Negative ADC1 1x Gain"] 52 | 53 | ADC2_ADC3_1X: [16, "Differential Inputs Positive ADC2 Negative ADC3 1x Gain"] 54 | ADC3_ADC3_20X: [17, "Differential Inputs Positive ADC3 Negative ADC3 20x Gain (for offset compensation)"] 55 | ADC4_ADC3_20X: [18, "Differential Inputs Positive ADC4 Negative ADC3 20x Gain"] 56 | ADC4_ADC3_1X: [19, "Differential Inputs Positive ADC4 Negative ADC3 1x Gain"] 57 | 58 | ADC4_ADC5_20X: [20, "Differential Inputs Positive ADC4 Negative ADC5 20x Gain"] 59 | ADC4_ADC5_1X: [21, "Differential Inputs Positive ADC4 Negative ADC5 1x Gain"] 60 | ADC5_ADC5_20X: [22, "Differential Inputs Positive ADC5 Negative ADC5 20x Gain (for offset compensation)"] 61 | ADC6_ADC5_20X: [23, "Differential Inputs Positive ADC6 Negative ADC5 20x Gain"] 62 | ADC6_ADC5_1X: [24, "Differential Inputs Positive ADC6 Negative ADC5 1x Gain"] 63 | 64 | ADC8_ADC9_20X: [25, "Differential Inputs Positive ADC8 Negative ADC9 20x Gain"] 65 | ADC8_ADC9_1X: [26, "Differential Inputs Positive ADC8 Negative ADC9 1x Gain"] 66 | ADC9_ADC9_20X: [27, "Differential Inputs Positive ADC9 Negative ADC9 20x Gain (for offset compensation)"] 67 | ADC10_ADC9_20X: [28, "Differential Inputs Positive ADC10 Negative ADC9 20x Gain"] 68 | ADC10_ADC9_1X: [29, "Differential Inputs Positive ADC10 Negative ADC9 1x Gain"] 69 | 70 | ADC_VBG: [30, "Internal 1.18V Reference (VBG)"] 71 | ADC_GND: [31, "0V (GND)"] 72 | REFS: 73 | _replace_enum: 74 | VCC: [0, "Vcc used as Voltage Reference, disconnected from Aref"] 75 | AREF: [1, "External Voltage Reference at AREF pin, Internal Voltage Reference turned off"] 76 | INTERNAL: [2, "Internal 2.56V Voltage Reference without external bypass"] 77 | INTERNAL_BYPASS: [3, "Internal 2.56V Voltage Reference with external bypass capacitor at AREF pin"] 78 | -------------------------------------------------------------------------------- /patch/attiny261a.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/attiny261a.svd 2 | 3 | _include: 4 | - "common/ac.yaml" 5 | - "common/tiny/attinyx61a-adc.yaml" 6 | - "common/tiny/attinyx61a-ports.yaml" 7 | - "common/tiny/usi.yaml" 8 | - "common/wdt.yaml" 9 | - "timer/attiny861.yaml" 10 | - "common/tiny/attinyx61a-timers.yaml" 11 | 12 | # All FUSEs are read-only from the CPU. 13 | FUSE: 14 | _modify: 15 | "*": 16 | access: read-only 17 | -------------------------------------------------------------------------------- /patch/attiny402.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - common/attiny-xmega/common.yaml 3 | - common/attiny-xmega/0-series.yaml 4 | -------------------------------------------------------------------------------- /patch/attiny404.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - common/attiny-xmega/common.yaml 3 | - common/attiny-xmega/0-series.yaml 4 | -------------------------------------------------------------------------------- /patch/attiny412.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - common/attiny-xmega/common.yaml 3 | - common/attiny-xmega/1-series.yaml 4 | -------------------------------------------------------------------------------- /patch/attiny414.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - common/attiny-xmega/common.yaml 3 | - common/attiny-xmega/1-series.yaml 4 | -------------------------------------------------------------------------------- /patch/attiny416.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - common/attiny-xmega/common.yaml 3 | - common/attiny-xmega/1-series.yaml 4 | -------------------------------------------------------------------------------- /patch/attiny461a.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/attiny461a.svd 2 | 3 | _include: 4 | - "common/ac.yaml" 5 | - "common/tiny/attinyx61a-adc.yaml" 6 | - "common/tiny/attinyx61a-ports.yaml" 7 | - "common/tiny/usi.yaml" 8 | - "common/wdt.yaml" 9 | - "timer/attiny861.yaml" 10 | - "common/tiny/attinyx61a-timers.yaml" 11 | 12 | # All FUSEs are read-only from the CPU. 13 | FUSE: 14 | _modify: 15 | "*": 16 | access: read-only 17 | -------------------------------------------------------------------------------- /patch/attiny804.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/attiny804.svd 2 | 3 | _include: 4 | - common/attiny-xmega/common.yaml 5 | - common/attiny-xmega/0-series.yaml 6 | -------------------------------------------------------------------------------- /patch/attiny816.yaml: -------------------------------------------------------------------------------- 1 | CRCSCAN: 2 | CTRLB: 3 | SRC: 4 | _replace_enum: 5 | FLASH: [0, "CRC on entire flash"] 6 | BOOTAPP: [1, "CRC on boot and appl section of flash"] 7 | BOOT: [2, "CRC on boot section of flash"] 8 | MODE: 9 | _replace_enum: 10 | PRIORITY: [0, "Priority to flash"] 11 | 12 | NVMCTRL: 13 | CTRLA: 14 | CMD: 15 | _replace_enum: 16 | NONE: [0, "No command"] 17 | WP: [1, "Write page"] 18 | ER: [2, "Erase page"] 19 | ERWP: [3, "Erase and write page"] 20 | PBC: [4, "Page buffer clear"] 21 | CHER: [5, "Chip erase"] 22 | EEER: [6, "EEPROM erase"] 23 | WFU: [7, "Write fuse (PDI only)"] 24 | 25 | SLPCTRL: 26 | CTRLA: 27 | SMODE: 28 | _replace_enum: 29 | IDLE: [0, "Idle mode"] 30 | STANDBY: [1, "Standby Mode"] 31 | PDOWN: [2, "Power-down Mode"] 32 | 33 | TCD0: 34 | EVCTRL?: 35 | CFG: 36 | _replace_enum: 37 | NEITHER: [0, "Neither Filter nor Asynchronous Event is enabled"] 38 | FILTERON: [1, "Input Capture Noise Cancellation Filter enabled"] 39 | ASYNCON: [2, "Asynchronous Event output qualification enabled"] 40 | 41 | USART0: 42 | STATUS: 43 | _modify: 44 | WFB: 45 | access: write-only 46 | -------------------------------------------------------------------------------- /patch/attiny828.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/spi.yaml" 5 | - "common/wdt.yaml" 6 | 7 | - "timer/attiny828.yaml" 8 | 9 | ADC: 10 | ADCSRA: 11 | ADPS: 12 | _replace_enum: 13 | PRESCALER_2: [1, "Prescaler Value 2"] 14 | PRESCALER_4: [2, "Prescaler Value 4"] 15 | PRESCALER_8: [3, "Prescaler Value 8"] 16 | PRESCALER_16: [4, "Prescaler Value 16"] 17 | PRESCALER_32: [5, "Prescaler Value 32"] 18 | PRESCALER_64: [6, "Prescaler Value 64"] 19 | PRESCALER_128: [7, "Prescaler Value 128"] 20 | ADCSRB: 21 | ADTS: 22 | _replace_enum: 23 | FREE_RUNNING: [0, "Free Running Mode"] 24 | ANALOG_COMPARATOR: [1, "Analog Comparator"] 25 | EXTERNAL_INTERRUPT: [2, "External Interrupt Request 0"] 26 | TIMER0_COMPARE_MATCH_A: [3, "Timer/Counter0 Compare Match A"] 27 | TIMER0_OVERFLOW: [4, "Timer/Counter0 Overflow"] 28 | TIMER1_COMPARE_MATCH_B: [5, "Timer/Counter1 Compare Match B"] 29 | TIMER1_OVERFLOW: [6, "Timer/Counter1 Overflow"] 30 | TIMER1_CAPTURE_EVENT: [7, "Timer/Counter1 Capture Event"] 31 | ADMUXB: 32 | REFS: 33 | _replace_enum: 34 | VCC: [0, "Vcc used as analog reference"] 35 | INTERNAL: [1, "Internal 1.1V Voltage Reference"] 36 | 37 | CPU: 38 | SMCR: 39 | SM: 40 | _replace_enum: 41 | IDLE: [ 0, "Idle" ] 42 | ADC: [ 1, "ADC Noise Reduction" ] 43 | PDOWN: [ 2, "Power Down" ] 44 | 45 | # Remove EEAR register duplicate declaration 46 | EEPROM: 47 | _delete: 48 | - "EEAR" 49 | 50 | EXINT: 51 | EICRA: 52 | ISC0: 53 | _replace_enum: 54 | LOW: [0, "The low level of INTx generates an interrupt request"] 55 | TOGGLE: [1, "Any logical change on INTx generates an interrupt request"] 56 | FALLING: [2, "The falling edge of INTx generates an interrupt request"] 57 | RISING: [3, "The rising edge of INTx generates an interrupt request"] 58 | 59 | # ATtiny828 has only one USART peripheral and it's not is not compatible with common USARTn pattern. 60 | USART: 61 | UCSRA: 62 | _modify: 63 | UPE: 64 | access: read-only 65 | DOR: 66 | access: read-only 67 | FE: 68 | access: read-only 69 | UDRE: 70 | access: read-only 71 | TXC: 72 | description: "USART Transmit Complete" 73 | RXC: 74 | access: read-only 75 | UCSRB: 76 | _modify: 77 | RXB8: 78 | access: read-only 79 | UCSRC: 80 | UMSEL: 81 | _replace_enum: 82 | USART_ASYNC: [0, "Asynchronous USART"] 83 | USART_SYNC: [1, "Synchronous USART"] 84 | # The following option is missing from atdf file, but it's present in the datasheet 85 | SPI_MASTER: [3, "Master SPI (MSPIM)"] 86 | UPM: 87 | _replace_enum: 88 | DISABLED: [0, "Disabled"] 89 | PARITY_EVEN: [2, "Enabled, Even Parity"] 90 | PARITY_ODD: [3, "Enabled, Odd Parity"] 91 | USBS: 92 | _replace_enum: 93 | STOP1: [0, "1-bit"] 94 | STOP2: [1, "2-bit"] 95 | UCSZ: 96 | _replace_enum: 97 | CHR5: [0, "Character Size: 5 bit"] 98 | CHR6: [1, "Character Size: 6 bit"] 99 | CHR7: [2, "Character Size: 7 bit"] 100 | CHR8: [3, "Character Size: 8 bit"] 101 | UCPOL: 102 | _replace_enum: 103 | RISING_EDGE: [0, "Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge"] 104 | FALLING_EDGE: [1, "Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge"] 105 | -------------------------------------------------------------------------------- /patch/attiny84.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/wdt.yaml" 5 | 6 | - "common/tiny/exint.yaml" 7 | - "common/tiny/usi.yaml" 8 | 9 | - "timer/attiny84.yaml" 10 | 11 | AC: 12 | _modify: 13 | DIDR0: 14 | description: "Digital Input Disable Register 0" 15 | DIDR0: 16 | _delete: 17 | - ADC0D 18 | _modify: 19 | ADC1D: 20 | description: "ADC1 (AIN0) Digital input buffer disable" 21 | _add: 22 | ADC2D: 23 | description: "ADC2 (AIN1) Digital input buffer disable" 24 | bitOffset: 2 25 | bitWidth: 1 26 | access: read-write 27 | ADC: 28 | ADCSRA: 29 | ADPS: 30 | _replace_enum: 31 | PRESCALER_2: [1, "Prescaler Value 2"] 32 | PRESCALER_4: [2, "Prescaler Value 4"] 33 | PRESCALER_8: [3, "Prescaler Value 8"] 34 | PRESCALER_16: [4, "Prescaler Value 16"] 35 | PRESCALER_32: [5, "Prescaler Value 32"] 36 | PRESCALER_64: [6, "Prescaler Value 64"] 37 | PRESCALER_128: [7, "Prescaler Value 128"] 38 | ADCSRB: 39 | ADTS: 40 | _replace_enum: 41 | FREE: [0, "Free Running mode"] 42 | AC: [1, "Analog Comparator"] 43 | INT0: [2, "External Interrupt Request 0"] 44 | TC0_CMA: [3, "Timer/Counter0 Compare Match A"] 45 | TC0_OVF: [4, "Timer/Counter0 Overflow"] 46 | TC0_CMB: [5, "Timer/Counter0 Compare Match B"] 47 | PCIR: [6, "Pin Change Interrupt Request"] 48 | ADMUX: 49 | _add: 50 | MUX: 51 | description: "Analog Channel and Gain Selection Bits" 52 | bitOffset: 0 53 | bitWidth: 6 54 | access: read-write 55 | REFS: 56 | description: "Reference Selection Bits" 57 | bitOffset: 6 58 | bitWidth: 2 59 | access: read-write 60 | MUX: 61 | ADC0: [0, "Single-ended Input ADC0"] 62 | ADC1: [1, "Single-ended Input ADC1"] 63 | ADC2: [2, "Single-ended Input ADC2"] 64 | ADC3: [3, "Single-ended Input ADC3"] 65 | ADC4: [4, "Single-ended Input ADC4"] 66 | ADC5: [5, "Single-ended Input ADC5"] 67 | ADC6: [6, "Single-ended Input ADC6"] 68 | ADC7: [7, "Single-ended Input ADC7"] 69 | 70 | ADC_GND: [32, "0V (GND)"] 71 | ADC_VBG: [33, "Internal Reference (VBG)"] 72 | TEMPSENS: [34, "Temperature sensor"] 73 | 74 | ADC0_ADC0_20X: [35, "Differential Inputs Positive ADC0 Negative ADC0 20x Gain"] 75 | ADC0_ADC1_1X: [8, "Differential Inputs Positive ADC0 Negative ADC1 1x Gain"] 76 | ADC0_ADC1_20X: [9, "Differential Inputs Postive ADC0 Negative ADC1 20x Gain"] 77 | ADC0_ADC3_1X: [10, "Differential Inputs Positive ADC0 Negative ADC3 1x Gain"] 78 | ADC0_ADC3_20X: [11, "Differential Inputs Positive ADC0 Negative ADC3 20x Gain"] 79 | 80 | ADC1_ADC0_1X: [40, "Differential Inputs Positive ADC1 Negative ADC0 1x Gain"] 81 | ADC1_ADC0_20X: [41, "Differential Inputs Positive ADC1 Negative ADC0 20x Gain"] 82 | ADC1_ADC2_1X: [12, "Differential Inputs Positive ADC1 Negative ADC2 1x Gain"] 83 | ADC1_ADC2_20X: [13, "Differential Inputs Positive ADC1 Negative ADC2 20x Gain"] 84 | ADC1_ADC3_1X: [14, "Differential Inputs Positive ADC1 Negative ADC3 1x Gain"] 85 | ADC1_ADC3_20X: [15, "Differential Inputs Positive ADC1 Negative ADC3 20x Gain"] 86 | 87 | ADC2_ADC1_1X: [44, "Differential Inputs Positive ADC2 Negative ADC2 1x Gain"] 88 | ADC2_ADC1_20X: [45, "Differential Inputs Positive ADC2 Negative ADC2 20x Gain"] 89 | ADC2_ADC3_1X: [16, "Differential Inputs Positive ADC2 Negative ADC3 1x Gain"] 90 | ADC2_ADC3_20X: [17, "Differential Inputs Positive ADC2 Negative ADC3 20x Gain"] 91 | 92 | ADC3_ADC0_1X: [42, "Differential Inputs Positive ADC3 Negative ADC0 1x Gain"] 93 | ADC3_ADC0_20X: [43, "Differential Inputs Positive ADC3 Negative ADC0 20x Gain"] 94 | ADC3_ADC1_1X: [46, "Differential Inputs Positive ADC3 Negative ADC1 1x Gain"] 95 | ADC3_ADC1_20X: [47, "Differential Inputs Positive ADC3 Negative ADC1 20x Gain"] 96 | ADC3_ADC2_1X: [48, "Differential Inputs Positive ADC3 Negative ADC2 1x Gain"] 97 | ADC3_ADC2_20X: [49, "Differential Inputs Positive ADC3 Negative ADC2 20x Gain"] 98 | ADC3_ADC3_1X: [36, "Differential Inputs Positive ADC3 Negative ADC3 1x Gain"] 99 | ADC3_ADC3_20X: [37, "Differential Inputs Positive ADC3 Negative ADC3 20x Gain"] 100 | ADC3_ADC4_1X: [18, "Differential Inputs Positive ADC4 Negative ADC0 1x Gain"] 101 | ADC3_ADC4_20X: [19, "Differential Inputs Positive ADC4 Negative ADC0 20x Gain"] 102 | ADC3_ADC5_1X: [20, "Differential Inputs Positive ADC5 Negative ADC1 1x Gain"] 103 | ADC3_ADC5_20X: [21, "Differential Inputs Positive ADC5 Negative ADC1 20x Gain"] 104 | ADC3_ADC6_1X: [22, "Differential Inputs Positive ADC6 Negative ADC2 1x Gain"] 105 | ADC3_ADC6_20X: [23, "Differential Inputs Positive ADC6 Negative ADC2 20x Gain"] 106 | ADC3_ADC7_1X: [24, "Differential Inputs Positive ADC7 Negative ADC3 1x Gain"] 107 | ADC3_ADC7_20X: [25, "Differential Inputs Positive ADC7 Negative ADC3 20x Gain"] 108 | 109 | ADC4_ADC3_1X: [50, "Differential Inputs Positive ADC4 Negative ADC3 1x Gain"] 110 | ADC4_ADC3_20X: [51, "Differential Inputs Positive ADC4 Negative ADC3 20x Gain"] 111 | ADC4_ADC5_1X: [26, "Differential Inputs Positive ADC4 Negative ADC5 1x Gain"] 112 | ADC4_ADC5_20X: [27, "Differential Inputs Positive ADC4 Negative ADC5 20x Gain"] 113 | 114 | ADC5_ADC3_1X: [52, "Differential Inputs Positive ADC5 Negative ADC3 1x Gain"] 115 | ADC5_ADC3_20X: [53, "Differential Inputs Positive ADC5 Negative ADC3 20x Gain"] 116 | ADC5_ADC4_1X: [58, "Differential Inputs Positive ADC5 Negative ADC4 1x Gain"] 117 | ADC5_ADC4_20X: [59, "Differential Inputs Positive ADC5 Negative ADC4 20x Gain"] 118 | ADC5_ADC6_1X: [28, "Differential Inputs Positive ADC5 Negative ADC6 1x Gain"] 119 | ADC5_ADC6_20X: [29, "Differential Inputs Positive ADC5 Negative ADC6 20x Gain"] 120 | 121 | ADC6_ADC3_1X: [54, "Differential Inputs Positive ADC6 Negative ADC3 1x Gain"] 122 | ADC6_ADC3_20X: [55, "Differential Inputs Positive ADC6 Negative ADC3 20x Gain"] 123 | ADC6_ADC5_1X: [60, "Differential Inputs Positive ADC6 Negative ADC5 1x Gain"] 124 | ADC6_ADC5_20X: [61, "Differential Inputs Positive ADC6 Negative ADC5 20x Gain"] 125 | ADC6_ADC7_1X: [30, "Differential Inputs Positive ADC6 Negative ADC7 1x Gain"] 126 | ADC6_ADC7_20X: [31, "Differential Inputs Positive ADC6 Negative ADC7 20x Gain"] 127 | 128 | ADC7_ADC3_1X: [56, "Differential Inputs Positive ADC7 Negative ADC3 1x Gain"] 129 | ADC7_ADC3_20X: [57, "Differential Inputs Positive ADC7 Negative ADC3 20x Gain"] 130 | ADC7_ADC6_1X: [62, "Differential Inputs Positive ADC7 Negative ADC6 1x Gain"] 131 | ADC7_ADC6_20X: [63, "Differential Inputs Positive ADC7 Negative ADC6 20x Gain"] 132 | ADC7_ADC7_1X: [38, "Differential Inputs Positive ADC7 Negative ADC7 1x Gain"] 133 | ADC7_ADC7_20X: [39, "Differential Inputs Positive ADC7 Negative ADC7 20x Gain"] 134 | REFS: 135 | VCC: [0, "Vcc used as Voltage Reference, disconnected from Aref"] 136 | AREF: [1, "External Voltage Reference at AREF pin, Internal Voltage Reference turned off"] 137 | INTERNAL: [2, "Internal 1.1V Voltage Reference"] 138 | CPU: 139 | CLKPR: 140 | CLKPS: 141 | _replace_enum: 142 | PRESCALER_1: [0, "Prescaler Value 1"] 143 | PRESCALER_2: [1, "Prescaler Value 2"] 144 | PRESCALER_4: [2, "Prescaler Value 4"] 145 | PRESCALER_8: [3, "Prescaler Value 8"] 146 | PRESCALER_16: [4, "Prescaler Value 16"] 147 | PRESCALER_32: [5, "Prescaler Value 32"] 148 | PRESCALER_64: [6, "Prescaler Value 64"] 149 | PRESCALER_128: [7, "Prescaler Value 128"] 150 | PRESCALER_256: [8, "Prescaler Value 256"] 151 | MCUCR: 152 | _add: 153 | BODS: 154 | description: "BOD Sleep (available on some devices)" 155 | bitOffset: 7 156 | bitWidth: 1 157 | access: read-write 158 | BODSE: 159 | description: "BOD Sleep Enable (available on some devices)" 160 | bitOffset: 2 161 | bitWidth: 1 162 | access: read-write 163 | 164 | PORTA: 165 | DDRA: 166 | _add: 167 | PA0: 168 | description: "Pin A0" 169 | bitRange: "[0:0]" 170 | access: read-write 171 | PA1: 172 | description: "Pin A1" 173 | bitRange: "[1:1]" 174 | access: read-write 175 | PA2: 176 | description: "Pin A2" 177 | bitRange: "[2:2]" 178 | access: read-write 179 | PA3: 180 | description: "Pin A3" 181 | bitRange: "[3:3]" 182 | access: read-write 183 | PA4: 184 | description: "Pin A4" 185 | bitRange: "[4:4]" 186 | access: read-write 187 | PA5: 188 | description: "Pin A5" 189 | bitRange: "[5:5]" 190 | access: read-write 191 | PA6: 192 | description: "Pin A6" 193 | bitRange: "[6:6]" 194 | access: read-write 195 | PA7: 196 | description: "Pin A7" 197 | bitRange: "[7:7]" 198 | access: read-write 199 | PINA: 200 | _add: 201 | PA0: 202 | description: "Pin A0" 203 | bitRange: "[0:0]" 204 | access: read-write 205 | PA1: 206 | description: "Pin A1" 207 | bitRange: "[1:1]" 208 | access: read-write 209 | PA2: 210 | description: "Pin A2" 211 | bitRange: "[2:2]" 212 | access: read-write 213 | PA3: 214 | description: "Pin A3" 215 | bitRange: "[3:3]" 216 | access: read-write 217 | PA4: 218 | description: "Pin A4" 219 | bitRange: "[4:4]" 220 | access: read-write 221 | PA5: 222 | description: "Pin A5" 223 | bitRange: "[5:5]" 224 | access: read-write 225 | PA6: 226 | description: "Pin A6" 227 | bitRange: "[6:6]" 228 | access: read-write 229 | PA7: 230 | description: "Pin A7" 231 | bitRange: "[7:7]" 232 | access: read-write 233 | PORTA: 234 | _add: 235 | PA0: 236 | description: "Pin A0" 237 | bitRange: "[0:0]" 238 | access: read-write 239 | PA1: 240 | description: "Pin A1" 241 | bitRange: "[1:1]" 242 | access: read-write 243 | PA2: 244 | description: "Pin A2" 245 | bitRange: "[2:2]" 246 | access: read-write 247 | PA3: 248 | description: "Pin A3" 249 | bitRange: "[3:3]" 250 | access: read-write 251 | PA4: 252 | description: "Pin A4" 253 | bitRange: "[4:4]" 254 | access: read-write 255 | PA5: 256 | description: "Pin A5" 257 | bitRange: "[5:5]" 258 | access: read-write 259 | PA6: 260 | description: "Pin A6" 261 | bitRange: "[6:6]" 262 | access: read-write 263 | PA7: 264 | description: "Pin A7" 265 | bitRange: "[7:7]" 266 | access: read-write 267 | 268 | PORTB: 269 | DDRB: 270 | _add: 271 | PB0: 272 | description: "Pin B0" 273 | bitRange: "[0:0]" 274 | access: read-write 275 | PB1: 276 | description: "Pin B1" 277 | bitRange: "[1:1]" 278 | access: read-write 279 | PB2: 280 | description: "Pin B2" 281 | bitRange: "[2:2]" 282 | access: read-write 283 | PB3: 284 | description: "Pin B3" 285 | bitRange: "[3:3]" 286 | access: read-write 287 | PINB: 288 | _add: 289 | PB0: 290 | description: "Pin B0" 291 | bitRange: "[0:0]" 292 | access: read-write 293 | PB1: 294 | description: "Pin B1" 295 | bitRange: "[1:1]" 296 | access: read-write 297 | PB2: 298 | description: "Pin B2" 299 | bitRange: "[2:2]" 300 | access: read-write 301 | PB3: 302 | description: "Pin B3" 303 | bitRange: "[3:3]" 304 | access: read-write 305 | PORTB: 306 | _add: 307 | PB0: 308 | description: "Pin B0" 309 | bitRange: "[0:0]" 310 | access: read-write 311 | PB1: 312 | description: "Pin B1" 313 | bitRange: "[1:1]" 314 | access: read-write 315 | PB2: 316 | description: "Pin B2" 317 | bitRange: "[2:2]" 318 | access: read-write 319 | PB3: 320 | description: "Pin B3" 321 | bitRange: "[3:3]" 322 | access: read-write 323 | -------------------------------------------------------------------------------- /patch/attiny841.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/spi.yaml" 4 | - "common/usart.yaml" 5 | - "common/wdt.yaml" 6 | 7 | - "timer/attiny841.yaml" 8 | 9 | ADC: 10 | ADCSRA: 11 | ADPS: 12 | _replace_enum: 13 | PRESCALER_2: [1, "Prescaler Value 2"] 14 | PRESCALER_4: [2, "Prescaler Value 4"] 15 | PRESCALER_8: [3, "Prescaler Value 8"] 16 | PRESCALER_16: [4, "Prescaler Value 16"] 17 | PRESCALER_32: [5, "Prescaler Value 32"] 18 | PRESCALER_64: [6, "Prescaler Value 64"] 19 | PRESCALER_128: [7, "Prescaler Value 128"] 20 | ADMUXB: 21 | REFS: 22 | _replace_enum: 23 | VCC: [0, "Vcc"] 24 | INTERNAL_1: [1, "Internal 1.1V Voltage Reference with AREF disconnected"] 25 | INTERNAL_2: [2, "Internal 2.2V Voltage Reference with AREF disconnected"] 26 | INTERNAL_4: [3, "Internal 4.096V Voltage Reference with AREF disconnected"] 27 | AREF: [4, "AREF with internal reference off"] 28 | AREF_INTERNAL_1: [5, "Internal 1.1V Voltage Reference with external capacitor at AREF pin"] 29 | AREF_INTERNAL_2: [6, "Internal 2.2V Voltage Reference with external capacitor at AREF pin"] 30 | AREF_INTERNAL_4: [7, "Internal 4.096V Voltage Reference with external capacitor at AREF pin"] 31 | 32 | # While this chip does have a TWI peripheral, it only performs as a 33 | # slave, so it doesn't have many of the fields that the common peripheral 34 | # does, like TWWC, TWAMR, and TWPS 35 | TWI*: 36 | TWSCRB: 37 | TWAA: 38 | _replace_enum: 39 | SEND_ACK: [0, "Send ACK (timing depends on `TWSME`)"] 40 | SEND_NACK: [1, "Send NACK (timing depends on `TWSME`)"] 41 | -------------------------------------------------------------------------------- /patch/attiny84a.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/eeprom.yaml" 3 | 4 | AC: 5 | _modify: 6 | DIDR0: 7 | description: "Digital Input Disable Register" 8 | ADC: 9 | ADCSRA: 10 | ADPS: 11 | _replace_enum: 12 | PRESCALER_2: [1, "Prescaler Value 2"] 13 | PRESCALER_4: [2, "Prescaler Value 4"] 14 | PRESCALER_8: [3, "Prescaler Value 8"] 15 | PRESCALER_16: [4, "Prescaler Value 16"] 16 | PRESCALER_32: [5, "Prescaler Value 32"] 17 | PRESCALER_64: [6, "Prescaler Value 64"] 18 | PRESCALER_128: [7, "Prescaler Value 128"] 19 | ADMUX: 20 | MUX: 21 | ADC0: [0, "Single-ended Input ADC0"] 22 | ADC1: [1, "Single-ended Input ADC1"] 23 | ADC2: [2, "Single-ended Input ADC2"] 24 | ADC3: [3, "Single-ended Input ADC3"] 25 | ADC4: [4, "Single-ended Input ADC4"] 26 | ADC5: [5, "Single-ended Input ADC5"] 27 | ADC6: [6, "Single-ended Input ADC6"] 28 | ADC7: [7, "Single-ended Input ADC7"] 29 | 30 | ADC_GND: [32, "0V (GND)"] 31 | ADC_VBG: [33, "Internal Reference (VBG)"] 32 | TEMPSENS: [34, "Temperature sensor"] 33 | REFS: 34 | _replace_enum: 35 | VCC: [0, "VCC used as analog reference, disconnected from PA0 (AREF)"] 36 | AREF: [1, "External voltage reference at PA0 (AREF) pin, internal reference turned off"] 37 | INTERNAL: [2, "Internal 1.1V voltage reference"] 38 | 39 | CPU: 40 | CLKPR: 41 | CLKPS: 42 | _replace_enum: 43 | PRESCALER_1: [0, "Prescaler Value 1"] 44 | PRESCALER_2: [1, "Prescaler Value 2"] 45 | PRESCALER_4: [2, "Prescaler Value 4"] 46 | PRESCALER_8: [3, "Prescaler Value 8"] 47 | PRESCALER_16: [4, "Prescaler Value 16"] 48 | PRESCALER_32: [5, "Prescaler Value 32"] 49 | PRESCALER_64: [6, "Prescaler Value 64"] 50 | PRESCALER_128: [7, "Prescaler Value 128"] 51 | PRESCALER_256: [8, "Prescaler Value 256"] 52 | -------------------------------------------------------------------------------- /patch/attiny85.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/wdt.yaml" 5 | 6 | - "common/tiny/exint.yaml" 7 | - "common/tiny/usi.yaml" 8 | 9 | - "timer/attiny85.yaml" 10 | 11 | AC: 12 | _modify: 13 | DIDR0: 14 | description: "Digital Input Disable Register 0" 15 | ADC: 16 | _modify: 17 | ADCSRA: 18 | description: "ADC Control and Status Register A" 19 | ADCSRA: 20 | ADPS: 21 | _replace_enum: 22 | PRESCALER_2: [1, "Prescaler Value 2"] 23 | PRESCALER_4: [2, "Prescaler Value 4"] 24 | PRESCALER_8: [3, "Prescaler Value 8"] 25 | PRESCALER_16: [4, "Prescaler Value 16"] 26 | PRESCALER_32: [5, "Prescaler Value 32"] 27 | PRESCALER_64: [6, "Prescaler Value 64"] 28 | PRESCALER_128: [7, "Prescaler Value 128"] 29 | ADCSRB: 30 | ADTS: 31 | _replace_enum: 32 | FREE: [0, "Free Running mode"] 33 | AC: [1, "Analog Comparator"] 34 | INT0: [2, "External Interrupt Request 0"] 35 | TC0_CMA: [3, "Timer/Counter0 Compare Match A"] 36 | TC0_OVF: [4, "Timer/Counter0 Overflow"] 37 | TC0_CMB: [5, "Timer/Counter0 Compare Match B"] 38 | PCIR: [6, "Pin Change Interrupt Request"] 39 | ADMUX: 40 | _modify: 41 | MUX: 42 | _write_constraint: enum 43 | REFS: 44 | _write_constraint: enum 45 | MUX: 46 | _replace_enum: 47 | ADC0: [0, "Single-ended Input ADC0"] 48 | ADC1: [1, "Single-ended Input ADC1"] 49 | ADC2: [2, "Single-ended Input ADC2"] 50 | ADC3: [3, "Single-ended Input ADC3"] 51 | ADC2_ADC2_1X: [4, "Differential Inputs Positive ADC2 Negative ADC2 1x Gain"] 52 | ADC2_ADC2_20X: [5, "Differential Inputs Positive ADC2 Negative ADC2 20x Gain"] 53 | ADC2_ADC3_1X: [6, "Differential Inputs Positive ADC2 Negative ADC3 1x Gain"] 54 | ADC2_ADC3_20X: [7, "Differential Inputs Positive ADC2 Negative ADC3 20x Gain"] 55 | ADC0_ADC0_1X: [8, "Differential Inputs Positive ADC0 Negative ADC0 1x Gain"] 56 | ADC0_ADC0_20X: [9, "Differential Inputs Positive ADC0 Negative ADC0 20x Gain"] 57 | ADC0_ADC1_1X: [10, "Differential Inputs Positive ADC0 Negative ADC1 1x Gain"] 58 | ADC0_ADC1_20X: [11, "Differential Inputs Positive ADC0 Negative ADC1 20x Gain"] 59 | ADC_VBG: [12, "Internal Reference (VBG)"] 60 | ADC_GND: [13, "0V (GND)"] 61 | TEMPSENS: [15, "Temperature sensor"] 62 | REFS: 63 | _replace_enum: 64 | VCC: [0, "Vcc used as Voltage Reference, disconnected from Aref"] 65 | AREF: [1, "External Voltage Reference at AREF pin, Internal Voltage Reference turned off"] 66 | INTERNAL: [2, "Internal Voltage Reference (1.1V when REFS2 is cleared, 2.56V when REFS2 is set) without external bypass"] 67 | INTERNAL_BYPASS: [3, "Internal 2.56V Voltage Reference with external bypass capacitor at AREF pin (REFS2 must be set)"] 68 | CPU: 69 | CLKPR: 70 | CLKPS: 71 | _replace_enum: 72 | PRESCALER_1: [0, "Prescaler Value 1"] 73 | PRESCALER_2: [1, "Prescaler Value 2"] 74 | PRESCALER_4: [2, "Prescaler Value 4"] 75 | PRESCALER_8: [3, "Prescaler Value 8"] 76 | PRESCALER_16: [4, "Prescaler Value 16"] 77 | PRESCALER_32: [5, "Prescaler Value 32"] 78 | PRESCALER_64: [6, "Prescaler Value 64"] 79 | PRESCALER_128: [7, "Prescaler Value 128"] 80 | PRESCALER_256: [8, "Prescaler Value 256"] 81 | MCUCR: 82 | _delete: 83 | - ISC? 84 | _add: 85 | BODS: 86 | description: "BOD Sleep (available on some devices)" 87 | bitOffset: 7 88 | bitWidth: 1 89 | access: read-write 90 | BODSE: 91 | description: "BOD Sleep Enable (available on some devices)" 92 | bitOffset: 2 93 | bitWidth: 1 94 | access: read-write 95 | PLLCSR: 96 | _modify: 97 | PLOCK: 98 | access: read-only 99 | EXINT: 100 | # This doesn't work: 101 | # _modify: 102 | # PCMSK: 103 | # _write_constraint: [0, 63] 104 | PCMSK: 105 | _add: 106 | PCINT0: 107 | description: Enable pin change interrupt on pin 0 108 | bitOffset: 0 109 | bitWidth: 1 110 | access: read-write 111 | PCINT1: 112 | description: Enable pin change interrupt on pin 1 113 | bitOffset: 1 114 | bitWidth: 1 115 | access: read-write 116 | PCINT2: 117 | description: Enable pin change interrupt on pin 2 118 | bitOffset: 2 119 | bitWidth: 1 120 | access: read-write 121 | PCINT3: 122 | description: Enable pin change interrupt on pin 3 123 | bitOffset: 3 124 | bitWidth: 1 125 | access: read-write 126 | PCINT4: 127 | description: Enable pin change interrupt on pin 4 128 | bitOffset: 4 129 | bitWidth: 1 130 | access: read-write 131 | PCINT5: 132 | description: Enable pin change interrupt on pin 5 133 | bitOffset: 5 134 | bitWidth: 1 135 | access: read-write 136 | -------------------------------------------------------------------------------- /patch/attiny861.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/adc.yaml" 4 | - "common/tiny/usi.yaml" 5 | - "common/wdt.yaml" 6 | 7 | - "timer/attiny861.yaml" 8 | 9 | -------------------------------------------------------------------------------- /patch/attiny861a.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/attiny861a.svd 2 | 3 | _include: 4 | - "common/ac.yaml" 5 | - "common/tiny/attinyx61a-adc.yaml" 6 | - "common/tiny/attinyx61a-ports.yaml" 7 | - "common/tiny/usi.yaml" 8 | - "common/wdt.yaml" 9 | - "timer/attiny861.yaml" 10 | - "common/tiny/attinyx61a-timers.yaml" 11 | 12 | # All FUSEs are read-only from the CPU. 13 | FUSE: 14 | _modify: 15 | "*": 16 | access: read-only 17 | -------------------------------------------------------------------------------- /patch/attiny88.yaml: -------------------------------------------------------------------------------- 1 | _include: 2 | - "common/ac.yaml" 3 | - "common/eeprom.yaml" 4 | - "common/spi.yaml" 5 | - "common/twi.yaml" 6 | - "common/wdt.yaml" 7 | 8 | - "timer/attiny88.yaml" 9 | 10 | ADC: 11 | ADMUX: 12 | _modify: 13 | MUX: 14 | description: "Analog Channel Selection Bits" 15 | MUX: 16 | _replace_enum: 17 | ADC0: [0, "ADC Single Ended Input pin 0"] 18 | ADC1: [1, "ADC Single Ended Input pin 1"] 19 | ADC2: [2, "ADC Single Ended Input pin 2"] 20 | ADC3: [3, "ADC Single Ended Input pin 3"] 21 | ADC4: [4, "ADC Single Ended Input pin 4"] 22 | ADC5: [5, "ADC Single Ended Input pin 5"] 23 | ADC6: [6, "ADC Single Ended Input pin 6"] 24 | ADC7: [7, "ADC Single Ended Input pin 7"] 25 | TEMPSENS: [8, "Temperature sensor"] 26 | ADC_VBG: [14, "Internal Reference (VBG)"] 27 | ADC_GND: [15, "0V (GND)"] 28 | REFS0: 29 | _replace_enum: 30 | INTERNAL: [0, "Internal 1.1V Voltage Reference"] 31 | AVCC: [1, "AVcc Reference"] 32 | ADCSRA: 33 | ADPS: 34 | _replace_enum: 35 | PRESCALER_2: [1, "Prescaler Value 2"] 36 | PRESCALER_4: [2, "Prescaler Value 4"] 37 | PRESCALER_8: [3, "Prescaler Value 8"] 38 | PRESCALER_16: [4, "Prescaler Value 16"] 39 | PRESCALER_32: [5, "Prescaler Value 32"] 40 | PRESCALER_64: [6, "Prescaler Value 64"] 41 | PRESCALER_128: [7, "Prescaler Value 128"] 42 | ADCSRB: 43 | ADTS: 44 | _replace_enum: 45 | FREE: [0, "Free Running mode"] 46 | AC: [1, "Analog Comparator"] 47 | INT0: [2, "External Interrupt Request 0"] 48 | TC0_CMA: [3, "Timer/Counter0 Compare Match A"] 49 | TC0_OVF: [4, "Timer/Counter0 Overflow"] 50 | TC1_CMB: [5, "Timer/Counter1 Compare Match B"] 51 | TC1_OVF: [6, "Timer/Counter1 Overflow"] 52 | TC1_CE: [7, "Timer/Counter1 Capture Event"] 53 | CPU: 54 | CLKPR: 55 | CLKPS: 56 | _replace_enum: 57 | PRESCALER_1: [0, "Prescaler Value 1"] 58 | PRESCALER_2: [1, "Prescaler Value 2"] 59 | PRESCALER_4: [2, "Prescaler Value 4"] 60 | PRESCALER_8: [3, "Prescaler Value 8"] 61 | PRESCALER_16: [4, "Prescaler Value 16"] 62 | PRESCALER_32: [5, "Prescaler Value 32"] 63 | PRESCALER_64: [6, "Prescaler Value 64"] 64 | PRESCALER_128: [7, "Prescaler Value 128"] 65 | PRESCALER_256: [8, "Prescaler Value 256"] 66 | SMCR: 67 | SM: 68 | _replace_enum: 69 | IDLE: [0, "Idle"] 70 | ADC: [1, "ADC Noise Reduction"] 71 | PDOWN: [2, "Power-down"] 72 | EXINT: 73 | EICRA: 74 | ISC?: 75 | _replace_enum: 76 | LOW: [0, "The low level of INTx generates an interrupt request"] 77 | TOGGLE: [1, "Any logical change on INTx generates an interrupt request"] 78 | FALLING: [2, "The falling edge of INTx generates an interrupt request"] 79 | RISING: [3, "The rising edge of INTx generates an interrupt request"] 80 | _modify: 81 | PCICR: 82 | description: "Pin Change Interrupt Control Register" 83 | -------------------------------------------------------------------------------- /patch/common/ac.yaml: -------------------------------------------------------------------------------- 1 | # Patches for the Analog Comparator 2 | # 3 | # - Make the control-register actually writable 4 | # - Fix the description of the "Interrupt Mode Select" field 5 | # - Make just the Output field of ACSR read-only 6 | # - Fix the "Interrupt Mode Select" enumerated values 7 | AC: 8 | ACSR,ACSR?A,ACSRA: 9 | _modify: 10 | ACIS,ACIS?: 11 | description: "Analog Comparator Interrupt Mode Select" 12 | ACO*: 13 | access: read-only 14 | ACIS,ACIS?: 15 | _replace_enum: 16 | ON_TOGGLE: [0, "Interrupt on Toggle"] 17 | # Leaving [1, 'Reserved'] out 18 | ON_FALLING_EDGE: [2, "Interrupt on Falling Edge"] 19 | ON_RISING_EDGE: [3, "Interrupt on Rising Edge"] 20 | -------------------------------------------------------------------------------- /patch/common/adc.yaml: -------------------------------------------------------------------------------- 1 | # Patches for the Analog Digital Converter 2 | # 3 | # - Make the control-register actually writable 4 | ADC: 5 | ADCSRA: 6 | ADPS: 7 | _replace_enum: 8 | PRESCALER_2: [1, "Prescaler Value 2"] 9 | PRESCALER_4: [2, "Prescaler Value 4"] 10 | PRESCALER_8: [3, "Prescaler Value 8"] 11 | PRESCALER_16: [4, "Prescaler Value 16"] 12 | PRESCALER_32: [5, "Prescaler Value 32"] 13 | PRESCALER_64: [6, "Prescaler Value 64"] 14 | PRESCALER_128: [7, "Prescaler Value 128"] 15 | ADMUX: 16 | REFS: 17 | _replace_enum: 18 | AREF: [0, "Aref Internal Vref turned off"] 19 | AVCC: [1, "AVcc with external capacitor at AREF pin"] 20 | INTERNAL: [3, "Internal 1.1V Voltage Reference with external capacitor at AREF pin"] 21 | -------------------------------------------------------------------------------- /patch/common/at90/adc.yaml: -------------------------------------------------------------------------------- 1 | 2 | _include: 3 | - "../adc.yaml" 4 | 5 | ADC: 6 | ADMUX: 7 | MUX: 8 | _replace_enum: 9 | ADC0: [0, "ADC Single Ended Input pin 0"] 10 | ADC1: [1, "ADC Single Ended Input pin 1"] 11 | ADC2: [2, "ADC Single Ended Input pin 2"] 12 | ADC3: [3, "ADC Single Ended Input pin 3"] 13 | ADC4: [4, "ADC Single Ended Input pin 4"] 14 | ADC5: [5, "ADC Single Ended Input pin 5"] 15 | ADC6: [6, "ADC Single Ended Input pin 6"] 16 | ADC7: [7, "ADC Single Ended Input pin 7"] 17 | ADC0_ADC0_10X: [8, "ADC Differential Inputs Positive pin 0 Negative pin 0 10x Gain"] 18 | ADC1_ADC0_10X: [9, "ADC Differential Inputs Positive pin 1 Negative pin 0 10x Gain"] 19 | ADC0_ADC0_200X: [10, "ADC Differential Inputs Positive pin 0 Negative pin 0 200x Gain"] 20 | ADC1_ADC0_200X: [11, "ADC Differential Inputs Positive pin 1 Negative pin 0 200x Gain"] 21 | ADC2_ADC2_10X: [12, "ADC Differential Inputs Positive pin 2 Negative pin 2 10x Gain"] 22 | ADC3_ADC2_10X: [13, "ADC Differential Inputs Positive pin 3 Negative pin 2 10x Gain"] 23 | ADC2_ADC2_200X: [14, "ADC Differential Inputs Positive pin 2 Negative pin 2 200x Gain"] 24 | ADC3_ADC2_200X: [15, "ADC Differential Inputs Positive pin 3 Negative pin 2 200x Gain"] 25 | ADC0_ADC1_1X: [16, "ADC Differential Inputs Positive pin 0 Negative pin 1 1x Gain"] 26 | ADC1_ADC1_1X: [17, "ADC Differential Inputs Positive pin 1 Negative pin 1 1x Gain"] 27 | ADC2_ADC1_1X: [18, "ADC Differential Inputs Positive pin 2 Negative pin 1 1x Gain"] 28 | ADC3_ADC1_1X: [19, "ADC Differential Inputs Positive pin 3 Negative pin 1 1x Gain"] 29 | ADC4_ADC1_1X: [20, "ADC Differential Inputs Positive pin 4 Negative pin 1 1x Gain"] 30 | ADC5_ADC1_1X: [21, "ADC Differential Inputs Positive pin 5 Negative pin 1 1x Gain"] 31 | ADC6_ADC1_1X: [22, "ADC Differential Inputs Positive pin 6 Negative pin 1 1x Gain"] 32 | ADC7_ADC1_1X: [23, "ADC Differential Inputs Positive pin 7 Negative pin 1 1x Gain"] 33 | ADC0_ADC2_1X: [24, "ADC Differential Inputs Positive pin 0 Negative pin 2 1x Gain"] 34 | ADC1_ADC2_1X: [25, "ADC Differential Inputs Positive pin 1 Negative pin 2 1x Gain"] 35 | ADC2_ADC2_1X: [26, "ADC Differential Inputs Positive pin 2 Negative pin 2 1x Gain"] 36 | ADC3_ADC2_1X: [27, "ADC Differential Inputs Positive pin 3 Negative pin 2 1x Gain"] 37 | ADC4_ADC2_1X: [28, "ADC Differential Inputs Positive pin 4 Negative pin 2 1x Gain"] 38 | ADC5_ADC2_1X: [29, "ADC Differential Inputs Positive pin 5 Negative pin 2 1x Gain"] 39 | ADC_VBG: [30, "Internal Reference (VBG)"] 40 | ADC_GND: [31, "0V (GND)"] 41 | -------------------------------------------------------------------------------- /patch/common/at90/spi.yaml: -------------------------------------------------------------------------------- 1 | # Patches for the SPI peripheral 2 | # 3 | # Fix the SP2X status register bit to have write access 4 | SPI*: 5 | SPSR: 6 | _modify: 7 | SPIF: 8 | access: read-only 9 | WCOL: 10 | access: read-only 11 | -------------------------------------------------------------------------------- /patch/common/at90/usart.yaml: -------------------------------------------------------------------------------- 1 | USART?: 2 | UCSR?A: 3 | _modify: 4 | UPE?: 5 | access: read-only 6 | DOR?: 7 | access: read-only 8 | FE?: 9 | access: read-only 10 | UDRE?: 11 | access: read-only 12 | TXC?: 13 | description: "USART Transmit Complete" 14 | RXC?: 15 | access: read-only 16 | UCSR?B: 17 | _modify: 18 | RXB8?: 19 | access: read-only 20 | UCSR?C: 21 | UMSEL?: 22 | _replace_enum: 23 | USART_ASYNC: [0, "Asynchronous Operation"] 24 | USART_SYNC: [1, "Synchronous Operation"] 25 | UPM?: 26 | _replace_enum: 27 | DISABLED: [0, "Disabled"] 28 | PARITY_EVEN: [2, "Enabled, Even Parity"] 29 | PARITY_ODD: [3, "Enabled, Odd Parity"] 30 | USBS?: 31 | _replace_enum: 32 | STOP1: [0, "1-bit"] 33 | STOP2: [1, "2-bit"] 34 | UCSZ?: 35 | _replace_enum: 36 | CHR5: [0, "Character Size: 5 bit"] 37 | CHR6: [1, "Character Size: 6 bit"] 38 | CHR7: [2, "Character Size: 7 bit"] 39 | CHR8: [3, "Character Size: 8 bit"] 40 | UCPOL?: 41 | _replace_enum: 42 | RISING_EDGE: [0, "Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge"] 43 | FALLING_EDGE: [1, "Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge"] 44 | -------------------------------------------------------------------------------- /patch/common/attiny-1-series.yaml: -------------------------------------------------------------------------------- 1 | # Nothing needed beyond what we already have for the 0-series 2 | # This is probably good for at least ATtiny212/214/412/414/416, but may not be valid for ATtiny81* and ATtiny161* 3 | 4 | {} 5 | -------------------------------------------------------------------------------- /patch/common/attiny-xmega/0-series.yaml: -------------------------------------------------------------------------------- 1 | # Nothing needed beyond common config 2 | # This is probably good for at least ATtiny202/204/402/404/406, but may not be valid for ATtiny80* and ATtiny160* 3 | 4 | {} 5 | -------------------------------------------------------------------------------- /patch/common/attiny-xmega/1-series.yaml: -------------------------------------------------------------------------------- 1 | # Nothing needed beyond common config 2 | # This is probably good for at least ATtiny212/214/412/414/416, but may not be valid for ATtiny81* and ATtiny161* 3 | 4 | {} 5 | -------------------------------------------------------------------------------- /patch/common/attiny-xmega/2-series.yaml: -------------------------------------------------------------------------------- 1 | # VPORTA.DIR is located at memory address 0x0. So far rust is not able to access 2 | # memory address 0x0. It treats it as invalid pointer and immediately panics 3 | # without even trying to access the address. 4 | VPORTA: 5 | _delete: DIR 6 | -------------------------------------------------------------------------------- /patch/common/attiny-xmega/common.yaml: -------------------------------------------------------------------------------- 1 | # This is probably good for ATtiny20x, ATtiny40x, ATtiny21x, ATtiny41x 2 | # It may not be enough for Attiny8xx, ATtiny16xx, or ATtinyx2x 3 | 4 | TCB0: 5 | CTRLB: 6 | _modify: 7 | # 'async' is reserved 8 | ASYNC: 9 | name: "TCB_ASYNC" 10 | 11 | # Split this in 2 for ease of use 12 | TWI0: 13 | SADDR: 14 | _add: 15 | # FIXME: Make this so we don't need 'unsafe' 16 | ADDR: 17 | description: "Client Address" 18 | bitRange: "[7:1]" 19 | access: read-write 20 | GCE: 21 | description: "General Call Recognition Enable Bit" 22 | bitRange: "[0:0]" 23 | access: read-write 24 | 25 | USERROW: 26 | _modify: 27 | "USERROW*": 28 | description: "User Row Bytes" 29 | _array: 30 | "USERROW*": {} 31 | 32 | GPIO: 33 | _modify: 34 | "GPIO*": 35 | description: "General Purpose IO Registers" 36 | _array: 37 | "GPIO*": {} 38 | 39 | SIGROW: 40 | _modify: 41 | "DEVICEID*": 42 | description: "Device IO Bytes" 43 | "SERNUM*": 44 | description: "Serial Number Bytes" 45 | "TEMPSENSE0": 46 | description: "Temperature Sensor Calibration: Gain/Slope" 47 | "TEMPSENSE1": 48 | description: "Temperature Sensor Calibration: Offset" 49 | _array: 50 | "DEVICEID*": {} 51 | "SERNUM*": {} 52 | 53 | # All FUSEs are read-only from the CPU (can only be modified with UPDI) 54 | FUSE: 55 | _modify: 56 | "*": 57 | access: read-only 58 | 59 | PORT[A-Z]: 60 | _modify: 61 | # 'in' is reserved 62 | IN: 63 | name: INPUT 64 | 65 | SPI*: 66 | CTRLA: 67 | PRESC: 68 | _replace_enum: 69 | CLK_PER_4_2: 70 | [0, "Peripheral clock / 4 if CLK2X == 0 else Peripheral clock / 2"] 71 | CLK_PER_16_8: 72 | [1, "Peripheral clock / 16 if CLK2X == 0 else Peripheral clock / 8"] 73 | CLK_PER_64_32: 74 | [2, "Peripheral clock / 64 if CLK2X == 0 else Peripheral clock / 32"] 75 | CLK_PER_128_64: 76 | [3, "Peripheral clock / 128 if CLK2X == 0 else Peripheral clock / 64"] 77 | -------------------------------------------------------------------------------- /patch/common/eeprom.yaml: -------------------------------------------------------------------------------- 1 | EEPROM: 2 | EECR: 3 | EEPM: 4 | _replace_enum: 5 | ATOMIC: [0, "Atomic (erase and write in one operation)"] 6 | ERASE: [1, "Erase only"] 7 | WRITE: [2, "Write only"] 8 | -------------------------------------------------------------------------------- /patch/common/mega0/port.yaml: -------------------------------------------------------------------------------- 1 | PORTC: 2 | _delete: 3 | - OUTSET 4 | _add: 5 | OUTSET: 6 | description: Output Value Set 7 | addressOffset: 0x5 8 | size: 0x8 9 | access: read-write 10 | fields: 11 | PC0: 12 | description: Pin C0 13 | bitRange: "[0:0]" 14 | access: read-write 15 | PC1: 16 | description: Pin C1 17 | bitRange: "[1:1]" 18 | access: read-write 19 | PC2: 20 | description: Pin C2 21 | bitRange: "[2:2]" 22 | access: read-write 23 | PC3: 24 | description: Pin C3 25 | bitRange: "[3:3]" 26 | access: read-write 27 | PORTD: 28 | _delete: 29 | - OUTSET 30 | _add: 31 | OUTSET: 32 | description: Output Value Set 33 | addressOffset: 0x5 34 | size: 0x8 35 | access: read-write 36 | fields: 37 | PD0: 38 | description: Pin D0 39 | bitRange: "[0:0]" 40 | access: read-write 41 | PD1: 42 | description: Pin D1 43 | bitRange: "[1:1]" 44 | access: read-write 45 | PD2: 46 | description: Pin D2 47 | bitRange: "[2:2]" 48 | access: read-write 49 | PD3: 50 | description: Pin D3 51 | bitRange: "[3:3]" 52 | access: read-write 53 | PD4: 54 | description: Pin D4 55 | bitRange: "[4:4]" 56 | access: read-write 57 | PD5: 58 | description: Pin D5 59 | bitRange: "[5:5]" 60 | access: read-write 61 | PD6: 62 | description: Pin D6 63 | bitRange: "[6:6]" 64 | access: read-write 65 | PD7: 66 | description: Pin D7 67 | bitRange: "[7:7]" 68 | access: read-write 69 | 70 | PORTF: 71 | _delete: 72 | - OUTSET 73 | _add: 74 | OUTSET: 75 | description: Output Value Set 76 | addressOffset: 0x5 77 | size: 0x8 78 | access: read-write 79 | fields: 80 | PF0: 81 | description: Pin F0 82 | bitRange: "[0:0]" 83 | access: read-write 84 | PF1: 85 | description: Pin F1 86 | bitRange: "[1:1]" 87 | access: read-write 88 | PF2: 89 | description: Pin F2 90 | bitRange: "[2:2]" 91 | access: read-write 92 | PF3: 93 | description: Pin F3 94 | bitRange: "[3:3]" 95 | access: read-write 96 | PF4: 97 | description: Pin F4 98 | bitRange: "[4:4]" 99 | access: read-write 100 | PF5: 101 | description: Pin F5 102 | bitRange: "[5:5]" 103 | access: read-write 104 | PF6: 105 | description: Pin F6 106 | bitRange: "[6:6]" 107 | access: read-write 108 | -------------------------------------------------------------------------------- /patch/common/pll.yaml: -------------------------------------------------------------------------------- 1 | # Patches for the PLL Clock Generator 2 | # 3 | # - Make the Lock Detector field read-only 4 | # - Add descriptions for "Input Multiplexer" and "USB Postscaler" 5 | # - Add enumerated values to "Lock Frequency" and Postscaler fields 6 | PLL: 7 | PLLCSR: 8 | _modify: 9 | PLOCK: 10 | access: read-only 11 | PLLFRQ: 12 | _modify: 13 | PINMUX: 14 | description: "PLL Input Multiplexer" 15 | PLLUSB: 16 | description: "PLL Postscaler for USB Peripheral" 17 | PDIV: 18 | description: "PLL Lock Frequency" 19 | _write_constraint: none 20 | PLLTM: 21 | description: "PLL Postscaler for High Speed Timer" 22 | _write_constraint: enum 23 | PDIV: 24 | MHZ40: [0b0011, "40 MHz"] 25 | MHZ48: [0b0100, "48 MHz"] 26 | MHZ56: [0b0101, "56 MHz"] 27 | MHZ72: [0b0111, "72 MHz"] 28 | MHZ80: [0b1000, "80 MHz"] 29 | MHZ88: [0b1001, "88 MHz"] 30 | MHZ96: [0b1010, "96 MHz"] 31 | PLLTM: 32 | DISCONNECTED: [0, "0 (Disconnected)"] 33 | FACTOR_1: [1, "1"] 34 | FACTOR_15: [2, "1.5"] 35 | FACTOR_2: [3, "2"] 36 | -------------------------------------------------------------------------------- /patch/common/spi.yaml: -------------------------------------------------------------------------------- 1 | # Patches for the SPI peripheral 2 | # 3 | # Fix the SP2X status register bit to have write access 4 | SPI*: 5 | SPSR: 6 | _modify: 7 | SPIF: 8 | access: read-only 9 | WCOL: 10 | access: read-only 11 | SPCR: 12 | SPR: 13 | _replace_enum: 14 | FOSC_4_2: [0, "Fosc/4 if SPI2X == 0 else Fosc/2"] 15 | FOSC_16_8: [1, "Fosc/16 if SPI2X == 0 else Fosc/8"] 16 | FOSC_64_32: [2, "Fosc/64 if SPI2X == 0 else Fosc/32"] 17 | FOSC_128_64: [3, "Fosc/128 if SPI2X == 0 else Fosc/64"] 18 | -------------------------------------------------------------------------------- /patch/common/tiny/attinyx61a-adc.yaml: -------------------------------------------------------------------------------- 1 | # attiny261a, attiny461a, attiny861a 2 | 3 | ADC: 4 | _modify: 5 | ADCSRA: 6 | description: "ADC Control and Status Register A" 7 | ADCSRA: 8 | ADPS: 9 | _replace_enum: 10 | PRESCALER_2: [1, "Prescaler Value 2"] 11 | PRESCALER_4: [2, "Prescaler Value 4"] 12 | PRESCALER_8: [3, "Prescaler Value 8"] 13 | PRESCALER_16: [4, "Prescaler Value 16"] 14 | PRESCALER_32: [5, "Prescaler Value 32"] 15 | PRESCALER_64: [6, "Prescaler Value 64"] 16 | PRESCALER_128: [7, "Prescaler Value 128"] 17 | ADMUX: 18 | _modify: 19 | MUX: 20 | _write_constraint: enum 21 | REFS: 22 | _write_constraint: enum 23 | MUX: 24 | _replace_enum: 25 | ADC0: [0, "Single-ended Input ADC0"] 26 | ADC1: [1, "Single-ended Input ADC1"] 27 | ADC2: [2, "Single-ended Input ADC2"] 28 | ADC3: [3, "Single-ended Input ADC3"] 29 | ADC4: [4, "Single-ended Input ADC4"] 30 | ADC5: [5, "Single-ended Input ADC5"] 31 | ADC6: [6, "Single-ended Input ADC6"] 32 | ADC7: [7, "Single-ended Input ADC7"] 33 | ADC8: [8, "Single-ended Input ADC8"] 34 | ADC9: [9, "Single-ended Input ADC9"] 35 | ADC10: [10, "Single-ended Input ADC10"] 36 | 37 | ADC0_ADC1_20X: [11, "Differential Inputs Positive ADC0 Negative ADC1 20x Gain"] 38 | ADC0_ADC1_1X: [12, "Differential Inputs Positive ADC0 Negative ADC1 1x Gain"] 39 | ADC1_ADC1_20X: [13, "Differential Inputs Positive ADC1 Negative ADC1 20x Gain (for offset compensation)"] 40 | ADC2_ADC1_20X: [14, "Differential Inputs Positive ADC2 Negative ADC1 20x Gain"] 41 | ADC2_ADC1_1X: [15, "Differential Inputs Positive ADC2 Negative ADC1 1x Gain"] 42 | 43 | ADC2_ADC3_1X: [16, "Differential Inputs Positive ADC2 Negative ADC3 1x Gain"] 44 | ADC3_ADC3_20X: [17, "Differential Inputs Positive ADC3 Negative ADC3 20x Gain (for offset compensation)"] 45 | ADC4_ADC3_20X: [18, "Differential Inputs Positive ADC4 Negative ADC3 20x Gain"] 46 | ADC4_ADC3_1X: [19, "Differential Inputs Positive ADC4 Negative ADC3 1x Gain"] 47 | 48 | ADC4_ADC5_20X: [20, "Differential Inputs Positive ADC4 Negative ADC5 20x Gain"] 49 | ADC4_ADC5_1X: [21, "Differential Inputs Positive ADC4 Negative ADC5 1x Gain"] 50 | ADC5_ADC5_20X: [22, "Differential Inputs Positive ADC5 Negative ADC5 20x Gain (for offset compensation)"] 51 | ADC6_ADC5_20X: [23, "Differential Inputs Positive ADC6 Negative ADC5 20x Gain"] 52 | ADC6_ADC5_1X: [24, "Differential Inputs Positive ADC6 Negative ADC5 1x Gain"] 53 | 54 | ADC8_ADC9_20X: [25, "Differential Inputs Positive ADC8 Negative ADC9 20x Gain"] 55 | ADC8_ADC9_1X: [26, "Differential Inputs Positive ADC8 Negative ADC9 1x Gain"] 56 | ADC9_ADC9_20X: [27, "Differential Inputs Positive ADC9 Negative ADC9 20x Gain (for offset compensation)"] 57 | ADC10_ADC9_20X: [28, "Differential Inputs Positive ADC10 Negative ADC9 20x Gain"] 58 | ADC10_ADC9_1X: [29, "Differential Inputs Positive ADC10 Negative ADC9 1x Gain"] 59 | 60 | ADC_VREF_1P1: [30, "Internal 1.1V Reference"] 61 | ADC_GND: [31, "0V (GND)"] 62 | 63 | # TODO: More mux settings are possible together with ADCSRB/MUX5=1 64 | 65 | REFS: 66 | _replace_enum: 67 | VCC: [0, "Vcc used as Voltage Reference, disconnected from Aref"] 68 | AREF: [1, "External Voltage Reference at AREF pin, Internal Voltage Reference turned off"] 69 | INTERNAL: [2, "Internal 1.1V Voltage Reference"] 70 | 71 | # TODO: More ref settings are possible together with ADCSRB/REFS2=1 72 | -------------------------------------------------------------------------------- /patch/common/tiny/attinyx61a-ports.yaml: -------------------------------------------------------------------------------- 1 | # attiny26, attiny261a, attiny461a, attiny861a 2 | 3 | PORTA: 4 | DDRA: 5 | _add: 6 | PA0: 7 | description: "Pin A0" 8 | bitRange: "[0:0]" 9 | access: read-write 10 | PA1: 11 | description: "Pin A1" 12 | bitRange: "[1:1]" 13 | access: read-write 14 | PA2: 15 | description: "Pin A2" 16 | bitRange: "[2:2]" 17 | access: read-write 18 | PA3: 19 | description: "Pin A3" 20 | bitRange: "[3:3]" 21 | access: read-write 22 | PA4: 23 | description: "Pin A4" 24 | bitRange: "[4:4]" 25 | access: read-write 26 | PA5: 27 | description: "Pin A5" 28 | bitRange: "[5:5]" 29 | access: read-write 30 | PA6: 31 | description: "Pin A6" 32 | bitRange: "[6:6]" 33 | access: read-write 34 | PA7: 35 | description: "Pin A7" 36 | bitRange: "[7:7]" 37 | access: read-write 38 | PINA: 39 | _add: 40 | PA0: 41 | description: "Pin A0" 42 | bitRange: "[0:0]" 43 | access: read-write 44 | PA1: 45 | description: "Pin A1" 46 | bitRange: "[1:1]" 47 | access: read-write 48 | PA2: 49 | description: "Pin A2" 50 | bitRange: "[2:2]" 51 | access: read-write 52 | PA3: 53 | description: "Pin A3" 54 | bitRange: "[3:3]" 55 | access: read-write 56 | PA4: 57 | description: "Pin A4" 58 | bitRange: "[4:4]" 59 | access: read-write 60 | PA5: 61 | description: "Pin A5" 62 | bitRange: "[5:5]" 63 | access: read-write 64 | PA6: 65 | description: "Pin A6" 66 | bitRange: "[6:6]" 67 | access: read-write 68 | PA7: 69 | description: "Pin A7" 70 | bitRange: "[7:7]" 71 | access: read-write 72 | PORTA: 73 | _add: 74 | PA0: 75 | description: "Pin A0" 76 | bitRange: "[0:0]" 77 | access: read-write 78 | PA1: 79 | description: "Pin A1" 80 | bitRange: "[1:1]" 81 | access: read-write 82 | PA2: 83 | description: "Pin A2" 84 | bitRange: "[2:2]" 85 | access: read-write 86 | PA3: 87 | description: "Pin A3" 88 | bitRange: "[3:3]" 89 | access: read-write 90 | PA4: 91 | description: "Pin A4" 92 | bitRange: "[4:4]" 93 | access: read-write 94 | PA5: 95 | description: "Pin A5" 96 | bitRange: "[5:5]" 97 | access: read-write 98 | PA6: 99 | description: "Pin A6" 100 | bitRange: "[6:6]" 101 | access: read-write 102 | PA7: 103 | description: "Pin A7" 104 | bitRange: "[7:7]" 105 | access: read-write 106 | 107 | PORTB: 108 | DDRB: 109 | _add: 110 | PB0: 111 | description: "Pin B0" 112 | bitRange: "[0:0]" 113 | access: read-write 114 | PB1: 115 | description: "Pin B1" 116 | bitRange: "[1:1]" 117 | access: read-write 118 | PB2: 119 | description: "Pin B2" 120 | bitRange: "[2:2]" 121 | access: read-write 122 | PB3: 123 | description: "Pin B3" 124 | bitRange: "[3:3]" 125 | access: read-write 126 | PB4: 127 | description: "Pin B4" 128 | bitRange: "[4:4]" 129 | access: read-write 130 | PB5: 131 | description: "Pin B5" 132 | bitRange: "[5:5]" 133 | access: read-write 134 | PB6: 135 | description: "Pin B6" 136 | bitRange: "[6:6]" 137 | access: read-write 138 | PB7: 139 | description: "Pin B7" 140 | bitRange: "[7:7]" 141 | access: read-write 142 | PINB: 143 | _add: 144 | PB0: 145 | description: "Pin B0" 146 | bitRange: "[0:0]" 147 | access: read-write 148 | PB1: 149 | description: "Pin B1" 150 | bitRange: "[1:1]" 151 | access: read-write 152 | PB2: 153 | description: "Pin B2" 154 | bitRange: "[2:2]" 155 | access: read-write 156 | PB3: 157 | description: "Pin B3" 158 | bitRange: "[3:3]" 159 | access: read-write 160 | PB4: 161 | description: "Pin B4" 162 | bitRange: "[4:4]" 163 | access: read-write 164 | PB5: 165 | description: "Pin B5" 166 | bitRange: "[5:5]" 167 | access: read-write 168 | PB6: 169 | description: "Pin B6" 170 | bitRange: "[6:6]" 171 | access: read-write 172 | PB7: 173 | description: "Pin B7" 174 | bitRange: "[7:7]" 175 | access: read-write 176 | PORTB: 177 | _add: 178 | PB0: 179 | description: "Pin B0" 180 | bitRange: "[0:0]" 181 | access: read-write 182 | PB1: 183 | description: "Pin B1" 184 | bitRange: "[1:1]" 185 | access: read-write 186 | PB2: 187 | description: "Pin B2" 188 | bitRange: "[2:2]" 189 | access: read-write 190 | PB3: 191 | description: "Pin B3" 192 | bitRange: "[3:3]" 193 | access: read-write 194 | PB4: 195 | description: "Pin B4" 196 | bitRange: "[4:4]" 197 | access: read-write 198 | PB5: 199 | description: "Pin B5" 200 | bitRange: "[5:5]" 201 | access: read-write 202 | PB6: 203 | description: "Pin B6" 204 | bitRange: "[6:6]" 205 | access: read-write 206 | PB7: 207 | description: "Pin B7" 208 | bitRange: "[7:7]" 209 | access: read-write 210 | -------------------------------------------------------------------------------- /patch/common/tiny/attinyx61a-timers.yaml: -------------------------------------------------------------------------------- 1 | # attiny261a, attiny461a, attiny861a 2 | 3 | TC0: 4 | TCCR0A: 5 | _modify: 6 | WGM00: 7 | name: CTC0 8 | -------------------------------------------------------------------------------- /patch/common/tiny/exint.yaml: -------------------------------------------------------------------------------- 1 | EXINT: 2 | MCUCR: 3 | _delete: 4 | - ISC?? 5 | _add: 6 | ISC0: 7 | description: "Interrupt Sense Control 0 bits" 8 | bitOffset: 0 9 | bitWidth: 2 10 | access: read-write 11 | ISC0: 12 | _replace_enum: 13 | LOW: [0, "The low level of INTx generates an interrupt request"] 14 | TOGGLE: [1, "Any logical change on INTx generates an interrupt request"] 15 | FALLING: [2, "The falling edge of INTx generates an interrupt request"] 16 | RISING: [3, "The rising edge of INTx generates an interrupt request"] 17 | -------------------------------------------------------------------------------- /patch/common/tiny/usi.yaml: -------------------------------------------------------------------------------- 1 | USI: 2 | USICR: 3 | _modify: 4 | USICLK: 5 | access: write-only 6 | USITC: 7 | access: write-only 8 | USIWM: 9 | _replace_enum: 10 | DISABLED: [0, "All detectors disabled. Port pins operates as normal."] 11 | THREE_WIRE: [1, "Three-wire mode. Uses DO, DI, and USCK pins."] 12 | TWO_WIRE_SLAVE: [2, "Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins."] 13 | TWO_WIRE_MASTER: [3, "Two-wire mode (Master). Uses SDA and SCL pins."] 14 | USICS: 15 | NO_CLOCK: [0, "No Clock/Software clock strobe"] 16 | TC0: [1, "Timer/Counter0 Compare Match"] 17 | EXT_POS: [2, "External, positive edge"] 18 | EXT_NEG: [3, "External, negative edge"] 19 | USISR: 20 | _modify: 21 | USIDC: 22 | access: read-only 23 | -------------------------------------------------------------------------------- /patch/common/twi.yaml: -------------------------------------------------------------------------------- 1 | # Patches for the Two-Wire-Interface peripheral (i2c) 2 | # 3 | # - Make the Control Register read-write with only the 4 | # "Write Collision Flag" being read-only 5 | # - Fix the "Slave Address Mask" description 6 | # - Fix the Prescaler enumerated values 7 | TWI*: 8 | TWCR: 9 | _modify: 10 | TWWC: 11 | access: read-only 12 | TWAMR: 13 | _modify: 14 | TWAM*: 15 | description: "TWI (Slave) Address Mask Bits" 16 | TWSR: 17 | _modify: 18 | TWS: 19 | access: read-only 20 | TWPS: 21 | _replace_enum: 22 | PRESCALER_1: [0, "Prescaler Value 1"] 23 | PRESCALER_4: [1, "Prescaler Value 4"] 24 | PRESCALER_16: [2, "Prescaler Value 16"] 25 | PRESCALER_64: [3, "Prescaler Value 64"] 26 | -------------------------------------------------------------------------------- /patch/common/usart-single-attiny2313.yaml: -------------------------------------------------------------------------------- 1 | USART: 2 | UCSRA: 3 | _modify: 4 | UPE: 5 | access: read-only 6 | DOR: 7 | access: read-only 8 | FE: 9 | access: read-only 10 | UDRE: 11 | access: read-only 12 | TXC: 13 | description: "USART Transmit Complete" 14 | RXC: 15 | access: read-only 16 | UCSRB: 17 | _modify: 18 | RXB8: 19 | access: read-only 20 | UCSRC: 21 | UMSEL: 22 | _replace_enum: 23 | USART_ASYNC: [0, "Asynchronous USART"] 24 | USART_SYNC: [1, "Synchronous USART"] 25 | UPM: 26 | _replace_enum: 27 | DISABLED: [0, "Disabled"] 28 | PARITY_EVEN: [2, "Enabled, Even Parity"] 29 | PARITY_ODD: [3, "Enabled, Odd Parity"] 30 | USBS: 31 | _replace_enum: 32 | STOP1: [0, "1-bit"] 33 | STOP2: [1, "2-bit"] 34 | UCSZ: 35 | CHR5: [0, "Character Size: 5 bit"] 36 | CHR6: [1, "Character Size: 6 bit"] 37 | CHR7: [2, "Character Size: 7 bit"] 38 | CHR8: [3, "Character Size: 8 bit"] 39 | UCPOL: 40 | _replace_enum: 41 | RISING_EDGE: [0, "Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge"] 42 | FALLING_EDGE: [1, "Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge"] 43 | -------------------------------------------------------------------------------- /patch/common/usart-single-attiny2313a.yaml: -------------------------------------------------------------------------------- 1 | USART: 2 | UCSRA: 3 | _modify: 4 | UPE: 5 | access: read-only 6 | DOR: 7 | access: read-only 8 | FE: 9 | access: read-only 10 | UDRE: 11 | access: read-only 12 | TXC: 13 | description: "USART Transmit Complete" 14 | RXC: 15 | access: read-only 16 | UCSRB: 17 | _modify: 18 | RXB8: 19 | access: read-only 20 | UCSRC: 21 | UMSEL: 22 | _replace_enum: 23 | USART_ASYNC: [0, "Asynchronous USART"] 24 | USART_SYNC: [1, "Synchronous USART"] 25 | SPI_MASTER: [3, "Master SPI (MSPIM)"] 26 | UPM: 27 | _replace_enum: 28 | DISABLED: [0, "Disabled"] 29 | PARITY_EVEN: [2, "Enabled, Even Parity"] 30 | PARITY_ODD: [3, "Enabled, Odd Parity"] 31 | USBS: 32 | _replace_enum: 33 | STOP1: [0, "1-bit"] 34 | STOP2: [1, "2-bit"] 35 | UCSZ: 36 | CHR5: [0, "Character Size: 5 bit"] 37 | CHR6: [1, "Character Size: 6 bit"] 38 | CHR7: [2, "Character Size: 7 bit"] 39 | CHR8: [3, "Character Size: 8 bit"] 40 | UCPOL: 41 | _replace_enum: 42 | RISING_EDGE: [0, "Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge"] 43 | FALLING_EDGE: [1, "Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge"] 44 | -------------------------------------------------------------------------------- /patch/common/usart.yaml: -------------------------------------------------------------------------------- 1 | USART?: 2 | UCSR?A: 3 | _modify: 4 | UPE?: 5 | access: read-only 6 | DOR?: 7 | access: read-only 8 | FE?: 9 | access: read-only 10 | UDRE?: 11 | access: read-only 12 | TXC?: 13 | description: "USART Transmit Complete" 14 | RXC?: 15 | access: read-only 16 | UCSR?B: 17 | _modify: 18 | RXB8?: 19 | access: read-only 20 | UCSR?C: 21 | UMSEL?: 22 | _replace_enum: 23 | USART_ASYNC: [0, "Asynchronous USART"] 24 | USART_SYNC: [1, "Synchronous USART"] 25 | SPI_MASTER: [3, "Master SPI (MSPIM)"] 26 | UPM?: 27 | _replace_enum: 28 | DISABLED: [0, "Disabled"] 29 | PARITY_EVEN: [2, "Enabled, Even Parity"] 30 | PARITY_ODD: [3, "Enabled, Odd Parity"] 31 | USBS?: 32 | _replace_enum: 33 | STOP1: [0, "1-bit"] 34 | STOP2: [1, "2-bit"] 35 | UCSZ?: 36 | _replace_enum: 37 | CHR5: [0, "Character Size: 5 bit"] 38 | CHR6: [1, "Character Size: 6 bit"] 39 | CHR7: [2, "Character Size: 7 bit"] 40 | CHR8: [3, "Character Size: 8 bit"] 41 | UCPOL?: 42 | _replace_enum: 43 | RISING_EDGE: [0, "Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge"] 44 | FALLING_EDGE: [1, "Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge"] 45 | -------------------------------------------------------------------------------- /patch/common/wdt.yaml: -------------------------------------------------------------------------------- 1 | # Patches for the Watchdog Timer 2 | # 3 | # The control register has a different name between ATmega and 4 | # ATtiny (WDTCSR vs WDTCR). 5 | # 6 | # - Remove the overlapping WDP (Prescaler) field and replace 7 | # it with two separate fields. 8 | # - TODO: See if svd2rust would support some kind of mask? 9 | WDT: 10 | WDTCSR,WDTCR: 11 | _delete: 12 | - WDP 13 | _add: 14 | WDPL: 15 | description: "Watchdog Timer Prescaler - Low Bits" 16 | bitRange: "[2:0]" 17 | WDPH: 18 | description: "Watchdog Timer Prescaler - High Bit" 19 | bitRange: "[5:5]" 20 | WDPL: 21 | CYCLES_2K_512K: [0, "- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set"] 22 | CYCLES_4K_1024K: [1, "- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set"] 23 | CYCLES_8K: [2, "- 8192 cycles, ~64ms"] 24 | CYCLES_16K: [3, "- 16K (16384) cycles, ~0.125s"] 25 | CYCLES_32K: [4, "- 32K (32768) cycles, ~0.25s"] 26 | CYCLES_64K: [5, "- 64K (65536) cycles, ~0.5s"] 27 | CYCLES_128K: [6, "- 128K (131072) cycles, ~1s"] 28 | CYCLES_256K: [7, "- 256K (262144) cycles, ~2s"] 29 | -------------------------------------------------------------------------------- /patch/timer/atmega1280-2560.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit.yaml" 7 | 8 | TC1,TC3,TC4,TC5: 9 | _include: 10 | - "dev/16bit.yaml" 11 | 12 | TC2: 13 | _include: 14 | - "dev/8bit-async.yaml" 15 | -------------------------------------------------------------------------------- /patch/timer/atmega1284p.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit.yaml" 7 | 8 | TC1: 9 | _include: 10 | - "dev/16bit.yaml" 11 | 12 | TC2: 13 | _include: 14 | - "dev/8bit-async.yaml" 15 | 16 | TC3: 17 | _include: 18 | - "dev/16bit.yaml" 19 | -------------------------------------------------------------------------------- /patch/timer/atmega128a.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit-async-mega8.yaml" 7 | 8 | TC1: 9 | _include: 10 | - "dev/16bit.yaml" 11 | 12 | TC2: 13 | _include: 14 | - "dev/8bit-mega8.yaml" 15 | 16 | TC3: 17 | _include: 18 | - "dev/16bit.yaml" 19 | -------------------------------------------------------------------------------- /patch/timer/atmega128rfa1.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | 5 | TC0: 6 | _include: 7 | - "dev/8bit.yaml" 8 | TCCR0A: 9 | COM0A: 10 | _replace_enum: 11 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 12 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 13 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"] 14 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"] 15 | 16 | TC1: 17 | _include: 18 | - "dev/16bit.yaml" 19 | 20 | TCCR1A: 21 | COM1A: 22 | _replace_enum: 23 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 24 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 25 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"] 26 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"] 27 | COM1B: 28 | _replace_enum: 29 | disconnected: [0, "Normal port operation, OC0A disconnected"] 30 | match_toggle: [1, "Toggle OC0A on Compare Match"] 31 | match_clear: [2, "Clear OC0A on Compare Match"] 32 | match_set: [3, "Set OC0A on Compare Match"] 33 | 34 | TC2: 35 | _include: 36 | - "dev/8bit-async.yaml" 37 | TCCR2A: 38 | COM2A: 39 | _replace_enum: 40 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 41 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 42 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"] 43 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"] 44 | 45 | TC3: 46 | _include: 47 | - "dev/16bit.yaml" 48 | 49 | TCCR3A: 50 | COM3A: 51 | _replace_enum: 52 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 53 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 54 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"] 55 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"] 56 | COM3B: 57 | _replace_enum: 58 | disconnected: [0, "Normal port operation, OC0A disconnected"] 59 | match_toggle: [1, "Toggle OC0A on Compare Match"] 60 | match_clear: [2, "Clear OC0A on Compare Match"] 61 | match_set: [3, "Set OC0A on Compare Match"] 62 | 63 | TC4: 64 | _include: 65 | - "dev/16bit.yaml" 66 | 67 | TCCR4A: 68 | COM4A: 69 | _replace_enum: 70 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 71 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 72 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"] 73 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"] 74 | COM4B: 75 | _replace_enum: 76 | disconnected: [0, "Normal port operation, OC0A disconnected"] 77 | match_toggle: [1, "Toggle OC0A on Compare Match"] 78 | match_clear: [2, "Clear OC0A on Compare Match"] 79 | match_set: [3, "Set OC0A on Compare Match"] 80 | 81 | TC5: 82 | _include: 83 | - "dev/16bit.yaml" 84 | 85 | TCCR5A: 86 | COM5A: 87 | _replace_enum: 88 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 89 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 90 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"] 91 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"] 92 | COM5B: 93 | _replace_enum: 94 | disconnected: [0, "Normal port operation, OC0A disconnected"] 95 | match_toggle: [1, "Toggle OC0A on Compare Match"] 96 | match_clear: [2, "Clear OC0A on Compare Match"] 97 | match_set: [3, "Set OC0A on Compare Match"] -------------------------------------------------------------------------------- /patch/timer/atmega16.yaml: -------------------------------------------------------------------------------- 1 | TC0: 2 | TCCR0: 3 | _delete: 4 | - CS00 5 | - CS01 6 | - CS02 7 | _add: 8 | CS: 9 | description: "Clock Select" 10 | bitRange: "[2:0]" 11 | CS: 12 | _replace_enum: 13 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 14 | DIRECT: [1, "Running, No Prescaling"] 15 | PRESCALE_8: [2, "Running, CLK/8"] 16 | PRESCALE_64: [3, "Running, CLK/64"] 17 | PRESCALE_256: [4, "Running, CLK/256"] 18 | PRESCALE_1024: [5, "Running, CLK/1024"] 19 | EXT_FALLING: [6, "Running, ExtClk T0 Falling Edge"] 20 | EXT_RISING: [7, "Running, ExtClk T0 Rising Edge"] 21 | TC1: 22 | # TCCR1A is too complex for me to implement right now, because it has 3 different 23 | # modes depending on bits which are set elsewhere. 24 | TCCR1B: # ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 25 | _delete: 26 | - CS10 27 | - CS11 28 | - CS12 29 | _add: 30 | CS: 31 | description: "Clock Select" 32 | bitRange: "[2:0]" 33 | CS: 34 | _replace_enum: 35 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 36 | DIRECT: [1, "Running, No Prescaling"] 37 | PRESCALE_8: [2, "Running, CLK/8"] 38 | PRESCALE_64: [3, "Running, CLK/64"] 39 | PRESCALE_256: [4, "Running, CLK/256"] 40 | PRESCALE_1024: [5, "Running, CLK/1024"] 41 | EXT_FALLING: [6, "Running, ExtClk T1 Falling Edge"] 42 | EXT_RISING: [7, "Running, ExtClk T1 Rising Edge"] 43 | TC2: 44 | TCCR2: 45 | _delete: 46 | - CS20 47 | - CS21 48 | - CS22 49 | _add: 50 | CS: 51 | description: "Clock Select" 52 | bitRange: "[2:0]" 53 | CS: 54 | _replace_enum: 55 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 56 | DIRECT: [1, "Running, No Prescaling"] 57 | PRESCALE_8: [2, "Running, CLK/8"] 58 | PRESCALE_32: [3, "Running, CLK/32"] 59 | PRESCALE_64: [4, "Running, CLK/64"] 60 | PRESCALE_128: [5, "Running, CLK/128"] 61 | PRESCALE_256: [6, "Running, CLK/256"] 62 | PRESCALE_1024: [7, "Running, CLK/1024"] 63 | -------------------------------------------------------------------------------- /patch/timer/atmega2560.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit.yaml" 7 | 8 | TC1,TC3,TC4,TC5: 9 | _include: 10 | - "dev/16bit.yaml" 11 | 12 | TC2: 13 | _include: 14 | - "dev/8bit-async.yaml" 15 | -------------------------------------------------------------------------------- /patch/timer/atmega324pa.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit.yaml" 7 | 8 | TC1: 9 | _include: 10 | - "dev/16bit.yaml" 11 | 12 | TC2: 13 | _include: 14 | - "dev/8bit-async.yaml" 15 | -------------------------------------------------------------------------------- /patch/timer/atmega328p.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit.yaml" 7 | 8 | TC1: 9 | _include: 10 | - "dev/16bit.yaml" 11 | 12 | TC2: 13 | _include: 14 | - "dev/8bit-async.yaml" 15 | -------------------------------------------------------------------------------- /patch/timer/atmega328pb.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit.yaml" 7 | 8 | TC1: 9 | _include: 10 | - "dev/16bit.yaml" 11 | 12 | TC2: 13 | _include: 14 | - "dev/8bit-async.yaml" 15 | 16 | TC3: 17 | TCCR3B: 18 | # Merge WGM32 and WGM33 19 | _delete: 20 | - "WGM3*" 21 | _add: 22 | WGM3: 23 | description: Waveform Generation Mode 24 | bitOffset: 3 25 | bitWidth: 2 26 | access: read-write 27 | _include: 28 | - "dev/16bit.yaml" 29 | 30 | TC4: 31 | TCCR4B: 32 | # Merge WGM42 and WGM43 33 | _delete: 34 | - "WGM4*" 35 | _add: 36 | WGM4: 37 | description: Waveform Generation Mode 38 | bitOffset: 3 39 | bitWidth: 2 40 | access: read-write 41 | 42 | _include: 43 | - "dev/16bit.yaml" 44 | 45 | -------------------------------------------------------------------------------- /patch/timer/atmega32u4.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit.yaml" 7 | 8 | TC1,TC3: 9 | _include: 10 | - "dev/16bit.yaml" 11 | 12 | TC4: 13 | _include: 14 | - "dev/10bit.yaml" 15 | -------------------------------------------------------------------------------- /patch/timer/atmega8.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit-mega8.yaml" 7 | 8 | TC1: 9 | _include: 10 | - "dev/16bit-mega8.yaml" 11 | 12 | TC2: 13 | _include: 14 | - "dev/8bit-async-mega8.yaml" 15 | -------------------------------------------------------------------------------- /patch/timer/atmega8u2.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit.yaml" 7 | 8 | TC1: 9 | _include: 10 | - "dev/16bit.yaml" 11 | -------------------------------------------------------------------------------- /patch/timer/attiny13a.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | _modify: 5 | TC0: 6 | description: "Timer/Counter0, 8-bit, PWM" 7 | 8 | TC0: 9 | _include: 10 | - "dev/8bit-tiny8n-tc0.yaml" 11 | -------------------------------------------------------------------------------- /patch/timer/attiny167.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | _modify: 5 | TC1: 6 | description: "Timer/Counter1, 16-bit, PWM" 7 | 8 | TC0: 9 | _include: 10 | - "dev/8bit-tiny167.yaml" 11 | 12 | TC1: 13 | _include: 14 | - "dev/16bit.yaml" 15 | -------------------------------------------------------------------------------- /patch/timer/attiny2313-common.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | TC0: 5 | _include: 6 | - "dev/8bit.yaml" 7 | 8 | TC1: 9 | _include: 10 | - "dev/16bit.yaml" 11 | -------------------------------------------------------------------------------- /patch/timer/attiny828.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | _modify: 5 | TC0: 6 | description: "Timer/Counter0, 8-bit, PWM" 7 | TC1: 8 | description: "Timer/Counter1, 16-bit" 9 | 10 | TC0: 11 | _include: 12 | - "dev/8bit-tiny8n-tc0.yaml" 13 | 14 | TC1: 15 | _include: 16 | - "dev/16bit.yaml" 17 | -------------------------------------------------------------------------------- /patch/timer/attiny84.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | _modify: 5 | TC0: 6 | description: "Timer/Counter0, 8-bit, PWM" 7 | 8 | TC0: 9 | _include: 10 | - "dev/8bit-tiny8n-tc0.yaml" 11 | 12 | TC1: 13 | _include: 14 | - "dev/16bit.yaml" 15 | -------------------------------------------------------------------------------- /patch/timer/attiny841.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | _modify: 5 | TC0: 6 | description: "Timer/Counter0, 8-bit, PWM" 7 | TC1: 8 | description: "Timer/Counter1, 16-bit" 9 | TC2: 10 | description: "Timer/Counter2, 16-bit" 11 | 12 | TC0: 13 | _include: 14 | - "dev/8bit-tiny8n-tc0.yaml" 15 | 16 | TC1,TC2: 17 | _include: 18 | - "dev/16bit.yaml" 19 | -------------------------------------------------------------------------------- /patch/timer/attiny85.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | _modify: 5 | TC0: 6 | description: "Timer/Counter0, 8-bit, PWM" 7 | TC1: 8 | description: "Timer/Counter1, 8-bit" 9 | 10 | TC0: 11 | _include: 12 | - "dev/8bit-tiny8n-tc0.yaml" 13 | 14 | TC1: 15 | _include: 16 | - "dev/8bit-tiny85-tc1.yaml" 17 | -------------------------------------------------------------------------------- /patch/timer/attiny861.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | _modify: 5 | TC0: 6 | description: "Timer/Counter0" 7 | TC1: 8 | description: "Timer/Counter1, 10-bit" 9 | 10 | TC0: 11 | _include: 12 | - "dev/16bit-tiny861-tc0.yaml" 13 | 14 | TC1: 15 | _include: 16 | - "dev/10bit.yaml" 17 | -------------------------------------------------------------------------------- /patch/timer/attiny88.yaml: -------------------------------------------------------------------------------- 1 | # This intermediate file is needed because peripheral-level includes are not 2 | # supported in top-level files. 3 | 4 | _modify: 5 | TC1: 6 | description: "Timer/Counter1, 16-bit, PWM" 7 | 8 | TC0: 9 | _include: 10 | - "dev/8bit-tiny88.yaml" 11 | 12 | TC1: 13 | _include: 14 | - "dev/16bit.yaml" 15 | -------------------------------------------------------------------------------- /patch/timer/dev/10bit.yaml: -------------------------------------------------------------------------------- 1 | TCCR?A,TCCR?C: 2 | _modify: 3 | FOC??: 4 | access: write-only 5 | COM??: 6 | _write_constraint: enum 7 | COM??: 8 | _replace_enum: 9 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 10 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 11 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)"] 12 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)"] 13 | 14 | TCCR?B: 15 | _modify: 16 | CS?: 17 | _write_constraint: enum 18 | CS?: 19 | _replace_enum: 20 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 21 | DIRECT: [1, "Running, No Prescaling"] 22 | PRESCALE_2: [2, "Running, CLK/2"] 23 | PRESCALE_4: [3, "Running, CLK/4"] 24 | PRESCALE_8: [4, "Running, CLK/8"] 25 | PRESCALE_16: [5, "Running, CLK/16"] 26 | PRESCALE_32: [6, "Running, CLK/32"] 27 | PRESCALE_64: [7, "Running, CLK/64"] 28 | PRESCALE_128: [8, "Running, CLK/128"] 29 | PRESCALE_256: [9, "Running, CLK/256"] 30 | PRESCALE_512: [10, "Running, CLK/512"] 31 | PRESCALE_1024: [11, "Running, CLK/1024"] 32 | PRESCALE_2048: [12, "Running, CLK/2048"] 33 | PRESCALE_4096: [13, "Running, CLK/4096"] 34 | PRESCALE_8192: [14, "Running, CLK/8192"] 35 | PRESCALE_16384: [15, "Running, CLK/16384"] 36 | DTPS?: 37 | _replace_enum: 38 | X1: [0, "1x (no division)"] 39 | X2: [1, "2x"] 40 | X4: [2, "4x"] 41 | X8: [3, "8x"] 42 | 43 | TCCR?D: 44 | _modify: 45 | WGM?: 46 | _write_constraint: enum 47 | WGM?: 48 | _replace_enum: 49 | PWM_FAST: [0, "Fast PWM, Update: *TOP*, Flag: *TOP*"] 50 | PWM_CORRECT: [1, "Phase and Frequency Correct PWM, Update: *BOTTOM*, Flag: *BOTTOM*"] 51 | PWM_SINGLE_SLOPE: [2, "PWM6 / Single-slope, Update: *TOP*, Flag: *TOP*"] 52 | PWM_DUAL_SLOPE: [3, "PWM6 / Dual-slope, Update: *BOTTOM*, Flag: *BOTTOM*"] 53 | 54 | _modify: 55 | TC?H: 56 | description: Timer/Counter High Bits 57 | -------------------------------------------------------------------------------- /patch/timer/dev/16bit-mega8.yaml: -------------------------------------------------------------------------------- 1 | TCCR?A: 2 | _modify: 3 | COM?A: 4 | description: "Compare Output A Mode" 5 | _write_constraint: enum 6 | COM?B: 7 | description: "Compare Output B Mode" 8 | _write_constraint: enum 9 | FOC??: 10 | access: write-only 11 | COM??: 12 | _replace_enum: 13 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 14 | MATCH_TOGGLE: [1, "Toggle OC1x on Compare Match (Might depend on WGM)"] 15 | MATCH_CLEAR: [2, "Clear OC1x on Compare Match (If PWM is enabled, OC1x is set at BOTTOM)"] 16 | MATCH_SET: [3, "Set OC1x on Compare Match (If PWM is enabled, OC1x is cleared at BOTTOM)"] 17 | 18 | TCCR?B: 19 | _modify: 20 | CS?: 21 | _write_constraint: enum 22 | CS?: 23 | _replace_enum: 24 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 25 | DIRECT: [1, "Running, No Prescaling"] 26 | PRESCALE_8: [2, "Running, CLK/8"] 27 | PRESCALE_64: [3, "Running, CLK/64"] 28 | PRESCALE_256: [4, "Running, CLK/256"] 29 | PRESCALE_1024: [5, "Running, CLK/1024"] 30 | EXT_FALLING: [6, "Running, ExtClk Tx Falling Edge"] 31 | EXT_RISING: [7, "Running, ExtClk Tx Rising Edge"] 32 | -------------------------------------------------------------------------------- /patch/timer/dev/16bit-tiny861-tc0.yaml: -------------------------------------------------------------------------------- 1 | TCCR?B: 2 | _modify: 3 | CS?: 4 | _write_constraint: enum 5 | CS?: 6 | _replace_enum: 7 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 8 | DIRECT: [1, "Running, No Prescaling"] 9 | PRESCALE_8: [2, "Running, CLK/8"] 10 | PRESCALE_64: [3, "Running, CLK/64"] 11 | PRESCALE_256: [4, "Running, CLK/256"] 12 | PRESCALE_1024: [5, "Running, CLK/1024"] 13 | EXT_FALLING: [6, "Running, ExtClk Tx Falling Edge"] 14 | EXT_RISING: [7, "Running, ExtClk Tx Rising Edge"] 15 | 16 | -------------------------------------------------------------------------------- /patch/timer/dev/16bit.yaml: -------------------------------------------------------------------------------- 1 | TCCR?A: 2 | _modify: 3 | COM??: 4 | _write_constraint: enum 5 | COM??: 6 | _replace_enum: 7 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 8 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 9 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"] 10 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"] 11 | 12 | TCCR?B: 13 | _modify: 14 | CS?: 15 | _write_constraint: enum 16 | CS?: 17 | _replace_enum: 18 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 19 | DIRECT: [1, "Running, No Prescaling"] 20 | PRESCALE_8: [2, "Running, CLK/8"] 21 | PRESCALE_64: [3, "Running, CLK/64"] 22 | PRESCALE_256: [4, "Running, CLK/256"] 23 | PRESCALE_1024: [5, "Running, CLK/1024"] 24 | EXT_FALLING: [6, "Running, ExtClk Tx Falling Edge"] 25 | EXT_RISING: [7, "Running, ExtClk Tx Rising Edge"] 26 | 27 | TCCR?C: 28 | _modify: 29 | FOC??: 30 | access: write-only 31 | -------------------------------------------------------------------------------- /patch/timer/dev/8bit-async-mega8.yaml: -------------------------------------------------------------------------------- 1 | TCCR?: 2 | _modify: 3 | COM?: 4 | _write_constraint: enum 5 | FOC?: 6 | access: write-only 7 | COM?: 8 | _replace_enum: 9 | DISCONNECTED: [0, "Normal port operation, OC2 disconnected"] 10 | MATCH_CLEAR: [2, "Clear OC2 on Compare Match (If PWM is enabled, OC2 is set at BOTTOM)"] 11 | MATCH_SET: [3, "Set OC2 on Compare Match (If PWM is enabled, OC2 is cleared at BOTTOM)"] 12 | CS?: 13 | _replace_enum: 14 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 15 | DIRECT: [1, "Running, No Prescaling"] 16 | PRESCALE_8: [2, "Running, CLK/8"] 17 | PRESCALE_32: [3, "Running, CLK/32"] 18 | PRESCALE_64: [4, "Running, CLK/64"] 19 | PRESCALE_128: [5, "Running, CLK/128"] 20 | PRESCALE_256: [6, "Running, CLK/256"] 21 | PRESCALE_1024: [7, "Running, CLK/1024"] 22 | -------------------------------------------------------------------------------- /patch/timer/dev/8bit-async.yaml: -------------------------------------------------------------------------------- 1 | TCCR?A: 2 | _modify: 3 | COM?A: 4 | description: "Compare Output A Mode" 5 | _write_constraint: enum 6 | COM?B: 7 | description: "Compare Output B Mode" 8 | _write_constraint: enum 9 | WGM?: 10 | _write_constraint: enum 11 | COM??: 12 | _replace_enum: 13 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 14 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 15 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)"] 16 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)"] 17 | WGM?: 18 | _replace_enum: 19 | NORMAL_TOP: [0, "Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*"] 20 | PWM_PHASE: [1, "Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*"] 21 | CTC: [2, "CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*"] 22 | PWM_FAST: [3, "Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*"] 23 | 24 | TCCR?B: 25 | _modify: 26 | WGM?2: 27 | description: "Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)" 28 | FOC??: 29 | access: write-only 30 | CS?: 31 | _replace_enum: 32 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 33 | DIRECT: [1, "Running, No Prescaling"] 34 | PRESCALE_8: [2, "Running, CLK/8"] 35 | PRESCALE_32: [3, "Running, CLK/32"] 36 | PRESCALE_64: [4, "Running, CLK/64"] 37 | PRESCALE_128: [5, "Running, CLK/128"] 38 | PRESCALE_256: [6, "Running, CLK/256"] 39 | PRESCALE_1024: [7, "Running, CLK/1024"] 40 | -------------------------------------------------------------------------------- /patch/timer/dev/8bit-mega8.yaml: -------------------------------------------------------------------------------- 1 | TCCR?: 2 | _delete: 3 | - CS00 4 | - CS01 5 | - CS02 6 | _add: 7 | CS0: 8 | description: "Clock Select 0" 9 | bitRange: "[2:0]" 10 | CS0: 11 | _replace_enum: 12 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 13 | DIRECT: [1, "Running, No Prescaling"] 14 | PRESCALE_8: [2, "Running, CLK/8"] 15 | PRESCALE_64: [3, "Running, CLK/64"] 16 | PRESCALE_256: [4, "Running, CLK/256"] 17 | PRESCALE_1024: [5, "Running, CLK/1024"] 18 | EXT_FALLING: [6, "Running, ExtClk Tx Falling Edge"] 19 | EXT_RISING: [7, "Running, ExtClk Tx Rising Edge"] 20 | -------------------------------------------------------------------------------- /patch/timer/dev/8bit-tiny167.yaml: -------------------------------------------------------------------------------- 1 | TCCR?B: 2 | _modify: 3 | CS?: 4 | _write_constraint: enum 5 | 6 | CS?: 7 | _replace_enum: 8 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 9 | DIRECT: [1, "Running, No Prescaling"] 10 | PRESCALE_8: [2, "Running, CLK/8"] 11 | PRESCALE_32: [3, "Running, CLK/32"] 12 | PRESCALE_64: [4, "Running, CLK/64"] 13 | PRESCALE_128: [5, "Running, CLK/128"] 14 | PRESCALE_256: [6, "Running, CLK/256"] 15 | PRESCALE_1024: [7, "Running, CLK/1024"] 16 | -------------------------------------------------------------------------------- /patch/timer/dev/8bit-tiny85-tc1.yaml: -------------------------------------------------------------------------------- 1 | TCCR?,GTCCR: 2 | COM??: 3 | _replace_enum: 4 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 5 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match"] 6 | MATCH_CLEAR: [2, "Clear OCix on Compare Match"] 7 | MATCH_SET: [3, "Set OCix on Compare Match"] 8 | 9 | TCCR?: 10 | CS?: 11 | _replace_enum: 12 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 13 | DIRECT: [1, "Running, No Prescaling"] 14 | PRESCALE_2: [2, "Running, CLK/2"] 15 | PRESCALE_4: [3, "Running, CLK/4"] 16 | PRESCALE_8: [4, "Running, CLK/8"] 17 | PRESCALE_16: [5, "Running, CLK/16"] 18 | PRESCALE_32: [6, "Running, CLK/32"] 19 | PRESCALE_64: [7, "Running, CLK/64"] 20 | PRESCALE_128: [8, "Running, CLK/128"] 21 | PRESCALE_256: [9, "Running, CLK/256"] 22 | PRESCALE_512: [10, "Running, CLK/512"] 23 | PRESCALE_1024: [11, "Running, CLK/1024"] 24 | PRESCALE_2048: [12, "Running, CLK/2048"] 25 | PRESCALE_4096: [13, "Running, CLK/4096"] 26 | PRESCALE_8192: [14, "Running, CLK/8192"] 27 | PRESCALE_16384: [15, "Running, CLK/16384"] 28 | 29 | _modify: 30 | DT1A: 31 | description: "Dead Time Value Register A" 32 | DT1B: 33 | description: "Dead Time Value Register B" 34 | OCR1A: 35 | description: "Output Compare Register A" 36 | OCR1B: 37 | description: "Output Compare Register B" 38 | OCR1C: 39 | description: "Output Compare Register C" 40 | 41 | GTCCR: 42 | _modify: 43 | FOC??: 44 | access: write-only 45 | 46 | DTPS: 47 | DTPS: 48 | _replace_enum: 49 | DIRECT: [0, "No Prescaling"] 50 | PRESCALE_2: [1, "Division factor 2"] 51 | PRESCALE_4: [2, "Division factor 4"] 52 | PRESCALE_8: [3, "Division factor 8"] 53 | -------------------------------------------------------------------------------- /patch/timer/dev/8bit-tiny88.yaml: -------------------------------------------------------------------------------- 1 | TCCR?A: 2 | CS?: 3 | _replace_enum: 4 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 5 | DIRECT: [1, "Running, No Prescaling"] 6 | PRESCALE_8: [2, "Running, CLK/8"] 7 | PRESCALE_64: [3, "Running, CLK/64"] 8 | PRESCALE_256: [4, "Running, CLK/256"] 9 | PRESCALE_1024: [5, "Running, CLK/1024"] 10 | EXT_FALLING: [6, "Running, ExtClk Tx Falling Edge"] 11 | EXT_RISING: [7, "Running, ExtClk Tx Rising Edge"] 12 | -------------------------------------------------------------------------------- /patch/timer/dev/8bit-tiny8n-tc0.yaml: -------------------------------------------------------------------------------- 1 | TCCR?A: 2 | _modify: 3 | COM?A: 4 | description: "Compare Output A Mode" 5 | _write_constraint: enum 6 | COM?B: 7 | description: "Compare Output B Mode" 8 | _write_constraint: enum 9 | WGM?: 10 | _write_constraint: enum 11 | COM??: 12 | _replace_enum: 13 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 14 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 15 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"] 16 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"] 17 | WGM?: 18 | _replace_enum: 19 | NORMAL_TOP: [0, "Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*"] 20 | PWM_PHASE: [1, "Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*"] 21 | CTC: [2, "CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*"] 22 | PWM_FAST: [3, "Fast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*"] 23 | 24 | TCCR?B: 25 | _modify: 26 | WGM?2: 27 | description: "Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)" 28 | FOC??: 29 | access: write-only 30 | CS?: 31 | _replace_enum: 32 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 33 | DIRECT: [1, "Running, No Prescaling"] 34 | PRESCALE_8: [2, "Running, CLK/8"] 35 | PRESCALE_64: [3, "Running, CLK/64"] 36 | PRESCALE_256: [4, "Running, CLK/256"] 37 | PRESCALE_1024: [5, "Running, CLK/1024"] 38 | EXT_FALLING: [6, "Running, ExtClk Tx Falling Edge"] 39 | EXT_RISING: [7, "Running, ExtClk Tx Rising Edge"] 40 | 41 | _modify: 42 | OCR0A: 43 | description: "Output Compare Register A" 44 | OCR0B: 45 | description: "Output Compare Register B" 46 | -------------------------------------------------------------------------------- /patch/timer/dev/8bit.yaml: -------------------------------------------------------------------------------- 1 | TCCR?A: 2 | _modify: 3 | COM?A: 4 | description: "Compare Output A Mode" 5 | _write_constraint: enum 6 | COM?B: 7 | description: "Compare Output B Mode" 8 | _write_constraint: enum 9 | WGM?: 10 | _write_constraint: enum 11 | COM??: 12 | _replace_enum: 13 | DISCONNECTED: [0, "Normal port operation, OCix disconnected"] 14 | MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"] 15 | MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)"] 16 | MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)"] 17 | WGM?: 18 | _replace_enum: 19 | NORMAL_TOP: [0, "Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*"] 20 | PWM_PHASE: [1, "Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*"] 21 | CTC: [2, "CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*"] 22 | PWM_FAST: [3, "Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*"] 23 | 24 | TCCR?B: 25 | _modify: 26 | WGM?2: 27 | description: "Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)" 28 | FOC??: 29 | access: write-only 30 | CS?: 31 | _replace_enum: 32 | NO_CLOCK: [0, "No clock source (Timer/Counter stopped)"] 33 | DIRECT: [1, "Running, No Prescaling"] 34 | PRESCALE_8: [2, "Running, CLK/8"] 35 | PRESCALE_64: [3, "Running, CLK/64"] 36 | PRESCALE_256: [4, "Running, CLK/256"] 37 | PRESCALE_1024: [5, "Running, CLK/1024"] 38 | EXT_FALLING: [6, "Running, ExtClk Tx Falling Edge"] 39 | EXT_RISING: [7, "Running, ExtClk Tx Rising Edge"] 40 | -------------------------------------------------------------------------------- /src/asm.rs: -------------------------------------------------------------------------------- 1 | //! Assembly instructions 2 | 3 | #[cfg(target_arch = "avr")] 4 | use core::arch::asm; 5 | 6 | /// No Operation 7 | #[inline(always)] 8 | pub fn nop() { 9 | cfg_if::cfg_if! { 10 | if #[cfg(target_arch = "avr")] { 11 | unsafe { asm!("nop") } 12 | } else { 13 | unimplemented!() 14 | } 15 | } 16 | } 17 | 18 | /// Sleep / Wait For Interrupt 19 | #[inline(always)] 20 | pub fn sleep() { 21 | cfg_if::cfg_if! { 22 | if #[cfg(target_arch = "avr")] { 23 | unsafe { asm!("sleep") } 24 | } else { 25 | unimplemented!() 26 | } 27 | } 28 | } 29 | 30 | /// Watchdog Reset 31 | #[inline(always)] 32 | pub fn wdr() { 33 | cfg_if::cfg_if! { 34 | if #[cfg(target_arch = "avr")] { 35 | unsafe { asm!("wdr") } 36 | } else { 37 | unimplemented!() 38 | } 39 | } 40 | } 41 | 42 | /// Get the stack size in bytes, for debbuging. 43 | #[cfg(feature = "rt")] 44 | #[inline(always)] 45 | pub fn get_stack_size() -> usize { 46 | extern "C" { 47 | static __DATA_REGION_ORIGIN__: usize; 48 | static __DATA_REGION_LENGTH__: usize; 49 | } 50 | 51 | use core::ptr::addr_of; 52 | 53 | cfg_if::cfg_if! { 54 | if #[cfg(target_arch = "avr")] { 55 | unsafe { 56 | let data_region_end = addr_of!(__DATA_REGION_ORIGIN__) as usize + addr_of!(__DATA_REGION_LENGTH__) as usize; 57 | let sp: usize; 58 | if data_region_end > u8::MAX as usize { 59 | // Here the stack pointer is 2 bytes. 60 | 61 | let spl: u8; 62 | let sph: u8; 63 | core::arch::asm!( 64 | "in {}, 0x3d", 65 | "in {}, 0x3e", 66 | out(reg) spl, 67 | out(reg) sph, 68 | options(nostack, nomem, pure), 69 | ); 70 | sp = usize::from_le_bytes([spl, sph]); 71 | } else { 72 | // Here the stack pointer is 1 byte. 73 | 74 | let spl: u8; 75 | core::arch::asm!( 76 | "in {}, 0x3d", 77 | out(reg) spl, 78 | options(nostack, nomem, pure), 79 | ); 80 | sp = spl as usize; 81 | } 82 | data_region_end - sp 83 | } 84 | } else { 85 | unimplemented!() 86 | } 87 | } 88 | } 89 | 90 | /// Blocks the program for at least `cycles` CPU cycles. 91 | /// 92 | /// This is intended for very simple delays in low-level drivers, but it 93 | /// has some caveats: 94 | /// 95 | /// - The delay may be significantly longer if an interrupt is serviced at the 96 | /// same time, since the delay loop will not be executing during the interrupt. 97 | /// If you need precise timing, use a hardware timer peripheral instead. 98 | /// 99 | /// - The real-time delay depends on the CPU clock frequency. If you want to 100 | /// conveniently specify a delay value in real-time units like microseconds, 101 | /// then use the `delay` module in the HAL crate for your platform. 102 | #[inline(always)] 103 | pub fn delay_cycles(cycles: u32) { 104 | cfg_if::cfg_if! { 105 | if #[cfg(target_arch = "avr")] { 106 | let mut cycles_bytes = cycles.to_le_bytes(); 107 | // Each loop iteration takes 6 cycles when the branch is taken, 108 | // and 5 cycles when the branch is not taken. 109 | // So, this loop is guaranteed to run for at least `cycles - 1` 110 | // cycles, and there will be approximately 4 cycles before the 111 | // loop to initialize the counting registers. 112 | unsafe { 113 | asm!( 114 | "1:", 115 | "subi {r0}, 6", 116 | "sbci {r1}, 0", 117 | "sbci {r2}, 0", 118 | "sbci {r3}, 0", 119 | "brcc 1b", 120 | 121 | r0 = inout(reg_upper) cycles_bytes[0], 122 | r1 = inout(reg_upper) cycles_bytes[1], 123 | r2 = inout(reg_upper) cycles_bytes[2], 124 | r3 = inout(reg_upper) cycles_bytes[3], 125 | ) 126 | } 127 | } else { 128 | let _ = cycles; 129 | unimplemented!() 130 | } 131 | } 132 | } 133 | -------------------------------------------------------------------------------- /src/devices.rs: -------------------------------------------------------------------------------- 1 | #[allow(renamed_and_removed_lints)] 2 | #[allow(private_no_mangle_statics)] 3 | #[no_mangle] 4 | pub(crate) static mut DEVICE_PERIPHERALS: bool = false; 5 | 6 | /// [AT90CAN128](https://www.microchip.com/wwwproducts/en/AT90CAN128) 7 | #[cfg(feature = "at90can128")] 8 | pub mod at90can128 { 9 | include!(concat!(env!("OUT_DIR"), "/pac/at90can128.rs")); 10 | } 11 | 12 | /// [AT90CAN64](https://www.microchip.com/wwwproducts/en/AT90CAN64) 13 | #[cfg(feature = "at90can64")] 14 | pub mod at90can64 { 15 | include!(concat!(env!("OUT_DIR"), "/pac/at90can64.rs")); 16 | } 17 | 18 | /// [AT90CAN32](https://www.microchip.com/wwwproducts/en/AT90CAN32) 19 | #[cfg(feature = "at90can32")] 20 | pub mod at90can32 { 21 | include!(concat!(env!("OUT_DIR"), "/pac/at90can32.rs")); 22 | } 23 | 24 | /// [AT90USB1286](https://www.microchip.com/wwwproducts/en/AT90USB1286) 25 | #[cfg(feature = "at90usb1286")] 26 | pub mod at90usb1286 { 27 | include!(concat!(env!("OUT_DIR"), "/pac/at90usb1286.rs")); 28 | } 29 | 30 | /// [ATmega1280](https://www.microchip.com/wwwproducts/en/ATmega1280) 31 | #[cfg(feature = "atmega1280")] 32 | pub mod atmega1280 { 33 | include!(concat!(env!("OUT_DIR"), "/pac/atmega1280.rs")); 34 | } 35 | 36 | /// [ATmega1284P](https://www.microchip.com/en-us/product/ATmega1284P) 37 | #[cfg(feature = "atmega1284p")] 38 | pub mod atmega1284p { 39 | include!(concat!(env!("OUT_DIR"), "/pac/atmega1284p.rs")); 40 | } 41 | 42 | /// [ATmega128A](https://www.microchip.com/wwwproducts/en/ATmega128A) 43 | #[cfg(feature = "atmega128a")] 44 | pub mod atmega128a { 45 | include!(concat!(env!("OUT_DIR"), "/pac/atmega128a.rs")); 46 | } 47 | 48 | /// [ATmega128RFA1](https://www.microchip.com/en-us/product/ATmega128RFA1) 49 | #[cfg(feature = "atmega128rfa1")] 50 | pub mod atmega128rfa1 { 51 | include!(concat!(env!("OUT_DIR"), "/pac/atmega128rfa1.rs")); 52 | } 53 | 54 | /// [ATmega16](https://www.microchip.com/wwwproducts/en/ATmega16) 55 | #[cfg(feature = "atmega16")] 56 | pub mod atmega16 { 57 | include!(concat!(env!("OUT_DIR"), "/pac/atmega16.rs")); 58 | } 59 | 60 | /// [ATmega164PA](https://www.microchip.com/en-us/product/ATmega164PA) 61 | #[cfg(feature = "atmega164pa")] 62 | pub mod atmega164pa { 63 | include!(concat!(env!("OUT_DIR"), "/pac/atmega164pa.rs")); 64 | } 65 | 66 | /// [ATmega168](https://www.microchip.com/wwwproducts/en/ATmega168) 67 | #[cfg(feature = "atmega168")] 68 | pub mod atmega168 { 69 | include!(concat!(env!("OUT_DIR"), "/pac/atmega168.rs")); 70 | } 71 | 72 | /// [ATmega16u2](https://www.microchip.com/wwwproducts/en/ATmega16u2) 73 | #[cfg(feature = "atmega16u2")] 74 | pub mod atmega16u2 { 75 | include!(concat!(env!("OUT_DIR"), "/pac/atmega16u2.rs")); 76 | } 77 | 78 | /// [ATmega2560](https://www.microchip.com/wwwproducts/en/ATmega2560) 79 | #[cfg(feature = "atmega2560")] 80 | pub mod atmega2560 { 81 | include!(concat!(env!("OUT_DIR"), "/pac/atmega2560.rs")); 82 | } 83 | 84 | /// [ATmega324PA](https://www.microchip.com/wwwproducts/en/ATmega324PA) 85 | #[cfg(feature = "atmega324pa")] 86 | pub mod atmega324pa { 87 | include!(concat!(env!("OUT_DIR"), "/pac/atmega324pa.rs")); 88 | } 89 | 90 | /// [ATmega328P](https://www.microchip.com/wwwproducts/en/ATmega328P) 91 | #[cfg(feature = "atmega328p")] 92 | pub mod atmega328p { 93 | include!(concat!(env!("OUT_DIR"), "/pac/atmega328p.rs")); 94 | } 95 | 96 | /// [ATmega328PB](https://www.microchip.com/wwwproducts/en/ATmega328PB) 97 | #[cfg(feature = "atmega328pb")] 98 | pub mod atmega328pb { 99 | include!(concat!(env!("OUT_DIR"), "/pac/atmega328pb.rs")); 100 | } 101 | 102 | /// [ATmega32A](https://www.microchip.com/wwwproducts/en/ATmega32A) 103 | #[cfg(feature = "atmega32a")] 104 | pub mod atmega32a { 105 | include!(concat!(env!("OUT_DIR"), "/pac/atmega32a.rs")); 106 | } 107 | 108 | /// [ATmega32u2](https://www.microchip.com/wwwproducts/en/ATmega32u2) 109 | #[cfg(feature = "atmega32u2")] 110 | pub mod atmega32u2 { 111 | include!(concat!(env!("OUT_DIR"), "/pac/atmega32u2.rs")); 112 | } 113 | 114 | /// [ATmega32U4](https://www.microchip.com/wwwproducts/en/ATmega32U4) 115 | #[cfg(feature = "atmega32u4")] 116 | pub mod atmega32u4 { 117 | include!(concat!(env!("OUT_DIR"), "/pac/atmega32u4.rs")); 118 | } 119 | 120 | /// [ATmega3208](https://www.microchip.com/wwwproducts/en/ATmega3208) 121 | #[cfg(feature = "atmega3208")] 122 | pub mod atmega3208 { 123 | include!(concat!(env!("OUT_DIR"), "/pac/atmega3208.rs")); 124 | } 125 | 126 | /// [ATmega3209](https://www.microchip.com/wwwproducts/en/ATmega3209) 127 | #[cfg(feature = "atmega3209")] 128 | pub mod atmega3209 { 129 | include!(concat!(env!("OUT_DIR"), "/pac/atmega3209.rs")); 130 | } 131 | 132 | /// [ATmega4808](https://www.microchip.com/wwwproducts/en/ATmega4808) 133 | #[cfg(feature = "atmega4808")] 134 | pub mod atmega4808 { 135 | include!(concat!(env!("OUT_DIR"), "/pac/atmega4808.rs")); 136 | } 137 | 138 | /// [ATmega4809](https://www.microchip.com/wwwproducts/en/ATmega4809) 139 | #[cfg(feature = "atmega4809")] 140 | pub mod atmega4809 { 141 | include!(concat!(env!("OUT_DIR"), "/pac/atmega4809.rs")); 142 | } 143 | 144 | /// [ATmega48P](https://www.microchip.com/wwwproducts/en/ATmega48P) 145 | #[cfg(feature = "atmega48p")] 146 | pub mod atmega48p { 147 | include!(concat!(env!("OUT_DIR"), "/pac/atmega48p.rs")); 148 | } 149 | 150 | /// [ATmega8](https://www.microchip.com/wwwproducts/en/ATmega8) 151 | #[cfg(feature = "atmega8")] 152 | pub mod atmega8 { 153 | include!(concat!(env!("OUT_DIR"), "/pac/atmega8.rs")); 154 | } 155 | 156 | /// [ATmega8u2](https://www.microchip.com/wwwproducts/en/ATmega8u2) 157 | #[cfg(feature = "atmega8u2")] 158 | pub mod atmega8u2 { 159 | include!(concat!(env!("OUT_DIR"), "/pac/atmega8u2.rs")); 160 | } 161 | 162 | /// [ATmega64](https://www.microchip.com/wwwproducts/en/ATmega64) 163 | #[cfg(feature = "atmega64")] 164 | pub mod atmega64 { 165 | include!(concat!(env!("OUT_DIR"), "/pac/atmega64.rs")); 166 | } 167 | 168 | /// [ATmega644](https://www.microchip.com/wwwproducts/en/ATmega644) 169 | #[cfg(feature = "atmega644")] 170 | pub mod atmega644 { 171 | include!(concat!(env!("OUT_DIR"), "/pac/atmega644.rs")); 172 | } 173 | 174 | /// [ATmega88P](https://www.microchip.com/wwwproducts/en/ATmega88P) 175 | #[cfg(feature = "atmega88p")] 176 | pub mod atmega88p { 177 | include!(concat!(env!("OUT_DIR"), "/pac/atmega88p.rs")); 178 | } 179 | 180 | /// [ATtiny13A](https://www.microchip.com/wwwproducts/en/ATtiny13A) 181 | #[cfg(feature = "attiny13a")] 182 | pub mod attiny13a { 183 | include!(concat!(env!("OUT_DIR"), "/pac/attiny13a.rs")); 184 | } 185 | 186 | /// [ATtiny167](https://www.microchip.com/wwwproducts/en/ATtiny167) 187 | #[cfg(feature = "attiny167")] 188 | pub mod attiny167 { 189 | include!(concat!(env!("OUT_DIR"), "/pac/attiny167.rs")); 190 | } 191 | 192 | /// [ATtiny1606](https://www.microchip.com/wwwproducts/en/ATtiny1606) 193 | #[cfg(feature = "attiny1606")] 194 | pub mod attiny1606 { 195 | include!(concat!(env!("OUT_DIR"), "/pac/attiny1606.rs")); 196 | } 197 | 198 | /// [ATtiny1604](https://www.microchip.com/wwwproducts/en/ATtiny1604) 199 | #[cfg(feature = "attiny1604")] 200 | pub mod attiny1604 { 201 | include!(concat!(env!("OUT_DIR"), "/pac/attiny1604.rs")); 202 | } 203 | 204 | /// [ATtiny1614](https://www.microchip.com/wwwproducts/en/ATtiny1614) 205 | #[cfg(feature = "attiny1614")] 206 | pub mod attiny1614 { 207 | include!(concat!(env!("OUT_DIR"), "/pac/attiny1614.rs")); 208 | } 209 | 210 | /// [ATtiny1626](https://www.microchip.com/wwwproducts/en/ATtiny1626) 211 | #[cfg(feature = "attiny1626")] 212 | pub mod attiny1626 { 213 | include!(concat!(env!("OUT_DIR"), "/pac/attiny1626.rs")); 214 | } 215 | 216 | /// [ATtiny202](https://www.microchip.com/wwwproducts/en/ATtiny202) 217 | #[cfg(feature = "attiny202")] 218 | pub mod attiny202 { 219 | include!(concat!(env!("OUT_DIR"), "/pac/attiny202.rs")); 220 | } 221 | 222 | /// [ATtiny204](https://www.microchip.com/wwwproducts/en/ATtiny204) 223 | #[cfg(feature = "attiny204")] 224 | pub mod attiny204 { 225 | include!(concat!(env!("OUT_DIR"), "/pac/attiny204.rs")); 226 | } 227 | 228 | /// [ATtiny212](https://www.microchip.com/wwwproducts/en/ATtiny212) 229 | #[cfg(feature = "attiny212")] 230 | pub mod attiny212 { 231 | include!(concat!(env!("OUT_DIR"), "/pac/attiny212.rs")); 232 | } 233 | 234 | /// [ATtiny214](https://www.microchip.com/wwwproducts/en/ATtiny214) 235 | #[cfg(feature = "attiny214")] 236 | pub mod attiny214 { 237 | include!(concat!(env!("OUT_DIR"), "/pac/attiny214.rs")); 238 | } 239 | 240 | /// [ATtiny2313](https://www.microchip.com/wwwproducts/en/ATtiny2313) 241 | #[cfg(feature = "attiny2313")] 242 | pub mod attiny2313 { 243 | include!(concat!(env!("OUT_DIR"), "/pac/attiny2313.rs")); 244 | } 245 | 246 | /// [ATtiny2313A](https://www.microchip.com/wwwproducts/en/ATtiny2313A) 247 | #[cfg(feature = "attiny2313a")] 248 | pub mod attiny2313a { 249 | include!(concat!(env!("OUT_DIR"), "/pac/attiny2313a.rs")); 250 | } 251 | 252 | /// [ATtiny26](https://www.microchip.com/wwwproducts/en/ATtiny26) 253 | #[cfg(feature = "attiny26")] 254 | pub mod attiny26 { 255 | include!(concat!(env!("OUT_DIR"), "/pac/attiny26.rs")); 256 | } 257 | 258 | /// [ATtiny261a](https://www.microchip.com/wwwproducts/en/ATtiny261a) 259 | #[cfg(feature = "attiny261a")] 260 | pub mod attiny261a { 261 | include!(concat!(env!("OUT_DIR"), "/pac/attiny261a.rs")); 262 | } 263 | 264 | /// [ATtiny402](https://www.microchip.com/en-us/product/ATTINY402) 265 | #[cfg(feature = "attiny402")] 266 | pub mod attiny402 { 267 | include!(concat!(env!("OUT_DIR"), "/pac/attiny402.rs")); 268 | } 269 | 270 | /// [ATtiny404](https://www.microchip.com/en-us/product/ATTINY404) 271 | #[cfg(feature = "attiny404")] 272 | pub mod attiny404 { 273 | include!(concat!(env!("OUT_DIR"), "/pac/attiny404.rs")); 274 | } 275 | 276 | /// [ATtiny412](https://www.microchip.com/wwwproducts/en/ATtiny412) 277 | #[cfg(feature = "attiny412")] 278 | pub mod attiny412 { 279 | include!(concat!(env!("OUT_DIR"), "/pac/attiny412.rs")); 280 | } 281 | 282 | /// [ATtiny414](https://www.microchip.com/wwwproducts/en/ATtiny414) 283 | #[cfg(feature = "attiny414")] 284 | pub mod attiny414 { 285 | include!(concat!(env!("OUT_DIR"), "/pac/attiny414.rs")); 286 | } 287 | 288 | /// [ATtiny416](https://www.microchip.com/wwwproducts/en/ATtiny416) 289 | #[cfg(feature = "attiny416")] 290 | pub mod attiny416 { 291 | include!(concat!(env!("OUT_DIR"), "/pac/attiny416.rs")); 292 | } 293 | 294 | /// [ATtiny44a](https://www.microchip.com/en-us/product/ATtiny44a) 295 | #[cfg(feature = "attiny44a")] 296 | pub mod attiny44a { 297 | include!(concat!(env!("OUT_DIR"), "/pac/attiny44a.rs")); 298 | } 299 | 300 | /// [ATtiny461a](https://www.microchip.com/en-us/product/ATtiny461a) 301 | #[cfg(feature = "attiny461a")] 302 | pub mod attiny461a { 303 | include!(concat!(env!("OUT_DIR"), "/pac/attiny461a.rs")); 304 | } 305 | 306 | /// [ATtiny804](https://www.microchip.com/wwwproducts/en/ATtiny804) 307 | #[cfg(feature = "attiny804")] 308 | pub mod attiny804 { 309 | include!(concat!(env!("OUT_DIR"), "/pac/attiny804.rs")); 310 | } 311 | 312 | /// [ATtiny816](https://www.microchip.com/wwwproducts/en/ATtiny816) 313 | #[cfg(feature = "attiny816")] 314 | pub mod attiny816 { 315 | include!(concat!(env!("OUT_DIR"), "/pac/attiny816.rs")); 316 | } 317 | 318 | /// [ATtiny828](https://www.microchip.com/wwwproducts/en/ATtiny828) 319 | #[cfg(feature = "attiny828")] 320 | pub mod attiny828 { 321 | include!(concat!(env!("OUT_DIR"), "/pac/attiny828.rs")); 322 | } 323 | 324 | /// [ATtiny84](https://www.microchip.com/wwwproducts/en/ATtiny84) 325 | #[cfg(feature = "attiny84")] 326 | pub mod attiny84 { 327 | include!(concat!(env!("OUT_DIR"), "/pac/attiny84.rs")); 328 | } 329 | 330 | /// [ATtiny841](https://www.microchip.com/wwwproducts/en/ATtiny841) 331 | #[cfg(feature = "attiny841")] 332 | pub mod attiny841 { 333 | include!(concat!(env!("OUT_DIR"), "/pac/attiny841.rs")); 334 | } 335 | 336 | /// [ATtiny84a](https://www.microchip.com/en-us/product/ATtiny84a) 337 | #[cfg(feature = "attiny84a")] 338 | pub mod attiny84a { 339 | include!(concat!(env!("OUT_DIR"), "/pac/attiny84a.rs")); 340 | } 341 | 342 | /// [ATtiny85](https://www.microchip.com/wwwproducts/en/ATtiny85) 343 | #[cfg(feature = "attiny85")] 344 | pub mod attiny85 { 345 | include!(concat!(env!("OUT_DIR"), "/pac/attiny85.rs")); 346 | } 347 | 348 | /// [ATtiny861](https://www.microchip.com/wwwproducts/en/ATtiny861) 349 | #[cfg(feature = "attiny861")] 350 | pub mod attiny861 { 351 | include!(concat!(env!("OUT_DIR"), "/pac/attiny861.rs")); 352 | } 353 | 354 | /// [ATtiny861a](https://www.microchip.com/wwwproducts/en/ATtiny861a) 355 | #[cfg(feature = "attiny861a")] 356 | pub mod attiny861a { 357 | include!(concat!(env!("OUT_DIR"), "/pac/attiny861a.rs")); 358 | } 359 | 360 | /// [ATtiny88](https://www.microchip.com/wwwproducts/en/ATtiny88) 361 | #[cfg(feature = "attiny88")] 362 | pub mod attiny88 { 363 | include!(concat!(env!("OUT_DIR"), "/pac/attiny88.rs")); 364 | } 365 | 366 | /// [AVR64DU32](https://www.microchip.com/wwwproducts/en/AVR64DU32) 367 | #[cfg(feature = "avr64du32")] 368 | pub mod avr64du32 { 369 | include!(concat!(env!("OUT_DIR"), "/pac/avr64du32.rs")); 370 | } 371 | 372 | /// [AVR64DU28](https://www.microchip.com/wwwproducts/en/AVR64DU28) 373 | #[cfg(feature = "avr64du28")] 374 | pub mod avr64du28 { 375 | include!(concat!(env!("OUT_DIR"), "/pac/avr64du28.rs")); 376 | } 377 | 378 | /// [AVR128DB28](https://www.microchip.com/wwwproducts/en/AVR128DB28) 379 | #[cfg(feature = "avr128db28")] 380 | pub mod avr128db28 { 381 | include!(concat!(env!("OUT_DIR"), "/pac/avr128db28.rs")); 382 | } 383 | -------------------------------------------------------------------------------- /src/interrupt.rs: -------------------------------------------------------------------------------- 1 | //! Chip-Generic Interrupt Utilities 2 | //! 3 | //! For the most part, [crate::interrupt::free] is what you want: 4 | //! 5 | //! ``` 6 | //! avr_device::interrupt::free(|cs| { 7 | //! // Interrupts are disabled here 8 | //! }); 9 | //! ``` 10 | //! 11 | //! To access shared state, Mutex can be used: 12 | //! 13 | //! ``` 14 | //! use avr_device::interrupt::Mutex; 15 | //! use core::cell::Cell; 16 | //! 17 | //! // Use Cell, if the wrapped type is Copy. 18 | //! // Use RefCell, if the wrapped type is not Copy or if you need a reference to it for other reasons. 19 | //! static MYGLOBAL: Mutex> = Mutex::new(Cell::new(0)); 20 | //! 21 | //! fn my_fun() { 22 | //! avr_device::interrupt::free(|cs| { 23 | //! // Interrupts are disabled here 24 | //! 25 | //! // Acquire mutex to global variable. 26 | //! let myglobal_ref = MYGLOBAL.borrow(cs); 27 | //! // Write to the global variable. 28 | //! myglobal_ref.set(42); 29 | //! }); 30 | //! } 31 | //! ``` 32 | 33 | pub use bare_metal::{CriticalSection, Mutex}; 34 | 35 | #[cfg(target_arch = "avr")] 36 | use core::arch::asm; 37 | 38 | /// Opaque structure for storing the global interrupt flag status. 39 | /// 40 | /// This structure does not implement `Copy` and `Clone`, 41 | /// because the user shall not duplicate and pass it twice to [crate::interrupt::restore]. 42 | #[derive(Debug)] 43 | #[cfg_attr(feature = "ufmt", derive(ufmt::derive::uDebug))] 44 | pub struct IrqFlag { 45 | // The saved SREG. 46 | sreg: u8, 47 | } 48 | 49 | impl IrqFlag { 50 | #[inline(always)] 51 | fn new(sreg: u8) -> IrqFlag { 52 | IrqFlag { sreg } 53 | } 54 | 55 | /// Check the status of the saved global interrupt flag. 56 | /// 57 | /// Returns true, if the saved global interrupt flag is set (IRQs enabled). 58 | /// Otherwise returns false. 59 | /// 60 | /// This method can be used to check whether interrupts were enabled 61 | /// before the [crate::interrupt::disable_save] call. 62 | /// You probably shouldn't make your program behavior dependent on this state. 63 | /// Consider using a different design. 64 | #[inline(always)] 65 | pub fn enabled(&self) -> bool { 66 | self.sreg & 0x80 != 0 67 | } 68 | } 69 | 70 | /// Disable the global interrupt flag. 71 | /// 72 | /// *Hint*: Most of the time you probably don't want to use this function directly. 73 | /// Consider creating a critical section with [crate::interrupt::free] instead. 74 | /// 75 | /// This function is an optimization fence. 76 | /// That means memory accesses will not be re-ordered by the compiler across this function call. 77 | #[inline(always)] 78 | pub fn disable() { 79 | cfg_if::cfg_if! { 80 | if #[cfg(target_arch = "avr")] { 81 | // Disable interrupts 82 | unsafe { asm!("cli") }; 83 | } else { 84 | unimplemented!() 85 | } 86 | } 87 | } 88 | 89 | /// Disable the global interrupt flag and return an opaque representation of the previous flag status. 90 | /// 91 | /// *Hint*: Most of the time you probably don't want to use this function directly. 92 | /// Consider creating a critical section with [crate::interrupt::free] instead. 93 | /// 94 | /// This function is an optimization fence. 95 | /// That means memory accesses will not be re-ordered by the compiler across this function call. 96 | /// 97 | /// Returns an object that contains the status of the global interrupt flag from *before* the `disable_save()` call. 98 | /// This object shall later be passed to the [crate::interrupt::restore] function. 99 | #[inline(always)] 100 | #[allow(unreachable_code)] 101 | pub fn disable_save() -> IrqFlag { 102 | let sreg; 103 | cfg_if::cfg_if! { 104 | if #[cfg(target_arch = "avr")] { 105 | // Store current state 106 | unsafe { 107 | asm!( 108 | "in {sreg}, 0x3F", 109 | sreg = out(reg) sreg, 110 | ) 111 | }; 112 | } else { 113 | let _ = sreg; 114 | unimplemented!() 115 | } 116 | } 117 | // Disable interrupts 118 | disable(); 119 | 120 | IrqFlag::new(sreg) 121 | } 122 | 123 | /// Enable the global interrupt flag. 124 | /// 125 | /// *Warning*: This function enables interrupts, no matter what the enable-state was before [crate::interrupt::disable]. 126 | /// Especially in library code, where the previous interrupt state may be unknown, 127 | /// this function call shall be avoided. 128 | /// Most of the time you probably don't want to use this function directly. 129 | /// Consider creating a critical section with [crate::interrupt::free] instead. 130 | /// 131 | /// This function is an optimization fence. 132 | /// That means memory accesses will not be re-ordered by the compiler across this function call. 133 | /// 134 | /// # Safety 135 | /// 136 | /// - Do not call this function inside an [crate::interrupt::free] critical section 137 | #[inline(always)] 138 | pub unsafe fn enable() { 139 | cfg_if::cfg_if! { 140 | if #[cfg(target_arch = "avr")] { 141 | asm!("sei"); 142 | } else { 143 | unimplemented!() 144 | } 145 | } 146 | } 147 | 148 | /// Restore the global interrupt flag to its previous state before [crate::interrupt::disable_save]. 149 | /// 150 | /// *Hint*: Most of the time you probably don't want to use this function directly. 151 | /// Consider creating a critical section with [crate::interrupt::free] instead. 152 | /// 153 | /// This function is an optimization fence. 154 | /// That means memory accesses will not be re-ordered by the compiler across this function call. 155 | /// 156 | /// # Safety 157 | /// 158 | /// - If you call this function inside of a [crate::interrupt::free] critical section, the 159 | /// corresponding [crate::interrupt::disable_save] must also be in the same critical section. 160 | /// - If you nest multiple [crate::interrupt::disable_save] + [crate::interrupt::restore] 161 | /// sequences, the [crate::interrupt::restore] must be called in the reverse order of the 162 | /// [crate::interrupt::disable_save] call order. 163 | /// That means the first saved IrqFlag must be restored last. 164 | #[inline(always)] 165 | pub unsafe fn restore(irq_flag: IrqFlag) { 166 | cfg_if::cfg_if! { 167 | if #[cfg(target_arch = "avr")] { 168 | // Restore global interrupt flag in SREG. 169 | // This also clobbers all other bits in SREG. 170 | asm!( 171 | "out 0x3F, {sreg}", 172 | sreg = in(reg) irq_flag.sreg, 173 | ); 174 | } else { 175 | let _ = irq_flag; 176 | unimplemented!() 177 | } 178 | } 179 | } 180 | 181 | /// Check whether the global interrupt flag is currently enabled (in SREG). 182 | /// 183 | /// *Warning*: You shouldn't use this to hand craft your own memory/interrupt safety mechanisms. 184 | /// This function may be used for things such as deciding whether to do 185 | /// expensive calculations in library code, or similar things. 186 | /// 187 | /// This function is **not** an optimization fence. 188 | /// That means memory accesses *can* be re-ordered by the compiler across this function call. 189 | #[inline(always)] 190 | #[allow(unreachable_code)] 191 | pub fn is_enabled() -> bool { 192 | let sreg; 193 | cfg_if::cfg_if! { 194 | if #[cfg(target_arch = "avr")] { 195 | // Store current state 196 | unsafe { 197 | asm!( 198 | "in {sreg}, 0x3F", 199 | sreg = out(reg) sreg, 200 | options(readonly, preserves_flags, nostack), 201 | ) 202 | }; 203 | } else { 204 | let _ = sreg; 205 | unimplemented!() 206 | } 207 | } 208 | 209 | IrqFlag::new(sreg).enabled() 210 | } 211 | 212 | /// Execute closure `f` in an interrupt-free context. 213 | /// 214 | /// This is also known as a "critical section". 215 | #[inline(always)] 216 | pub fn free(f: F) -> R 217 | where 218 | F: FnOnce(CriticalSection) -> R, 219 | { 220 | cfg_if::cfg_if! { 221 | if #[cfg(target_arch = "avr")] { 222 | // Disable interrupts. This is an optimization fence. 223 | let irq_flag = disable_save(); 224 | 225 | let r = f(unsafe { CriticalSection::new() }); 226 | 227 | // Restore interrupt state. This is an optimization fence. 228 | unsafe { restore(irq_flag); } 229 | 230 | r 231 | } else { 232 | let _ = f; 233 | unimplemented!() 234 | } 235 | } 236 | } 237 | 238 | #[cfg(feature = "critical-section")] 239 | mod cs { 240 | use critical_section::RawRestoreState; 241 | 242 | struct AvrCriticalSection; 243 | critical_section::set_impl!(AvrCriticalSection); 244 | 245 | unsafe impl critical_section::Impl for AvrCriticalSection { 246 | unsafe fn acquire() -> RawRestoreState { 247 | crate::interrupt::disable_save().sreg 248 | } 249 | 250 | unsafe fn release(restore_state: RawRestoreState) { 251 | crate::interrupt::restore(crate::interrupt::IrqFlag::new(restore_state)) 252 | } 253 | } 254 | } 255 | -------------------------------------------------------------------------------- /vendor/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2018 Microchip Technology Inc. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the Licence at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | -------------------------------------------------------------------------------- /vendor/README.md: -------------------------------------------------------------------------------- 1 | Vendored ATDF Files 2 | =================== 3 | 4 | These atdfs were downloaded from and are kept in here to be converted to *svd* using [atdf2svd](https://github.com/Rahix/atdf2svd) and later to rust using [svd2rust](https://github.com/rust-embedded/svd2rust). 5 | 6 | Please keep in mind that the names of these files have to be exactly the same as the names of the rust modules (ie `atmega32u4` instead of `ATmega32U4`). 7 | 8 | ## License 9 | The *atdf* files in this directory are licensed under the Apache License, Version 2.0 ([LICENSE-VENDOR](./LICENSE)). 10 | --------------------------------------------------------------------------------