├── README.md ├── RSA.cache └── wt │ ├── java_command_handlers.wdf │ ├── project.wpc │ ├── synthesis.wdf │ ├── webtalk_pa.xml │ └── xsim.wdf ├── RSA.hw ├── RSA.lpr └── webtalk │ ├── .xsim_webtallk.info │ ├── labtool_webtalk.log │ ├── usage_statistics_ext_labtool.html │ └── usage_statistics_ext_labtool.xml ├── RSA.ip_user_files └── README.txt ├── RSA.sim └── sim_1 │ └── behav │ ├── compile.bat │ ├── compile.log │ ├── elaborate.bat │ ├── elaborate.log │ ├── glbl.v │ ├── simulate.bat │ ├── simulate.log │ ├── tb_main.tcl │ ├── tb_main_behav.wdb │ ├── tb_main_vlog.prj │ ├── webtalk.jou │ ├── webtalk.log │ ├── webtalk_4860.backup.jou │ ├── webtalk_4860.backup.log │ ├── xelab.pb │ ├── xsim.dir │ ├── tb_main_behav │ │ ├── Compile_Options.txt │ │ ├── TempBreakPointFile.txt │ │ ├── xsim.dbg │ │ ├── xsim.mem │ │ ├── xsim.reloc │ │ ├── xsim.rtti │ │ ├── xsim.svtype │ │ ├── xsim.type │ │ ├── xsim.xdbg │ │ ├── xsimcrash.log │ │ ├── xsimk.exe │ │ └── xsimkernel.log │ ├── xil_defaultlib │ │ ├── control.sdb │ │ ├── glbl.sdb │ │ ├── inverter.sdb │ │ ├── mod.sdb │ │ ├── mod_exp.sdb │ │ ├── tb_main.sdb │ │ └── xil_defaultlib.rlx │ └── xsim.svtype │ ├── xsim.ini │ ├── xvlog.log │ └── xvlog.pb ├── RSA.srcs ├── sim_1 │ └── new │ │ ├── mod_tb.v │ │ ├── tb_inverter.v │ │ ├── tb_main.v │ │ └── tb_mod_exp.v └── sources_1 │ └── new │ ├── control.v │ ├── dff.v │ ├── divider.v │ ├── inverter.v │ ├── mod.v │ ├── mod_exp.v │ └── mux.v ├── RSA.xpr ├── archive_project_summary.txt ├── vivado.jou └── vivado.log /README.md: -------------------------------------------------------------------------------- 1 | # RSA Cryptosystem implementation in Verilog 2 | 3 | Modules include 4 | - Modular Inverter 5 | - Modular Exponentiator 6 | - Divider 7 | -------------------------------------------------------------------------------- /RSA.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 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70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203235352c20323634:31:00:00 77 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203235382c20323631:31:00:00 78 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203331382c20313135:31:00:00 79 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630302c20323632:32:00:00 80 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630302c20323634:31:00:00 81 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630302c20323635:31:00:00 82 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630302c20323636:31:00:00 83 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630312c20323632:31:00:00 84 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630312c20323633:31:00:00 85 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630322c20323633:32:00:00 86 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630332c203132382c2066616c73652c2066616c73652c2066616c73652c2066616c73652c2074727565:31:00:00 87 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630332c20313239:31:00:00 88 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74625f6d61696e2e762c203630332c20323637:31:00:00 89 | eof:4271969805 90 | -------------------------------------------------------------------------------- /RSA.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:23 3 | eof: 4 | -------------------------------------------------------------------------------- /RSA.cache/wt/synthesis.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 3 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:72746c5f31:00:00 4 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 5 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 6 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 7 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 8 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 9 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 10 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 11 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 12 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 13 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:5b7370656369666965645d:00:00 14 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 15 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 16 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 17 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 18 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 19 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 20 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 21 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 22 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 23 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 24 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 25 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 26 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 27 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 28 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 29 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 30 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 31 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 32 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 33 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 34 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 35 | eof:3025419679 36 | -------------------------------------------------------------------------------- /RSA.cache/wt/webtalk_pa.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 |
11 |
12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 |
135 | 136 | 137 | -------------------------------------------------------------------------------- /RSA.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:241934075 5 | -------------------------------------------------------------------------------- /RSA.hw/RSA.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /RSA.hw/webtalk/.xsim_webtallk.info: -------------------------------------------------------------------------------- 1 | 1468768967 2 | 0 3 | 2 4 | 0 5 | 4f764db9-066d-449b-9ecf-054e1d08f457 6 | -------------------------------------------------------------------------------- /RSA.hw/webtalk/labtool_webtalk.log: -------------------------------------------------------------------------------- 1 | 2 | ****** Webtalk v2016.2 (64-bit) 3 | **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 6 | 7 | source G:/study/verilog/RSA/RSAfinal/.Xil/Vivado-2804-dell/PrjAr/_X_/RSA.hw/webtalk/labtool_webtalk.tcl -notrace 8 | INFO: [Common 17-206] Exiting Webtalk at Sun Jul 17 20:52:48 2016... 9 | -------------------------------------------------------------------------------- /RSA.hw/webtalk/usage_statistics_ext_labtool.html: -------------------------------------------------------------------------------- 1 | Device Usage Statistics Report 2 |

LABTOOL Usage Report


3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
software_version_and_target_device
betaFALSEbuild_version1577090
date_generatedSun Jul 17 20:52:47 2016os_platformWIN64
product_versionVivado v2016.2 (64-bit)project_id4f764db9-066d-449b-9ecf-054e1d08f457
project_iteration1random_id47de97f2-7adf-4dcf-838c-544cedf0f651
registration_id47de97f2-7adf-4dcf-838c-544cedf0f651route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowlabtool

21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 |
user_environment
cpu_nameIntel(R) Core(TM) i7-4500U CPU @ 1.80GHzcpu_speed2394 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

30 | 31 | 32 |
vivado_usage

33 | 34 | 35 | 42 |
labtool
36 | 37 | 38 | 39 | 40 |
usage
cable=pgmcnt=00:00:00
41 |

43 | 44 | 45 | -------------------------------------------------------------------------------- /RSA.hw/webtalk/usage_statistics_ext_labtool.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 |
4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
21 |
22 | 23 | 24 | 25 | 26 | 27 | 28 |
29 |
30 |
31 | 32 | 33 |
34 |
35 |
36 |
37 |
38 | 39 | -------------------------------------------------------------------------------- /RSA.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | set xv_path=G:\\xilinx_vivado\\Vivado\\2016.2\\bin 3 | echo "xvlog -m64 --relax -prj tb_main_vlog.prj" 4 | call %xv_path%/xvlog -m64 --relax -prj tb_main_vlog.prj -log xvlog.log 5 | call type xvlog.log > compile.log 6 | if "%errorlevel%"=="1" goto END 7 | if "%errorlevel%"=="0" goto SUCCESS 8 | :END 9 | exit 1 10 | :SUCCESS 11 | exit 0 12 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/compile.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module mod 3 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v:4] 4 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v:5] 5 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v:6] 6 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v:7] 7 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v" into library xil_defaultlib 8 | INFO: [VRFC 10-311] analyzing module mod_exp 9 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v:7] 10 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v:8] 11 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v:9] 12 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v:13] 13 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v" into library xil_defaultlib 14 | INFO: [VRFC 10-311] analyzing module inverter 15 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v:9] 16 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v:10] 17 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v:14] 18 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v:15] 19 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/control.v" into library xil_defaultlib 20 | INFO: [VRFC 10-311] analyzing module control 21 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/control.v:3] 22 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/control.v:8] 23 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/control.v:9] 24 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sim_1/new/tb_main.v" into library xil_defaultlib 25 | INFO: [VRFC 10-311] analyzing module tb_main 26 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/glbl.v" into library xil_defaultlib 27 | INFO: [VRFC 10-311] analyzing module glbl 28 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | set xv_path=G:\\xilinx_vivado\\Vivado\\2016.2\\bin 3 | call %xv_path%/xelab -wto cfd6a0fdc80e41e2bc5f7cabcb165e64 -m64 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_main_behav xil_defaultlib.tb_main xil_defaultlib.glbl -log elaborate.log 4 | if "%errorlevel%"=="0" goto SUCCESS 5 | if "%errorlevel%"=="1" goto END 6 | :END 7 | exit 1 8 | :SUCCESS 9 | exit 0 10 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2016.2 2 | Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. 3 | Running: G:/xilinx_vivado/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto cfd6a0fdc80e41e2bc5f7cabcb165e64 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_main_behav xil_defaultlib.tb_main xil_defaultlib.glbl -log elaborate.log 4 | Using 2 slave threads. 5 | Starting static elaboration 6 | WARNING: [VRFC 10-278] actual bit length 256 differs from formal bit length 512 for port msg_out [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sim_1/new/tb_main.v:10] 7 | Completed static elaboration 8 | Starting simulation data flow analysis 9 | Completed simulation data flow analysis 10 | Time Resolution for simulation is 1ps 11 | Compiling module xil_defaultlib.mod(WIDTH=512) 12 | Compiling module xil_defaultlib.inverter(WIDTH=256) 13 | Compiling module xil_defaultlib.mod_exp(WIDTH=256) 14 | Compiling module xil_defaultlib.control(WIDTH=256) 15 | Compiling module xil_defaultlib.tb_main 16 | Compiling module xil_defaultlib.glbl 17 | Built simulation snapshot tb_main_behav 18 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | 11 | //-------- STARTUP Globals -------------- 12 | wire GSR; 13 | wire GTS; 14 | wire GWE; 15 | wire PRLD; 16 | tri1 p_up_tmp; 17 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 18 | 19 | wire PROGB_GLBL; 20 | wire CCLKO_GLBL; 21 | wire FCSBO_GLBL; 22 | wire [3:0] DO_GLBL; 23 | wire [3:0] DI_GLBL; 24 | 25 | reg GSR_int; 26 | reg GTS_int; 27 | reg PRLD_int; 28 | 29 | //-------- JTAG Globals -------------- 30 | wire JTAG_TDO_GLBL; 31 | wire JTAG_TCK_GLBL; 32 | wire JTAG_TDI_GLBL; 33 | wire JTAG_TMS_GLBL; 34 | wire JTAG_TRST_GLBL; 35 | 36 | reg JTAG_CAPTURE_GLBL; 37 | reg JTAG_RESET_GLBL; 38 | reg JTAG_SHIFT_GLBL; 39 | reg JTAG_UPDATE_GLBL; 40 | reg JTAG_RUNTEST_GLBL; 41 | 42 | reg JTAG_SEL1_GLBL = 0; 43 | reg JTAG_SEL2_GLBL = 0 ; 44 | reg JTAG_SEL3_GLBL = 0; 45 | reg JTAG_SEL4_GLBL = 0; 46 | 47 | reg JTAG_USER_TDO1_GLBL = 1'bz; 48 | reg JTAG_USER_TDO2_GLBL = 1'bz; 49 | reg JTAG_USER_TDO3_GLBL = 1'bz; 50 | reg JTAG_USER_TDO4_GLBL = 1'bz; 51 | 52 | assign (weak1, weak0) GSR = GSR_int; 53 | assign (weak1, weak0) GTS = GTS_int; 54 | assign (weak1, weak0) PRLD = PRLD_int; 55 | 56 | initial begin 57 | GSR_int = 1'b1; 58 | PRLD_int = 1'b1; 59 | #(ROC_WIDTH) 60 | GSR_int = 1'b0; 61 | PRLD_int = 1'b0; 62 | end 63 | 64 | initial begin 65 | GTS_int = 1'b1; 66 | #(TOC_WIDTH) 67 | GTS_int = 1'b0; 68 | end 69 | 70 | endmodule 71 | `endif 72 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | set xv_path=G:\\xilinx_vivado\\Vivado\\2016.2\\bin 3 | call %xv_path%/xsim tb_main_behav -key {Behavioral:sim_1:Functional:tb_main} -tclbatch tb_main.tcl -log simulate.log 4 | if "%errorlevel%"=="0" goto SUCCESS 5 | if "%errorlevel%"=="1" goto END 6 | :END 7 | exit 1 8 | :SUCCESS 9 | exit 0 10 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/simulate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2016.2 2 | Time resolution is 1 ps 3 | $finish called at time : 3 us : File "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sim_1/new/tb_main.v" Line 22 4 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/tb_main.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 3000ns 12 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/tb_main_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Rajandeep/RSA-CRYPTOSYSTEM-using-verilog/023ff53d053ac1182f7ea311d88b114ac96a3fc6/RSA.sim/sim_1/behav/tb_main_behav.wdb -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/tb_main_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib "../../../RSA.srcs/sources_1/new/mod.v" 3 | verilog xil_defaultlib "../../../RSA.srcs/sources_1/new/mod_exp.v" 4 | verilog xil_defaultlib "../../../RSA.srcs/sources_1/new/inverter.v" 5 | verilog xil_defaultlib "../../../RSA.srcs/sources_1/new/control.v" 6 | verilog xil_defaultlib "../../../RSA.srcs/sim_1/new/tb_main.v" 7 | 8 | # compile glbl module 9 | verilog xil_defaultlib "glbl.v" 10 | 11 | # Do not sort compile order 12 | nosort 13 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Fri Jul 08 10:46:28 2016 6 | # Process ID: 7100 7 | # Current directory: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/webtalk.log 10 | # Journal file: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/webtalk.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Fri Jul 08 10:46:28 2016 6 | # Process ID: 7100 7 | # Current directory: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/webtalk.log 10 | # Journal file: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Fri Jul 08 10:46:28 2016... 14 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/webtalk_4860.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Fri Jul 08 10:42:56 2016 6 | # Process ID: 4860 7 | # Current directory: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/webtalk.log 10 | # Journal file: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/webtalk_4860.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Fri Jul 08 10:42:56 2016 6 | # Process ID: 4860 7 | # Current directory: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/webtalk.log 10 | # Journal file: C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Fri Jul 08 10:42:56 2016... 14 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Rajandeep/RSA-CRYPTOSYSTEM-using-verilog/023ff53d053ac1182f7ea311d88b114ac96a3fc6/RSA.sim/sim_1/behav/xelab.pb -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "cfd6a0fdc80e41e2bc5f7cabcb165e64" --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_main_behav" "xil_defaultlib.tb_main" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/xsim.dir/tb_main_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- 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Usage: 30 ms 5 | Simulation completed 6 | Simulation Memory Usage: 8500 KB (Peak: 8500 KB) 7 | Simulation CPU Usage: 92 ms 8 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/xsim.dir/xil_defaultlib/control.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Rajandeep/RSA-CRYPTOSYSTEM-using-verilog/023ff53d053ac1182f7ea311d88b114ac96a3fc6/RSA.sim/sim_1/behav/xsim.dir/xil_defaultlib/control.sdb -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/xsim.dir/xil_defaultlib/glbl.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Rajandeep/RSA-CRYPTOSYSTEM-using-verilog/023ff53d053ac1182f7ea311d88b114ac96a3fc6/RSA.sim/sim_1/behav/xsim.dir/xil_defaultlib/glbl.sdb -------------------------------------------------------------------------------- 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D:/Dev-Verilog/RSA/RSA.srcs/sources_1/new/control.v,1467909101,verilog,,,,,,,,,,, 6 | D:/Dev-Verilog/RSA/RSA.srcs/sources_1/new/inverter.v,1467888315,verilog,,,,,,,,,,, 7 | D:/Dev-Verilog/RSA/RSA.srcs/sources_1/new/mod.v,1467284170,verilog,,,,,,,,,,, 8 | D:/Dev-Verilog/RSA/RSA.srcs/sources_1/new/mod_exp.v,1467896964,verilog,,,,,,,,,,, 9 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/xsim.dir/xsim.svtype: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/xsim.ini: -------------------------------------------------------------------------------- 1 | xil_defaultlib=xsim.dir/xil_defaultlib 2 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/xvlog.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module mod 3 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v:4] 4 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v:5] 5 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v:6] 6 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod.v:7] 7 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v" into library xil_defaultlib 8 | INFO: [VRFC 10-311] analyzing module mod_exp 9 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v:7] 10 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v:8] 11 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v:9] 12 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/mod_exp.v:13] 13 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v" into library xil_defaultlib 14 | INFO: [VRFC 10-311] analyzing module inverter 15 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v:9] 16 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v:10] 17 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v:14] 18 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/inverter.v:15] 19 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/control.v" into library xil_defaultlib 20 | INFO: [VRFC 10-311] analyzing module control 21 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/control.v:3] 22 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/control.v:8] 23 | WARNING: [VRFC 10-756] identifier WIDTH is used before its declaration [C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sources_1/new/control.v:9] 24 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.srcs/sim_1/new/tb_main.v" into library xil_defaultlib 25 | INFO: [VRFC 10-311] analyzing module tb_main 26 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/rajandeep/Desktop/RSA/RSA.sim/sim_1/behav/glbl.v" into library xil_defaultlib 27 | INFO: [VRFC 10-311] analyzing module glbl 28 | -------------------------------------------------------------------------------- /RSA.sim/sim_1/behav/xvlog.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Rajandeep/RSA-CRYPTOSYSTEM-using-verilog/023ff53d053ac1182f7ea311d88b114ac96a3fc6/RSA.sim/sim_1/behav/xvlog.pb -------------------------------------------------------------------------------- /RSA.srcs/sim_1/new/mod_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module mod_tb; 3 | parameter WIDTH = 64; 4 | reg [WIDTH-1:0] a,n; 5 | wire [WIDTH-1:0] r,q; 6 | mod m1(a,n,r,q); 7 | defparam m1.WIDTH = WIDTH; 8 | 9 | initial begin 10 | a = 12345; 11 | n = 23; 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /RSA.srcs/sim_1/new/tb_inverter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define WIDTH 32 3 | module tb_inverter; 4 | reg [`WIDTH-1:0] p; 5 | reg [`WIDTH-1:0] q; 6 | reg clk; 7 | reg reset; 8 | wire finish; 9 | wire [`WIDTH-1:0] e; 10 | wire [`WIDTH*2-1:0] d; 11 | 12 | inverter uut(p,q,clk,reset,finish,e,d); 13 | 14 | initial begin 15 | p = 32'd23; 16 | q = 32'd5; 17 | clk = 0; 18 | reset = 0; 19 | #10 reset = 1; 20 | #10 reset = 0; 21 | end 22 | 23 | always #5 clk = ~clk; 24 | endmodule 25 | -------------------------------------------------------------------------------- /RSA.srcs/sim_1/new/tb_main.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define WIDTH 256 3 | module tb_main; 4 | reg [`WIDTH-1:0] p,q; 5 | reg clk,reset,reset1,encrypt_decrypt; 6 | reg [`WIDTH-1:0] msg_in; 7 | wire [`WIDTH-1:0] msg_out; 8 | wire mod_exp_finish; 9 | 10 | control uut(p,q,clk,reset,reset1,encrypt_decrypt,msg_in,msg_out,mod_exp_finish); 11 | defparam uut.WIDTH = `WIDTH; 12 | 13 | initial begin 14 | p = 128'd113680897410347; 15 | q = 128'd7999808077935876437321; 16 | clk = 0; 17 | reset =0; reset1=0; 18 | encrypt_decrypt = 0; 19 | msg_in = 256'h0000000000000000000000000000000000262d806a3e18f03ab37b2857e7e149; 20 | #10 reset = 1; 21 | #10 reset = 0; 22 | #2980 $finish; 23 | end 24 | 25 | initial begin 26 | #1000 reset1 = 1; 27 | #10 reset1 = 0; 28 | end 29 | 30 | always #5 clk = ~clk; 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /RSA.srcs/sim_1/new/tb_mod_exp.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define WIDTH 32 3 | module tb_mod_exp; 4 | 5 | reg [`WIDTH*2-1:0] base; 6 | reg [`WIDTH*2-1:0] modulo; 7 | reg [`WIDTH*2-1:0] exponent; 8 | reg clk; 9 | reg reset; 10 | wire finish; 11 | wire [`WIDTH*2-1:0] result; 12 | 13 | mod_exp uut(base,modulo,exponent,clk,reset,finish,result); 14 | defparam uut.WIDTH = `WIDTH; 15 | 16 | initial begin 17 | base = 5; 18 | modulo = 13; 19 | exponent = 567; 20 | clk = 0; 21 | reset = 0; 22 | #10 reset = 1; 23 | #10 reset = 0; 24 | end 25 | 26 | always #5 clk = ~clk; 27 | endmodule 28 | -------------------------------------------------------------------------------- /RSA.srcs/sources_1/new/control.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module control( 3 | input [WIDTH-1:0] p,q, //Input Random Primes 4 | input clk,//system wide clock 5 | input reset,//resets inverter module 6 | input reset1,//resets modular exponentiation module 7 | input encrypt_decrypt,//1 for encryption and 0 for decryption 8 | input [WIDTH-1:0] msg_in,//input either message or cipher 9 | output [WIDTH*2-1:0] msg_out,//output either decrypted message or cipher 10 | output mod_exp_finish//finish signal indicator of mod exp module 11 | ); 12 | 13 | parameter WIDTH = 32;//defines size of input ports 14 | 15 | wire inverter_finish; 16 | wire [WIDTH*2-1:0] e,d; 17 | wire [WIDTH*2-1:0] exponent = encrypt_decrypt?e:d; 18 | wire [WIDTH*2-1:0] modulo = p*q; 19 | wire mod_exp_reset = 1'b0; 20 | 21 | reg [WIDTH*2-1:0] exp_reg,msg_reg; 22 | reg [WIDTH*2-1:0] mod_reg; 23 | 24 | always @(posedge clk)begin 25 | exp_reg <= exponent; 26 | mod_reg <= modulo; 27 | msg_reg <= msg_in; 28 | end 29 | 30 | inverter i(p,q,clk,reset,inverter_finish,e,d); 31 | defparam i.WIDTH = WIDTH; 32 | mod_exp m(msg_reg,mod_reg,exp_reg,clk,reset1,mod_exp_finish,msg_out); 33 | defparam m.WIDTH = WIDTH; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /RSA.srcs/sources_1/new/dff.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //Positive edge triggered D Flip Flop with asynch reset and a 2:1 mux 3 | module dff( 4 | input D, //Input 5 | input rst, //Active High Reset 6 | input clk, //Clock 7 | output reg q //Output 8 | ); 9 | 10 | always @(posedge clk or posedge rst) begin 11 | if(rst) q<=0; 12 | else q<=D; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /RSA.srcs/sources_1/new/divider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module divider(Z, R, done, X, Y, start, clk); 3 | output [7:0] Z; 4 | output [15:0] R; 5 | output done; 6 | input [15:0] X; 7 | input [7:0] Y; 8 | input start; 9 | input clk; 10 | reg [7:0] Q; 11 | reg [15:0] R; 12 | reg [15:0] y; 13 | reg [15:0] x; 14 | reg [5:0] cnt; 15 | reg done; 16 | reg last; 17 | initial $monitor("x = %d R = %d",x,R); 18 | 19 | always @(posedge clk) begin 20 | done <= 0; 21 | last <= 0; 22 | if (start) 23 | cnt <= 0; 24 | else 25 | cnt <= cnt + 1; 26 | if (cnt == 6'd14) 27 | last <= 1; 28 | else if (cnt == 6'd15) 29 | done <= 1; 30 | end 31 | 32 | always @(posedge clk) 33 | if (start) begin 34 | x = X; 35 | R = 0; 36 | end 37 | else if (~last && (R < Y)) begin 38 | R = {R[14:0],x[15]}; 39 | x[15:1] = x[14:0]; 40 | R = R + Y; 41 | x[0] = 1'b0; 42 | end 43 | else if (~last && (R > Y)) begin 44 | R = {R[14:0],x[15]}; 45 | x[15:1] = x[14:0]; 46 | R = R - Y; 47 | x[0] = 1'b1; 48 | end 49 | 50 | assign Z = x; 51 | endmodule -------------------------------------------------------------------------------- /RSA.srcs/sources_1/new/inverter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define UPDATING 3'd1 3 | `define CHECK 3'd2 4 | `define HOLDING 3'd3 5 | /*to calculate decryption key 'd' and encryption key 'e' we use extended euclidian algorithm 6 | i.e d * e = 1 mod (phi) 7 | */ 8 | module inverter( 9 | input [WIDTH-1:0] p,//prime number 1 10 | input [WIDTH-1:0] q,//prime nu,ber 2 11 | input clk,//system clock 12 | input reset,//resets module 13 | output finish,//indicates finish for operation 14 | output [WIDTH*2-1:0] e,//encryption key 15 | output [WIDTH*2-1:0] d//decryption key 16 | ); 17 | 18 | parameter WIDTH = 32; 19 | 20 | reg [WIDTH*2-1:0] totient_reg,a,b,y,y_prev;//totient here represents phi 21 | reg [2:0] state; 22 | reg [WIDTH-1:0] e_reg; 23 | 24 | wire [WIDTH*2-1:0] totient = (p-1)*(q-1); 25 | wire [WIDTH*2-1:0] quotient,b_next; 26 | wire [WIDTH*2-1:0] y_next = y_prev - quotient * y; 27 | wire [WIDTH-1:0] e_plus3 = e_reg + 2; 28 | assign finish = (state == `HOLDING) ? 1'b1 : 1'b0; 29 | assign e = e_reg; 30 | assign d = y_prev; 31 | 32 | mod x_mod_y(a,b,b_next,quotient);//divider module 33 | defparam x_mod_y.WIDTH = WIDTH*2; 34 | 35 | always @(posedge clk) begin 36 | if(reset) begin 37 | totient_reg <= totient; 38 | a <= totient; 39 | b <= 3; 40 | e_reg <=3; 41 | y <= 1; 42 | y_prev <= 0; 43 | state = `UPDATING; 44 | end 45 | case(state) 46 | `UPDATING: begin 47 | if(b != 64'd0) begin 48 | a <= b; 49 | b <= b_next; 50 | y <= y_next; 51 | y_prev <= y; 52 | state <= `UPDATING; 53 | end 54 | else state <= `CHECK; 55 | end 56 | `CHECK: begin 57 | if(a == 64'd1 && y_prev[WIDTH*2-1] == 1'b0) 58 | state = `HOLDING; 59 | else begin 60 | a <= totient_reg; 61 | b <= e_plus3; 62 | e_reg <= e_plus3; 63 | y <= 1; 64 | y_prev = 0; 65 | state <= `UPDATING; 66 | end 67 | end 68 | `HOLDING: begin 69 | end 70 | endcase 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /RSA.srcs/sources_1/new/mod.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mod( 4 | input [WIDTH-1:0] a, 5 | input [WIDTH-1:0] n, 6 | output [WIDTH-1:0] R, 7 | output [WIDTH-1:0] Q 8 | ); 9 | parameter WIDTH = 19; 10 | reg [WIDTH-1:0] A,N; 11 | reg [WIDTH:0] p; 12 | integer i; 13 | 14 | always@ (a or n) begin 15 | A = a; 16 | N = n; 17 | p = 0; 18 | for(i=0;i < WIDTH;i=i+1) begin 19 | p = {p[WIDTH-2:0],A[WIDTH-1]}; 20 | A[WIDTH-1:1] = A[WIDTH-2:0]; 21 | p = p-N; 22 | if(p[WIDTH-1] == 1)begin 23 | A[0] = 1'b0; 24 | p = p + N; 25 | end 26 | else 27 | A[0] =1'b1; 28 | end 29 | 30 | end 31 | 32 | assign R = p,Q = A; 33 | endmodule 34 | -------------------------------------------------------------------------------- /RSA.srcs/sources_1/new/mod_exp.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define UPDATE 2'd1 3 | `define HOLD 2'd2 4 | /* to calculate *** a^b mod n *** we use right to left binary exponentiation (by .BRUCE SCHIENER) 5 | */ 6 | module mod_exp( 7 | input [WIDTH*2-1:0] base,//base here represents (a) 8 | input [WIDTH*2-1:0] modulo,//modulo here is modulus (n) 9 | input [WIDTH*2-1:0] exponent,//exponent here is the power of base (b) 10 | input clk,//system clk 11 | input reset,//resets module 12 | output finish,//sends finish signal on completion 13 | output [WIDTH*2-1:0] result 14 | ); 15 | 16 | parameter WIDTH = 32; 17 | 18 | reg [WIDTH*2-1:0] base_reg,modulo_reg,exponent_reg,result_reg; 19 | reg [1:0] state; 20 | 21 | wire [WIDTH*2-1:0] result_mul_base = result_reg * base_reg; 22 | wire [WIDTH*2-1:0] result_next; 23 | wire [WIDTH*2-1:0] base_squared = base_reg * base_reg; 24 | wire [WIDTH*2-1:0] base_next; 25 | wire [WIDTH*2-1:0] exponent_next = exponent_reg >> 1; 26 | 27 | assign finish = (state == `HOLD) ? 1'b1:1'b0; 28 | assign result = result_reg; 29 | 30 | mod base_squared_mod(base_squared,modulo_reg,base_next,); // implementation of 31 | defparam base_squared_mod.WIDTH = WIDTH*2; // right to left 32 | // binary exponentiation 33 | mod result_mul_base_mod (result_mul_base,modulo_reg,result_next,); // by. 34 | defparam result_mul_base_mod.WIDTH = WIDTH*2; // BRUCE SCHIEMER 35 | 36 | 37 | always @(posedge clk) begin 38 | if(reset) begin //initialisation of values 39 | base_reg <= base; 40 | modulo_reg <= modulo; 41 | exponent_reg <= exponent; 42 | result_reg <= 32'd1; 43 | state <= `UPDATE; 44 | end 45 | else case(state) 46 | `UPDATE: begin 47 | if (exponent_reg != 64'd0) begin 48 | if (exponent_reg[0]) 49 | result_reg <= result_next; 50 | base_reg <= base_next; 51 | exponent_reg <= exponent_next; 52 | state <= `UPDATE; 53 | end 54 | else state <= `HOLD; 55 | end 56 | 57 | `HOLD: begin 58 | end 59 | endcase 60 | end 61 | endmodule 62 | -------------------------------------------------------------------------------- /RSA.srcs/sources_1/new/mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //2:1 mux 3 | module mux( 4 | output reg out, //Output 5 | input sel, //Input 1 6 | input a, //Input 2 7 | input b //Select Line 8 | ); 9 | 10 | wire not_sel; 11 | always @(sel or not_sel) 12 | out = (sel&a)|(not_sel&b); 13 | 14 | assign not_sel = ~sel; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /RSA.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 86 | 87 | 88 | 89 | 90 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 143 | 144 | 145 | 146 | 147 | 150 | 151 | 153 | 154 | 156 | 157 | 159 | 160 | 162 | 163 | 165 | 166 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | -------------------------------------------------------------------------------- /archive_project_summary.txt: -------------------------------------------------------------------------------- 1 | *************************************************************************************** 2 | * PROJECT ARCHIVE SUMMARY REPORT 3 | * 4 | * (archive_project_summary.txt) 5 | * 6 | * PLEASE READ THIS REPORT TO GET THE DETAILED INFORMATION ABOUT THE PROJECT DATA THAT 7 | * WAS ARCHIVED FOR THE CURRENT PROJECT 8 | * 9 | * The report is divided into following five sections:- 10 | * 11 | * Section (1) - PROJECT INFORMATION 12 | * This section provides the details of the current project that was archived 13 | * 14 | * Section (2) - INCLUDED/EXCLUDED RUNS 15 | * This section summarizes the list of design runs for which the results were included 16 | * or excluded from the archive 17 | * 18 | * Section (3) - ARCHIVED SOURCES 19 | * This section summarizes the list of files that were added to the archive 20 | * 21 | * Section (3.1) - INCLUDE FILES 22 | * This section summarizes the list of 'include' files that were added to the archive 23 | * 24 | * Section (3.1.1) - INCLUDE_DIRS SETTINGS 25 | * This section summarizes the 'verilog include directory' path settings, if any 26 | * 27 | * Section (3.2) - REMOTE SOURCES 28 | * This section summarizes the list of referenced 'remote' files that were 'imported' 29 | * into the archived project 30 | * 31 | * Section (3.3) - SOURCES SUMMARY 32 | * This section summarizes the list of all the files present in the archive 33 | * 34 | * Section (3.4) - REMOTE IP DEFINITIONS 35 | * This section summarizes the list of all the remote IP's present in the archive 36 | * 37 | * Section (4) - JOURNAL/LOG FILES 38 | * This section summarizes the list of journal/log files that were added to the archive 39 | * 40 | *************************************************************************************** 41 | 42 | Section (1) - PROJECT INFORMATION 43 | --------------------------------- 44 | Name = RSA 45 | Directory = G:/study/verilog/RSA/RSAfinal 46 | 47 | WARNING: Please verify the compiled library directory path for the following property in the 48 | current project. The path may point to an invalid location after opening this project. 49 | This could happen if the project was unarchived in a location where this path is not 50 | accessible. To resolve this issue, please set this property with the desired path 51 | before launching simulation:- 52 | 53 | Property = compxlib.xsim_compiled_library_dir 54 | Path = 55 | 56 | Section (2) - INCLUDED RUNS 57 | --------------------------- 58 | The run results were included for the following runs in the archived project:- 59 | 60 | 61 | 62 | 63 | Section (3) - ARCHIVED SOURCES 64 | ------------------------------ 65 | The following sub-sections describes the list of sources that were archived for the current project:- 66 | 67 | Section (3.1) - INCLUDE FILES 68 | ----------------------------- 69 | List of referenced 'RTL Include' files that were 'imported' into the archived project:- 70 | 71 | None 72 | 73 | Section (3.1.1) - INCLUDE_DIRS SETTINGS 74 | --------------------------------------- 75 | List of the "INCLUDE_DIRS" fileset property settings that may or may not be applicable in the archived 76 | project, since most the 'RTL Include' files referenced in the original project were 'imported' into the 77 | archived project. 78 | 79 | fileset RTL include directory paths (INCLUDE_DIRS):- 80 | None 81 | 82 | fileset RTL include directory paths (INCLUDE_DIRS):- 83 | None 84 | 85 | Section (3.2) - REMOTE SOURCES 86 | ------------------------------ 87 | List of referenced 'remote' design files that were 'imported' into the archived project:- 88 | 89 | 90 | None 91 | 92 | 93 | None 94 | 95 | 96 | None 97 | 98 | Section (3.3) - SOURCES SUMMARY 99 | ------------------------------- 100 | List of all the source files present in the archived project:- 101 | 102 | 103 | ./RSA.srcs/sources_1/new/mod.v 104 | ./RSA.srcs/sources_1/new/mod_exp.v 105 | ./RSA.srcs/sources_1/new/inverter.v 106 | ./RSA.srcs/sources_1/new/control.v 107 | 108 | 109 | None 110 | 111 | 112 | ./RSA.srcs/sim_1/new/tb_main.v 113 | 114 | Section (3.4) - REMOTE IP DEFINITIONS 115 | ------------------------------------- 116 | List of all the remote IP's present in the archived project:- 117 | 118 | 119 | None 120 | 121 | Section (4) - JOURNAL/LOG FILES 122 | ------------------------------- 123 | List of Journal/Log files that were added to the archived project:- 124 | 125 | Source File = G:/study/verilog/RSA/RSAfinal/vivado.jou 126 | Archived Location = ./RSA/vivado.jou 127 | 128 | Source File = G:/study/verilog/RSA/RSAfinal/vivado.log 129 | Archived Location = ./RSA/vivado.log 130 | 131 | -------------------------------------------------------------------------------- /vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Sun Jul 17 20:45:22 2016 6 | # Process ID: 3424 7 | # Current directory: G:/study/verilog/RSA/RSAfinal 8 | # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6428 G:\study\verilog\RSA\RSAfinal\RSA.xpr 9 | # Log file: G:/study/verilog/RSA/RSAfinal/vivado.log 10 | # Journal file: G:/study/verilog/RSA/RSAfinal\vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project G:/study/verilog/RSA/RSAfinal/RSA.xpr 14 | update_compile_order -fileset sources_1 15 | archive_project C:/Users/rajandeep/Desktop/rsa/RSA.xpr.zip -temp_dir G:/study/verilog/RSA/RSAfinal/.Xil/Vivado-2804-dell -force 16 | -------------------------------------------------------------------------------- /vivado.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Sun Jul 17 20:45:22 2016 6 | # Process ID: 3424 7 | # Current directory: G:/study/verilog/RSA/RSAfinal 8 | # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6428 G:\study\verilog\RSA\RSAfinal\RSA.xpr 9 | # Log file: G:/study/verilog/RSA/RSAfinal/vivado.log 10 | # Journal file: G:/study/verilog/RSA/RSAfinal\vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project G:/study/verilog/RSA/RSAfinal/RSA.xpr 14 | INFO: [Project 1-313] Project file moved from 'C:/Users/rajandeep****** Webtalk v2016.2 (64-bit) 15 | **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 16 | **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 17 | ** Copyright 1986-2016 Xilinx, Inc. AINFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'G:/xilinx_vivado/Vivado/2016.2/data/ip'. 18 | open_project: Time (s): cpu = 00:00:14 ; elapsed = 00:00:38 . Memory (MB): peak = 714.793 ; gain = 151.609 19 | update_compile_order exit 20 | INFO: [Common archive_project C:/Users/rajandeep/Desktop/rsa/RSA.xpr.zip -temp_dir G:/study/verilog/RSA/RSAfinal/.Xil/Vivado-2804-dell -force 21 | INFO: [Coretcl 2-137] starting archive... 22 | INFO: [Coretcl 2-1499] Saving project copy to temporary location 'G:/study/verilog/RSA/RSAfinal/.Xil/Vivado-2804-dell' for archiving project 23 | Scanning sources... 24 | Finished scanning sources 25 | INFO: [Coretcl 2-1211] Creating project copy for archival... 26 | INFO: [Coretcl 2-1213] Including run results for 'synth_1' 27 | INFO: [Coretcl 2-1213] Including run results for 'impl_1' 28 | --------------------------------------------------------------------------------