├── .ccsproject ├── .cproject ├── .gitignore ├── .launches └── ucOSport_DSP28335_Demo.launch ├── .project ├── DSP2833x_BSP ├── include │ ├── DSP2833x_Adc.h │ ├── DSP2833x_CpuTimers.h │ ├── DSP2833x_DMA.h │ ├── DSP2833x_DefaultIsr.h │ ├── DSP2833x_DevEmu.h │ ├── DSP2833x_Device.h │ ├── DSP2833x_Dma_defines.h │ ├── DSP2833x_ECan.h │ ├── DSP2833x_ECap.h │ ├── DSP2833x_EPwm.h │ ├── DSP2833x_EPwm_defines.h │ ├── DSP2833x_EQep.h │ ├── DSP2833x_Examples.h │ ├── DSP2833x_GlobalPrototypes.h │ ├── DSP2833x_Gpio.h │ ├── DSP2833x_I2c.h │ ├── DSP2833x_I2c_defines.h │ ├── DSP2833x_Mcbsp.h │ ├── DSP2833x_PieCtrl.h │ ├── DSP2833x_PieVect.h │ ├── DSP2833x_Sci.h │ ├── DSP2833x_Spi.h │ ├── DSP2833x_SysCtrl.h │ ├── DSP2833x_XIntrupt.h │ └── DSP2833x_Xintf.h └── source │ ├── DSP2833x_ADC_cal.asm │ ├── DSP2833x_CSMPasswords.asm │ ├── DSP2833x_CodeStartBranch.asm │ ├── DSP2833x_CpuTimers.c │ ├── DSP2833x_DBGIER.asm │ ├── DSP2833x_DefaultIsr.c │ ├── DSP2833x_DisInt.asm │ ├── DSP2833x_GlobalVariableDefs.c │ ├── DSP2833x_Gpio.c │ ├── DSP2833x_MemCopy.c │ ├── DSP2833x_PieCtrl.c │ ├── DSP2833x_PieVect.c │ ├── DSP2833x_SysCtrl.c │ └── DSP2833x_usDelay.asm ├── LICENSE ├── README.md ├── clean.bat ├── clean.sh ├── cmd ├── DSP2833x_Headers_nonBIOS.cmd └── F28335.cmd ├── docs ├── NNP项目用比例阀.assets │ ├── image-20210128135331834.png │ ├── image-20210128152025890.png │ ├── image-20210205135205756.png │ └── image-20210205135230231.png └── μCOS-II嵌入式实时操作系统.md ├── main.c ├── targetConfigs ├── TMS320F28335.ccxml └── readme.txt └── ucos-ii ├── config ├── app_cfg.h ├── cpu_cfg.h ├── lib_cfg.h └── os_cfg.h ├── uC-CPU ├── C28x │ └── CCS │ │ ├── cpu.h │ │ ├── cpu_a.asm │ │ └── cpu_c.c ├── cpu_cache.h ├── cpu_core.c ├── cpu_core.h └── cpu_def.h ├── uC-LIB ├── lib_ascii.c ├── lib_ascii.h ├── lib_def.h ├── lib_math.c ├── lib_math.h ├── lib_mem.c ├── lib_mem.h ├── lib_str.c └── lib_str.h └── uCOS-II ├── Ports └── C28x │ └── Generic │ └── CCS │ ├── os_cpu.h │ ├── os_cpu_a.asm │ ├── os_cpu_c.c │ ├── os_cpu_i.asm │ └── os_dbg.c └── Source ├── os.h ├── os_core.c ├── os_flag.c ├── os_mbox.c ├── os_mem.c ├── os_mutex.c ├── os_q.c ├── os_sem.c ├── os_task.c ├── os_time.c ├── os_tmr.c └── ucos_ii.h /.ccsproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .settings 2 | .launches 3 | Debug 4 | *.swp 5 | Debug/*.obj 6 | Debug/*/*/.obj 7 | -------------------------------------------------------------------------------- /.launches/ucOSport_DSP28335_Demo.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | ucOSport_DSP28335_Demo 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | 11 | 12 | 13 | 14 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 15 | full,incremental, 16 | 17 | 18 | 19 | 20 | 21 | com.ti.ccstudio.core.ccsNature 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.core.ccnature 25 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 26 | 27 | 28 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_CpuTimers.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: March 20, 2007 15:33:42 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_CpuTimers.h 6 | // 7 | // TITLE: DSP2833x CPU 32-bit Timers Register Definitions. 8 | // 9 | // NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and 10 | // other realtime operating systems. 11 | // 12 | // Do not use these two timers in your application if you ever plan 13 | // on integrating DSP-BIOS or another realtime OS. 14 | // 15 | // For this reason, comment out the code to manipulate these two 16 | // timers if using DSP-BIOS or another realtime OS. 17 | // 18 | //########################################################################### 19 | // $TI Release: F2833x Support Library v2.01.00.00 $ 20 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 21 | // $Copyright: 22 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 23 | // 24 | // Redistribution and use in source and binary forms, with or without 25 | // modification, are permitted provided that the following conditions 26 | // are met: 27 | // 28 | // Redistributions of source code must retain the above copyright 29 | // notice, this list of conditions and the following disclaimer. 30 | // 31 | // Redistributions in binary form must reproduce the above copyright 32 | // notice, this list of conditions and the following disclaimer in the 33 | // documentation and/or other materials provided with the 34 | // distribution. 35 | // 36 | // Neither the name of Texas Instruments Incorporated nor the names of 37 | // its contributors may be used to endorse or promote products derived 38 | // from this software without specific prior written permission. 39 | // 40 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 | // $ 52 | //########################################################################### 53 | 54 | #ifndef DSP2833x_CPU_TIMERS_H 55 | #define DSP2833x_CPU_TIMERS_H 56 | 57 | #ifdef __cplusplus 58 | extern "C" { 59 | #endif 60 | 61 | // 62 | // CPU Timer Register Bit Definitions 63 | // 64 | 65 | // 66 | // TCR: Control register bit definitions 67 | // 68 | struct TCR_BITS { // bits description 69 | Uint16 rsvd1:4; // 3:0 reserved 70 | Uint16 TSS:1; // 4 Timer Start/Stop 71 | Uint16 TRB:1; // 5 Timer reload 72 | Uint16 rsvd2:4; // 9:6 reserved 73 | Uint16 SOFT:1; // 10 Emulation modes 74 | Uint16 FREE:1; // 11 75 | Uint16 rsvd3:2; // 12:13 reserved 76 | Uint16 TIE:1; // 14 Output enable 77 | Uint16 TIF:1; // 15 Interrupt flag 78 | }; 79 | 80 | union TCR_REG { 81 | Uint16 all; 82 | struct TCR_BITS bit; 83 | }; 84 | 85 | // 86 | // TPR: Pre-scale low bit definitions 87 | // 88 | struct TPR_BITS { // bits description 89 | Uint16 TDDR:8; // 7:0 Divide-down low 90 | Uint16 PSC:8; // 15:8 Prescale counter low 91 | }; 92 | 93 | union TPR_REG { 94 | Uint16 all; 95 | struct TPR_BITS bit; 96 | }; 97 | 98 | // 99 | // TPRH: Pre-scale high bit definitions 100 | // 101 | struct TPRH_BITS { // bits description 102 | Uint16 TDDRH:8; // 7:0 Divide-down high 103 | Uint16 PSCH:8; // 15:8 Prescale counter high 104 | }; 105 | 106 | union TPRH_REG { 107 | Uint16 all; 108 | struct TPRH_BITS bit; 109 | }; 110 | 111 | // 112 | // TIM, TIMH: Timer register definitions 113 | // 114 | struct TIM_REG { 115 | Uint16 LSW; 116 | Uint16 MSW; 117 | }; 118 | 119 | union TIM_GROUP { 120 | Uint32 all; 121 | struct TIM_REG half; 122 | }; 123 | 124 | // 125 | // PRD, PRDH: Period register definitions 126 | // 127 | struct PRD_REG { 128 | Uint16 LSW; 129 | Uint16 MSW; 130 | }; 131 | 132 | union PRD_GROUP { 133 | Uint32 all; 134 | struct PRD_REG half; 135 | }; 136 | 137 | // 138 | // CPU Timer Register File 139 | // 140 | struct CPUTIMER_REGS { 141 | union TIM_GROUP TIM; // Timer counter register 142 | union PRD_GROUP PRD; // Period register 143 | union TCR_REG TCR; // Timer control register 144 | Uint16 rsvd1; // reserved 145 | union TPR_REG TPR; // Timer pre-scale low 146 | union TPRH_REG TPRH; // Timer pre-scale high 147 | }; 148 | 149 | // 150 | // CPU Timer Support Variables 151 | // 152 | struct CPUTIMER_VARS { 153 | volatile struct CPUTIMER_REGS *RegsAddr; 154 | Uint32 InterruptCount; 155 | float CPUFreqInMHz; 156 | float PeriodInUSec; 157 | }; 158 | 159 | // 160 | // Function prototypes and external definitions 161 | // 162 | void InitCpuTimers(void); 163 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); 164 | 165 | extern volatile struct CPUTIMER_REGS CpuTimer0Regs; 166 | extern struct CPUTIMER_VARS CpuTimer0; 167 | 168 | // 169 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. 170 | // Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS 171 | // 172 | extern volatile struct CPUTIMER_REGS CpuTimer1Regs; 173 | extern volatile struct CPUTIMER_REGS CpuTimer2Regs; 174 | 175 | extern struct CPUTIMER_VARS CpuTimer1; 176 | extern struct CPUTIMER_VARS CpuTimer2; 177 | 178 | // 179 | // Defines for useful Timer Operations: 180 | // 181 | 182 | // 183 | // Start Timer 184 | // 185 | #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 186 | 187 | // 188 | // Stop Timer 189 | // 190 | #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 191 | 192 | // 193 | // Reload Timer With period Value 194 | // 195 | #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 196 | 197 | // 198 | // Read 32-Bit Timer Value 199 | // 200 | #define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all 201 | 202 | // 203 | // Read 32-Bit Period Value 204 | // 205 | #define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all 206 | 207 | // 208 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 209 | // Do not use these two timers if you ever plan on integrating 210 | // DSP-BIOS or another realtime OS. 211 | // 212 | // For this reason, comment out the code to manipulate these two timers 213 | // if using DSP-BIOS or another realtime OS. 214 | // 215 | 216 | // 217 | // Start Timer 218 | // 219 | #define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 220 | #define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 221 | 222 | // 223 | // Stop Timer 224 | // 225 | #define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 226 | #define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 227 | 228 | // 229 | // Reload Timer With period Value 230 | // 231 | #define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 232 | #define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 233 | 234 | // 235 | // Read 32-Bit Timer Value 236 | // 237 | #define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all 238 | #define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all 239 | 240 | // 241 | // Read 32-Bit Period Value 242 | // 243 | #define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all 244 | #define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all 245 | 246 | #ifdef __cplusplus 247 | } 248 | #endif /* extern "C" */ 249 | 250 | #endif // end of DSP2833x_CPU_TIMERS_H definition 251 | 252 | // 253 | // End of file 254 | // 255 | 256 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_DefaultIsr.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:45:37 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_DefaultIsr.h 6 | // 7 | // TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_DEFAULT_ISR_H 46 | #define DSP2833x_DEFAULT_ISR_H 47 | 48 | #ifdef __cplusplus 49 | extern "C" { 50 | #endif 51 | 52 | // 53 | // Default Interrupt Service Routine Declarations: 54 | // 55 | // The following function prototypes are for the 56 | // default ISR routines used with the default PIE vector table. 57 | // This default vector table is found in the DSP2833x_PieVect.h 58 | // file. 59 | // 60 | 61 | // 62 | // Non-Peripheral Interrupts 63 | // 64 | interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 65 | interrupt void INT14_ISR(void); // CPU-Timer2 66 | interrupt void DATALOG_ISR(void); // Datalogging interrupt 67 | interrupt void RTOSINT_ISR(void); // RTOS interrupt 68 | interrupt void EMUINT_ISR(void); // Emulation interrupt 69 | interrupt void NMI_ISR(void); // Non-maskable interrupt 70 | interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP 71 | interrupt void USER1_ISR(void); // User Defined trap 1 72 | interrupt void USER2_ISR(void); // User Defined trap 2 73 | interrupt void USER3_ISR(void); // User Defined trap 3 74 | interrupt void USER4_ISR(void); // User Defined trap 4 75 | interrupt void USER5_ISR(void); // User Defined trap 5 76 | interrupt void USER6_ISR(void); // User Defined trap 6 77 | interrupt void USER7_ISR(void); // User Defined trap 7 78 | interrupt void USER8_ISR(void); // User Defined trap 8 79 | interrupt void USER9_ISR(void); // User Defined trap 9 80 | interrupt void USER10_ISR(void); // User Defined trap 10 81 | interrupt void USER11_ISR(void); // User Defined trap 11 82 | interrupt void USER12_ISR(void); // User Defined trap 12 83 | 84 | // 85 | // Group 1 PIE Interrupt Service Routines 86 | // 87 | interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR 88 | interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR 89 | interrupt void XINT1_ISR(void); // External interrupt 1 90 | interrupt void XINT2_ISR(void); // External interrupt 2 91 | interrupt void ADCINT_ISR(void); // ADC 92 | interrupt void TINT0_ISR(void); // Timer 0 93 | interrupt void WAKEINT_ISR(void); // WD 94 | 95 | // 96 | // Group 2 PIE Interrupt Service Routines 97 | // 98 | interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 99 | interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 100 | interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 101 | interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 102 | interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 103 | interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 104 | 105 | // 106 | // Group 3 PIE Interrupt Service Routines 107 | // 108 | interrupt void EPWM1_INT_ISR(void); // EPWM-1 109 | interrupt void EPWM2_INT_ISR(void); // EPWM-2 110 | interrupt void EPWM3_INT_ISR(void); // EPWM-3 111 | interrupt void EPWM4_INT_ISR(void); // EPWM-4 112 | interrupt void EPWM5_INT_ISR(void); // EPWM-5 113 | interrupt void EPWM6_INT_ISR(void); // EPWM-6 114 | 115 | // 116 | // Group 4 PIE Interrupt Service Routines 117 | // 118 | interrupt void ECAP1_INT_ISR(void); // ECAP-1 119 | interrupt void ECAP2_INT_ISR(void); // ECAP-2 120 | interrupt void ECAP3_INT_ISR(void); // ECAP-3 121 | interrupt void ECAP4_INT_ISR(void); // ECAP-4 122 | interrupt void ECAP5_INT_ISR(void); // ECAP-5 123 | interrupt void ECAP6_INT_ISR(void); // ECAP-6 124 | 125 | // 126 | // Group 5 PIE Interrupt Service Routines 127 | // 128 | interrupt void EQEP1_INT_ISR(void); // EQEP-1 129 | interrupt void EQEP2_INT_ISR(void); // EQEP-2 130 | 131 | // 132 | // Group 6 PIE Interrupt Service Routines 133 | // 134 | interrupt void SPIRXINTA_ISR(void); // SPI-A 135 | interrupt void SPITXINTA_ISR(void); // SPI-A 136 | interrupt void MRINTA_ISR(void); // McBSP-A 137 | interrupt void MXINTA_ISR(void); // McBSP-A 138 | interrupt void MRINTB_ISR(void); // McBSP-B 139 | interrupt void MXINTB_ISR(void); // McBSP-B 140 | 141 | // 142 | // Group 7 PIE Interrupt Service Routines 143 | // 144 | interrupt void DINTCH1_ISR(void); // DMA-Channel 1 145 | interrupt void DINTCH2_ISR(void); // DMA-Channel 2 146 | interrupt void DINTCH3_ISR(void); // DMA-Channel 3 147 | interrupt void DINTCH4_ISR(void); // DMA-Channel 4 148 | interrupt void DINTCH5_ISR(void); // DMA-Channel 5 149 | interrupt void DINTCH6_ISR(void); // DMA-Channel 6 150 | 151 | // 152 | // Group 8 PIE Interrupt Service Routines 153 | // 154 | interrupt void I2CINT1A_ISR(void); // I2C-A 155 | interrupt void I2CINT2A_ISR(void); // I2C-A 156 | interrupt void SCIRXINTC_ISR(void); // SCI-C 157 | interrupt void SCITXINTC_ISR(void); // SCI-C 158 | 159 | // 160 | // Group 9 PIE Interrupt Service Routines 161 | // 162 | interrupt void SCIRXINTA_ISR(void); // SCI-A 163 | interrupt void SCITXINTA_ISR(void); // SCI-A 164 | interrupt void SCIRXINTB_ISR(void); // SCI-B 165 | interrupt void SCITXINTB_ISR(void); // SCI-B 166 | interrupt void ECAN0INTA_ISR(void); // eCAN-A 167 | interrupt void ECAN1INTA_ISR(void); // eCAN-A 168 | interrupt void ECAN0INTB_ISR(void); // eCAN-B 169 | interrupt void ECAN1INTB_ISR(void); // eCAN-B 170 | 171 | // 172 | // Group 10 PIE Interrupt Service Routines 173 | // 174 | 175 | // 176 | // Group 11 PIE Interrupt Service Routines 177 | // 178 | 179 | // 180 | // Group 12 PIE Interrupt Service Routines 181 | // 182 | interrupt void XINT3_ISR(void); // External interrupt 3 183 | interrupt void XINT4_ISR(void); // External interrupt 4 184 | interrupt void XINT5_ISR(void); // External interrupt 5 185 | interrupt void XINT6_ISR(void); // External interrupt 6 186 | interrupt void XINT7_ISR(void); // External interrupt 7 187 | interrupt void LVF_ISR(void); // Latched overflow flag 188 | interrupt void LUF_ISR(void); // Latched underflow flag 189 | 190 | // 191 | // Catch-all for Reserved Locations For testing purposes 192 | // 193 | interrupt void PIE_RESERVED(void); // Reserved for test 194 | interrupt void rsvd_ISR(void); // for test 195 | interrupt void INT_NOTUSED_ISR(void); // for unused interrupts 196 | 197 | #ifdef __cplusplus 198 | } 199 | #endif /* extern "C" */ 200 | 201 | #endif // end of DSP2833x_DEFAULT_ISR_H definition 202 | 203 | // 204 | // End of file 205 | // 206 | 207 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_DevEmu.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: April 15, 2009 10:05:17 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_DevEmu.h 6 | // 7 | // TITLE: DSP2833x Device Emulation Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_DEV_EMU_H 46 | #define DSP2833x_DEV_EMU_H 47 | 48 | #ifdef __cplusplus 49 | extern "C" { 50 | #endif 51 | 52 | // 53 | // Device Emulation Register Bit Definitions: 54 | // 55 | 56 | // 57 | // Device Configuration Register Bit Definitions 58 | // 59 | struct DEVICECNF_BITS { // bits description 60 | Uint16 rsvd1:3; // 2:0 reserved 61 | Uint16 VMAPS:1; // 3 VMAP Status 62 | Uint16 rsvd2:1; // 4 reserved 63 | Uint16 XRSn:1; // 5 XRSn Signal Status 64 | Uint16 rsvd3:10; // 15:6 65 | Uint16 rsvd4:3; // 18:16 66 | Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection 67 | Uint16 rsvd5:7; // 26:20 reserved 68 | Uint16 TRSTN:1; // 27 Status of TRSTn signal 69 | Uint16 rsvd6:4; // 31:28 reserved 70 | }; 71 | 72 | union DEVICECNF_REG { 73 | Uint32 all; 74 | struct DEVICECNF_BITS bit; 75 | }; 76 | 77 | // 78 | // CLASSID 79 | // 80 | struct CLASSID_BITS { // bits description 81 | Uint16 CLASSNO:8; // 7:0 Class Number 82 | Uint16 PARTTYPE:8; // 15:8 Part Type 83 | }; 84 | 85 | union CLASSID_REG { 86 | Uint16 all; 87 | struct CLASSID_BITS bit; 88 | }; 89 | 90 | struct DEV_EMU_REGS { 91 | union DEVICECNF_REG DEVICECNF; // device configuration 92 | union CLASSID_REG CLASSID; // Class ID 93 | Uint16 REVID; // Device ID 94 | Uint16 PROTSTART; // Write-Read protection start 95 | Uint16 PROTRANGE; // Write-Read protection range 96 | Uint16 rsvd2[202]; 97 | }; 98 | 99 | // 100 | // PARTID 101 | // 102 | struct PARTID_BITS { // bits description 103 | Uint16 PARTNO:8; // 7:0 Part Number 104 | Uint16 PARTTYPE:8; // 15:8 Part Type 105 | }; 106 | 107 | union PARTID_REG { 108 | Uint16 all; 109 | struct PARTID_BITS bit; 110 | }; 111 | 112 | struct PARTID_REGS { 113 | union PARTID_REG PARTID; // Part ID 114 | }; 115 | 116 | // 117 | // Device Emulation Register References & Function Declarations 118 | // 119 | extern volatile struct DEV_EMU_REGS DevEmuRegs; 120 | extern volatile struct PARTID_REGS PartIdRegs; 121 | 122 | #ifdef __cplusplus 123 | } 124 | #endif /* extern "C" */ 125 | 126 | #endif // end of DSP2833x_DEV_EMU_H definition 127 | 128 | // 129 | // End of file 130 | // 131 | 132 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_Device.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/5 $ 2 | // Checkin $Date: January 22, 2008 16:55:35 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Device.h 6 | // 7 | // TITLE: DSP2833x Device Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_DEVICE_H 46 | #define DSP2833x_DEVICE_H 47 | 48 | 49 | #ifdef __cplusplus 50 | extern "C" { 51 | #endif 52 | 53 | // 54 | // Defines 55 | // 56 | #define TARGET 1 57 | 58 | // 59 | // User To Select Target Device 60 | // 61 | #define DSP28_28335 TARGET // Selects '28335/'28235 62 | #define DSP28_28334 0 // Selects '28334/'28234 63 | #define DSP28_28333 0 // Selects '28333/' 64 | #define DSP28_28332 0 // Selects '28332/'28232 65 | 66 | // 67 | // Common CPU Definitions 68 | // 69 | extern cregister volatile unsigned int IFR; 70 | extern cregister volatile unsigned int IER; 71 | 72 | #define EINT asm(" clrc INTM") 73 | #define DINT asm(" setc INTM") 74 | #define ERTM asm(" clrc DBGM") 75 | #define DRTM asm(" setc DBGM") 76 | #define EALLOW asm(" EALLOW") 77 | #define EDIS asm(" EDIS") 78 | #define ESTOP0 asm(" ESTOP0") 79 | 80 | #define M_INT1 0x0001 81 | #define M_INT2 0x0002 82 | #define M_INT3 0x0004 83 | #define M_INT4 0x0008 84 | #define M_INT5 0x0010 85 | #define M_INT6 0x0020 86 | #define M_INT7 0x0040 87 | #define M_INT8 0x0080 88 | #define M_INT9 0x0100 89 | #define M_INT10 0x0200 90 | #define M_INT11 0x0400 91 | #define M_INT12 0x0800 92 | #define M_INT13 0x1000 93 | #define M_INT14 0x2000 94 | #define M_DLOG 0x4000 95 | #define M_RTOS 0x8000 96 | 97 | #define BIT0 0x0001 98 | #define BIT1 0x0002 99 | #define BIT2 0x0004 100 | #define BIT3 0x0008 101 | #define BIT4 0x0010 102 | #define BIT5 0x0020 103 | #define BIT6 0x0040 104 | #define BIT7 0x0080 105 | #define BIT8 0x0100 106 | #define BIT9 0x0200 107 | #define BIT10 0x0400 108 | #define BIT11 0x0800 109 | #define BIT12 0x1000 110 | #define BIT13 0x2000 111 | #define BIT14 0x4000 112 | #define BIT15 0x8000 113 | 114 | // 115 | // For Portability, User Is Recommended To Use Following Data Type Size 116 | // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: 117 | // 118 | #ifndef DSP28_DATA_TYPES 119 | #define DSP28_DATA_TYPES 120 | typedef int int16; 121 | typedef long int32; 122 | typedef long long int64; 123 | typedef unsigned int Uint16; 124 | typedef unsigned long Uint32; 125 | typedef unsigned long long Uint64; 126 | typedef float float32; 127 | typedef long double float64; 128 | #endif 129 | 130 | // 131 | // Included Peripheral Header Files 132 | // 133 | #include "DSP2833x_Adc.h" // ADC Registers 134 | #include "DSP2833x_DevEmu.h" // Device Emulation Registers 135 | #include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers 136 | #include "DSP2833x_ECan.h" // Enhanced eCAN Registers 137 | #include "DSP2833x_ECap.h" // Enhanced Capture 138 | #include "DSP2833x_DMA.h" // DMA Registers 139 | #include "DSP2833x_EPwm.h" // Enhanced PWM 140 | #include "DSP2833x_EQep.h" // Enhanced QEP 141 | #include "DSP2833x_Gpio.h" // General Purpose I/O Registers 142 | #include "DSP2833x_I2c.h" // I2C Registers 143 | #include "DSP2833x_Mcbsp.h" // McBSP 144 | #include "DSP2833x_PieCtrl.h" // PIE Control Registers 145 | #include "DSP2833x_PieVect.h" // PIE Vector Table 146 | #include "DSP2833x_Spi.h" // SPI Registers 147 | #include "DSP2833x_Sci.h" // SCI Registers 148 | #include "DSP2833x_SysCtrl.h" // System Control/Power Modes 149 | #include "DSP2833x_XIntrupt.h" // External Interrupts 150 | #include "DSP2833x_Xintf.h" // XINTF External Interface 151 | 152 | #if DSP28_28335 || DSP28_28333 153 | #define DSP28_EPWM1 1 154 | #define DSP28_EPWM2 1 155 | #define DSP28_EPWM3 1 156 | #define DSP28_EPWM4 1 157 | #define DSP28_EPWM5 1 158 | #define DSP28_EPWM6 1 159 | #define DSP28_ECAP1 1 160 | #define DSP28_ECAP2 1 161 | #define DSP28_ECAP3 1 162 | #define DSP28_ECAP4 1 163 | #define DSP28_ECAP5 1 164 | #define DSP28_ECAP6 1 165 | #define DSP28_EQEP1 1 166 | #define DSP28_EQEP2 1 167 | #define DSP28_ECANA 1 168 | #define DSP28_ECANB 1 169 | #define DSP28_MCBSPA 1 170 | #define DSP28_MCBSPB 1 171 | #define DSP28_SPIA 1 172 | #define DSP28_SCIA 1 173 | #define DSP28_SCIB 1 174 | #define DSP28_SCIC 1 175 | #define DSP28_I2CA 1 176 | #endif // end DSP28_28335 || DSP28_28333 177 | 178 | #if DSP28_28334 179 | #define DSP28_EPWM1 1 180 | #define DSP28_EPWM2 1 181 | #define DSP28_EPWM3 1 182 | #define DSP28_EPWM4 1 183 | #define DSP28_EPWM5 1 184 | #define DSP28_EPWM6 1 185 | #define DSP28_ECAP1 1 186 | #define DSP28_ECAP2 1 187 | #define DSP28_ECAP3 1 188 | #define DSP28_ECAP4 1 189 | #define DSP28_ECAP5 0 190 | #define DSP28_ECAP6 0 191 | #define DSP28_EQEP1 1 192 | #define DSP28_EQEP2 1 193 | #define DSP28_ECANA 1 194 | #define DSP28_ECANB 1 195 | #define DSP28_MCBSPA 1 196 | #define DSP28_MCBSPB 1 197 | #define DSP28_SPIA 1 198 | #define DSP28_SCIA 1 199 | #define DSP28_SCIB 1 200 | #define DSP28_SCIC 1 201 | #define DSP28_I2CA 1 202 | #endif // end DSP28_28334 203 | 204 | #if DSP28_28332 205 | #define DSP28_EPWM1 1 206 | #define DSP28_EPWM2 1 207 | #define DSP28_EPWM3 1 208 | #define DSP28_EPWM4 1 209 | #define DSP28_EPWM5 1 210 | #define DSP28_EPWM6 1 211 | #define DSP28_ECAP1 1 212 | #define DSP28_ECAP2 1 213 | #define DSP28_ECAP3 1 214 | #define DSP28_ECAP4 1 215 | #define DSP28_ECAP5 0 216 | #define DSP28_ECAP6 0 217 | #define DSP28_EQEP1 1 218 | #define DSP28_EQEP2 1 219 | #define DSP28_ECANA 1 220 | #define DSP28_ECANB 1 221 | #define DSP28_MCBSPA 1 222 | #define DSP28_MCBSPB 0 223 | #define DSP28_SPIA 1 224 | #define DSP28_SCIA 1 225 | #define DSP28_SCIB 1 226 | #define DSP28_SCIC 0 227 | #define DSP28_I2CA 1 228 | #endif // end DSP28_28332 229 | 230 | #ifdef __cplusplus 231 | } 232 | #endif /* extern "C" */ 233 | 234 | #endif // end of DSP2833x_DEVICE_H definition 235 | 236 | // 237 | // End of file 238 | // 239 | 240 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_Dma_defines.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: August 14, 2007 16:32:29 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Dma_defines.h 6 | // 7 | // TITLE: #defines used in DMA examples 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_DMA_DEFINES_H 46 | #define DSP2833x_DMA_DEFINES_H 47 | 48 | 49 | #ifdef __cplusplus 50 | extern "C" { 51 | #endif 52 | 53 | // 54 | // MODE 55 | // 56 | // PERINTSEL bits 57 | // 58 | #define DMA_SEQ1INT 1 59 | #define DMA_SEQ2INT 2 60 | #define DMA_XINT1 3 61 | #define DMA_XINT2 4 62 | #define DMA_XINT3 5 63 | #define DMA_XINT4 6 64 | #define DMA_XINT5 7 65 | #define DMA_XINT6 8 66 | #define DMA_XINT7 9 67 | #define DMA_XINT13 10 68 | #define DMA_TINT0 11 69 | #define DMA_TINT1 12 70 | #define DMA_TINT2 13 71 | #define DMA_MXEVTA 14 72 | #define DMA_MREVTA 15 73 | #define DMA_MXREVTB 16 74 | #define DMA_MREVTB 17 75 | 76 | // 77 | // OVERINTE bit 78 | // 79 | #define OVRFLOW_DISABLE 0x0 80 | #define OVEFLOW_ENABLE 0x1 81 | 82 | // 83 | // PERINTE bit 84 | // 85 | #define PERINT_DISABLE 0x0 86 | #define PERINT_ENABLE 0x1 87 | 88 | // 89 | // CHINTMODE bits 90 | // 91 | #define CHINT_BEGIN 0x0 92 | #define CHINT_END 0x1 93 | 94 | // 95 | // ONESHOT bits 96 | // 97 | #define ONESHOT_DISABLE 0x0 98 | #define ONESHOT_ENABLE 0x1 99 | 100 | // 101 | // CONTINOUS bit 102 | // 103 | #define CONT_DISABLE 0x0 104 | #define CONT_ENABLE 0x1 105 | 106 | // 107 | // SYNCE bit 108 | // 109 | #define SYNC_DISABLE 0x0 110 | #define SYNC_ENABLE 0x1 111 | 112 | // 113 | // SYNCSEL bit 114 | // 115 | #define SYNC_SRC 0x0 116 | #define SYNC_DST 0x1 117 | 118 | // 119 | // DATASIZE bit 120 | // 121 | #define SIXTEEN_BIT 0x0 122 | #define THIRTYTWO_BIT 0x1 123 | 124 | // 125 | // CHINTE bit 126 | // 127 | #define CHINT_DISABLE 0x0 128 | #define CHINT_ENABLE 0x1 129 | 130 | #ifdef __cplusplus 131 | } 132 | #endif /* extern "C" */ 133 | 134 | #endif // - end of DSP2833x_EPWM_DEFINES_H 135 | 136 | // 137 | // End of file 138 | // 139 | 140 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_ECap.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:52:07 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_ECap.h 6 | // 7 | // TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_ECAP_H 46 | #define DSP2833x_ECAP_H 47 | 48 | 49 | #ifdef __cplusplus 50 | extern "C" { 51 | #endif 52 | 53 | // 54 | // Capture control register 1 bit definitions 55 | // 56 | struct ECCTL1_BITS { // bits description 57 | Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select 58 | Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 59 | Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select 60 | Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 61 | Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select 62 | Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 63 | Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select 64 | Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 65 | Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap 66 | // Event 67 | Uint16 PRESCALE:5; // 13:9 Event Filter prescale select 68 | Uint16 FREE_SOFT:2; // 15:14 Emulation mode 69 | }; 70 | 71 | union ECCTL1_REG { 72 | Uint16 all; 73 | struct ECCTL1_BITS bit; 74 | }; 75 | 76 | // 77 | // In V1.1 the STOPVALUE bit field was changed to 78 | // STOP_WRAP. This correlated to a silicon change from 79 | // F2833x Rev 0 to Rev A. 80 | // 81 | 82 | // 83 | // Capture control register 2 bit definitions 84 | // 85 | struct ECCTL2_BITS { // bits description 86 | Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot 87 | Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous 88 | Uint16 REARM:1; // 3 One-shot re-arm 89 | Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop 90 | Uint16 SYNCI_EN:1; // 5 Counter sync-in select 91 | Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode 92 | Uint16 SWSYNC:1; // 8 SW forced counter sync 93 | Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select 94 | Uint16 APWMPOL:1; // 10 APWM output polarity select 95 | Uint16 rsvd1:5; // 15:11 96 | }; 97 | 98 | union ECCTL2_REG { 99 | Uint16 all; 100 | struct ECCTL2_BITS bit; 101 | }; 102 | 103 | // 104 | // ECAP interrupt enable register bit definitions 105 | // 106 | struct ECEINT_BITS { // bits description 107 | Uint16 rsvd1:1; // 0 reserved 108 | Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable 109 | Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable 110 | Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable 111 | Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable 112 | Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable 113 | Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable 114 | Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable 115 | Uint16 rsvd2:8; // 15:8 reserved 116 | }; 117 | 118 | union ECEINT_REG { 119 | Uint16 all; 120 | struct ECEINT_BITS bit; 121 | }; 122 | 123 | // 124 | // ECAP interrupt flag register bit definitions 125 | // 126 | struct ECFLG_BITS { // bits description 127 | Uint16 INT:1; // 0 Global Flag 128 | Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag 129 | Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag 130 | Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag 131 | Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag 132 | Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag 133 | Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag 134 | Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag 135 | Uint16 rsvd2:8; // 15:8 reserved 136 | }; 137 | 138 | union ECFLG_REG { 139 | Uint16 all; 140 | struct ECFLG_BITS bit; 141 | }; 142 | 143 | struct ECAP_REGS { 144 | Uint32 TSCTR; // Time stamp counter 145 | Uint32 CTRPHS; // Counter phase 146 | Uint32 CAP1; // Capture 1 147 | Uint32 CAP2; // Capture 2 148 | Uint32 CAP3; // Capture 3 149 | Uint32 CAP4; // Capture 4 150 | Uint16 rsvd1[8]; // reserved 151 | union ECCTL1_REG ECCTL1; // Capture Control Reg 1 152 | union ECCTL2_REG ECCTL2; // Capture Control Reg 2 153 | union ECEINT_REG ECEINT; // ECAP interrupt enable 154 | union ECFLG_REG ECFLG; // ECAP interrupt flags 155 | union ECFLG_REG ECCLR; // ECAP interrupt clear 156 | union ECEINT_REG ECFRC; // ECAP interrupt force 157 | Uint16 rsvd2[6]; // reserved 158 | }; 159 | 160 | // 161 | // GPI/O External References & Function Declarations 162 | // 163 | extern volatile struct ECAP_REGS ECap1Regs; 164 | extern volatile struct ECAP_REGS ECap2Regs; 165 | extern volatile struct ECAP_REGS ECap3Regs; 166 | extern volatile struct ECAP_REGS ECap4Regs; 167 | extern volatile struct ECAP_REGS ECap5Regs; 168 | extern volatile struct ECAP_REGS ECap6Regs; 169 | 170 | #ifdef __cplusplus 171 | } 172 | #endif /* extern "C" */ 173 | 174 | #endif // end of DSP2833x_ECAP_H definition 175 | 176 | // 177 | // End of file 178 | // 179 | 180 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_EPwm_defines.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:45:39 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_EPwm_defines.h 6 | // 7 | // TITLE: #defines used in ePWM examples examples 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_EPWM_DEFINES_H 46 | #define DSP2833x_EPWM_DEFINES_H 47 | 48 | 49 | #ifdef __cplusplus 50 | extern "C" { 51 | #endif 52 | 53 | // 54 | // TBCTL (Time-Base Control) 55 | // 56 | // CTRMODE bits 57 | // 58 | #define TB_COUNT_UP 0x0 59 | #define TB_COUNT_DOWN 0x1 60 | #define TB_COUNT_UPDOWN 0x2 61 | #define TB_FREEZE 0x3 62 | 63 | // 64 | // PHSEN bit 65 | // 66 | #define TB_DISABLE 0x0 67 | #define TB_ENABLE 0x1 68 | 69 | // 70 | // PRDLD bit 71 | // 72 | #define TB_SHADOW 0x0 73 | #define TB_IMMEDIATE 0x1 74 | 75 | // 76 | // SYNCOSEL bits 77 | // 78 | #define TB_SYNC_IN 0x0 79 | #define TB_CTR_ZERO 0x1 80 | #define TB_CTR_CMPB 0x2 81 | #define TB_SYNC_DISABLE 0x3 82 | 83 | // 84 | // HSPCLKDIV and CLKDIV bits 85 | // 86 | #define TB_DIV1 0x0 87 | #define TB_DIV2 0x1 88 | #define TB_DIV4 0x2 89 | 90 | // 91 | // PHSDIR bit 92 | // 93 | #define TB_DOWN 0x0 94 | #define TB_UP 0x1 95 | 96 | // 97 | // CMPCTL (Compare Control) 98 | // 99 | // LOADAMODE and LOADBMODE bits 100 | // 101 | #define CC_CTR_ZERO 0x0 102 | #define CC_CTR_PRD 0x1 103 | #define CC_CTR_ZERO_PRD 0x2 104 | #define CC_LD_DISABLE 0x3 105 | 106 | // 107 | // SHDWAMODE and SHDWBMODE bits 108 | // 109 | #define CC_SHADOW 0x0 110 | #define CC_IMMEDIATE 0x1 111 | 112 | // 113 | // AQCTLA and AQCTLB (Action Qualifier Control) 114 | // 115 | // ZRO, PRD, CAU, CAD, CBU, CBD bits 116 | // 117 | #define AQ_NO_ACTION 0x0 118 | #define AQ_CLEAR 0x1 119 | #define AQ_SET 0x2 120 | #define AQ_TOGGLE 0x3 121 | 122 | // 123 | // DBCTL (Dead-Band Control) 124 | // 125 | // OUT MODE bits 126 | // 127 | #define DB_DISABLE 0x0 128 | #define DBB_ENABLE 0x1 129 | #define DBA_ENABLE 0x2 130 | #define DB_FULL_ENABLE 0x3 131 | 132 | // 133 | // POLSEL bits 134 | // 135 | #define DB_ACTV_HI 0x0 136 | #define DB_ACTV_LOC 0x1 137 | #define DB_ACTV_HIC 0x2 138 | #define DB_ACTV_LO 0x3 139 | 140 | // 141 | // IN MODE 142 | // 143 | #define DBA_ALL 0x0 144 | #define DBB_RED_DBA_FED 0x1 145 | #define DBA_RED_DBB_FED 0x2 146 | #define DBB_ALL 0x3 147 | 148 | // 149 | // CHPCTL (chopper control) 150 | // 151 | // CHPEN bit 152 | // 153 | #define CHP_DISABLE 0x0 154 | #define CHP_ENABLE 0x1 155 | 156 | // 157 | // CHPFREQ bits 158 | // 159 | #define CHP_DIV1 0x0 160 | #define CHP_DIV2 0x1 161 | #define CHP_DIV3 0x2 162 | #define CHP_DIV4 0x3 163 | #define CHP_DIV5 0x4 164 | #define CHP_DIV6 0x5 165 | #define CHP_DIV7 0x6 166 | #define CHP_DIV8 0x7 167 | 168 | // 169 | // CHPDUTY bits 170 | // 171 | #define CHP1_8TH 0x0 172 | #define CHP2_8TH 0x1 173 | #define CHP3_8TH 0x2 174 | #define CHP4_8TH 0x3 175 | #define CHP5_8TH 0x4 176 | #define CHP6_8TH 0x5 177 | #define CHP7_8TH 0x6 178 | 179 | // 180 | // TZSEL (Trip Zone Select) 181 | // 182 | // CBCn and OSHTn bits 183 | // 184 | #define TZ_DISABLE 0x0 185 | #define TZ_ENABLE 0x1 186 | 187 | // 188 | // TZCTL (Trip Zone Control) 189 | // 190 | // TZA and TZB bits 191 | // 192 | #define TZ_HIZ 0x0 193 | #define TZ_FORCE_HI 0x1 194 | #define TZ_FORCE_LO 0x2 195 | #define TZ_NO_CHANGE 0x3 196 | 197 | // 198 | // ETSEL (Event Trigger Select) 199 | // 200 | #define ET_CTR_ZERO 0x1 201 | #define ET_CTR_PRD 0x2 202 | #define ET_CTRU_CMPA 0x4 203 | #define ET_CTRD_CMPA 0x5 204 | #define ET_CTRU_CMPB 0x6 205 | #define ET_CTRD_CMPB 0x7 206 | 207 | // 208 | // ETPS (Event Trigger Pre-scale) 209 | // 210 | // INTPRD, SOCAPRD, SOCBPRD bits 211 | // 212 | #define ET_DISABLE 0x0 213 | #define ET_1ST 0x1 214 | #define ET_2ND 0x2 215 | #define ET_3RD 0x3 216 | 217 | // 218 | // HRPWM (High Resolution PWM) 219 | // 220 | // HRCNFG 221 | // 222 | #define HR_Disable 0x0 223 | #define HR_REP 0x1 224 | #define HR_FEP 0x2 225 | #define HR_BEP 0x3 226 | 227 | #define HR_CMP 0x0 228 | #define HR_PHS 0x1 229 | 230 | #define HR_CTR_ZERO 0x0 231 | #define HR_CTR_PRD 0x1 232 | 233 | 234 | #ifdef __cplusplus 235 | } 236 | #endif /* extern "C" */ 237 | 238 | #endif // - end of DSP2833x_EPWM_DEFINES_H 239 | 240 | // 241 | // End of file 242 | // 243 | 244 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_Examples.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/9 $ 2 | // Checkin $Date: July 2, 2008 14:31:12 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Examples.h 6 | // 7 | // TITLE: DSP2833x Device Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_EXAMPLES_H 46 | #define DSP2833x_EXAMPLES_H 47 | 48 | 49 | #ifdef __cplusplus 50 | extern "C" { 51 | #endif 52 | 53 | // 54 | // Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. 55 | // 56 | //#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT 57 | //#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT 58 | #define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT 59 | //#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT 60 | 61 | #define DSP28_PLLCR 10 62 | //#define DSP28_PLLCR 9 63 | //#define DSP28_PLLCR 8 64 | //#define DSP28_PLLCR 7 65 | //#define DSP28_PLLCR 6 66 | //#define DSP28_PLLCR 5 67 | //#define DSP28_PLLCR 4 68 | //#define DSP28_PLLCR 3 69 | //#define DSP28_PLLCR 2 70 | //#define DSP28_PLLCR 1 71 | //#define DSP28_PLLCR 0 // PLL is bypassed in this mode 72 | 73 | // 74 | // Specify the clock rate of the CPU (SYSCLKOUT) in nS. 75 | // 76 | // Take into account the input clock frequency and the PLL multiplier 77 | // selected in step 1. 78 | // 79 | // Use one of the values provided, or define your own. 80 | // The trailing L is required tells the compiler to treat 81 | // the number as a 64-bit value. 82 | // 83 | // Only one statement should be uncommented. 84 | // 85 | // Example 1:150 MHz devices: 86 | // CLKIN is a 30MHz crystal. 87 | // 88 | // In step 1 the user specified PLLCR = 0xA for a 89 | // 150Mhz CPU clock (SYSCLKOUT = 150MHz). 90 | // 91 | // In this case, the CPU_RATE will be 6.667L 92 | // Uncomment the line: #define CPU_RATE 6.667L 93 | // 94 | // Example 2: 100 MHz devices: 95 | // CLKIN is a 20MHz crystal. 96 | // 97 | // In step 1 the user specified PLLCR = 0xA for a 98 | // 100Mhz CPU clock (SYSCLKOUT = 100MHz). 99 | // 100 | // In this case, the CPU_RATE will be 10.000L 101 | // Uncomment the line: #define CPU_RATE 10.000L 102 | // 103 | #define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) 104 | //#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) 105 | //#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) 106 | //#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) 107 | //#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) 108 | //#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) 109 | //#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) 110 | //#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) 111 | //#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) 112 | //#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) 113 | //#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) 114 | 115 | // 116 | // Target device (in DSP2833x_Device.h) determines CPU frequency 117 | // (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz 118 | // (for 28332 and 28333). User does not have to change anything here. 119 | // 120 | #if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only 121 | #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) 122 | #define CPU_FRQ_150MHZ 0 123 | #else 124 | #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 125 | #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT 126 | #endif 127 | 128 | // 129 | // Include Example Header Files 130 | // 131 | 132 | // 133 | // Prototypes for global functions within the .c files. 134 | // 135 | #include "DSP2833x_GlobalPrototypes.h" 136 | #include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. 137 | #include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. 138 | #include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. 139 | 140 | #define PARTNO_28335 0xEF 141 | #define PARTNO_28334 0xEE 142 | #define PARTNO_28333 0xEA 143 | #define PARTNO_28332 0xED 144 | 145 | // 146 | // Include files not used with DSP/BIOS 147 | // 148 | #ifndef DSP28_BIOS 149 | #include "DSP2833x_DefaultIsr.h" 150 | #endif 151 | 152 | // 153 | // DO NOT MODIFY THIS LINE. 154 | // 155 | #define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ 156 | (long double)CPU_RATE) - 9.0L) / 5.0L) 157 | 158 | #ifdef __cplusplus 159 | } 160 | #endif /* extern "C" */ 161 | 162 | #endif // end of DSP2833x_EXAMPLES_H definition 163 | 164 | // 165 | // End of file 166 | // 167 | 168 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_I2c.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: March 22, 2007 10:40:22 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_I2c.h 6 | // 7 | // TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module 8 | // Register Bit Definitions. 9 | // 10 | //########################################################################### 11 | // $TI Release: F2833x Support Library v2.01.00.00 $ 12 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 13 | // $Copyright: 14 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 15 | // 16 | // Redistribution and use in source and binary forms, with or without 17 | // modification, are permitted provided that the following conditions 18 | // are met: 19 | // 20 | // Redistributions of source code must retain the above copyright 21 | // notice, this list of conditions and the following disclaimer. 22 | // 23 | // Redistributions in binary form must reproduce the above copyright 24 | // notice, this list of conditions and the following disclaimer in the 25 | // documentation and/or other materials provided with the 26 | // distribution. 27 | // 28 | // Neither the name of Texas Instruments Incorporated nor the names of 29 | // its contributors may be used to endorse or promote products derived 30 | // from this software without specific prior written permission. 31 | // 32 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 35 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 36 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 37 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 38 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 42 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 | // $ 44 | //########################################################################### 45 | 46 | #ifndef DSP2833x_I2C_H 47 | #define DSP2833x_I2C_H 48 | 49 | 50 | #ifdef __cplusplus 51 | extern "C" { 52 | #endif 53 | 54 | // 55 | // I2C interrupt vector register bit definitions 56 | // 57 | struct I2CISRC_BITS { // bits description 58 | Uint16 INTCODE:3; // 2:0 Interrupt code 59 | Uint16 rsvd1:13; // 15:3 reserved 60 | }; 61 | 62 | union I2CISRC_REG { 63 | Uint16 all; 64 | struct I2CISRC_BITS bit; 65 | }; 66 | 67 | // 68 | // I2C interrupt mask register bit definitions 69 | // 70 | struct I2CIER_BITS { // bits description 71 | Uint16 ARBL:1; // 0 Arbitration lost interrupt 72 | Uint16 NACK:1; // 1 No ack interrupt 73 | Uint16 ARDY:1; // 2 Register access ready interrupt 74 | Uint16 RRDY:1; // 3 Recieve data ready interrupt 75 | Uint16 XRDY:1; // 4 Transmit data ready interrupt 76 | Uint16 SCD:1; // 5 Stop condition detection 77 | Uint16 AAS:1; // 6 Address as slave 78 | Uint16 rsvd:9; // 15:7 reserved 79 | }; 80 | 81 | union I2CIER_REG { 82 | Uint16 all; 83 | struct I2CIER_BITS bit; 84 | }; 85 | 86 | // 87 | // I2C status register bit definitions 88 | // 89 | struct I2CSTR_BITS { // bits description 90 | Uint16 ARBL:1; // 0 Arbitration lost interrupt 91 | Uint16 NACK:1; // 1 No ack interrupt 92 | Uint16 ARDY:1; // 2 Register access ready interrupt 93 | Uint16 RRDY:1; // 3 Recieve data ready interrupt 94 | Uint16 XRDY:1; // 4 Transmit data ready interrupt 95 | Uint16 SCD:1; // 5 Stop condition detection 96 | Uint16 rsvd1:2; // 7:6 reserved 97 | Uint16 AD0:1; // 8 Address Zero 98 | Uint16 AAS:1; // 9 Address as slave 99 | Uint16 XSMT:1; // 10 XMIT shift empty 100 | Uint16 RSFULL:1; // 11 Recieve shift full 101 | Uint16 BB:1; // 12 Bus busy 102 | Uint16 NACKSNT:1; // 13 A no ack sent 103 | Uint16 SDIR:1; // 14 Slave direction 104 | Uint16 rsvd2:1; // 15 reserved 105 | }; 106 | 107 | union I2CSTR_REG { 108 | Uint16 all; 109 | struct I2CSTR_BITS bit; 110 | }; 111 | 112 | // 113 | // I2C mode control register bit definitions 114 | // 115 | struct I2CMDR_BITS { // bits description 116 | Uint16 BC:3; // 2:0 Bit count 117 | Uint16 FDF:1; // 3 Free data format 118 | Uint16 STB:1; // 4 Start byte 119 | Uint16 IRS:1; // 5 I2C Reset not 120 | Uint16 DLB:1; // 6 Digital loopback 121 | Uint16 RM:1; // 7 Repeat mode 122 | Uint16 XA:1; // 8 Expand address 123 | Uint16 TRX:1; // 9 Transmitter/reciever 124 | Uint16 MST:1; // 10 Master/slave 125 | Uint16 STP:1; // 11 Stop condition 126 | Uint16 rsvd1:1; // 12 reserved 127 | Uint16 STT:1; // 13 Start condition 128 | Uint16 FREE:1; // 14 Emulation mode 129 | Uint16 NACKMOD:1; // 15 No Ack mode 130 | }; 131 | 132 | union I2CMDR_REG { 133 | Uint16 all; 134 | struct I2CMDR_BITS bit; 135 | }; 136 | 137 | // 138 | // I2C extended mode control register bit definitions 139 | // 140 | struct I2CEMDR_BITS { // bits description 141 | Uint16 BCM:1; // 0 Backward compatibility mode 142 | Uint16 rsvd:15; // 15 reserved 143 | }; 144 | 145 | union I2CEMDR_REG { 146 | Uint16 all; 147 | struct I2CEMDR_BITS bit; 148 | }; 149 | 150 | // 151 | // I2C pre-scaler register bit definitions 152 | // 153 | struct I2CPSC_BITS { // bits description 154 | Uint16 IPSC:8; // 7:0 pre-scaler 155 | Uint16 rsvd1:8; // 15:8 reserved 156 | }; 157 | 158 | union I2CPSC_REG { 159 | Uint16 all; 160 | struct I2CPSC_BITS bit; 161 | }; 162 | 163 | // 164 | // TX FIFO control register bit definitions 165 | // 166 | struct I2CFFTX_BITS { // bits description 167 | Uint16 TXFFIL:5; // 4:0 FIFO interrupt level 168 | Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable 169 | Uint16 TXFFINTCLR:1; // 6 FIFO clear 170 | Uint16 TXFFINT:1; // 7 FIFO interrupt flag 171 | Uint16 TXFFST:5; // 12:8 FIFO level status 172 | Uint16 TXFFRST:1; // 13 FIFO reset 173 | Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs 174 | Uint16 rsvd1:1; // 15 reserved 175 | }; 176 | 177 | union I2CFFTX_REG { 178 | Uint16 all; 179 | struct I2CFFTX_BITS bit; 180 | }; 181 | 182 | // 183 | // RX FIFO control register bit definitions 184 | // 185 | struct I2CFFRX_BITS { // bits description 186 | Uint16 RXFFIL:5; // 4:0 FIFO interrupt level 187 | Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable 188 | Uint16 RXFFINTCLR:1; // 6 FIFO clear 189 | Uint16 RXFFINT:1; // 7 FIFO interrupt flag 190 | Uint16 RXFFST:5; // 12:8 FIFO level 191 | Uint16 RXFFRST:1; // 13 FIFO reset 192 | Uint16 rsvd1:2; // 15:14 reserved 193 | }; 194 | 195 | union I2CFFRX_REG { 196 | Uint16 all; 197 | struct I2CFFRX_BITS bit; 198 | }; 199 | 200 | struct I2C_REGS { 201 | Uint16 I2COAR; // Own address register 202 | union I2CIER_REG I2CIER; // Interrupt enable 203 | union I2CSTR_REG I2CSTR; // Interrupt status 204 | Uint16 I2CCLKL; // Clock divider low 205 | Uint16 I2CCLKH; // Clock divider high 206 | Uint16 I2CCNT; // Data count 207 | Uint16 I2CDRR; // Data recieve 208 | Uint16 I2CSAR; // Slave address 209 | Uint16 I2CDXR; // Data transmit 210 | union I2CMDR_REG I2CMDR; // Mode 211 | union I2CISRC_REG I2CISRC; // Interrupt source 212 | union I2CEMDR_REG I2CEMDR; // Extended Mode 213 | union I2CPSC_REG I2CPSC; // Pre-scaler 214 | Uint16 rsvd2[19]; // reserved 215 | union I2CFFTX_REG I2CFFTX; // Transmit FIFO 216 | union I2CFFRX_REG I2CFFRX; // Recieve FIFO 217 | }; 218 | 219 | // 220 | // External References & Function Declarations 221 | // 222 | extern volatile struct I2C_REGS I2caRegs; 223 | 224 | #ifdef __cplusplus 225 | } 226 | #endif /* extern "C" */ 227 | 228 | #endif // end of DSP2833x_I2C_H definition 229 | 230 | // 231 | // End of file 232 | // 233 | 234 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_I2c_defines.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: April 16, 2008 17:16:47 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_I2cExample.h 6 | // 7 | // TITLE: 2833x I2C Example Code Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_I2C_DEFINES_H 46 | #define DSP2833x_I2C_DEFINES_H 47 | 48 | // 49 | // Defines 50 | // 51 | 52 | // 53 | // Error Messages 54 | // 55 | #define I2C_ERROR 0xFFFF 56 | #define I2C_ARB_LOST_ERROR 0x0001 57 | #define I2C_NACK_ERROR 0x0002 58 | #define I2C_BUS_BUSY_ERROR 0x1000 59 | #define I2C_STP_NOT_READY_ERROR 0x5555 60 | #define I2C_NO_FLAGS 0xAAAA 61 | #define I2C_SUCCESS 0x0000 62 | 63 | // 64 | // Clear Status Flags 65 | // 66 | #define I2C_CLR_AL_BIT 0x0001 67 | #define I2C_CLR_NACK_BIT 0x0002 68 | #define I2C_CLR_ARDY_BIT 0x0004 69 | #define I2C_CLR_RRDY_BIT 0x0008 70 | #define I2C_CLR_SCD_BIT 0x0020 71 | 72 | // 73 | // Interrupt Source Messages 74 | // 75 | #define I2C_NO_ISRC 0x0000 76 | #define I2C_ARB_ISRC 0x0001 77 | #define I2C_NACK_ISRC 0x0002 78 | #define I2C_ARDY_ISRC 0x0003 79 | #define I2C_RX_ISRC 0x0004 80 | #define I2C_TX_ISRC 0x0005 81 | #define I2C_SCD_ISRC 0x0006 82 | #define I2C_AAS_ISRC 0x0007 83 | 84 | // 85 | // I2CMSG structure defines 86 | // 87 | #define I2C_NO_STOP 0 88 | #define I2C_YES_STOP 1 89 | #define I2C_RECEIVE 0 90 | #define I2C_TRANSMIT 1 91 | #define I2C_MAX_BUFFER_SIZE 16 92 | 93 | // 94 | // I2C Slave State defines 95 | // 96 | #define I2C_NOTSLAVE 0 97 | #define I2C_ADDR_AS_SLAVE 1 98 | #define I2C_ST_MSG_READY 2 99 | 100 | // 101 | // I2C Slave Receiver messages defines 102 | // 103 | #define I2C_SND_MSG1 1 104 | #define I2C_SND_MSG2 2 105 | 106 | // 107 | // I2C State defines 108 | // 109 | #define I2C_IDLE 0 110 | #define I2C_SLAVE_RECEIVER 1 111 | #define I2C_SLAVE_TRANSMITTER 2 112 | #define I2C_MASTER_RECEIVER 3 113 | #define I2C_MASTER_TRANSMITTER 4 114 | 115 | // 116 | // I2C Message Commands for I2CMSG struct 117 | // 118 | #define I2C_MSGSTAT_INACTIVE 0x0000 119 | #define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 120 | #define I2C_MSGSTAT_WRITE_BUSY 0x0011 121 | #define I2C_MSGSTAT_SEND_NOSTOP 0x0020 122 | #define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 123 | #define I2C_MSGSTAT_RESTART 0x0022 124 | #define I2C_MSGSTAT_READ_BUSY 0x0023 125 | 126 | // 127 | // Generic defines 128 | // 129 | #define I2C_TRUE 1 130 | #define I2C_FALSE 0 131 | #define I2C_YES 1 132 | #define I2C_NO 0 133 | #define I2C_DUMMY_BYTE 0 134 | 135 | // 136 | // Structures 137 | // 138 | 139 | // 140 | // I2C Message Structure 141 | // 142 | struct I2CMSG 143 | { 144 | Uint16 MsgStatus; // Word stating what state msg is in: 145 | // I2C_MSGCMD_INACTIVE = do not send msg 146 | // I2C_MSGCMD_BUSY = msg start has been sent, 147 | // awaiting stop 148 | // I2C_MSGCMD_SEND_WITHSTOP = command to send 149 | // master trans msg complete with a stop bit 150 | // I2C_MSGCMD_SEND_NOSTOP = command to send 151 | // master trans msg without the stop bit 152 | // I2C_MSGCMD_RESTART = command to send a restart 153 | // as a master receiver with a stop bit 154 | Uint16 SlaveAddress; // I2C address of slave msg is intended for 155 | Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) 156 | 157 | // 158 | // EEPROM address of data associated with msg (high byte) 159 | // 160 | Uint16 MemoryHighAddr; 161 | 162 | // 163 | // EEPROM address of data associated with msg (low byte) 164 | // 165 | Uint16 MemoryLowAddr; 166 | 167 | // 168 | // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to 169 | // the FIFO's 170 | Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; 171 | }; 172 | 173 | 174 | #endif // end of DSP2833x_I2C_DEFINES_H definition 175 | 176 | // 177 | // End of file 178 | // 179 | 180 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_PieCtrl.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:52:24 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_PieCtrl.h 6 | // 7 | // TITLE: DSP2833x Device PIE Control Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_PIE_CTRL_H 46 | #define DSP2833x_PIE_CTRL_H 47 | 48 | #ifdef __cplusplus 49 | extern "C" { 50 | #endif 51 | 52 | // 53 | // PIE Control Register Bit Definitions 54 | // 55 | 56 | // 57 | // PIECTRL: Register bit definitions 58 | // 59 | struct PIECTRL_BITS { // bits description 60 | Uint16 ENPIE:1; // 0 Enable PIE block 61 | Uint16 PIEVECT:15; // 15:1 Fetched vector address 62 | }; 63 | 64 | union PIECTRL_REG { 65 | Uint16 all; 66 | struct PIECTRL_BITS bit; 67 | }; 68 | 69 | // 70 | // PIEIER: Register bit definitions 71 | // 72 | struct PIEIER_BITS { // bits description 73 | Uint16 INTx1:1; // 0 INTx.1 74 | Uint16 INTx2:1; // 1 INTx.2 75 | Uint16 INTx3:1; // 2 INTx.3 76 | Uint16 INTx4:1; // 3 INTx.4 77 | Uint16 INTx5:1; // 4 INTx.5 78 | Uint16 INTx6:1; // 5 INTx.6 79 | Uint16 INTx7:1; // 6 INTx.7 80 | Uint16 INTx8:1; // 7 INTx.8 81 | Uint16 rsvd:8; // 15:8 reserved 82 | }; 83 | 84 | union PIEIER_REG { 85 | Uint16 all; 86 | struct PIEIER_BITS bit; 87 | }; 88 | 89 | // 90 | // PIEIFR: Register bit definitions 91 | // 92 | struct PIEIFR_BITS { // bits description 93 | Uint16 INTx1:1; // 0 INTx.1 94 | Uint16 INTx2:1; // 1 INTx.2 95 | Uint16 INTx3:1; // 2 INTx.3 96 | Uint16 INTx4:1; // 3 INTx.4 97 | Uint16 INTx5:1; // 4 INTx.5 98 | Uint16 INTx6:1; // 5 INTx.6 99 | Uint16 INTx7:1; // 6 INTx.7 100 | Uint16 INTx8:1; // 7 INTx.8 101 | Uint16 rsvd:8; // 15:8 reserved 102 | }; 103 | 104 | union PIEIFR_REG { 105 | Uint16 all; 106 | struct PIEIFR_BITS bit; 107 | }; 108 | 109 | // 110 | // PIEACK: Register bit definitions 111 | // 112 | struct PIEACK_BITS { // bits description 113 | Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 114 | Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 115 | Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 116 | Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 117 | Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 118 | Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 119 | Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 120 | Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 121 | Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 122 | Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 123 | Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 124 | Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 125 | Uint16 rsvd:4; // 15:12 reserved 126 | }; 127 | 128 | union PIEACK_REG { 129 | Uint16 all; 130 | struct PIEACK_BITS bit; 131 | }; 132 | 133 | // 134 | // PIE Control Register File 135 | // 136 | struct PIE_CTRL_REGS { 137 | union PIECTRL_REG PIECTRL; // PIE control register 138 | union PIEACK_REG PIEACK; // PIE acknowledge 139 | union PIEIER_REG PIEIER1; // PIE int1 IER register 140 | union PIEIFR_REG PIEIFR1; // PIE int1 IFR register 141 | union PIEIER_REG PIEIER2; // PIE INT2 IER register 142 | union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register 143 | union PIEIER_REG PIEIER3; // PIE INT3 IER register 144 | union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register 145 | union PIEIER_REG PIEIER4; // PIE INT4 IER register 146 | union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register 147 | union PIEIER_REG PIEIER5; // PIE INT5 IER register 148 | union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register 149 | union PIEIER_REG PIEIER6; // PIE INT6 IER register 150 | union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register 151 | union PIEIER_REG PIEIER7; // PIE INT7 IER register 152 | union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register 153 | union PIEIER_REG PIEIER8; // PIE INT8 IER register 154 | union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register 155 | union PIEIER_REG PIEIER9; // PIE INT9 IER register 156 | union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register 157 | union PIEIER_REG PIEIER10; // PIE int10 IER register 158 | union PIEIFR_REG PIEIFR10; // PIE int10 IFR register 159 | union PIEIER_REG PIEIER11; // PIE int11 IER register 160 | union PIEIFR_REG PIEIFR11; // PIE int11 IFR register 161 | union PIEIER_REG PIEIER12; // PIE int12 IER register 162 | union PIEIFR_REG PIEIFR12; // PIE int12 IFR register 163 | }; 164 | 165 | // 166 | // Defines 167 | // 168 | #define PIEACK_GROUP1 0x0001 169 | #define PIEACK_GROUP2 0x0002 170 | #define PIEACK_GROUP3 0x0004 171 | #define PIEACK_GROUP4 0x0008 172 | #define PIEACK_GROUP5 0x0010 173 | #define PIEACK_GROUP6 0x0020 174 | #define PIEACK_GROUP7 0x0040 175 | #define PIEACK_GROUP8 0x0080 176 | #define PIEACK_GROUP9 0x0100 177 | #define PIEACK_GROUP10 0x0200 178 | #define PIEACK_GROUP11 0x0400 179 | #define PIEACK_GROUP12 0x0800 180 | 181 | // 182 | // PIE Control Registers External References & Function Declarations 183 | // 184 | extern volatile struct PIE_CTRL_REGS PieCtrlRegs; 185 | 186 | #ifdef __cplusplus 187 | } 188 | #endif /* extern "C" */ 189 | 190 | #endif // end of DSP2833x_PIE_CTRL_H definition 191 | 192 | // 193 | // End of file 194 | // 195 | 196 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_PieVect.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: March 16, 2007 09:00:21 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_PieVect.h 6 | // 7 | // TITLE: DSP2833x Devices PIE Vector Table Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_PIE_VECT_H 46 | #define DSP2833x_PIE_VECT_H 47 | 48 | #ifdef __cplusplus 49 | extern "C" { 50 | #endif 51 | 52 | // 53 | // PIE Interrupt Vector Table Definition 54 | // 55 | 56 | // 57 | // Typedef used to create a user type called PINT (pointer to interrupt) 58 | // 59 | typedef interrupt void(*PINT)(void); 60 | 61 | // 62 | // Vector Table Define 63 | // 64 | struct PIE_VECT_TABLE { 65 | // 66 | // Reset is never fetched from this table. It will always be fetched from 67 | // 0x3FFFC0 in boot ROM 68 | // 69 | PINT PIE1_RESERVED; 70 | PINT PIE2_RESERVED; 71 | PINT PIE3_RESERVED; 72 | PINT PIE4_RESERVED; 73 | PINT PIE5_RESERVED; 74 | PINT PIE6_RESERVED; 75 | PINT PIE7_RESERVED; 76 | PINT PIE8_RESERVED; 77 | PINT PIE9_RESERVED; 78 | PINT PIE10_RESERVED; 79 | PINT PIE11_RESERVED; 80 | PINT PIE12_RESERVED; 81 | PINT PIE13_RESERVED; 82 | 83 | // 84 | // Non-Peripheral Interrupts 85 | // 86 | PINT XINT13; // XINT13 / CPU-Timer1 87 | PINT TINT2; // CPU-Timer2 88 | PINT DATALOG; // Datalogging interrupt 89 | PINT RTOSINT; // RTOS interrupt 90 | PINT EMUINT; // Emulation interrupt 91 | PINT XNMI; // Non-maskable interrupt 92 | PINT ILLEGAL; // Illegal operation TRAP 93 | PINT USER1; // User Defined trap 1 94 | PINT USER2; // User Defined trap 2 95 | PINT USER3; // User Defined trap 3 96 | PINT USER4; // User Defined trap 4 97 | PINT USER5; // User Defined trap 5 98 | PINT USER6; // User Defined trap 6 99 | PINT USER7; // User Defined trap 7 100 | PINT USER8; // User Defined trap 8 101 | PINT USER9; // User Defined trap 9 102 | PINT USER10; // User Defined trap 10 103 | PINT USER11; // User Defined trap 11 104 | PINT USER12; // User Defined trap 12 105 | 106 | // 107 | // Group 1 PIE Peripheral Vectors 108 | // 109 | PINT SEQ1INT; 110 | PINT SEQ2INT; 111 | PINT rsvd1_3; 112 | PINT XINT1; 113 | PINT XINT2; 114 | PINT ADCINT; // ADC 115 | PINT TINT0; // Timer 0 116 | PINT WAKEINT; // WD 117 | 118 | // 119 | // Group 2 PIE Peripheral Vectors 120 | // 121 | PINT EPWM1_TZINT; // EPWM-1 122 | PINT EPWM2_TZINT; // EPWM-2 123 | PINT EPWM3_TZINT; // EPWM-3 124 | PINT EPWM4_TZINT; // EPWM-4 125 | PINT EPWM5_TZINT; // EPWM-5 126 | PINT EPWM6_TZINT; // EPWM-6 127 | PINT rsvd2_7; 128 | PINT rsvd2_8; 129 | 130 | // 131 | // Group 3 PIE Peripheral Vectors 132 | // 133 | PINT EPWM1_INT; // EPWM-1 134 | PINT EPWM2_INT; // EPWM-2 135 | PINT EPWM3_INT; // EPWM-3 136 | PINT EPWM4_INT; // EPWM-4 137 | PINT EPWM5_INT; // EPWM-5 138 | PINT EPWM6_INT; // EPWM-6 139 | PINT rsvd3_7; 140 | PINT rsvd3_8; 141 | 142 | // 143 | // Group 4 PIE Peripheral Vectors 144 | // 145 | PINT ECAP1_INT; // ECAP-1 146 | PINT ECAP2_INT; // ECAP-2 147 | PINT ECAP3_INT; // ECAP-3 148 | PINT ECAP4_INT; // ECAP-4 149 | PINT ECAP5_INT; // ECAP-5 150 | PINT ECAP6_INT; // ECAP-6 151 | PINT rsvd4_7; 152 | PINT rsvd4_8; 153 | 154 | // 155 | // Group 5 PIE Peripheral Vectors 156 | // 157 | PINT EQEP1_INT; // EQEP-1 158 | PINT EQEP2_INT; // EQEP-2 159 | PINT rsvd5_3; 160 | PINT rsvd5_4; 161 | PINT rsvd5_5; 162 | PINT rsvd5_6; 163 | PINT rsvd5_7; 164 | PINT rsvd5_8; 165 | 166 | // 167 | // Group 6 PIE Peripheral Vectors 168 | // 169 | PINT SPIRXINTA; // SPI-A 170 | PINT SPITXINTA; // SPI-A 171 | PINT MRINTB; // McBSP-B 172 | PINT MXINTB; // McBSP-B 173 | PINT MRINTA; // McBSP-A 174 | PINT MXINTA; // McBSP-A 175 | PINT rsvd6_7; 176 | PINT rsvd6_8; 177 | 178 | // 179 | // Group 7 PIE Peripheral Vectors 180 | // 181 | PINT DINTCH1; // DMA 182 | PINT DINTCH2; // DMA 183 | PINT DINTCH3; // DMA 184 | PINT DINTCH4; // DMA 185 | PINT DINTCH5; // DMA 186 | PINT DINTCH6; // DMA 187 | PINT rsvd7_7; 188 | PINT rsvd7_8; 189 | 190 | // 191 | // Group 8 PIE Peripheral Vectors 192 | // 193 | PINT I2CINT1A; // I2C-A 194 | PINT I2CINT2A; // I2C-A 195 | PINT rsvd8_3; 196 | PINT rsvd8_4; 197 | PINT SCIRXINTC; // SCI-C 198 | PINT SCITXINTC; // SCI-C 199 | PINT rsvd8_7; 200 | PINT rsvd8_8; 201 | 202 | // 203 | // Group 9 PIE Peripheral Vectors 204 | // 205 | PINT SCIRXINTA; // SCI-A 206 | PINT SCITXINTA; // SCI-A 207 | PINT SCIRXINTB; // SCI-B 208 | PINT SCITXINTB; // SCI-B 209 | PINT ECAN0INTA; // eCAN-A 210 | PINT ECAN1INTA; // eCAN-A 211 | PINT ECAN0INTB; // eCAN-B 212 | PINT ECAN1INTB; // eCAN-B 213 | 214 | // 215 | // Group 10 PIE Peripheral Vectors 216 | // 217 | PINT rsvd10_1; 218 | PINT rsvd10_2; 219 | PINT rsvd10_3; 220 | PINT rsvd10_4; 221 | PINT rsvd10_5; 222 | PINT rsvd10_6; 223 | PINT rsvd10_7; 224 | PINT rsvd10_8; 225 | 226 | // 227 | // Group 11 PIE Peripheral Vectors 228 | // 229 | PINT rsvd11_1; 230 | PINT rsvd11_2; 231 | PINT rsvd11_3; 232 | PINT rsvd11_4; 233 | PINT rsvd11_5; 234 | PINT rsvd11_6; 235 | PINT rsvd11_7; 236 | PINT rsvd11_8; 237 | 238 | // 239 | // Group 12 PIE Peripheral Vectors 240 | // 241 | PINT XINT3; // External interrupt 242 | PINT XINT4; 243 | PINT XINT5; 244 | PINT XINT6; 245 | PINT XINT7; 246 | PINT rsvd12_6; 247 | PINT LVF; // Latched overflow 248 | PINT LUF; // Latched underflow 249 | }; 250 | 251 | // 252 | // PIE Interrupt Vector Table External References & Function Declarations 253 | // 254 | extern volatile struct PIE_VECT_TABLE PieVectTable; 255 | 256 | #ifdef __cplusplus 257 | } 258 | #endif /* extern "C" */ 259 | 260 | #endif // end of DSP2833x_PIE_VECT_H definition 261 | 262 | // 263 | // End of file 264 | // 265 | 266 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_Sci.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: March 1, 2007 15:57:02 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Sci.h 6 | // 7 | // TITLE: DSP2833x Device SCI Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_SCI_H 46 | #define DSP2833x_SCI_H 47 | 48 | #ifdef __cplusplus 49 | extern "C" { 50 | #endif 51 | 52 | // 53 | // SCI Individual Register Bit Definitions 54 | // 55 | 56 | // 57 | // SCICCR communication control register bit definitions 58 | // 59 | struct SCICCR_BITS { // bit description 60 | Uint16 SCICHAR:3; // 2:0 Character length control 61 | Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control 62 | Uint16 LOOPBKENA:1; // 4 Loop Back enable 63 | Uint16 PARITYENA:1; // 5 Parity enable 64 | Uint16 PARITY:1; // 6 Even or Odd Parity 65 | Uint16 STOPBITS:1; // 7 Number of Stop Bits 66 | Uint16 rsvd1:8; // 15:8 reserved 67 | }; 68 | 69 | union SCICCR_REG { 70 | Uint16 all; 71 | struct SCICCR_BITS bit; 72 | }; 73 | 74 | // 75 | // SCICTL1 control register 1 bit definitions 76 | // 77 | struct SCICTL1_BITS { // bit description 78 | Uint16 RXENA:1; // 0 SCI receiver enable 79 | Uint16 TXENA:1; // 1 SCI transmitter enable 80 | Uint16 SLEEP:1; // 2 SCI sleep 81 | Uint16 TXWAKE:1; // 3 Transmitter wakeup method 82 | Uint16 rsvd:1; // 4 reserved 83 | Uint16 SWRESET:1; // 5 Software reset 84 | Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable 85 | Uint16 rsvd1:9; // 15:7 reserved 86 | }; 87 | 88 | union SCICTL1_REG { 89 | Uint16 all; 90 | struct SCICTL1_BITS bit; 91 | }; 92 | 93 | // 94 | // SCICTL2 control register 2 bit definitions 95 | // 96 | struct SCICTL2_BITS { // bit description 97 | Uint16 TXINTENA:1; // 0 Transmit interrupt enable 98 | Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable 99 | Uint16 rsvd:4; // 5:2 reserved 100 | Uint16 TXEMPTY:1; // 6 Transmitter empty flag 101 | Uint16 TXRDY:1; // 7 Transmitter ready flag 102 | Uint16 rsvd1:8; // 15:8 reserved 103 | }; 104 | 105 | union SCICTL2_REG { 106 | Uint16 all; 107 | struct SCICTL2_BITS bit; 108 | }; 109 | 110 | // 111 | // SCIRXST Receiver status register bit definitions 112 | // 113 | struct SCIRXST_BITS { // bit description 114 | Uint16 rsvd:1; // 0 reserved 115 | Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag 116 | Uint16 PE:1; // 2 Parity error flag 117 | Uint16 OE:1; // 3 Overrun error flag 118 | Uint16 FE:1; // 4 Framing error flag 119 | Uint16 BRKDT:1; // 5 Break-detect flag 120 | Uint16 RXRDY:1; // 6 Receiver ready flag 121 | Uint16 RXERROR:1; // 7 Receiver error flag 122 | }; 123 | 124 | union SCIRXST_REG { 125 | Uint16 all; 126 | struct SCIRXST_BITS bit; 127 | }; 128 | 129 | // 130 | // SCIRXBUF Receiver Data Buffer with FIFO bit definitions 131 | // 132 | struct SCIRXBUF_BITS { // bits description 133 | Uint16 RXDT:8; // 7:0 Receive word 134 | Uint16 rsvd:6; // 13:8 reserved 135 | Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode 136 | Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode 137 | }; 138 | 139 | union SCIRXBUF_REG { 140 | Uint16 all; 141 | struct SCIRXBUF_BITS bit; 142 | }; 143 | 144 | // 145 | // SCIPRI Priority control register bit definitions 146 | // 147 | struct SCIPRI_BITS { // bit description 148 | Uint16 rsvd:3; // 2:0 reserved 149 | Uint16 FREE:1; // 3 Free emulation suspend mode 150 | Uint16 SOFT:1; // 4 Soft emulation suspend mode 151 | Uint16 rsvd1:3; // 7:5 reserved 152 | }; 153 | 154 | union SCIPRI_REG { 155 | Uint16 all; 156 | struct SCIPRI_BITS bit; 157 | }; 158 | 159 | // 160 | // SCI FIFO Transmit register bit definitions 161 | // 162 | struct SCIFFTX_BITS { // bit description 163 | Uint16 TXFFIL:5; // 4:0 Interrupt level 164 | Uint16 TXFFIENA:1; // 5 Interrupt enable 165 | Uint16 TXFFINTCLR:1; // 6 Clear INT flag 166 | Uint16 TXFFINT:1; // 7 INT flag 167 | Uint16 TXFFST:5; // 12:8 FIFO status 168 | Uint16 TXFIFOXRESET:1; // 13 FIFO reset 169 | Uint16 SCIFFENA:1; // 14 Enhancement enable 170 | Uint16 SCIRST:1; // 15 SCI reset rx/tx channels 171 | }; 172 | 173 | union SCIFFTX_REG { 174 | Uint16 all; 175 | struct SCIFFTX_BITS bit; 176 | }; 177 | 178 | // 179 | // SCI FIFO recieve register bit definitions 180 | // 181 | struct SCIFFRX_BITS { // bits description 182 | Uint16 RXFFIL:5; // 4:0 Interrupt level 183 | Uint16 RXFFIENA:1; // 5 Interrupt enable 184 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 185 | Uint16 RXFFINT:1; // 7 INT flag 186 | Uint16 RXFFST:5; // 12:8 FIFO status 187 | Uint16 RXFIFORESET:1; // 13 FIFO reset 188 | Uint16 RXFFOVRCLR:1; // 14 Clear overflow 189 | Uint16 RXFFOVF:1; // 15 FIFO overflow 190 | }; 191 | 192 | union SCIFFRX_REG { 193 | Uint16 all; 194 | struct SCIFFRX_BITS bit; 195 | }; 196 | 197 | // 198 | // SCI FIFO control register bit definitions 199 | // 200 | struct SCIFFCT_BITS { // bits description 201 | Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay 202 | Uint16 rsvd:5; // 12:8 reserved 203 | Uint16 CDC:1; // 13 Auto baud mode enable 204 | Uint16 ABDCLR:1; // 14 Auto baud clear 205 | Uint16 ABD:1; // 15 Auto baud detect 206 | }; 207 | 208 | union SCIFFCT_REG { 209 | Uint16 all; 210 | struct SCIFFCT_BITS bit; 211 | }; 212 | 213 | // 214 | // SCI Register File 215 | // 216 | struct SCI_REGS { 217 | union SCICCR_REG SCICCR; // Communications control register 218 | union SCICTL1_REG SCICTL1; // Control register 1 219 | Uint16 SCIHBAUD; // Baud rate (high) register 220 | Uint16 SCILBAUD; // Baud rate (low) register 221 | union SCICTL2_REG SCICTL2; // Control register 2 222 | union SCIRXST_REG SCIRXST; // Recieve status register 223 | Uint16 SCIRXEMU; // Recieve emulation buffer register 224 | union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer 225 | Uint16 rsvd1; // reserved 226 | Uint16 SCITXBUF; // Transmit data buffer 227 | union SCIFFTX_REG SCIFFTX; // FIFO transmit register 228 | union SCIFFRX_REG SCIFFRX; // FIFO recieve register 229 | union SCIFFCT_REG SCIFFCT; // FIFO control register 230 | Uint16 rsvd2; // reserved 231 | Uint16 rsvd3; // reserved 232 | union SCIPRI_REG SCIPRI; // FIFO Priority control 233 | }; 234 | 235 | // 236 | // SCI External References & Function Declarations 237 | // 238 | extern volatile struct SCI_REGS SciaRegs; 239 | extern volatile struct SCI_REGS ScibRegs; 240 | extern volatile struct SCI_REGS ScicRegs; 241 | 242 | #ifdef __cplusplus 243 | } 244 | #endif /* extern "C" */ 245 | 246 | #endif // end of DSP2833x_SCI_H definition 247 | 248 | // 249 | // End of file 250 | // 251 | 252 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_Spi.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/3 $ 2 | // Checkin $Date: April 17, 2008 11:08:27 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Spi.h 6 | // 7 | // TITLE: DSP2833x Device SPI Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_SPI_H 46 | #define DSP2833x_SPI_H 47 | 48 | #ifdef __cplusplus 49 | extern "C" { 50 | #endif 51 | 52 | // 53 | // SPI Individual Register Bit Definitions 54 | // 55 | 56 | // 57 | // SPI FIFO Transmit register bit definitions 58 | // 59 | struct SPIFFTX_BITS { // bit description 60 | Uint16 TXFFIL:5; // 4:0 Interrupt level 61 | Uint16 TXFFIENA:1; // 5 Interrupt enable 62 | Uint16 TXFFINTCLR:1; // 6 Clear INT flag 63 | Uint16 TXFFINT:1; // 7 INT flag 64 | Uint16 TXFFST:5; // 12:8 FIFO status 65 | Uint16 TXFIFO:1; // 13 FIFO reset 66 | Uint16 SPIFFENA:1; // 14 Enhancement enable 67 | Uint16 SPIRST:1; // 15 Reset SPI 68 | }; 69 | 70 | union SPIFFTX_REG { 71 | Uint16 all; 72 | struct SPIFFTX_BITS bit; 73 | }; 74 | 75 | // 76 | // SPI FIFO recieve register bit definitions 77 | // 78 | struct SPIFFRX_BITS { // bits description 79 | Uint16 RXFFIL:5; // 4:0 Interrupt level 80 | Uint16 RXFFIENA:1; // 5 Interrupt enable 81 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 82 | Uint16 RXFFINT:1; // 7 INT flag 83 | Uint16 RXFFST:5; // 12:8 FIFO status 84 | Uint16 RXFIFORESET:1; // 13 FIFO reset 85 | Uint16 RXFFOVFCLR:1; // 14 Clear overflow 86 | Uint16 RXFFOVF:1; // 15 FIFO overflow 87 | }; 88 | 89 | union SPIFFRX_REG { 90 | Uint16 all; 91 | struct SPIFFRX_BITS bit; 92 | }; 93 | 94 | // 95 | // SPI FIFO control register bit definitions 96 | // 97 | struct SPIFFCT_BITS { // bits description 98 | Uint16 TXDLY:8; // 7:0 FIFO transmit delay 99 | Uint16 rsvd:8; // 15:8 reserved 100 | }; 101 | 102 | union SPIFFCT_REG { 103 | Uint16 all; 104 | struct SPIFFCT_BITS bit; 105 | }; 106 | 107 | // 108 | // SPI configuration register bit definitions 109 | // 110 | struct SPICCR_BITS { // bits description 111 | Uint16 SPICHAR:4; // 3:0 Character length control 112 | Uint16 SPILBK:1; // 4 Loop-back enable/disable 113 | Uint16 rsvd1:1; // 5 reserved 114 | Uint16 CLKPOLARITY:1; // 6 Clock polarity 115 | Uint16 SPISWRESET:1; // 7 SPI SW Reset 116 | Uint16 rsvd2:8; // 15:8 reserved 117 | }; 118 | 119 | union SPICCR_REG { 120 | Uint16 all; 121 | struct SPICCR_BITS bit; 122 | }; 123 | 124 | // 125 | // SPI operation control register bit definitions 126 | // 127 | struct SPICTL_BITS { // bits description 128 | Uint16 SPIINTENA:1; // 0 Interrupt enable 129 | Uint16 TALK:1; // 1 Master/Slave transmit enable 130 | Uint16 MASTER_SLAVE:1; // 2 Network control mode 131 | Uint16 CLK_PHASE:1; // 3 Clock phase select 132 | Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable 133 | Uint16 rsvd:11; // 15:5 reserved 134 | }; 135 | 136 | union SPICTL_REG { 137 | Uint16 all; 138 | struct SPICTL_BITS bit; 139 | }; 140 | 141 | // 142 | // SPI status register bit definitions 143 | // 144 | struct SPISTS_BITS { // bits description 145 | Uint16 rsvd1:5; // 4:0 reserved 146 | Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag 147 | Uint16 INT_FLAG:1; // 6 SPI interrupt flag 148 | Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag 149 | Uint16 rsvd2:8; // 15:8 reserved 150 | }; 151 | 152 | union SPISTS_REG { 153 | Uint16 all; 154 | struct SPISTS_BITS bit; 155 | }; 156 | 157 | // 158 | // SPI priority control register bit definitions 159 | // 160 | struct SPIPRI_BITS { // bits description 161 | Uint16 rsvd1:4; // 3:0 reserved 162 | Uint16 FREE:1; // 4 Free emulation mode control 163 | Uint16 SOFT:1; // 5 Soft emulation mode control 164 | Uint16 rsvd2:1; // 6 reserved 165 | Uint16 rsvd3:9; // 15:7 reserved 166 | }; 167 | 168 | union SPIPRI_REG { 169 | Uint16 all; 170 | struct SPIPRI_BITS bit; 171 | }; 172 | 173 | // 174 | // SPI Register File 175 | // 176 | struct SPI_REGS { 177 | union SPICCR_REG SPICCR; // Configuration register 178 | union SPICTL_REG SPICTL; // Operation control register 179 | union SPISTS_REG SPISTS; // Status register 180 | Uint16 rsvd1; // reserved 181 | Uint16 SPIBRR; // Baud Rate 182 | Uint16 rsvd2; // reserved 183 | Uint16 SPIRXEMU; // Emulation buffer 184 | Uint16 SPIRXBUF; // Serial input buffer 185 | Uint16 SPITXBUF; // Serial output buffer 186 | Uint16 SPIDAT; // Serial data 187 | union SPIFFTX_REG SPIFFTX; // FIFO transmit register 188 | union SPIFFRX_REG SPIFFRX; // FIFO recieve register 189 | union SPIFFCT_REG SPIFFCT; // FIFO control register 190 | Uint16 rsvd3[2]; // reserved 191 | union SPIPRI_REG SPIPRI; // FIFO Priority control 192 | }; 193 | 194 | // 195 | // SPI External References & Function Declarations 196 | // 197 | extern volatile struct SPI_REGS SpiaRegs; 198 | 199 | #ifdef __cplusplus 200 | } 201 | #endif /* extern "C" */ 202 | 203 | #endif // end of DSP2833x_SPI_H definition 204 | 205 | // 206 | // End of file 207 | // 208 | 209 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_XIntrupt.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:52:39 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_XIntrupt.h 6 | // 7 | // TITLE: DSP2833x Device External Interrupt Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_XINTRUPT_H 46 | #define DSP2833x_XINTRUPT_H 47 | 48 | 49 | #ifdef __cplusplus 50 | extern "C" { 51 | #endif 52 | 53 | struct XINTCR_BITS { 54 | Uint16 ENABLE:1; // 0 enable/disable 55 | Uint16 rsvd1:1; // 1 reserved 56 | Uint16 POLARITY:2; // 3:2 pos/neg, both triggered 57 | Uint16 rsvd2:12; //15:4 reserved 58 | }; 59 | 60 | union XINTCR_REG { 61 | Uint16 all; 62 | struct XINTCR_BITS bit; 63 | }; 64 | 65 | struct XNMICR_BITS { 66 | Uint16 ENABLE:1; // 0 enable/disable 67 | Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 68 | Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered 69 | Uint16 rsvd2:12; // 15:4 reserved 70 | }; 71 | 72 | union XNMICR_REG { 73 | Uint16 all; 74 | struct XNMICR_BITS bit; 75 | }; 76 | 77 | // 78 | // External Interrupt Register File 79 | // 80 | struct XINTRUPT_REGS { 81 | union XINTCR_REG XINT1CR; 82 | union XINTCR_REG XINT2CR; 83 | union XINTCR_REG XINT3CR; 84 | union XINTCR_REG XINT4CR; 85 | union XINTCR_REG XINT5CR; 86 | union XINTCR_REG XINT6CR; 87 | union XINTCR_REG XINT7CR; 88 | union XNMICR_REG XNMICR; 89 | Uint16 XINT1CTR; 90 | Uint16 XINT2CTR; 91 | Uint16 rsvd[5]; 92 | Uint16 XNMICTR; 93 | }; 94 | 95 | // 96 | // External Interrupt References & Function Declarations 97 | // 98 | extern volatile struct XINTRUPT_REGS XIntruptRegs; 99 | 100 | #ifdef __cplusplus 101 | } 102 | #endif /* extern "C" */ 103 | 104 | #endif // end of DSP2833x_XINTF_H definition 105 | 106 | // 107 | // End of file 108 | // 109 | 110 | -------------------------------------------------------------------------------- /DSP2833x_BSP/include/DSP2833x_Xintf.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: July 27, 2009 13:57:25 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Xintf.h 6 | // 7 | // TITLE: DSP2833x Device External Interface Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | #ifndef DSP2833x_XINTF_H 46 | #define DSP2833x_XINTF_H 47 | 48 | #ifdef __cplusplus 49 | extern "C" { 50 | #endif 51 | 52 | // 53 | // XINTF timing register bit definitions 54 | // 55 | struct XTIMING_BITS { // bits description 56 | Uint16 XWRTRAIL:2; // 1:0 Write access trail timing 57 | Uint16 XWRACTIVE:3; // 4:2 Write access active timing 58 | Uint16 XWRLEAD:2; // 6:5 Write access lead timing 59 | Uint16 XRDTRAIL:2; // 8:7 Read access trail timing 60 | Uint16 XRDACTIVE:3; // 11:9 Read access active timing 61 | Uint16 XRDLEAD:2; // 13:12 Read access lead timing 62 | Uint16 USEREADY:1; // 14 Extend access using HW waitstates 63 | Uint16 READYMODE:1; // 15 Ready mode 64 | Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b 65 | Uint16 rsvd1:4; // 21:18 reserved 66 | Uint16 X2TIMING:1; // 22 Double lead/active/trail timing 67 | Uint16 rsvd3:9; // 31:23 reserved 68 | }; 69 | 70 | union XTIMING_REG { 71 | Uint32 all; 72 | struct XTIMING_BITS bit; 73 | }; 74 | 75 | // 76 | // XINTF control register bit definitions 77 | // 78 | struct XINTCNF2_BITS { // bits description 79 | Uint16 WRBUFF:2; // 1:0 Write buffer depth 80 | Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK 81 | Uint16 CLKOFF:1; // 3 Disable XCLKOUT 82 | Uint16 rsvd1:2; // 5:4 reserved 83 | Uint16 WLEVEL:2; // 7:6 Current level of the write buffer 84 | Uint16 rsvd2:1; // 8 reserved 85 | Uint16 HOLD:1; // 9 Hold enable/disable 86 | Uint16 HOLDS:1; // 10 Current state of HOLDn input 87 | Uint16 HOLDAS:1; // 11 Current state of HOLDAn output 88 | Uint16 rsvd3:4; // 15:12 reserved 89 | Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK 90 | Uint16 rsvd4:13; // 31:19 reserved 91 | }; 92 | 93 | union XINTCNF2_REG { 94 | Uint32 all; 95 | struct XINTCNF2_BITS bit; 96 | }; 97 | 98 | // 99 | // XINTF bank switching register bit definitions 100 | // 101 | struct XBANK_BITS { // bits description 102 | Uint16 BANK:3; // 2:0 Zone for which banking is enabled 103 | Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add 104 | Uint16 rsvd:10; // 15:6 reserved 105 | }; 106 | 107 | union XBANK_REG { 108 | Uint16 all; 109 | struct XBANK_BITS bit; 110 | }; 111 | 112 | struct XRESET_BITS { 113 | Uint16 XHARDRESET:1; 114 | Uint16 rsvd1:15; 115 | }; 116 | 117 | union XRESET_REG { 118 | Uint16 all; 119 | struct XRESET_BITS bit; 120 | }; 121 | 122 | // 123 | // XINTF Register File 124 | // 125 | struct XINTF_REGS { 126 | union XTIMING_REG XTIMING0; 127 | Uint32 rsvd1[5]; 128 | union XTIMING_REG XTIMING6; 129 | union XTIMING_REG XTIMING7; 130 | Uint32 rsvd2[2]; 131 | union XINTCNF2_REG XINTCNF2; 132 | Uint32 rsvd3; 133 | union XBANK_REG XBANK; 134 | Uint16 rsvd4; 135 | Uint16 XREVISION; 136 | Uint16 rsvd5[2]; 137 | union XRESET_REG XRESET; 138 | }; 139 | 140 | // 141 | // XINTF External References & Function Declarations 142 | // 143 | extern volatile struct XINTF_REGS XintfRegs; 144 | 145 | #ifdef __cplusplus 146 | } 147 | #endif /* extern "C" */ 148 | 149 | #endif // end of DSP2833x_XINTF_H definition 150 | 151 | // 152 | // End of File 153 | // 154 | 155 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_ADC_cal.asm: -------------------------------------------------------------------------------- 1 | ;; TI File $Revision: /main/1 $ 2 | ;; Checkin $Date: July 30, 2007 10:29:23 $ 3 | ;;########################################################################### 4 | ;; 5 | ;; FILE: ADC_cal.asm 6 | ;; 7 | ;; TITLE: 2833x Boot Rom ADC Cal routine. 8 | ;; 9 | ;; Functions: 10 | ;; 11 | ;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and 12 | ;; ADCOFFTRIM registers 13 | ;; Notes: 14 | ;; 15 | ;;########################################################################### 16 | ;; $TI Release: F2833x Support Library v2.01.00.00 $ 17 | ;; $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 18 | ;; $Copyright: 19 | ;// Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 20 | ;// 21 | ;// Redistribution and use in source and binary forms, with or without 22 | ;// modification, are permitted provided that the following conditions 23 | ;// are met: 24 | ;// 25 | ;// Redistributions of source code must retain the above copyright 26 | ;// notice, this list of conditions and the following disclaimer. 27 | ;// 28 | ;// Redistributions in binary form must reproduce the above copyright 29 | ;// notice, this list of conditions and the following disclaimer in the 30 | ;// documentation and/or other materials provided with the 31 | ;// distribution. 32 | ;// 33 | ;// Neither the name of Texas Instruments Incorporated nor the names of 34 | ;// its contributors may be used to endorse or promote products derived 35 | ;// from this software without specific prior written permission. 36 | ;// 37 | ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 38 | ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 39 | ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 40 | ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 41 | ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 | ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 43 | ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 44 | ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 45 | ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 46 | ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 | ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 | ;// $ 49 | ;;########################################################################### 50 | 51 | .def _ADC_cal 52 | .asg "0x711C", ADCREFSEL_LOC 53 | 54 | ;----------------------------------------------- 55 | ; _ADC_cal 56 | ;----------------------------------------------- 57 | ;----------------------------------------------- 58 | ; This is the ADC cal routine.This routine is programmed into 59 | ; reserved memory by the factory. 0xAAAA and 0xBBBB are place- 60 | ; holders for calibration data. 61 | ;The actual values programmed by TI are device specific. 62 | ; 63 | ; This function assumes that the clocks have been 64 | ; enabled to the ADC module. 65 | ;----------------------------------------------- 66 | 67 | .sect ".adc_cal" 68 | 69 | _ADC_cal 70 | MOVW DP, #ADCREFSEL_LOC >> 6 71 | MOV @28, #0xAAAA ; actual value may not be 0xAAAA 72 | MOV @29, #0xBBBB ; actual value may not be 0xBBBB 73 | LRETR 74 | ;eof ---------- 75 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_CSMPasswords.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/3 $ 2 | ;// Checkin $Date: June 26, 2007 16:41:07 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_CSMPasswords.asm 6 | ;// 7 | ;// TITLE: DSP2833x Code Security Module Passwords. 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// This file is used to specify password values to 12 | ;// program into the CSM password locations in Flash 13 | ;// at 0x33FFF8 - 0x33FFFF. 14 | ;// 15 | ;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are 16 | ;// all programmed to 0x0000 17 | ;// 18 | ;//########################################################################### 19 | ;// $TI Release: F2833x Support Library v2.01.00.00 $ 20 | ;// $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 21 | ;// $Copyright: 22 | ;// Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 23 | ;// 24 | ;// Redistribution and use in source and binary forms, with or without 25 | ;// modification, are permitted provided that the following conditions 26 | ;// are met: 27 | ;// 28 | ;// Redistributions of source code must retain the above copyright 29 | ;// notice, this list of conditions and the following disclaimer. 30 | ;// 31 | ;// Redistributions in binary form must reproduce the above copyright 32 | ;// notice, this list of conditions and the following disclaimer in the 33 | ;// documentation and/or other materials provided with the 34 | ;// distribution. 35 | ;// 36 | ;// Neither the name of Texas Instruments Incorporated nor the names of 37 | ;// its contributors may be used to endorse or promote products derived 38 | ;// from this software without specific prior written permission. 39 | ;// 40 | ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 | ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 | ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 | ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 | ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 | ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 | ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 | ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 | ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 | ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 | ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 | ;// $ 52 | ;//########################################################################### 53 | 54 | ; The "csmpasswords" section contains the actual CSM passwords that will be 55 | ; linked and programmed into to the CSM password locations (PWL) in flash. 56 | ; These passwords must be known in order to unlock the CSM module. 57 | ; All 0xFFFF's (erased) is the default value for the password locations (PWL). 58 | 59 | ; It is recommended that all passwords be left as 0xFFFF during code 60 | ; development. Passwords of 0xFFFF do not activate code security and dummy 61 | ; reads of the CSM PWL registers is all that is required to unlock the CSM. 62 | ; When code development is complete, modify the passwords to activate the 63 | ; code security module. 64 | 65 | .sect "csmpasswds" 66 | 67 | .int 0xFFFF ;PWL0 (LSW of 128-bit password) 68 | .int 0xFFFF ;PWL1 69 | .int 0xFFFF ;PWL2 70 | .int 0xFFFF ;PWL3 71 | .int 0xFFFF ;PWL4 72 | .int 0xFFFF ;PWL5 73 | .int 0xFFFF ;PWL6 74 | .int 0xFFFF ;PWL7 (MSW of 128-bit password) 75 | 76 | ;---------------------------------------------------------------------- 77 | 78 | ; For code security operation, all addresses between 0x33FF80 and 79 | ; 0X33fff5 cannot be used as program code or data. These locations 80 | ; must be programmed to 0x0000 when the code security password locations 81 | ; (PWL) are programmed. If security is not a concern, then these addresses 82 | ; can be used for code or data. 83 | 84 | ; The section "csm_rsvd" can be used to program these locations to 0x0000. 85 | 86 | .sect "csm_rsvd" 87 | .loop (33FFF5h - 33FF80h + 1) 88 | .int 0x0000 89 | .endloop 90 | 91 | ;//=========================================================================== 92 | ;// End of file. 93 | ;//=========================================================================== 94 | 95 | 96 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_CodeStartBranch.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:45:55 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_CodeStartBranch.asm 6 | ;// 7 | ;// TITLE: Branch for redirecting code execution after boot. 8 | ;// 9 | ;// For these examples, code_start is the first code that is executed after 10 | ;// exiting the boot ROM code. 11 | ;// 12 | ;// The codestart section in the linker cmd file is used to physically place 13 | ;// this code at the correct memory location. This section should be placed 14 | ;// at the location the BOOT ROM will re-direct the code to. For example, 15 | ;// for boot to FLASH this code will be located at 0x3f7ff6. 16 | ;// 17 | ;// In addition, the example DSP2833x projects are setup such that the codegen 18 | ;// entry point is also set to the code_start label. This is done by linker 19 | ;// option -e in the project build options. When the debugger loads the code, 20 | ;// it will automatically set the PC to the "entry point" address indicated by 21 | ;// the -e linker option. In this case the debugger is simply assigning the PC, 22 | ;// it is not the same as a full reset of the device. 23 | ;// 24 | ;// The compiler may warn that the entry point for the project is other then 25 | ;// _c_init00. _c_init00 is the C environment setup and is run before 26 | ;// main() is entered. The code_start code will re-direct the execution 27 | ;// to _c_init00 and thus there is no worry and this warning can be ignored. 28 | ;// 29 | ;//########################################################################### 30 | ;// $TI Release: F2833x Support Library v2.01.00.00 $ 31 | ;// $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 32 | ;// $Copyright: 33 | ;// Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 34 | ;// 35 | ;// Redistribution and use in source and binary forms, with or without 36 | ;// modification, are permitted provided that the following conditions 37 | ;// are met: 38 | ;// 39 | ;// Redistributions of source code must retain the above copyright 40 | ;// notice, this list of conditions and the following disclaimer. 41 | ;// 42 | ;// Redistributions in binary form must reproduce the above copyright 43 | ;// notice, this list of conditions and the following disclaimer in the 44 | ;// documentation and/or other materials provided with the 45 | ;// distribution. 46 | ;// 47 | ;// Neither the name of Texas Instruments Incorporated nor the names of 48 | ;// its contributors may be used to endorse or promote products derived 49 | ;// from this software without specific prior written permission. 50 | ;// 51 | ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 | ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 | ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 | ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 | ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 | ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 | ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 | ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 | ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 | ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 | ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 | ;// $ 63 | ;//########################################################################### 64 | 65 | 66 | *********************************************************************** 67 | 68 | WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 69 | 70 | .ref _c_int00 71 | .global code_start 72 | 73 | *********************************************************************** 74 | * Function: codestart section 75 | * 76 | * Description: Branch to code starting point 77 | *********************************************************************** 78 | 79 | .sect "codestart" 80 | 81 | code_start: 82 | .if WD_DISABLE == 1 83 | LB wd_disable ;Branch to watchdog disable code 84 | .else 85 | LB _c_int00 ;Branch to start of boot.asm in RTS library 86 | .endif 87 | 88 | ;end codestart section 89 | 90 | 91 | *********************************************************************** 92 | * Function: wd_disable 93 | * 94 | * Description: Disables the watchdog timer 95 | *********************************************************************** 96 | .if WD_DISABLE == 1 97 | 98 | .text 99 | wd_disable: 100 | SETC OBJMODE ;Set OBJMODE for 28x object code 101 | EALLOW ;Enable EALLOW protected register access 102 | MOVZ DP, #7029h>>6 ;Set data page for WDCR register 103 | MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD 104 | EDIS ;Disable EALLOW protected register access 105 | LB _c_int00 ;Branch to start of boot.asm in RTS library 106 | 107 | .endif 108 | 109 | ;end wd_disable 110 | 111 | 112 | 113 | .end 114 | 115 | ;//=========================================================================== 116 | ;// End of file. 117 | ;//=========================================================================== 118 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_CpuTimers.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: July 9, 2009 10:51:59 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_CpuTimers.c 6 | // 7 | // TITLE: CPU 32-bit Timers Initialization & Support Functions. 8 | // 9 | // NOTES: CpuTimer2 is reserved for use with DSP BIOS and 10 | // other realtime operating systems. 11 | // 12 | // Do not use these this timer in your application if you ever plan 13 | // on integrating DSP-BIOS or another realtime OS. 14 | // 15 | //########################################################################### 16 | // $TI Release: F2833x Support Library v2.01.00.00 $ 17 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 18 | // $Copyright: 19 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 20 | // 21 | // Redistribution and use in source and binary forms, with or without 22 | // modification, are permitted provided that the following conditions 23 | // are met: 24 | // 25 | // Redistributions of source code must retain the above copyright 26 | // notice, this list of conditions and the following disclaimer. 27 | // 28 | // Redistributions in binary form must reproduce the above copyright 29 | // notice, this list of conditions and the following disclaimer in the 30 | // documentation and/or other materials provided with the 31 | // distribution. 32 | // 33 | // Neither the name of Texas Instruments Incorporated nor the names of 34 | // its contributors may be used to endorse or promote products derived 35 | // from this software without specific prior written permission. 36 | // 37 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 38 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 39 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 40 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 41 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 43 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 44 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 45 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 46 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 | // $ 49 | //########################################################################### 50 | 51 | // 52 | // Included Files 53 | // 54 | #include "DSP2833x_Device.h" // Headerfile Include File 55 | #include "DSP2833x_Examples.h" // Examples Include File 56 | 57 | // 58 | // Defines 59 | // 60 | struct CPUTIMER_VARS CpuTimer0; 61 | 62 | // 63 | // When using DSP BIOS & other RTOS, comment out CPU Timer 2 code. 64 | // 65 | struct CPUTIMER_VARS CpuTimer1; 66 | struct CPUTIMER_VARS CpuTimer2; 67 | 68 | // 69 | // InitCpuTimers - This function initializes all three CPU timers to a known 70 | // state. 71 | // 72 | void 73 | InitCpuTimers(void) 74 | { 75 | // 76 | // CPU Timer 0 - Initialize address pointers to respective timer registers 77 | // 78 | CpuTimer0.RegsAddr = &CpuTimer0Regs; 79 | 80 | // 81 | // Initialize timer period to maximum 82 | // 83 | CpuTimer0Regs.PRD.all = 0xFFFFFFFF; 84 | 85 | // 86 | // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) 87 | // 88 | CpuTimer0Regs.TPR.all = 0; 89 | CpuTimer0Regs.TPRH.all = 0; 90 | 91 | // 92 | // Make sure timer is stopped 93 | // 94 | CpuTimer0Regs.TCR.bit.TSS = 1; 95 | 96 | // 97 | // Reload all counter register with period value 98 | // 99 | CpuTimer0Regs.TCR.bit.TRB = 1; 100 | 101 | // 102 | // Reset interrupt counters 103 | // 104 | CpuTimer0.InterruptCount = 0; 105 | 106 | // 107 | // CpuTimer2 is reserved for DSP BIOS & other RTOS 108 | // Do not use this timer if you ever plan on integrating 109 | // DSP-BIOS or another realtime OS. 110 | // 111 | 112 | // 113 | // Initialize address pointers to respective timer registers 114 | // 115 | CpuTimer1.RegsAddr = &CpuTimer1Regs; 116 | CpuTimer2.RegsAddr = &CpuTimer2Regs; 117 | 118 | // 119 | // Initialize timer period to maximum 120 | // 121 | CpuTimer1Regs.PRD.all = 0xFFFFFFFF; 122 | CpuTimer2Regs.PRD.all = 0xFFFFFFFF; 123 | 124 | // 125 | // Make sure timers are stopped 126 | // 127 | CpuTimer1Regs.TCR.bit.TSS = 1; 128 | CpuTimer2Regs.TCR.bit.TSS = 1; 129 | 130 | // 131 | // Reload all counter register with period value 132 | // 133 | CpuTimer1Regs.TCR.bit.TRB = 1; 134 | CpuTimer2Regs.TCR.bit.TRB = 1; 135 | 136 | // 137 | // Reset interrupt counters 138 | // 139 | CpuTimer1.InterruptCount = 0; 140 | CpuTimer2.InterruptCount = 0; 141 | } 142 | 143 | // 144 | // ConfigCpuTimer - This function initializes the selected timer to the period 145 | // specified by the "Freq" and "Period" parameters. The "Freq" is entered as 146 | // "MHz" and the period in "uSeconds". The timer is held in the stopped state 147 | // after configuration. 148 | // 149 | void 150 | ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) 151 | { 152 | Uint32 temp; 153 | 154 | // 155 | // Initialize timer period 156 | // 157 | Timer->CPUFreqInMHz = Freq; 158 | Timer->PeriodInUSec = Period; 159 | temp = (long) (Freq * Period); 160 | Timer->RegsAddr->PRD.all = temp; 161 | 162 | // 163 | // Set pre-scale counter to divide by 1 (SYSCLKOUT) 164 | // 165 | Timer->RegsAddr->TPR.all = 0; 166 | Timer->RegsAddr->TPRH.all = 0; 167 | 168 | // 169 | // Initialize timer control register 170 | // 171 | 172 | // 173 | // 1 = Stop timer, 0 = Start/Restart Timer 174 | // 175 | Timer->RegsAddr->TCR.bit.TSS = 1; 176 | 177 | Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer 178 | Timer->RegsAddr->TCR.bit.SOFT = 1; 179 | Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run 180 | 181 | // 182 | // 0 = Disable/ 1 = Enable Timer Interrupt 183 | // 184 | Timer->RegsAddr->TCR.bit.TIE = 1; 185 | 186 | // 187 | // Reset interrupt counter 188 | // 189 | Timer->InterruptCount = 0; 190 | } 191 | 192 | // 193 | // End of File 194 | // 195 | 196 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_DBGIER.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:46:03 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_DBGIER.asm 6 | ;// 7 | ;// TITLE: Set the DBGIER register 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// Function to set the DBGIER register (for realtime emulation). 12 | ;// Function Prototype: void SetDBGIER(Uint16) 13 | ;// Useage: SetDBGIER(value); 14 | ;// Input Parameters: Uint16 value = value to put in DBGIER register. 15 | ;// Return Value: none 16 | ;// 17 | ;//########################################################################### 18 | ;// $TI Release: F2833x Support Library v2.01.00.00 $ 19 | ;// $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 20 | ;// $Copyright: 21 | ;// Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 22 | ;// 23 | ;// Redistribution and use in source and binary forms, with or without 24 | ;// modification, are permitted provided that the following conditions 25 | ;// are met: 26 | ;// 27 | ;// Redistributions of source code must retain the above copyright 28 | ;// notice, this list of conditions and the following disclaimer. 29 | ;// 30 | ;// Redistributions in binary form must reproduce the above copyright 31 | ;// notice, this list of conditions and the following disclaimer in the 32 | ;// documentation and/or other materials provided with the 33 | ;// distribution. 34 | ;// 35 | ;// Neither the name of Texas Instruments Incorporated nor the names of 36 | ;// its contributors may be used to endorse or promote products derived 37 | ;// from this software without specific prior written permission. 38 | ;// 39 | ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 40 | ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 41 | ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 42 | ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 43 | ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 44 | ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 45 | ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 46 | ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 47 | ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 48 | ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 49 | ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 50 | ;// $ 51 | ;//########################################################################### 52 | .global _SetDBGIER 53 | .text 54 | 55 | _SetDBGIER: 56 | MOV *SP++,AL 57 | POP DBGIER 58 | LRETR 59 | 60 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_DisInt.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:46:09 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_DisInt.asm 6 | ;// 7 | ;// TITLE: Disable and Restore INTM and DBGM 8 | ;// 9 | ;// Function Prototypes: 10 | ;// 11 | ;// Uint16 DSP28x_DisableInt(); 12 | ;// and void DSP28x_RestoreInt(Uint16 Stat0); 13 | ;// 14 | ;// Usage: 15 | ;// 16 | ;// DSP28x_DisableInt() sets both the INTM and DBGM 17 | ;// bits to disable maskable interrupts. Before doing 18 | ;// this, the current value of ST1 is stored on the stack 19 | ;// so that the values can be restored later. The value 20 | ;// of ST1 before the masks are set is returned to the 21 | ;// user in AL. This is then used to restore their state 22 | ;// via the DSP28x_RestoreInt(Uint16 ST1) function. 23 | ;// 24 | ;// Example 25 | ;// 26 | ;// Uint16 StatusReg1 27 | ;// StatusReg1 = DSP28x_DisableInt(); 28 | ;// 29 | ;// ... May also want to disable INTM here 30 | ;// 31 | ;// ... code here 32 | ;// 33 | ;// DSP28x_RestoreInt(StatusReg1); 34 | ;// 35 | ;// ... Restore INTM enable 36 | ;// 37 | ;//########################################################################### 38 | ;// $TI Release: F2833x Support Library v2.01.00.00 $ 39 | ;// $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 40 | ;// $Copyright: 41 | ;// Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 42 | ;// 43 | ;// Redistribution and use in source and binary forms, with or without 44 | ;// modification, are permitted provided that the following conditions 45 | ;// are met: 46 | ;// 47 | ;// Redistributions of source code must retain the above copyright 48 | ;// notice, this list of conditions and the following disclaimer. 49 | ;// 50 | ;// Redistributions in binary form must reproduce the above copyright 51 | ;// notice, this list of conditions and the following disclaimer in the 52 | ;// documentation and/or other materials provided with the 53 | ;// distribution. 54 | ;// 55 | ;// Neither the name of Texas Instruments Incorporated nor the names of 56 | ;// its contributors may be used to endorse or promote products derived 57 | ;// from this software without specific prior written permission. 58 | ;// 59 | ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 60 | ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 61 | ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 62 | ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 63 | ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 64 | ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 65 | ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 66 | ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 67 | ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 68 | ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 69 | ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 70 | ;// $ 71 | ;//########################################################################### 72 | 73 | 74 | 75 | 76 | .def _DSP28x_DisableInt 77 | .def _DSP28x_RestoreInt 78 | 79 | 80 | _DSP28x_DisableInt: 81 | PUSH ST1 82 | SETC INTM,DBGM 83 | MOV AL, *--SP 84 | LRETR 85 | 86 | _DSP28x_RestoreInt: 87 | MOV *SP++, AL 88 | POP ST1 89 | LRETR 90 | 91 | 92 | ;//=========================================================================== 93 | ;// End of file. 94 | ;//=========================================================================== 95 | 96 | 97 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_Gpio.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:46:25 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_Gpio.c 6 | // 7 | // TITLE: DSP2833x General Purpose I/O Initialization & Support Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | // 46 | // Included Files 47 | // 48 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 49 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 50 | 51 | // 52 | // InitGpio - This function initializes the Gpio to a known (default) state. 53 | // 54 | // For more details on configuring GPIO's as peripheral functions, 55 | // refer to the individual peripheral examples and/or GPIO setup example. 56 | // 57 | void 58 | InitGpio(void) 59 | { 60 | EALLOW; 61 | 62 | // 63 | // Each GPIO pin can be: 64 | // a) a GPIO input/output 65 | // b) peripheral function 1 66 | // c) peripheral function 2 67 | // d) peripheral function 3 68 | // By default, all are GPIO Inputs 69 | // 70 | GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15 71 | GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31 72 | GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39 73 | GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63 74 | GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79 75 | GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95 76 | 77 | GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs 78 | GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs 79 | GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs 80 | 81 | // 82 | // Each input can have different qualification 83 | // a) input synchronized to SYSCLKOUT 84 | // b) input qualified by a sampling window 85 | // c) input sent asynchronously (valid for peripheral inputs only) 86 | // 87 | GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT 88 | GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT 89 | GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT 90 | GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT 91 | 92 | // 93 | // Pull-ups can be enabled or disabled 94 | // 95 | GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31 96 | GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63 97 | GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79 98 | //GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31 99 | //GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34 100 | //GpioCtrlRegs.GPCPUD.all = 0xFFFF; // Pullup's disabled GPIO64-GPIO79 101 | 102 | EDIS; 103 | } 104 | 105 | // 106 | // End of file 107 | // 108 | 109 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_MemCopy.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:46:33 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_MemCopy.c 6 | // 7 | // TITLE: Memory Copy Utility 8 | // 9 | // ASSUMPTIONS: 10 | // 11 | // DESCRIPTION: 12 | // 13 | // This function will copy the specified memory contents from 14 | // one location to another. 15 | // 16 | // Uint16 *SourceAddr Pointer to the first word to be moved 17 | // SourceAddr < SourceEndAddr 18 | // Uint16* SourceEndAddr Pointer to the last word to be moved 19 | // Uint16* DestAddr Pointer to the first destination word 20 | // 21 | // No checks are made for invalid memory locations or that the 22 | // end address is > then the first start address. 23 | // 24 | //########################################################################### 25 | // $TI Release: F2833x Support Library v2.01.00.00 $ 26 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 27 | // $Copyright: 28 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 29 | // 30 | // Redistribution and use in source and binary forms, with or without 31 | // modification, are permitted provided that the following conditions 32 | // are met: 33 | // 34 | // Redistributions of source code must retain the above copyright 35 | // notice, this list of conditions and the following disclaimer. 36 | // 37 | // Redistributions in binary form must reproduce the above copyright 38 | // notice, this list of conditions and the following disclaimer in the 39 | // documentation and/or other materials provided with the 40 | // distribution. 41 | // 42 | // Neither the name of Texas Instruments Incorporated nor the names of 43 | // its contributors may be used to endorse or promote products derived 44 | // from this software without specific prior written permission. 45 | // 46 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 | // $ 58 | //########################################################################### 59 | 60 | // 61 | // Included Files 62 | // 63 | #include "DSP2833x_Device.h" 64 | 65 | // 66 | // MemCopy - 67 | // 68 | void 69 | MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr) 70 | { 71 | while(SourceAddr < SourceEndAddr) 72 | { 73 | *DestAddr++ = *SourceAddr++; 74 | } 75 | return; 76 | } 77 | 78 | // 79 | // End of file 80 | // 81 | 82 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_PieCtrl.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:46:35 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_PieCtrl.c 6 | // 7 | // TITLE: DSP2833x Device PIE Control Register Initialization Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | // 46 | // Included Files 47 | // 48 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 49 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 50 | 51 | // 52 | // InitPieCtrl - This function initializes the PIE control registers to a known 53 | // state. 54 | // 55 | void 56 | InitPieCtrl(void) 57 | { 58 | // 59 | // Disable Interrupts at the CPU level 60 | // 61 | DINT; 62 | 63 | // 64 | // Disable the PIE 65 | // 66 | PieCtrlRegs.PIECTRL.bit.ENPIE = 0; 67 | 68 | // 69 | // Clear all PIEIER registers 70 | // 71 | PieCtrlRegs.PIEIER1.all = 0; 72 | PieCtrlRegs.PIEIER2.all = 0; 73 | PieCtrlRegs.PIEIER3.all = 0; 74 | PieCtrlRegs.PIEIER4.all = 0; 75 | PieCtrlRegs.PIEIER5.all = 0; 76 | PieCtrlRegs.PIEIER6.all = 0; 77 | PieCtrlRegs.PIEIER7.all = 0; 78 | PieCtrlRegs.PIEIER8.all = 0; 79 | PieCtrlRegs.PIEIER9.all = 0; 80 | PieCtrlRegs.PIEIER10.all = 0; 81 | PieCtrlRegs.PIEIER11.all = 0; 82 | PieCtrlRegs.PIEIER12.all = 0; 83 | 84 | // 85 | // Clear all PIEIFR registers 86 | // 87 | PieCtrlRegs.PIEIFR1.all = 0; 88 | PieCtrlRegs.PIEIFR2.all = 0; 89 | PieCtrlRegs.PIEIFR3.all = 0; 90 | PieCtrlRegs.PIEIFR4.all = 0; 91 | PieCtrlRegs.PIEIFR5.all = 0; 92 | PieCtrlRegs.PIEIFR6.all = 0; 93 | PieCtrlRegs.PIEIFR7.all = 0; 94 | PieCtrlRegs.PIEIFR8.all = 0; 95 | PieCtrlRegs.PIEIFR9.all = 0; 96 | PieCtrlRegs.PIEIFR10.all = 0; 97 | PieCtrlRegs.PIEIFR11.all = 0; 98 | PieCtrlRegs.PIEIFR12.all = 0; 99 | } 100 | 101 | // 102 | // EnableInterrupts - This function enables the PIE module and CPU interrupts 103 | // 104 | void 105 | EnableInterrupts() 106 | { 107 | // 108 | // Enable the PIE 109 | // 110 | PieCtrlRegs.PIECTRL.bit.ENPIE = 1; 111 | 112 | // 113 | // Enables PIE to drive a pulse into the CPU 114 | // 115 | PieCtrlRegs.PIEACK.all = 0xFFFF; 116 | 117 | // 118 | // Enable Interrupts at the CPU level 119 | // 120 | EINT; 121 | } 122 | 123 | // 124 | // End of file 125 | // 126 | 127 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_PieVect.c: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:46:38 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_PieVect.c 6 | // 7 | // TITLE: DSP2833x Devices PIE Vector Table Initialization Functions. 8 | // 9 | //########################################################################### 10 | // $TI Release: F2833x Support Library v2.01.00.00 $ 11 | // $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 12 | // $Copyright: 13 | // Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 14 | // 15 | // Redistribution and use in source and binary forms, with or without 16 | // modification, are permitted provided that the following conditions 17 | // are met: 18 | // 19 | // Redistributions of source code must retain the above copyright 20 | // notice, this list of conditions and the following disclaimer. 21 | // 22 | // Redistributions in binary form must reproduce the above copyright 23 | // notice, this list of conditions and the following disclaimer in the 24 | // documentation and/or other materials provided with the 25 | // distribution. 26 | // 27 | // Neither the name of Texas Instruments Incorporated nor the names of 28 | // its contributors may be used to endorse or promote products derived 29 | // from this software without specific prior written permission. 30 | // 31 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | // $ 43 | //########################################################################### 44 | 45 | // 46 | // Included Files 47 | // 48 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 49 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 50 | 51 | const struct PIE_VECT_TABLE PieVectTableInit = 52 | { 53 | PIE_RESERVED, // 0 Reserved space 54 | PIE_RESERVED, // 1 Reserved space 55 | PIE_RESERVED, // 2 Reserved space 56 | PIE_RESERVED, // 3 Reserved space 57 | PIE_RESERVED, // 4 Reserved space 58 | PIE_RESERVED, // 5 Reserved space 59 | PIE_RESERVED, // 6 Reserved space 60 | PIE_RESERVED, // 7 Reserved space 61 | PIE_RESERVED, // 8 Reserved space 62 | PIE_RESERVED, // 9 Reserved space 63 | PIE_RESERVED, // 10 Reserved space 64 | PIE_RESERVED, // 11 Reserved space 65 | PIE_RESERVED, // 12 Reserved space 66 | 67 | // 68 | // Non-Peripheral Interrupts 69 | // 70 | INT13_ISR, // XINT13 or CPU-Timer 1 71 | INT14_ISR, // CPU-Timer2 72 | DATALOG_ISR, // Datalogging interrupt 73 | RTOSINT_ISR, // RTOS interrupt 74 | EMUINT_ISR, // Emulation interrupt 75 | NMI_ISR, // Non-maskable interrupt 76 | ILLEGAL_ISR, // Illegal operation TRAP 77 | USER1_ISR, // User Defined trap 1 78 | USER2_ISR, // User Defined trap 2 79 | USER3_ISR, // User Defined trap 3 80 | USER4_ISR, // User Defined trap 4 81 | USER5_ISR, // User Defined trap 5 82 | USER6_ISR, // User Defined trap 6 83 | USER7_ISR, // User Defined trap 7 84 | USER8_ISR, // User Defined trap 8 85 | USER9_ISR, // User Defined trap 9 86 | USER10_ISR, // User Defined trap 10 87 | USER11_ISR, // User Defined trap 11 88 | USER12_ISR, // User Defined trap 12 89 | 90 | // 91 | // Group 1 PIE Vectors 92 | // 93 | SEQ1INT_ISR, // 1.1 ADC 94 | SEQ2INT_ISR, // 1.2 ADC 95 | rsvd_ISR, // 1.3 96 | XINT1_ISR, // 1.4 97 | XINT2_ISR, // 1.5 98 | ADCINT_ISR, // 1.6 ADC 99 | TINT0_ISR, // 1.7 Timer 0 100 | WAKEINT_ISR, // 1.8 WD, Low Power 101 | 102 | // 103 | // Group 2 PIE Vectors 104 | // 105 | EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone 106 | EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone 107 | EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone 108 | EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone 109 | EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone 110 | EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone 111 | rsvd_ISR, // 2.7 112 | rsvd_ISR, // 2.8 113 | 114 | // 115 | // Group 3 PIE Vectors 116 | // 117 | EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt 118 | EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt 119 | EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt 120 | EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt 121 | EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt 122 | EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt 123 | rsvd_ISR, // 3.7 124 | rsvd_ISR, // 3.8 125 | 126 | // 127 | // Group 4 PIE Vectors 128 | // 129 | ECAP1_INT_ISR, // 4.1 ECAP-1 130 | ECAP2_INT_ISR, // 4.2 ECAP-2 131 | ECAP3_INT_ISR, // 4.3 ECAP-3 132 | ECAP4_INT_ISR, // 4.4 ECAP-4 133 | ECAP5_INT_ISR, // 4.5 ECAP-5 134 | ECAP6_INT_ISR, // 4.6 ECAP-6 135 | rsvd_ISR, // 4.7 136 | rsvd_ISR, // 4.8 137 | 138 | // 139 | // Group 5 PIE Vectors 140 | // 141 | EQEP1_INT_ISR, // 5.1 EQEP-1 142 | EQEP2_INT_ISR, // 5.2 EQEP-2 143 | rsvd_ISR, // 5.3 144 | rsvd_ISR, // 5.4 145 | rsvd_ISR, // 5.5 146 | rsvd_ISR, // 5.6 147 | rsvd_ISR, // 5.7 148 | rsvd_ISR, // 5.8 149 | 150 | // 151 | // Group 6 PIE Vectors 152 | // 153 | SPIRXINTA_ISR, // 6.1 SPI-A 154 | SPITXINTA_ISR, // 6.2 SPI-A 155 | MRINTA_ISR, // 6.3 McBSP-A 156 | MXINTA_ISR, // 6.4 McBSP-A 157 | MRINTB_ISR, // 6.5 McBSP-B 158 | MXINTB_ISR, // 6.6 McBSP-B 159 | rsvd_ISR, // 6.7 160 | rsvd_ISR, // 6.8 161 | 162 | // 163 | // Group 7 PIE Vectors 164 | // 165 | DINTCH1_ISR, // 7.1 DMA channel 1 166 | DINTCH2_ISR, // 7.2 DMA channel 2 167 | DINTCH3_ISR, // 7.3 DMA channel 3 168 | DINTCH4_ISR, // 7.4 DMA channel 4 169 | DINTCH5_ISR, // 7.5 DMA channel 5 170 | DINTCH6_ISR, // 7.6 DMA channel 6 171 | rsvd_ISR, // 7.7 172 | rsvd_ISR, // 7.8 173 | 174 | // 175 | // Group 8 PIE Vectors 176 | // 177 | I2CINT1A_ISR, // 8.1 I2C 178 | I2CINT2A_ISR, // 8.2 I2C 179 | rsvd_ISR, // 8.3 180 | rsvd_ISR, // 8.4 181 | SCIRXINTC_ISR, // 8.5 SCI-C 182 | SCITXINTC_ISR, // 8.6 SCI-C 183 | rsvd_ISR, // 8.7 184 | rsvd_ISR, // 8.8 185 | 186 | // 187 | // Group 9 PIE Vectors 188 | // 189 | SCIRXINTA_ISR, // 9.1 SCI-A 190 | SCITXINTA_ISR, // 9.2 SCI-A 191 | SCIRXINTB_ISR, // 9.3 SCI-B 192 | SCITXINTB_ISR, // 9.4 SCI-B 193 | ECAN0INTA_ISR, // 9.5 eCAN-A 194 | ECAN1INTA_ISR, // 9.6 eCAN-A 195 | ECAN0INTB_ISR, // 9.7 eCAN-B 196 | ECAN1INTB_ISR, // 9.8 eCAN-B 197 | 198 | // 199 | // Group 10 PIE Vectors 200 | // 201 | rsvd_ISR, // 10.1 202 | rsvd_ISR, // 10.2 203 | rsvd_ISR, // 10.3 204 | rsvd_ISR, // 10.4 205 | rsvd_ISR, // 10.5 206 | rsvd_ISR, // 10.6 207 | rsvd_ISR, // 10.7 208 | rsvd_ISR, // 10.8 209 | 210 | // 211 | // Group 11 PIE Vectors 212 | // 213 | rsvd_ISR, // 11.1 214 | rsvd_ISR, // 11.2 215 | rsvd_ISR, // 11.3 216 | rsvd_ISR, // 11.4 217 | rsvd_ISR, // 11.5 218 | rsvd_ISR, // 11.6 219 | rsvd_ISR, // 11.7 220 | rsvd_ISR, // 11.8 221 | 222 | // 223 | // Group 12 PIE Vectors 224 | // 225 | XINT3_ISR, // 12.1 226 | XINT4_ISR, // 12.2 227 | XINT5_ISR, // 12.3 228 | XINT6_ISR, // 12.4 229 | XINT7_ISR, // 12.5 230 | rsvd_ISR, // 12.6 231 | LVF_ISR, // 12.7 232 | LUF_ISR, // 12.8 233 | }; 234 | 235 | // 236 | // InitPieVectTable - This function initializes the PIE vector table to a known 237 | // state. This function must be executed after boot time. 238 | // 239 | void 240 | InitPieVectTable(void) 241 | { 242 | int16 i; 243 | Uint32 *Source = (void *) &PieVectTableInit; 244 | volatile Uint32 *Dest = (void *) &PieVectTable; 245 | 246 | EALLOW; 247 | for(i=0; i < 128; i++) 248 | { 249 | *Dest++ = *Source++; 250 | } 251 | EDIS; 252 | 253 | // 254 | // Enable the PIE Vector Table 255 | // 256 | PieCtrlRegs.PIECTRL.bit.ENPIE = 1; 257 | } 258 | 259 | // 260 | // End of file 261 | // 262 | 263 | -------------------------------------------------------------------------------- /DSP2833x_BSP/source/DSP2833x_usDelay.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/4 $ 2 | ;// Checkin $Date: July 30, 2007 10:28:57 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_usDelay.asm 6 | ;// 7 | ;// TITLE: Simple delay function 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// This is a simple delay function that can be used to insert a specified 12 | ;// delay into code. 13 | ;// 14 | ;// This function is only accurate if executed from internal zero-waitstate 15 | ;// SARAM. If it is executed from waitstate memory then the delay will be 16 | ;// longer then specified. 17 | ;// 18 | ;// To use this function: 19 | ;// 20 | ;// 1 - update the CPU clock speed in the DSP2833x_Examples.h 21 | ;// file. For example: 22 | ;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed 23 | ;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed 24 | ;// 25 | ;// 2 - Call this function by using the DELAY_US(A) macro 26 | ;// that is defined in the DSP2833x_Examples.h file. This macro 27 | ;// will convert the number of microseconds specified 28 | ;// into a loop count for use with this function. 29 | ;// This count will be based on the CPU frequency you specify. 30 | ;// 31 | ;// 3 - For the most accurate delay 32 | ;// - Execute this function in 0 waitstate RAM. 33 | ;// - Disable interrupts before calling the function 34 | ;// If you do not disable interrupts, then think of 35 | ;// this as an "at least" delay function as the actual 36 | ;// delay may be longer. 37 | ;// 38 | ;// The C assembly call from the DELAY_US(time) macro will 39 | ;// look as follows: 40 | ;// 41 | ;// extern void Delay(long LoopCount); 42 | ;// 43 | ;// MOV AL,#LowLoopCount 44 | ;// MOV AH,#HighLoopCount 45 | ;// LCR _Delay 46 | ;// 47 | ;// Or as follows (if count is less then 16-bits): 48 | ;// 49 | ;// MOV ACC,#LoopCount 50 | ;// LCR _Delay 51 | ;// 52 | ;// 53 | ;//########################################################################### 54 | ;// $TI Release: F2833x Support Library v2.01.00.00 $ 55 | ;// $Release Date: Sun Oct 4 16:07:01 IST 2020 $ 56 | ;// $Copyright: 57 | ;// Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/ 58 | ;// 59 | ;// Redistribution and use in source and binary forms, with or without 60 | ;// modification, are permitted provided that the following conditions 61 | ;// are met: 62 | ;// 63 | ;// Redistributions of source code must retain the above copyright 64 | ;// notice, this list of conditions and the following disclaimer. 65 | ;// 66 | ;// Redistributions in binary form must reproduce the above copyright 67 | ;// notice, this list of conditions and the following disclaimer in the 68 | ;// documentation and/or other materials provided with the 69 | ;// distribution. 70 | ;// 71 | ;// Neither the name of Texas Instruments Incorporated nor the names of 72 | ;// its contributors may be used to endorse or promote products derived 73 | ;// from this software without specific prior written permission. 74 | ;// 75 | ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 76 | ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 77 | ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 78 | ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 79 | ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 | ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 81 | ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 82 | ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 83 | ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 84 | ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 85 | ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 | ;// $ 87 | ;//########################################################################### 88 | 89 | .def _DSP28x_usDelay 90 | .sect "ramfuncs" 91 | 92 | .global __DSP28x_usDelay 93 | _DSP28x_usDelay: 94 | SUB ACC,#1 95 | BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 96 | LRETR 97 | 98 | ;There is a 9/10 cycle overhead and each loop 99 | ;takes five cycles. The LoopCount is given by 100 | ;the following formula: 101 | ; DELAY_CPU_CYCLES = 9 + 5*LoopCount 102 | ; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 103 | ; The macro DELAY_US(A) performs this calculation for you 104 | ; 105 | ;//=========================================================================== 106 | ;// End of file. 107 | ;//=========================================================================== 108 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ucOSii_in_DSP28335 2 | port the embeded real time OS uc/OS ii to the TI DSP28335 3 | -------------------------------------------------------------------------------- /clean.bat: -------------------------------------------------------------------------------- 1 | DEL /S /Q .\Debug\*.* 2 | RD /S /Q Debug 3 | DEL /S /Q .\.settings\*.* 4 | RD /S /Q .settings -------------------------------------------------------------------------------- /clean.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | rm -rf Debug 3 | rm -rf .settings 4 | -------------------------------------------------------------------------------- /docs/NNP项目用比例阀.assets/image-20210128135331834.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RanFang66/ucOSii_in_DSP28335/df9a1a31f72235402295e755e2eb0a9be9eb3e62/docs/NNP项目用比例阀.assets/image-20210128135331834.png -------------------------------------------------------------------------------- /docs/NNP项目用比例阀.assets/image-20210128152025890.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RanFang66/ucOSii_in_DSP28335/df9a1a31f72235402295e755e2eb0a9be9eb3e62/docs/NNP项目用比例阀.assets/image-20210128152025890.png -------------------------------------------------------------------------------- /docs/NNP项目用比例阀.assets/image-20210205135205756.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RanFang66/ucOSii_in_DSP28335/df9a1a31f72235402295e755e2eb0a9be9eb3e62/docs/NNP项目用比例阀.assets/image-20210205135205756.png -------------------------------------------------------------------------------- /docs/NNP项目用比例阀.assets/image-20210205135230231.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RanFang66/ucOSii_in_DSP28335/df9a1a31f72235402295e755e2eb0a9be9eb3e62/docs/NNP项目用比例阀.assets/image-20210205135230231.png -------------------------------------------------------------------------------- /main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RanFang66/ucOSii_in_DSP28335/df9a1a31f72235402295e755e2eb0a9be9eb3e62/main.c -------------------------------------------------------------------------------- /targetConfigs/TMS320F28335.ccxml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /targetConfigs/readme.txt: -------------------------------------------------------------------------------- 1 | The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based 2 | on the device and connection settings specified in your project on the Properties > General page. 3 | 4 | Please note that in automatic target-configuration management, changes to the project's device and/or 5 | connection settings will either modify an existing or generate a new target-configuration file. Thus, 6 | if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, 7 | you may create your own target-configuration file for this project and manage it manually. You can 8 | always switch back to automatic target-configuration management by checking the "Manage the project's 9 | target-configuration automatically" checkbox on the project's Properties > General page. -------------------------------------------------------------------------------- /ucos-ii/config/app_cfg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * EXAMPLE CODE 4 | * 5 | * (c) Copyright 2015; Micrium, Inc.; Weston, FL 6 | * 7 | * All rights reserved. Protected by international copyright laws. 8 | * Knowledge of the source code may NOT be used to develop a similar product. 9 | * Please help us continue to provide the Embedded community with the finest 10 | * software available. Your honesty is greatly appreciated. 11 | ********************************************************************************************************* 12 | */ 13 | 14 | /* 15 | ********************************************************************************************************* 16 | * APPLICATION CONFIGURATION 17 | * 18 | * Delfino 28335 19 | * on the 20 | * TMDSDOCK28335 21 | * Experimenter Kit 22 | * 23 | * Filename : app_cfg.h 24 | * Version : V1.00 25 | ********************************************************************************************************* 26 | */ 27 | 28 | #ifndef APP_CFG_MODULE_PRESENT 29 | #define APP_CFG_MODULE_PRESENT 30 | 31 | 32 | /* 33 | ********************************************************************************************************* 34 | * ADDITIONAL uC/MODULE ENABLES 35 | ********************************************************************************************************* 36 | */ 37 | 38 | 39 | /* 40 | ********************************************************************************************************* 41 | * TASK PRIORITIES 42 | ********************************************************************************************************* 43 | */ 44 | 45 | #define APP_CFG_TASK_START_PRIO 2u 46 | #define APP_CFG_TASK_PEND_PRIO 3u 47 | #define APP_CFG_TASK_POST_PRIO 4u 48 | 49 | 50 | /* 51 | ********************************************************************************************************* 52 | * TASK IDs 53 | ********************************************************************************************************* 54 | */ 55 | 56 | #define APP_CFG_TASK_START_ID 0u 57 | #define APP_CFG_TASK_PEND_ID 1u 58 | #define APP_CFG_TASK_POST_ID 2u 59 | 60 | /* 61 | ********************************************************************************************************* 62 | * TASK STACK SIZES 63 | ********************************************************************************************************* 64 | */ 65 | 66 | #define APP_CFG_TASK_STK_SIZE 128u 67 | 68 | 69 | /* 70 | ********************************************************************************************************* 71 | * TRACE / DEBUG CONFIGURATION 72 | ********************************************************************************************************* 73 | */ 74 | #ifndef TRACE_LEVEL_OFF 75 | #define TRACE_LEVEL_OFF 0 76 | #endif 77 | 78 | #ifndef TRACE_LEVEL_INFO 79 | #define TRACE_LEVEL_INFO 1 80 | #endif 81 | 82 | #ifndef TRACE_LEVEL_DBG 83 | #define TRACE_LEVEL_DBG 2 84 | #endif 85 | 86 | 87 | #define APP_CFG_TRACE_LEVEL TRACE_LEVEL_OFF 88 | #define APP_CFG_TRACE printf 89 | 90 | #define BSP_CFG_TRACE_LEVEL TRACE_LEVEL_OFF 91 | #define BSP_CFG_TRACE printf 92 | 93 | #define APP_TRACE_INFO(x) ((APP_CFG_TRACE_LEVEL >= TRACE_LEVEL_INFO) ? (void)(APP_CFG_TRACE x) : (void)0) 94 | #define APP_TRACE_DBG(x) ((APP_CFG_TRACE_LEVEL >= TRACE_LEVEL_DBG) ? (void)(APP_CFG_TRACE x) : (void)0) 95 | 96 | #define BSP_TRACE_INFO(x) ((BSP_CFG_TRACE_LEVEL >= TRACE_LEVEL_INFO) ? (void)(BSP_CFG_TRACE x) : (void)0) 97 | #define BSP_TRACE_DBG(x) ((BSP_CFG_TRACE_LEVEL >= TRACE_LEVEL_DBG) ? (void)(BSP_CFG_TRACE x) : (void)0) 98 | 99 | #endif 100 | 101 | -------------------------------------------------------------------------------- /ucos-ii/config/lib_cfg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * EXAMPLE CODE 4 | * 5 | * This file is provided as an example on how to use Micrium products. 6 | * 7 | * Please feel free to use any application code labeled as 'EXAMPLE CODE' in 8 | * your application products. Example code may be used as is, in whole or in 9 | * part, or may be used as a reference only. This file can be modified as 10 | * required to meet the end-product requirements. 11 | * 12 | * Please help us continue to provide the Embedded community with the finest 13 | * software available. Your honesty is greatly appreciated. 14 | * 15 | * You can find information about uC/LIB by visiting doc.micrium.com. 16 | * You can contact us at: http://www.micrium.com 17 | ********************************************************************************************************* 18 | */ 19 | 20 | /* 21 | ********************************************************************************************************* 22 | * 23 | * CUSTOM LIBRARY CONFIGURATION FILE 24 | * 25 | * Delfino 28335 26 | * on the 27 | * TMDSDOCK28335 28 | * Experimenter Kit 29 | * 30 | * Filename : lib_cfg.h 31 | * Version : V1.37.02 32 | * Programmer(s) : JFT 33 | ********************************************************************************************************* 34 | */ 35 | 36 | 37 | /* 38 | ********************************************************************************************************* 39 | * MODULE 40 | ********************************************************************************************************* 41 | */ 42 | 43 | #ifndef LIB_CFG_MODULE_PRESENT 44 | #define LIB_CFG_MODULE_PRESENT 45 | 46 | 47 | /* 48 | ********************************************************************************************************* 49 | ********************************************************************************************************* 50 | * MEMORY LIBRARY CONFIGURATION 51 | ********************************************************************************************************* 52 | ********************************************************************************************************* 53 | */ 54 | 55 | /* 56 | ********************************************************************************************************* 57 | * MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION 58 | * 59 | * Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external 60 | * argument check feature : 61 | * 62 | * (a) When ENABLED, arguments received from any port interface provided by the developer 63 | * or application are checked/validated. 64 | * 65 | * (b) When DISABLED, NO arguments received from any port interface provided by the developer 66 | * or application are checked/validated. 67 | ********************************************************************************************************* 68 | */ 69 | 70 | /* External argument check. */ 71 | /* Indicates if arguments received from any port ... */ 72 | /* ... interface provided by the developer or ... */ 73 | /* ... application are checked/validated. */ 74 | #define LIB_MEM_CFG_ARG_CHK_EXT_EN DEF_DISABLED 75 | 76 | 77 | /* 78 | ********************************************************************************************************* 79 | * MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION 80 | * 81 | * Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory function(s). 82 | ********************************************************************************************************* 83 | */ 84 | 85 | /* Assembly-optimized function(s). */ 86 | /* Enable/disable assembly-optimized memory ... */ 87 | /* ... function(s). [see Note #1] */ 88 | #define LIB_MEM_CFG_OPTIMIZE_ASM_EN DEF_DISABLED 89 | 90 | 91 | /* 92 | ********************************************************************************************************* 93 | * MEMORY ALLOCATION CONFIGURATION 94 | * 95 | * Note(s) : (1) Configure LIB_MEM_CFG_DBG_INFO_EN to enable/disable memory allocation usage tracking 96 | * that associates a name with each segment or dynamic pool allocated. 97 | * 98 | * (2) (a) Configure LIB_MEM_CFG_HEAP_SIZE with the desired size of heap memory (in octets). 99 | * 100 | * (b) Configure LIB_MEM_CFG_HEAP_BASE_ADDR to specify a base address for heap memory : 101 | * 102 | * (1) Heap initialized to specified application memory, if LIB_MEM_CFG_HEAP_BASE_ADDR 103 | * #define'd in 'lib_cfg.h'; 104 | * CANNOT #define to address 0x0 105 | * 106 | * (2) Heap declared to Mem_Heap[] in 'lib_mem.c', if LIB_MEM_CFG_HEAP_BASE_ADDR 107 | * NOT #define'd in 'lib_cfg.h' 108 | ********************************************************************************************************* 109 | */ 110 | 111 | /* Allocation debugging information. */ 112 | /* Enable/disable allocation of debug information ... */ 113 | /* ... associated to each memory allocation. */ 114 | #define LIB_MEM_CFG_DBG_INFO_EN DEF_DISABLED 115 | 116 | 117 | /* Heap memory size (in bytes). */ 118 | /* Configure the desired size of the heap memory. ... */ 119 | /* ... Set to 0 to disable heap allocation features. */ 120 | #define LIB_MEM_CFG_HEAP_SIZE 4096u 121 | 122 | 123 | /* Heap memory padding alignment (in bytes). */ 124 | /* Configure the desired size of padding alignment ... */ 125 | /* ... of each buffer allocated from the heap. */ 126 | #define LIB_MEM_CFG_HEAP_PADDING_ALIGN LIB_MEM_PADDING_ALIGN_NONE 127 | 128 | #if 0 /* Remove this to have heap alloc at specified addr. */ 129 | #define LIB_MEM_CFG_HEAP_BASE_ADDR 0x00000000 /* Configure heap memory base address (see Note #2b). */ 130 | #endif 131 | 132 | 133 | /* 134 | ********************************************************************************************************* 135 | ********************************************************************************************************* 136 | * STRING LIBRARY CONFIGURATION 137 | ********************************************************************************************************* 138 | ********************************************************************************************************* 139 | */ 140 | 141 | /* 142 | ********************************************************************************************************* 143 | * STRING FLOATING POINT CONFIGURATION 144 | * 145 | * Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s). 146 | * 147 | * (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant 148 | * digits to calculate &/or display for floating point string function(s). 149 | * 150 | * See also 'lib_str.h STRING FLOATING POINT DEFINES Note #1'. 151 | ********************************************************************************************************* 152 | */ 153 | 154 | /* Floating point feature(s). */ 155 | /* Enable/disable floating point to string functions. */ 156 | #define LIB_STR_CFG_FP_EN DEF_DISABLED 157 | 158 | 159 | /* Floating point number of significant digits. */ 160 | /* Configure the maximum number of significant ... */ 161 | /* ... digits to calculate &/or display for ... */ 162 | /* ... floating point string function(s). */ 163 | #define LIB_STR_CFG_FP_MAX_NBR_DIG_SIG LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT 164 | 165 | 166 | /* 167 | ********************************************************************************************************* 168 | * MODULE END 169 | ********************************************************************************************************* 170 | */ 171 | 172 | #endif /* End of lib cfg module include. */ 173 | 174 | -------------------------------------------------------------------------------- /ucos-ii/uC-CPU/C28x/CCS/cpu_c.c: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CPU 4 | * CPU CONFIGURATION & PORT LAYER 5 | * 6 | * (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL 7 | * 8 | * All rights reserved. Protected by international copyright laws. 9 | * 10 | * uC/CPU is provided in source form to registered licensees ONLY. It is 11 | * illegal to distribute this source code to any third party unless you receive 12 | * written permission by an authorized Micrium representative. Knowledge of 13 | * the source code may NOT be used to develop a similar product. 14 | * 15 | * Please help us continue to provide the Embedded community with the finest 16 | * software available. Your honesty is greatly appreciated. 17 | * 18 | * You can find our product's user manual, API reference, release notes and 19 | * more information at https://doc.micrium.com. 20 | * You can contact us at www.micrium.com. 21 | ********************************************************************************************************* 22 | */ 23 | 24 | /* 25 | ********************************************************************************************************* 26 | * 27 | * CPU PORT FILE 28 | * 29 | * TI C28x 30 | * TI C/C++ Compiler 31 | * 32 | * 33 | * Filename : cpu_c.c 34 | * Version : V1.30.02.00 35 | * Programmer(s) : JFT 36 | ********************************************************************************************************* 37 | */ 38 | 39 | 40 | /* 41 | ********************************************************************************************************* 42 | * INCLUDE FILES 43 | ********************************************************************************************************* 44 | */ 45 | 46 | #include 47 | #include 48 | 49 | 50 | #ifdef __cplusplus 51 | extern "C" { 52 | #endif 53 | 54 | 55 | /* 56 | ********************************************************************************************************* 57 | * LOCAL DEFINES 58 | ********************************************************************************************************* 59 | */ 60 | 61 | 62 | /* 63 | ********************************************************************************************************* 64 | * LOCAL CONSTANTS 65 | ********************************************************************************************************* 66 | */ 67 | 68 | 69 | /* 70 | ********************************************************************************************************* 71 | * LOCAL DATA TYPES 72 | ********************************************************************************************************* 73 | */ 74 | 75 | 76 | /* 77 | ********************************************************************************************************* 78 | * LOCAL TABLES 79 | ********************************************************************************************************* 80 | */ 81 | 82 | 83 | /* 84 | ********************************************************************************************************* 85 | * LOCAL GLOBAL VARIABLES 86 | ********************************************************************************************************* 87 | */ 88 | 89 | 90 | /* 91 | ********************************************************************************************************* 92 | * LOCAL FUNCTION PROTOTYPES 93 | ********************************************************************************************************* 94 | */ 95 | 96 | 97 | /* 98 | ********************************************************************************************************* 99 | * LOCAL CONFIGURATION ERRORS 100 | ********************************************************************************************************* 101 | */ 102 | 103 | 104 | /* 105 | ********************************************************************************************************* 106 | * CPU_IntSrcDis() 107 | * 108 | * Description : Disable an interrupt source. 109 | * 110 | * Argument(s) : int_id Interrupt source in interrupt enable register. 111 | * 112 | * Return(s) : none. 113 | * 114 | * Caller(s) : Application. 115 | * 116 | * Note(s) : (1) The RESET interrupt cannot be disabled. 117 | ********************************************************************************************************* 118 | */ 119 | 120 | void CPU_IntSrcDis (CPU_DATA bit) 121 | { 122 | CPU_SR_ALLOC(); 123 | 124 | 125 | if (bit <= CPU_INT_RTOSINT) { 126 | CPU_CRITICAL_ENTER(); 127 | IER = IER & ~(1u << (bit-1)); 128 | CPU_CRITICAL_EXIT(); 129 | } 130 | } 131 | 132 | 133 | /* 134 | ********************************************************************************************************* 135 | * CPU_IntSrcEn() 136 | * 137 | * Description : Enable an interrupt source. 138 | * 139 | * Argument(s) : int_id Interrupt source in interrupt enable register. 140 | * 141 | * Return(s) : none. 142 | * 143 | * Caller(s) : Application. 144 | * 145 | * Note(s) : none. 146 | ********************************************************************************************************* 147 | */ 148 | 149 | void CPU_IntSrcEn (CPU_DATA bit) 150 | { 151 | CPU_SR_ALLOC(); 152 | 153 | 154 | if (bit <= CPU_INT_RTOSINT) { 155 | CPU_CRITICAL_ENTER(); 156 | IER = IER | (1u << (bit-1)); 157 | CPU_CRITICAL_EXIT(); 158 | } 159 | } 160 | 161 | 162 | /* 163 | ********************************************************************************************************* 164 | * CPU_IntSrcPendClr() 165 | * 166 | * Description : Clear a pending interrupt. 167 | * 168 | * Argument(s) : bit Bit of interrupt source in interrupt enable register (see 'CPU_IntSrcDis()'). 169 | * 170 | * Return(s) : none. 171 | * 172 | * Caller(s) : Application. 173 | * 174 | * Note(s) : none. 175 | ********************************************************************************************************* 176 | */ 177 | 178 | void CPU_IntSrcPendClr (CPU_DATA bit) 179 | { 180 | /* The 'AND IFR' instruction cannot be used with ... */ 181 | /* ... anything else than a 16bit constant. */ 182 | switch (bit) { 183 | case CPU_INT_RTOSINT: 184 | asm(" AND IFR, #0x7FFF"); 185 | break; 186 | 187 | 188 | case CPU_INT_DLOGINT: 189 | asm(" AND IFR, #0xBFFF"); 190 | break; 191 | 192 | 193 | case CPU_INT_INT14: 194 | asm(" AND IFR, #0xDFFF"); 195 | break; 196 | 197 | 198 | case CPU_INT_INT13: 199 | asm(" AND IFR, #0xEFFF"); 200 | break; 201 | 202 | 203 | case CPU_INT_INT12: 204 | asm(" AND IFR, #0xF7FF"); 205 | break; 206 | 207 | 208 | case CPU_INT_INT11: 209 | asm(" AND IFR, #0xFBFF"); 210 | break; 211 | 212 | 213 | case CPU_INT_INT10: 214 | asm(" AND IFR, #0xFDFF"); 215 | break; 216 | 217 | 218 | case CPU_INT_INT9: 219 | asm(" AND IFR, #0xFEFF"); 220 | break; 221 | 222 | 223 | case CPU_INT_INT8: 224 | asm(" AND IFR, #0xFF7F"); 225 | break; 226 | 227 | 228 | case CPU_INT_INT7: 229 | asm(" AND IFR, #0xFFBF"); 230 | break; 231 | 232 | 233 | case CPU_INT_INT6: 234 | asm(" AND IFR, #0xFFDF"); 235 | break; 236 | 237 | 238 | case CPU_INT_INT5: 239 | asm(" AND IFR, #0xFFEF"); 240 | break; 241 | 242 | 243 | case CPU_INT_INT4: 244 | asm(" AND IFR, #0xFFF7"); 245 | break; 246 | 247 | 248 | case CPU_INT_INT3: 249 | asm(" AND IFR, #0xFFFB"); 250 | break; 251 | 252 | 253 | case CPU_INT_INT2: 254 | asm(" AND IFR, #0xFFFD"); 255 | break; 256 | 257 | 258 | case CPU_INT_INT1: 259 | asm(" AND IFR, #0xFFFE"); 260 | break; 261 | 262 | 263 | default: /* 'default' case intentionally empty. */ 264 | break; 265 | } 266 | } 267 | 268 | 269 | #ifdef __cplusplus 270 | } 271 | #endif 272 | -------------------------------------------------------------------------------- /ucos-ii/uC-CPU/cpu_cache.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CPU 4 | * CPU CONFIGURATION & PORT LAYER 5 | * 6 | * (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL 7 | * 8 | * All rights reserved. Protected by international copyright laws. 9 | * 10 | * uC/CPU is provided in source form to registered licensees ONLY. It is 11 | * illegal to distribute this source code to any third party unless you receive 12 | * written permission by an authorized Micrium representative. Knowledge of 13 | * the source code may NOT be used to develop a similar product. 14 | * 15 | * Please help us continue to provide the Embedded community with the finest 16 | * software available. Your honesty is greatly appreciated. 17 | * 18 | * You can find our product's user manual, API reference, release notes and 19 | * more information at https://doc.micrium.com. 20 | * You can contact us at www.micrium.com. 21 | ********************************************************************************************************* 22 | */ 23 | 24 | /* 25 | ********************************************************************************************************* 26 | * 27 | * CACHE CPU MODULE 28 | * 29 | * Filename : cpu_cache.h 30 | * Version : V1.30.02 31 | * Programmer(s) : JBL 32 | ********************************************************************************************************* 33 | */ 34 | 35 | 36 | /* 37 | ********************************************************************************************************* 38 | * MODULE 39 | * 40 | * Note(s) : (1) This cache CPU header file is protected from multiple pre-processor inclusion through use of 41 | * the cache CPU module present pre-processor macro definition. 42 | ********************************************************************************************************* 43 | */ 44 | 45 | #ifndef CPU_CACHE_MODULE_PRESENT /* See Note #1. */ 46 | #define CPU_CACHE_MODULE_PRESENT 47 | 48 | 49 | /* 50 | ********************************************************************************************************* 51 | * EXTERNS 52 | ********************************************************************************************************* 53 | */ 54 | 55 | #ifdef CPU_CACHE_MODULE 56 | #define CPU_CACHE_EXT 57 | #else 58 | #define CPU_CACHE_EXT extern 59 | #endif 60 | 61 | 62 | /* 63 | ********************************************************************************************************* 64 | * INCLUDE FILES 65 | ********************************************************************************************************* 66 | */ 67 | 68 | #include 69 | #include 70 | #include 71 | 72 | 73 | /* 74 | ********************************************************************************************************* 75 | * CACHE CONFIGURATION 76 | ********************************************************************************************************* 77 | */ 78 | 79 | #ifndef CPU_CFG_CACHE_MGMT_EN 80 | #define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED 81 | #endif 82 | 83 | 84 | /* 85 | ********************************************************************************************************* 86 | * CACHE OPERATIONS DEFINES 87 | ********************************************************************************************************* 88 | */ 89 | 90 | #if (CPU_CFG_CACHE_MGMT_EN == DEF_ENABLED) 91 | #ifndef CPU_DCACHE_RANGE_FLUSH 92 | #define CPU_DCACHE_RANGE_FLUSH(addr_start, len) CPU_DCache_RangeFlush(addr_start, len) 93 | #endif /* CPU_DCACHE_RANGE_FLUSH */ 94 | #else 95 | #define CPU_DCACHE_RANGE_FLUSH(addr_start, len) 96 | #endif /* CPU_CFG_CACHE_MGMT_EN) */ 97 | 98 | 99 | #if (CPU_CFG_CACHE_MGMT_EN == DEF_ENABLED) 100 | #ifndef CPU_DCACHE_RANGE_INV 101 | #define CPU_DCACHE_RANGE_INV(addr_start, len) CPU_DCache_RangeInv(addr_start, len) 102 | #endif /* CPU_DCACHE_RANGE_INV */ 103 | #else 104 | #define CPU_DCACHE_RANGE_INV(addr_start, len) 105 | #endif /* CPU_CFG_CACHE_MGMT_EN) */ 106 | 107 | 108 | /* 109 | ********************************************************************************************************* 110 | * FUNCTION PROTOTYPES 111 | ********************************************************************************************************* 112 | */ 113 | 114 | #if (CPU_CFG_CACHE_MGMT_EN == DEF_ENABLED) 115 | 116 | #ifdef __cplusplus 117 | extern "C" { 118 | #endif 119 | 120 | void CPU_Cache_Init (void); 121 | 122 | void CPU_DCache_RangeFlush(void *addr_start, 123 | CPU_ADDR len); 124 | 125 | void CPU_DCache_RangeInv (void *addr_start, 126 | CPU_ADDR len); 127 | 128 | #ifdef __cplusplus 129 | } 130 | #endif 131 | 132 | #endif /* CPU_CFG_CACHE_MGMT_EN */ 133 | 134 | 135 | /* 136 | ********************************************************************************************************* 137 | * MODULE END 138 | * 139 | * Note(s) : (1) See 'cpu_core.h MODULE'. 140 | ********************************************************************************************************* 141 | */ 142 | 143 | #endif /* End of CPU core module include. */ 144 | -------------------------------------------------------------------------------- /ucos-ii/uCOS-II/Ports/C28x/Generic/CCS/os_cpu.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/OS-II 4 | * The Real-Time Kernel 5 | * 6 | * 7 | * (c) Copyright 2009-2015; Micrium, Inc.; Weston, FL 8 | * All rights reserved. Protected by international copyright laws. 9 | * 10 | * TI C28x Port 11 | * 12 | * File : OS_CPU.H 13 | ; Version : V2.92.11 14 | * By : JFT 15 | * 16 | * LICENSING TERMS: 17 | * --------------- 18 | * uC/OS-II is provided in source form for FREE short-term evaluation, for educational use or 19 | * for peaceful research. If you plan or intend to use uC/OS-II in a commercial application/ 20 | * product then, you need to contact Micrium to properly license uC/OS-II for its use in your 21 | * application/product. We provide ALL the source code for your convenience and to help you 22 | * experience uC/OS-II. The fact that the source is provided does NOT mean that you can use 23 | * it commercially without paying a licensing fee. 24 | * 25 | * Knowledge of the source code may NOT be used to develop a similar product. 26 | * 27 | * Please help us continue to provide the embedded community with the finest software available. 28 | * Your honesty is greatly appreciated. 29 | * 30 | * You can contact us at www.micrium.com, or by phone at +1 (954) 217-2036. 31 | * 32 | * For : TI C28x 33 | * Mode : C28 Object mode 34 | * Toolchain : TI C/C++ Compiler 35 | ********************************************************************************************************* 36 | */ 37 | 38 | #ifndef OS_CPU_H 39 | #define OS_CPU_H 40 | 41 | #ifdef OS_CPU_GLOBALS 42 | #define OS_CPU_EXT 43 | #else 44 | #define OS_CPU_EXT extern 45 | #endif 46 | 47 | 48 | /* 49 | ********************************************************************************************************* 50 | * DEFINES 51 | ********************************************************************************************************* 52 | */ 53 | 54 | 55 | /* 56 | ********************************************************************************************************* 57 | * OS TICK INTERRUPT PRIORITY CONFIGURATION 58 | * 59 | * Note(s) : (1) For systems that don't need any high, real-time priority interrupts; the tick interrupt 60 | * should be configured as the highest priority interrupt but won't adversely affect system 61 | * operations. 62 | * 63 | * (2) For systems that need one or more high, real-time interrupts; these should be configured 64 | * higher than the tick interrupt which MAY delay execution of the tick interrupt. 65 | * 66 | * (a) If the higher priority interrupts do NOT continually consume CPU cycles but only 67 | * occasionally delay tick interrupts, then the real-time interrupts can successfully 68 | * handle their intermittent/periodic events with the system not losing tick interrupts 69 | * but only increasing the jitter. 70 | * 71 | * (b) If the higher priority interrupts consume enough CPU cycles to continually delay the 72 | * tick interrupt, then the CPU/system is most likely over-burdened & can't be expected 73 | * to handle all its interrupts/tasks. The system time reference gets compromised as a 74 | * result of losing tick interrupts. 75 | ********************************************************************************************************* 76 | */ 77 | 78 | 79 | /* 80 | ********************************************************************************************************* 81 | * DATA TYPES 82 | * (Compiler Specific) 83 | ********************************************************************************************************* 84 | */ 85 | 86 | typedef unsigned char BOOLEAN; 87 | typedef unsigned char INT8U; /* Unsigned 8 bit quantity */ 88 | typedef signed char INT8S; /* Signed 8 bit quantity */ 89 | typedef unsigned short INT16U; /* Unsigned 16 bit quantity */ 90 | typedef signed short INT16S; /* Signed 16 bit quantity */ 91 | typedef unsigned long INT32U; /* Unsigned 32 bit quantity */ 92 | typedef signed long INT32S; /* Signed 32 bit quantity */ 93 | typedef float FP32; /* Single precision floating point */ 94 | typedef long double FP64; /* Double precision floating point */ 95 | 96 | typedef unsigned short OS_STK; /* Each stack entry is 16-bit wide */ 97 | typedef unsigned short OS_CPU_SR; /* Define size of CPU status register (INTM = 1 bit) */ 98 | 99 | 100 | /* 101 | ********************************************************************************************************* 102 | * C28x 103 | * Critical Section Management 104 | * 105 | * Method #1: Disable/Enable interrupts using simple instructions. After critical section, interrupts 106 | * will be enabled even if they were disabled before entering the critical section. 107 | * NOT IMPLEMENTED 108 | * 109 | * Method #2: Disable/Enable interrupts by preserving the state of interrupts. In other words, if 110 | * interrupts were disabled before entering the critical section, they will be disabled when 111 | * leaving the critical section. 112 | * NOT IMPLEMENTED 113 | * 114 | * Method #3: Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you 115 | * would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then 116 | * disable interrupts. 'cpu_sr' is allocated in all of uC/OS-II's functions that need to 117 | * disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr' 118 | * into the CPU's status register. 119 | ********************************************************************************************************* 120 | */ 121 | 122 | #define OS_CRITICAL_METHOD 3u 123 | 124 | #if OS_CRITICAL_METHOD == 3u 125 | #define OS_ENTER_CRITICAL() {cpu_sr = OS_CPU_SR_Save();} 126 | #define OS_EXIT_CRITICAL() {OS_CPU_SR_Restore(cpu_sr);} 127 | #endif 128 | 129 | 130 | /* 131 | ********************************************************************************************************* 132 | * C28x Miscellaneous 133 | ********************************************************************************************************* 134 | */ 135 | 136 | #define OS_STK_GROWTH 0u /* Stack grows from LOW to HIGH memory on C28x */ 137 | 138 | 139 | /* 140 | ********************************************************************************************************* 141 | * OS_TASK_SW 142 | * 143 | * Note(s): OS_TASK_SW() invokes the task level context switch. 144 | * 145 | * (1) On some processors, this corresponds to a call to OSCtxSw() which is an assembly language 146 | * function that performs the context switch. 147 | * 148 | * (2) On some processors, you need to simulate an interrupt using a 'software interrupt' or a 149 | * TRAP instruction. Some compilers allow you to add in-line assembly language as shown. 150 | ********************************************************************************************************* 151 | */ 152 | 153 | #define OS_TASK_SW() asm(" TRAP #16") 154 | 155 | 156 | /* 157 | ********************************************************************************************************* 158 | * OSIntCtxSw 159 | * 160 | * Note(s): OSIntCtxSw() invokes the interrupt level context switch. 161 | * 162 | * (1) On some processors, this corresponds to a call to OSIntCtxSw() which is an assembly language 163 | * function that performs the context switch. 164 | * 165 | * (2) On some processors, you need to simulate an interrupt using a 'software interrupt' or a 166 | * TRAP instruction. Some compilers allow you to add in-line assembly language as shown. 167 | ********************************************************************************************************* 168 | */ 169 | 170 | #define OSIntCtxSw() asm(" TRAP #16") 171 | 172 | 173 | /* 174 | ********************************************************************************************************* 175 | * GLOBAL VARIABLES 176 | ********************************************************************************************************* 177 | */ 178 | 179 | 180 | /* 181 | ********************************************************************************************************* 182 | * FUNCTION PROTOTYPES 183 | ********************************************************************************************************* 184 | */ 185 | /* Wrapper functions to get ST0 and ST1 registers. */ 186 | INT16U OS_CPU_GetST0 (void); 187 | INT16U OS_CPU_GetST1 (void); 188 | /* OS-II Port Implementation. See OS_CPU_A.ASM */ 189 | #if (OS_CRITICAL_METHOD == 3u) 190 | OS_CPU_SR OS_CPU_SR_Save (void); 191 | void OS_CPU_SR_Restore (OS_CPU_SR cpu_sr); 192 | #endif 193 | 194 | void OSStartHighRdy (void); 195 | 196 | void OS_CPU_RTOSINT_Handler(void); 197 | 198 | #endif 199 | 200 | -------------------------------------------------------------------------------- /ucos-ii/uCOS-II/Ports/C28x/Generic/CCS/os_cpu_i.asm: -------------------------------------------------------------------------------- 1 | ; 2 | ;******************************************************************************************************** 3 | ; uC/OS-II 4 | ; The Real-Time Kernel 5 | ; 6 | ; 7 | ; (c) Copyright 2009-2015; Micrium, Inc.; Weston, FL 8 | ; All rights reserved. Protected by international copyright laws. 9 | ; 10 | ; ASSEMBLY LANGUAGE MACROS 11 | ; TI C28x Port 12 | ; 13 | ; File : OS_CPU_I.ASM 14 | ; Version : V2.92.11 15 | ; By : JFT 16 | ; 17 | ; LICENSING TERMS: 18 | ; --------------- 19 | ; uC/OS-II is provided in source form for FREE short-term evaluation, for educational use or 20 | ; for peaceful research. If you plan or intend to use uC/OS-II in a commercial application/ 21 | ; product then, you need to contact Micrium to properly license uC/OS-II for its use in your 22 | ; application/product. We provide ALL the source code for your convenience and to help you 23 | ; experience uC/OS-II. The fact that the source is provided does NOT mean that you can use 24 | ; it commercially without paying a licensing fee. 25 | ; 26 | ; Knowledge of the source code may NOT be used to develop a similar product. 27 | ; 28 | ; Please help us continue to provide the embedded community with the finest software available. 29 | ; Your honesty is greatly appreciated. 30 | ; 31 | ; You can contact us at www.micrium.com, or by phone at +1 (954) 217-2036. 32 | ; 33 | ; For : TI C28x 34 | ; Mode : C28 Object mode 35 | ; Toolchain : TI C/C++ Compiler 36 | ;******************************************************************************************************** 37 | ; 38 | 39 | ;******************************************************************************************************** 40 | ; OS_CTX_SAVE 41 | ; 42 | ; Description : This MACRO saves the CPU registers (i.e. CPU context) onto the current task's stack using 43 | ; the same order as they were saved in OSTaskStkInit(). 44 | ;******************************************************************************************************** 45 | 46 | OS_CTX_SAVE .macro 47 | ; Save remaining registers. 48 | PUSH AR1H:AR0H ; AR1H:AR0H 49 | PUSH XAR2 ; XAR2 50 | PUSH XAR3 ; XAR3 51 | PUSH XAR4 ; XAR4 52 | PUSH XAR5 ; XAR5 53 | PUSH XAR6 ; XAR6 54 | PUSH XAR7 ; XAR7 55 | PUSH XT ; XT 56 | PUSH RPC ; RPC 57 | 58 | .if .TMS320C2800_FPU32 = 1 ; Save FPU registers, if enabled. 59 | MOVZ AR1 , @SP ; Can't use SP for indirect addressing. 60 | MOV32 *XAR1++, R0H ; R0H 61 | MOV32 *XAR1++, R1H ; R1H 62 | MOV32 *XAR1++, R2H ; R2H 63 | MOV32 *XAR1++, R3H ; R3H 64 | MOV32 *XAR1++, R4H ; R4H 65 | MOV32 *XAR1++, R5H ; R5H 66 | MOV32 *XAR1++, R6H ; R6H 67 | MOV32 *XAR1++, R7H ; R7H 68 | MOV32 *XAR1++, STF ; STF 69 | MOV AL , AR1 ; Can't use indirect addressing with RB. 70 | MOV @SP , AL ; Restore SP. 71 | PUSH RB ; RB 72 | .endif 73 | .endm 74 | 75 | 76 | ;******************************************************************************************************** 77 | ; OS_CTX_RESTORE 78 | ; 79 | ; Description : This MACRO restores the CPU registers (i.e. context) from the new task's stack in the 80 | ; reverse order of OS_CTX_SAVE (see above) 81 | ;******************************************************************************************************** 82 | 83 | OS_CTX_RESTORE .macro 84 | .if .TMS320C2800_FPU32 = 1 ; Restore FPU registers, if enabled. 85 | POP RB ; RB 86 | MOVZ AR1, @SP ; Can't use SP for indirect addressing. 87 | MOV32 STF, *--XAR1 ; STF 88 | MOV32 R7H, *--XAR1 ; R7H 89 | MOV32 R6H, *--XAR1 ; R6H 90 | MOV32 R5H, *--XAR1 ; R5H 91 | MOV32 R4H, *--XAR1 ; R4H 92 | MOV32 R3H, *--XAR1 ; R3H 93 | MOV32 R2H, *--XAR1 ; R2H 94 | MOV32 R1H, *--XAR1 ; R1H 95 | MOV32 R0H, *--XAR1 ; R0H 96 | MOV AL , AR1 ; Restore SP. 97 | MOV @SP , AL 98 | .endif 99 | ; Restore CPU registers part 1. 100 | POP RPC ; RPC 101 | POP XT ; XT 102 | POP XAR7 ; XAR7 103 | POP XAR6 ; XAR6 104 | POP XAR5 ; XAR5 105 | POP XAR4 ; XAR4 106 | POP XAR3 ; XAR3 107 | POP XAR2 ; XAR2 108 | 109 | ; Overwrite saved IER in stack frame. 110 | MOVZ AR0 , @SP ; Get SP. 111 | SUBB XAR0, #6 ; Point to old IER. 112 | MOVL ACC , *XAR0 ; Get old DBGSTAT:IER. 113 | AND ACC, #0xFFFF << 16 114 | MOV AL, IER ; Get current IER. 115 | MOVL *XAR0, ACC ; Overwrite IER. 116 | 117 | ; Restore registers part 2. 118 | POP AR1H:AR0H ; AR1H:AR0H 119 | .endm 120 | 121 | -------------------------------------------------------------------------------- /ucos-ii/uCOS-II/Ports/C28x/Generic/CCS/os_dbg.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RanFang66/ucOSii_in_DSP28335/df9a1a31f72235402295e755e2eb0a9be9eb3e62/ucos-ii/uCOS-II/Ports/C28x/Generic/CCS/os_dbg.c -------------------------------------------------------------------------------- /ucos-ii/uCOS-II/Source/os.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/OS-II 4 | * The Real-Time Kernel 5 | * 6 | * (c) Copyright 1992-2013, Micrium, Weston, FL 7 | * All Rights Reserved 8 | * 9 | * File : os.h 10 | * By : Jean J. Labrosse 11 | * Version : V2.92.10 12 | * 13 | * LICENSING TERMS: 14 | * --------------- 15 | * uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. 16 | * If you plan on using uC/OS-II in a commercial product you need to contact Micrium to properly license 17 | * its use in your product. We provide ALL the source code for your convenience and to help you experience 18 | * uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a 19 | * licensing fee. 20 | * 21 | * Note : This file is included in the uC/OS-II for compatibility with uC/OS-III and should not be used 22 | * in normal circumstances. 23 | ********************************************************************************************************* 24 | */ 25 | 26 | #include 27 | 28 | 29 | typedef INT8U OS_ERR; 30 | --------------------------------------------------------------------------------