├── .gitignore
├── .gitmodules
├── .travis.yml
├── AUTHORS
├── CLI
    ├── CLI.cpp
    ├── CLI.h
    ├── CLIBase.cpp
    ├── CLICommands.cpp
    ├── CLIServer.cpp
    ├── Makefile.am
    └── README.CLI
├── COPYING
├── ChangeLog
├── Control
    ├── CBS.cpp
    ├── CBS.h
    ├── CodecSet.h
    ├── ControlCommon.h
    ├── ControlTransfer.cpp
    ├── ControlTransfer.h
    ├── DCCHDispatch.cpp
    ├── L3CallControl.cpp
    ├── L3CallControl.h
    ├── L3Handover.cpp
    ├── L3Handover.h
    ├── L3LogicalChannel.cpp
    ├── L3LogicalChannel.h
    ├── L3MMLayer.cpp
    ├── L3MMLayer.h
    ├── L3MobilityManagement.cpp
    ├── L3MobilityManagement.h
    ├── L3SMSControl.cpp
    ├── L3SMSControl.h
    ├── L3StateMachine.cpp
    ├── L3StateMachine.h
    ├── L3SupServ.cpp
    ├── L3SupServ.h
    ├── L3TermCause.cpp
    ├── L3TermCause.h
    ├── L3TranEntry.cpp
    ├── L3TranEntry.h
    ├── L3Utils.cpp
    ├── L3Utils.h
    ├── Makefile.am
    ├── PagingEntry.cpp
    ├── PagingEntry.h
    ├── README.Control
    ├── RRLPServer.cpp
    ├── RRLPServer.h
    ├── RRLP_PDU_Test.cpp
    ├── TMSITable.cpp
    ├── TMSITable.h
    └── ladders.awk
├── GPRS
    ├── BSSG.cpp
    ├── BSSG.h
    ├── BSSGMessages.cpp
    ├── BSSGMessages.h
    ├── ByteVector.cpp
    ├── ByteVector.h
    ├── CS4.txt
    ├── FEC.cpp
    ├── FEC.h
    ├── GPRSCLI.cpp
    ├── GPRSExport.h
    ├── GPRSInternal.h
    ├── GPRSRLC.h
    ├── GPRSTDMA.h
    ├── MAC.cpp
    ├── MAC.h
    ├── MSInfo.cpp
    ├── MSInfo.h
    ├── Makefile.am
    ├── MsgBase.cpp
    ├── MsgBase.h
    ├── RLC.cpp
    ├── RLCEngine.cpp
    ├── RLCEngine.h
    ├── RLCHdr.h
    ├── RLCMessages.cpp
    ├── RLCMessages.h
    ├── RList.h
    ├── ScalarTypes.h
    ├── TBF.cpp
    ├── TBF.h
    ├── makefile.pat
    ├── makefile.tests
    ├── notes.txt
    ├── pat.txt
    ├── pinghttp.c
    └── todo.txt
├── GSM
    ├── AppInfTest.cpp
    ├── GSM610Tables.cpp
    ├── GSM610Tables.h
    ├── GSMCCCH.cpp
    ├── GSMCCCH.h
    ├── GSMChannelHistory.cpp
    ├── GSMChannelHistory.h
    ├── GSMCommon.cpp
    ├── GSMCommon.h
    ├── GSMConfig.cpp
    ├── GSMConfig.h
    ├── GSML1FEC.cpp
    ├── GSML1FEC.h
    ├── GSML2LAPDm.cpp
    ├── GSML2LAPDm.h
    ├── GSML3CCElements.cpp
    ├── GSML3CCElements.h
    ├── GSML3CCMessages.cpp
    ├── GSML3CCMessages.h
    ├── GSML3CommonElements.cpp
    ├── GSML3CommonElements.h
    ├── GSML3GPRSElements.cpp
    ├── GSML3GPRSElements.h
    ├── GSML3MMElements.cpp
    ├── GSML3MMElements.h
    ├── GSML3MMMessages.cpp
    ├── GSML3MMMessages.h
    ├── GSML3Message.cpp
    ├── GSML3Message.h
    ├── GSML3RRElements.cpp
    ├── GSML3RRElements.h
    ├── GSML3RRMessages.cpp
    ├── GSML3RRMessages.h
    ├── GSML3SSMessages.cpp
    ├── GSML3SSMessages.h
    ├── GSMLogicalChannel.cpp
    ├── GSMLogicalChannel.h
    ├── GSMRadioResource.cpp
    ├── GSMRadioResource.h
    ├── GSMSMSCBL3Messages.cpp
    ├── GSMSMSCBL3Messages.h
    ├── GSMTAPDump.cpp
    ├── GSMTAPDump.h
    ├── GSMTDMA.cpp
    ├── GSMTDMA.h
    ├── GSMTransfer.cpp
    ├── GSMTransfer.h
    ├── Makefile.am
    ├── PhysicalStatus.cpp
    ├── PhysicalStatus.h
    ├── PowerManager.cpp
    ├── PowerManager.h
    └── gsmtap.h
├── GSMShare
    ├── A51.cpp
    ├── A51.h
    ├── A51Test.cpp
    ├── AMRTest.cpp
    ├── AmrCoder.cpp
    ├── AmrCoder.h
    ├── GSM503Tables.cpp
    ├── GSM503Tables.h
    ├── L3Enums.cpp
    ├── L3Enums.h
    ├── Makefile.am
    ├── Viterbi.h
    ├── ViterbiR204.cpp
    ├── ViterbiR204.h
    └── ViterbiTest.cpp
├── Globals
    ├── GlobalVars.cpp
    ├── Globals.cpp
    ├── Globals.h
    ├── GrabRepoInfo.sh
    └── Makefile.am
├── INSTALL
├── INSTALLATION
├── LEGAL
├── Makefile.am
├── Makefile.common
├── NEWS
├── Peering
    ├── Makefile.am
    ├── NeighborTable.cpp
    ├── NeighborTable.h
    ├── Peering.cpp
    └── Peering.h
├── README
├── README.APIs.md
├── SGSNGGSN
    ├── GPRSL3Messages.cpp
    ├── GPRSL3Messages.h
    ├── Ggsn.cpp
    ├── Ggsn.h
    ├── LLC.cpp
    ├── LLC.h
    ├── Makefile.am
    ├── Sgsn.cpp
    ├── Sgsn.h
    ├── SgsnBase.h
    ├── SgsnCli.cpp
    ├── SgsnExport.h
    ├── iputils.cpp
    ├── miniggsn.cpp
    └── miniggsn.h
├── SIP
    ├── Makefile.am
    ├── SIP2Interface.cpp
    ├── SIP2Interface.h
    ├── SIPBNF.txt
    ├── SIPBase.cpp
    ├── SIPBase.h
    ├── SIPDialog.cpp
    ├── SIPDialog.h
    ├── SIPExport.h
    ├── SIPMessage.cpp
    ├── SIPMessage.h
    ├── SIPParse.cpp
    ├── SIPParse.h
    ├── SIPRtp.cpp
    ├── SIPRtp.h
    ├── SIPTransaction.cpp
    ├── SIPTransaction.h
    ├── SIPUtility.cpp
    └── SIPUtility.h
├── SMS
    ├── Makefile.am
    ├── SMSMessages.cpp
    ├── SMSMessages.h
    ├── SMSTransfer.cpp
    └── SMSTransfer.h
├── Scanning
    ├── Makefile.am
    ├── Scanning.cpp
    └── Scanning.h
├── TRXManager
    ├── Makefile.am
    ├── README.TRXManager
    ├── TRXManager.cpp
    ├── TRXManager.h
    └── clockdump.sh
├── Transceiver52M
    ├── Complex.h
    ├── DummyLoad.cpp
    ├── DummyLoad.h
    ├── Makefile.am
    ├── README
    ├── README.DFEsymbolspaced
    ├── README.Talgorithm
    ├── Resampler.cpp
    ├── Resampler.h
    ├── Transceiver.cpp
    ├── Transceiver.h
    ├── UHDDevice.cpp
    ├── USRPDevice.cpp
    ├── USRPDevice.h
    ├── convert.c
    ├── convert.h
    ├── convolve.c
    ├── convolve.h
    ├── inband-signaling-usb
    ├── laurent.m
    ├── pulseApproximate.m
    ├── radioClock.cpp
    ├── radioClock.h
    ├── radioDevice.h
    ├── radioInterface.cpp
    ├── radioInterface.h
    ├── radioInterfaceResamp.cpp
    ├── radioVector.cpp
    ├── radioVector.h
    ├── runTransceiver.cpp
    ├── sigProcLib.cpp
    ├── sigProcLib.h
    └── std_inband.rbf
├── TransceiverRAD1
    ├── Complex.h
    ├── DummyLoad.cpp
    ├── DummyLoad.h
    ├── FactoryCalibration.cpp
    ├── FactoryCalibration.h
    ├── Makefile.am
    ├── PowerScanner.cpp
    ├── RAD1Cmd.cpp
    ├── RAD1Device.cpp
    ├── RAD1Device.h
    ├── RAD1RxRawPower.cpp
    ├── RAD1RxRawPowerSweep.cpp
    ├── RAD1SN.cpp
    ├── RAD1ping.cpp
    ├── README
    ├── README.DFEsymbolspaced
    ├── README.Talgorithm
    ├── Transceiver.cpp
    ├── Transceiver.h
    ├── ad9862.h
    ├── burn-rnrad1-eeprom.sh
    ├── bytesex.h
    ├── commands.h
    ├── ezusb.ihx
    ├── fpga.rbf
    ├── fpga
    │   ├── README.RAD1
    │   ├── inband_lib
    │   │   ├── chan_fifo_reader.v
    │   │   ├── channel_demux.v
    │   │   ├── channel_ram.v
    │   │   ├── cmd_reader.v
    │   │   ├── data_packet_fifo.v
    │   │   ├── packet_builder.v
    │   │   ├── register_io.v
    │   │   ├── rx_buffer_inband.v
    │   │   ├── test_comparator.v
    │   │   ├── tx_buffer_inband.v
    │   │   ├── tx_packer.v
    │   │   ├── usb_fifo_reader.v
    │   │   ├── usb_fifo_writer.v
    │   │   └── usb_packet_fifo.v
    │   ├── megacells
    │   │   ├── accum32.bsf
    │   │   ├── accum32.cmp
    │   │   ├── accum32.inc
    │   │   ├── accum32.v
    │   │   ├── accum32_bb.v
    │   │   ├── accum32_inst.v
    │   │   ├── add32.bsf
    │   │   ├── add32.cmp
    │   │   ├── add32.inc
    │   │   ├── add32.v
    │   │   ├── add32_bb.v
    │   │   ├── add32_inst.v
    │   │   ├── addsub16.bsf
    │   │   ├── addsub16.cmp
    │   │   ├── addsub16.inc
    │   │   ├── addsub16.v
    │   │   ├── addsub16_bb.v
    │   │   ├── addsub16_inst.v
    │   │   ├── bustri.bsf
    │   │   ├── bustri.cmp
    │   │   ├── bustri.inc
    │   │   ├── bustri.v
    │   │   ├── bustri_bb.v
    │   │   ├── bustri_inst.v
    │   │   ├── clk_doubler.v
    │   │   ├── clk_doubler_bb.v
    │   │   ├── dspclkpll.v
    │   │   ├── dspclkpll_bb.v
    │   │   ├── fifo_1kx16.bsf
    │   │   ├── fifo_1kx16.cmp
    │   │   ├── fifo_1kx16.inc
    │   │   ├── fifo_1kx16.v
    │   │   ├── fifo_1kx16_bb.v
    │   │   ├── fifo_1kx16_inst.v
    │   │   ├── fifo_2k.v
    │   │   ├── fifo_2k_bb.v
    │   │   ├── fifo_4k.v
    │   │   ├── fifo_4k_18.v
    │   │   ├── fifo_4k_bb.v
    │   │   ├── fifo_4kx16_dc.bsf
    │   │   ├── fifo_4kx16_dc.cmp
    │   │   ├── fifo_4kx16_dc.inc
    │   │   ├── fifo_4kx16_dc.v
    │   │   ├── fifo_4kx16_dc_bb.v
    │   │   ├── fifo_4kx16_dc_inst.v
    │   │   ├── mylpm_addsub.bsf
    │   │   ├── mylpm_addsub.cmp
    │   │   ├── mylpm_addsub.inc
    │   │   ├── mylpm_addsub.v
    │   │   ├── mylpm_addsub_bb.v
    │   │   ├── mylpm_addsub_inst.v
    │   │   ├── pll.v
    │   │   ├── pll_bb.v
    │   │   ├── pll_inst.v
    │   │   ├── sub32.bsf
    │   │   ├── sub32.cmp
    │   │   ├── sub32.inc
    │   │   ├── sub32.v
    │   │   ├── sub32_bb.v
    │   │   └── sub32_inst.v
    │   ├── models
    │   │   ├── bustri.v
    │   │   ├── fifo.v
    │   │   ├── fifo_1c_1k.v
    │   │   ├── fifo_1c_2k.v
    │   │   ├── fifo_1c_4k.v
    │   │   ├── fifo_1k.v
    │   │   ├── fifo_2k.v
    │   │   ├── fifo_4k.v
    │   │   ├── fifo_4k_18.v
    │   │   ├── pll.v
    │   │   └── ssram.v
    │   ├── sdr_lib
    │   │   ├── adc_interface.v
    │   │   ├── atr_delay.v
    │   │   ├── bidir_reg.v
    │   │   ├── cic_dec_shifter.v
    │   │   ├── cic_decim.v
    │   │   ├── cic_int_shifter.v
    │   │   ├── cic_interp.v
    │   │   ├── clk_divider.v
    │   │   ├── cordic.v
    │   │   ├── cordic_stage.v
    │   │   ├── ddc.v
    │   │   ├── dpram.v
    │   │   ├── duc.v
    │   │   ├── ext_fifo.v
    │   │   ├── fifo_1kx16.bsf
    │   │   ├── fifo_1kx16.cmp
    │   │   ├── fifo_1kx16.inc
    │   │   ├── fifo_1kx16.v
    │   │   ├── fifo_1kx16_bb.v
    │   │   ├── fifo_1kx16_inst.v
    │   │   ├── fifo_4kx16_dc.bsf
    │   │   ├── fifo_4kx16_dc.cmp
    │   │   ├── fifo_4kx16_dc.inc
    │   │   ├── fifo_4kx16_dc.v
    │   │   ├── fifo_4kx16_dc_bb.v
    │   │   ├── fifo_4kx16_dc_inst.v
    │   │   ├── gen_cordic_consts.py
    │   │   ├── gen_sync.v
    │   │   ├── hb
    │   │   │   ├── acc.v
    │   │   │   ├── coeff_rom.v
    │   │   │   ├── halfband_decim.v
    │   │   │   ├── halfband_interp.v
    │   │   │   ├── mac.v
    │   │   │   ├── mult.v
    │   │   │   ├── ram16_2port.v
    │   │   │   ├── ram16_2sum.v
    │   │   │   └── ram32_2sum.v
    │   │   ├── io_pins.v
    │   │   ├── master_control.v
    │   │   ├── master_control_multi.v
    │   │   ├── phase_acc.v
    │   │   ├── ram.v
    │   │   ├── ram16.v
    │   │   ├── ram32.v
    │   │   ├── ram64.v
    │   │   ├── rssi.v
    │   │   ├── rx_buffer.v
    │   │   ├── rx_chain.v
    │   │   ├── rx_chain_dual.v
    │   │   ├── rx_dcoffset.v
    │   │   ├── serial_io.v
    │   │   ├── setting_reg.v
    │   │   ├── setting_reg_masked.v
    │   │   ├── sign_extend.v
    │   │   ├── strobe_gen.v
    │   │   ├── tx_buffer.v
    │   │   ├── tx_chain.v
    │   │   └── tx_chain_hb.v
    │   └── toplevel
    │   │   ├── include
    │   │       ├── common_config_1rxhb_1tx.vh
    │   │       ├── common_config_2rxhb_2tx.vh
    │   │       └── common_config_bottom.vh
    │   │   └── usrp_inband_usb
    │   │       ├── config.vh
    │   │       ├── usrp_inband_usb.csf
    │   │       ├── usrp_inband_usb.esf
    │   │       ├── usrp_inband_usb.pin
    │   │       ├── usrp_inband_usb.psf
    │   │       ├── usrp_inband_usb.qpf
    │   │       ├── usrp_inband_usb.qsf
    │   │       └── usrp_inband_usb.v
    ├── fpga_regs.h
    ├── fusb.cpp
    ├── fusb.h
    ├── i2c.h
    ├── ids.h
    ├── inband-signaling-usb
    ├── interfaces.h
    ├── pulseApproximate.m
    ├── radioDevice.h
    ├── radioInterface.cpp
    ├── radioInterface.h
    ├── rnrad1.h
    ├── rnrad1Core.cpp
    ├── rnrad1Core.h
    ├── rnrad1Rx.cpp
    ├── rnrad1Tx.cpp
    ├── runTransceiver.cpp
    ├── sigProcLib.cpp
    ├── sigProcLib.h
    ├── sigProcLibTest.cpp
    └── spi.h
├── apps
    ├── .gdbinit
    ├── CLI
    ├── GetConfigurationKeys.cpp
    ├── JSONEventsClient.cpp
    ├── Makefile.am
    ├── OpenBTS.cpp
    ├── OpenBTS.example.sql
    ├── OpenBTSCLI.cpp
    ├── OpenBTSConfig.h
    ├── OpenBTSDo
    ├── exportConfigTable.sh
    ├── generateConfigTable.sh
    ├── generateTeX.sh
    ├── importConfigTable.sh
    ├── iptables.rules
    ├── logrotated.OpenBTS
    ├── openbts.conf
    ├── openbtsconfig
    └── rsyslogd.OpenBTS.conf
├── autogen.sh
├── config
    ├── Makefile.am
    ├── ax_check_compile_flag.m4
    ├── ax_ext.m4
    ├── ax_gcc_x86_avx_xgetbv.m4
    ├── ax_gcc_x86_cpuid.m4
    ├── pkg.m4
    └── test_ortp_version.cpp
├── configure.ac
├── ctags.sh
├── debian
    ├── changelog
    ├── compat
    ├── control
    ├── postinst
    ├── postrm
    ├── preinst
    ├── prerm
    └── rules
├── doc
    ├── CodingStandard
    └── Makefile.am
├── package
    ├── deb-after-install.sh
    ├── deb-before-install.sh
    ├── rpm-after-install.sh
    └── rpm-before-install.sh
└── tools
    ├── Makefile.am
    ├── Makefile.standalone
    ├── README
    ├── hata.cpp
    └── translateConfig.py


/.gitignore:
--------------------------------------------------------------------------------
 1 | ._*
 2 | *.in
 3 | .deps
 4 | .libs
 5 | *.o
 6 | *.lo
 7 | *.la
 8 | Makefile
 9 | aclocal.m4
10 | autom4te.cache
11 | build-arch-stamp
12 | build-indep-stamp
13 | compile
14 | config/test_ortp_version
15 | config.guess
16 | config.h
17 | config.log
18 | config.status
19 | config.sub
20 | config/libtool.m4
21 | config/ltoptions.m4
22 | config/ltsugar.m4
23 | config/ltversion.m4
24 | config/lt~obsolete.m4
25 | configure
26 | configure-stamp
27 | debian/debhelper.log
28 | depcomp
29 | install-sh
30 | libtool
31 | ltmain.sh
32 | missing
33 | stamp-h1
34 | Transceiver52M/transceiver
35 | TransceiverRAD1/RAD1Cmd
36 | TransceiverRAD1/RAD1RxRawPower
37 | TransceiverRAD1/RAD1RxRawPowerSweep
38 | TransceiverRAD1/RAD1SN
39 | TransceiverRAD1/RAD1ping
40 | TransceiverRAD1/sigProcLibTest
41 | TransceiverRAD1/transceiver
42 | apps/OpenBTS
43 | apps/OpenBTSCLI
44 | apps/JSONEventsClient
45 | GSMShare/A51Test
46 | GSMShare/AMRTest
47 | GSMShare/ViterbiTest
48 | TransceiverRAD1/PowerScanner
49 | debian/files
50 | debian/substvars
51 | debian/openbts*
52 | 


--------------------------------------------------------------------------------
/.gitmodules:
--------------------------------------------------------------------------------
1 | [submodule "CommonLibs"]
2 | 	path = CommonLibs
3 | 	url = https://github.com/RangeNetworks/CommonLibs.git
4 | 	branch = master
5 | [submodule "NodeManager"]
6 | 	path = NodeManager
7 | 	url = https://github.com/RangeNetworks/NodeManager.git
8 | 	branch = master
9 | 


--------------------------------------------------------------------------------
/.travis.yml:
--------------------------------------------------------------------------------
 1 | language: cpp
 2 | compiler: gcc
 3 | 
 4 | notifications:
 5 |   irc:
 6 |     channels:
 7 |       - "chat.freenode.net#openbts"
 8 |     template:
 9 |       - "%{repository} : %{message} : %{build_url}"
10 |     on_success: change
11 |     on_failure: always
12 | 
13 | git:
14 |   submodules: false
15 | 
16 | before_install:
17 |  - sudo apt-get update 
18 |  - sudo apt-get install -qq libortp-dev libusb-1.0-0-dev libreadline-dev
19 |  - git clone https://github.com/RangeNetworks/liba53.git
20 |  - cd liba53
21 |  - dpkg-buildpackage -us -uc
22 |  - cd ..
23 |  - sudo dpkg -i liba53*.deb 
24 |  - git clone https://github.com/RangeNetworks/libcoredumper.git
25 |  - cd libcoredumper
26 |  - ./build.sh
27 |  - sudo dpkg -i *.deb
28 |  - cd ..
29 |  - git submodule update --init --recursive
30 |  - sudo ./NodeManager/install_libzmq.sh
31 | 
32 | #install:
33 | #  - sh bootstrap.sh
34 | 
35 | script:
36 |   - dpkg-buildpackage -us -uc
37 | 
38 | 


--------------------------------------------------------------------------------
/CLI/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2009 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | EXTRA_DIST = \
25 | 	README.CLI 
26 | 
27 | # AM_CXXFLAGS = -Wall
28 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
29 | 
30 | noinst_LTLIBRARIES = libcli.la
31 | 
32 | libcli_la_SOURCES = \
33 | 	CLIServer.cpp \
34 | 	CLICommands.cpp \
35 | 	CLIBase.cpp \
36 | 	CLI.cpp
37 | 
38 | noinst_HEADERS = \
39 | 	CLI.h
40 | 


--------------------------------------------------------------------------------
/CLI/README.CLI:
--------------------------------------------------------------------------------
1 | This is the directory for the OpenBTS command line interface.
2 | 
3 | 


--------------------------------------------------------------------------------
/ChangeLog:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/RangeNetworks/openbts/7766ef94f2d885c197430e74a89f02740f0c04e6/ChangeLog


--------------------------------------------------------------------------------
/Control/L3CallControl.h:
--------------------------------------------------------------------------------
 1 | /* 
 2 | * Copyright 2013, 2014 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses;
 5 | * see the COPYING file in the main directory for licensing
 6 | * information for this specific distribution.
 7 | *
 8 | * This use of this software may be subject to additional restrictions.
 9 | * See the LEGAL file in the main directory for details.
10 | 
11 |     This program is distributed in the hope that it will be useful,
12 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
13 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 | */
15 | 
16 | #ifndef _L3CALLCONTROL_H_
17 | #define _L3CALLCONTROL_H_ 1
18 | 
19 | #include "L3StateMachine.h"
20 | #include <GSMCommon.h>
21 | #include <GSML3Message.h>
22 | 
23 | namespace Control {
24 | void startMOC(const GSM::L3MMMessage *l3msg, MMContext *dcch, L3CMServiceType::TypeCode serviceType);
25 | void initMTC(TranEntry *tran);
26 | void startInboundHandoverMachine(TranEntry *tran);
27 | 
28 | };	// namespace
29 | 
30 | #endif
31 | 


--------------------------------------------------------------------------------
/Control/L3Handover.h:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2014 Range Networks, Inc.
 3 | *
 4 | 
 5 |     This program is distributed in the hope that it will be useful,
 6 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
 7 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 8 | 
 9 | * This software is distributed under multiple licenses;
10 | * see the COPYING file in the main directory for licensing
11 | * information for this specific distribution.
12 | *
13 | * This use of this software may be subject to additional restrictions.
14 | * See the LEGAL file in the main directory for details.
15 | */
16 | 
17 | #ifndef L3HANDOVER_H
18 | #define L3HANDOVER_H
19 | 
20 | namespace GSM {
21 | 	class L3MeasurementResults;
22 | 	class SACCHLogicalChannel;
23 | };
24 | 
25 | namespace Control {
26 | 	class L3LogicalChannel;
27 | 	class TranEntry;
28 | 
29 | void ProcessHandoverAccess(L3LogicalChannel *chan);
30 | bool outboundHandoverTransfer(TranEntry* transaction, L3LogicalChannel *TCH);
31 | void HandoverDetermination(const GSM::L3MeasurementResults* measurements, GSM::SACCHLogicalChannel* sacch);
32 | };
33 | #endif
34 | 


--------------------------------------------------------------------------------
/Control/L3SMSControl.h:
--------------------------------------------------------------------------------
 1 | /* 
 2 | * Copyright 2013, 2014 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses;
 5 | * see the COPYING file in the main directory for licensing
 6 | * information for this specific distribution.
 7 | *
 8 | * This use of this software may be subject to additional restrictions.
 9 | * See the LEGAL file in the main directory for details.
10 | 
11 |     This program is distributed in the hope that it will be useful,
12 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
13 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 | */
15 | 
16 | #ifndef _L3SMSCONTROL_H_
17 | #define _L3SMSCONTROL_H_
18 | 
19 | #include "L3LogicalChannel.h"
20 | #include "ControlCommon.h"
21 | 
22 | namespace Control {
23 | 
24 | // 3GPP 4.11 5.2. These are the SMS states.  It is nearly empty.  The only one we care about is awaiting the final ack.
25 | enum SmsState {
26 | 	SmsNonexistent,	// Not an SMS state; we use to mean there is no SMS transaction.
27 | 	MoSmsIdle,
28 | 	MoSmsWaitForAck,
29 | 	// In the spec this is a catch-all for any other state.  For us this is a transitory state we dont care about because
30 | 	// the TranEntry will be removed momentarily.
31 | 	MoSmsMMConnection,
32 | };
33 | 
34 | void startMOSMS(const GSM::L3MMMessage *l3msg, MMContext *dcch);
35 | void initMTSMS(TranEntry *tran);
36 | 
37 | };
38 | #endif
39 | 


--------------------------------------------------------------------------------
/Control/L3SupServ.h:
--------------------------------------------------------------------------------
 1 | /* 
 2 | * Copyright 2013, 2014 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses;
 5 | * see the COPYING file in the main directory for licensing
 6 | * information for this specific distribution.
 7 | *
 8 | * This use of this software may be subject to additional restrictions.
 9 | * See the LEGAL file in the main directory for details.
10 | 
11 |     This program is distributed in the hope that it will be useful,
12 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
13 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 | */
15 | 
16 | #ifndef _L3SUPSERV_H_
17 | #define _L3SUPSERV_H_ 1
18 | 
19 | 
20 | #include "ControlCommon.h"
21 | #include "L3StateMachine.h"
22 | #include <GSML3MMMessages.h>
23 | 
24 | namespace Control {
25 | 
26 | // The base class for SS [Supplementary Services]
27 | class SSDBase : public MachineBase {
28 | 	protected:
29 | 	MachineStatus handleSSMessage(const GSM::L3Message*ssmsg);
30 | 	SSDBase(TranEntry *wTran) : MachineBase(wTran) {}
31 | };
32 | 
33 | void startMOSSD(const GSM::L3CMServiceRequest*cmsrq, MMContext *mmchan);
34 | string ssMap2Ussd(const unsigned char *mapcmd,unsigned maplen);
35 | 
36 | };
37 | #endif
38 | 


--------------------------------------------------------------------------------
/Control/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2010 Kestrel Signal Processing, Inc.
 4 | # Copyright 2011, 2014 Range Networks, Inc.
 5 | #
 6 | # This software is distributed under the terms of the GNU Public License.
 7 | # See the COPYING file in the main directory for details.
 8 | #
 9 | # This program is free software: you can redistribute it and/or modify
10 | # it under the terms of the GNU General Public License as published by
11 | # the Free Software Foundation, either version 3 of the License, or
12 | # (at your option) any later version.
13 | #
14 | # This program is distributed in the hope that it will be useful,
15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 | # GNU General Public License for more details.
18 | #
19 | # You should have received a copy of the GNU General Public License
20 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
21 | #
22 | 
23 | include $(top_srcdir)/Makefile.common
24 | 
25 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
26 | # AM_CXXFLAGS = -Wall
27 | 
28 | EXTRA_DIST = README.Control
29 | 
30 | noinst_LTLIBRARIES = libcontrol.la
31 | 
32 | 
33 | # L3CallControl.cpp
34 | libcontrol_la_SOURCES = \
35 | 	L3TermCause.cpp \
36 | 	L3CallControl.cpp \
37 | 	PagingEntry.cpp \
38 | 	L3Handover.cpp \
39 | 	L3SMSControl.cpp \
40 | 	L3MobilityManagement.cpp \
41 | 	L3StateMachine.cpp \
42 | 	L3SupServ.cpp \
43 | 	L3MMLayer.cpp \
44 | 	L3TranEntry.cpp \
45 | 	L3LogicalChannel.cpp \
46 | 	L3Utils.cpp \
47 | 	TMSITable.cpp \
48 | 	ControlTransfer.cpp \
49 | 	DCCHDispatch.cpp \
50 | 	CBS.cpp \
51 | 	RRLPServer.cpp
52 | 
53 | 
54 | # TODO - move CollectMSInfo.cpp and RRLPQueryController.cpp to RRLP directory.
55 | 
56 | noinst_HEADERS = \
57 | 	L3TermCause.h \
58 | 	CodecSet.h \
59 | 	PagingEntry.h \
60 | 	L3Handover.h \
61 | 	L3SMSControl.h \
62 | 	L3CallControl.h \
63 | 	L3MobilityManagement.h \
64 | 	L3StateMachine.h \
65 | 	L3SupServ.h \
66 | 	L3MMLayer.h \
67 | 	L3TranEntry.h \
68 | 	L3LogicalChannel.h \
69 | 	L3Utils.h \
70 | 	ControlCommon.h \
71 | 	ControlTransfer.h \
72 | 	TMSITable.h \
73 | 	TMSITable.h \
74 | 	CBS.h \
75 | 	RRLPServer.h
76 | 


--------------------------------------------------------------------------------
/Control/README.Control:
--------------------------------------------------------------------------------
 1 | This directory contains control-layer functions for the access point.
 2 | 
 3 | Most GSM L3 and VoIP messages terminate here.
 4 | 
 5 | Everything in this directory should be in the Control namespace.
 6 | 
 7 | Components:
 8 | 
 9 | RadioResource -- Functions for RR procedures (paging, access grant)
10 | MobilityManagement -- Functions for MM procedures (CM service, location updating)
11 | CallControl -- Functions for CC (mobile originated, mobile terminated)
12 | SMS -- Funcitons for text messaging.
13 | 
14 | 
15 | 
16 | SIP and RTP UDP/IP Port Assignments
17 | 
18 | Component	Protocol	Port(s)
19 | Asterisk	SIP		5060
20 | Zoiper		SIP		5061
21 | AP/BTS		SIP		5062
22 | Zoiper		RTP		16384-16385
23 | Asterisk	RTP		16386-16483
24 | AP/BTS		RTP		16484-16583
25 | 
26 | 


--------------------------------------------------------------------------------
/Control/RRLPServer.cpp:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/RangeNetworks/openbts/7766ef94f2d885c197430e74a89f02740f0c04e6/Control/RRLPServer.cpp


--------------------------------------------------------------------------------
/Control/RRLPServer.h:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/RangeNetworks/openbts/7766ef94f2d885c197430e74a89f02740f0c04e6/Control/RRLPServer.h


--------------------------------------------------------------------------------
/Control/RRLP_PDU_Test.cpp:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2014 Range Networks, Inc.
 3 | *
 4 |     This program is distributed in the hope that it will be useful,
 5 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
 6 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 7 | 
 8 | * This software is distributed under multiple licenses;
 9 | * see the COPYING file in the main directory for licensing
10 | * information for this specific distribution.
11 | *
12 | * This use of this software may be subject to additional restrictions.
13 | * See the LEGAL file in the main directory for details.
14 | */
15 | 
16 | #include "Configuration.h"
17 | #include "RRLPQueryController.h"
18 | 
19 | using namespace GSM;
20 | using namespace GSM::RRLP;
21 | 
22 | // compile one liner:
23 | // g++ -DRRLP_TEST_HACK -L../GSM/.libs -L../CommonLibs/.libs -I../CLI -I../Globals -I../GSM -I../CommonLibs RRLPQueryController.cpp RRLP_PDU_Test.cpp -lcommon -lGSM -lpthread -o RRLP_PDU_Test
24 | 
25 | // Required by various stuff - I think a TODO is to allow tests to work without
26 | // having to copy this line around.
27 | ConfigurationTable gConfig("OpenBTS.config");
28 | 
29 | int main()
30 | {
31 |     // This is a MsrPositionRsp with valid coordinates
32 |     // 38.28411340713501,237.95414686203003,22 (as parsed by the erlang automatically generated
33 |     // implementation - checked against a map).
34 |     BitVector test("0000011000111000000000000001011000100010000100011111111111111111010010101111101111011110101101100100000011010110110100111000111010100011110010010100111000000000010001000001100000011000110010000010000100010000");
35 |     RRLPQueryController c(test);
36 |     return 0;
37 | }
38 | 
39 | 


--------------------------------------------------------------------------------
/GPRS/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
25 | # CXXFLAGS = -g -O2
26 | 
27 | noinst_LTLIBRARIES = libGPRS.la
28 | 
29 | libGPRS_la_SOURCES = \
30 | 	MSInfo.cpp \
31 | 	RLCEngine.cpp \
32 | 	TBF.cpp \
33 | 	MAC.cpp \
34 | 	FEC.cpp \
35 | 	RLCEngine.cpp \
36 | 	RLCMessages.cpp \
37 | 	ByteVector.cpp \
38 | 	GPRSCLI.cpp \
39 | 	RLC.cpp \
40 | 	MsgBase.cpp
41 | #BSSGMessages.cpp
42 | #BSSG.cpp
43 | 
44 | noinst_HEADERS = \
45 | 	ByteVector.h \
46 | 	FEC.h \
47 | 	GPRSExport.h \
48 | 	GPRSInternal.h \
49 | 	GPRSTDMA.h \
50 | 	MAC.h \
51 | 	MsgBase.h \
52 | 	GPRSRLC.h \
53 | 	RLCEngine.h \
54 | 	RLCHdr.h \
55 | 	RLCMessages.h \
56 | 	RList.h \
57 | 	ScalarTypes.h \
58 | 	TBF.h \
59 | 	MSInfo.h
60 | #	BSSG.h
61 | #	BSSGMessages.h
62 | 


--------------------------------------------------------------------------------
/GPRS/makefile.tests:
--------------------------------------------------------------------------------
 1 | HDR=BSSG.h BSSGMessages.h ByteVector.h FEC.h GPRSExport.h GPRSInternal.h \
 2 | 	GPRSTDMA.h MAC.h MsgBase.h RLCEngine.h RLCHdr.h RLCMessages.h RList.h \
 3 | 	ScalarTypes.h TBF.h Transfer.h Utils.h
 4 | #HDR= Utils.h BSSG.h BSSGMessages.h FEC.h GPRSExport.h GPRSInternal.h \
 5 | #	GPRSTDMA.h MAC.h RLCEngine.h RLCHdr.h RLCMessages.h TBF.h Transfer.h Utils.h BaseTypes.h
 6 | SRC= GPRSConfig.cpp TBF.cpp RLCMessages.cpp BSSG.cpp BSSGMessages.cpp ByteVector.cpp FEC.cpp MAC.cpp MsgBase.cpp \
 7 | 	RLCEngine.cpp Transfer.cpp Utils.cpp
 8 | 
 9 | INCLUDE= -I. -I..  -I../CommonLibs -I../Control -I../GPRS -I../GSM -I../SIP -I../SMS -I../TRXManager -I../Globals -I../CLI -I../HLR -I../SR -I../sqlite3
10 | 
11 | ODIR=.libs
12 | 
13 | OBJ= $(SRC:%.cpp=$(ODIR)/%.o)
14 | 
15 | 
16 | all: lib
17 | 
18 | test1: test1.cpp Makefile libGPRS.a
19 | 	g++ $(INCLUDE) -o test1 test1.cpp libGPRS.a ../CommonLibs/.libs/libcommon.a
20 | 
21 | test2: test1.cpp Makefile libGPRS.a
22 | 	g++ $(INCLUDE) -o test1 test1.cpp libGPRS.a ../CommonLibs/.libs/libcommon.a ../GSM/.libs/libGSM.a
23 | 
24 | lib: $(OBJ)
25 | 	ar cru $(ODIR)/libGPRS.a $(OBJ)
26 | 	touch libGPRS.la
27 | 
28 | #.cpp.o:
29 | $(ODIR)/%.o: %.cpp
30 | 	-mkdir o 2>/dev/null
31 | 	g++ -DHAVE_CONFIG_H -I. -I. -I..  -I../CommonLibs -I../Control -I../GPRS -I../GSM -I../SIP -I../SMS -I../TRXManager -I../Globals -I../CLI -I../HLR -I../SR -I../sqlite3  -Wall -g -c -o $(ODIR)/$*.o $*.cpp
32 | 
33 | 
34 | 
35 | 
36 | # g++ -DHAVE_CONFIG_H -I. -I. -I..  -I../CommonLibs -I../Control -I../GPRS -I../GSM -I../SIP -I../SMS -I../TRXManager -I../Globals -I../CLI -I../HLR -I../SR -I../sqlite3  -Wall -O3 -g -O2 -MT RadioResource.lo -MD -MP -MF ".deps/RadioResource.Tpo" -c -o RadioResource.lo RadioResource.cpp; \
37 | 		        then mv -f ".deps/RadioResource.Tpo" ".deps/RadioResource.Plo"; else rm -f ".deps/RadioResource.Tpo"; exit 1; fi
38 | 
39 | $(OBJ):$(HDR)
40 | 
41 | svnadd:
42 | 	svn add $(HDR) $(SRC)
43 | 
44 | clean:
45 | 	/bin/rm $(ODIR)/*
46 | 
47 | commit:
48 | 	svn commit $(HDR) $(SRC)
49 | 
50 | ping: ping.o
51 | 	gcc -o ping ping.c
52 | 
53 | pinghttp: pinghttp.c iputils.c makefile.tests
54 | 	gcc -DSTANDALONE=1 -o pinghttp $(CFLAGS) pinghttp.c iputils.c
55 | 
56 | 
57 | tags: .ALWAYS
58 | 	cd ..; sh PAT.ctags
59 | 
60 | .ALWAYS:
61 | 


--------------------------------------------------------------------------------
/GSM/AppInfTest.cpp:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2011, 2014 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses;
 5 | * see the COPYING file in the main directory for licensing
 6 | * information for this specific distribution.
 7 | *
 8 | * This use of this software may be subject to additional restrictions.
 9 | * See the LEGAL file in the main directory for details.
10 | 
11 |     This program is distributed in the hope that it will be useful,
12 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
13 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 | */
15 | 
16 | #define LOG_GROUP LogGroup::GSM		// Can set Log.Level.GSM for debugging
17 | 
18 | #include <iostream>
19 | 
20 | #include <GSML3RRMessages.h>
21 | #include <GSMTransfer.h>
22 | 
23 | // Load configuration from a file.
24 | ConfigurationTable gConfig("OpenBTS.config");
25 | 
26 | int main()
27 | {
28 |     GSM::L3ApplicationInformation ai();
29 |     static const char init_request_msbased_gps[4] = {'@', '\x01', 'x', '\xa8'}; // pre encoded PER for the following XER:
30 |     static std::vector<char> request_msbased_gps(init_request_msbased_gps,
31 |         init_request_msbased_gps + sizeof(init_request_msbased_gps));
32 |     GSM::L3ApplicationInformation ai2(request_msbased_gps);
33 | 
34 |     GSM::L3Frame f(ai2);
35 |     std::cout << f;
36 | 
37 |     return 0;
38 | }
39 | 
40 | 


--------------------------------------------------------------------------------
/GSM/GSM610Tables.h:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2008 Free Software Foundation, Inc.
 3 | * Copyright 2014 Range Networks, Inc.
 4 | *
 5 | * This software is distributed under multiple licenses; see the COPYING file in the main directory for licensing information for this specific distribution.
 6 | *
 7 | * This use of this software may be subject to additional restrictions.
 8 | * See the LEGAL file in the main directory for details.
 9 | 
10 |     This program is distributed in the hope that it will be useful,
11 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
12 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 | 
14 | */
15 | 
16 | 
17 | 
18 | #ifndef GSM610TABLES_H
19 | #define GSM610TABLES_H
20 | 
21 | 
22 | 
23 | namespace GSM {
24 | 
25 | /** Table #2 from GSM 05.03 */
26 | extern const unsigned int g610BitOrder[260];
27 | 
28 | }
29 | 
30 | 
31 | #endif
32 | 


--------------------------------------------------------------------------------
/GSM/GSMTAPDump.h:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2008, 2009 Free Software Foundation, Inc.
 3 | * Copyright 2014 Range Networks, Inc.
 4 | *
 5 | * This software is distributed under multiple licenses; see the COPYING file in the main directory for licensing information for this specific distribution.
 6 | *
 7 |     This program is distributed in the hope that it will be useful,
 8 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
 9 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
10 | 
11 | *
12 | * This use of this software may be subject to additional restrictions.
13 | * See the LEGAL file in the main directory for details.
14 | 
15 | */
16 | 
17 | 
18 | 
19 | #ifndef GSMTAPDUMP_H
20 | #define GSMTAPDUMP_H
21 | 
22 | #include "gsmtap.h"
23 | #include "GSMCommon.h"
24 | #include "GSMTransfer.h"
25 | 
26 | 
27 | void gWriteGSMTAP(unsigned ARFCN, unsigned TS, unsigned FN,
28 |                   GSM::TypeAndOffset to, bool is_sacch, bool ul_dln,
29 |                   const BitVector2& frame,
30 | 				  unsigned wType = GSMTAP_TYPE_UM);
31 | #endif
32 | 
33 | // vim: ts=4 sw=4
34 | 


--------------------------------------------------------------------------------
/GSM/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | #AM_CPPFLAGS = -Wall $(STD_DEFINES_AND_INCLUDES)
25 | #AM_CXXFLAGS = -O2 -g
26 | 
27 | noinst_LTLIBRARIES = libGSM.la
28 | 
29 | libGSM_la_SOURCES = \
30 | 	GSMChannelHistory.cpp \
31 | 	GSMCCCH.cpp \
32 | 	GSMRadioResource.cpp \
33 | 	GSML3SSMessages.cpp \
34 | 	GSM610Tables.cpp \
35 | 	GSMCommon.cpp \
36 | 	GSMConfig.cpp \
37 | 	GSML1FEC.cpp \
38 | 	GSML2LAPDm.cpp \
39 | 	GSML3CCElements.cpp \
40 | 	GSML3CCMessages.cpp \
41 | 	GSML3CommonElements.cpp \
42 | 	GSML3GPRSElements.cpp \
43 | 	GSML3Message.cpp \
44 | 	GSML3MMElements.cpp \
45 | 	GSML3MMMessages.cpp \
46 | 	GSML3RRElements.cpp \
47 | 	GSML3RRMessages.cpp \
48 | 	GSMLogicalChannel.cpp \
49 | 	GSMTDMA.cpp \
50 | 	GSMTransfer.cpp \
51 | 	GSMTAPDump.cpp \
52 | 	GSMSMSCBL3Messages.cpp \
53 | 	PowerManager.cpp\
54 | 	PhysicalStatus.cpp
55 | 
56 | noinst_HEADERS = \
57 | 	GSMChannelHistory.h \
58 | 	GSMCCCH.h \
59 | 	GSMRadioResource.h \
60 | 	GSML3SSMessages.h \
61 |  	GSM610Tables.h \
62 | 	GSMCommon.h \
63 | 	GSMConfig.h \
64 | 	GSML1FEC.h \
65 | 	GSML2LAPDm.h \
66 | 	GSML3CCElements.h \
67 | 	GSML3CCMessages.h \
68 | 	GSML3CommonElements.h \
69 | 	GSML3GPRSElements.h \
70 | 	GSML3Message.h \
71 | 	GSML3MMElements.h \
72 | 	GSML3MMMessages.h \
73 | 	GSML3RRElements.h \
74 | 	GSML3RRMessages.h \
75 | 	GSMLogicalChannel.h \
76 | 	GSMTDMA.h \
77 | 	GSMTransfer.h \
78 | 	PowerManager.h \
79 | 	GSMTAPDump.h \
80 | 	GSMSMSCBL3Messages.h \
81 | 	gsmtap.h \
82 | 	PhysicalStatus.h
83 | 
84 | 


--------------------------------------------------------------------------------
/GSM/PhysicalStatus.h:
--------------------------------------------------------------------------------
 1 | /**@file Declarations for PhysicalStatus and related classes. */
 2 | /*
 3 | * Copyright 2010 Kestrel Signal Processing, Inc.
 4 | * Copyright 2011, 2014 Range Networks, Inc.
 5 | *
 6 | * This software is distributed under multiple licenses;
 7 | * see the COPYING file in the main directory for licensing
 8 | * information for this specific distribution.
 9 | *
10 | * This use of this software may be subject to additional restrictions.
11 | * See the LEGAL file in the main directory for details.
12 | 
13 |     This program is distributed in the hope that it will be useful,
14 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
15 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 | 
17 | */
18 | 
19 | 
20 | 
21 | #ifndef PHYSICALSTATUS_H
22 | #define PHYSICALSTATUS_H
23 | 
24 | #include <map>
25 | 
26 | #include <Timeval.h>
27 | #include <Threads.h>
28 | 
29 | 
30 | struct sqlite3;
31 | 
32 | 
33 | namespace GSM {
34 | 
35 | class L3MeasurementResults;
36 | class SACCHLogicalChannel;
37 | 
38 | /**
39 | 	A table for tracking the state of channels.
40 | */
41 | class PhysicalStatus {
42 | 
43 | private:
44 | 
45 | 	Mutex mLock;		///< to reduce the load on the filesystem locking
46 | 	sqlite3 *mDB;		///< database connection
47 | 
48 | public:
49 | 
50 | 	/**
51 | 		Initialize a physical status reporting table.
52 | 		@param path Path fto sqlite3 database file.
53 | 		@return 0 if the database was successfully opened and initialized; 1 otherwise
54 | 	*/
55 | 	int open(const char*wPath);
56 | 
57 | 	~PhysicalStatus();
58 | 
59 | 	/** 
60 | 		Add reporting information associated with a channel to the table.
61 | 		@param chan The channel to report.
62 | 		@param measResults The measurement report.
63 | 		@return The result of the SQLite query: true for the query being executed successfully, false otherwise.
64 | 	*/
65 | 	bool setPhysical(const SACCHLogicalChannel* chan, const L3MeasurementResults& measResults);
66 | 
67 | 	/**
68 | 		Dump the physical status table to the output stream.
69 | 		@param os The output stream to dump the channel information to.
70 | 	*/
71 | //	void dump(std::ostream& os) const;
72 | 
73 | 	private:
74 | 
75 | 	/** 
76 | 		Create entry in table. This is for the initial creation.
77 | 		@param chan The channel to create an entry for.
78 | 		@return The result of the SQLite query: true for the query being executed successfully, false otherwise.
79 | 	*/
80 | 	bool createEntry(const SACCHLogicalChannel* chan);
81 | 
82 | 
83 | };
84 | 
85 | 
86 | }
87 | 
88 | #endif
89 | 
90 | // vim: ts=4 sw=4
91 | 


--------------------------------------------------------------------------------
/GSM/PowerManager.cpp:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2009 Free Software Foundation, Inc.
 3 | * Copyright 2014 Range Networks, Inc.
 4 | *
 5 | * This software is distributed under multiple licenses; see the COPYING file in the main directory for licensing information for this specific distribution.
 6 | *
 7 | * This use of this software may be subject to additional restrictions.
 8 | * See the LEGAL file in the main directory for details.
 9 | 
10 |     This program is distributed in the hope that it will be useful,
11 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
12 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 | 
14 | */
15 | 
16 | #include "PowerManager.h"
17 | #include <Logger.h>
18 | #include <OpenBTSConfig.h>
19 | #include <GSMConfig.h>
20 | #include <TRXManager.h>
21 | #include <ControlCommon.h>
22 | 
23 | #define LOG_GROUP LogGroup::GSM		// Can set Log.Level.GSM for debugging
24 | 
25 | extern TransceiverManager gTRX;
26 | 
27 | namespace GSM {
28 | 
29 | PowerManager gPowerManager;
30 | 
31 | 
32 | void PowerManager::pmSetAttenDirect(int atten)
33 | {
34 | 	mRadio->setPower(atten);
35 | 	mAtten = atten;
36 | 	LOG(INFO) << "setting power to -" << mAtten << " dB at uptime="<<gBTS.uptime();
37 | }
38 | 
39 | void PowerManager::pmSetAtten(int atten)
40 | {
41 | 	if (atten != mAtten) { pmSetAttenDirect(atten); }
42 | }
43 | 
44 | 
45 | 
46 | void PowerManager::pmStart()
47 | {
48 | 	LOG(INFO);
49 | 	mRadio = gTRX.ARFCN(0);
50 | 	pmSetAttenDirect(gConfig.getNum("GSM.Radio.PowerManager.MaxAttenDB"));
51 | }
52 | 
53 | };
54 | 
55 | // vim: ts=4 sw=4
56 | 


--------------------------------------------------------------------------------
/GSM/PowerManager.h:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2009 Free Software Foundation, Inc.
 3 | * Copyright 2014 Range Networks, Inc.
 4 | *
 5 | * This software is distributed under multiple licenses; see the COPYING file in the main directory for licensing information for this specific distribution.
 6 | *
 7 | * This use of this software may be subject to additional restrictions.
 8 | * See the LEGAL file in the main directory for details.
 9 | 
10 |     This program is distributed in the hope that it will be useful,
11 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
12 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 | 
14 | */
15 | 
16 | #ifndef __POWER_CONTROL__
17 | #define __POWER_CONTROL__
18 | 
19 | #include <iostream>
20 | 
21 | #include <Timeval.h>
22 | #include <Threads.h>
23 | 
24 | // forward declaration
25 | //class Timeval;
26 | 
27 | // Make it all inline for now - no change to automake
28 | 
29 | class ARFCNManager;
30 | 
31 | 
32 | namespace GSM {
33 | 
34 | 
35 | class PowerManager {
36 | 
37 |   private:
38 | 	ARFCNManager* mRadio;
39 | 	volatile int mAtten;	///< current attenuation.
40 | 	void pmSetAttenDirect(int atten);
41 | 
42 |   public:
43 | 	PowerManager() : mAtten(-9999) {}
44 | 	void pmStart();
45 | 	void pmSetAtten(int atten);
46 | 	int power() { return -mAtten; }
47 | };
48 | 
49 | extern PowerManager gPowerManager;
50 | 
51 | 
52 | }	// namespace GSM
53 | 
54 | 
55 | #endif // __POWER_CONTROL__
56 | 
57 | // vim: ts=4 sw=4
58 | 


--------------------------------------------------------------------------------
/GSMShare/A51.h:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | #include <stdio.h>
 4 | #include <stdlib.h>
 5 | 
 6 | typedef unsigned char byte;
 7 | typedef unsigned long word;
 8 | typedef word bit;
 9 | 
10 | void A51_GSM( byte *key, int klen, int count, byte *block1, byte *block2 );
11 | 
12 | 


--------------------------------------------------------------------------------
/GSMShare/GSM503Tables.h:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2012, 2014 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses; see the COPYING file in the main directory for licensing information for this specific distribution.
 5 | *
 6 | * This use of this software may be subject to additional restrictions.
 7 | * See the LEGAL file in the main directory for details.
 8 | 
 9 |     This program is distributed in the hope that it will be useful,
10 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
11 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 | 
13 | */
14 | 
15 | 
16 | 
17 | #ifndef GSM503TABLES_H
18 | #define GSM503TABLES_H
19 | 
20 | 
21 | 
22 | namespace GSM {
23 | 
24 | // don't change the positions in this enum
25 | // (pat) The first 8 values are used as indicies into numerous tables.
26 | // (pat) Encoder/decoder mode includes 8 modes for AMR + TCH_FS makes 9.
27 | // TODO: Add AFS_SID type.  And why is it not type 8?
28 | enum AMRMode {TCH_AFS12_2, TCH_AFS10_2, TCH_AFS7_95, TCH_AFS7_4, TCH_AFS6_7, TCH_AFS5_9, TCH_AFS5_15, TCH_AFS4_75, TCH_FS};
29 | 
30 | /** Tables #7-14 from GSM 05.03 */
31 | extern const unsigned int gAMRBitOrderTCH_AFS12_2[244];
32 | extern const unsigned int gAMRBitOrderTCH_AFS10_2[204];
33 | extern const unsigned int gAMRBitOrderTCH_AFS7_95[159];
34 | extern const unsigned int gAMRBitOrderTCH_AFS7_4[148];
35 | extern const unsigned int gAMRBitOrderTCH_AFS6_7[134];
36 | extern const unsigned int gAMRBitOrderTCH_AFS5_9[118];
37 | extern const unsigned int gAMRBitOrderTCH_AFS5_15[103];
38 | extern const unsigned int gAMRBitOrderTCH_AFS4_75[95];
39 | 
40 | /** GSM 05.03 3.9.4.4 */
41 | extern const unsigned int gAMRPuncturedTCH_AFS12_2[60];
42 | extern const unsigned int gAMRPuncturedTCH_AFS10_2[194];
43 | extern const unsigned int gAMRPuncturedTCH_AFS7_95[65];
44 | extern const unsigned int gAMRPuncturedTCH_AFS7_4[26];
45 | extern const unsigned int gAMRPuncturedTCH_AFS6_7[128];
46 | extern const unsigned int gAMRPuncturedTCH_AFS5_9[72];
47 | extern const unsigned int gAMRPuncturedTCH_AFS5_15[117];
48 | extern const unsigned int gAMRPuncturedTCH_AFS4_75[87];
49 | 
50 | /* GSM 05.03 Tables 7-14 */
51 | extern const unsigned *gAMRBitOrder[8];
52 | 
53 | /* GSM 05.03 3.9.4.2 */
54 | extern const unsigned gAMRKd[9];
55 | 
56 | /* GSM 05.03 3.9.4.2 */
57 | extern const unsigned gAMRClass1ALth[8];
58 | 
59 | /* GSM 05.03 3.9.4.4 */
60 | extern const unsigned gAMRTCHUCLth[8];
61 | 
62 | /* GSM 05.03 3.9.4.2 */
63 | extern const unsigned gAMRPunctureLth[8];
64 | 
65 | /* GSM 05.03 3.9.4.4 */
66 | extern const unsigned *gAMRPuncture[8];
67 | 
68 | }
69 | 
70 | 
71 | #endif
72 | 


--------------------------------------------------------------------------------
/GSMShare/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008, 2009 Free Software Foundation, Inc.
 3 | # Copyright 2011, 2012, 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | noinst_LTLIBRARIES = libGSMShare.la
25 | 
26 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
27 | # AM_CXXFLAGS = -Wall -O3 -g -ldl -lpthread
28 | libGSMShare_la_CXXFLAGS = $(AM_CXXFLAGS) -O3
29 | libGSMShare_la_SOURCES = \
30 | 	L3Enums.cpp \
31 | 	AmrCoder.cpp \
32 | 	GSM503Tables.cpp \
33 | 	ViterbiR204.cpp \
34 | 	A51.cpp
35 | 
36 | noinst_PROGRAMS = \
37 | 	ViterbiTest \
38 | 	AMRTest \
39 | 	A51Test
40 | 
41 | #	ReportingTest 
42 | 
43 | noinst_HEADERS = \
44 | 	L3Enums.h \
45 | 	Viterbi.h \
46 | 	ViterbiR204.h \
47 | 	AmrCoder.h \
48 | 	ViterbiR204.h \
49 | 	GSM503Tables.h \
50 | 	A51.h
51 | 
52 | ViterbiTest_SOURCES = ViterbiTest.cpp
53 | ViterbiTest_LDADD = \
54 | 	$(GLOBALS_LA) \
55 | 	$(noinst_LTLIBRARIES) \
56 | 	$(GSM_LA) \
57 | 	$(COMMON_LA) \
58 | 	$(SQLITE_LA)
59 | 	
60 | AMRTest_SOURCES = AMRTest.cpp
61 | AMRTest_LDADD = \
62 | 	$(GLOBALS_LA) \
63 | 	$(noinst_LTLIBRARIES) \
64 | 	$(GSM_LA) \
65 | 	$(COMMON_LA) \
66 | 	$(SQLITE_LA)
67 | 
68 | A51Test_SOURCES = A51Test.cpp
69 | A51Test_LDADD = \
70 | 	$(GLOBALS_LA) \
71 | 	$(noinst_LTLIBRARIES) \
72 | 	$(GSM_LA) \
73 | 	$(COMMON_LA) \
74 | 	$(SQLITE_LA)
75 | 


--------------------------------------------------------------------------------
/GSMShare/Viterbi.h:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2013, 2014 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses;
 5 | * see the COPYING file in the main directory for licensing
 6 | * information for this specific distribution.
 7 | *
 8 | * This use of this software may be subject to additional restrictions.
 9 | * See the LEGAL file in the main directory for details.
10 | 
11 |     This program is distributed in the hope that it will be useful,
12 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
13 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 | 
15 | */
16 | 
17 | 
18 | #ifndef _VITERBI_H_
19 | #define _VITERBI_H_ 1
20 | 
21 | // (pat) Virtual base class for Viterbi and Turbo coder/decoders.
22 | class ViterbiBase {
23 | 	public:
24 | 	virtual void encode(const BitVector &in, BitVector& target) const = 0;
25 | 	virtual void decode(const SoftVector &in, BitVector& target) = 0;
26 | 	// (pat) Return error count from most recent decoder run.
27 | 	// If you get -1 from this, the method is not defined in the Viterbi class.
28 | 	virtual int getBEC() { return -1; }
29 | 	//virtual ~ViterbiBase();   Currently None of these have destructors.
30 | 
31 | 	// These functions are logically part of the Viterbi functionality, even though they do not use any class variables.
32 | 	unsigned applyPoly(uint64_t val, uint64_t poly);
33 | 	unsigned applyPoly(uint64_t val, uint64_t poly, unsigned order);
34 | };
35 | #endif
36 | 


--------------------------------------------------------------------------------
/Globals/Globals.cpp:
--------------------------------------------------------------------------------
 1 | /**@file Global system parameters. */
 2 | /*
 3 | * Copyright 2008, 2009, 2010 Free Software Foundation, Inc.
 4 | * Copyright 2010 Kestrel Signal Processing, Inc.
 5 | * Copyright 2011-2021 Range Networks, Inc.
 6 | *
 7 | * This software is distributed under multiple licenses;
 8 | * see the COPYING file in the main directory for licensing
 9 | * information for this specific distribution.
10 | *
11 | * This use of this software may be subject to additional restrictions.
12 | * See the LEGAL file in the main directory for details.
13 | 
14 |     This program is distributed in the hope that it will be useful,
15 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 | 
18 | */
19 | 
20 | #include "config.h"
21 | #include <Globals.h>
22 | #include <CLI.h>
23 | #include <TMSITable.h>
24 | #include <URLEncode.h>
25 | 
26 | #define PROD_CAT "P"
27 | 
28 | #define FEATURES "+GPRS "
29 | 
30 | const char *gVERSION(void) { return VERSION; }
31 | const char *gFEATURES(void) { return FEATURES; }
32 | const char *gPROD_CAT(void) { return PROD_CAT; }
33 | 
34 | CommandLine::Parser gParser;
35 | 
36 | static Timeval watchdog;
37 | static bool watchdogActive = false;
38 | static Mutex watchdogLock;
39 | 
40 | void gResetWatchdog()
41 | {
42 | 	ScopedLock lock(watchdogLock);
43 | 	int value = gConfig.getNum("Control.WatchdogMinutes");
44 | 	if (value <= 0) { watchdogActive = false; }	// The stupid timer core-dumps if you call reset with a 0 value.
45 | 	else { watchdog.future(value*60*1000); }
46 | 	LOG(DEBUG) << "reset watchdog timer, expires in " << watchdog.remaining() / 1000 << " seconds";
47 | }
48 | 
49 | size_t gWatchdogRemaining()
50 | {
51 | 	// Returns remaning time in seconds.
52 | 	ScopedLock lock(watchdogLock);
53 | 	return watchdogActive ? watchdog.remaining() / 1000 : 0;
54 | }
55 | 
56 | bool gWatchdogExpired()
57 | {
58 | 	ScopedLock lock(watchdogLock);
59 | 	return watchdogActive ? watchdog.passed() : false;
60 | }
61 | 


--------------------------------------------------------------------------------
/Globals/Globals.h:
--------------------------------------------------------------------------------
 1 | /**@file Global system parameters. */
 2 | /*
 3 | * Copyright 2008, 2009 Free Software Foundation, Inc.
 4 | * Copyright 2011-2021 Range Networks, Inc.
 5 | *
 6 | * This software is distributed under multiple licenses;
 7 | * see the COPYING file in the main directory for licensing
 8 | * information for this specific distribution.
 9 | *
10 | * This use of this software may be subject to additional restrictions.
11 | * See the LEGAL file in the main directory for details.
12 | 
13 |     This program is distributed in the hope that it will be useful,
14 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
15 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 | 
17 | */
18 | 
19 | /*
20 | 	This file keeps global system parameters.
21 | */
22 | 
23 | #ifndef GLOBALS_H
24 | #define GLOBALS_H
25 | 
26 | #if !defined(BUILD_CLI)
27 | #include <GSMCommon.h>
28 | #include <OpenBTSConfig.h>
29 | #include <CLI.h>
30 | #include <PhysicalStatus.h>
31 | //#include <TMSITable.h>
32 | #include <TRXManager.h>
33 | #include <Reporting.h>
34 | 
35 | #ifndef RN_DEVERLOPER_MODE
36 | #define RN_DEVERLOPER_MODE 0
37 | #endif
38 | 
39 | #ifndef RN_DISABLE_MEMORY_LEAK_TEST
40 | #define RN_DISABLE_MEMORY_LEAK_TEST 1
41 | #endif
42 | 
43 | namespace GPRS { extern unsigned GPRSDebug; }
44 | 
45 | /** Date-and-time string, defined in OpenBTS.cpp. */
46 | extern const char* gDateTime;
47 | 
48 | /**
49 | 	Just about everything goes into the configuration table.
50 | 	This should be defined in the main body of the top-level application.
51 | */
52 | extern OpenBTSConfig gConfig;
53 | #endif // !defined(BUILD_CLI)
54 | 
55 | /** The OpenBTS welcome message. */
56 | extern const char* gOpenBTSWelcome;
57 | 
58 | /** The OpenBTS version string. */
59 | extern const char *gVersionString;
60 | 
61 | #if !defined(BUILD_CLI)
62 | /** The central parser. */
63 | extern CommandLine::Parser gParser;
64 | 
65 | /** The global TMSI table. */
66 | //extern Control::TMSITable gTMSITable;
67 | 
68 | /** The physical status reporting table */
69 | extern GSM::PhysicalStatus gPhysStatus;
70 | 
71 | /** The global transceiver interface. */
72 | extern TransceiverManager gTRX;
73 | 
74 | /** A global watchdog timer. */
75 | void gResetWatchdog();
76 | size_t gWatchdogRemaining();
77 | bool gWatchdogExpired();
78 | 
79 | extern ReportingTable gReports;
80 | 
81 | extern const char *gVERSION(void);
82 | extern const char *gFEATURES(void);
83 | extern const char *gPROD_CAT(void);
84 | #endif // !defined(BUILD_CLI)
85 | #endif
86 | 


--------------------------------------------------------------------------------
/Globals/GrabRepoInfo.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/sh
 2 | 
 3 | #
 4 | # Copyright 2014 Range Networks, Inc.
 5 | #
 6 | # This software is distributed under the terms of the GNU Public License.
 7 | # See the COPYING file in the main directory for details.
 8 | #
 9 | # This program is free software: you can redistribute it and/or modify
10 | # it under the terms of the GNU General Public License as published by
11 | # the Free Software Foundation, either version 3 of the License, or
12 | # (at your option) any later version.
13 | #
14 | # This program is distributed in the hope that it will be useful,
15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 | # GNU General Public License for more details.
18 | #
19 | # You should have received a copy of the GNU General Public License
20 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
21 | #
22 | 
23 | cd $1
24 | 
25 | INFO=""
26 | if [ -d ./.svn ]; then
27 | 	INFO="r$(svn info . | grep "Last Changed Rev:" | cut -d " " -f 4) CommonLibs:r$(svn info ./CommonLibs | grep "Last Changed Rev:" | cut -d " " -f 4)"
28 | elif [ -d ./.git ]; then
29 | 	INFO="$(git rev-parse --short=10 HEAD) CommonLibs:$(cd CommonLibs; git rev-parse --short=10 HEAD)"
30 | fi
31 | 
32 | echo $INFO
33 | 


--------------------------------------------------------------------------------
/Globals/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
25 | # AM_CXXFLAGS = -Wall
26 | 
27 | noinst_LTLIBRARIES = libglobals.la
28 | 
29 | libglobals_la_SOURCES = Globals.cpp GlobalVars.cpp
30 | 
31 | noinst_PROGRAMS = 
32 | 
33 | noinst_HEADERS = \
34 | 	Globals.h
35 | 


--------------------------------------------------------------------------------
/INSTALL:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/RangeNetworks/openbts/7766ef94f2d885c197430e74a89f02740f0c04e6/INSTALL


--------------------------------------------------------------------------------
/INSTALLATION:
--------------------------------------------------------------------------------
 1 | Installation Requirements
 2 | 
 3 | 
 4 | 
 5 | OpenBTS compiles to a simple Unix binary and does not require special
 6 | installation.
 7 | 
 8 | One some systems (Ubuntu), you will need to define LIBS = -lpthread prior to
 9 | running configure.
10 | 
11 | To run OpenBTS, the following should be installed:
12 | 
13 | 	Asterisk (http://www.asterisk.org), running SIP on port 5060.
14 | 
15 | 	libortp (http://freshmeat.net/projects/ortp/)
16 | 
17 | 	libusrp (http://gnuradio.org).
18 | 	This is part of the GNURadio installation.
19 | 	It is the only part used by OpenBTS.
20 | 
21 | 
22 | OpenBTS logs to syslogd as facility LOG_LOCAL7.  Please set your /etc/syslog.conf
23 | accordingly.
24 | 
25 | 
26 | For information on specific executables, see tests/README.tests and
27 | apps/README.apps.
28 | 
29 | See http://gnuradio.org/redmine/wiki/gnuradio/OpenBTS/BuildingAndRunning for more
30 | information.
31 | 
32 | 


--------------------------------------------------------------------------------
/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | DESTDIR ?= 
25 | 
26 | # must be kept in sync with AC_CONFIG_MACRO_DIR in configure.ac
27 | ACLOCAL_AMFLAGS = -I config
28 | 
29 | # Order must be preserved
30 | _SUBDIRS = \
31 | 	config \
32 | 	CommonLibs \
33 | 	Globals \
34 | 	SIP \
35 | 	GSM \
36 | 	SMS \
37 | 	Scanning \
38 | 	TRXManager \
39 | 	Control \
40 | 	Peering \
41 | 	NodeManager \
42 | 	GPRS \
43 | 	SGSNGGSN \
44 | 	CLI \
45 | 	GSMShare \
46 | 	apps \
47 | 	doc
48 | 
49 | #if UHD or USRP1 defined, build Transceiver52M as well
50 | if UHD
51 | SUBDIRS = $(_SUBDIRS) \
52 | 	  Transceiver52M
53 | UHD = 1
54 | else
55 | if USRP1
56 | SUBDIRS = $(_SUBDIRS) \
57 | 	  Transceiver52M
58 | USRP1 = 1
59 | else
60 | SUBDIRS = $(_SUBDIRS) \
61 | 	  TransceiverRAD1
62 | endif
63 | endif
64 | 
65 | EXTRA_DIST = \
66 | 	INSTALLATION \
67 | 	LEGAL \
68 | 	COPYING \
69 | 	README.APIs \
70 | 	README
71 | 
72 | install: all
73 | 	$(MAKE) -C ./apps install
74 | if UHD
75 | 	$(MAKE) -C ./Transceiver52M install
76 | else
77 | if USRP1
78 | 	$(MAKE) -C ./Transceiver52M install
79 | else
80 | 	$(MAKE) -C ./TransceiverRAD1 install
81 | endif
82 | endif
83 | 
84 | FORCE:
85 | 


--------------------------------------------------------------------------------
/NEWS:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/RangeNetworks/openbts/7766ef94f2d885c197430e74a89f02740f0c04e6/NEWS


--------------------------------------------------------------------------------
/Peering/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2010 Kestrel Signal Processing, Inc.
 4 | # Copyright 2011, 2014 Range Networks, Inc.
 5 | #
 6 | # This software is distributed under the terms of the GNU Public License.
 7 | # See the COPYING file in the main directory for details.
 8 | #
 9 | # This program is free software: you can redistribute it and/or modify
10 | # it under the terms of the GNU General Public License as published by
11 | # the Free Software Foundation, either version 3 of the License, or
12 | # (at your option) any later version.
13 | #
14 | # This program is distributed in the hope that it will be useful,
15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 | # GNU General Public License for more details.
18 | #
19 | # You should have received a copy of the GNU General Public License
20 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
21 | #
22 | 
23 | include $(top_srcdir)/Makefile.common
24 | 
25 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
26 | # AM_CXXFLAGS = -Wall -O3
27 | 
28 | noinst_LTLIBRARIES = libpeering.la
29 | 
30 | libpeering_la_CXXFLAGS = $(AM_CXXFLAGS) -O3
31 | libpeering_la_SOURCES = \
32 | 	NeighborTable.cpp \
33 | 	Peering.cpp
34 | 
35 | noinst_HEADERS = \
36 | 	NeighborTable.h \
37 | 	Peering.h
38 | 


--------------------------------------------------------------------------------
/README.APIs.md:
--------------------------------------------------------------------------------
 1 | # APIs in OpenBTS
 2 | 
 3 | There are going to be more and more APIs made available in OpenBTS. This is a live reference to their schemas and current versions. The Commands API is documented in the handbook in the NodeManager section. This document focuses on the the new events APIs.
 4 | 
 5 | Individual Events API can be enabled or disabled via the key listed in each section. Also, a specific version of that API can be selected for application compatibility. Events are published on the port defined by the key: ```NodeManager.Events.Port```. An example client is in apps/JSONEventsClient.cpp.
 6 | 
 7 | 
 8 | ## PhysicalStatus Events API
 9 | 
10 |  - Current Version: 0.1
11 |  - Available Versions: 0.1
12 |  - Configured Via: ```NodeManager.API.PhysicalStatus```
13 | 
14 | The PhysicalStatus API provides raw physical readings from the SACCH (Slow Associated Control CHannel). The SACCH is active when interacting with a MS (Mobile Station) via a SDCCH (Standard Dedicated Control CHannel) or a TCH (Traffic CHannel). SDCCH interactions can be SMS exchanges, LUR (Location Update Requests) or voice call setups. TCH interactions are voice calls once media is flowing or GPRS sessions.
15 | 
16 | Readings are available approximately every half-second on the SACCH. These readings contain information about the burst itself, the logical channel that is being used and neighbor reports from the handset.
17 | 
18 | An example for version 0.1 of the event data emitted by this API follows:
19 | 
20 | ```
21 | {
22 | 	"name" : "PhysicalStatus",
23 | 	"timestamp" : "18446744072283447705",
24 | 	"version" : "0.1",
25 | 	"data" : {
26 | 		"burst" : {
27 | 			"RSSI" : -49.4808,
28 | 			"RSSP" : -27.4808,
29 | 			"actualMSPower" : 11,
30 | 			"actualMSTimingAdvance" : 0,
31 | 			"timingError" : 1.59709
32 | 		},
33 | 		"channel" : {
34 | 			"ARFCN" : 153,
35 | 			"IMSI" : "001010000000001",
36 | 			"carrierNumber" : 0,
37 | 			"timeslotNumber" : 0,
38 | 			"typeAndOffset" : "SDCCH/4-1",
39 | 			"uplinkFrameErrorRate" : 0
40 | 		},
41 | 		"reports" : {
42 | 			"neighboringCells" : [],
43 | 			"servingCell" : {
44 | 				"RXLEVEL_FULL_dBm" : -67,
45 | 				"RXLEVEL_SUB_dBm" : -67,
46 | 				"RXQUALITY_FULL_BER" : 0,
47 | 				"RXQUALITY_SUB_BER" : 0
48 | 			}
49 | 		}
50 | 	}
51 | }
52 | ```
53 | 


--------------------------------------------------------------------------------
/SGSNGGSN/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
25 | #AM_CXXFLAGS = -O2 -g
26 | 
27 | noinst_LTLIBRARIES = libSGSNGGSN.la
28 | 
29 | 
30 | libSGSNGGSN_la_SOURCES = \
31 | 	Sgsn.cpp \
32 | 	Ggsn.cpp \
33 | 	GPRSL3Messages.cpp \
34 | 	iputils.cpp \
35 | 	miniggsn.cpp \
36 | 	LLC.cpp \
37 | 	SgsnCli.cpp
38 | 
39 | noinst_HEADERS = \
40 | 	Ggsn.h \
41 | 	GPRSL3Messages.h \
42 | 	LLC.h \
43 | 	miniggsn.h \
44 | 	SgsnBase.h \
45 | 	Sgsn.h
46 | 


--------------------------------------------------------------------------------
/SIP/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | # Previously: -I$(ORTP_INCLUDEDIR) $(ORTP_CPPFLAGS)
25 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
26 | # AM_CXXFLAGS = -Wall -Wextra
27 | 
28 | noinst_LTLIBRARIES = libSIP.la
29 | 
30 | libSIP_la_CXXFLAGS = $(AM_CXXFLAGS) -Wextra
31 | libSIP_la_SOURCES = \
32 | 	SIPRtp.cpp \
33 | 	SIPParse.cpp \
34 | 	SIPMessage.cpp \
35 | 	SIPDialog.cpp \
36 | 	SIP2Interface.cpp \
37 | 	SIPBase.cpp \
38 | 	SIPUtility.cpp \
39 | 	SIPTransaction.cpp
40 | 
41 | noinst_HEADERS = \
42 | 	SIPRtp.h \
43 | 	SIPParse.h \
44 | 	SIPBase.h \
45 | 	SIPDialog.h \
46 | 	SIPTransaction.h \
47 | 	SIP2Interface.h \
48 | 	SIPMessage.h \
49 | 	SIPUtility.h \
50 | 	SIPExport.h
51 | 


--------------------------------------------------------------------------------
/SMS/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
25 | # AM_CXXFLAGS = -Wall
26 | 
27 | noinst_LTLIBRARIES = libSMS.la
28 | 
29 | libSMS_la_SOURCES = \
30 | 	SMSMessages.cpp \
31 | 	SMSTransfer.cpp
32 | 
33 | noinst_HEADERS = \
34 | 	SMSMessages.h \
35 | 	SMSTransfer.h
36 | 


--------------------------------------------------------------------------------
/Scanning/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU Affero General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU Affero General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU Affero General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
25 | # AM_CXXFLAGS = -Wall
26 | 
27 | noinst_LTLIBRARIES = libscanning.la
28 | 
29 | libscanning_la_SOURCES = Scanning.cpp $(SQLITE_LA)
30 | 
31 | noinst_PROGRAMS = 
32 | 
33 | noinst_HEADERS = Scanning.h
34 | 


--------------------------------------------------------------------------------
/TRXManager/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | EXTRA_DIST = \
25 | 	README.TRXManager \
26 | 	clockdump.sh
27 | 
28 | # AM_CPPFLAGS = $(STD_DEFINES_AND_INCLUDES)
29 | # AM_CXXFLAGS = -Wall
30 | 
31 | noinst_LTLIBRARIES = libtrxmanager.la
32 | 
33 | libtrxmanager_la_SOURCES = \
34 | 	TRXManager.cpp
35 | 
36 | noinst_HEADERS = \
37 | 	TRXManager.h
38 | 


--------------------------------------------------------------------------------
/TRXManager/clockdump.sh:
--------------------------------------------------------------------------------
1 | #!/bin/sh
2 | sudo tcpdump -i lo0 -A udp port 5700
3 | 
4 | 


--------------------------------------------------------------------------------
/Transceiver52M/README:
--------------------------------------------------------------------------------
 1 | The Transceiver
 2 | 
 3 | The transceiver consists of three modules:
 4 |    --- transceiver
 5 |    --- radioInterface
 6 |    --- USRPDevice
 7 | 
 8 | The USRPDevice module is basically a driver that reads/writes
 9 | packets to a USRP with two RFX900 daughterboards, board 
10 | A is the Tx chain and board B is the Rx chain.  
11 | 
12 | The radioInterface module is basically an interface b/w the
13 | transceiver and the USRP.   It operates the basestation clock
14 | based upon the sample count of received USRP samples.  Packets 
15 | from the USRP are queued and segmented into GSM bursts that are
16 | passed up to the transceiver; bursts from the transceiver are
17 | passed down to the USRP. 
18 | 
19 | The transceiver basically operates "layer 0" of the GSM stack,
20 | performing the modulation, detection, and demodulation of GSM 
21 | bursts.  It communicates with the GSM stack via three UDP sockets,
22 | one socket for data, one for control messages, and one socket to
23 | pass clocking information.  The transceiver contains a priority
24 | queue to sort to-be-transmitted bursts, and a filler table to fill
25 | in timeslots that do not have bursts in the priority queue.  The
26 | transceiver tries to stay ahead of the basestation clock, adapting 
27 | its latency when underruns are reported by the radioInterface/USRP.
28 | Received bursts (from the radioInterface) pass through a simple 
29 | energy detector, a RACH or midamble correlator, and a DFE-based demodulator.
30 | 
31 | NOTE: There's a SWLOOPBACK #define statement, where the USRP is replaced
32 | with a memory buffer.  In this mode, data written to the USRP is actually stored 
33 | in a buffer, and read commands to the USRP simply pull data from this buffer.
34 | This was very useful in early testing, and still may be useful in testing basic
35 | Transceiver and radioInterface functionality. 
36 | 


--------------------------------------------------------------------------------
/Transceiver52M/README.DFEsymbolspaced:
--------------------------------------------------------------------------------
 1 | signalVectors G0, G1.  i.e. G0(D) = 1 +2D + 3D^2 = [1 2 3]
 2 | G0(D) = 1/sqrt(SNR).
 3 | G1(D) = [h0 h1D .. h_(N-1)D^(N-1)]
 4 | for i = 0,1,...,N_f-1,
 5 |   d = |G0(0)|^2+|G1(0)|^2
 6 |   l_i(D) = D^i ( G0(D)*G0'(0) + G1(D)*G1'(0) )/d
 7 |   k = G1(0)/G0(0) 
 8 |   G0n(D) = G0(D)+k'*G1(D)
 9 |   G1n(D) = (-G0(D)*k+G1(D))/D
10 |   G0(D) = G0n(D)/sqrt(1+k*k')
11 |   G1(D) = G1n(D)/sqrt(1+k*k')
12 | end
13 | 
14 | 
15 | 


--------------------------------------------------------------------------------
/Transceiver52M/README.Talgorithm:
--------------------------------------------------------------------------------
 1 | Basic model:
 2 | 
 3 | Have channel H = {h_0, h_1, ..., h_{K-1}}.
 4 | Have received sequence Y = {y_0, ..., y_{K+N}}.
 5 | Have transmitted sequence X = {x_0, ..., x_{N-1}}.
 6 | Denote state S_n = {x_n, x_{n-1}, ..., x_{n-L}}.
 7 | 
 8 | Define a bag as an unordered collection with two operations, add and take.
 9 | We have three bags:
10 |    S: a bag of survivors.
11 |    F: a bag of available data structures.
12 | 
13 | At time n, start with a non-empty bag S of survivors from time n-1.
14 | Take a member out of S, and create all possible branches and their corresponding metrics.  If metric ratio is above T, discard branch.  Otherwise, check branch against entry in pruning table P.  If branch metric is smaller than the existing entry's metric in P, then replace entry with branch.  Otherwise, discard branch.
15 | Once all possible branches of S have been created and pruned, S should be empty.Empty pruning table back into S, thus P is now empty.  Repeat.
16 | 


--------------------------------------------------------------------------------
/Transceiver52M/convert.h:
--------------------------------------------------------------------------------
1 | #ifndef _CONVERT_H_
2 | #define _CONVERT_H_
3 | 
4 | void convert_float_short(short *out, float *in, float scale, int len);
5 | void convert_short_float(float *out, short *in, int len);
6 | 
7 | #endif /* _CONVERT_H_ */
8 | 


--------------------------------------------------------------------------------
/Transceiver52M/convolve.h:
--------------------------------------------------------------------------------
 1 | #ifndef _CONVOLVE_H_
 2 | #define _CONVOLVE_H_
 3 | 
 4 | void *convolve_h_alloc(int num);
 5 | 
 6 | int convolve_real(float *x, int x_len,
 7 | 		  float *h, int h_len,
 8 | 		  float *y, int y_len,
 9 | 		  int start, int len,
10 | 		  int step, int offset);
11 | 
12 | int convolve_complex(float *x, int x_len,
13 | 		     float *h, int h_len,
14 | 		     float *y, int y_len,
15 | 		     int start, int len,
16 | 		     int step, int offset);
17 | 
18 | int base_convolve_real(float *x, int x_len,
19 | 		       float *h, int h_len,
20 | 		       float *y, int y_len,
21 | 		       int start, int len,
22 | 		       int step, int offset);
23 | 
24 | int base_convolve_complex(float *x, int x_len,
25 | 			  float *h, int h_len,
26 | 			  float *y, int y_len,
27 | 			  int start, int len,
28 | 			  int step, int offset);
29 | 
30 | #endif /* _CONVOLVE_H_ */
31 | 


--------------------------------------------------------------------------------
/Transceiver52M/laurent.m:
--------------------------------------------------------------------------------
 1 | %
 2 | % Laurent decomposition of GMSK signals
 3 | % Generates C0, C1, and C2 pulse shapes
 4 | %
 5 | % Pierre Laurent, "Exact and Approximate Construction of Digital Phase
 6 | %   Modulations by Superposition of Amplitude Modulated Pulses", IEEE
 7 | %   Transactions of Communications, Vol. 34, No. 2, Feb 1986.
 8 | %
 9 | % Author: Thomas Tsou <tom@tsou.cc>
10 | %
11 | 
12 | % Modulation parameters
13 | oversamp = 16;
14 | L = 3;
15 | f = 270.83333e3;
16 | T = 1/f;
17 | h = 0.5;
18 | BT = 0.30;
19 | B = BT / T;
20 | 
21 | % Generate sampling points for L symbol periods
22 | t = -(L*T/2):T/oversamp:(L*T/2);
23 | t = t(1:end-1) + (T/oversamp/2);
24 | 
25 | % Generate Gaussian pulse
26 | g = qfunc(2*pi*B*(t - T/2)/(log(2)^.5)) - qfunc(2*pi*B*(t + T/2)/(log(2)^.5));
27 | g = g / sum(g) * pi/2;
28 | g = [0 g];
29 | 
30 | % Integrate phase 
31 | q = 0;
32 | for i = 1:size(g,2);
33 |     q(i) = sum(g(1:i));
34 | end
35 | 
36 | % Compute two sided "generalized phase pulse" function
37 | s = 0;
38 | for i = 1:size(g,2);
39 |     s(i) = sin(q(i)) / sin(pi*h);
40 | end
41 | for i = (size(g,2) + 1):(2 * size(g,2) - 1);
42 |     s(i) = sin(pi*h - q(i - (size(g,2) - 1))) / sin(pi*h);
43 | end
44 | 
45 | % Compute C0 pulse: valid for all L values
46 | c0 = s(1:end-(oversamp*(L-1)));
47 | for i = 1:L-1;
48 |     c0 = c0 .* s((1 + i*oversamp):end-(oversamp*(L - 1 - i)));
49 | end
50 | 
51 | % Compute C1 pulse: valid for L = 3 only!
52 | %   C1 = S0 * S4 * S2
53 | c1 = s(1:end-(oversamp*(4)));
54 | c1 = c1 .* s((1 + 4*oversamp):end-(oversamp*(4 - 1 - 3)));
55 | c1 = c1 .* s((1 + 2*oversamp):end-(oversamp*(4 - 1 - 1)));
56 | 
57 | % Compute C2 pulse: valid for L = 3 only!
58 | %   C2 = S0 * S1 * S5
59 | c2 = s(1:end-(oversamp*(5)));
60 | c2 = c2 .* s((1 + 1*oversamp):end-(oversamp*(5 - 1 - 0)));
61 | c2 = c2 .* s((1 + 5*oversamp):end-(oversamp*(5 - 1 - 4)));
62 | 
63 | % Plot C0, C1, C2 Laurent pulse series
64 | figure(1);
65 | hold off;
66 | plot((0:size(c0,2)-1)/oversamp - 2,c0, 'b');
67 | hold on;
68 | plot((0:size(c1,2)-1)/oversamp - 2,c1, 'r');
69 | plot((0:size(c2,2)-1)/oversamp - 2,c2, 'g');
70 | 
71 | % Generate OpenBTS pulse
72 | numSamples = size(c0,2); 
73 | centerPoint = (numSamples - 1)/2;
74 | i = ((0:numSamples) - centerPoint) / oversamp;
75 | xP = .96*exp(-1.1380*i.^2 - 0.527*i.^4);
76 | xP = xP / max(xP) * max(c0);
77 | 
78 | % Plot C0 pulse compared to OpenBTS pulse
79 | figure(2);
80 | hold off;
81 | plot((0:size(c0,2)-1)/oversamp, c0, 'b');
82 | hold on;
83 | plot((0:size(xP,2)-1)/oversamp, xP, 'r');
84 | 


--------------------------------------------------------------------------------
/Transceiver52M/pulseApproximate.m:
--------------------------------------------------------------------------------
 1 | pp = [0 0 0.015 0.18 0.7 0.96 0.7 0.18 0.015 0 0];
 2 | t = -2.5:0.5:2.5;
 3 | 
 4 | v = -0.000:-0.001:-1.999;
 5 | 
 6 | 
 7 | for ix1 = 1:length(v),
 8 | 	    disp(ix1);
 9 |  for ix2 = 1:length(v),
10 |   p = exp(v(ix1)*t.^2+v(ix2)*t.^4);
11 |   r(ix1,ix2) = norm(p./max(abs(p)) - pp./max(abs(pp)));
12 |  end;
13 | end;
14 | 
15 | 
16 | 


--------------------------------------------------------------------------------
/Transceiver52M/radioClock.cpp:
--------------------------------------------------------------------------------
 1 | /*
 2 |  * Written by Thomas Tsou <ttsou@vt.edu>
 3 |  * Based on code by Harvind S Samra <hssamra@kestrelsp.com>
 4 |  *
 5 |  * Copyright 2011 Free Software Foundation, Inc.
 6 |  *
 7 |  * This program is free software: you can redistribute it and/or modify
 8 |  * it under the terms of the GNU Affero General Public License as published by
 9 |  * the Free Software Foundation, either version 3 of the License, or
10 |  * (at your option) any later version.
11 |  *
12 |  * This program is distributed in the hope that it will be useful,
13 |  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 |  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 |  * GNU Affero General Public License for more details.
16 |  *
17 |  * You should have received a copy of the GNU Affero General Public License
18 |  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 |  * See the COPYING file in the main directory for details.
20 |  */
21 | 
22 | #include "radioClock.h"
23 | 
24 | void RadioClock::set(const GSM::Time& wTime)
25 | {
26 | 	mLock.lock();
27 | 	mClock = wTime;
28 | 	updateSignal.signal();
29 | 	mLock.unlock();
30 | }
31 | 
32 | void RadioClock::incTN()
33 | {
34 | 	mLock.lock();
35 | 	mClock.incTN();
36 | 	updateSignal.signal();
37 | 	mLock.unlock();
38 | }
39 | 
40 | GSM::Time RadioClock::get()
41 | {
42 | 	mLock.lock();
43 | 	GSM::Time retVal = mClock;
44 | 	mLock.unlock();
45 | 
46 | 	return retVal;
47 | }
48 | 
49 | void RadioClock::wait()
50 | {
51 | 	mLock.lock();
52 | 	updateSignal.wait(mLock,1);
53 | 	mLock.unlock();
54 | }
55 | 


--------------------------------------------------------------------------------
/Transceiver52M/radioClock.h:
--------------------------------------------------------------------------------
 1 | /*
 2 |  * Written by Thomas Tsou <ttsou@vt.edu>
 3 |  * Based on code by Harvind S Samra <hssamra@kestrelsp.com>
 4 |  *
 5 |  * Copyright 2011 Free Software Foundation, Inc.
 6 |  *
 7 |  * This program is free software: you can redistribute it and/or modify
 8 |  * it under the terms of the GNU Affero General Public License as published by
 9 |  * the Free Software Foundation, either version 3 of the License, or
10 |  * (at your option) any later version.
11 |  *
12 |  * This program is distributed in the hope that it will be useful,
13 |  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 |  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 |  * GNU Affero General Public License for more details.
16 |  *
17 |  * You should have received a copy of the GNU Affero General Public License
18 |  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 |  * See the COPYING file in the main directory for details.
20 |  */
21 | 
22 | #ifndef RADIOCLOCK_H
23 | #define RADIOCLOCK_H
24 | 
25 | #include "GSMCommon.h"
26 | 
27 | class RadioClock {
28 | public:
29 | 	void set(const GSM::Time& wTime);
30 | 	void incTN();
31 | 	GSM::Time get();
32 | 	void wait();
33 | 
34 | private:
35 | 	GSM::Time mClock;
36 | 	Mutex mLock;
37 | 	Signal updateSignal;
38 | };
39 | 
40 | #endif /* RADIOCLOCK_H */
41 | 


--------------------------------------------------------------------------------
/Transceiver52M/radioVector.h:
--------------------------------------------------------------------------------
 1 | /*
 2 |  * Written by Thomas Tsou <ttsou@vt.edu>
 3 |  * Based on code by Harvind S Samra <hssamra@kestrelsp.com>
 4 |  *
 5 |  * Copyright 2011 Free Software Foundation, Inc.
 6 |  *
 7 |  * This program is free software: you can redistribute it and/or modify
 8 |  * it under the terms of the GNU Affero General Public License as published by
 9 |  * the Free Software Foundation, either version 3 of the License, or
10 |  * (at your option) any later version.
11 |  *
12 |  * This program is distributed in the hope that it will be useful,
13 |  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 |  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 |  * GNU Affero General Public License for more details.
16 |  *
17 |  * You should have received a copy of the GNU Affero General Public License
18 |  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 |  * See the COPYING file in the main directory for details.
20 |  */
21 | 
22 | #ifndef RADIOVECTOR_H
23 | #define RADIOVECTOR_H
24 | 
25 | #include "sigProcLib.h"
26 | #include "GSMCommon.h"
27 | 
28 | class radioVector : public signalVector {
29 | public:
30 | 	radioVector(const signalVector& wVector, GSM::Time& wTime);
31 | 	GSM::Time getTime() const;
32 | 	void setTime(const GSM::Time& wTime);
33 | 	bool operator>(const radioVector& other) const;
34 | 
35 | private:
36 | 	GSM::Time mTime;
37 | };
38 | 
39 | class noiseVector : std::vector<float> {
40 | public:
41 | 	noiseVector(size_t len = 0);
42 | 	bool insert(float val);
43 | 	float avg();
44 | 
45 | private:
46 | 	std::vector<float>::iterator it;
47 | };
48 | 
49 | class VectorFIFO {
50 | public:
51 | 	unsigned size();
52 | 	void put(radioVector *ptr);
53 | 	radioVector *get();
54 | 
55 | private:
56 | 	PointerFIFO mQ;
57 | };
58 | 
59 | class VectorQueue : public InterthreadPriorityQueue<radioVector> {
60 | public:
61 | 	GSM::Time nextTime() const;
62 | 	radioVector* getStaleBurst(const GSM::Time& targTime);
63 | 	radioVector* getCurrentBurst(const GSM::Time& targTime);
64 | };
65 | 
66 | #endif /* RADIOVECTOR_H */
67 | 


--------------------------------------------------------------------------------
/Transceiver52M/std_inband.rbf:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/RangeNetworks/openbts/7766ef94f2d885c197430e74a89f02740f0c04e6/Transceiver52M/std_inband.rbf


--------------------------------------------------------------------------------
/TransceiverRAD1/FactoryCalibration.h:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2013, 2014 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses;
 5 | * see the COPYING file in the main directory for licensing
 6 | * information for this specific distribution.
 7 | *
 8 | * This use of this software may be subject to additional restrictions.
 9 | * See the LEGAL file in the main directory for details.
10 | 
11 |     This program is distributed in the hope that it will be useful,
12 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
13 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 | 
15 | */
16 | 
17 | #include "rnrad1Core.h"
18 | 
19 | /*
20 | 	TODO : lots of copied bits from RAD1CMD and RAD1SN, could definitely be improved
21 | 		by simplifying the hex<->dec parsing. Comments from rad1_setup.sh inline.
22 | */
23 | class FactoryCalibration {
24 | 
25 | 	private:
26 | 
27 | 	rnrad1Core * core;
28 | 	unsigned int sdrsn;
29 | 	unsigned int rfsn;
30 | 	unsigned int band;
31 | 	unsigned int freq;
32 | 	unsigned int rxgain;
33 | 	unsigned int txgain;
34 | 
35 | 	static int hexval (char ch);
36 | 	static unsigned char * hex_string_to_binary(const char *string, int *lenptr);
37 | 	bool i2c_write(int i2c_addr, char *hex_string);
38 | 	std::string i2c_read(int i2c_addr, int len);
39 | 	unsigned int hex2dec(std::string hex);
40 | 
41 | 	public:
42 | 
43 | 	unsigned int getValue(std::string name);
44 | 	void readEEPROM(int deviceID);
45 | };
46 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/README:
--------------------------------------------------------------------------------
 1 | The Transceiver
 2 | 
 3 | The transceiver consists of three modules:
 4 |    --- transceiver
 5 |    --- radioInterface
 6 |    --- USRPDevice
 7 | 
 8 | The USRPDevice module is basically a driver that reads/writes
 9 | packets to a USRP with two RFX900 daughterboards, board 
10 | A is the Tx chain and board B is the Rx chain.  
11 | 
12 | The radioInterface module is basically an interface b/w the
13 | transceiver and the USRP.   It operates the basestation clock
14 | based upon the sample count of received USRP samples.  Packets 
15 | from the USRP are queued and segmented into GSM bursts that are
16 | passed up to the transceiver; bursts from the transceiver are
17 | passed down to the USRP. 
18 | 
19 | The transceiver basically operates "layer 0" of the GSM stack,
20 | performing the modulation, detection, and demodulation of GSM 
21 | bursts.  It communicates with the GSM stack via three UDP sockets,
22 | one socket for data, one for control messages, and one socket to
23 | pass clocking information.  The transceiver contains a priority
24 | queue to sort to-be-transmitted bursts, and a filler table to fill
25 | in timeslots that do not have bursts in the priority queue.  The
26 | transceiver tries to stay ahead of the basestation clock, adapting 
27 | its latency when underruns are reported by the radioInterface/USRP.
28 | Received bursts (from the radioInterface) pass through a simple 
29 | energy detector, a RACH or midamble correlator, and a DFE-based demodulator.
30 | 
31 | NOTE: There's a SWLOOPBACK #define statement, where the USRP is replaced
32 | with a memory buffer.  In this mode, data written to the USRP is actually stored 
33 | in a buffer, and read commands to the USRP simply pull data from this buffer.
34 | This was very useful in early testing, and still may be useful in testing basic
35 | Transceiver and radioInterface functionality. 
36 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/README.DFEsymbolspaced:
--------------------------------------------------------------------------------
 1 | signalVectors G0, G1.  i.e. G0(D) = 1 +2D + 3D^2 = [1 2 3]
 2 | G0(D) = 1/sqrt(SNR).
 3 | G1(D) = [h0 h1D .. h_(N-1)D^(N-1)]
 4 | for i = 0,1,...,N_f-1,
 5 |   d = |G0(0)|^2+|G1(0)|^2
 6 |   l_i(D) = D^i ( G0(D)*G0'(0) + G1(D)*G1'(0) )/d
 7 |   k = G1(0)/G0(0) 
 8 |   G0n(D) = G0(D)+k'*G1(D)
 9 |   G1n(D) = (-G0(D)*k+G1(D))/D
10 |   G0(D) = G0n(D)/sqrt(1+k*k')
11 |   G1(D) = G1n(D)/sqrt(1+k*k')
12 | end
13 | 
14 | 
15 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/README.Talgorithm:
--------------------------------------------------------------------------------
 1 | Basic model:
 2 | 
 3 | Have channel H = {h_0, h_1, ..., h_{K-1}}.
 4 | Have received sequence Y = {y_0, ..., y_{K+N}}.
 5 | Have transmitted sequence X = {x_0, ..., x_{N-1}}.
 6 | Denote state S_n = {x_n, x_{n-1}, ..., x_{n-L}}.
 7 | 
 8 | Define a bag as an unordered collection with two operations, add and take.
 9 | We have three bags:
10 |    S: a bag of survivors.
11 |    F: a bag of available data structures.
12 | 
13 | At time n, start with a non-empty bag S of survivors from time n-1.
14 | Take a member out of S, and create all possible branches and their corresponding metrics.  If metric ratio is above T, discard branch.  Otherwise, check branch against entry in pruning table P.  If branch metric is smaller than the existing entry's metric in P, then replace entry with branch.  Otherwise, discard branch.
15 | Once all possible branches of S have been created and pruned, S should be empty.Empty pruning table back into S, thus P is now empty.  Repeat.
16 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/bytesex.h:
--------------------------------------------------------------------------------
 1 | #ifndef INCLUDED_USRP_BYTESEX_H
 2 | #define INCLUDED_USRP_BYTESEX_H
 3 | 
 4 | /*!
 5 |  * \brief routines for convertering between host and usrp byte order
 6 |  *
 7 |  * Prior to including this file, the user must include "config.h"
 8 |  * which will or won't define WORDS_BIGENDIAN based on the
 9 |  * result of the AC_C_BIGENDIAN autoconf test.
10 |  */
11 | 
12 | #ifdef HAVE_BYTESWAP_H
13 | #include <byteswap.h>
14 | #else
15 | 
16 | #warning Using non-portable code (likely wrong other than ILP32).
17 | 
18 | static inline unsigned short int
19 | bswap_16 (unsigned short int x)
20 | {
21 |   return ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8));
22 | }
23 | 
24 | static inline unsigned int
25 | bswap_32 (unsigned int x)
26 | {
27 |   return ((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >>  8) \
28 |         | (((x) & 0x0000ff00) <<  8) | (((x) & 0x000000ff) << 24));
29 | }
30 | #endif
31 | 
32 | 
33 | #ifdef WORDS_BIGENDIAN
34 | 
35 | static inline unsigned int
36 | host_to_usrp_u32 (unsigned int x)
37 | {
38 |   return bswap_32(x);
39 | }
40 | 
41 | static inline unsigned int
42 | usrp_to_host_u32 (unsigned int x)
43 | {
44 |   return bswap_32(x);
45 | }
46 | 
47 | static inline short int
48 | host_to_usrp_short (short int x)
49 | {
50 |   return bswap_16 (x);
51 | }
52 | 
53 | static inline short int
54 | usrp_to_host_short (short int x)
55 | {
56 |   return bswap_16 (x);
57 | }
58 | 
59 | #else
60 | 
61 | static inline unsigned int
62 | host_to_usrp_u32 (unsigned int x)
63 | {
64 |   return x;
65 | }
66 | 
67 | static inline unsigned int
68 | usrp_to_host_u32 (unsigned int x)
69 | {
70 |   return x;
71 | }
72 | 
73 | static inline short int
74 | host_to_usrp_short (short int x)
75 | {
76 |   return x;
77 | }
78 | 
79 | static inline short int
80 | usrp_to_host_short (unsigned short int x)
81 | {
82 |   return x;
83 | }
84 | 
85 | #endif
86 | 
87 | #endif /* INCLUDED_USRP_BYTESEX_H */
88 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga.rbf:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/RangeNetworks/openbts/7766ef94f2d885c197430e74a89f02740f0c04e6/TransceiverRAD1/fpga.rbf


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/README.RAD1:
--------------------------------------------------------------------------------
 1 | RAD1 changes 
 2 | -----------------------------------------------------
 3 | 
 4 | chan_fifo_reader.v
 5 | changed timestamp_clock -> "adc_time"
 6 | added JITTER
 7 | 
 8 | cic_interp.v
 9 | changes clear_me --> reset
10 | 
11 | cic_int_shifter.v
12 | increased default value of bitgain to "21"
13 |  
14 | cmd_reader.v
15 | propagated name change timestamp_clock
16 | 
17 | io_pins.v
18 | removed --> inout wire [15:0] io_2, inout wire [15:0] io_3,
19 | removed --> input wire [15:0] reg_2, input wire [15:0] reg_3,
20 | +	 `FR_OE_2 : io_2_oe
21 | +	   <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
22 | +	 `FR_OE_3 : io_3_oe
23 | +	   <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
24 |  
25 | master_control.v
26 | removed -->  wire [7:0] master_controls;
27 | 
28 | packet_builder.v
29 | parameter NUM_CHAN = 1 --> used to be 2
30 | changes name timestamp_complete -- tstamp_complete;
31 | 
32 | register_io.v
33 | added 
34 | -     atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate, decim_rate, 
35 | -     atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1,
36 | -     atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3, 
37 | -     txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);   
38 | 
39 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/inband_lib/channel_demux.v:
--------------------------------------------------------------------------------
 1 | module channel_demux
 2 |  #(parameter NUM_CHAN = 2) (     //usb Side
 3 |    input [31:0]usbdata_final,
 4 |    input WR_final, 
 5 |    // TX Side
 6 |    input reset,
 7 |    input txclk,
 8 |    output reg [NUM_CHAN:0] WR_channel,
 9 |    output reg [31:0] ram_data,
10 |    output reg [NUM_CHAN:0] WR_done_channel );
11 |    /* Parse header and forward to ram */
12 | 	
13 |     reg [2:0]reader_state;
14 |     reg [4:0]channel ;
15 |     reg [6:0]read_length ;
16 | 	
17 | 	 // States
18 |     parameter IDLE      =    3'd0;
19 |     parameter HEADER    =    3'd1;
20 |     parameter WAIT      =    3'd2;
21 |     parameter FORWARD   =    3'd3;
22 | 	
23 | 	`define CHANNEL 20:16
24 | 	`define PKT_SIZE 127
25 | 	wire [4:0] true_channel;
26 | 	assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
27 | 							NUM_CHAN : (usbdata_final[`CHANNEL]);
28 | 	
29 | 	always @(posedge txclk)
30 | 	  begin
31 | 	    if (reset)
32 | 	      begin
33 | 	       reader_state <= IDLE;
34 | 	       WR_channel <= 0;
35 | 	       WR_done_channel <= 0;
36 | 	      end
37 | 	      else
38 | 	        case (reader_state)
39 | 	        IDLE: begin
40 | 	            if (WR_final)
41 | 	                reader_state <= HEADER; 
42 | 	            end
43 | 	       
44 |             // Store channel and forware header
45 | 	        HEADER: begin
46 | 	            channel <= true_channel;
47 | 	            WR_channel[true_channel] <= 1;
48 | 	            ram_data <= usbdata_final;
49 | 				read_length <= 7'd0 ;
50 | 				
51 |                 reader_state <= WAIT;
52 | 	        end
53 | 	       
54 | 	        WAIT: begin
55 | 	           WR_channel[channel] <= 0;
56 | 	
57 | 			   if (read_length == `PKT_SIZE)
58 | 	               reader_state <= IDLE;
59 | 	           else if (WR_final)
60 | 	               reader_state <= FORWARD;
61 | 	        end
62 | 	       
63 | 	        FORWARD: begin
64 | 	           WR_channel[channel] <= 1;
65 | 	           ram_data <= usbdata_final;
66 | 	           read_length <= read_length + 7'd1;
67 | 	           
68 | 	           reader_state <= WAIT;
69 | 	        end
70 | 	
71 | 			default:
72 |                begin
73 | 					//error handling
74 |                    reader_state <= IDLE;
75 |                end
76 | 	       endcase
77 | 	   end
78 | endmodule
79 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/inband_lib/test_comparator.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | // Range Networks 
 3 | // Unsigned 16-bit greater or equal comparator.
 4 | // for test module
 5 | 
 6 | module testcompar
 7 |    (
 8 |      input usbdata_packed[31:0],
 9 | 	  output reg test_bit1
10 | 	);
11 | 	usbdata_packed[15:0] A;
12 | 	usbdata_packed[31:16] B;
13 | 	assign test_bit1 = A == B ? 1'b1 : 1'b0;
14 | 	endmodule 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/inband_lib/usb_fifo_reader.v:
--------------------------------------------------------------------------------
 1 | module usb_fifo_reader (
 2 |       input usbclk,
 3 |       input bus_reset, 
 4 |       input RD,
 5 |       output rdreq,
 6 |       );
 7 |       
 8 |     // FX2 Bug Fix
 9 |     reg [8:0] read_count;
10 |     always @(negedge usbclk)
11 |         if(bus_reset)
12 |             read_count <= #1 9'd0;
13 |         else if(RD & ~read_count[8])
14 |             read_count <= #1 read_count + 9'd1;
15 |         else
16 |             read_count <= #1 RD ? read_count : 9'b0;
17 |             
18 |     assign rdreq = RD & ~read_count[8];
19 |     
20 |     
21 |  
22 | endmodule
23 |        
24 |    
25 |    


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/accum32.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | component accum32
23 | 	PORT
24 | 	(
25 | 		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
26 | 		clock		: IN STD_LOGIC  := '0';
27 | 		clken		: IN STD_LOGIC  := '1';
28 | 		aclr		: IN STD_LOGIC  := '0';
29 | 		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
30 | 	);
31 | end component;
32 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/accum32.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | FUNCTION accum32 
23 | (
24 | 	data[31..0],
25 | 	clock,
26 | 	clken,
27 | 	aclr
28 | )
29 | 
30 | RETURNS (
31 | 	result[31..0]
32 | );
33 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/accum32_bb.v:
--------------------------------------------------------------------------------
 1 | //Copyright (C) 1991-2003 Altera Corporation
 2 | //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | //support information,  device programming or simulation file,  and any other
 4 | //associated  documentation or information  provided by  Altera  or a partner
 5 | //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | //other  use  of such  megafunction  design,  netlist,  support  information,
 8 | //device programming or simulation file,  or any other  related documentation
 9 | //or information  is prohibited  for  any  other purpose,  including, but not
10 | //limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | //any other  silicon devices,  unless such use is  explicitly  licensed under
12 | //a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | //intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | //support  information,  device programming or simulation file,  or any other
16 | //related documentation or information provided by  Altera  or a megafunction
17 | //partner, remains with Altera, the megafunction partner, or their respective
18 | //licensors. No other licenses, including any licenses needed under any third
19 | //party's intellectual property, are provided herein.
20 | 
21 | module accum32 (
22 | 	data,
23 | 	clock,
24 | 	clken,
25 | 	aclr,
26 | 	result)/* synthesis synthesis_clearbox = 1 */;
27 | 
28 | 	input	[31:0]  data;
29 | 	input	  clock;
30 | 	input	  clken;
31 | 	input	  aclr;
32 | 	output	[31:0]  result;
33 | 
34 | endmodule
35 | 
36 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/accum32_inst.v:
--------------------------------------------------------------------------------
1 | accum32	accum32_inst (
2 | 	.data ( data_sig ),
3 | 	.clock ( clock_sig ),
4 | 	.clken ( clken_sig ),
5 | 	.aclr ( aclr_sig ),
6 | 	.result ( result_sig )
7 | 	);
8 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/add32.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | component add32
23 | 	PORT
24 | 	(
25 | 		dataa		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
26 | 		datab		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
27 | 		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
28 | 	);
29 | end component;
30 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/add32.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | FUNCTION add32 
23 | (
24 | 	dataa[7..0],
25 | 	datab[7..0]
26 | )
27 | 
28 | RETURNS (
29 | 	result[7..0]
30 | );
31 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/add32_bb.v:
--------------------------------------------------------------------------------
 1 | //Copyright (C) 1991-2003 Altera Corporation
 2 | //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | //support information,  device programming or simulation file,  and any other
 4 | //associated  documentation or information  provided by  Altera  or a partner
 5 | //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | //other  use  of such  megafunction  design,  netlist,  support  information,
 8 | //device programming or simulation file,  or any other  related documentation
 9 | //or information  is prohibited  for  any  other purpose,  including, but not
10 | //limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | //any other  silicon devices,  unless such use is  explicitly  licensed under
12 | //a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | //intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | //support  information,  device programming or simulation file,  or any other
16 | //related documentation or information provided by  Altera  or a megafunction
17 | //partner, remains with Altera, the megafunction partner, or their respective
18 | //licensors. No other licenses, including any licenses needed under any third
19 | //party's intellectual property, are provided herein.
20 | 
21 | module add32 (
22 | 	dataa,
23 | 	datab,
24 | 	result)/* synthesis synthesis_clearbox = 1 */;
25 | 
26 | 	input	[7:0]  dataa;
27 | 	input	[7:0]  datab;
28 | 	output	[7:0]  result;
29 | 
30 | endmodule
31 | 
32 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/add32_inst.v:
--------------------------------------------------------------------------------
1 | add32	add32_inst (
2 | 	.dataa ( dataa_sig ),
3 | 	.datab ( datab_sig ),
4 | 	.result ( result_sig )
5 | 	);
6 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/addsub16.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | component addsub16
23 | 	PORT
24 | 	(
25 | 		add_sub		: IN STD_LOGIC ;
26 | 		dataa		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
27 | 		datab		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
28 | 		clock		: IN STD_LOGIC ;
29 | 		aclr		: IN STD_LOGIC ;
30 | 		clken		: IN STD_LOGIC ;
31 | 		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
32 | 	);
33 | end component;
34 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/addsub16.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | FUNCTION addsub16 
23 | (
24 | 	add_sub,
25 | 	dataa[15..0],
26 | 	datab[15..0],
27 | 	clock,
28 | 	aclr,
29 | 	clken
30 | )
31 | 
32 | RETURNS (
33 | 	result[15..0]
34 | );
35 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/addsub16_bb.v:
--------------------------------------------------------------------------------
 1 | //Copyright (C) 1991-2003 Altera Corporation
 2 | //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | //support information,  device programming or simulation file,  and any other
 4 | //associated  documentation or information  provided by  Altera  or a partner
 5 | //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | //other  use  of such  megafunction  design,  netlist,  support  information,
 8 | //device programming or simulation file,  or any other  related documentation
 9 | //or information  is prohibited  for  any  other purpose,  including, but not
10 | //limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | //any other  silicon devices,  unless such use is  explicitly  licensed under
12 | //a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | //intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | //support  information,  device programming or simulation file,  or any other
16 | //related documentation or information provided by  Altera  or a megafunction
17 | //partner, remains with Altera, the megafunction partner, or their respective
18 | //licensors. No other licenses, including any licenses needed under any third
19 | //party's intellectual property, are provided herein.
20 | 
21 | module addsub16 (
22 | 	add_sub,
23 | 	dataa,
24 | 	datab,
25 | 	clock,
26 | 	aclr,
27 | 	clken,
28 | 	result)/* synthesis synthesis_clearbox = 1 */;
29 | 
30 | 	input	  add_sub;
31 | 	input	[15:0]  dataa;
32 | 	input	[15:0]  datab;
33 | 	input	  clock;
34 | 	input	  aclr;
35 | 	input	  clken;
36 | 	output	[15:0]  result;
37 | 
38 | endmodule
39 | 
40 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/addsub16_inst.v:
--------------------------------------------------------------------------------
 1 | addsub16	addsub16_inst (
 2 | 	.add_sub ( add_sub_sig ),
 3 | 	.dataa ( dataa_sig ),
 4 | 	.datab ( datab_sig ),
 5 | 	.clock ( clock_sig ),
 6 | 	.aclr ( aclr_sig ),
 7 | 	.clken ( clken_sig ),
 8 | 	.result ( result_sig )
 9 | 	);
10 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/bustri.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | component bustri
23 | 	PORT
24 | 	(
25 | 		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
26 | 		enabledt		: IN STD_LOGIC ;
27 | 		tridata		: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
28 | 	);
29 | end component;
30 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/bustri.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | FUNCTION bustri 
23 | (
24 | 	data[15..0],
25 | 	enabledt
26 | )
27 | 
28 | RETURNS (
29 | 	tridata[15..0]
30 | );
31 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/bustri_bb.v:
--------------------------------------------------------------------------------
 1 | //Copyright (C) 1991-2003 Altera Corporation
 2 | //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | //support information,  device programming or simulation file,  and any other
 4 | //associated  documentation or information  provided by  Altera  or a partner
 5 | //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | //other  use  of such  megafunction  design,  netlist,  support  information,
 8 | //device programming or simulation file,  or any other  related documentation
 9 | //or information  is prohibited  for  any  other purpose,  including, but not
10 | //limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | //any other  silicon devices,  unless such use is  explicitly  licensed under
12 | //a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | //intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | //support  information,  device programming or simulation file,  or any other
16 | //related documentation or information provided by  Altera  or a megafunction
17 | //partner, remains with Altera, the megafunction partner, or their respective
18 | //licensors. No other licenses, including any licenses needed under any third
19 | //party's intellectual property, are provided herein.
20 | 
21 | module bustri (
22 | 	data,
23 | 	enabledt,
24 | 	tridata);
25 | 
26 | 	input	[15:0]  data;
27 | 	input	  enabledt;
28 | 	inout	[15:0]  tridata;
29 | 
30 | endmodule
31 | 
32 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/bustri_inst.v:
--------------------------------------------------------------------------------
1 | bustri	bustri_inst (
2 | 	.data ( data_sig ),
3 | 	.enabledt ( enabledt_sig ),
4 | 	.tridata ( tridata_sig )
5 | 	);
6 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/dspclkpll_bb.v:
--------------------------------------------------------------------------------
 1 | //Copyright (C) 1991-2004 Altera Corporation
 2 | //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | //support information,  device programming or simulation file,  and any other
 4 | //associated  documentation or information  provided by  Altera  or a partner
 5 | //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | //other  use  of such  megafunction  design,  netlist,  support  information,
 8 | //device programming or simulation file,  or any other  related documentation
 9 | //or information  is prohibited  for  any  other purpose,  including, but not
10 | //limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | //any other  silicon devices,  unless such use is  explicitly  licensed under
12 | //a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | //intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | //support  information,  device programming or simulation file,  or any other
16 | //related documentation or information provided by  Altera  or a megafunction
17 | //partner, remains with Altera, the megafunction partner, or their respective
18 | //licensors. No other licenses, including any licenses needed under any third
19 | //party's intellectual property, are provided herein.
20 | 
21 | module dspclkpll (
22 | 	inclk0,
23 | 	c0,
24 | 	c1);
25 | 
26 | 	input	  inclk0;
27 | 	output	  c0;
28 | 	output	  c1;
29 | 
30 | endmodule
31 | 
32 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/fifo_1kx16.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2006 Altera Corporation
 2 | --Your use of Altera Corporation's design tools, logic functions 
 3 | --and other software and tools, and its AMPP partner logic 
 4 | --functions, and any output files any of the foregoing 
 5 | --(including device programming or simulation files), and any 
 6 | --associated documentation or information are expressly subject 
 7 | --to the terms and conditions of the Altera Program License 
 8 | --Subscription Agreement, Altera MegaCore Function License 
 9 | --Agreement, or other applicable license agreement, including, 
10 | --without limitation, that your use is for the sole purpose of 
11 | --programming logic devices manufactured by Altera and sold by 
12 | --Altera or its authorized distributors.  Please refer to the 
13 | --applicable agreement for further details.
14 | 
15 | 
16 | component fifo_1kx16
17 | 	PORT
18 | 	(
19 | 		aclr		: IN STD_LOGIC ;
20 | 		clock		: IN STD_LOGIC ;
21 | 		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
22 | 		rdreq		: IN STD_LOGIC ;
23 | 		wrreq		: IN STD_LOGIC ;
24 | 		almost_empty		: OUT STD_LOGIC ;
25 | 		empty		: OUT STD_LOGIC ;
26 | 		full		: OUT STD_LOGIC ;
27 | 		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
28 | 		usedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
29 | 	);
30 | end component;
31 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/fifo_1kx16.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2006 Altera Corporation
 2 | --Your use of Altera Corporation's design tools, logic functions 
 3 | --and other software and tools, and its AMPP partner logic 
 4 | --functions, and any output files any of the foregoing 
 5 | --(including device programming or simulation files), and any 
 6 | --associated documentation or information are expressly subject 
 7 | --to the terms and conditions of the Altera Program License 
 8 | --Subscription Agreement, Altera MegaCore Function License 
 9 | --Agreement, or other applicable license agreement, including, 
10 | --without limitation, that your use is for the sole purpose of 
11 | --programming logic devices manufactured by Altera and sold by 
12 | --Altera or its authorized distributors.  Please refer to the 
13 | --applicable agreement for further details.
14 | 
15 | 
16 | FUNCTION fifo_1kx16 
17 | (
18 | 	aclr,
19 | 	clock,
20 | 	data[15..0],
21 | 	rdreq,
22 | 	wrreq
23 | )
24 | 
25 | RETURNS (
26 | 	almost_empty,
27 | 	empty,
28 | 	full,
29 | 	q[15..0],
30 | 	usedw[9..0]
31 | );
32 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/fifo_1kx16_inst.v:
--------------------------------------------------------------------------------
 1 | fifo_1kx16	fifo_1kx16_inst (
 2 | 	.aclr ( aclr_sig ),
 3 | 	.clock ( clock_sig ),
 4 | 	.data ( data_sig ),
 5 | 	.rdreq ( rdreq_sig ),
 6 | 	.wrreq ( wrreq_sig ),
 7 | 	.almost_empty ( almost_empty_sig ),
 8 | 	.empty ( empty_sig ),
 9 | 	.full ( full_sig ),
10 | 	.q ( q_sig ),
11 | 	.usedw ( usedw_sig )
12 | 	);
13 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/fifo_4kx16_dc.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2006 Altera Corporation
 2 | --Your use of Altera Corporation's design tools, logic functions 
 3 | --and other software and tools, and its AMPP partner logic 
 4 | --functions, and any output files any of the foregoing 
 5 | --(including device programming or simulation files), and any 
 6 | --associated documentation or information are expressly subject 
 7 | --to the terms and conditions of the Altera Program License 
 8 | --Subscription Agreement, Altera MegaCore Function License 
 9 | --Agreement, or other applicable license agreement, including, 
10 | --without limitation, that your use is for the sole purpose of 
11 | --programming logic devices manufactured by Altera and sold by 
12 | --Altera or its authorized distributors.  Please refer to the 
13 | --applicable agreement for further details.
14 | 
15 | 
16 | component fifo_4kx16_dc
17 | 	PORT
18 | 	(
19 | 		aclr		: IN STD_LOGIC  := '0';
20 | 		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
21 | 		rdclk		: IN STD_LOGIC ;
22 | 		rdreq		: IN STD_LOGIC ;
23 | 		wrclk		: IN STD_LOGIC ;
24 | 		wrreq		: IN STD_LOGIC ;
25 | 		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
26 | 		rdempty		: OUT STD_LOGIC ;
27 | 		rdusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
28 | 		wrfull		: OUT STD_LOGIC ;
29 | 		wrusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
30 | 	);
31 | end component;
32 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/fifo_4kx16_dc.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2006 Altera Corporation
 2 | --Your use of Altera Corporation's design tools, logic functions 
 3 | --and other software and tools, and its AMPP partner logic 
 4 | --functions, and any output files any of the foregoing 
 5 | --(including device programming or simulation files), and any 
 6 | --associated documentation or information are expressly subject 
 7 | --to the terms and conditions of the Altera Program License 
 8 | --Subscription Agreement, Altera MegaCore Function License 
 9 | --Agreement, or other applicable license agreement, including, 
10 | --without limitation, that your use is for the sole purpose of 
11 | --programming logic devices manufactured by Altera and sold by 
12 | --Altera or its authorized distributors.  Please refer to the 
13 | --applicable agreement for further details.
14 | 
15 | 
16 | FUNCTION fifo_4kx16_dc 
17 | (
18 | 	aclr,
19 | 	data[15..0],
20 | 	rdclk,
21 | 	rdreq,
22 | 	wrclk,
23 | 	wrreq
24 | )
25 | 
26 | RETURNS (
27 | 	q[15..0],
28 | 	rdempty,
29 | 	rdusedw[11..0],
30 | 	wrfull,
31 | 	wrusedw[11..0]
32 | );
33 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/fifo_4kx16_dc_inst.v:
--------------------------------------------------------------------------------
 1 | fifo_4kx16_dc	fifo_4kx16_dc_inst (
 2 | 	.aclr ( aclr_sig ),
 3 | 	.data ( data_sig ),
 4 | 	.rdclk ( rdclk_sig ),
 5 | 	.rdreq ( rdreq_sig ),
 6 | 	.wrclk ( wrclk_sig ),
 7 | 	.wrreq ( wrreq_sig ),
 8 | 	.q ( q_sig ),
 9 | 	.rdempty ( rdempty_sig ),
10 | 	.rdusedw ( rdusedw_sig ),
11 | 	.wrfull ( wrfull_sig ),
12 | 	.wrusedw ( wrusedw_sig )
13 | 	);
14 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/mylpm_addsub.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | component mylpm_addsub
23 | 	PORT
24 | 	(
25 | 		add_sub		: IN STD_LOGIC ;
26 | 		dataa		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
27 | 		datab		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
28 | 		clock		: IN STD_LOGIC ;
29 | 		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
30 | 	);
31 | end component;
32 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/mylpm_addsub.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | FUNCTION mylpm_addsub 
23 | (
24 | 	add_sub,
25 | 	dataa[15..0],
26 | 	datab[15..0],
27 | 	clock
28 | )
29 | 
30 | RETURNS (
31 | 	result[15..0]
32 | );
33 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/mylpm_addsub_bb.v:
--------------------------------------------------------------------------------
 1 | //Copyright (C) 1991-2003 Altera Corporation
 2 | //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | //support information,  device programming or simulation file,  and any other
 4 | //associated  documentation or information  provided by  Altera  or a partner
 5 | //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | //other  use  of such  megafunction  design,  netlist,  support  information,
 8 | //device programming or simulation file,  or any other  related documentation
 9 | //or information  is prohibited  for  any  other purpose,  including, but not
10 | //limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | //any other  silicon devices,  unless such use is  explicitly  licensed under
12 | //a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | //intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | //support  information,  device programming or simulation file,  or any other
16 | //related documentation or information provided by  Altera  or a megafunction
17 | //partner, remains with Altera, the megafunction partner, or their respective
18 | //licensors. No other licenses, including any licenses needed under any third
19 | //party's intellectual property, are provided herein.
20 | 
21 | module mylpm_addsub (
22 | 	add_sub,
23 | 	dataa,
24 | 	datab,
25 | 	clock,
26 | 	result);
27 | 
28 | 	input	  add_sub;
29 | 	input	[15:0]  dataa;
30 | 	input	[15:0]  datab;
31 | 	input	  clock;
32 | 	output	[15:0]  result;
33 | 
34 | endmodule
35 | 
36 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/mylpm_addsub_inst.v:
--------------------------------------------------------------------------------
1 | mylpm_addsub	mylpm_addsub_inst (
2 | 	.add_sub ( add_sub_sig ),
3 | 	.dataa ( dataa_sig ),
4 | 	.datab ( datab_sig ),
5 | 	.clock ( clock_sig ),
6 | 	.result ( result_sig )
7 | 	);
8 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/pll_bb.v:
--------------------------------------------------------------------------------
 1 | //Copyright (C) 1991-2004 Altera Corporation
 2 | //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | //support information,  device programming or simulation file,  and any other
 4 | //associated  documentation or information  provided by  Altera  or a partner
 5 | //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | //other  use  of such  megafunction  design,  netlist,  support  information,
 8 | //device programming or simulation file,  or any other  related documentation
 9 | //or information  is prohibited  for  any  other purpose,  including, but not
10 | //limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | //any other  silicon devices,  unless such use is  explicitly  licensed under
12 | //a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | //intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | //support  information,  device programming or simulation file,  or any other
16 | //related documentation or information provided by  Altera  or a megafunction
17 | //partner, remains with Altera, the megafunction partner, or their respective
18 | //licensors. No other licenses, including any licenses needed under any third
19 | //party's intellectual property, are provided herein.
20 | 
21 | module pll (
22 | 	inclk0,
23 | 	c0);
24 | 
25 | 	input	  inclk0;
26 | 	output	  c0;
27 | 
28 | endmodule
29 | 
30 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/pll_inst.v:
--------------------------------------------------------------------------------
1 | pll	pll_inst (
2 | 	.inclk0 ( inclk0_sig ),
3 | 	.c0 ( c0_sig )
4 | 	);
5 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/sub32.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | component sub32
23 | 	PORT
24 | 	(
25 | 		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
26 | 		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
27 | 		clock		: IN STD_LOGIC ;
28 | 		aclr		: IN STD_LOGIC ;
29 | 		clken		: IN STD_LOGIC ;
30 | 		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
31 | 	);
32 | end component;
33 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/sub32.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2003 Altera Corporation
 2 | --Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | --support information,  device programming or simulation file,  and any other
 4 | --associated  documentation or information  provided by  Altera  or a partner
 5 | --under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | --to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | --other  use  of such  megafunction  design,  netlist,  support  information,
 8 | --device programming or simulation file,  or any other  related documentation
 9 | --or information  is prohibited  for  any  other purpose,  including, but not
10 | --limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | --any other  silicon devices,  unless such use is  explicitly  licensed under
12 | --a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | --intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | --secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | --support  information,  device programming or simulation file,  or any other
16 | --related documentation or information provided by  Altera  or a megafunction
17 | --partner, remains with Altera, the megafunction partner, or their respective
18 | --licensors. No other licenses, including any licenses needed under any third
19 | --party's intellectual property, are provided herein.
20 | 
21 | 
22 | FUNCTION sub32 
23 | (
24 | 	dataa[31..0],
25 | 	datab[31..0],
26 | 	clock,
27 | 	aclr,
28 | 	clken
29 | )
30 | 
31 | RETURNS (
32 | 	result[31..0]
33 | );
34 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/sub32_bb.v:
--------------------------------------------------------------------------------
 1 | //Copyright (C) 1991-2003 Altera Corporation
 2 | //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | //support information,  device programming or simulation file,  and any other
 4 | //associated  documentation or information  provided by  Altera  or a partner
 5 | //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | //other  use  of such  megafunction  design,  netlist,  support  information,
 8 | //device programming or simulation file,  or any other  related documentation
 9 | //or information  is prohibited  for  any  other purpose,  including, but not
10 | //limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | //any other  silicon devices,  unless such use is  explicitly  licensed under
12 | //a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | //intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | //support  information,  device programming or simulation file,  or any other
16 | //related documentation or information provided by  Altera  or a megafunction
17 | //partner, remains with Altera, the megafunction partner, or their respective
18 | //licensors. No other licenses, including any licenses needed under any third
19 | //party's intellectual property, are provided herein.
20 | 
21 | module sub32 (
22 | 	dataa,
23 | 	datab,
24 | 	clock,
25 | 	aclr,
26 | 	clken,
27 | 	result)/* synthesis synthesis_clearbox = 1 */;
28 | 
29 | 	input	[31:0]  dataa;
30 | 	input	[31:0]  datab;
31 | 	input	  clock;
32 | 	input	  aclr;
33 | 	input	  clken;
34 | 	output	[31:0]  result;
35 | 
36 | endmodule
37 | 
38 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/megacells/sub32_inst.v:
--------------------------------------------------------------------------------
1 | sub32	sub32_inst (
2 | 	.dataa ( dataa_sig ),
3 | 	.datab ( datab_sig ),
4 | 	.clock ( clock_sig ),
5 | 	.aclr ( aclr_sig ),
6 | 	.clken ( clken_sig ),
7 | 	.result ( result_sig )
8 | 	);
9 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/bustri.v:
--------------------------------------------------------------------------------
 1 | 
 2 | // Model for tristate bus on altera
 3 | // FIXME do we really need to use a megacell for this?
 4 | 
 5 | module bustri (data,
 6 | 	       enabledt,
 7 | 	       tridata);
 8 |    
 9 |    input [15:0]  data;
10 |    input 	 enabledt;
11 |    inout [15:0]  tridata;
12 |    
13 |    assign 	 tridata = enabledt ? data :16'bz;
14 |    
15 | endmodule // bustri
16 | 
17 | 
18 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/fifo.v:
--------------------------------------------------------------------------------
 1 | // Model of FIFO in Altera
 2 | 
 3 | module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
 4 | 		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
 5 |    
 6 |    parameter width = 16;
 7 |    parameter depth = 1024;
 8 |    parameter addr_bits = 10;
 9 |    
10 |    //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
11 |    
12 |    input [width-1:0] data;
13 |    input 	     wrreq;
14 |    input 	     rdreq;
15 |    input 	     rdclk;
16 |    input 	     wrclk;
17 |    input 	     aclr;
18 |    output [width-1:0] q;
19 |    output 	      rdfull;
20 |    output 	      rdempty;
21 |    output reg [addr_bits-1:0]  rdusedw;
22 |    output wrfull;
23 |    output wrempty;
24 |    output reg [addr_bits-1:0]  wrusedw;
25 |    
26 |    reg [width-1:0] mem [0:depth-1];
27 |    reg [addr_bits-1:0] 	      rdptr;
28 |    reg [addr_bits-1:0] 	      wrptr;
29 |    
30 | `ifdef rd_req
31 |    reg [width-1:0]    q;
32 | `else
33 |    wire [width-1:0]   q;
34 | `endif
35 |    
36 |    integer 	      i;
37 |    
38 |    always @( aclr)
39 |      begin
40 | 	wrptr <= #1 0;
41 | 	rdptr <= #1 0;
42 | 	for(i=0;i<depth;i=i+1)
43 | 	  mem[i] <= #1 0;
44 |      end
45 |    
46 |    always @(posedge wrclk)
47 |      if(wrreq)
48 |        begin
49 | 	  wrptr <= #1 wrptr+1;
50 | 	  mem[wrptr] <= #1 data;
51 |        end
52 |    
53 |    always @(posedge rdclk)
54 |      if(rdreq)
55 |        begin
56 |    	  rdptr <= #1 rdptr+1;
57 | `ifdef rd_req
58 | 	  q <= #1 mem[rdptr];
59 | `endif
60 |        end
61 |    
62 | `ifdef rd_req
63 | `else
64 |    assign q = mem[rdptr];
65 | `endif
66 |    
67 |    // Fix these
68 |    always @(posedge wrclk)
69 |      wrusedw <= #1 wrptr - rdptr;
70 |    
71 |    always @(posedge rdclk)
72 |      rdusedw <= #1 wrptr - rdptr;
73 |    
74 |    assign wrempty = (wrusedw == 0);
75 |    assign wrfull = (wrusedw == depth-1);
76 |    
77 |    assign rdempty = (rdusedw == 0);
78 |    assign rdfull = (rdusedw == depth-1);
79 |    
80 | endmodule // fifo
81 | 
82 | 
83 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/fifo_1c_1k.v:
--------------------------------------------------------------------------------
 1 | // Model of FIFO in Altera
 2 | 
 3 | module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
 4 | 		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
 5 | 
 6 |    parameter width = 32;
 7 |    parameter depth = 1024;
 8 |    //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
 9 |       
10 |    input [31:0] data;
11 |    input 	wrreq;
12 |    input 	rdreq;
13 |    input 	rdclk;
14 |    input 	wrclk;
15 |    input 	aclr;
16 |    output [31:0] q;
17 |    output 	 rdfull;
18 |    output 	 rdempty;
19 |    output [9:0]  rdusedw;
20 |    output 	 wrfull;
21 |    output 	 wrempty;
22 |    output [9:0]  wrusedw;
23 |    
24 |    reg [width-1:0] mem [0:depth-1];
25 |    reg [7:0] 	   rdptr;
26 |    reg [7:0] 	   wrptr;
27 |    
28 | `ifdef rd_req
29 |    reg [width-1:0] q;
30 | `else
31 |    wire [width-1:0] q;
32 | `endif
33 |    
34 |    reg [9:0] 	    rdusedw;
35 |    reg [9:0] 	    wrusedw;
36 |    
37 |    integer 	    i;
38 | 
39 |    always @( aclr)
40 |      begin
41 | 	wrptr <= #1 0;
42 | 	rdptr <= #1 0;
43 | 	for(i=0;i<depth;i=i+1)
44 | 	  mem[i] <= #1 0;
45 |      end
46 |    
47 |    always @(posedge wrclk)
48 |      if(wrreq)
49 |        begin
50 | 	  wrptr <= #1 wrptr+1;
51 | 	  mem[wrptr] <= #1 data;
52 |        end
53 |    
54 |    always @(posedge rdclk)
55 |      if(rdreq)
56 |        begin
57 |    	  rdptr <= #1 rdptr+1;
58 | `ifdef rd_req
59 | 	  q <= #1 mem[rdptr];
60 | `endif
61 |        end
62 |    
63 | `ifdef rd_req
64 | `else
65 |    assign q = mem[rdptr];
66 | `endif
67 |    
68 |    // Fix these
69 |    always @(posedge wrclk)
70 |      wrusedw <= #1 wrptr - rdptr;
71 |    
72 |    always @(posedge rdclk)
73 |      rdusedw <= #1 wrptr - rdptr;
74 | 
75 |    assign wrempty = (wrusedw == 0);
76 |    assign wrfull = (wrusedw == depth-1);
77 | 
78 |    assign rdempty = (rdusedw == 0);
79 |    assign rdfull = (rdusedw == depth-1);
80 |    
81 | endmodule // fifo_1c_1k
82 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/fifo_1c_2k.v:
--------------------------------------------------------------------------------
 1 | // Model of FIFO in Altera
 2 | 
 3 | module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
 4 | 		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
 5 | 
 6 |    parameter width = 32;
 7 |    parameter depth = 2048;
 8 |    //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
 9 |       
10 |    input [31:0] data;
11 |    input 	wrreq;
12 |    input 	rdreq;
13 |    input 	rdclk;
14 |    input 	wrclk;
15 |    input 	aclr;
16 |    output [31:0] q;
17 |    output 	 rdfull;
18 |    output 	 rdempty;
19 |    output [10:0]  rdusedw;
20 |    output 	 wrfull;
21 |    output 	 wrempty;
22 |    output [10:0]  wrusedw;
23 |    
24 |    reg [width-1:0] mem [0:depth-1];
25 |    reg [7:0] 	   rdptr;
26 |    reg [7:0] 	   wrptr;
27 |    
28 | `ifdef rd_req
29 |    reg [width-1:0] q;
30 | `else
31 |    wire [width-1:0] q;
32 | `endif
33 |    
34 |    reg [10:0] 	    rdusedw;
35 |    reg [10:0] 	    wrusedw;
36 |    
37 |    integer 	    i;
38 | 
39 |    always @( aclr)
40 |      begin
41 | 	wrptr <= #1 0;
42 | 	rdptr <= #1 0;
43 | 	for(i=0;i<depth;i=i+1)
44 | 	  mem[i] <= #1 0;
45 |      end
46 |    
47 |    always @(posedge wrclk)
48 |      if(wrreq)
49 |        begin
50 | 	  wrptr <= #1 wrptr+1;
51 | 	  mem[wrptr] <= #1 data;
52 |        end
53 |    
54 |    always @(posedge rdclk)
55 |      if(rdreq)
56 |        begin
57 |    	  rdptr <= #1 rdptr+1;
58 | `ifdef rd_req
59 | 	  q <= #1 mem[rdptr];
60 | `endif
61 |        end
62 |    
63 | `ifdef rd_req
64 | `else
65 |    assign q = mem[rdptr];
66 | `endif
67 |    
68 |    // Fix these
69 |    always @(posedge wrclk)
70 |      wrusedw <= #1 wrptr - rdptr;
71 |    
72 |    always @(posedge rdclk)
73 |      rdusedw <= #1 wrptr - rdptr;
74 | 
75 |    assign wrempty = (wrusedw == 0);
76 |    assign wrfull = (wrusedw == depth-1);
77 |    
78 |    assign rdempty = (rdusedw == 0);
79 |    assign rdfull = (rdusedw == depth-1);
80 |    
81 | endmodule // fifo_1c_2k
82 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/fifo_1c_4k.v:
--------------------------------------------------------------------------------
 1 | // Model of FIFO in Altera
 2 | 
 3 | module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
 4 | 		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
 5 | 
 6 |    parameter width = 32;
 7 |    parameter depth = 4096;
 8 |    //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
 9 |       
10 |    input [31:0] data;
11 |    input 	wrreq;
12 |    input 	rdreq;
13 |    input 	rdclk;
14 |    input 	wrclk;
15 |    input 	aclr;
16 |    output [31:0] q;
17 |    output 	 rdfull;
18 |    output 	 rdempty;
19 |    output [7:0]  rdusedw;
20 |    output 	 wrfull;
21 |    output 	 wrempty;
22 |    output [7:0]  wrusedw;
23 |    
24 |    reg [width-1:0] mem [0:depth-1];
25 |    reg [7:0] 	   rdptr;
26 |    reg [7:0] 	   wrptr;
27 |    
28 | `ifdef rd_req
29 |    reg [width-1:0] q;
30 | `else
31 |    wire [width-1:0] q;
32 | `endif
33 |    
34 |    reg [7:0] 	    rdusedw;
35 |    reg [7:0] 	    wrusedw;
36 |    
37 |    integer 	    i;
38 | 
39 |    always @( aclr)
40 |      begin
41 | 	wrptr <= #1 0;
42 | 	rdptr <= #1 0;
43 | 	for(i=0;i<depth;i=i+1)
44 | 	  mem[i] <= #1 0;
45 |      end
46 |    
47 |    always @(posedge wrclk)
48 |      if(wrreq)
49 |        begin
50 | 	  wrptr <= #1 wrptr+1;
51 | 	  mem[wrptr] <= #1 data;
52 |        end
53 |    
54 |    always @(posedge rdclk)
55 |      if(rdreq)
56 |        begin
57 |    	  rdptr <= #1 rdptr+1;
58 | `ifdef rd_req
59 | 	  q <= #1 mem[rdptr];
60 | `endif
61 |        end
62 |    
63 | `ifdef rd_req
64 | `else
65 |    assign q = mem[rdptr];
66 | `endif
67 |    
68 |    // Fix these
69 |    always @(posedge wrclk)
70 |      wrusedw <= #1 wrptr - rdptr;
71 |    
72 |    always @(posedge rdclk)
73 |      rdusedw <= #1 wrptr - rdptr;
74 |    
75 |    
76 | endmodule // fifo_1c_4k
77 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/fifo_1k.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module fifo_1k
 4 |   (  input [15:0] data,
 5 |      input 	wrreq,
 6 |      input 	rdreq,
 7 |      input 	rdclk,
 8 |      input 	wrclk,
 9 |      input 	aclr,
10 |      output [15:0] q,
11 |      output 	 rdfull,
12 |      output 	 rdempty,
13 |      output [9:0] rdusedw,
14 |      output 	 wrfull,
15 |      output 	 wrempty,
16 |      output [9:0]  wrusedw
17 |      );
18 | 
19 | fifo #(.width(16),.depth(1024),.addr_bits(10)) fifo_1k 
20 |   ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
21 |     rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
22 |    
23 | endmodule // fifo_1k
24 |    
25 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/fifo_2k.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module fifo_2k
 4 |   (  input [15:0] data,
 5 |      input 	wrreq,
 6 |      input 	rdreq,
 7 |      input 	rdclk,
 8 |      input 	wrclk,
 9 |      input 	aclr,
10 |      output [15:0] q,
11 |      output 	 rdfull,
12 |      output 	 rdempty,
13 |      output [10:0] rdusedw,
14 |      output 	 wrfull,
15 |      output 	 wrempty,
16 |      output [10:0]  wrusedw
17 |      );
18 | 
19 | fifo #(.width(16),.depth(2048),.addr_bits(11)) fifo_2k 
20 |   ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
21 |     rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
22 |    
23 | endmodule // fifo_1k
24 |    
25 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/fifo_4k.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module fifo_4k
 4 |   (  input [15:0] data,
 5 |      input 	wrreq,
 6 |      input 	rdreq,
 7 |      input 	rdclk,
 8 |      input 	wrclk,
 9 |      input 	aclr,
10 |      output [15:0] q,
11 |      output 	 rdfull,
12 |      output 	 rdempty,
13 |      output [11:0] rdusedw,
14 |      output 	 wrfull,
15 |      output 	 wrempty,
16 |      output [11:0]  wrusedw
17 |      );
18 | 
19 | fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k 
20 |   ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
21 |     rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
22 |    
23 | endmodule // fifo_1k
24 |    
25 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/fifo_4k_18.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module fifo_4k_18
 4 |   (input  [17:0] data,
 5 |    input         wrreq,
 6 |    input         wrclk,
 7 |    output 	 wrfull,
 8 |    output 	 wrempty,
 9 |    output [11:0] wrusedw,
10 | 
11 |    output [17:0] q,
12 |    input         rdreq,
13 |    input         rdclk,
14 |    output 	 rdfull,
15 |    output 	 rdempty,
16 |    output [11:0] rdusedw,
17 | 
18 |    input 	 aclr );
19 | 
20 | fifo #(.width(18),.depth(4096),.addr_bits(12)) fifo_4k 
21 |   ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
22 |     rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
23 |    
24 | endmodule // fifo_4k_18
25 | 
26 |    
27 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/pll.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2003 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | // Very simple model for the PLL in the RX buffer
23 | 
24 | module pll (inclk0,c0);
25 |    
26 |    input	  inclk0;
27 |    output	  c0;
28 | 
29 |    assign 	  c0 = #9 inclk0;
30 |       
31 | endmodule // pll
32 | 
33 | 
34 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/models/ssram.v:
--------------------------------------------------------------------------------
 1 | 
 2 | // Model of Pipelined [ZBT] Synchronous SRAM
 3 | 
 4 | module ssram(clock,addr,data,wen,ce);
 5 |    parameter addrbits = 19;
 6 |    parameter depth = 524288;
 7 | 
 8 |    input clock;
 9 |    input [addrbits-1:0] addr;
10 |    inout [35:0] data;
11 |    input wen;
12 |    input ce;
13 | 
14 |    reg [35:0] ram [0:depth-1];
15 |    
16 |    reg read_d1,read_d2;
17 |    reg write_d1,write_d2;
18 |    reg [addrbits-1:0] addr_d1,addr_d2;
19 |    
20 |    always @(posedge clock)
21 |      begin
22 | 	read_d1 <= #1 ce & ~wen;
23 | 	write_d1 <= #1 ce & wen;
24 | 	addr_d1 <= #1 addr;
25 | 	read_d2 <= #1 read_d1;
26 | 	write_d2 <= #1 write_d1;
27 | 	addr_d2 <= #1 addr_d1;
28 | 	if(write_d2)
29 | 	  ram[addr_d2] = data;
30 |      end // always @ (posedge clock)
31 | 
32 |    data = (ce & read_d2) ? ram[addr_d2] : 36'bz;
33 | 
34 |    always @(posedge clock)
35 |      if(~ce & (write_d2 | write_d1 | wen))
36 |        $display("$time ERROR:  RAM CE not asserted during write cycle");
37 |    
38 | endmodule // ssram
39 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/atr_delay.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2007 Corgan Enterprises LLC
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
23 |    input        clk_i;
24 |    input        rst_i;
25 |    input        ena_i;
26 |    input        tx_empty_i;
27 |    input [11:0] tx_delay_i;
28 |    input [11:0] rx_delay_i;
29 |    output       atr_tx_o;
30 | 
31 |    reg [3:0] 	state;
32 |    reg [11:0] 	count;
33 | 
34 |    `define ST_RX_DELAY 4'b0001
35 |    `define ST_RX       4'b0010
36 |    `define ST_TX_DELAY 4'b0100
37 |    `define ST_TX       4'b1000
38 | 
39 |    always @(posedge clk_i)
40 |      if (rst_i | ~ena_i)
41 |        begin
42 | 	  state <= `ST_RX;
43 | 	  count <= 12'b0;
44 |        end
45 |      else
46 |        case (state)
47 | 	 `ST_RX:
48 | 	   if (!tx_empty_i)
49 | 	     begin
50 | 		state <= `ST_TX_DELAY;
51 | 		count <= tx_delay_i;
52 | 	     end
53 | 
54 | 	 `ST_TX_DELAY:
55 | 	   if (count == 0)
56 | 	     state <= `ST_TX;
57 | 	   else
58 | 	     count <= count - 1;
59 | 
60 | 	 `ST_TX:
61 | 	   if (tx_empty_i)
62 | 	     begin
63 | 		state <= `ST_RX_DELAY;
64 | 		count <= rx_delay_i;
65 | 	     end
66 | 
67 | 	 `ST_RX_DELAY:
68 | 	   if (count == 0)
69 | 	     state <= `ST_RX;
70 | 	   else
71 | 	     count <= count - 1;
72 | 	 
73 | 	 default:		// Error
74 | 	   begin
75 | 	      state <= `ST_RX;
76 | 	      count <= 0;
77 | 	   end
78 |        endcase
79 |    
80 |    assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
81 |    
82 | endmodule // atr_delay
83 | 
84 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/bidir_reg.v:
--------------------------------------------------------------------------------
 1 | // Bidirectional registers
 2 | 
 3 | module bidir_reg
 4 |   ( inout wire [15:0] tristate,
 5 |     input wire [15:0] oe,
 6 |     input wire [15:0] reg_val );
 7 | 
 8 |    // This would be much cleaner if all the tools
 9 |    // supported "for generate"........
10 | 
11 |    assign 	 tristate[0] = oe[0] ? reg_val[0] : 1'bz;
12 |    assign 	 tristate[1] = oe[1] ? reg_val[1] : 1'bz;
13 |    assign 	 tristate[2] = oe[2] ? reg_val[2] : 1'bz;
14 |    assign 	 tristate[3] = oe[3] ? reg_val[3] : 1'bz;
15 |    assign 	 tristate[4] = oe[4] ? reg_val[4] : 1'bz;
16 |    assign 	 tristate[5] = oe[5] ? reg_val[5] : 1'bz;
17 |    assign 	 tristate[6] = oe[6] ? reg_val[6] : 1'bz;
18 |    assign 	 tristate[7] = oe[7] ? reg_val[7] : 1'bz;
19 |    assign 	 tristate[8] = oe[8] ? reg_val[8] : 1'bz;
20 |    assign 	 tristate[9] = oe[9] ? reg_val[9] : 1'bz;
21 |    assign 	 tristate[10] = oe[10] ? reg_val[10] : 1'bz;
22 |    assign 	 tristate[11] = oe[11] ? reg_val[11] : 1'bz;
23 |    assign 	 tristate[12] = oe[12] ? reg_val[12] : 1'bz;
24 |    assign 	 tristate[13] = oe[13] ? reg_val[13] : 1'bz;
25 |    assign 	 tristate[14] = oe[14] ? reg_val[14] : 1'bz;
26 |    assign 	 tristate[15] = oe[15] ? reg_val[15] : 1'bz;
27 |    
28 | endmodule // bidir_reg
29 | 
30 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/clk_divider.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2003 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | 
23 | module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
24 |    reg [7:0] counter;
25 |    
26 |    // FIXME maybe should use PLL or switch to double edge version	
27 | 	
28 |    always @(posedge in_clk or posedge reset)
29 |      if(reset)
30 |        counter <= #1 8'd0;
31 |      else if(counter == 0)
32 |        counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
33 |      else
34 |        counter <= #1 counter-8'd1;
35 |    
36 |    always @(posedge in_clk or posedge reset)
37 |      if(reset)
38 |        out_clk <= #1 1'b0;
39 |      else if(counter == 0)
40 |        out_clk <= #1 ~out_clk;
41 |    
42 | endmodule // clk_divider
43 | 
44 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/cordic_stage.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2003 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
23 |    parameter bitwidth = 16;
24 |    parameter zwidth = 16;
25 |    parameter shift = 1;
26 |    
27 |    input     clock;
28 |    input     reset;
29 |    input     enable;
30 |    input [bitwidth-1:0] xi,yi;
31 |    input [zwidth-1:0] zi;
32 |    input [zwidth-1:0] constant;
33 |    output [bitwidth-1:0] xo,yo;
34 |    output [zwidth-1:0] zo;
35 |    
36 |    wire z_is_pos = ~zi[zwidth-1];
37 | 
38 |    reg [bitwidth-1:0] 	 xo,yo;
39 |    reg [zwidth-1:0] zo;
40 |    
41 |    always @(posedge clock)
42 |      if(reset)
43 |        begin
44 | 	  xo <= #1 0;
45 | 	  yo <= #1 0;
46 | 	  zo <= #1 0;
47 |        end
48 |      else if(enable)
49 |        begin
50 | 	  xo <= #1 z_is_pos ?   
51 | 		xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
52 | 		xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
53 | 	  yo <= #1 z_is_pos ?   
54 | 		yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
55 | 		yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
56 | 	  zo <= #1 z_is_pos ?   
57 | 		zi - constant :
58 | 		zi + constant;
59 |        end
60 | endmodule
61 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/dpram.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2003 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | 
23 | 
24 | module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
25 |    parameter depth = 4;
26 |    parameter width = 16;
27 |    parameter size = 16;
28 |    
29 |    input wclk;
30 |    input [width-1:0] wdata;
31 |    input [depth-1:0] waddr;
32 |    input 	     wen;
33 | 
34 |    input rclk;
35 |    output reg [width-1:0] rdata;
36 |    input [depth-1:0]  raddr;
37 |    
38 |    reg [width-1:0]    ram [0:size-1];
39 |    
40 |    always @(posedge wclk)
41 |      if(wen)
42 |        ram[waddr] <= #1 wdata;
43 |    
44 |    always @(posedge rclk)
45 |      rdata <= #1 ram[raddr];
46 |    
47 | endmodule // dpram
48 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/fifo_1kx16.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2006 Altera Corporation
 2 | --Your use of Altera Corporation's design tools, logic functions 
 3 | --and other software and tools, and its AMPP partner logic 
 4 | --functions, and any output files any of the foregoing 
 5 | --(including device programming or simulation files), and any 
 6 | --associated documentation or information are expressly subject 
 7 | --to the terms and conditions of the Altera Program License 
 8 | --Subscription Agreement, Altera MegaCore Function License 
 9 | --Agreement, or other applicable license agreement, including, 
10 | --without limitation, that your use is for the sole purpose of 
11 | --programming logic devices manufactured by Altera and sold by 
12 | --Altera or its authorized distributors.  Please refer to the 
13 | --applicable agreement for further details.
14 | 
15 | 
16 | component fifo_1kx16
17 | 	PORT
18 | 	(
19 | 		aclr		: IN STD_LOGIC ;
20 | 		clock		: IN STD_LOGIC ;
21 | 		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
22 | 		rdreq		: IN STD_LOGIC ;
23 | 		wrreq		: IN STD_LOGIC ;
24 | 		almost_empty		: OUT STD_LOGIC ;
25 | 		empty		: OUT STD_LOGIC ;
26 | 		full		: OUT STD_LOGIC ;
27 | 		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
28 | 		usedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
29 | 	);
30 | end component;
31 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/fifo_1kx16.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2006 Altera Corporation
 2 | --Your use of Altera Corporation's design tools, logic functions 
 3 | --and other software and tools, and its AMPP partner logic 
 4 | --functions, and any output files any of the foregoing 
 5 | --(including device programming or simulation files), and any 
 6 | --associated documentation or information are expressly subject 
 7 | --to the terms and conditions of the Altera Program License 
 8 | --Subscription Agreement, Altera MegaCore Function License 
 9 | --Agreement, or other applicable license agreement, including, 
10 | --without limitation, that your use is for the sole purpose of 
11 | --programming logic devices manufactured by Altera and sold by 
12 | --Altera or its authorized distributors.  Please refer to the 
13 | --applicable agreement for further details.
14 | 
15 | 
16 | FUNCTION fifo_1kx16 
17 | (
18 | 	aclr,
19 | 	clock,
20 | 	data[15..0],
21 | 	rdreq,
22 | 	wrreq
23 | )
24 | 
25 | RETURNS (
26 | 	almost_empty,
27 | 	empty,
28 | 	full,
29 | 	q[15..0],
30 | 	usedw[9..0]
31 | );
32 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/fifo_1kx16_inst.v:
--------------------------------------------------------------------------------
 1 | fifo_1kx16	fifo_1kx16_inst (
 2 | 	.aclr ( aclr_sig ),
 3 | 	.clock ( clock_sig ),
 4 | 	.data ( data_sig ),
 5 | 	.rdreq ( rdreq_sig ),
 6 | 	.wrreq ( wrreq_sig ),
 7 | 	.almost_empty ( almost_empty_sig ),
 8 | 	.empty ( empty_sig ),
 9 | 	.full ( full_sig ),
10 | 	.q ( q_sig ),
11 | 	.usedw ( usedw_sig )
12 | 	);
13 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/fifo_4kx16_dc.cmp:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2006 Altera Corporation
 2 | --Your use of Altera Corporation's design tools, logic functions 
 3 | --and other software and tools, and its AMPP partner logic 
 4 | --functions, and any output files any of the foregoing 
 5 | --(including device programming or simulation files), and any 
 6 | --associated documentation or information are expressly subject 
 7 | --to the terms and conditions of the Altera Program License 
 8 | --Subscription Agreement, Altera MegaCore Function License 
 9 | --Agreement, or other applicable license agreement, including, 
10 | --without limitation, that your use is for the sole purpose of 
11 | --programming logic devices manufactured by Altera and sold by 
12 | --Altera or its authorized distributors.  Please refer to the 
13 | --applicable agreement for further details.
14 | 
15 | 
16 | component fifo_4kx16_dc
17 | 	PORT
18 | 	(
19 | 		aclr		: IN STD_LOGIC  := '0';
20 | 		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
21 | 		rdclk		: IN STD_LOGIC ;
22 | 		rdreq		: IN STD_LOGIC ;
23 | 		wrclk		: IN STD_LOGIC ;
24 | 		wrreq		: IN STD_LOGIC ;
25 | 		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
26 | 		rdempty		: OUT STD_LOGIC ;
27 | 		rdusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
28 | 		wrfull		: OUT STD_LOGIC ;
29 | 		wrusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
30 | 	);
31 | end component;
32 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/fifo_4kx16_dc.inc:
--------------------------------------------------------------------------------
 1 | --Copyright (C) 1991-2006 Altera Corporation
 2 | --Your use of Altera Corporation's design tools, logic functions 
 3 | --and other software and tools, and its AMPP partner logic 
 4 | --functions, and any output files any of the foregoing 
 5 | --(including device programming or simulation files), and any 
 6 | --associated documentation or information are expressly subject 
 7 | --to the terms and conditions of the Altera Program License 
 8 | --Subscription Agreement, Altera MegaCore Function License 
 9 | --Agreement, or other applicable license agreement, including, 
10 | --without limitation, that your use is for the sole purpose of 
11 | --programming logic devices manufactured by Altera and sold by 
12 | --Altera or its authorized distributors.  Please refer to the 
13 | --applicable agreement for further details.
14 | 
15 | 
16 | FUNCTION fifo_4kx16_dc 
17 | (
18 | 	aclr,
19 | 	data[15..0],
20 | 	rdclk,
21 | 	rdreq,
22 | 	wrclk,
23 | 	wrreq
24 | )
25 | 
26 | RETURNS (
27 | 	q[15..0],
28 | 	rdempty,
29 | 	rdusedw[11..0],
30 | 	wrfull,
31 | 	wrusedw[11..0]
32 | );
33 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/fifo_4kx16_dc_inst.v:
--------------------------------------------------------------------------------
 1 | fifo_4kx16_dc	fifo_4kx16_dc_inst (
 2 | 	.aclr ( aclr_sig ),
 3 | 	.data ( data_sig ),
 4 | 	.rdclk ( rdclk_sig ),
 5 | 	.rdreq ( rdreq_sig ),
 6 | 	.wrclk ( wrclk_sig ),
 7 | 	.wrreq ( wrreq_sig ),
 8 | 	.q ( q_sig ),
 9 | 	.rdempty ( rdempty_sig ),
10 | 	.rdusedw ( rdusedw_sig ),
11 | 	.wrfull ( wrfull_sig ),
12 | 	.wrusedw ( wrusedw_sig )
13 | 	);
14 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/gen_cordic_consts.py:
--------------------------------------------------------------------------------
 1 | #!/usr/bin/env python
 2 | 
 3 | import math
 4 | 
 5 | zwidth = 16
 6 | 
 7 | for i in range(17):
 8 |     c = math.atan (1.0/(2**i)) / (2 * math.pi) * (1 << zwidth)
 9 |     print "`define c%02d %d'd%d" % (i, zwidth, round (c))
10 |     
11 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/gen_sync.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2003 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | module gen_sync
23 |   ( input clock,
24 |     input reset,
25 |     input enable,
26 |     input [7:0] rate,
27 |     output wire sync );
28 |    
29 | //   parameter width = 8;
30 |    
31 |    reg [7:0] counter;
32 |    assign sync = |(((rate+1)>>1)& counter);
33 |       
34 |    always @(posedge clock)
35 |      if(reset || ~enable)
36 |        counter <= #1 0;
37 |      else if(counter == rate)
38 |        counter <= #1 0;
39 |      else 
40 |        counter <= #1 counter + 8'd1;
41 |    
42 | endmodule // gen_sync
43 | 
44 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/hb/acc.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module acc (input clock, input reset, input clear, input enable_in, output reg enable_out,
 4 | 	    input signed [30:0] addend, output reg signed [33:0] sum );
 5 | 
 6 |    always @(posedge clock)
 7 |      if(reset)
 8 |        sum <= #1 34'd0;
 9 |      //else if(clear & enable_in)
10 |      //  sum <= #1 addend;
11 |      //else if(clear)
12 |      //  sum <= #1 34'd0;
13 |      else if(clear)
14 |        sum <= #1 addend;
15 |      else if(enable_in)
16 |        sum <= #1 sum + addend;
17 | 
18 |    always @(posedge clock)
19 |      enable_out <= #1 enable_in;
20 |    
21 | endmodule // acc
22 | 
23 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/hb/coeff_rom.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);
 4 | 
 5 |    always @(posedge clock)
 6 |      case (addr)
 7 |        3'd0 : data <= #1 -16'd49;
 8 |        3'd1 : data <= #1 16'd165;
 9 |        3'd2 : data <= #1 -16'd412;
10 |        3'd3 : data <= #1 16'd873;
11 |        3'd4 : data <= #1 -16'd1681;
12 |        3'd5 : data <= #1 16'd3135;
13 |        3'd6 : data <= #1 -16'd6282;
14 |        3'd7 : data <= #1 16'd20628;
15 |      endcase // case(addr)
16 |       
17 | endmodule // coeff_rom
18 | 
19 | 
20 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/hb/mac.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module mac (input clock, input reset, input enable, input clear,
 4 | 	    input signed [15:0] x, input signed [15:0] y,
 5 | 	    input [7:0] shift, output [15:0] z );
 6 | 
 7 |    reg signed [30:0] product;
 8 |    reg signed [39:0] z_int;
 9 |    reg signed [15:0] z_shift;
10 | 
11 |    reg enable_d1;
12 |    always @(posedge clock)
13 |      enable_d1 <= #1 enable;
14 |    
15 |    always @(posedge clock)
16 |      if(reset | clear)
17 |        z_int <= #1 40'd0;
18 |      else if(enable_d1)
19 |        z_int <= #1 z_int + {{9{product[30]}},product};
20 | 
21 |    always @(posedge clock)
22 |      product <= #1 x*y;
23 | 
24 |    always @*   // FIXME full case? parallel case?
25 |      case(shift)
26 |        //8'd0 : z_shift <= z_int[39:24];
27 |        //8'd1 : z_shift <= z_int[38:23];
28 |        //8'd2 : z_shift <= z_int[37:22];
29 |        //8'd3 : z_shift <= z_int[36:21];
30 |        //8'd4 : z_shift <= z_int[35:20];
31 |        //8'd5 : z_shift <= z_int[34:19];
32 |        8'd6 : z_shift <= z_int[33:18];
33 |        8'd7 : z_shift <= z_int[32:17];
34 |        8'd8 : z_shift <= z_int[31:16];
35 |        8'd9 : z_shift <= z_int[30:15];
36 |        8'd10 : z_shift <= z_int[29:14];
37 |        8'd11 : z_shift <= z_int[28:13];
38 |        //8'd12 : z_shift <= z_int[27:12];
39 |        //8'd13 : z_shift <= z_int[26:11];
40 |        //8'd14 : z_shift <= z_int[25:10];
41 |        //8'd15 : z_shift <= z_int[24:9];
42 |        //8'd16 : z_shift <= z_int[23:8];
43 |        //8'd17 : z_shift <= z_int[22:7];
44 |        //8'd18 : z_shift <= z_int[21:6];
45 |        //8'd19 : z_shift <= z_int[20:5];
46 |        //8'd20 : z_shift <= z_int[19:4];
47 |        //8'd21 : z_shift <= z_int[18:3];
48 |        //8'd22 : z_shift <= z_int[17:2];
49 |        //8'd23 : z_shift <= z_int[16:1];
50 |        //8'd24 : z_shift <= z_int[15:0];
51 |        default : z_shift <= z_int[15:0];
52 |      endcase // case(shift)
53 |    
54 |    // FIXME do we need to saturate?
55 |    //assign z = z_shift;
56 |    assign z = z_int[15:0];
57 |    
58 | endmodule // mac
59 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/hb/mult.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product,
 4 | 	     input enable_in, output reg enable_out );
 5 | 
 6 |    always @(posedge clock)
 7 |      if(enable_in)
 8 |        product <= #1 x*y;
 9 |      else
10 |        product <= #1 31'd0;
11 |    
12 |    always @(posedge clock)
13 |      enable_out <= #1 enable_in;
14 |    
15 | endmodule // mult
16 | 
17 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/hb/ram16_2port.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module ram16_2port (input clock, input write, 
 4 | 		    input [3:0] wr_addr, input [15:0] wr_data,
 5 | 		    input [3:0] rd_addr1, output reg [15:0] rd_data1,
 6 | 		    input [3:0] rd_addr2, output reg [15:0] rd_data2);
 7 |    
 8 |    reg [15:0] 			ram_array [0:31];
 9 |    
10 |    always @(posedge clock)
11 |      rd_data1 <= #1 ram_array[rd_addr1];
12 |    
13 |    always @(posedge clock)
14 |      rd_data2 <= #1 ram_array[rd_addr2];
15 |    
16 |    always @(posedge clock)
17 |      if(write)
18 |        ram_array[wr_addr] <= #1 wr_data;
19 |    
20 | endmodule // ram16_2port
21 | 
22 | 
23 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/hb/ram16_2sum.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module ram16_2sum (input clock, input write, 
 4 | 		   input [3:0] wr_addr, input [15:0] wr_data,
 5 | 		   input [3:0] rd_addr1, input [3:0] rd_addr2,
 6 |                    output reg [15:0] sum);
 7 |    
 8 |    reg signed [15:0] 	  ram_array [0:15];
 9 |    reg signed [15:0] 	  a,b;
10 |    wire signed [16:0] 	  sum_int;
11 |    
12 |    always @(posedge clock)
13 |      if(write)
14 |        ram_array[wr_addr] <= #1 wr_data;
15 |       
16 |    always @(posedge clock)
17 |      begin
18 | 	a <= #1 ram_array[rd_addr1];
19 | 	b <= #1 ram_array[rd_addr2];
20 |      end
21 |    
22 |    assign sum_int = {a[15],a} + {b[15],b};
23 |    
24 |    always @(posedge clock)
25 |      sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
26 |      
27 | endmodule // ram16_2sum
28 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/hb/ram32_2sum.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module ram32_2sum (input clock, input write, 
 4 | 		   input [4:0] wr_addr, input [15:0] wr_data,
 5 | 		   input [4:0] rd_addr1, input [4:0] rd_addr2,
 6 | 		   output reg [15:0] sum);
 7 |    
 8 |    reg [15:0] 			ram_array [0:31];
 9 |    wire [16:0] 			sum_int;
10 |    
11 |    always @(posedge clock)
12 |      if(write)
13 |        ram_array[wr_addr] <= #1 wr_data;
14 | 
15 |    assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];
16 | 
17 |    always @(posedge clock)
18 |      sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
19 | 
20 |    
21 | endmodule // ram32_2sum
22 | 
23 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/io_pins.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2005,2006 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | `include "../../firmware/include/fpga_regs_common.v"
23 | `include "../../firmware/include/fpga_regs_standard.v"
24 | 
25 | module io_pins
26 |   ( inout wire [15:0] io_0, inout wire [15:0] io_1,
27 |     input wire [15:0] reg_0, input wire [15:0] reg_1, 
28 |     input clock, input rx_reset, input tx_reset,
29 |     input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
30 |    
31 |    reg [15:0] io_0_oe,io_1_oe;
32 |    
33 |    bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
34 |    bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
35 |     
36 |    // Upper 16 bits are mask for lower 16
37 |    always @(posedge clock)
38 |      if(serial_strobe)
39 |        case(serial_addr)
40 | 	 `FR_OE_0 : io_0_oe
41 | 	   <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
42 | 	 `FR_OE_1 : io_1_oe
43 | 	   <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
44 | 	   endcase // case(serial_addr)
45 | 
46 | endmodule // io_pins
47 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/phase_acc.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2003 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | 
23 | 
24 | // Basic Phase accumulator for DDS
25 | 
26 | 
27 | module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);   
28 |    parameter FREQADDR = 0;
29 |    parameter PHASEADDR = 0;
30 |    parameter resolution = 32;
31 |    
32 |    input     clk, reset, enable, strobe;
33 |    input [6:0] serial_addr;
34 |    input [31:0] serial_data;
35 |    input 	serial_strobe;
36 |    
37 |    output reg [resolution-1:0] phase;
38 |    wire [resolution-1:0] freq;
39 | 
40 |    setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
41 | 
42 |    always @(posedge clk)
43 |      if(reset)
44 |        phase <= #1 32'b0;
45 |      else if(serial_strobe & (serial_addr == PHASEADDR))
46 |        phase <= #1 serial_data;
47 |      else if(enable & strobe)
48 |        phase <= #1 phase + freq;
49 | 
50 | endmodule // phase_acc
51 | 
52 |    
53 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/ram.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module ram (input clock, input write, 
 4 | 	    input [4:0] wr_addr, input [15:0] wr_data,
 5 | 	    input [4:0] rd_addr, output reg [15:0] rd_data);
 6 | 
 7 |    reg [15:0] 		ram_array [0:31];
 8 | 
 9 |    always @(posedge clock)
10 |      rd_data <= #1 ram_array[rd_addr];
11 | 
12 |    always @(posedge clock)
13 |      if(write)
14 |        ram_array[wr_addr] <= #1 wr_data;
15 | 
16 | endmodule // ram
17 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/ram16.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module ram16 (input clock, input write, 
 4 | 	      input [3:0] wr_addr, input [15:0] wr_data,
 5 | 	      input [3:0] rd_addr, output reg [15:0] rd_data);
 6 | 
 7 |    reg [15:0] 		ram_array [0:15];
 8 | 
 9 |    always @(posedge clock)
10 |      rd_data <= #1 ram_array[rd_addr];
11 | 
12 |    always @(posedge clock)
13 |      if(write)
14 |        ram_array[wr_addr] <= #1 wr_data;
15 | 
16 | endmodule // ram16
17 | 
18 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/ram32.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module ram32 (input clock, input write, 
 4 | 	      input [4:0] wr_addr, input [15:0] wr_data,
 5 | 	      input [4:0] rd_addr, output reg [15:0] rd_data);
 6 | 
 7 |    reg [15:0] 		ram_array [0:31];
 8 | 
 9 |    always @(posedge clock)
10 |      rd_data <= #1 ram_array[rd_addr];
11 | 
12 |    always @(posedge clock)
13 |      if(write)
14 |        ram_array[wr_addr] <= #1 wr_data;
15 | 
16 | endmodule // ram32
17 | 
18 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/ram64.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module ram64 (input clock, input write, 
 4 | 	      input [5:0] wr_addr, input [15:0] wr_data,
 5 | 	      input [5:0] rd_addr, output reg [15:0] rd_data);
 6 | 
 7 |    reg [15:0] 		ram_array [0:63];
 8 | 
 9 |    always @(posedge clock)
10 |      rd_data <= #1 ram_array[rd_addr];
11 | 
12 |    always @(posedge clock)
13 |      if(write)
14 |        ram_array[wr_addr] <= #1 wr_data;
15 | 
16 | endmodule // ram64
17 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/rssi.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module rssi (input clock, input reset, input enable,
 4 | 	     input [11:0] adc, output [15:0] rssi, output [15:0] over_count);
 5 | 
 6 |    wire 		  over_hi = (adc == 12'h7FF);
 7 |    wire 		  over_lo = (adc == 12'h800);
 8 |    wire 		  over = over_hi | over_lo;
 9 | 
10 |    reg [25:0] 		  over_count_int;
11 |    always @(posedge clock)
12 |      if(reset | ~enable)
13 |        over_count_int <= #1 26'd0;
14 |      else
15 |        over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10];
16 |    
17 |    assign      over_count = over_count_int[25:10];
18 |    
19 |    wire [11:0] abs_adc = adc[11] ? ~adc : adc;
20 | 
21 |    reg [25:0]  rssi_int;
22 |    always @(posedge clock)
23 |      if(reset | ~enable)
24 |        rssi_int <= #1 26'd0;
25 |      else
26 |        rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
27 | 
28 |    assign      rssi = rssi_int[25:10];
29 |    
30 | endmodule // rssi
31 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/rx_dcoffset.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module rx_dcoffset (input clock, input enable, input reset, 
 4 | 		    input signed [15:0] adc_in, output signed [15:0] adc_out,
 5 | 		    input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe);
 6 |    parameter 		  MYADDR = 0;
 7 |    
 8 |    reg signed [31:0] 		 integrator;
 9 |    wire signed [15:0] 		 scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]);
10 |    assign 			 adc_out = adc_in - scaled_integrator;
11 | 
12 |    // FIXME do we need signed?
13 |    //FIXME  What do we do when clipping?
14 |    always @(posedge clock)
15 |      if(reset)
16 |        integrator <= #1 32'd0;
17 |      else if(serial_strobe & (MYADDR == serial_addr))
18 |        integrator <= #1 {serial_data[15:0],16'd0};
19 |      else if(enable)
20 |        integrator <= #1 integrator + adc_out;
21 | 
22 | endmodule // rx_dcoffset
23 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/setting_reg.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module setting_reg
 4 |   ( input clock, input reset, input strobe, input wire [6:0] addr,
 5 |     input wire [31:0] in, output reg [31:0] out, output reg changed);
 6 |    parameter my_addr = 0;
 7 |    
 8 |    always @(posedge clock)
 9 |      if(reset)
10 |        begin
11 | 	  out <= #1 32'd0;
12 | 	  changed <= #1 1'b0;
13 |        end
14 |      else
15 |        if(strobe & (my_addr==addr))
16 | 	 begin
17 | 	    out <= #1 in;
18 | 	    changed <= #1 1'b1;
19 | 	 end
20 |        else
21 | 	 changed <= #1 1'b0;
22 |    
23 | endmodule // setting_reg
24 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/setting_reg_masked.v:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | module setting_reg_masked
 4 |   ( input clock, input reset, input strobe, input wire [6:0] addr,
 5 |     input wire [31:0] in, output reg [31:0] out, output reg changed);
 6 | /* upper 16 bits are mask, lower 16 bits are value 
 7 |  * Note that you get a 16 bit register, not a 32 bit one */
 8 | 
 9 |    parameter my_addr = 0;
10 |    
11 |    always @(posedge clock)
12 |      if(reset)
13 |        begin
14 | 	  out <= #1 32'd0;
15 | 	  changed <= #1 1'b0;
16 |        end
17 |      else
18 |        if(strobe & (my_addr==addr))
19 | 	 begin
20 | 	    out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );
21 | 	    changed <= #1 1'b1;
22 | 	 end
23 |        else
24 | 	 changed <= #1 1'b0;
25 |    
26 | endmodule // setting_reg_masked
27 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/sign_extend.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2003 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | 
23 | // Sign extension "macro"
24 | // bits_out should be greater than bits_in
25 | 
26 | module sign_extend (in,out);
27 | 	parameter bits_in=0;  // FIXME Quartus insists on a default
28 | 	parameter bits_out=0;
29 | 	
30 | 	input [bits_in-1:0] in;
31 | 	output [bits_out-1:0] out;
32 | 	
33 | 	assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
34 | 	
35 | endmodule
36 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/strobe_gen.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2003 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | 
23 | 
24 | module strobe_gen 
25 |   ( input clock,
26 |     input reset,
27 |     input enable,
28 |     input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
29 |     input strobe_in,
30 |     output wire strobe );
31 |    
32 | //   parameter width = 8;
33 |    
34 |    reg [7:0] counter;
35 |    assign strobe = ~|counter && enable && strobe_in;
36 |    
37 |    always @(posedge clock)
38 |      if(reset | ~enable)
39 |        counter <= #1 8'd0;
40 |      else if(strobe_in)
41 |        if(counter == 0)
42 | 	 counter <= #1 rate;
43 |        else 
44 | 	 counter <= #1 counter - 8'd1;
45 |    
46 | endmodule // strobe_gen
47 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/sdr_lib/tx_chain.v:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2003 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | module tx_chain
23 |   (input clock,
24 |    input reset,
25 |    input enable,
26 |    input wire [7:0] interp_rate,
27 |    input sample_strobe,
28 |    input interpolator_strobe,
29 |    input wire [31:0] freq,
30 |    input wire [15:0] i_in,
31 |    input wire [15:0] q_in,
32 |    output wire [15:0] i_out,
33 |    output wire [15:0] q_out
34 |    );
35 | 
36 |    wire [15:0] bb_i, bb_q;
37 | 
38 |    cic_interp cic_interp_i
39 |      ( .clock(clock),.reset(reset),.enable(enable),
40 |        .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
41 |        .signal_in(i_in),.signal_out(bb_i) );
42 | 
43 |    cic_interp cic_interp_q
44 |      ( .clock(clock),.reset(reset),.enable(enable),
45 |        .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
46 |        .signal_in(q_in),.signal_out(bb_q) );
47 |    
48 | `define NOCORDIC_TX
49 | `ifdef NOCORDIC_TX
50 |    assign      i_out = bb_i;
51 |    assign      q_out = bb_q;
52 | `else
53 |    wire [31:0] phase;
54 | 
55 |    phase_acc phase_acc_tx
56 |      (.clk(clock),.reset(reset),.enable(enable),
57 |       .strobe(sample_strobe),.freq(freq),.phase(phase) );
58 |    
59 |    cordic tx_cordic_0
60 |      ( .clock(clock),.reset(reset),.enable(sample_strobe), 
61 |        .xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
62 |        .xo(i_out),.yo(q_out),.zo() );
63 | `endif
64 | 
65 | endmodule // tx_chain
66 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/toplevel/include/common_config_1rxhb_1tx.vh:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2006 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | // ------------------------------------------------------------
23 | // If TX_ON is not defined, there is *no* transmit circuitry built
24 |   `define TX_ON
25 | 
26 | // ------------------------------------------------------------
27 | // Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
28 | // to respectively enable 1, 2 or 4 transmit channels.
29 | // [Please note that only TX_SINGLE and TX_DUAL are currently valid]
30 |   `define TX_SINGLE
31 | //`define TX_DUAL
32 | //`define TX_QUAD
33 | 
34 | // ------------------------------------------------------------
35 | // Define TX_HB_ON to enable the transmit halfband filter
36 | // [Not implemented]
37 | //`define TX_HB_ON
38 | 
39 | // ------------------------------------------------------------
40 | // IF RX_ON is not defined, there is *no* receive circuitry built
41 |   `define RX_ON
42 | 
43 | // ------------------------------------------------------------
44 | // Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
45 | // to respectively define 1, 2 or 4 receive channels.
46 | 
47 |   `define RX_SINGLE
48 | //`define RX_DUAL
49 | //`define RX_QUAD
50 | 
51 | // ------------------------------------------------------------
52 | // Define RX_HB_ON to enable the receive halfband filter
53 |   `define RX_HB_ON
54 | 
55 | // ------------------------------------------------------------
56 | // Define RX_NCO_ON to enable the receive Numerical Controlled Osc
57 |   `define RX_NCO_ON
58 | 
59 | // ------------------------------------------------------------
60 | // Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
61 |   `define RX_CIC_ON
62 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/toplevel/include/common_config_2rxhb_2tx.vh:
--------------------------------------------------------------------------------
 1 | // -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2006 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | // ------------------------------------------------------------
23 | // If TX_ON is not defined, there is *no* transmit circuitry built
24 |   `define TX_ON
25 | 
26 | // ------------------------------------------------------------
27 | // Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
28 | // to respectively enable 1, 2 or 4 transmit channels.
29 | // [Please note that only TX_SINGLE and TX_DUAL are currently valid]
30 | //  `define TX_SINGLE
31 |   `define TX_DUAL
32 | //`define TX_QUAD
33 |  
34 | // ------------------------------------------------------------
35 | // Define TX_HB_ON to enable the transmit halfband filter
36 | // [Not implemented]
37 | //`define TX_HB_ON
38 | 
39 | // ------------------------------------------------------------
40 | // IF RX_ON is not defined, there is *no* receive circuitry built
41 |   `define RX_ON
42 | 
43 | // ------------------------------------------------------------
44 | // Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
45 | // to respectively define 1, 2 or 4 receive channels.
46 | 
47 | //  `define RX_SINGLE
48 | //`define RX_DUAL
49 |   `define RX_QUAD
50 | 
51 | // ------------------------------------------------------------
52 | // Define RX_HB_ON to enable the receive halfband filter
53 |   `define RX_HB_ON
54 | 
55 | // ------------------------------------------------------------
56 | // Define RX_NCO_ON to enable the receive Numerical Controlled Osc
57 |   `define RX_NCO_ON
58 | 
59 | // ------------------------------------------------------------
60 | // Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
61 |   `define RX_CIC_ON
62 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/toplevel/usrp_inband_usb/config.vh:
--------------------------------------------------------------------------------
 1 | 	// -*- verilog -*-
 2 | //
 3 | //  USRP - Universal Software Radio Peripheral
 4 | //
 5 | //  Copyright (C) 2006,2007 Matt Ettus
 6 | //
 7 | //  This program is free software; you can redistribute it and/or modify
 8 | //  it under the terms of the GNU General Public License as published by
 9 | //  the Free Software Foundation; either version 2 of the License, or
10 | //  (at your option) any later version.
11 | //
12 | //  This program is distributed in the hope that it will be useful,
13 | //  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | //  GNU General Public License for more details.
16 | //
17 | //  You should have received a copy of the GNU General Public License
18 | //  along with this program; if not, write to the Free Software
19 | //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20 | //
21 | 
22 | // ====================================================================
23 | //            User control over what parts get included
24 | //
25 | //                  >>>> EDIT ONLY THIS SECTION <<<<
26 | //                  Uncomment only ONE configuration
27 | // ====================================================================
28 | 
29 | // ====================================================================
30 | // FIXME drive configuration selection from the command line and/or gui
31 | // ====================================================================
32 | 
33 | // Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel
34 | // XXX tomr uncomment for test of size reduction  
35 |   `include "../include/common_config_1rxhb_1tx.vh"
36 | 
37 | // Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
38 | // `include "../include/common_config_2rxhb_2tx.vh"
39 | 
40 | // Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
41 | //`include "../include/common_config_4rx_0tx.vh"
42 | 
43 | // Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels
44 | //`include "../include/common_config_2rxhb_0tx.vh"
45 | 
46 | // Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels
47 | //`include "../include/common_config_2rx_0tx.vh"
48 | 
49 | // Add other "known to fit" configurations here...
50 | 
51 | // ====================================================================
52 | //  Now include the common footer
53 | // ====================================================================
54 |   `include "../include/common_config_bottom.vh"
55 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.esf:
--------------------------------------------------------------------------------
 1 | SIMULATOR_SETTINGS
 2 | {
 3 | 	ESTIMATE_POWER_CONSUMPTION = OFF;
 4 | 	GLITCH_INTERVAL = 1NS;
 5 | 	GLITCH_DETECTION = OFF;
 6 | 	SIMULATION_COVERAGE = ON;
 7 | 	CHECK_OUTPUTS = OFF;
 8 | 	SETUP_HOLD_DETECTION = OFF;
 9 | 	POWER_ESTIMATION_START_TIME = "0 NS";
10 | 	ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
11 | 	SIMULATION_MODE = TIMING;
12 | 	START_TIME = 0NS;
13 | 	USE_COMPILER_SETTINGS = usrp_inband_usb;
14 | }
15 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qpf:
--------------------------------------------------------------------------------
 1 | # Copyright (C) 1991-2004 Altera Corporation
 2 | # Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 3 | # support information,  device programming or simulation file,  and any other
 4 | # associated  documentation or information  provided by  Altera  or a partner
 5 | # under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 6 | # to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 7 | # other  use  of such  megafunction  design,  netlist,  support  information,
 8 | # device programming or simulation file,  or any other  related documentation
 9 | # or information  is prohibited  for  any  other purpose,  including, but not
10 | # limited to  modification,  reverse engineering,  de-compiling, or use  with
11 | # any other  silicon devices,  unless such use is  explicitly  licensed under
12 | # a separate agreement with  Altera  or a megafunction partner.  Title to the
13 | # intellectual property,  including patents,  copyrights,  trademarks,  trade
14 | # secrets,  or maskworks,  embodied in any such megafunction design, netlist,
15 | # support  information,  device programming or simulation file,  or any other
16 | # related documentation or information provided by  Altera  or a megafunction
17 | # partner, remains with Altera, the megafunction partner, or their respective
18 | # licensors. No other licenses, including any licenses needed under any third
19 | # party's intellectual property, are provided herein.
20 | 
21 | 
22 | 
23 | QUARTUS_VERSION = "4.0"
24 | DATE = "17:10:11  December 20, 2004"
25 | 
26 | 
27 | # Active Revisions
28 | 
29 | PROJECT_REVISION = "usrp_inband_usb"
30 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/i2c.h:
--------------------------------------------------------------------------------
 1 | // I2C addresses
 2 | 
 3 | #define I2C_DEV_EEPROM  0x50            // 24LC02[45]:  7-bits 1010xxx
 4 | 
 5 | #define I2C_ADDR_BOOT   (I2C_DEV_EEPROM | 0x0)
 6 | #define I2C_ADDR_TX_A   (I2C_DEV_EEPROM | 0x4)
 7 | #define I2C_ADDR_RX_A   (I2C_DEV_EEPROM | 0x5)
 8 | #define I2C_ADDR_TX_B   (I2C_DEV_EEPROM | 0x6)
 9 | #define I2C_ADDR_RX_B   (I2C_DEV_EEPROM | 0x7)
10 | 
11 | 
12 | // format of FX2 BOOT EEPROM
13 | //      00: 0xC0        code for ``Read IDs from EEPROM''
14 | //      01: 0xFE        USB Vendor ID (LSB)
15 | //      02: 0xFF        USB Vendor ID (MSB)
16 | //      03: 0x02        USB Product ID (LSB)
17 | //      04: 0x00        USB Product ID (MSB)
18 | //      05: 0x01        USB Device ID (LSB)     // rev1
19 | //      06: 0x00        USB Device ID (MSB)     // 0 = unconfig'd (no firmware)
20 | //      07: 0x00        option byte
21 | 
22 | // format of daughterboard EEPROM
23 | //      00: 0xDB        code for ``I'm a daughterboard''
24 | //      01:   ..        Daughterboard ID (LSB)
25 | //      02:   ..        Daughterboard ID (MSB)
26 | //      03:   ..        io bits  7-0 direction (bit set if it's an output from m'board)
27 | //      04:   ..        io bits 15-8 direction (bit set if it's an output from m'board)
28 | //      05:   ..        ADC0 DC offset correction (LSB)
29 | //      06:   ..        ADC0 DC offset correction (MSB)
30 | //      07:   ..        ADC1 DC offset correction (LSB)
31 | //      08:   ..        ADC1 DC offset correction (MSB)
32 | //      ...
33 | //      1f:   ..        negative of the sum of bytes [0x00, 0x1e]
34 | 
35 | #define DB_EEPROM_MAGIC         0x00
36 | #define   DB_EEPROM_MAGIC_VALUE                 0xDB
37 | #define DB_EEPROM_ID_LSB                0x01
38 | #define DB_EEPROM_ID_MSB                0x02
39 | #define DB_EEPROM_OE_LSB                0x03
40 | #define DB_EEPROM_OE_MSB                0x04
41 | #define DB_EEPROM_OFFSET_0_LSB          0x05    // offset correction for ADC or DAC 0
42 | #define DB_EEPROM_OFFSET_0_MSB          0x06
43 | #define DB_EEPROM_OFFSET_1_LSB          0x07    // offset correction for ADC or DAC 1
44 | #define DB_EEPROM_OFFSET_1_MSB          0x08
45 | #define DB_EEPROM_CHKSUM                0x1f
46 | 
47 | #define DB_EEPROM_CLEN                  0x20    // length of common portion of eeprom
48 | 
49 | #define DB_EEPROM_CUSTOM_BASE           DB_EEPROM_CLEN  // first avail offset for
50 |                                                         //   daughterboard specific use
51 | 
52 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/ids.h:
--------------------------------------------------------------------------------
 1 | #define USB_VID_CYPRESS                 0x04b4
 2 | #define USB_PID_CYPRESS_FX2             0x8613
 3 | 
 4 | 
 5 | #define USB_VID_FSF                     0xfffe    // Free Software Folks
 6 | #define USB_PID_FSF_EXP_0               0x0000    // Experimental 0
 7 | #define USB_PID_FSF_EXP_1               0x0001    // Experimental 1
 8 | #define USB_PID_FSF_RAD1                0x0002    // Universal Software Radio Peripheral
 9 | #define USB_PID_FSF_RAD1_reserved       0x0003    // Universal Software Radio Peripheral
10 | #define USB_PID_FSF_SSRP                0x0004    // Simple Software Radio Peripheral
11 | #define USB_PID_FSF_SSRP_reserved       0x0005    // Simple Software Radio Peripheral
12 | #define USB_PID_FSF_HPSDR               0x0006    // High Performance Software Defined Radio (Internal Boot)
13 | #define USB_PID_FSF_HPSDR_HA            0x0007    // High Performance Software Defined Radio (Host Assisted Boot)
14 | #define USB_PID_FSF_QS1R                0x0008    // QS1R HF receiver
15 | #define USB_PID_FSF_EZDOP               0x0009    // ezdop <jcorgan@aeinet.com>
16 | #define USB_PID_FSF_BDALE_0             0x000a    // Bdale Garbee <bdale@gag.com>
17 | #define USB_PID_FSF_BDALE_1             0x000b    // Bdale Garbee <bdale@gag.com>
18 | #define USB_PID_FSF_BDALE_2             0x000c    // Bdale Garbee <bdale@gag.com>
19 | #define USB_PID_FSF_BDALE_3             0x000d    // Bdale Garbee <bdale@gag.com>
20 | #define USB_PID_FSF_BDALE_4             0x000e    // Bdale Garbee <bdale@gag.com>
21 | #define USB_PID_FSF_BDALE_5             0x000f    // Bdale Garbee <bdale@gag.com>
22 | #define USB_PID_FSF_BDALE_6             0x0010    // Bdale Garbee <bdale@gag.com>
23 | #define USB_PID_FSF_BDALE_7             0x0011    // Bdale Garbee <bdale@gag.com>
24 | #define USB_PID_FSF_BDALE_8             0x0012    // Bdale Garbee <bdale@gag.com>
25 | #define USB_PID_FSF_BDALE_9             0x0013    // Bdale Garbee <bdale@gag.com>
26 | #define USB_PID_FSF_HPSDR_HERMES        0x0014    // HPSDR Hermes
27 | #define USB_PID_FSF_THINKRF             0x0015    // Catalin Patulea <catalin.patulea@thinkrf.com>
28 | #define USB_PID_FSF_MSA                 0x0016    // Hans de Bok <hdbok@dionaea.demon.nl> Scotty's Modular Spectrum Analyzer
29 | 
30 | #define USB_PID_FSF_LBNL_UXO            0x0018    // http://recycle.lbl.gov/~ldoolitt/uxo/
31 | 
32 | 
33 | #define USB_DID_RAD1_0                  0x0000    // unconfigured rev 0 RAD1
34 | #define USB_DID_RAD1_1                  0x0001    // unconfigured rev 1 RAD1
35 | #define USB_DID_RAD1_2                  0x0002    // unconfigured rev 2 RAD1
36 | 
37 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/interfaces.h:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2014 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses; see the COPYING file in the main directory for licensing information for this specific distribution.
 5 | *
 6 | * This use of this software may be subject to additional restrictions.
 7 | * See the LEGAL file in the main directory for details.
 8 | 
 9 |     This program is distributed in the hope that it will be useful,
10 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
11 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 | 
13 | */
14 | 
15 | 
16 | /*
17 |  * We've now split the RAD1 into 3 separate interfaces.
18 |  *
19 |  * Interface 0 contains only ep0 and is used for command and status.
20 |  * Interface 1 is the Tx path and it uses ep2 OUT BULK.
21 |  * Interface 2 is the Rx path and it uses ep6 IN BULK.
22 |  */
23 | 
24 | #define RAD1_CMD_INTERFACE              0
25 | #define RAD1_CMD_ALTINTERFACE           0
26 | #define RAD1_CMD_ENDPOINT               0
27 | 
28 | #define RAD1_TX_INTERFACE               1
29 | #define RAD1_TX_ALTINTERFACE            0
30 | #define RAD1_TX_ENDPOINT                2       // streaming data from host to FPGA
31 | 
32 | #define RAD1_RX_INTERFACE               2
33 | #define RAD1_RX_ALTINTERFACE            0
34 | #define RAD1_RX_ENDPOINT                6       // streaming data from FPGA to host
35 | 
36 | 


--------------------------------------------------------------------------------
/TransceiverRAD1/pulseApproximate.m:
--------------------------------------------------------------------------------
 1 | pp = [0 0 0.015 0.18 0.7 0.96 0.7 0.18 0.015 0 0];
 2 | t = -2.5:0.5:2.5;
 3 | 
 4 | v = -0.000:-0.001:-1.999;
 5 | 
 6 | 
 7 | for ix1 = 1:length(v),
 8 | 	    disp(ix1);
 9 |  for ix2 = 1:length(v),
10 |   p = exp(v(ix1)*t.^2+v(ix2)*t.^4);
11 |   r(ix1,ix2) = norm(p./max(abs(p)) - pp./max(abs(pp)));
12 |  end;
13 | end;
14 | 
15 | 
16 | 


--------------------------------------------------------------------------------
/apps/.gdbinit:
--------------------------------------------------------------------------------
1 | file /OpenBTS/OpenBTS
2 | set logging on
3 | set print frame-arguments all
4 | set print pretty on
5 | run
6 | bt
7 | 


--------------------------------------------------------------------------------
/apps/CLI:
--------------------------------------------------------------------------------
1 | #!/bin/bash
2 | sudo /OpenBTS/OpenBTSCLI
3 | 
4 | 


--------------------------------------------------------------------------------
/apps/JSONEventsClient.cpp:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2014 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses;
 5 | * see the COPYING file in the main directory for licensing
 6 | * information for this specific distribution.
 7 | *
 8 | * This use of this software may be subject to additional restrictions.
 9 | * See the LEGAL file in the main directory for details.
10 | 
11 | 	This program is distributed in the hope that it will be useful,
12 | 	but WITHOUT ANY WARRANTY; without even the implied warranty of
13 | 	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 | */
15 | 
16 | 
17 | #include <iostream>
18 | #include <sstream>
19 | #include <cstdlib>
20 | #include <zmq.hpp>
21 | 
22 | int main(int argc, char **argv)
23 | {
24 | 	zmq::context_t context(4);
25 | 	zmq::socket_t targetPublisher(context, ZMQ_SUB);
26 | 	std::string localopenbts = "tcp://127.0.0.1:45160";
27 | 
28 | 	targetPublisher.setsockopt(ZMQ_SUBSCRIBE, "", 0);
29 | 	targetPublisher.connect(localopenbts.c_str());
30 | 	while (1) {
31 | 		try {
32 | 			zmq::message_t event;
33 | 			targetPublisher.recv(&event);
34 | 			std::cout << std::string(static_cast<char*>(event.data()), event.size()) << std::endl;
35 | 
36 | 		} catch(const zmq::error_t& e) {
37 | 			std::cout << "!! exception !!" << std::endl;
38 | 		}
39 | 	}
40 | }
41 | 


--------------------------------------------------------------------------------
/apps/OpenBTSConfig.h:
--------------------------------------------------------------------------------
 1 | /*
 2 | * Copyright 2014-2021 Range Networks, Inc.
 3 | *
 4 | * This software is distributed under multiple licenses;
 5 | * see the COPYING file in the main directory for licensing
 6 | * information for this specific distribution.
 7 | *
 8 | * This use of this software may be subject to additional restrictions.
 9 | * See the LEGAL file in the main directory for details.
10 | 
11 |     This program is distributed in the hope that it will be useful,
12 |     but WITHOUT ANY WARRANTY; without even the implied warranty of
13 |     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 | 
15 | */
16 | 
17 | #ifndef _CONFIGKEYS_H_
18 | #define _CONFIGKEYS_H_ 1
19 | 
20 | #include <Configuration.h>
21 | 
22 | // pat 3-2014: Added a better way to get these config values.
23 | class OpenBTSConfig : public ConfigurationTable {
24 | 	public:
25 | 	OpenBTSConfig(const char* filename, const char *wCmdName, ConfigurationKeyMap wSchema) :
26 | 		ConfigurationTable(filename, wCmdName, wSchema)
27 | 		{}
28 |     	OpenBTSConfig(void) {}; // used by CLI
29 | 
30 | 	void configUpdateKeys();
31 | 
32 | 	// This structure mirrors the config variable names in GetConfigurationKeys.cpp.
33 | 	// Any value added here must also be added to configUpdateKeys(), which function is
34 | 	// called after any change to the config to update the values in this structure.
35 | 	struct GSM {
36 | 		struct Handover {
37 | 			int FailureHoldoff;
38 | 			int Margin;
39 | 			int Ny1;
40 | 
41 | 			struct History { int Max; } History;
42 | 			struct Noise { int Factor; } Noise;
43 | 
44 | 			struct RXLEV_DL { float Target; int History, Margin, PenaltyTime; } RXLEV_DL;
45 | 		} Handover;
46 | 		struct {
47 | 			struct Power { int Min, Max, Damping; } Power;
48 | 			struct TA { int Damping, Max; } TA;
49 | 		} MS;
50 | 		struct {
51 | 			int T3103, T3105, T3109, T3113, T3212;
52 | 		} Timer;
53 | 		struct {
54 | 			int RADIO_LINK_TIMEOUT;
55 | 		} BTS;
56 | 	} GSM;
57 | };
58 | 
59 | extern OpenBTSConfig gConfig;
60 | #endif
61 | 


--------------------------------------------------------------------------------
/apps/OpenBTSDo:
--------------------------------------------------------------------------------
1 | #!/bin/bash
2 | 
3 | exec /OpenBTS/OpenBTSCLI -p 49300 -t 127.0.0.1 -d $*
4 | 
5 | 


--------------------------------------------------------------------------------
/apps/exportConfigTable.sh:
--------------------------------------------------------------------------------
1 | #!/bin/sh
2 | 
3 | sqlite3 /etc/OpenBTS/OpenBTS.db ".dump CONFIG" > OpenBTS.export.sql
4 | 


--------------------------------------------------------------------------------
/apps/generateConfigTable.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/sh
 2 | 
 3 | CONFIG_DIR=/etc/OpenBTS
 4 | 
 5 | # Create the dir if it dos not exist
 6 | if [ ! -d "$CONFIG_DIR" ]; then
 7 |         mkdir $CONFIG_DIR
 8 | fi
 9 | 
10 | # Create the dir if it dos not exist
11 | if [ ! -d "$CONFIG_DIR/saved" ]; then
12 |         mkdir $CONFIG_DIR/saved
13 | fi
14 | 
15 | # backup any exsisting DB before we create the default
16 | if [ -e $CONFIG_DIR/OpenBTS.db ]; then
17 | 	mv -f $CONFIG_DIR/OpenBTS.db $CONFIG_DIR/saved/OpenBTS.db
18 | fi
19 | 
20 | sqlite3 $CONFIG_DIR/OpenBTS.db ".read $1"
21 | 


--------------------------------------------------------------------------------
/apps/generateTeX.sh:
--------------------------------------------------------------------------------
1 | #!/bin/sh
2 | 
3 | sqlite3 -separator "" $1 "select '\item ',KEYSTRING,' -- ',COMMENTS from CONFIG order by KEYSTRING;"
4 | 


--------------------------------------------------------------------------------
/apps/importConfigTable.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/sh
 2 | 
 3 | CONFIG_DIR=/etc/OpenBTS
 4 | 
 5 | # Create the config dir if it dos not exist
 6 | if [ ! -d "$CONFIG_DIR" ]; then
 7 |         mkdir $CONFIG_DIR
 8 | fi
 9 | 
10 | # Create the config/saved dir if it dos not exist
11 | if [ ! -d "$CONFIG_DIR/saved" ]; then
12 |         mkdir $CONFIG_DIR/saved
13 | fi
14 | 
15 | # backup any exsisting DB before we create the default
16 | if [ -e $CONFIG_DIR/OpenBTS.db ]; then
17 | 	mv -f $CONFIG_DIR/OpenBTS.db $CONFIG_DIR/saved/OpenBTS.db
18 | fi
19 | sqlite3 $CONFIG_DIR/OpenBTS.db ".read OpenBTS.export.sql"
20 | 


--------------------------------------------------------------------------------
/apps/iptables.rules:
--------------------------------------------------------------------------------
 1 | # Generated by iptables-save v1.4.4
 2 | *nat
 3 | :PREROUTING ACCEPT [0:0]
 4 | :POSTROUTING ACCEPT [0:0]
 5 | :OUTPUT ACCEPT [0:0]
 6 | -A POSTROUTING -o eth0 -j MASQUERADE 
 7 | COMMIT
 8 | # Generated by iptables-save v1.4.4
 9 | *filter
10 | :INPUT ACCEPT [0:0]
11 | :FORWARD ACCEPT [0:0]
12 | :OUTPUT ACCEPT [0:0]
13 | COMMIT
14 | 


--------------------------------------------------------------------------------
/apps/logrotated.OpenBTS:
--------------------------------------------------------------------------------
1 | /var/log/OpenBTS.log {
2 | 	size 20M
3 | 	rotate 10
4 | 	compress
5 | 	notifempty
6 | }
7 | 


--------------------------------------------------------------------------------
/apps/openbts.conf:
--------------------------------------------------------------------------------
 1 | # openbts - Range Networks RAN for GSM and GPRS
 2 | #
 3 | # This service runs openbts from the point the system is
 4 | # started until it is shut down again.
 5 | 
 6 | start on stopped rc RUNLEVEL=[2345]
 7 | stop on runlevel [!2345]
 8 | 
 9 | respawn
10 | script
11 | 	cd /OpenBTS
12 | # Uncomment this line and comment out the default ./OpenBTS line to enable automatic gdb backtraces to /OpenBTS/gdb.txt (via .gdbinit)
13 | #	exec gdb
14 | 	exec ./OpenBTS
15 | end script
16 | 
17 | pre-start script
18 | 	# Since Ubuntu clears /var/run on reboot, create this before we try to start
19 | 	if [ ! -e /var/run/OpenBTS ]; then
20 | 		mkdir /var/run/OpenBTS
21 | 	fi
22 | 
23 | 	if [ ! -e /var/run/rrlp ]; then
24 | 		mkdir /var/run/rrlp
25 | 		chmod 777 /var/run/rrlp
26 | 	fi
27 | 
28 | 	# place for CRD data
29 | 	if [ ! -e /var/lib/OpenBTS ]; then
30 | 		mkdir /var/lib/OpenBTS
31 | 	fi
32 | 
33 | # make sure permissions are set up correctly
34 | if [ -d /var/lib/asterisk/sqlite3dir ]; then
35 | 	chown -R asterisk:www-data /var/lib/asterisk/sqlite3dir
36 | 	chmod 775 /var/lib/asterisk/sqlite3dir
37 | 	chmod 664 /var/lib/asterisk/sqlite3dir/sqlite3*
38 | fi
39 | end script
40 | 
41 | post-stop script
42 | 	if pgrep transceiver; then killall transceiver; fi
43 | end script
44 | 


--------------------------------------------------------------------------------
/apps/openbtsconfig:
--------------------------------------------------------------------------------
1 | #!/bin/bash
2 | if [ $# -eq '1' ]
3 | then
4 | 	sqlite3 /etc/OpenBTS/OpenBTS.db "select KEYSTRING,VALUESTRING from CONFIG where KEYSTRING like '%$1%'";
5 | else
6 | 	sqlite3 /etc/OpenBTS/OpenBTS.db "insert or replace into CONFIG (VALUESTRING,KEYSTRING) values ('$2','$1')";
7 | fi
8 | 


--------------------------------------------------------------------------------
/apps/rsyslogd.OpenBTS.conf:
--------------------------------------------------------------------------------
 1 | # OpenBTS logging controls
 2 | 
 3 | # (pat) These options increase the rate-limit on number of messages per second.
 4 | # See http://www.rsyslog.com/changing-the-settings/
 5 | $SystemLogRateLimitInterval 2
 6 | $SystemLogRateLimitBurst 100000
 7 | 
 8 | local7.*			/var/log/OpenBTS.log
 9 | 
10 | 


--------------------------------------------------------------------------------
/config/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | # Install m4 macros in this directory
25 | m4datadir = $(datadir)/aclocal
26 | 
27 | # List your m4 macros here
28 | m4macros = \
29 | 	pkg.m4
30 | 
31 | EXTRA_DIST = $(m4macros) 
32 | 


--------------------------------------------------------------------------------
/config/test_ortp_version.cpp:
--------------------------------------------------------------------------------
1 | #include <ortp/ortp.h>
2 | 
3 | int main(int argc, char **argv)
4 | {
5 | 	RtpSession * mSession;
6 | 	mSession = rtp_session_new(RTP_SESSION_SENDRECV);
7 | 	rtp_session_set_local_addr(mSession, "0.0.0.0", -1, -1);
8 | }
9 | 


--------------------------------------------------------------------------------
/ctags.sh:
--------------------------------------------------------------------------------
 1 | #DIRS="AsteriskConfig tools"
 2 | DIRS="CLI CommonLibs Control GPRS GSM GSMShare Globals Peering
 3 | 	SGSNGGSN SIP SMS SR TRXManager TransceiverRAD1 apps
 4 | # sqlite3 doc pat
 5 | 
 6 | files=""
 7 | for dir in $DIRS;do
 8 |     files="$files $dir/*.h $dir/*.c*"
 9 | done
10 | 
11 | eval echo $files
12 | # Ignore PACKED keyword
13 | eval ctags -I PACKED --extra=+fq $files
14 | 
15 | 


--------------------------------------------------------------------------------
/debian/changelog:
--------------------------------------------------------------------------------
1 | openbts (5.0) unstable; urgency=low
2 | 
3 |     * Test
4 | 
5 |  -- Range Packager <buildmanager@rangenetworks.com>  Mon, 15 Sep 2014 17:42:42 -0700
6 | 


--------------------------------------------------------------------------------
/debian/compat:
--------------------------------------------------------------------------------
1 | 7
2 | 


--------------------------------------------------------------------------------
/debian/control:
--------------------------------------------------------------------------------
 1 | Source: openbts
 2 | Section: comm
 3 | Priority: optional
 4 | Maintainer: Range Networks, Inc. <info@rangenetworks.com>
 5 | Homepage: http://www.rangenetworks.com/
 6 | Build-Depends: build-essential, debhelper (>= 7), pkg-config, autoconf, libtool, libortp-dev, libortp8 | libortp9, libsqlite3-dev, libusb-1.0-0-dev, libreadline-dev, libzmq3-dev, libzmq3 | libzmq5, liba53
 7 | Standards-Version: 3.7.3
 8 | 
 9 | Package: openbts
10 | Section: comm
11 | Priority: optional
12 | Architecture: any
13 | Essential: no
14 | Depends: sqlite3, libusb-1.0-0, libortp-dev, libc6, pkg-config, libzmq3 | libzmq5, liba53, libreadline6
15 | Description: Range Networks - OpenBTS GSM+GPRS Radio Access Network Node
16 | 


--------------------------------------------------------------------------------
/debian/postinst:
--------------------------------------------------------------------------------
 1 | #!/bin/sh
 2 | # postinst script for test
 3 | #
 4 | # see: dh_installdeb(1)
 5 | 
 6 | # TODO: For now disable "set -e" since I have not figured out how to get sqlite3 to SHUT UP!
 7 | #set -e
 8 | 
 9 | # summary of how this script can be called:
10 | #        * <postinst> `configure' <most-recently-configured-version>
11 | #        * <old-postinst> `abort-upgrade' <new version>
12 | #        * <conflictor's-postinst> `abort-remove' `in-favour' <package>
13 | #          <new-version>
14 | #        * <postinst> `abort-remove'
15 | #        * <deconfigured's-postinst> `abort-deconfigure' `in-favour'
16 | #          <failed-install-package> <version> `removing'
17 | #          <conflicting-package> <version>
18 | # for details, see http://www.debian.org/doc/debian-policy/ or
19 | # the debian-policy package
20 | 
21 | configure()
22 | {
23 | DATE=$(date --rfc-3339='date')
24 | CONFIG_BACKUP=/etc/OpenBTS/OpenBTS.dump-$DATE
25 | 
26 | # add user openbts
27 | if ! getent passwd openbts > /dev/null ; then
28 | 	echo 'Adding system user for OpenBTS' 1>&2
29 | 	adduser --system --group --quiet \
30 | 		--home /home/openbts \
31 | 		--no-create-home --disabled-login \
32 | 		--gecos "OpenBTS daemon" \
33 | 		openbts
34 | fi
35 | 
36 | # add user openbts to some groups
37 | for group in sudo asterisk www-data; do
38 | 	if groups openbts | grep -w -q -v $group; then
39 | 		adduser openbts $group
40 | 	fi
41 | done
42 | 
43 | if [ ! -e $CONFIG_BACKUP ]; then
44 |         sqlite3 /etc/OpenBTS/OpenBTS.db ".dump" > $CONFIG_BACKUP
45 | fi
46 | 
47 | sqlite3 /etc/OpenBTS/OpenBTS.db ".read /etc/OpenBTS/OpenBTS.example.sql" > /dev/null 2>&1
48 | 
49 | chown openbts:openbts /home/openbts/openbtsconfig
50 | 
51 | }
52 | 
53 | case "$1" in
54 |     configure)
55 | 	configure
56 |     ;;
57 | 
58 |     abort-upgrade|abort-remove|abort-deconfigure)
59 |     ;;
60 | 
61 |     *)
62 |         echo "postinst called with unknown argument \`$1'" >&2
63 |         exit 1
64 |     ;;
65 | esac
66 | 
67 | # dh_installdeb will replace this with shell code automatically
68 | # generated by other debhelper scripts.
69 | 
70 | #DEBHELPER#
71 | 
72 | exit 0
73 | 


--------------------------------------------------------------------------------
/debian/postrm:
--------------------------------------------------------------------------------
 1 | #!/bin/sh
 2 | # postrm script for test
 3 | #
 4 | # see: dh_installdeb(1)
 5 | 
 6 | set -e
 7 | 
 8 | # summary of how this script can be called:
 9 | #        * <postrm> `remove'
10 | #        * <postrm> `purge'
11 | #        * <old-postrm> `upgrade' <new-version>
12 | #        * <new-postrm> `failed-upgrade' <old-version>
13 | #        * <new-postrm> `abort-install'
14 | #        * <new-postrm> `abort-install' <old-version>
15 | #        * <new-postrm> `abort-upgrade' <old-version>
16 | #        * <disappearer's-postrm> `disappear' <overwriter>
17 | #          <overwriter-version>
18 | # for details, see http://www.debian.org/doc/debian-policy/ or
19 | # the debian-policy package
20 | 
21 | 
22 | case "$1" in
23 |     purge|remove|upgrade|failed-upgrade|abort-install|abort-upgrade|disappear)
24 |     ;;
25 | 
26 |     *)
27 |         echo "postrm called with unknown argument \`$1'" >&2
28 |         exit 1
29 |     ;;
30 | esac
31 | 
32 | # dh_installdeb will replace this with shell code automatically
33 | # generated by other debhelper scripts.
34 | 
35 | #DEBHELPER#
36 | 
37 | exit 0
38 | 


--------------------------------------------------------------------------------
/debian/preinst:
--------------------------------------------------------------------------------
 1 | #!/bin/sh
 2 | # preinst script for test
 3 | #
 4 | # see: dh_installdeb(1)
 5 | 
 6 | set -e
 7 | 
 8 | # summary of how this script can be called:
 9 | #        * <new-preinst> `install'
10 | #        * <new-preinst> `install' <old-version>
11 | #        * <new-preinst> `upgrade' <old-version>
12 | #        * <old-preinst> `abort-upgrade' <new-version>
13 | # for details, see http://www.debian.org/doc/debian-policy/ or
14 | # the debian-policy package
15 | 
16 | install()
17 | {
18 | INSTALL_DIR=/OpenBTS
19 | DATE=$(date --rfc-3339='date')
20 | BACKUP_DIR=$INSTALL_DIR/backup_$DATE
21 | 
22 | if [ -f $INSTALL_DIR/OpenBTS -a -f $INSTALL_DIR/transceiver ]; then
23 |     if [ ! -e $BACKUP_DIR ]; then
24 |         mkdir -p $BACKUP_DIR/
25 | 
26 |         mv $INSTALL_DIR/OpenBTS $BACKUP_DIR/
27 |         mv $INSTALL_DIR/transceiver $BACKUP_DIR/
28 |     fi
29 | fi
30 | 
31 | }
32 | 
33 | case "$1" in
34 |     install|upgrade)
35 |         install
36 |     ;;
37 | 
38 |     abort-upgrade)
39 |     ;;
40 | 
41 |     *)
42 |         echo "preinst called with unknown argument \`$1'" >&2
43 |         exit 1
44 |     ;;
45 | esac
46 | 
47 | # dh_installdeb will replace this with shell code automatically
48 | # generated by other debhelper scripts.
49 | 
50 | #DEBHELPER#
51 | 
52 | exit 0
53 | 


--------------------------------------------------------------------------------
/debian/prerm:
--------------------------------------------------------------------------------
 1 | #!/bin/sh
 2 | # prerm script for test
 3 | #
 4 | # see: dh_installdeb(1)
 5 | 
 6 | set -e
 7 | 
 8 | # summary of how this script can be called:
 9 | #        * <prerm> `remove'
10 | #        * <old-prerm> `upgrade' <new-version>
11 | #        * <new-prerm> `failed-upgrade' <old-version>
12 | #        * <conflictor's-prerm> `remove' `in-favour' <package> <new-version>
13 | #        * <deconfigured's-prerm> `deconfigure' `in-favour'
14 | #          <package-being-installed> <version> `removing'
15 | #          <conflicting-package> <version>
16 | # for details, see http://www.debian.org/doc/debian-policy/ or
17 | # the debian-policy package
18 | 
19 | # remove()
20 | # {
21 | #     killall runloop.OpenBTS.sh &>/dev/null
22 | # }
23 | 
24 | case "$1" in
25 |     remove|upgrade|deconfigure)
26 | #        remove
27 |     ;;
28 | 
29 |     failed-upgrade)
30 |     ;;
31 | 
32 |     *)
33 |         echo "prerm called with unknown argument \`$1'" >&2
34 |         exit 1
35 |     ;;
36 | esac
37 | 
38 | # dh_installdeb will replace this with shell code automatically
39 | # generated by other debhelper scripts.
40 | 
41 | #DEBHELPER#
42 | 
43 | exit 0
44 | 


--------------------------------------------------------------------------------
/doc/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | # Copyright 2014 Range Networks, Inc.
 4 | #
 5 | # This software is distributed under the terms of the GNU Public License.
 6 | # See the COPYING file in the main directory for details.
 7 | #
 8 | # This program is free software: you can redistribute it and/or modify
 9 | # it under the terms of the GNU General Public License as published by
10 | # the Free Software Foundation, either version 3 of the License, or
11 | # (at your option) any later version.
12 | #
13 | # This program is distributed in the hope that it will be useful,
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 | # GNU General Public License for more details.
17 | #
18 | # You should have received a copy of the GNU General Public License
19 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 | #
21 | 
22 | include $(top_srcdir)/Makefile.common
23 | 
24 | EXTRA_DIST = \
25 | 	CodingStandard
26 | 
27 | 


--------------------------------------------------------------------------------
/package/deb-after-install.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/bash
 2 | 
 3 | # copy of debian/postinst
 4 | DATE=$(date --rfc-3339='date')
 5 | CONFIG_BACKUP=/etc/OpenBTS/OpenBTS.dump-$DATE
 6 | 
 7 | # add user openbts
 8 | if ! getent passwd openbts > /dev/null ; then
 9 |         echo 'Adding system user for OpenBTS' 1>&2
10 |         adduser --system --group --quiet \
11 |                 --home /home/openbts \
12 |                 --gecos "OpenBTS daemon" \
13 |                 openbts
14 | fi
15 | 
16 | # add user openbts to some groups
17 | for group in sudo www-data; do
18 |         if groups openbts | grep -w -q -v $group; then
19 |                 adduser openbts $group 
20 |         fi
21 | done
22 | 
23 | if [ ! -e $CONFIG_BACKUP ]; then
24 |         sqlite3 /etc/OpenBTS/OpenBTS.db ".dump" > $CONFIG_BACKUP
25 | fi
26 | 
27 | sqlite3 /etc/OpenBTS/OpenBTS.db ".read /etc/OpenBTS/OpenBTS.example.sql" > /dev/null 2>&1
28 | 
29 | chown openbts:openbts /home/openbts/openbtsconfig
30 | 
31 | 


--------------------------------------------------------------------------------
/package/deb-before-install.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/bash
 2 | 
 3 | # copy of debian/preinst
 4 | INSTALL_DIR=/OpenBTS
 5 | DATE=$(date --rfc-3339='date')
 6 | BACKUP_DIR=$INSTALL_DIR/backup_$DATE
 7 | 
 8 | if [ -f $INSTALL_DIR/OpenBTS -a -f $INSTALL_DIR/transceiver ]; then
 9 |     if [ ! -e $BACKUP_DIR ]; then
10 |         mkdir -p $BACKUP_DIR/
11 | 
12 |         mv $INSTALL_DIR/OpenBTS $BACKUP_DIR/
13 |         mv $INSTALL_DIR/transceiver $BACKUP_DIR/
14 |     fi
15 | fi
16 | 


--------------------------------------------------------------------------------
/package/rpm-after-install.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/bash
 2 | 
 3 | # copy of debian/postinst
 4 | DATE=$(date --rfc-3339='date')
 5 | CONFIG_BACKUP=/etc/OpenBTS/OpenBTS.dump-$DATE
 6 | 
 7 | # add user openbts
 8 | if ! getent passwd openbts > /dev/null ; then
 9 |         echo 'Adding system user for OpenBTS' 1>&2
10 |         adduser --system --group \
11 |                 --home /home/openbts \
12 | 				--user-group \
13 |                 --comment "OpenBTS daemon" \
14 |                 openbts
15 | fi
16 | 
17 | # add user openbts to some groups
18 | for group in sudo httpd; do
19 |         if egrep -i "^$group" /etc/group; then
20 |                 adduser -G $group openbts
21 |         fi
22 | done
23 | 
24 | if [ ! -e $CONFIG_BACKUP ]; then
25 |         sqlite3 /etc/OpenBTS/OpenBTS.db ".dump" > $CONFIG_BACKUP
26 | fi
27 | 
28 | sqlite3 /etc/OpenBTS/OpenBTS.db ".read /etc/OpenBTS/OpenBTS.example.sql" > /dev/null 2>&1
29 | 
30 | chown openbts:openbts /home/openbts/openbtsconfig
31 | 
32 | 


--------------------------------------------------------------------------------
/package/rpm-before-install.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/bash
 2 | 
 3 | # copy of debian/preinst
 4 | INSTALL_DIR=/OpenBTS
 5 | DATE=$(date --rfc-3339='date')
 6 | BACKUP_DIR=$INSTALL_DIR/backup_$DATE
 7 | 
 8 | if [ -f $INSTALL_DIR/OpenBTS -a -f $INSTALL_DIR/transceiver ]; then
 9 |     if [ ! -e $BACKUP_DIR ]; then
10 |         mkdir -p $BACKUP_DIR/
11 | 
12 |         mv $INSTALL_DIR/OpenBTS $BACKUP_DIR/
13 |         mv $INSTALL_DIR/transceiver $BACKUP_DIR/
14 |     fi
15 | fi
16 | 


--------------------------------------------------------------------------------
/tools/Makefile.am:
--------------------------------------------------------------------------------
 1 | #
 2 | # Copyright 2008 Free Software Foundation, Inc.
 3 | #
 4 | # This software is distributed under the terms of the GNU Public License.
 5 | # See the COPYING file in the main directory for details.
 6 | #
 7 | # This program is free software: you can redistribute it and/or modify
 8 | # it under the terms of the GNU General Public License as published by
 9 | # the Free Software Foundation, either version 3 of the License, or
10 | # (at your option) any later version.
11 | #
12 | # This program is distributed in the hope that it will be useful,
13 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
14 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 | # GNU General Public License for more details.
16 | #
17 | # You should have received a copy of the GNU General Public License
18 | # along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 | #
20 | 
21 | include $(top_srcdir)/Makefile.common
22 | 
23 | EXTRA_DIST = \
24 | 	Makefile.standalone \
25 | 	README \
26 | 	hata.cpp \
27 | 	translateConfig.py
28 | 
29 | 


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/tools/Makefile.standalone:
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1 | 
2 | hata: hata.cpp
3 | 	g++ -o hata hata.cpp
4 | 
5 | 


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/tools/README:
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1 | Network planning tools.
2 | Not part of the normal build process.
3 | 


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/tools/translateConfig.py:
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 1 | #!/usr/bin/python
 2 | 
 3 | 
 4 | import sys
 5 | 
 6 | 
 7 | if len(sys.argv)<2:
 8 | 	print sys.argv[0]," configFile"
 9 | 	sys.exit()
10 | 
11 | filename = sys.argv[1]
12 | 
13 | 
14 | # This needs to match what is in Configuration.cpp.
15 | header = " \
16 | CREATE TABLE IF NOT EXISTS CONFIG ( \
17 | KEYSTRING TEXT UNIQUE NOT NULL, \
18 | VALUESTRING TEXT, \
19 | STATIC INTEGER DEFAULT 0, \
20 | OPTIONAL INTEGER DEFAULT 0, \
21 | COMMENTS TEXT DEFAULT '' \
22 | );"
23 | 
24 | 
25 | inFile = open(filename,"r")
26 | 
27 | knownKeys = []
28 | 
29 | 
30 | def processDirective(dirLine):
31 | 	(directive,key) = dirLine.split(' ')
32 | 	if directive=="static":
33 | 		if key not in knownKeys:
34 | 			print "non-existant key",key,"cannot be static"
35 | 			sys.exit()
36 | 		print "UPDATE CONFIG SET STATIC=1 WHERE KEYSTRING==\""+key+"\";"
37 | 		return
38 | 	if directive=="optional":
39 | 		if key not in knownKeys:
40 | 			print "INSERT INTO CONFIG (KEYSTRING,OPTIONAL) VALUES (\""+key+"\",1);"
41 | 			return
42 | 		print "UPDATE CONFIG SET OPTIONAL=1 WHERE KEYSTRING==\""+key+"\";"
43 | 		return
44 | 	print "unknown directive",directive
45 | 	sys.exit()
46 | 
47 | 
48 | print header
49 | 
50 | for line in inFile:
51 | 	line = line[:-1].lstrip()
52 | 	if len(line)==0:
53 | 		continue
54 | 	# process comments
55 | 	if line[0]=='#':
56 | 		print "--", line
57 | 		continue
58 | 	# process directive
59 | 	if line[0]=='$':
60 | 		processDirective(line[1:])
61 | 		continue
62 | 	# key-value pairs
63 | 	keyval = line.split(' ',1)
64 | 	key = keyval[0]
65 | 	if key in knownKeys:
66 | 		print "key",key,"not unique"
67 | 		sys.exit()
68 | 	if len(keyval)==1:
69 | 		print "INSERT INTO CONFIG (KEYSTRING) VALUES (\""+key+"\");"
70 | 	else:
71 | 		value = keyval[1]
72 | 		print "INSERT INTO CONFIG (KEYSTRING,VALUESTRING) VALUES (\""+key+"\",\""+value+"\");"
73 | 	knownKeys.append(key)
74 | inFile.close()
75 | 
76 | 
77 | 
78 | 
79 | 
80 | 


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